Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 578
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T79 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4069856462 May 19 01:06:55 PM PDT 24 May 19 01:06:57 PM PDT 24 30643796 ps
T511 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1295993941 May 19 01:06:34 PM PDT 24 May 19 01:06:36 PM PDT 24 29225203 ps
T512 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.113606114 May 19 01:06:49 PM PDT 24 May 19 01:06:50 PM PDT 24 111170002 ps
T513 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2542524582 May 19 01:06:56 PM PDT 24 May 19 01:07:00 PM PDT 24 53838059 ps
T514 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1409866277 May 19 01:06:50 PM PDT 24 May 19 01:06:51 PM PDT 24 39665860 ps
T515 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3323677679 May 19 01:06:54 PM PDT 24 May 19 01:06:55 PM PDT 24 13822893 ps
T516 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.186279936 May 19 01:06:34 PM PDT 24 May 19 01:06:36 PM PDT 24 15985365 ps
T517 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.975379769 May 19 01:06:39 PM PDT 24 May 19 01:06:44 PM PDT 24 1283222879 ps
T518 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2956566670 May 19 01:06:50 PM PDT 24 May 19 01:06:52 PM PDT 24 56508755 ps
T519 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1775041148 May 19 01:06:56 PM PDT 24 May 19 01:06:58 PM PDT 24 59573225 ps
T520 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2302803244 May 19 01:06:37 PM PDT 24 May 19 01:06:39 PM PDT 24 19122848 ps
T521 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1191368791 May 19 01:07:01 PM PDT 24 May 19 01:07:03 PM PDT 24 362396760 ps
T522 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2042584326 May 19 01:07:06 PM PDT 24 May 19 01:07:07 PM PDT 24 24232663 ps
T523 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4257585612 May 19 01:06:45 PM PDT 24 May 19 01:06:47 PM PDT 24 196700407 ps
T524 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.712901197 May 19 01:06:39 PM PDT 24 May 19 01:06:40 PM PDT 24 81305379 ps
T525 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.71643177 May 19 01:06:39 PM PDT 24 May 19 01:06:41 PM PDT 24 31607793 ps
T80 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2996693297 May 19 01:06:52 PM PDT 24 May 19 01:06:53 PM PDT 24 14040461 ps
T526 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2297733671 May 19 01:06:35 PM PDT 24 May 19 01:06:37 PM PDT 24 122242121 ps
T527 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2893586792 May 19 01:06:34 PM PDT 24 May 19 01:06:37 PM PDT 24 16980305 ps
T81 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2068604093 May 19 01:06:36 PM PDT 24 May 19 01:06:38 PM PDT 24 50485402 ps
T528 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2101926599 May 19 01:07:00 PM PDT 24 May 19 01:07:02 PM PDT 24 39724155 ps
T529 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3371355323 May 19 01:06:52 PM PDT 24 May 19 01:06:55 PM PDT 24 116705674 ps
T530 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1471799487 May 19 01:06:59 PM PDT 24 May 19 01:07:00 PM PDT 24 25062286 ps
T531 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3199376669 May 19 01:06:39 PM PDT 24 May 19 01:06:41 PM PDT 24 47270986 ps
T532 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.89628197 May 19 01:06:41 PM PDT 24 May 19 01:06:44 PM PDT 24 473358250 ps
T82 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2746428216 May 19 01:06:32 PM PDT 24 May 19 01:06:34 PM PDT 24 37595162 ps
T533 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2403344383 May 19 01:06:52 PM PDT 24 May 19 01:06:56 PM PDT 24 162340993 ps
T534 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1464863825 May 19 01:06:40 PM PDT 24 May 19 01:06:42 PM PDT 24 440320325 ps
T535 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.314189365 May 19 01:06:33 PM PDT 24 May 19 01:06:34 PM PDT 24 125219830 ps
T83 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.985093677 May 19 01:06:53 PM PDT 24 May 19 01:06:54 PM PDT 24 23612563 ps
T536 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2478730861 May 19 01:06:55 PM PDT 24 May 19 01:06:57 PM PDT 24 66417502 ps
T537 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3181965562 May 19 01:06:49 PM PDT 24 May 19 01:06:51 PM PDT 24 534233306 ps
T538 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2944396888 May 19 01:06:39 PM PDT 24 May 19 01:06:41 PM PDT 24 28830615 ps
T539 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1866582339 May 19 01:06:51 PM PDT 24 May 19 01:06:53 PM PDT 24 46822198 ps
T540 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.666581043 May 19 01:07:00 PM PDT 24 May 19 01:07:02 PM PDT 24 28260668 ps
T541 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2084071608 May 19 01:06:55 PM PDT 24 May 19 01:06:57 PM PDT 24 47458612 ps
T542 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3504876193 May 19 01:07:00 PM PDT 24 May 19 01:07:02 PM PDT 24 39888395 ps
T543 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1090614885 May 19 01:06:50 PM PDT 24 May 19 01:06:52 PM PDT 24 51106915 ps
T544 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1045637684 May 19 01:06:45 PM PDT 24 May 19 01:06:47 PM PDT 24 36018898 ps
T545 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1409716653 May 19 01:06:56 PM PDT 24 May 19 01:06:58 PM PDT 24 127920040 ps
T546 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3203773789 May 19 01:06:54 PM PDT 24 May 19 01:06:56 PM PDT 24 50818149 ps
T547 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2982060349 May 19 01:06:34 PM PDT 24 May 19 01:06:36 PM PDT 24 69452945 ps
T548 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2274641756 May 19 01:07:00 PM PDT 24 May 19 01:07:02 PM PDT 24 27968794 ps
T85 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1186320537 May 19 01:06:35 PM PDT 24 May 19 01:06:37 PM PDT 24 15554817 ps
T549 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3394645362 May 19 01:06:45 PM PDT 24 May 19 01:06:48 PM PDT 24 70448463 ps
T550 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1590853689 May 19 01:06:45 PM PDT 24 May 19 01:06:47 PM PDT 24 42169203 ps
T551 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2505958461 May 19 01:06:43 PM PDT 24 May 19 01:06:45 PM PDT 24 151863850 ps
T552 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3888264995 May 19 01:06:28 PM PDT 24 May 19 01:06:30 PM PDT 24 154969093 ps
T87 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1398779361 May 19 01:06:33 PM PDT 24 May 19 01:06:36 PM PDT 24 114845075 ps
T86 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3174715068 May 19 01:06:53 PM PDT 24 May 19 01:06:55 PM PDT 24 11073493 ps
T553 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1184048558 May 19 01:06:40 PM PDT 24 May 19 01:06:42 PM PDT 24 59313977 ps
T554 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2910461455 May 19 01:07:01 PM PDT 24 May 19 01:07:02 PM PDT 24 32573655 ps
T555 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2862830316 May 19 01:07:12 PM PDT 24 May 19 01:07:15 PM PDT 24 30289840 ps
T556 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.668764351 May 19 01:06:54 PM PDT 24 May 19 01:06:56 PM PDT 24 46369343 ps
T557 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2527890856 May 19 01:06:30 PM PDT 24 May 19 01:06:34 PM PDT 24 418336460 ps
T558 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3542088055 May 19 01:06:38 PM PDT 24 May 19 01:06:40 PM PDT 24 114954170 ps
T559 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3691161039 May 19 01:06:59 PM PDT 24 May 19 01:07:00 PM PDT 24 53987666 ps
T560 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1956786871 May 19 01:06:44 PM PDT 24 May 19 01:06:46 PM PDT 24 23148472 ps
T561 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.640378553 May 19 01:06:44 PM PDT 24 May 19 01:06:46 PM PDT 24 46359107 ps
T562 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1033831177 May 19 01:06:53 PM PDT 24 May 19 01:06:55 PM PDT 24 92059027 ps
T563 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1256572438 May 19 01:06:43 PM PDT 24 May 19 01:06:45 PM PDT 24 68846952 ps
T564 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3564347910 May 19 01:07:00 PM PDT 24 May 19 01:07:02 PM PDT 24 15938760 ps
T88 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3836663601 May 19 01:06:53 PM PDT 24 May 19 01:06:54 PM PDT 24 21192753 ps
T565 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2188793457 May 19 01:06:34 PM PDT 24 May 19 01:06:37 PM PDT 24 89853516 ps
T566 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3639946093 May 19 01:06:44 PM PDT 24 May 19 01:06:46 PM PDT 24 32176874 ps
T567 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.264509971 May 19 01:06:29 PM PDT 24 May 19 01:06:31 PM PDT 24 24857235 ps
T568 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.424916691 May 19 01:07:01 PM PDT 24 May 19 01:07:03 PM PDT 24 14928078 ps
T569 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3691108893 May 19 01:06:56 PM PDT 24 May 19 01:06:58 PM PDT 24 53208493 ps
T84 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4004888299 May 19 01:06:40 PM PDT 24 May 19 01:06:42 PM PDT 24 15250883 ps
T570 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.425398952 May 19 01:07:02 PM PDT 24 May 19 01:07:03 PM PDT 24 76809434 ps
T571 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1641476288 May 19 01:07:00 PM PDT 24 May 19 01:07:01 PM PDT 24 55704563 ps
T572 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.108963681 May 19 01:06:49 PM PDT 24 May 19 01:06:50 PM PDT 24 64830719 ps
T573 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1963597641 May 19 01:06:39 PM PDT 24 May 19 01:06:42 PM PDT 24 117302700 ps
T574 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1672929940 May 19 01:06:53 PM PDT 24 May 19 01:06:56 PM PDT 24 447426063 ps
T575 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4249077461 May 19 01:06:45 PM PDT 24 May 19 01:06:47 PM PDT 24 38216977 ps
T576 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2881751774 May 19 01:06:33 PM PDT 24 May 19 01:06:36 PM PDT 24 34907357 ps
T577 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3251562376 May 19 01:06:45 PM PDT 24 May 19 01:06:49 PM PDT 24 776245320 ps
T578 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2309228620 May 19 01:06:29 PM PDT 24 May 19 01:06:31 PM PDT 24 14843154 ps

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2382109310
Short name T2
Test name
Test status
Simulation time 1899983238003 ps
CPU time 582.34 seconds
Started May 19 01:00:13 PM PDT 24
Finished May 19 01:09:56 PM PDT 24
Peak memory 182640 kb
Host smart-dfbef45a-c2eb-4a60-9c06-adeda659f365
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382109310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2382109310
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.4210437688
Short name T35
Test name
Test status
Simulation time 361495195145 ps
CPU time 479.02 seconds
Started May 19 01:00:13 PM PDT 24
Finished May 19 01:08:13 PM PDT 24
Peak memory 206780 kb
Host smart-e4c7ee36-baa1-44c9-85bd-7061a5bec070
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210437688 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.4210437688
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.588984696
Short name T23
Test name
Test status
Simulation time 890275099900 ps
CPU time 1525.15 seconds
Started May 19 12:59:21 PM PDT 24
Finished May 19 01:24:48 PM PDT 24
Peak memory 190820 kb
Host smart-970d6d42-9f2f-48ce-bfad-7a3a3518f646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588984696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
588984696
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.956328253
Short name T56
Test name
Test status
Simulation time 3065232623482 ps
CPU time 2456.21 seconds
Started May 19 12:59:35 PM PDT 24
Finished May 19 01:40:32 PM PDT 24
Peak memory 190856 kb
Host smart-ebca7a4d-a94f-4c9b-9a6b-70fbe6656d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956328253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
956328253
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.748974259
Short name T29
Test name
Test status
Simulation time 152176905 ps
CPU time 1.1 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:56 PM PDT 24
Peak memory 194888 kb
Host smart-99bdfd66-bdbe-40bb-8a01-b24bf7870fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748974259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.748974259
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.20207064
Short name T163
Test name
Test status
Simulation time 848465682073 ps
CPU time 3450.98 seconds
Started May 19 12:59:30 PM PDT 24
Finished May 19 01:57:02 PM PDT 24
Peak memory 190864 kb
Host smart-7a4d2a78-7009-4322-9501-cf236c47daa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20207064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.20207064
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3201409710
Short name T109
Test name
Test status
Simulation time 2116354748453 ps
CPU time 1424.16 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:23:20 PM PDT 24
Peak memory 190852 kb
Host smart-53cb0d4f-78bd-4075-bfae-8678f377ece3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201409710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3201409710
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2432233559
Short name T167
Test name
Test status
Simulation time 1244932657995 ps
CPU time 1874.61 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:30:50 PM PDT 24
Peak memory 190844 kb
Host smart-15c6bfae-2a44-4a5c-8887-4539ea7ba110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432233559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2432233559
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3948041850
Short name T119
Test name
Test status
Simulation time 1662015282589 ps
CPU time 3610.9 seconds
Started May 19 01:00:02 PM PDT 24
Finished May 19 02:00:14 PM PDT 24
Peak memory 195148 kb
Host smart-121d2d49-b427-4f46-b571-49f367dc883d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948041850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3948041850
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2755716758
Short name T209
Test name
Test status
Simulation time 808277108698 ps
CPU time 3555.23 seconds
Started May 19 12:59:42 PM PDT 24
Finished May 19 01:58:58 PM PDT 24
Peak memory 190772 kb
Host smart-98891218-9533-4eae-b776-7220635e1822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755716758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2755716758
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.4185701963
Short name T7
Test name
Test status
Simulation time 1003200701539 ps
CPU time 436.83 seconds
Started May 19 01:01:48 PM PDT 24
Finished May 19 01:09:06 PM PDT 24
Peak memory 193428 kb
Host smart-6c9a3b73-8402-4ea4-89f1-c6fd1275e7e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185701963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4185701963
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3518866292
Short name T172
Test name
Test status
Simulation time 694137799168 ps
CPU time 1981.52 seconds
Started May 19 01:00:23 PM PDT 24
Finished May 19 01:33:25 PM PDT 24
Peak memory 195936 kb
Host smart-c4f165c7-8f7c-4fa4-a2ba-6e246920b229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518866292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3518866292
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1469080611
Short name T219
Test name
Test status
Simulation time 2512639971994 ps
CPU time 1554.14 seconds
Started May 19 12:59:16 PM PDT 24
Finished May 19 01:25:12 PM PDT 24
Peak memory 190832 kb
Host smart-00275df8-53cd-4f99-878c-8b24eba36665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469080611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1469080611
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3074102180
Short name T171
Test name
Test status
Simulation time 1829357710454 ps
CPU time 1415.43 seconds
Started May 19 12:59:53 PM PDT 24
Finished May 19 01:23:29 PM PDT 24
Peak memory 190776 kb
Host smart-7cd8f17f-54e2-4d09-9710-118b9ad9ec5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074102180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3074102180
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.786654142
Short name T18
Test name
Test status
Simulation time 36617614 ps
CPU time 0.75 seconds
Started May 19 12:59:04 PM PDT 24
Finished May 19 12:59:06 PM PDT 24
Peak memory 213068 kb
Host smart-f2238355-da86-420a-907c-e30e21380f68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786654142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.786654142
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2333562619
Short name T325
Test name
Test status
Simulation time 665866165905 ps
CPU time 1155.92 seconds
Started May 19 12:59:47 PM PDT 24
Finished May 19 01:19:04 PM PDT 24
Peak memory 190792 kb
Host smart-ba4c5ef6-bc13-43d3-9bad-b401fa6408eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333562619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2333562619
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2068604093
Short name T81
Test name
Test status
Simulation time 50485402 ps
CPU time 0.62 seconds
Started May 19 01:06:36 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 182752 kb
Host smart-9ec751fb-a7bb-4e3d-9c82-20c7e9ead6c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068604093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2068604093
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2379883435
Short name T134
Test name
Test status
Simulation time 4344057253114 ps
CPU time 3600.55 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:59:38 PM PDT 24
Peak memory 189916 kb
Host smart-8bfa0c11-0d7f-439a-bf25-14fafdad5221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379883435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2379883435
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4002923020
Short name T146
Test name
Test status
Simulation time 576263190464 ps
CPU time 1662.02 seconds
Started May 19 01:00:15 PM PDT 24
Finished May 19 01:27:58 PM PDT 24
Peak memory 190856 kb
Host smart-a1750871-e798-4da1-8ebf-b4bf65662949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002923020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4002923020
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/116.rv_timer_random.4073536125
Short name T120
Test name
Test status
Simulation time 585671160476 ps
CPU time 638.4 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:12:03 PM PDT 24
Peak memory 190816 kb
Host smart-cd3bbcb5-8150-461a-9ce3-4af763948b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073536125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4073536125
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.939870902
Short name T309
Test name
Test status
Simulation time 648469486923 ps
CPU time 1663.75 seconds
Started May 19 12:59:52 PM PDT 24
Finished May 19 01:27:37 PM PDT 24
Peak memory 190844 kb
Host smart-ea7ac3c9-809b-465c-96bf-b628be92ad7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939870902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
939870902
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1862962849
Short name T187
Test name
Test status
Simulation time 217524275790 ps
CPU time 1561.9 seconds
Started May 19 12:59:05 PM PDT 24
Finished May 19 01:25:08 PM PDT 24
Peak memory 190776 kb
Host smart-40c33c6e-1f93-4cee-859d-8322fa16d30c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862962849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1862962849
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2164926483
Short name T113
Test name
Test status
Simulation time 1471509919594 ps
CPU time 1014.17 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 01:16:23 PM PDT 24
Peak memory 190832 kb
Host smart-3ec148c9-74d0-40c2-810c-7bb31c211dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164926483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2164926483
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3038291226
Short name T340
Test name
Test status
Simulation time 326478059291 ps
CPU time 2260.59 seconds
Started May 19 12:59:20 PM PDT 24
Finished May 19 01:37:02 PM PDT 24
Peak memory 194724 kb
Host smart-ba122dce-e62f-4e00-96b9-1958d4e7317c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038291226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3038291226
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/195.rv_timer_random.1752849238
Short name T277
Test name
Test status
Simulation time 400543893012 ps
CPU time 329.21 seconds
Started May 19 01:02:04 PM PDT 24
Finished May 19 01:07:34 PM PDT 24
Peak memory 191096 kb
Host smart-2f59e2eb-9c0a-4bc0-ac53-5a33e67d1f38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752849238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1752849238
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3117756417
Short name T266
Test name
Test status
Simulation time 107642038717 ps
CPU time 158.57 seconds
Started May 19 01:01:35 PM PDT 24
Finished May 19 01:04:15 PM PDT 24
Peak memory 190832 kb
Host smart-ea889a5f-2923-4097-8429-8828d861c4a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117756417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3117756417
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.312523177
Short name T192
Test name
Test status
Simulation time 618591393605 ps
CPU time 599.96 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:09:37 PM PDT 24
Peak memory 190808 kb
Host smart-dc43a672-9d44-4e28-9d89-bd5e2ad37bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312523177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
312523177
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/119.rv_timer_random.3463055579
Short name T100
Test name
Test status
Simulation time 470218685974 ps
CPU time 258.76 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:05:43 PM PDT 24
Peak memory 190700 kb
Host smart-6cd0a580-6782-4cf3-a9fb-cd9757c0d351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463055579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3463055579
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.984878289
Short name T257
Test name
Test status
Simulation time 48690319923 ps
CPU time 86.27 seconds
Started May 19 01:01:36 PM PDT 24
Finished May 19 01:03:04 PM PDT 24
Peak memory 190844 kb
Host smart-0e9c9af9-f712-4378-8bea-14fda945a927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984878289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.984878289
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1934411177
Short name T175
Test name
Test status
Simulation time 141991320312 ps
CPU time 732 seconds
Started May 19 01:00:56 PM PDT 24
Finished May 19 01:13:08 PM PDT 24
Peak memory 190836 kb
Host smart-7777e0aa-a622-48ef-a509-b445a702ad18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934411177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1934411177
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.3943375699
Short name T199
Test name
Test status
Simulation time 499138834229 ps
CPU time 392.39 seconds
Started May 19 01:01:18 PM PDT 24
Finished May 19 01:07:51 PM PDT 24
Peak memory 190840 kb
Host smart-1a9e699d-32bf-44e2-aa30-9a989a3bd37c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943375699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3943375699
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4022250989
Short name T161
Test name
Test status
Simulation time 130866265918 ps
CPU time 135.4 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:03:40 PM PDT 24
Peak memory 190820 kb
Host smart-718b00f7-786e-4d7f-88ab-43390871acdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022250989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4022250989
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.1299320508
Short name T147
Test name
Test status
Simulation time 302214416452 ps
CPU time 402.79 seconds
Started May 19 12:59:21 PM PDT 24
Finished May 19 01:06:05 PM PDT 24
Peak memory 190768 kb
Host smart-63fb3f2e-1c67-4599-b63e-fa754eddfe97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299320508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1299320508
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.872035030
Short name T57
Test name
Test status
Simulation time 1302808253893 ps
CPU time 1032.41 seconds
Started May 19 01:00:36 PM PDT 24
Finished May 19 01:17:49 PM PDT 24
Peak memory 195568 kb
Host smart-533eed7f-2936-49c0-8eb2-11cad7492d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872035030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
872035030
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3971773213
Short name T228
Test name
Test status
Simulation time 3435697073339 ps
CPU time 1020.78 seconds
Started May 19 01:00:40 PM PDT 24
Finished May 19 01:17:42 PM PDT 24
Peak memory 195276 kb
Host smart-f34da188-f363-4728-8839-d59d70285a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971773213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3971773213
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.3639760075
Short name T159
Test name
Test status
Simulation time 214252643467 ps
CPU time 368.57 seconds
Started May 19 01:01:14 PM PDT 24
Finished May 19 01:07:23 PM PDT 24
Peak memory 190832 kb
Host smart-8d9f6474-a21c-4186-9c56-cac42e41a815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639760075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3639760075
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.2834231394
Short name T133
Test name
Test status
Simulation time 850042926207 ps
CPU time 531.79 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:10:16 PM PDT 24
Peak memory 190824 kb
Host smart-1969f527-385d-438f-9c23-1140354a5c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834231394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2834231394
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.106093597
Short name T256
Test name
Test status
Simulation time 165137813229 ps
CPU time 2073.22 seconds
Started May 19 01:01:53 PM PDT 24
Finished May 19 01:36:26 PM PDT 24
Peak memory 190744 kb
Host smart-5e65d0d6-e0d2-4b93-af87-6aa7fb47ccf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106093597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.106093597
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2650796312
Short name T102
Test name
Test status
Simulation time 376814527744 ps
CPU time 332.56 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:05:10 PM PDT 24
Peak memory 190812 kb
Host smart-b6eda373-74c5-493e-92d4-439e67a91a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650796312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2650796312
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2364750303
Short name T41
Test name
Test status
Simulation time 972704127394 ps
CPU time 809.84 seconds
Started May 19 12:59:45 PM PDT 24
Finished May 19 01:13:15 PM PDT 24
Peak memory 190844 kb
Host smart-c0caeca0-e1f2-4eb7-b060-e05d7ceb5815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364750303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2364750303
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_random.3226569143
Short name T123
Test name
Test status
Simulation time 326088295921 ps
CPU time 767.38 seconds
Started May 19 12:59:13 PM PDT 24
Finished May 19 01:12:02 PM PDT 24
Peak memory 190808 kb
Host smart-9bd2f60f-2d4d-40d1-b8b3-a08dccd700ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226569143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3226569143
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1813849944
Short name T157
Test name
Test status
Simulation time 219435345241 ps
CPU time 191.62 seconds
Started May 19 01:00:51 PM PDT 24
Finished May 19 01:04:03 PM PDT 24
Peak memory 190796 kb
Host smart-a2f07061-82e0-4c95-9157-e66c4bf34e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813849944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1813849944
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.967835991
Short name T62
Test name
Test status
Simulation time 357112712349 ps
CPU time 536.79 seconds
Started May 19 01:01:18 PM PDT 24
Finished May 19 01:10:15 PM PDT 24
Peak memory 190760 kb
Host smart-70619d11-3d3a-4589-92aa-233d9b414af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967835991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.967835991
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3495874552
Short name T334
Test name
Test status
Simulation time 42717822316 ps
CPU time 40.39 seconds
Started May 19 12:59:03 PM PDT 24
Finished May 19 12:59:45 PM PDT 24
Peak memory 182600 kb
Host smart-46ec2023-e76f-4185-b32b-f28ac40bb4e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495874552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3495874552
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/149.rv_timer_random.1480241537
Short name T259
Test name
Test status
Simulation time 116844105141 ps
CPU time 261.05 seconds
Started May 19 01:01:41 PM PDT 24
Finished May 19 01:06:03 PM PDT 24
Peak memory 190840 kb
Host smart-22749523-ddbc-4bcb-bfbe-db8ac1657a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480241537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1480241537
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2115652018
Short name T141
Test name
Test status
Simulation time 1057278535864 ps
CPU time 463.62 seconds
Started May 19 01:01:53 PM PDT 24
Finished May 19 01:09:37 PM PDT 24
Peak memory 191104 kb
Host smart-b9fbc06f-a542-4ee7-8d8c-ec609fa664fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115652018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2115652018
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.307597593
Short name T233
Test name
Test status
Simulation time 263260099330 ps
CPU time 585.77 seconds
Started May 19 01:01:55 PM PDT 24
Finished May 19 01:11:41 PM PDT 24
Peak memory 190828 kb
Host smart-2c2610ea-35ae-419f-bc8c-bad04b1a9c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307597593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.307597593
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.876938905
Short name T155
Test name
Test status
Simulation time 184390066295 ps
CPU time 268.55 seconds
Started May 19 12:59:38 PM PDT 24
Finished May 19 01:04:07 PM PDT 24
Peak memory 190792 kb
Host smart-59ee2668-dc8c-4819-86af-8ecd34f79a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876938905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.876938905
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random.3461717497
Short name T158
Test name
Test status
Simulation time 147620559955 ps
CPU time 1750.42 seconds
Started May 19 01:00:23 PM PDT 24
Finished May 19 01:29:35 PM PDT 24
Peak memory 190768 kb
Host smart-b48e362b-e168-4ddb-a9d5-533fa5cc0fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461717497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3461717497
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.3012591145
Short name T317
Test name
Test status
Simulation time 840323788507 ps
CPU time 403.82 seconds
Started May 19 01:00:41 PM PDT 24
Finished May 19 01:07:26 PM PDT 24
Peak memory 190836 kb
Host smart-3a580384-4a8a-4db7-8bd1-2e9c329dc7f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012591145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3012591145
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3707754827
Short name T213
Test name
Test status
Simulation time 2281193971877 ps
CPU time 616.54 seconds
Started May 19 01:00:49 PM PDT 24
Finished May 19 01:11:07 PM PDT 24
Peak memory 190820 kb
Host smart-07880b09-530b-42a8-8579-9b7d46f370c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707754827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3707754827
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/89.rv_timer_random.3312772243
Short name T45
Test name
Test status
Simulation time 305314788138 ps
CPU time 1945.57 seconds
Started May 19 01:01:08 PM PDT 24
Finished May 19 01:33:34 PM PDT 24
Peak memory 190836 kb
Host smart-b2aa1a37-172f-4186-928a-b90ea3515134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312772243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3312772243
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1889824087
Short name T90
Test name
Test status
Simulation time 39369118 ps
CPU time 0.55 seconds
Started May 19 01:06:32 PM PDT 24
Finished May 19 01:06:33 PM PDT 24
Peak memory 182752 kb
Host smart-321ee7a9-a7a4-4f3a-8722-af3ffbcc568f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889824087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1889824087
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1398779361
Short name T87
Test name
Test status
Simulation time 114845075 ps
CPU time 0.74 seconds
Started May 19 01:06:33 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 192604 kb
Host smart-8c76d0fe-3f26-421c-b554-0d457280e9e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398779361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1398779361
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3628946150
Short name T30
Test name
Test status
Simulation time 67555151 ps
CPU time 1.1 seconds
Started May 19 01:06:55 PM PDT 24
Finished May 19 01:06:58 PM PDT 24
Peak memory 195548 kb
Host smart-ccff7423-a6bc-4b37-9d65-034fd9d92079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628946150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3628946150
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/101.rv_timer_random.568634204
Short name T137
Test name
Test status
Simulation time 154959515428 ps
CPU time 411.32 seconds
Started May 19 01:01:13 PM PDT 24
Finished May 19 01:08:05 PM PDT 24
Peak memory 190844 kb
Host smart-dece289b-81e1-4313-832e-f7d01a062506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568634204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.568634204
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.2826000703
Short name T283
Test name
Test status
Simulation time 109725250358 ps
CPU time 95.99 seconds
Started May 19 12:59:25 PM PDT 24
Finished May 19 01:01:02 PM PDT 24
Peak memory 190804 kb
Host smart-3b3ae20b-5e4c-446f-b130-271109e09ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826000703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2826000703
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.586859934
Short name T305
Test name
Test status
Simulation time 130520738280 ps
CPU time 657.46 seconds
Started May 19 01:01:59 PM PDT 24
Finished May 19 01:12:57 PM PDT 24
Peak memory 190836 kb
Host smart-162d2403-4ee0-4686-a049-2ce1e662fcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586859934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.586859934
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2662417821
Short name T238
Test name
Test status
Simulation time 214718229216 ps
CPU time 713.85 seconds
Started May 19 01:02:08 PM PDT 24
Finished May 19 01:14:02 PM PDT 24
Peak memory 190788 kb
Host smart-8a9ea4f6-638f-40d9-b37e-5ac0af0b2ed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662417821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2662417821
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.627879506
Short name T218
Test name
Test status
Simulation time 285346244962 ps
CPU time 800.08 seconds
Started May 19 12:59:10 PM PDT 24
Finished May 19 01:12:30 PM PDT 24
Peak memory 191064 kb
Host smart-b05b4f7d-420d-4f28-bacb-db80b6e817dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627879506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.627879506
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1067475641
Short name T130
Test name
Test status
Simulation time 52765252472 ps
CPU time 89.14 seconds
Started May 19 01:00:13 PM PDT 24
Finished May 19 01:01:43 PM PDT 24
Peak memory 182628 kb
Host smart-d182c6ed-3717-4ef2-89cb-fd75d83c0ca9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067475641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1067475641
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1937192715
Short name T190
Test name
Test status
Simulation time 493427822757 ps
CPU time 476.25 seconds
Started May 19 01:00:25 PM PDT 24
Finished May 19 01:08:22 PM PDT 24
Peak memory 182620 kb
Host smart-ab7f8a83-9333-4dbd-887e-31972f53871c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937192715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1937192715
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.1761454382
Short name T246
Test name
Test status
Simulation time 551152143315 ps
CPU time 302.71 seconds
Started May 19 01:00:34 PM PDT 24
Finished May 19 01:05:37 PM PDT 24
Peak memory 190756 kb
Host smart-9674754f-839e-432d-b369-c35761c4b1fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761454382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1761454382
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.364383554
Short name T267
Test name
Test status
Simulation time 131860954927 ps
CPU time 185.2 seconds
Started May 19 01:00:57 PM PDT 24
Finished May 19 01:04:03 PM PDT 24
Peak memory 193100 kb
Host smart-4d6a1102-58ca-4f08-986b-92805e31088b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364383554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.364383554
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.406609029
Short name T300
Test name
Test status
Simulation time 62570960979 ps
CPU time 34.08 seconds
Started May 19 12:59:22 PM PDT 24
Finished May 19 12:59:57 PM PDT 24
Peak memory 182912 kb
Host smart-cea9fa98-a9a0-4729-bb16-8b9d6eec4cbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406609029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.406609029
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.552456757
Short name T61
Test name
Test status
Simulation time 66269212306 ps
CPU time 106.88 seconds
Started May 19 12:59:24 PM PDT 24
Finished May 19 01:01:12 PM PDT 24
Peak memory 191096 kb
Host smart-a9521bb8-be20-4bfa-bda3-4888c78d1463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552456757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.552456757
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/104.rv_timer_random.4072902343
Short name T177
Test name
Test status
Simulation time 245454460580 ps
CPU time 682.72 seconds
Started May 19 01:01:12 PM PDT 24
Finished May 19 01:12:36 PM PDT 24
Peak memory 191148 kb
Host smart-55a51b4a-5888-4554-b253-87ad6c3f057f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072902343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4072902343
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1521636286
Short name T284
Test name
Test status
Simulation time 795759382319 ps
CPU time 1030.37 seconds
Started May 19 01:01:43 PM PDT 24
Finished May 19 01:18:54 PM PDT 24
Peak memory 190824 kb
Host smart-669c5601-1e34-4da0-81e4-71057c90ba4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521636286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1521636286
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3614063233
Short name T168
Test name
Test status
Simulation time 337278569103 ps
CPU time 380.33 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:07:44 PM PDT 24
Peak memory 190780 kb
Host smart-616ebe38-b502-4f17-a36a-95ec2221cb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614063233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3614063233
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.4098337604
Short name T162
Test name
Test status
Simulation time 669170692999 ps
CPU time 254.64 seconds
Started May 19 01:01:22 PM PDT 24
Finished May 19 01:05:37 PM PDT 24
Peak memory 190848 kb
Host smart-930ad4e4-e688-4737-8e3a-868afdcec17d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098337604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4098337604
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.907876260
Short name T232
Test name
Test status
Simulation time 459088214551 ps
CPU time 545.61 seconds
Started May 19 01:01:30 PM PDT 24
Finished May 19 01:10:36 PM PDT 24
Peak memory 190816 kb
Host smart-edac141b-a5b8-4b54-afb8-fe5e0de97694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907876260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.907876260
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3333663878
Short name T152
Test name
Test status
Simulation time 56651359106 ps
CPU time 100.78 seconds
Started May 19 01:01:37 PM PDT 24
Finished May 19 01:03:18 PM PDT 24
Peak memory 191096 kb
Host smart-29db4068-61a7-448c-8125-e98cc9576ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333663878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3333663878
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1920875057
Short name T255
Test name
Test status
Simulation time 40024999545 ps
CPU time 65.24 seconds
Started May 19 01:01:35 PM PDT 24
Finished May 19 01:02:41 PM PDT 24
Peak memory 182624 kb
Host smart-4614c0a0-a21a-44ab-8b15-b07d22be2a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920875057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1920875057
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3928281738
Short name T191
Test name
Test status
Simulation time 122422861127 ps
CPU time 142.7 seconds
Started May 19 12:59:26 PM PDT 24
Finished May 19 01:01:49 PM PDT 24
Peak memory 192128 kb
Host smart-ceb57d1a-a618-4822-8470-aa6b2eb2c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928281738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3928281738
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/146.rv_timer_random.58160816
Short name T323
Test name
Test status
Simulation time 46577671668 ps
CPU time 1182 seconds
Started May 19 01:01:41 PM PDT 24
Finished May 19 01:21:23 PM PDT 24
Peak memory 190764 kb
Host smart-4f7f387e-68d0-4bb9-bb3f-d0320d4dd59c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58160816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.58160816
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1607430891
Short name T328
Test name
Test status
Simulation time 92833407818 ps
CPU time 319.77 seconds
Started May 19 01:01:41 PM PDT 24
Finished May 19 01:07:01 PM PDT 24
Peak memory 190808 kb
Host smart-1b3147c5-f449-4820-a1c9-6e194369cadb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607430891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1607430891
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1888073148
Short name T200
Test name
Test status
Simulation time 139742682085 ps
CPU time 154.94 seconds
Started May 19 01:01:49 PM PDT 24
Finished May 19 01:04:24 PM PDT 24
Peak memory 190804 kb
Host smart-8dfe0f46-ce38-41b1-a677-dc92837b5d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888073148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1888073148
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.1305054317
Short name T451
Test name
Test status
Simulation time 710951536926 ps
CPU time 471.78 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 01:07:20 PM PDT 24
Peak memory 190796 kb
Host smart-91fdfde1-4f34-4c3e-bd98-348dc04c6fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305054317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1305054317
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1739466771
Short name T105
Test name
Test status
Simulation time 175708210501 ps
CPU time 579.96 seconds
Started May 19 01:01:51 PM PDT 24
Finished May 19 01:11:31 PM PDT 24
Peak memory 190820 kb
Host smart-21fb7d00-4cbe-41e1-b585-0997e0d5716a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739466771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1739466771
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2291055866
Short name T174
Test name
Test status
Simulation time 590701713228 ps
CPU time 753.59 seconds
Started May 19 01:01:48 PM PDT 24
Finished May 19 01:14:22 PM PDT 24
Peak memory 190820 kb
Host smart-88465a08-cabc-434e-993d-354606cb5e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291055866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2291055866
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3418539038
Short name T291
Test name
Test status
Simulation time 209601731904 ps
CPU time 305.04 seconds
Started May 19 01:01:54 PM PDT 24
Finished May 19 01:06:59 PM PDT 24
Peak memory 191068 kb
Host smart-5cfe9d55-cc57-422c-acca-ad36b0969088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418539038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3418539038
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.3214747786
Short name T118
Test name
Test status
Simulation time 164252827192 ps
CPU time 635.1 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 01:10:04 PM PDT 24
Peak memory 190804 kb
Host smart-b15cdfac-5a46-435a-a4db-ddce8f47dda8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214747786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3214747786
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.235575144
Short name T346
Test name
Test status
Simulation time 57729599778 ps
CPU time 112.75 seconds
Started May 19 12:59:29 PM PDT 24
Finished May 19 01:01:23 PM PDT 24
Peak memory 190740 kb
Host smart-0c9f216e-c2e1-4584-b481-6bbd0c224b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235575144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.235575144
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/182.rv_timer_random.3841956958
Short name T343
Test name
Test status
Simulation time 51570462147 ps
CPU time 40.6 seconds
Started May 19 01:02:00 PM PDT 24
Finished May 19 01:02:41 PM PDT 24
Peak memory 182600 kb
Host smart-dea24143-9346-4d55-96f8-1a9a4b353339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841956958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3841956958
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.482333336
Short name T9
Test name
Test status
Simulation time 37981334141 ps
CPU time 80.09 seconds
Started May 19 01:01:58 PM PDT 24
Finished May 19 01:03:18 PM PDT 24
Peak memory 190828 kb
Host smart-d1d13576-6675-4d14-875d-7ed29df32a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482333336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.482333336
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.377881102
Short name T115
Test name
Test status
Simulation time 219067123002 ps
CPU time 118.62 seconds
Started May 19 01:02:08 PM PDT 24
Finished May 19 01:04:08 PM PDT 24
Peak memory 190828 kb
Host smart-05a377ec-e93f-4344-b2ce-ba456033169d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377881102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.377881102
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.2633940170
Short name T295
Test name
Test status
Simulation time 311205989088 ps
CPU time 512.64 seconds
Started May 19 12:59:06 PM PDT 24
Finished May 19 01:07:40 PM PDT 24
Peak memory 193012 kb
Host smart-5d1fa72d-4174-4bb3-9d55-fd5ceb89833f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633940170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2633940170
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.706204510
Short name T181
Test name
Test status
Simulation time 126287148512 ps
CPU time 65.36 seconds
Started May 19 12:59:41 PM PDT 24
Finished May 19 01:00:47 PM PDT 24
Peak memory 182504 kb
Host smart-ce84f25b-7397-4f3a-acdc-0d130f80106e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706204510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.706204510
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random.3213084078
Short name T223
Test name
Test status
Simulation time 586482481303 ps
CPU time 457.33 seconds
Started May 19 12:59:46 PM PDT 24
Finished May 19 01:07:24 PM PDT 24
Peak memory 190836 kb
Host smart-d2cf594b-4921-49e0-b2ed-317b4c9a1d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213084078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3213084078
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3228036754
Short name T280
Test name
Test status
Simulation time 6271959901000 ps
CPU time 2215.64 seconds
Started May 19 12:59:16 PM PDT 24
Finished May 19 01:36:13 PM PDT 24
Peak memory 182608 kb
Host smart-07ebcfa5-a8b0-46a9-88e8-c83979b277d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228036754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3228036754
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/57.rv_timer_random.806086147
Short name T338
Test name
Test status
Simulation time 400416323676 ps
CPU time 403.29 seconds
Started May 19 01:00:50 PM PDT 24
Finished May 19 01:07:34 PM PDT 24
Peak memory 190800 kb
Host smart-31caeda4-56bd-4285-a4b0-44903be9f21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806086147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.806086147
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.621925532
Short name T318
Test name
Test status
Simulation time 522743507613 ps
CPU time 752.35 seconds
Started May 19 12:59:22 PM PDT 24
Finished May 19 01:11:56 PM PDT 24
Peak memory 194404 kb
Host smart-5c737db1-b322-4c73-8e74-0b62b8382e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621925532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.621925532
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.417637600
Short name T148
Test name
Test status
Simulation time 746366983199 ps
CPU time 836.97 seconds
Started May 19 01:01:07 PM PDT 24
Finished May 19 01:15:05 PM PDT 24
Peak memory 190812 kb
Host smart-75063e6c-7b9c-4947-86ed-739a25653472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417637600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.417637600
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3879020100
Short name T75
Test name
Test status
Simulation time 158274323 ps
CPU time 0.78 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 182624 kb
Host smart-c94835b3-0c00-4700-9d4e-d42629d52986
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879020100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3879020100
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2746428216
Short name T82
Test name
Test status
Simulation time 37595162 ps
CPU time 1.36 seconds
Started May 19 01:06:32 PM PDT 24
Finished May 19 01:06:34 PM PDT 24
Peak memory 192180 kb
Host smart-42cf2fde-32f7-4079-b5ab-da5cc8c0bf08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746428216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2746428216
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4289766397
Short name T54
Test name
Test status
Simulation time 52395881 ps
CPU time 0.56 seconds
Started May 19 01:06:28 PM PDT 24
Finished May 19 01:06:30 PM PDT 24
Peak memory 182628 kb
Host smart-9b4407e3-9bdf-4efe-ac35-569c805d7f36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289766397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.4289766397
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.264509971
Short name T567
Test name
Test status
Simulation time 24857235 ps
CPU time 0.7 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 193736 kb
Host smart-f486fde2-63c4-4223-a0c3-105b0062c695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264509971 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.264509971
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3005310812
Short name T475
Test name
Test status
Simulation time 43501816 ps
CPU time 0.52 seconds
Started May 19 01:06:28 PM PDT 24
Finished May 19 01:06:30 PM PDT 24
Peak memory 182040 kb
Host smart-4d7be025-3413-4afe-9e6c-1290b899669b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005310812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3005310812
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2309228620
Short name T578
Test name
Test status
Simulation time 14843154 ps
CPU time 0.65 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 191564 kb
Host smart-20de905f-0bef-4106-9245-bae55a950475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309228620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2309228620
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.4222692028
Short name T478
Test name
Test status
Simulation time 27842126 ps
CPU time 1.37 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:32 PM PDT 24
Peak memory 197604 kb
Host smart-362b85c8-b4b4-4a28-8641-beb08613f152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222692028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.4222692028
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3888264995
Short name T552
Test name
Test status
Simulation time 154969093 ps
CPU time 1.3 seconds
Started May 19 01:06:28 PM PDT 24
Finished May 19 01:06:30 PM PDT 24
Peak memory 183444 kb
Host smart-c9c5f45d-884d-4898-a249-77aa2fb7821e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888264995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3888264995
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.14416921
Short name T505
Test name
Test status
Simulation time 226420321 ps
CPU time 1.38 seconds
Started May 19 01:06:32 PM PDT 24
Finished May 19 01:06:34 PM PDT 24
Peak memory 193428 kb
Host smart-04d3ec32-4fbb-4bca-b065-d922aa5ac6a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14416921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ba
sh.14416921
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3748470287
Short name T94
Test name
Test status
Simulation time 20639533 ps
CPU time 0.55 seconds
Started May 19 01:06:35 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 182624 kb
Host smart-7beac835-eba3-47dc-adf1-899f18e78a6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748470287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3748470287
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2881751774
Short name T576
Test name
Test status
Simulation time 34907357 ps
CPU time 0.67 seconds
Started May 19 01:06:33 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 194400 kb
Host smart-20d360ee-4692-4e0a-b935-510e7dd3863b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881751774 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2881751774
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3827823403
Short name T496
Test name
Test status
Simulation time 16115414 ps
CPU time 0.53 seconds
Started May 19 01:06:29 PM PDT 24
Finished May 19 01:06:31 PM PDT 24
Peak memory 182624 kb
Host smart-75bac4c2-7862-458e-8e6c-e74591a7b809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827823403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3827823403
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2982060349
Short name T547
Test name
Test status
Simulation time 69452945 ps
CPU time 0.76 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 193344 kb
Host smart-5a183211-bf6e-4a46-ae07-b4fffb2264df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982060349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2982060349
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2527890856
Short name T557
Test name
Test status
Simulation time 418336460 ps
CPU time 3.54 seconds
Started May 19 01:06:30 PM PDT 24
Finished May 19 01:06:34 PM PDT 24
Peak memory 197632 kb
Host smart-b802a18a-c86a-4fc7-80e4-a6cd65076f68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527890856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2527890856
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.812619792
Short name T95
Test name
Test status
Simulation time 63043055 ps
CPU time 1.04 seconds
Started May 19 01:06:35 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 194952 kb
Host smart-d9b586df-fe81-4fb5-ba59-8ab8420f6673
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812619792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.812619792
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3639946093
Short name T566
Test name
Test status
Simulation time 32176874 ps
CPU time 0.88 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:46 PM PDT 24
Peak memory 197276 kb
Host smart-bf365d7f-0590-45cf-88e3-91f7c1a484a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639946093 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3639946093
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1754732539
Short name T91
Test name
Test status
Simulation time 13333611 ps
CPU time 0.56 seconds
Started May 19 01:06:46 PM PDT 24
Finished May 19 01:06:47 PM PDT 24
Peak memory 182648 kb
Host smart-db740c2e-540e-40e3-bfbc-bf229f4f1b60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754732539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1754732539
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3042497988
Short name T459
Test name
Test status
Simulation time 39355172 ps
CPU time 0.6 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:46 PM PDT 24
Peak memory 182608 kb
Host smart-32384229-4153-4daf-8850-d71b43d44588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042497988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3042497988
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1045637684
Short name T544
Test name
Test status
Simulation time 36018898 ps
CPU time 0.8 seconds
Started May 19 01:06:45 PM PDT 24
Finished May 19 01:06:47 PM PDT 24
Peak memory 193488 kb
Host smart-e4756656-abb2-40b0-bfd7-96f06e8ef6e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045637684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1045637684
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3394645362
Short name T549
Test name
Test status
Simulation time 70448463 ps
CPU time 1.84 seconds
Started May 19 01:06:45 PM PDT 24
Finished May 19 01:06:48 PM PDT 24
Peak memory 197596 kb
Host smart-c0bbf23a-0746-4b82-a0d9-7bcd4a17c6a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394645362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3394645362
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1085685755
Short name T510
Test name
Test status
Simulation time 130333148 ps
CPU time 1.4 seconds
Started May 19 01:06:47 PM PDT 24
Finished May 19 01:06:49 PM PDT 24
Peak memory 183180 kb
Host smart-49ad9f27-7cf6-4445-a7e9-5b8ce5f20ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085685755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1085685755
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1031922001
Short name T457
Test name
Test status
Simulation time 437078974 ps
CPU time 0.87 seconds
Started May 19 01:06:53 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 196736 kb
Host smart-8c2b7058-2dd4-4975-8fd9-3b76a88ccc35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031922001 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1031922001
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1434810261
Short name T491
Test name
Test status
Simulation time 31824322 ps
CPU time 0.54 seconds
Started May 19 01:06:49 PM PDT 24
Finished May 19 01:06:51 PM PDT 24
Peak memory 182768 kb
Host smart-2ced359b-4310-4d1f-a61f-1b36cbd090e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434810261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1434810261
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2956566670
Short name T518
Test name
Test status
Simulation time 56508755 ps
CPU time 0.53 seconds
Started May 19 01:06:50 PM PDT 24
Finished May 19 01:06:52 PM PDT 24
Peak memory 182036 kb
Host smart-dfcc9d58-d8c7-4974-959a-5eff9652b779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956566670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2956566670
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.108963681
Short name T572
Test name
Test status
Simulation time 64830719 ps
CPU time 0.69 seconds
Started May 19 01:06:49 PM PDT 24
Finished May 19 01:06:50 PM PDT 24
Peak memory 192080 kb
Host smart-d1c898c9-9b0b-4f52-b2ac-e6bfd1c4565e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108963681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.108963681
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3251562376
Short name T577
Test name
Test status
Simulation time 776245320 ps
CPU time 2.89 seconds
Started May 19 01:06:45 PM PDT 24
Finished May 19 01:06:49 PM PDT 24
Peak memory 197660 kb
Host smart-294d0ab7-ac00-4af2-8d6c-4f4c8dcd3794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251562376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3251562376
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1437897194
Short name T484
Test name
Test status
Simulation time 101620644 ps
CPU time 1.35 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:46 PM PDT 24
Peak memory 195444 kb
Host smart-dc51dcd8-f555-4793-9d69-17dc4f8b6888
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437897194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1437897194
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1033831177
Short name T562
Test name
Test status
Simulation time 92059027 ps
CPU time 0.66 seconds
Started May 19 01:06:53 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 194104 kb
Host smart-0bec3325-fe0b-480c-9b34-dc49055c2bba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033831177 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1033831177
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3836663601
Short name T88
Test name
Test status
Simulation time 21192753 ps
CPU time 0.64 seconds
Started May 19 01:06:53 PM PDT 24
Finished May 19 01:06:54 PM PDT 24
Peak memory 182688 kb
Host smart-a8e525ae-4226-4f9b-a02d-788b74564bf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836663601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3836663601
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2065655575
Short name T503
Test name
Test status
Simulation time 39375854 ps
CPU time 0.58 seconds
Started May 19 01:06:51 PM PDT 24
Finished May 19 01:06:53 PM PDT 24
Peak memory 182640 kb
Host smart-0e04610e-bf43-4d0d-b84f-1d60408afb39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065655575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2065655575
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3181965562
Short name T537
Test name
Test status
Simulation time 534233306 ps
CPU time 0.81 seconds
Started May 19 01:06:49 PM PDT 24
Finished May 19 01:06:51 PM PDT 24
Peak memory 193432 kb
Host smart-79304fbc-64ee-4e88-9d27-1bf3df81ddc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181965562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3181965562
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1672929940
Short name T574
Test name
Test status
Simulation time 447426063 ps
CPU time 1.16 seconds
Started May 19 01:06:53 PM PDT 24
Finished May 19 01:06:56 PM PDT 24
Peak memory 197152 kb
Host smart-7f7f5fe9-217f-4338-8b4e-b67e356e1950
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672929940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1672929940
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2084071608
Short name T541
Test name
Test status
Simulation time 47458612 ps
CPU time 0.83 seconds
Started May 19 01:06:55 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 193516 kb
Host smart-d3038b18-253a-4b1d-937e-3a9ad9936c94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084071608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2084071608
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1523407185
Short name T486
Test name
Test status
Simulation time 30679303 ps
CPU time 0.76 seconds
Started May 19 01:06:49 PM PDT 24
Finished May 19 01:06:51 PM PDT 24
Peak memory 195924 kb
Host smart-3cf02fac-dde6-47ad-8adc-493e9fc2f5d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523407185 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1523407185
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4069856462
Short name T79
Test name
Test status
Simulation time 30643796 ps
CPU time 0.63 seconds
Started May 19 01:06:55 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 182908 kb
Host smart-e139f2e9-aeec-4ef9-9eac-15fe004274b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069856462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.4069856462
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2149362456
Short name T466
Test name
Test status
Simulation time 58181818 ps
CPU time 0.56 seconds
Started May 19 01:06:53 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 182612 kb
Host smart-b6d87203-c18a-4186-bec2-cce2cdf49964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149362456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2149362456
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.422347101
Short name T89
Test name
Test status
Simulation time 242914738 ps
CPU time 0.78 seconds
Started May 19 01:06:55 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 193272 kb
Host smart-fc79f705-43b4-43a6-935c-c1f35e4a9612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422347101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.422347101
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.657348745
Short name T500
Test name
Test status
Simulation time 1009006786 ps
CPU time 2.36 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 197596 kb
Host smart-e8430ff2-0418-4fe0-9a7c-92c4ae643bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657348745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.657348745
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1427156895
Short name T501
Test name
Test status
Simulation time 55222692 ps
CPU time 0.86 seconds
Started May 19 01:06:51 PM PDT 24
Finished May 19 01:06:53 PM PDT 24
Peak memory 193772 kb
Host smart-36471207-404a-4a8b-a708-c441d7623f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427156895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1427156895
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4293931666
Short name T495
Test name
Test status
Simulation time 31016656 ps
CPU time 0.94 seconds
Started May 19 01:06:51 PM PDT 24
Finished May 19 01:06:53 PM PDT 24
Peak memory 196844 kb
Host smart-9c61b498-1110-4ee7-b933-2e00bfdedbe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293931666 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4293931666
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2996693297
Short name T80
Test name
Test status
Simulation time 14040461 ps
CPU time 0.55 seconds
Started May 19 01:06:52 PM PDT 24
Finished May 19 01:06:53 PM PDT 24
Peak memory 181888 kb
Host smart-e204ef66-334d-48cf-b9e0-3cc42601f59a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996693297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2996693297
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1409866277
Short name T514
Test name
Test status
Simulation time 39665860 ps
CPU time 0.51 seconds
Started May 19 01:06:50 PM PDT 24
Finished May 19 01:06:51 PM PDT 24
Peak memory 182288 kb
Host smart-dcc57e22-cdea-420a-ac5f-102d5d34ec5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409866277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1409866277
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3705326357
Short name T74
Test name
Test status
Simulation time 19112761 ps
CPU time 0.71 seconds
Started May 19 01:06:52 PM PDT 24
Finished May 19 01:06:54 PM PDT 24
Peak memory 191676 kb
Host smart-1a7ae8a8-9164-4e07-a727-cd33c3e352de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705326357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3705326357
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2242726335
Short name T488
Test name
Test status
Simulation time 485387486 ps
CPU time 1.25 seconds
Started May 19 01:06:49 PM PDT 24
Finished May 19 01:06:51 PM PDT 24
Peak memory 197596 kb
Host smart-72a4fbff-64e4-457d-9e4e-21cf9de4dffc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242726335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2242726335
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.807966298
Short name T494
Test name
Test status
Simulation time 33573030 ps
CPU time 1.14 seconds
Started May 19 01:06:49 PM PDT 24
Finished May 19 01:06:51 PM PDT 24
Peak memory 197532 kb
Host smart-21dfc19a-5a2e-4629-9b7b-a6f132ff87df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807966298 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.807966298
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.985093677
Short name T83
Test name
Test status
Simulation time 23612563 ps
CPU time 0.55 seconds
Started May 19 01:06:53 PM PDT 24
Finished May 19 01:06:54 PM PDT 24
Peak memory 182448 kb
Host smart-d2c3e925-6f9c-4c55-88a8-871e05311272
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985093677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.985093677
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.113606114
Short name T512
Test name
Test status
Simulation time 111170002 ps
CPU time 0.6 seconds
Started May 19 01:06:49 PM PDT 24
Finished May 19 01:06:50 PM PDT 24
Peak memory 182960 kb
Host smart-22df7765-ebcc-4a94-9f87-ad4ab4b49c67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113606114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.113606114
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1866582339
Short name T539
Test name
Test status
Simulation time 46822198 ps
CPU time 0.59 seconds
Started May 19 01:06:51 PM PDT 24
Finished May 19 01:06:53 PM PDT 24
Peak memory 191396 kb
Host smart-f60336d0-56a3-49c2-91ac-58562cd57158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866582339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1866582339
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2403344383
Short name T533
Test name
Test status
Simulation time 162340993 ps
CPU time 2.68 seconds
Started May 19 01:06:52 PM PDT 24
Finished May 19 01:06:56 PM PDT 24
Peak memory 197572 kb
Host smart-38e9bee3-fe39-4d28-998d-6b2f837e94f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403344383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2403344383
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1090614885
Short name T543
Test name
Test status
Simulation time 51106915 ps
CPU time 0.82 seconds
Started May 19 01:06:50 PM PDT 24
Finished May 19 01:06:52 PM PDT 24
Peak memory 193552 kb
Host smart-c7b3c849-07ad-4d0c-a7c5-7341272d49bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090614885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1090614885
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1409716653
Short name T545
Test name
Test status
Simulation time 127920040 ps
CPU time 0.66 seconds
Started May 19 01:06:56 PM PDT 24
Finished May 19 01:06:58 PM PDT 24
Peak memory 194820 kb
Host smart-484ce4e2-4dd5-4a74-bf46-e5da33b2edd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409716653 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1409716653
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3717486466
Short name T93
Test name
Test status
Simulation time 154238718 ps
CPU time 0.57 seconds
Started May 19 01:06:58 PM PDT 24
Finished May 19 01:06:59 PM PDT 24
Peak memory 182764 kb
Host smart-c0fd4a65-aadc-4f8e-8269-ec86837e4ec6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717486466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3717486466
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3323677679
Short name T515
Test name
Test status
Simulation time 13822893 ps
CPU time 0.53 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 182504 kb
Host smart-1620b92d-225e-4d1c-8747-956c8585482b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323677679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3323677679
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3691108893
Short name T569
Test name
Test status
Simulation time 53208493 ps
CPU time 0.75 seconds
Started May 19 01:06:56 PM PDT 24
Finished May 19 01:06:58 PM PDT 24
Peak memory 191728 kb
Host smart-bb4def73-f00d-47a9-bbfe-75e1867a1268
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691108893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3691108893
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3371355323
Short name T529
Test name
Test status
Simulation time 116705674 ps
CPU time 2.43 seconds
Started May 19 01:06:52 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 196980 kb
Host smart-1ca93580-6217-49f8-9e67-8985874d7195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371355323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3371355323
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3167866724
Short name T497
Test name
Test status
Simulation time 90112864 ps
CPU time 0.84 seconds
Started May 19 01:06:52 PM PDT 24
Finished May 19 01:06:54 PM PDT 24
Peak memory 193744 kb
Host smart-4b8c3a85-e139-4905-9941-4f8544cdd1a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167866724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3167866724
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.290518499
Short name T51
Test name
Test status
Simulation time 46145011 ps
CPU time 0.72 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 194928 kb
Host smart-9e18dad0-2bf5-45e0-be04-cffdb79f7f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290518499 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.290518499
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2478730861
Short name T536
Test name
Test status
Simulation time 66417502 ps
CPU time 0.57 seconds
Started May 19 01:06:55 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 182764 kb
Host smart-9faf85bc-445a-4585-8758-8af72f2fb491
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478730861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2478730861
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2186402640
Short name T460
Test name
Test status
Simulation time 11428904 ps
CPU time 0.52 seconds
Started May 19 01:06:56 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 181980 kb
Host smart-09dcc066-e174-4a7d-b7bc-7e9ac5811be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186402640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2186402640
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1361359139
Short name T70
Test name
Test status
Simulation time 24430229 ps
CPU time 0.66 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:56 PM PDT 24
Peak memory 192208 kb
Host smart-ecdd8fa4-97a8-4066-ac94-706d80368533
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361359139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1361359139
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.668764351
Short name T556
Test name
Test status
Simulation time 46369343 ps
CPU time 1.47 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:56 PM PDT 24
Peak memory 197644 kb
Host smart-399786e5-14d7-45a2-8eff-aa7a01f1faac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668764351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.668764351
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3695972341
Short name T508
Test name
Test status
Simulation time 396436522 ps
CPU time 1.36 seconds
Started May 19 01:06:56 PM PDT 24
Finished May 19 01:06:58 PM PDT 24
Peak memory 195332 kb
Host smart-7c3a909d-890a-4d98-91f5-e61aa5d669b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695972341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3695972341
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3308117777
Short name T52
Test name
Test status
Simulation time 55763351 ps
CPU time 0.83 seconds
Started May 19 01:06:53 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 196628 kb
Host smart-47a7f174-14d0-44a4-a902-51d8e45dc3c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308117777 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3308117777
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3174715068
Short name T86
Test name
Test status
Simulation time 11073493 ps
CPU time 0.54 seconds
Started May 19 01:06:53 PM PDT 24
Finished May 19 01:06:55 PM PDT 24
Peak memory 182688 kb
Host smart-dc4759a2-5ef3-4864-b8d8-05c3491caa84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174715068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3174715068
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1775041148
Short name T519
Test name
Test status
Simulation time 59573225 ps
CPU time 0.57 seconds
Started May 19 01:06:56 PM PDT 24
Finished May 19 01:06:58 PM PDT 24
Peak memory 182676 kb
Host smart-47158111-4be1-4d88-aea1-bfd05455bfae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775041148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1775041148
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3203773789
Short name T546
Test name
Test status
Simulation time 50818149 ps
CPU time 0.59 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:56 PM PDT 24
Peak memory 192040 kb
Host smart-d6dfa1ad-35c5-4db9-a5a6-46765890e6af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203773789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3203773789
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2542524582
Short name T513
Test name
Test status
Simulation time 53838059 ps
CPU time 2.84 seconds
Started May 19 01:06:56 PM PDT 24
Finished May 19 01:07:00 PM PDT 24
Peak memory 197572 kb
Host smart-cd86c30d-5c60-4e9e-9dbe-34b3befde56e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542524582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2542524582
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1191368791
Short name T521
Test name
Test status
Simulation time 362396760 ps
CPU time 0.84 seconds
Started May 19 01:07:01 PM PDT 24
Finished May 19 01:07:03 PM PDT 24
Peak memory 195376 kb
Host smart-e7c67081-f1af-4df3-ac80-796e0e7cd72f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191368791 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1191368791
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1261505617
Short name T33
Test name
Test status
Simulation time 13365540 ps
CPU time 0.56 seconds
Started May 19 01:07:06 PM PDT 24
Finished May 19 01:07:08 PM PDT 24
Peak memory 182760 kb
Host smart-dd81c035-2ec1-42fc-90a0-ac7675f8f069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261505617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1261505617
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1846572257
Short name T458
Test name
Test status
Simulation time 48099403 ps
CPU time 0.61 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 182640 kb
Host smart-f157a080-ea4b-4e6e-abcc-36683421d48b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846572257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1846572257
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3504876193
Short name T542
Test name
Test status
Simulation time 39888395 ps
CPU time 0.85 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 193556 kb
Host smart-562887c2-b423-4077-8ef4-d781f3c3479a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504876193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3504876193
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.348021387
Short name T462
Test name
Test status
Simulation time 179742381 ps
CPU time 2.92 seconds
Started May 19 01:06:55 PM PDT 24
Finished May 19 01:06:59 PM PDT 24
Peak memory 197408 kb
Host smart-690de893-da99-4c45-8a95-86f1da46eb5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348021387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.348021387
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1318829954
Short name T97
Test name
Test status
Simulation time 440108841 ps
CPU time 1.32 seconds
Started May 19 01:06:54 PM PDT 24
Finished May 19 01:06:57 PM PDT 24
Peak memory 183456 kb
Host smart-8fed4b13-dad0-4b8e-8b8e-8acbdd59b367
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318829954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1318829954
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.333422114
Short name T76
Test name
Test status
Simulation time 69426137 ps
CPU time 0.86 seconds
Started May 19 01:06:37 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 182688 kb
Host smart-1d2d3ea9-99c8-4f0c-b1d8-eab2eff06032
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333422114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.333422114
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.524301297
Short name T479
Test name
Test status
Simulation time 66935571 ps
CPU time 2.23 seconds
Started May 19 01:06:33 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 193292 kb
Host smart-d75dd1d6-3d84-4dc9-a51c-08f6bf305270
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524301297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.524301297
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1295993941
Short name T511
Test name
Test status
Simulation time 29225203 ps
CPU time 0.6 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 182752 kb
Host smart-d7872366-60f7-4672-9d74-9c5cf04c3cbc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295993941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1295993941
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3613447306
Short name T50
Test name
Test status
Simulation time 98982021 ps
CPU time 0.75 seconds
Started May 19 01:06:35 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 195516 kb
Host smart-91f89ad5-5d99-4987-98cd-7ead38860a18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613447306 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3613447306
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2893586792
Short name T527
Test name
Test status
Simulation time 16980305 ps
CPU time 0.59 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 182940 kb
Host smart-9017cdbb-c9b0-4e87-96d8-6f670845bdb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893586792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2893586792
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.186279936
Short name T516
Test name
Test status
Simulation time 15985365 ps
CPU time 0.55 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 182612 kb
Host smart-8de1407e-334f-46b1-9714-05f34545235b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186279936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.186279936
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.643338939
Short name T92
Test name
Test status
Simulation time 90102158 ps
CPU time 0.65 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 191472 kb
Host smart-68446327-2fd7-455a-8b15-883a3427c0db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643338939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.643338939
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2674915281
Short name T502
Test name
Test status
Simulation time 557485962 ps
CPU time 2.4 seconds
Started May 19 01:06:37 PM PDT 24
Finished May 19 01:06:40 PM PDT 24
Peak memory 197632 kb
Host smart-bccd29b1-f8b9-4e89-883e-2c804a46f207
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674915281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2674915281
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3383189665
Short name T96
Test name
Test status
Simulation time 372339846 ps
CPU time 1.41 seconds
Started May 19 01:06:35 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 183496 kb
Host smart-aa5493cc-6f0f-4701-9a55-c7f513119a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383189665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3383189665
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.424916691
Short name T568
Test name
Test status
Simulation time 14928078 ps
CPU time 0.6 seconds
Started May 19 01:07:01 PM PDT 24
Finished May 19 01:07:03 PM PDT 24
Peak memory 182688 kb
Host smart-59b4222d-00e5-4cb3-9d59-7dfd30740659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424916691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.424916691
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3547048047
Short name T455
Test name
Test status
Simulation time 15302712 ps
CPU time 0.57 seconds
Started May 19 01:07:06 PM PDT 24
Finished May 19 01:07:08 PM PDT 24
Peak memory 182312 kb
Host smart-61a2efa7-f955-48f4-b9b3-0a54e2a10b4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547048047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3547048047
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3437079063
Short name T507
Test name
Test status
Simulation time 11109649 ps
CPU time 0.54 seconds
Started May 19 01:07:08 PM PDT 24
Finished May 19 01:07:09 PM PDT 24
Peak memory 182100 kb
Host smart-d4b8e9c6-3563-4850-bff1-407184521799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437079063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3437079063
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.669257734
Short name T509
Test name
Test status
Simulation time 14434247 ps
CPU time 0.54 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 182048 kb
Host smart-bda394c3-1d38-420f-aac8-9a64df5502b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669257734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.669257734
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2716487728
Short name T469
Test name
Test status
Simulation time 16699378 ps
CPU time 0.59 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 182732 kb
Host smart-65cf6c05-6825-45b7-8e84-5cafc7be088c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716487728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2716487728
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.203256699
Short name T493
Test name
Test status
Simulation time 47587286 ps
CPU time 0.56 seconds
Started May 19 01:06:59 PM PDT 24
Finished May 19 01:07:00 PM PDT 24
Peak memory 182564 kb
Host smart-b3919188-748f-4fd8-b460-636fb036285d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203256699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.203256699
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.666581043
Short name T540
Test name
Test status
Simulation time 28260668 ps
CPU time 0.6 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 182536 kb
Host smart-4d11bd14-a299-4964-b3f2-40e8b34014ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666581043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.666581043
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3234742147
Short name T467
Test name
Test status
Simulation time 15019130 ps
CPU time 0.54 seconds
Started May 19 01:07:01 PM PDT 24
Finished May 19 01:07:03 PM PDT 24
Peak memory 182120 kb
Host smart-2eb6f680-d0a6-413d-b86f-97a43895ae7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234742147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3234742147
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3564347910
Short name T564
Test name
Test status
Simulation time 15938760 ps
CPU time 0.56 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 182620 kb
Host smart-723614aa-85f5-46a0-a048-e3220f987371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564347910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3564347910
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.425398952
Short name T570
Test name
Test status
Simulation time 76809434 ps
CPU time 0.55 seconds
Started May 19 01:07:02 PM PDT 24
Finished May 19 01:07:03 PM PDT 24
Peak memory 182300 kb
Host smart-20ed9e7b-f6a6-479e-b243-f1bfe61c859d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425398952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.425398952
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.314189365
Short name T535
Test name
Test status
Simulation time 125219830 ps
CPU time 0.62 seconds
Started May 19 01:06:33 PM PDT 24
Finished May 19 01:06:34 PM PDT 24
Peak memory 191988 kb
Host smart-fc1c3721-12dc-485f-be79-2ae5f0f308aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314189365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.314189365
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2135087019
Short name T73
Test name
Test status
Simulation time 155819678 ps
CPU time 1.43 seconds
Started May 19 01:06:35 PM PDT 24
Finished May 19 01:06:38 PM PDT 24
Peak memory 192120 kb
Host smart-6880435d-d888-4ad6-831a-c287ad519186
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135087019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2135087019
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2297733671
Short name T526
Test name
Test status
Simulation time 122242121 ps
CPU time 0.55 seconds
Started May 19 01:06:35 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 182732 kb
Host smart-e39a7af4-9546-4dd1-a027-7b2f86aef892
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297733671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2297733671
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1184048558
Short name T553
Test name
Test status
Simulation time 59313977 ps
CPU time 0.67 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 194396 kb
Host smart-77b27355-54cd-44d8-8543-c6f2c5bbd56d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184048558 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1184048558
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1186320537
Short name T85
Test name
Test status
Simulation time 15554817 ps
CPU time 0.59 seconds
Started May 19 01:06:35 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 182720 kb
Host smart-49b169c3-0471-4920-a337-f091b1fd29fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186320537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1186320537
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.349731946
Short name T498
Test name
Test status
Simulation time 18791241 ps
CPU time 0.58 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:36 PM PDT 24
Peak memory 182580 kb
Host smart-3d3ac057-7f91-4239-85f8-539796fe2913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349731946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.349731946
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2302803244
Short name T520
Test name
Test status
Simulation time 19122848 ps
CPU time 0.82 seconds
Started May 19 01:06:37 PM PDT 24
Finished May 19 01:06:39 PM PDT 24
Peak memory 193332 kb
Host smart-69189c81-7097-4604-bbec-16ae74a44e11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302803244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2302803244
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3171719665
Short name T473
Test name
Test status
Simulation time 219698068 ps
CPU time 2.12 seconds
Started May 19 01:06:33 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 197640 kb
Host smart-348b6568-9473-450e-b2e4-45d13c717b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171719665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3171719665
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2188793457
Short name T565
Test name
Test status
Simulation time 89853516 ps
CPU time 0.86 seconds
Started May 19 01:06:34 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 193816 kb
Host smart-1e102bb3-3f42-45b0-92f7-5921f650ccfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188793457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2188793457
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1641476288
Short name T571
Test name
Test status
Simulation time 55704563 ps
CPU time 0.56 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:01 PM PDT 24
Peak memory 182700 kb
Host smart-2a22d5c4-b1f5-462a-8123-f0f1e2eb5e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641476288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1641476288
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4290056688
Short name T465
Test name
Test status
Simulation time 13606477 ps
CPU time 0.57 seconds
Started May 19 01:07:01 PM PDT 24
Finished May 19 01:07:03 PM PDT 24
Peak memory 182100 kb
Host smart-88e80446-86bc-4693-866f-cac02347cee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290056688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4290056688
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2101926599
Short name T528
Test name
Test status
Simulation time 39724155 ps
CPU time 0.61 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 182588 kb
Host smart-247a1456-6219-4fd4-b3ca-c5fe830e04f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101926599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2101926599
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1471799487
Short name T530
Test name
Test status
Simulation time 25062286 ps
CPU time 0.54 seconds
Started May 19 01:06:59 PM PDT 24
Finished May 19 01:07:00 PM PDT 24
Peak memory 182088 kb
Host smart-f947b9fc-c81c-44a8-a184-9af518fdecb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471799487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1471799487
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2822289443
Short name T504
Test name
Test status
Simulation time 14586948 ps
CPU time 0.58 seconds
Started May 19 01:07:02 PM PDT 24
Finished May 19 01:07:03 PM PDT 24
Peak memory 182520 kb
Host smart-96906856-9e15-4712-8992-70b5e924d4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822289443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2822289443
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2910461455
Short name T554
Test name
Test status
Simulation time 32573655 ps
CPU time 0.56 seconds
Started May 19 01:07:01 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 182236 kb
Host smart-e1b5119e-05a6-4876-99c9-b957c07ea9ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910461455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2910461455
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2751178210
Short name T471
Test name
Test status
Simulation time 52591280 ps
CPU time 0.57 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 182916 kb
Host smart-4fbaeb8d-ae09-44e8-894a-71b7331e611e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751178210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2751178210
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2274641756
Short name T548
Test name
Test status
Simulation time 27968794 ps
CPU time 0.56 seconds
Started May 19 01:07:00 PM PDT 24
Finished May 19 01:07:02 PM PDT 24
Peak memory 182684 kb
Host smart-f42c46f9-5306-4e3c-9e44-96991d440f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274641756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2274641756
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3691161039
Short name T559
Test name
Test status
Simulation time 53987666 ps
CPU time 0.59 seconds
Started May 19 01:06:59 PM PDT 24
Finished May 19 01:07:00 PM PDT 24
Peak memory 182676 kb
Host smart-853bd0d6-bdba-4840-bbc9-47f44bda0471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691161039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3691161039
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2515554210
Short name T490
Test name
Test status
Simulation time 44622771 ps
CPU time 0.55 seconds
Started May 19 01:07:04 PM PDT 24
Finished May 19 01:07:05 PM PDT 24
Peak memory 182592 kb
Host smart-e6aa9d68-8d28-4db0-a3bd-bdb161c7fbd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515554210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2515554210
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2717461223
Short name T71
Test name
Test status
Simulation time 57169288 ps
CPU time 0.79 seconds
Started May 19 01:06:41 PM PDT 24
Finished May 19 01:06:43 PM PDT 24
Peak memory 192504 kb
Host smart-324f306e-38d4-4650-8c8f-e44eeb0387f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717461223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2717461223
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2338156277
Short name T487
Test name
Test status
Simulation time 91255954 ps
CPU time 3.18 seconds
Started May 19 01:06:39 PM PDT 24
Finished May 19 01:06:44 PM PDT 24
Peak memory 182968 kb
Host smart-6440ed3e-4522-4638-a572-c1f3dd5adec5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338156277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2338156277
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3137145405
Short name T77
Test name
Test status
Simulation time 16396798 ps
CPU time 0.56 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 182740 kb
Host smart-a8c81870-551a-4ff6-828f-3c042f6a24cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137145405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3137145405
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.205998600
Short name T482
Test name
Test status
Simulation time 33819019 ps
CPU time 0.86 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:46 PM PDT 24
Peak memory 197448 kb
Host smart-4704c921-462e-40bb-9395-e6957df8dc9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205998600 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.205998600
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3199376669
Short name T531
Test name
Test status
Simulation time 47270986 ps
CPU time 0.57 seconds
Started May 19 01:06:39 PM PDT 24
Finished May 19 01:06:41 PM PDT 24
Peak memory 182716 kb
Host smart-43586a52-2aed-4998-85d1-3846e8eee6a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199376669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3199376669
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.446050904
Short name T463
Test name
Test status
Simulation time 15551134 ps
CPU time 0.56 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 182352 kb
Host smart-9ac5d054-4df3-447c-bae4-7d2b7d7d130a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446050904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.446050904
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2944396888
Short name T538
Test name
Test status
Simulation time 28830615 ps
CPU time 0.69 seconds
Started May 19 01:06:39 PM PDT 24
Finished May 19 01:06:41 PM PDT 24
Peak memory 192248 kb
Host smart-c4cdb740-5b54-4f42-a650-cca6b46ea6db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944396888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2944396888
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.568055350
Short name T477
Test name
Test status
Simulation time 63672751 ps
CPU time 1.48 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:43 PM PDT 24
Peak memory 197876 kb
Host smart-349fd27c-715e-475f-a519-6fd5de3eee06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568055350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.568055350
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1464863825
Short name T534
Test name
Test status
Simulation time 440320325 ps
CPU time 1.39 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 195508 kb
Host smart-5427d9ae-1e75-4db6-8730-87ecbe20ca56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464863825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1464863825
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2036230363
Short name T476
Test name
Test status
Simulation time 18319541 ps
CPU time 0.52 seconds
Started May 19 01:07:07 PM PDT 24
Finished May 19 01:07:08 PM PDT 24
Peak memory 182256 kb
Host smart-ec332c1f-a04c-444e-99c8-4b95abacfc3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036230363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2036230363
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3481183984
Short name T474
Test name
Test status
Simulation time 12884004 ps
CPU time 0.56 seconds
Started May 19 01:07:09 PM PDT 24
Finished May 19 01:07:10 PM PDT 24
Peak memory 182700 kb
Host smart-49ddc693-07a5-483a-9b35-1ce79c4ae8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481183984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3481183984
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2042584326
Short name T522
Test name
Test status
Simulation time 24232663 ps
CPU time 0.54 seconds
Started May 19 01:07:06 PM PDT 24
Finished May 19 01:07:07 PM PDT 24
Peak memory 181976 kb
Host smart-0a008f99-03ec-496f-a7c3-e6c9b69523b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042584326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2042584326
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.304046916
Short name T483
Test name
Test status
Simulation time 34083760 ps
CPU time 0.53 seconds
Started May 19 01:07:05 PM PDT 24
Finished May 19 01:07:06 PM PDT 24
Peak memory 182068 kb
Host smart-8e238a90-ed61-4b77-8096-cd032effed93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304046916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.304046916
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.186515183
Short name T456
Test name
Test status
Simulation time 10866780 ps
CPU time 0.56 seconds
Started May 19 01:07:12 PM PDT 24
Finished May 19 01:07:15 PM PDT 24
Peak memory 182264 kb
Host smart-740f7d90-a60d-47c8-b718-271f84bca40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186515183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.186515183
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2568782587
Short name T485
Test name
Test status
Simulation time 32738980 ps
CPU time 0.51 seconds
Started May 19 01:07:04 PM PDT 24
Finished May 19 01:07:06 PM PDT 24
Peak memory 182056 kb
Host smart-b9841775-3259-4807-93ac-861b63b12582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568782587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2568782587
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3789913571
Short name T464
Test name
Test status
Simulation time 14919456 ps
CPU time 0.55 seconds
Started May 19 01:07:12 PM PDT 24
Finished May 19 01:07:15 PM PDT 24
Peak memory 182340 kb
Host smart-8a746149-12be-4d37-aa1a-4cbf000c60be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789913571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3789913571
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4163182782
Short name T499
Test name
Test status
Simulation time 11998064 ps
CPU time 0.52 seconds
Started May 19 01:07:11 PM PDT 24
Finished May 19 01:07:13 PM PDT 24
Peak memory 182312 kb
Host smart-ce203622-fca8-402a-830b-58ec0f8b7e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163182782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4163182782
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3259779731
Short name T480
Test name
Test status
Simulation time 19990121 ps
CPU time 0.54 seconds
Started May 19 01:07:11 PM PDT 24
Finished May 19 01:07:14 PM PDT 24
Peak memory 182312 kb
Host smart-7db9dfcb-7fd4-427e-aca9-2498b444b754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259779731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3259779731
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2862830316
Short name T555
Test name
Test status
Simulation time 30289840 ps
CPU time 0.63 seconds
Started May 19 01:07:12 PM PDT 24
Finished May 19 01:07:15 PM PDT 24
Peak memory 182884 kb
Host smart-5c9c4fac-e4c2-431f-a0c4-419570948471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862830316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2862830316
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1963597641
Short name T573
Test name
Test status
Simulation time 117302700 ps
CPU time 0.92 seconds
Started May 19 01:06:39 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 196964 kb
Host smart-e425537b-38cf-4a93-ad52-d59ed5e5493f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963597641 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1963597641
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.640378553
Short name T561
Test name
Test status
Simulation time 46359107 ps
CPU time 0.56 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:46 PM PDT 24
Peak memory 182760 kb
Host smart-8184c693-18c2-4bee-aba7-3a3ee07709af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640378553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.640378553
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2401040582
Short name T492
Test name
Test status
Simulation time 25726143 ps
CPU time 0.52 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:46 PM PDT 24
Peak memory 182312 kb
Host smart-e27318eb-1a65-4335-ba6e-cc04ddec263c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401040582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2401040582
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3563246229
Short name T69
Test name
Test status
Simulation time 41533550 ps
CPU time 0.85 seconds
Started May 19 01:06:43 PM PDT 24
Finished May 19 01:06:44 PM PDT 24
Peak memory 193572 kb
Host smart-9ce28db2-33f8-4d22-a41f-4ec60f9d3b84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563246229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3563246229
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.965939354
Short name T472
Test name
Test status
Simulation time 125716883 ps
CPU time 2.31 seconds
Started May 19 01:06:41 PM PDT 24
Finished May 19 01:06:44 PM PDT 24
Peak memory 197648 kb
Host smart-5d2a5a63-aec0-4f88-a567-0c0dc8d81a48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965939354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.965939354
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4257585612
Short name T523
Test name
Test status
Simulation time 196700407 ps
CPU time 1.36 seconds
Started May 19 01:06:45 PM PDT 24
Finished May 19 01:06:47 PM PDT 24
Peak memory 195252 kb
Host smart-a1f1be68-263d-48ec-9a7e-8274a02bd25c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257585612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.4257585612
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.71643177
Short name T525
Test name
Test status
Simulation time 31607793 ps
CPU time 1.44 seconds
Started May 19 01:06:39 PM PDT 24
Finished May 19 01:06:41 PM PDT 24
Peak memory 197652 kb
Host smart-c76f2c48-f917-406d-8693-3e16db8400e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71643177 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.71643177
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3091515998
Short name T470
Test name
Test status
Simulation time 46197881 ps
CPU time 0.57 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 182736 kb
Host smart-c9ba48a7-e8d3-40d3-91f2-72c5e80dd1ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091515998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3091515998
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1956786871
Short name T560
Test name
Test status
Simulation time 23148472 ps
CPU time 0.53 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:46 PM PDT 24
Peak memory 182332 kb
Host smart-374574a4-f715-4943-8334-5597acea4754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956786871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1956786871
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.779855744
Short name T32
Test name
Test status
Simulation time 123001623 ps
CPU time 0.76 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:45 PM PDT 24
Peak memory 193356 kb
Host smart-e15f7366-669c-4201-bfac-d848e66371e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779855744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.779855744
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.975379769
Short name T517
Test name
Test status
Simulation time 1283222879 ps
CPU time 3.15 seconds
Started May 19 01:06:39 PM PDT 24
Finished May 19 01:06:44 PM PDT 24
Peak memory 197628 kb
Host smart-aee7501e-a878-4547-b203-f234f6b24895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975379769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.975379769
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3861429163
Short name T468
Test name
Test status
Simulation time 53992874 ps
CPU time 0.84 seconds
Started May 19 01:06:45 PM PDT 24
Finished May 19 01:06:47 PM PDT 24
Peak memory 193776 kb
Host smart-2c6140d4-b2c3-4ced-a022-7d4155027ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861429163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3861429163
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2283917282
Short name T461
Test name
Test status
Simulation time 30367886 ps
CPU time 1.33 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:43 PM PDT 24
Peak memory 197852 kb
Host smart-75f6df47-c1dd-4cdf-9f48-2321b6e8a220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283917282 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2283917282
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1228891935
Short name T481
Test name
Test status
Simulation time 43911042 ps
CPU time 0.58 seconds
Started May 19 01:06:41 PM PDT 24
Finished May 19 01:06:43 PM PDT 24
Peak memory 182740 kb
Host smart-f8beea64-a873-445a-840a-240d46fcccd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228891935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1228891935
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.712901197
Short name T524
Test name
Test status
Simulation time 81305379 ps
CPU time 0.52 seconds
Started May 19 01:06:39 PM PDT 24
Finished May 19 01:06:40 PM PDT 24
Peak memory 182120 kb
Host smart-6069c729-f272-43e5-94bd-f11d78d0c706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712901197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.712901197
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2505958461
Short name T551
Test name
Test status
Simulation time 151863850 ps
CPU time 0.77 seconds
Started May 19 01:06:43 PM PDT 24
Finished May 19 01:06:45 PM PDT 24
Peak memory 193320 kb
Host smart-a74996b8-b0e1-4906-8e51-f0202d410a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505958461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2505958461
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1256572438
Short name T563
Test name
Test status
Simulation time 68846952 ps
CPU time 1 seconds
Started May 19 01:06:43 PM PDT 24
Finished May 19 01:06:45 PM PDT 24
Peak memory 197136 kb
Host smart-89a2c474-0268-4bef-9c87-1f597c54e0a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256572438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1256572438
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3542088055
Short name T558
Test name
Test status
Simulation time 114954170 ps
CPU time 1.09 seconds
Started May 19 01:06:38 PM PDT 24
Finished May 19 01:06:40 PM PDT 24
Peak memory 183440 kb
Host smart-9ae32d82-42c9-49d0-9fd6-c526b1ef97cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542088055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3542088055
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3287630001
Short name T506
Test name
Test status
Simulation time 32328394 ps
CPU time 1.41 seconds
Started May 19 01:06:46 PM PDT 24
Finished May 19 01:06:48 PM PDT 24
Peak memory 197648 kb
Host smart-110cda74-89fa-4da0-972f-28f307a85fd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287630001 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3287630001
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4004888299
Short name T84
Test name
Test status
Simulation time 15250883 ps
CPU time 0.58 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 182764 kb
Host smart-10bcc44b-1ffe-48a1-b14e-93b819c869f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004888299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4004888299
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1398410590
Short name T454
Test name
Test status
Simulation time 51237055 ps
CPU time 0.56 seconds
Started May 19 01:06:40 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 182524 kb
Host smart-efb6c9b3-f713-4838-a377-96c7e09d5bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398410590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1398410590
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1590853689
Short name T550
Test name
Test status
Simulation time 42169203 ps
CPU time 0.81 seconds
Started May 19 01:06:45 PM PDT 24
Finished May 19 01:06:47 PM PDT 24
Peak memory 193316 kb
Host smart-6fdcaf36-66e7-4b51-83d2-dfe60612c292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590853689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1590853689
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3616433755
Short name T55
Test name
Test status
Simulation time 424556614 ps
CPU time 2.11 seconds
Started May 19 01:06:42 PM PDT 24
Finished May 19 01:06:45 PM PDT 24
Peak memory 197640 kb
Host smart-2fc59984-f782-430e-93db-3850a4f02231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616433755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3616433755
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.89628197
Short name T532
Test name
Test status
Simulation time 473358250 ps
CPU time 1.34 seconds
Started May 19 01:06:41 PM PDT 24
Finished May 19 01:06:44 PM PDT 24
Peak memory 195528 kb
Host smart-721f3696-4494-4c0f-9c88-99ae8ec03818
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89628197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg
_err.89628197
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.786535082
Short name T53
Test name
Test status
Simulation time 103994096 ps
CPU time 0.84 seconds
Started May 19 01:06:46 PM PDT 24
Finished May 19 01:06:48 PM PDT 24
Peak memory 197232 kb
Host smart-d16c7328-0d91-4254-b43b-dfc828ab903a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786535082 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.786535082
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2658973247
Short name T78
Test name
Test status
Simulation time 11211356 ps
CPU time 0.57 seconds
Started May 19 01:06:44 PM PDT 24
Finished May 19 01:06:46 PM PDT 24
Peak memory 182712 kb
Host smart-852ca581-1c36-44f0-964a-982bd4d9444f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658973247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2658973247
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4249077461
Short name T575
Test name
Test status
Simulation time 38216977 ps
CPU time 0.52 seconds
Started May 19 01:06:45 PM PDT 24
Finished May 19 01:06:47 PM PDT 24
Peak memory 182072 kb
Host smart-be69ff7d-390d-4d56-a87e-e15327b994f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249077461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4249077461
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2712769140
Short name T72
Test name
Test status
Simulation time 33247953 ps
CPU time 0.8 seconds
Started May 19 01:06:46 PM PDT 24
Finished May 19 01:06:48 PM PDT 24
Peak memory 191696 kb
Host smart-790f74dc-ac3c-42c6-b246-e886e75c7bd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712769140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2712769140
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3013211726
Short name T489
Test name
Test status
Simulation time 368520581 ps
CPU time 1.31 seconds
Started May 19 01:06:43 PM PDT 24
Finished May 19 01:06:45 PM PDT 24
Peak memory 197508 kb
Host smart-e6f75282-51f5-47c0-904d-11d6ef24c75b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013211726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3013211726
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1920381088
Short name T31
Test name
Test status
Simulation time 265741586 ps
CPU time 1.07 seconds
Started May 19 01:06:47 PM PDT 24
Finished May 19 01:06:49 PM PDT 24
Peak memory 183528 kb
Host smart-aeff2ed9-f913-4b8b-b016-6e332685063d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920381088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1920381088
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3788972637
Short name T65
Test name
Test status
Simulation time 123059566024 ps
CPU time 160.75 seconds
Started May 19 12:59:05 PM PDT 24
Finished May 19 01:01:47 PM PDT 24
Peak memory 182648 kb
Host smart-b982fb7b-7cc2-4e3a-bbf1-713404065d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788972637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3788972637
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1458468294
Short name T67
Test name
Test status
Simulation time 707941065577 ps
CPU time 526.33 seconds
Started May 19 12:59:06 PM PDT 24
Finished May 19 01:07:53 PM PDT 24
Peak memory 190764 kb
Host smart-a8d34465-a5b0-4c42-bc55-2bf577aa5fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458468294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1458468294
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.390281427
Short name T369
Test name
Test status
Simulation time 17607482574 ps
CPU time 15.78 seconds
Started May 19 12:59:05 PM PDT 24
Finished May 19 12:59:22 PM PDT 24
Peak memory 182640 kb
Host smart-35360e91-527a-426e-9d85-f65f5468e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390281427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.390281427
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2152542816
Short name T370
Test name
Test status
Simulation time 75818318096 ps
CPU time 117.85 seconds
Started May 19 12:59:05 PM PDT 24
Finished May 19 01:01:04 PM PDT 24
Peak memory 182628 kb
Host smart-89462e9a-fbdc-4a2e-950a-5f2588a931e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152542816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2152542816
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.449431888
Short name T47
Test name
Test status
Simulation time 465696297401 ps
CPU time 266.96 seconds
Started May 19 12:59:06 PM PDT 24
Finished May 19 01:03:34 PM PDT 24
Peak memory 182556 kb
Host smart-5f12212c-5439-46c9-b40d-35e53f13a88a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449431888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.449431888
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2406797407
Short name T387
Test name
Test status
Simulation time 109981504058 ps
CPU time 125.41 seconds
Started May 19 12:59:06 PM PDT 24
Finished May 19 01:01:12 PM PDT 24
Peak memory 182620 kb
Host smart-bc507b29-12f4-4db8-bb0f-8ee342c42c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406797407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2406797407
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1938948404
Short name T281
Test name
Test status
Simulation time 501215363328 ps
CPU time 258.09 seconds
Started May 19 12:59:04 PM PDT 24
Finished May 19 01:03:23 PM PDT 24
Peak memory 190812 kb
Host smart-d441fb2e-8c47-4aae-9aa4-d557cbcfe1e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938948404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1938948404
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.982438653
Short name T333
Test name
Test status
Simulation time 182199691849 ps
CPU time 74.98 seconds
Started May 19 12:59:05 PM PDT 24
Finished May 19 01:00:21 PM PDT 24
Peak memory 182656 kb
Host smart-94808878-7925-4cdc-8e89-ce614c3bd228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982438653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.982438653
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3875442868
Short name T15
Test name
Test status
Simulation time 285470394 ps
CPU time 0.76 seconds
Started May 19 12:59:06 PM PDT 24
Finished May 19 12:59:08 PM PDT 24
Peak memory 213020 kb
Host smart-8b885461-0016-44eb-984c-573c7b151641
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875442868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3875442868
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.237713926
Short name T355
Test name
Test status
Simulation time 70577168504 ps
CPU time 99.48 seconds
Started May 19 12:59:24 PM PDT 24
Finished May 19 01:01:04 PM PDT 24
Peak memory 182648 kb
Host smart-f6c43b76-12df-47b0-a76a-d630e2fcff66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237713926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.237713926
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3870845934
Short name T237
Test name
Test status
Simulation time 309580472286 ps
CPU time 127.17 seconds
Started May 19 12:59:21 PM PDT 24
Finished May 19 01:01:30 PM PDT 24
Peak memory 190828 kb
Host smart-af04332b-7e60-4220-9cd6-3ed9e9515d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870845934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3870845934
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1369079220
Short name T39
Test name
Test status
Simulation time 111705633793 ps
CPU time 721.57 seconds
Started May 19 12:59:23 PM PDT 24
Finished May 19 01:11:25 PM PDT 24
Peak memory 205492 kb
Host smart-1e933bfe-638a-4052-aaa2-d0a0c051f8fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369079220 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1369079220
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.1775324079
Short name T49
Test name
Test status
Simulation time 83149850475 ps
CPU time 439.54 seconds
Started May 19 01:01:19 PM PDT 24
Finished May 19 01:08:39 PM PDT 24
Peak memory 190760 kb
Host smart-c3da4bb3-7fe0-4322-8fe2-063dd4e9850e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775324079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1775324079
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.753110583
Short name T1
Test name
Test status
Simulation time 37053875248 ps
CPU time 156.52 seconds
Started May 19 01:01:14 PM PDT 24
Finished May 19 01:03:51 PM PDT 24
Peak memory 190804 kb
Host smart-fd8ce7d1-27e1-4798-af16-53f81c27b2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753110583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.753110583
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.134278588
Short name T6
Test name
Test status
Simulation time 154026820820 ps
CPU time 394.2 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:07:58 PM PDT 24
Peak memory 191100 kb
Host smart-5e9144c0-2f85-4746-b9d5-d3eab03ed302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134278588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.134278588
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2016590954
Short name T351
Test name
Test status
Simulation time 42967492937 ps
CPU time 23.54 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:01:48 PM PDT 24
Peak memory 182888 kb
Host smart-ebecb09a-d804-418f-9a4c-06fa449f03dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016590954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2016590954
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1923541882
Short name T193
Test name
Test status
Simulation time 28558673869 ps
CPU time 44.79 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:02:09 PM PDT 24
Peak memory 182896 kb
Host smart-65528be5-43df-4162-9fd1-5b8d9d3faee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923541882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1923541882
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2454711702
Short name T352
Test name
Test status
Simulation time 46541535834 ps
CPU time 87.11 seconds
Started May 19 01:01:17 PM PDT 24
Finished May 19 01:02:45 PM PDT 24
Peak memory 182608 kb
Host smart-39e605bc-d3a6-4090-84d8-c4c46c0ed207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454711702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2454711702
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3351474057
Short name T184
Test name
Test status
Simulation time 970964059430 ps
CPU time 2181.49 seconds
Started May 19 01:01:18 PM PDT 24
Finished May 19 01:37:41 PM PDT 24
Peak memory 193244 kb
Host smart-e3e52e2e-e998-4e1a-abb0-1741b3832110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351474057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3351474057
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3434020938
Short name T342
Test name
Test status
Simulation time 1021237100781 ps
CPU time 560.41 seconds
Started May 19 12:59:29 PM PDT 24
Finished May 19 01:08:50 PM PDT 24
Peak memory 182652 kb
Host smart-616fdb1f-9a26-4767-957a-12269b3dd216
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434020938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3434020938
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.4052491534
Short name T395
Test name
Test status
Simulation time 361820563372 ps
CPU time 168.85 seconds
Started May 19 12:59:21 PM PDT 24
Finished May 19 01:02:11 PM PDT 24
Peak memory 182608 kb
Host smart-943e6c9b-a15e-4649-85cd-01859e4733bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052491534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4052491534
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.888852190
Short name T180
Test name
Test status
Simulation time 257136205419 ps
CPU time 378.32 seconds
Started May 19 12:59:32 PM PDT 24
Finished May 19 01:05:51 PM PDT 24
Peak memory 190832 kb
Host smart-c1a2b5d9-30ff-4b09-a152-bcb7555b8267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888852190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.888852190
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3631030082
Short name T450
Test name
Test status
Simulation time 40452879284 ps
CPU time 65.18 seconds
Started May 19 12:59:23 PM PDT 24
Finished May 19 01:00:29 PM PDT 24
Peak memory 190848 kb
Host smart-9dff0bc5-6b84-4071-962b-ba240e1e6710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631030082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3631030082
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.220842158
Short name T112
Test name
Test status
Simulation time 92550552598 ps
CPU time 41.28 seconds
Started May 19 01:01:18 PM PDT 24
Finished May 19 01:02:00 PM PDT 24
Peak memory 190792 kb
Host smart-425c9c70-5042-496f-98dc-a92562f49319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220842158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.220842158
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1572545678
Short name T425
Test name
Test status
Simulation time 374607899707 ps
CPU time 1134.36 seconds
Started May 19 01:01:19 PM PDT 24
Finished May 19 01:20:14 PM PDT 24
Peak memory 190824 kb
Host smart-886ddc34-4752-47ec-bbbc-d91cfa5a9c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572545678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1572545678
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3098128558
Short name T247
Test name
Test status
Simulation time 173494935660 ps
CPU time 107.19 seconds
Started May 19 01:01:19 PM PDT 24
Finished May 19 01:03:07 PM PDT 24
Peak memory 190848 kb
Host smart-26c19895-1ffa-450b-9286-b55e66207cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098128558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3098128558
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2012630796
Short name T186
Test name
Test status
Simulation time 191427505516 ps
CPU time 206.1 seconds
Started May 19 01:01:22 PM PDT 24
Finished May 19 01:04:49 PM PDT 24
Peak memory 190824 kb
Host smart-8ccb208e-2ee9-4b6f-a754-49f0cf12d36f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012630796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2012630796
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.672760558
Short name T4
Test name
Test status
Simulation time 214405454048 ps
CPU time 339.18 seconds
Started May 19 12:59:25 PM PDT 24
Finished May 19 01:05:05 PM PDT 24
Peak memory 182644 kb
Host smart-1df33e11-0064-4b37-89a8-2a7376ee4133
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672760558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.672760558
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.4049733908
Short name T362
Test name
Test status
Simulation time 74999861967 ps
CPU time 49.35 seconds
Started May 19 12:59:25 PM PDT 24
Finished May 19 01:00:15 PM PDT 24
Peak memory 182568 kb
Host smart-3f3374ff-6d15-46a6-8e8d-1eab39c38163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049733908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.4049733908
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.804378561
Short name T125
Test name
Test status
Simulation time 71253603444 ps
CPU time 108.98 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 01:01:18 PM PDT 24
Peak memory 194656 kb
Host smart-108ed905-5e6a-4d06-8d22-243a5bca835f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804378561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.804378561
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3734559297
Short name T448
Test name
Test status
Simulation time 436923232316 ps
CPU time 185.38 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 01:02:34 PM PDT 24
Peak memory 182640 kb
Host smart-a11640a1-d2ff-4cce-b23f-3443bfbad3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734559297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3734559297
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.298947811
Short name T230
Test name
Test status
Simulation time 417976234719 ps
CPU time 247.8 seconds
Started May 19 01:01:23 PM PDT 24
Finished May 19 01:05:32 PM PDT 24
Peak memory 190836 kb
Host smart-111e603a-75e1-44bb-9390-2d7ec0faaed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298947811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.298947811
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3209522569
Short name T327
Test name
Test status
Simulation time 501640160500 ps
CPU time 1786.44 seconds
Started May 19 01:01:22 PM PDT 24
Finished May 19 01:31:10 PM PDT 24
Peak memory 192572 kb
Host smart-076e25e1-10df-4dde-bc18-a085853eb082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209522569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3209522569
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1742263805
Short name T239
Test name
Test status
Simulation time 346131355797 ps
CPU time 201.55 seconds
Started May 19 01:01:24 PM PDT 24
Finished May 19 01:04:46 PM PDT 24
Peak memory 190824 kb
Host smart-772bec3e-6574-4e7b-ad85-9a6824e57b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742263805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1742263805
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2513234192
Short name T446
Test name
Test status
Simulation time 31533592701 ps
CPU time 53.45 seconds
Started May 19 01:01:31 PM PDT 24
Finished May 19 01:02:25 PM PDT 24
Peak memory 182616 kb
Host smart-ce157f69-b507-4757-825f-817a7df30027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513234192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2513234192
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3944185429
Short name T169
Test name
Test status
Simulation time 320142852690 ps
CPU time 518.26 seconds
Started May 19 01:01:36 PM PDT 24
Finished May 19 01:10:15 PM PDT 24
Peak memory 191096 kb
Host smart-0496e364-7d2f-480a-a596-abad5ed34683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944185429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3944185429
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1809983537
Short name T348
Test name
Test status
Simulation time 188798182095 ps
CPU time 483.97 seconds
Started May 19 01:01:31 PM PDT 24
Finished May 19 01:09:35 PM PDT 24
Peak memory 190812 kb
Host smart-baf53c40-60da-4933-8200-d33f31f1394c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809983537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1809983537
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1321531952
Short name T289
Test name
Test status
Simulation time 327967182275 ps
CPU time 1974.03 seconds
Started May 19 01:01:36 PM PDT 24
Finished May 19 01:34:31 PM PDT 24
Peak memory 191096 kb
Host smart-37d7646b-64b2-46f3-8c1e-13adb455b824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321531952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1321531952
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.231441765
Short name T229
Test name
Test status
Simulation time 10110047800 ps
CPU time 18.18 seconds
Started May 19 12:59:26 PM PDT 24
Finished May 19 12:59:45 PM PDT 24
Peak memory 182652 kb
Host smart-4daec878-4a58-4cf3-9fbf-36551737c31f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231441765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.231441765
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2901965673
Short name T354
Test name
Test status
Simulation time 55837041188 ps
CPU time 80.49 seconds
Started May 19 12:59:25 PM PDT 24
Finished May 19 01:00:46 PM PDT 24
Peak memory 182648 kb
Host smart-399cbf7a-176f-41e7-a829-7c3475ac8f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901965673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2901965673
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.706429381
Short name T339
Test name
Test status
Simulation time 65538554107 ps
CPU time 121.66 seconds
Started May 19 12:59:24 PM PDT 24
Finished May 19 01:01:27 PM PDT 24
Peak memory 190820 kb
Host smart-b3f164d2-ab4f-49c4-a256-6f29063078bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706429381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.706429381
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.604133983
Short name T417
Test name
Test status
Simulation time 174363143601 ps
CPU time 146.7 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 01:01:56 PM PDT 24
Peak memory 182604 kb
Host smart-fbbce382-318e-461e-b39e-1325ad5bad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604133983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.604133983
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2803795502
Short name T3
Test name
Test status
Simulation time 18447146 ps
CPU time 0.55 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 12:59:30 PM PDT 24
Peak memory 182368 kb
Host smart-854f40de-9061-4a7e-aee4-21b7b1d7e4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803795502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2803795502
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.1822354817
Short name T210
Test name
Test status
Simulation time 110707515364 ps
CPU time 915.17 seconds
Started May 19 01:01:30 PM PDT 24
Finished May 19 01:16:45 PM PDT 24
Peak memory 194140 kb
Host smart-0829e49a-8e1f-48b6-9ec6-b04c8faf1d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822354817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1822354817
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3044674289
Short name T206
Test name
Test status
Simulation time 268216508991 ps
CPU time 171.17 seconds
Started May 19 01:01:30 PM PDT 24
Finished May 19 01:04:22 PM PDT 24
Peak memory 190700 kb
Host smart-69578776-3ed3-4baa-b935-c92b201bd488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044674289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3044674289
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3306080784
Short name T205
Test name
Test status
Simulation time 740509130987 ps
CPU time 538.78 seconds
Started May 19 01:01:32 PM PDT 24
Finished May 19 01:10:31 PM PDT 24
Peak memory 194080 kb
Host smart-0f70391b-8653-4181-914e-410dfe5c60c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306080784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3306080784
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2817216307
Short name T444
Test name
Test status
Simulation time 27795486345 ps
CPU time 337.18 seconds
Started May 19 01:01:36 PM PDT 24
Finished May 19 01:07:14 PM PDT 24
Peak memory 182620 kb
Host smart-45904612-7490-473c-8b62-d62ecceba667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817216307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2817216307
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2486078432
Short name T265
Test name
Test status
Simulation time 581353568495 ps
CPU time 331.6 seconds
Started May 19 01:01:35 PM PDT 24
Finished May 19 01:07:07 PM PDT 24
Peak memory 190768 kb
Host smart-b4a8ca58-266c-4c45-b1c6-aa4b80972c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486078432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2486078432
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3367093710
Short name T275
Test name
Test status
Simulation time 326692825714 ps
CPU time 158.23 seconds
Started May 19 01:01:36 PM PDT 24
Finished May 19 01:04:14 PM PDT 24
Peak memory 190812 kb
Host smart-fae6361b-51e3-4978-a3a7-ed8d84833fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367093710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3367093710
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.8728440
Short name T116
Test name
Test status
Simulation time 471631485098 ps
CPU time 740.06 seconds
Started May 19 01:01:37 PM PDT 24
Finished May 19 01:13:58 PM PDT 24
Peak memory 194196 kb
Host smart-92e5e750-cb5f-4d47-8ebf-c58f3d77823c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8728440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.8728440
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2789933507
Short name T252
Test name
Test status
Simulation time 115905770647 ps
CPU time 296.4 seconds
Started May 19 01:01:36 PM PDT 24
Finished May 19 01:06:33 PM PDT 24
Peak memory 190780 kb
Host smart-34420c7d-e725-4fee-95bc-ff23a5d969fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789933507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2789933507
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.806030816
Short name T260
Test name
Test status
Simulation time 4807586310 ps
CPU time 9.6 seconds
Started May 19 12:59:27 PM PDT 24
Finished May 19 12:59:37 PM PDT 24
Peak memory 182640 kb
Host smart-0e591556-e375-4319-a440-66c8488a1e8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806030816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.806030816
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2596165858
Short name T427
Test name
Test status
Simulation time 300888882362 ps
CPU time 48.85 seconds
Started May 19 12:59:29 PM PDT 24
Finished May 19 01:00:18 PM PDT 24
Peak memory 182656 kb
Host smart-02328838-d38e-4e68-b7f9-9fe9b08bea73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596165858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2596165858
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3734055000
Short name T14
Test name
Test status
Simulation time 112361443925 ps
CPU time 298.55 seconds
Started May 19 12:59:29 PM PDT 24
Finished May 19 01:04:28 PM PDT 24
Peak memory 197244 kb
Host smart-a48c6cdf-e26e-403f-954a-3799c073732c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734055000 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3734055000
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.rv_timer_random.200047568
Short name T227
Test name
Test status
Simulation time 537681776447 ps
CPU time 189.02 seconds
Started May 19 01:01:38 PM PDT 24
Finished May 19 01:04:47 PM PDT 24
Peak memory 191100 kb
Host smart-2ff5bb4f-3545-478d-b77e-85485f28c745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200047568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.200047568
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.866113698
Short name T331
Test name
Test status
Simulation time 168485425192 ps
CPU time 91.3 seconds
Started May 19 01:01:34 PM PDT 24
Finished May 19 01:03:06 PM PDT 24
Peak memory 190828 kb
Host smart-24060b5d-0f1d-4bf9-95a7-1d58cf51da85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866113698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.866113698
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2779737681
Short name T315
Test name
Test status
Simulation time 39284965048 ps
CPU time 64.86 seconds
Started May 19 01:01:35 PM PDT 24
Finished May 19 01:02:41 PM PDT 24
Peak memory 182608 kb
Host smart-8dd56b9d-a455-4c8e-88f0-5a348d6aad9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779737681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2779737681
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2424067359
Short name T410
Test name
Test status
Simulation time 101996668645 ps
CPU time 60.18 seconds
Started May 19 01:01:34 PM PDT 24
Finished May 19 01:02:35 PM PDT 24
Peak memory 182640 kb
Host smart-13153e55-bef5-4141-993d-6525e4fd7d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424067359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2424067359
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2676024393
Short name T212
Test name
Test status
Simulation time 579438284556 ps
CPU time 1739.33 seconds
Started May 19 01:01:41 PM PDT 24
Finished May 19 01:30:41 PM PDT 24
Peak memory 190808 kb
Host smart-2abbfbb4-fc39-4f52-a2b6-31bca605756b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676024393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2676024393
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2794617039
Short name T188
Test name
Test status
Simulation time 844068912935 ps
CPU time 357.24 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 01:05:27 PM PDT 24
Peak memory 182652 kb
Host smart-97aa3f05-7789-4fc5-a0ed-2ef4ccd93beb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794617039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2794617039
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1945349123
Short name T447
Test name
Test status
Simulation time 456464973057 ps
CPU time 169.08 seconds
Started May 19 12:59:27 PM PDT 24
Finished May 19 01:02:17 PM PDT 24
Peak memory 182648 kb
Host smart-33815cf6-7d12-4128-a3dd-acbc479523f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945349123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1945349123
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1020948677
Short name T110
Test name
Test status
Simulation time 59835731351 ps
CPU time 100.43 seconds
Started May 19 12:59:26 PM PDT 24
Finished May 19 01:01:07 PM PDT 24
Peak memory 182636 kb
Host smart-d1b3b37c-a1a2-4e10-aa0e-74889c997d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020948677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1020948677
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.4178975649
Short name T347
Test name
Test status
Simulation time 331135708077 ps
CPU time 198.19 seconds
Started May 19 12:59:27 PM PDT 24
Finished May 19 01:02:45 PM PDT 24
Peak memory 190840 kb
Host smart-a5817460-09ca-4e3d-9a7a-ebee48d820dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178975649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.4178975649
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.4212873147
Short name T377
Test name
Test status
Simulation time 33376019 ps
CPU time 0.57 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 12:59:29 PM PDT 24
Peak memory 182308 kb
Host smart-62e516c7-c528-4f9b-bdf5-e5cf2ac683fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212873147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.4212873147
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1154372895
Short name T179
Test name
Test status
Simulation time 104285605294 ps
CPU time 159.09 seconds
Started May 19 01:01:39 PM PDT 24
Finished May 19 01:04:19 PM PDT 24
Peak memory 194428 kb
Host smart-219e15b8-56cf-420b-9081-3da2066b052b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154372895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1154372895
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.70869804
Short name T248
Test name
Test status
Simulation time 254861003278 ps
CPU time 291.91 seconds
Started May 19 01:01:41 PM PDT 24
Finished May 19 01:06:33 PM PDT 24
Peak memory 190816 kb
Host smart-d0cb3e3e-4560-4993-aaea-63333b3d13ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70869804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.70869804
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2584664863
Short name T443
Test name
Test status
Simulation time 62252441478 ps
CPU time 100.95 seconds
Started May 19 01:01:42 PM PDT 24
Finished May 19 01:03:24 PM PDT 24
Peak memory 194472 kb
Host smart-97b64ac7-5af5-4549-97f2-cd8c0655831d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584664863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2584664863
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3082555473
Short name T236
Test name
Test status
Simulation time 536630817649 ps
CPU time 231.07 seconds
Started May 19 01:01:43 PM PDT 24
Finished May 19 01:05:35 PM PDT 24
Peak memory 190804 kb
Host smart-652eb75e-7fc9-4fff-8d3e-6df01421dfe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082555473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3082555473
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3195060261
Short name T160
Test name
Test status
Simulation time 210997219559 ps
CPU time 537.39 seconds
Started May 19 01:01:40 PM PDT 24
Finished May 19 01:10:37 PM PDT 24
Peak memory 190824 kb
Host smart-6aa42f7b-d8d3-48c8-93bd-bb80db1dfa20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195060261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3195060261
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.930781998
Short name T126
Test name
Test status
Simulation time 157453969084 ps
CPU time 149.19 seconds
Started May 19 01:01:48 PM PDT 24
Finished May 19 01:04:18 PM PDT 24
Peak memory 190852 kb
Host smart-55e68ef2-ca50-43bf-92d5-013c5ede8584
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930781998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.930781998
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.372001327
Short name T46
Test name
Test status
Simulation time 206053968004 ps
CPU time 204.07 seconds
Started May 19 01:01:47 PM PDT 24
Finished May 19 01:05:12 PM PDT 24
Peak memory 190732 kb
Host smart-98eb0810-5941-4b6d-8ec4-8480a083ffc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372001327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.372001327
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.104703204
Short name T405
Test name
Test status
Simulation time 57475290336 ps
CPU time 246.62 seconds
Started May 19 01:01:48 PM PDT 24
Finished May 19 01:05:56 PM PDT 24
Peak memory 190836 kb
Host smart-17ec5ca0-e8ed-47d9-beb7-1418b2974281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104703204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.104703204
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2217831520
Short name T319
Test name
Test status
Simulation time 69433552230 ps
CPU time 748.91 seconds
Started May 19 01:01:48 PM PDT 24
Finished May 19 01:14:17 PM PDT 24
Peak memory 190840 kb
Host smart-aeb7b4b3-813f-40f7-8c93-14a715322112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217831520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2217831520
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.291489221
Short name T128
Test name
Test status
Simulation time 257623410363 ps
CPU time 410.04 seconds
Started May 19 12:59:28 PM PDT 24
Finished May 19 01:06:19 PM PDT 24
Peak memory 182644 kb
Host smart-19d02bf9-dda7-418f-a00e-44237d3483a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291489221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.291489221
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3790401712
Short name T385
Test name
Test status
Simulation time 160640903914 ps
CPU time 234.23 seconds
Started May 19 12:59:26 PM PDT 24
Finished May 19 01:03:21 PM PDT 24
Peak memory 182624 kb
Host smart-0a57d23f-8a05-482b-88d4-8f2067e69e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790401712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3790401712
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1008975364
Short name T436
Test name
Test status
Simulation time 85734853 ps
CPU time 1.07 seconds
Started May 19 12:59:33 PM PDT 24
Finished May 19 12:59:35 PM PDT 24
Peak memory 182576 kb
Host smart-2c20eb61-35e7-40fc-94de-fc89984dc14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008975364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1008975364
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.4124392251
Short name T271
Test name
Test status
Simulation time 2442374660413 ps
CPU time 1129.56 seconds
Started May 19 12:59:27 PM PDT 24
Finished May 19 01:18:18 PM PDT 24
Peak memory 190812 kb
Host smart-a03e73af-7c50-4d74-8237-6a81dd6f5540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124392251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.4124392251
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.147513265
Short name T22
Test name
Test status
Simulation time 234490837232 ps
CPU time 188.58 seconds
Started May 19 01:01:55 PM PDT 24
Finished May 19 01:05:04 PM PDT 24
Peak memory 190832 kb
Host smart-28060abb-fafb-40c9-8058-16a60d203569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147513265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.147513265
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.144406997
Short name T336
Test name
Test status
Simulation time 15449564216 ps
CPU time 66.33 seconds
Started May 19 01:01:48 PM PDT 24
Finished May 19 01:02:55 PM PDT 24
Peak memory 190804 kb
Host smart-f4e81e60-5d3a-48e6-9fd0-8e24aa4640ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144406997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.144406997
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.648069679
Short name T394
Test name
Test status
Simulation time 10327120537 ps
CPU time 16.04 seconds
Started May 19 01:01:49 PM PDT 24
Finished May 19 01:02:06 PM PDT 24
Peak memory 182596 kb
Host smart-77c49288-c870-4db8-989f-aa589c703784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648069679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.648069679
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2953519325
Short name T135
Test name
Test status
Simulation time 128222185512 ps
CPU time 443.75 seconds
Started May 19 01:01:48 PM PDT 24
Finished May 19 01:09:12 PM PDT 24
Peak memory 190808 kb
Host smart-db1d0e23-da34-412a-81db-e550c8cb5e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953519325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2953519325
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.4161489502
Short name T344
Test name
Test status
Simulation time 69607243739 ps
CPU time 99.9 seconds
Started May 19 01:01:47 PM PDT 24
Finished May 19 01:03:28 PM PDT 24
Peak memory 190824 kb
Host smart-1b50c205-11bc-414e-bbd4-340188a7531d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161489502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.4161489502
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1542927101
Short name T349
Test name
Test status
Simulation time 97009021924 ps
CPU time 46.94 seconds
Started May 19 01:01:54 PM PDT 24
Finished May 19 01:02:41 PM PDT 24
Peak memory 182580 kb
Host smart-adae6b5b-a5e3-4157-a84c-20296582e4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542927101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1542927101
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3142286455
Short name T403
Test name
Test status
Simulation time 27722688523 ps
CPU time 24.7 seconds
Started May 19 12:59:30 PM PDT 24
Finished May 19 12:59:55 PM PDT 24
Peak memory 182592 kb
Host smart-8292b587-8d72-4829-93b3-46bc6d6da6fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142286455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3142286455
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1982058659
Short name T439
Test name
Test status
Simulation time 354999295332 ps
CPU time 142.03 seconds
Started May 19 12:59:33 PM PDT 24
Finished May 19 01:01:56 PM PDT 24
Peak memory 182648 kb
Host smart-832d29c1-53f5-491d-8ea8-6983ed795ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982058659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1982058659
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.627421224
Short name T435
Test name
Test status
Simulation time 129226335324 ps
CPU time 67.49 seconds
Started May 19 12:59:35 PM PDT 24
Finished May 19 01:00:44 PM PDT 24
Peak memory 190768 kb
Host smart-77e72c5d-8229-4739-94fa-6e27f2241924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627421224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.627421224
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1022738723
Short name T59
Test name
Test status
Simulation time 110380671996 ps
CPU time 156.35 seconds
Started May 19 12:59:31 PM PDT 24
Finished May 19 01:02:08 PM PDT 24
Peak memory 193424 kb
Host smart-9bcca2a2-459c-4998-9845-2e815dc132f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022738723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1022738723
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.1879320470
Short name T217
Test name
Test status
Simulation time 16031065482 ps
CPU time 13.48 seconds
Started May 19 01:01:52 PM PDT 24
Finished May 19 01:02:06 PM PDT 24
Peak memory 182624 kb
Host smart-4fdab687-7e88-4ff2-87d9-d1c36ca469b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879320470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1879320470
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1434951578
Short name T288
Test name
Test status
Simulation time 25708678689 ps
CPU time 40.03 seconds
Started May 19 01:01:52 PM PDT 24
Finished May 19 01:02:32 PM PDT 24
Peak memory 182584 kb
Host smart-9660187f-ac44-415b-b330-85f24ff4b8d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434951578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1434951578
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3356147392
Short name T20
Test name
Test status
Simulation time 76432429598 ps
CPU time 542.76 seconds
Started May 19 01:01:52 PM PDT 24
Finished May 19 01:10:55 PM PDT 24
Peak memory 190796 kb
Host smart-2c2c0ac2-5b90-415f-8a81-9ab7130ac738
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356147392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3356147392
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3005277391
Short name T240
Test name
Test status
Simulation time 133860679815 ps
CPU time 157.11 seconds
Started May 19 01:01:54 PM PDT 24
Finished May 19 01:04:31 PM PDT 24
Peak memory 190820 kb
Host smart-bda3dc96-d462-4fa1-b42b-05d359850d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005277391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3005277391
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2088715812
Short name T269
Test name
Test status
Simulation time 2407931063935 ps
CPU time 2623.89 seconds
Started May 19 01:01:54 PM PDT 24
Finished May 19 01:45:39 PM PDT 24
Peak memory 190828 kb
Host smart-123e0b71-d71d-41be-b569-1012707630ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088715812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2088715812
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2701052190
Short name T154
Test name
Test status
Simulation time 437288516527 ps
CPU time 274.69 seconds
Started May 19 01:01:53 PM PDT 24
Finished May 19 01:06:28 PM PDT 24
Peak memory 182648 kb
Host smart-8dee55b8-3c2c-429e-876f-7232cb61a437
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701052190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2701052190
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3053984969
Short name T24
Test name
Test status
Simulation time 312045629753 ps
CPU time 526.02 seconds
Started May 19 01:02:02 PM PDT 24
Finished May 19 01:10:48 PM PDT 24
Peak memory 190820 kb
Host smart-6a304f69-44e7-4dfc-b2b9-ecadb2d34488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053984969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3053984969
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1427912662
Short name T287
Test name
Test status
Simulation time 286498803485 ps
CPU time 282.02 seconds
Started May 19 12:59:31 PM PDT 24
Finished May 19 01:04:14 PM PDT 24
Peak memory 182580 kb
Host smart-0c9aae62-37f1-4b0e-8ff7-01acd1b20307
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427912662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1427912662
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.523095051
Short name T368
Test name
Test status
Simulation time 86261774770 ps
CPU time 69.47 seconds
Started May 19 12:59:31 PM PDT 24
Finished May 19 01:00:41 PM PDT 24
Peak memory 182576 kb
Host smart-81a79f41-ba82-4312-9b5a-cca232683a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523095051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.523095051
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.457598881
Short name T176
Test name
Test status
Simulation time 191337245004 ps
CPU time 144.27 seconds
Started May 19 12:59:31 PM PDT 24
Finished May 19 01:01:56 PM PDT 24
Peak memory 194212 kb
Host smart-09cbc1cb-deb1-472a-820a-221fb58c843e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457598881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.457598881
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.256806595
Short name T111
Test name
Test status
Simulation time 122792694668 ps
CPU time 415.62 seconds
Started May 19 01:02:00 PM PDT 24
Finished May 19 01:08:57 PM PDT 24
Peak memory 190836 kb
Host smart-d4076bef-c968-4f4f-8602-e551e20332a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256806595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.256806595
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2173193209
Short name T149
Test name
Test status
Simulation time 59365644068 ps
CPU time 27.05 seconds
Started May 19 01:01:57 PM PDT 24
Finished May 19 01:02:25 PM PDT 24
Peak memory 190784 kb
Host smart-5655910e-d074-4a36-8221-059017bdd348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173193209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2173193209
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2843384467
Short name T214
Test name
Test status
Simulation time 302538249528 ps
CPU time 367.8 seconds
Started May 19 01:01:58 PM PDT 24
Finished May 19 01:08:07 PM PDT 24
Peak memory 190720 kb
Host smart-80ccba0f-0bcc-496c-8ebb-08597ad4191d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843384467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2843384467
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1091307602
Short name T164
Test name
Test status
Simulation time 44519733058 ps
CPU time 69.6 seconds
Started May 19 01:01:57 PM PDT 24
Finished May 19 01:03:07 PM PDT 24
Peak memory 182496 kb
Host smart-342b80fb-2ea1-4ef0-aeff-bc387d69fc29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091307602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1091307602
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2328546864
Short name T197
Test name
Test status
Simulation time 141586157587 ps
CPU time 732.39 seconds
Started May 19 01:01:59 PM PDT 24
Finished May 19 01:14:12 PM PDT 24
Peak memory 190776 kb
Host smart-c6a0afca-2da2-4459-a0c3-518583dcc063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328546864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2328546864
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.778058135
Short name T122
Test name
Test status
Simulation time 1378844989176 ps
CPU time 1113.24 seconds
Started May 19 01:01:58 PM PDT 24
Finished May 19 01:20:32 PM PDT 24
Peak memory 190812 kb
Host smart-ff0017d6-be19-4969-aec3-e28e00d176a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778058135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.778058135
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1083668202
Short name T308
Test name
Test status
Simulation time 157462021616 ps
CPU time 267.98 seconds
Started May 19 01:01:59 PM PDT 24
Finished May 19 01:06:28 PM PDT 24
Peak memory 190800 kb
Host smart-f864153d-4495-4f67-98e0-e68f07ef33a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083668202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1083668202
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3186142246
Short name T194
Test name
Test status
Simulation time 414835951255 ps
CPU time 176.31 seconds
Started May 19 01:01:59 PM PDT 24
Finished May 19 01:04:56 PM PDT 24
Peak memory 194324 kb
Host smart-55f5fd63-e06b-49ef-8a9f-a874088d679a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186142246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3186142246
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2233769778
Short name T207
Test name
Test status
Simulation time 46494062449 ps
CPU time 85.55 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:01:01 PM PDT 24
Peak memory 182652 kb
Host smart-16d8821a-f89f-436a-bbea-d5ac28ef8ddb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233769778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2233769778
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1771850759
Short name T396
Test name
Test status
Simulation time 129103150433 ps
CPU time 84.4 seconds
Started May 19 12:59:31 PM PDT 24
Finished May 19 01:00:57 PM PDT 24
Peak memory 182648 kb
Host smart-dde9be21-cba6-4c8e-8615-2545bbf5c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771850759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1771850759
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1298658325
Short name T48
Test name
Test status
Simulation time 264551709806 ps
CPU time 280.98 seconds
Started May 19 12:59:31 PM PDT 24
Finished May 19 01:04:13 PM PDT 24
Peak memory 190844 kb
Host smart-830c7897-4450-47d8-aa85-340c02efbdec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298658325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1298658325
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2141733981
Short name T66
Test name
Test status
Simulation time 47415444865 ps
CPU time 77.09 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:00:52 PM PDT 24
Peak memory 182624 kb
Host smart-4136292d-f880-4b7b-978e-09143333272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141733981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2141733981
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/191.rv_timer_random.1703145601
Short name T196
Test name
Test status
Simulation time 606312482123 ps
CPU time 411.48 seconds
Started May 19 01:01:58 PM PDT 24
Finished May 19 01:08:50 PM PDT 24
Peak memory 190768 kb
Host smart-cc047ec3-d5c6-47f6-b6f7-d449c3f2050c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703145601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1703145601
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3579478349
Short name T263
Test name
Test status
Simulation time 190870787624 ps
CPU time 278.54 seconds
Started May 19 01:01:58 PM PDT 24
Finished May 19 01:06:37 PM PDT 24
Peak memory 190804 kb
Host smart-a88916bd-72fe-489a-abbc-ba74a85d2572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579478349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3579478349
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2674397274
Short name T132
Test name
Test status
Simulation time 657660615465 ps
CPU time 1075.62 seconds
Started May 19 01:02:02 PM PDT 24
Finished May 19 01:19:58 PM PDT 24
Peak memory 190820 kb
Host smart-7270abbd-51e4-45a4-9582-cd75829d2989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674397274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2674397274
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4184324197
Short name T244
Test name
Test status
Simulation time 79250897926 ps
CPU time 156.55 seconds
Started May 19 01:02:04 PM PDT 24
Finished May 19 01:04:41 PM PDT 24
Peak memory 191144 kb
Host smart-133c6a90-cac0-4d10-aee1-74bb18fecd3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184324197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4184324197
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3334913463
Short name T114
Test name
Test status
Simulation time 79396913223 ps
CPU time 765.19 seconds
Started May 19 01:02:04 PM PDT 24
Finished May 19 01:14:50 PM PDT 24
Peak memory 190840 kb
Host smart-f39560e3-3478-481d-9c81-11f1407bcaaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334913463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3334913463
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.89260595
Short name T121
Test name
Test status
Simulation time 513473629036 ps
CPU time 206.49 seconds
Started May 19 01:02:06 PM PDT 24
Finished May 19 01:05:33 PM PDT 24
Peak memory 190816 kb
Host smart-be16f08e-30e9-46e0-b721-1ca887b3d97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89260595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.89260595
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.4143119719
Short name T270
Test name
Test status
Simulation time 325483247309 ps
CPU time 271.57 seconds
Started May 19 12:59:04 PM PDT 24
Finished May 19 01:03:37 PM PDT 24
Peak memory 182580 kb
Host smart-1fdbd8c1-4601-45a1-96a2-4e8a999c6f60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143119719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.4143119719
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3236902535
Short name T432
Test name
Test status
Simulation time 134290862258 ps
CPU time 192.27 seconds
Started May 19 12:59:05 PM PDT 24
Finished May 19 01:02:19 PM PDT 24
Peak memory 182648 kb
Host smart-d8db0450-bc11-4e61-ab48-f1891d44f4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236902535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3236902535
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1749792560
Short name T332
Test name
Test status
Simulation time 281404938358 ps
CPU time 77.15 seconds
Started May 19 12:59:16 PM PDT 24
Finished May 19 01:00:35 PM PDT 24
Peak memory 182620 kb
Host smart-99eaf204-c6c7-45c2-b701-fff0b6fdb531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749792560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1749792560
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2476605372
Short name T19
Test name
Test status
Simulation time 271058419 ps
CPU time 0.84 seconds
Started May 19 12:59:08 PM PDT 24
Finished May 19 12:59:10 PM PDT 24
Peak memory 213736 kb
Host smart-65e09617-9738-47aa-9fd5-a5c9082328b6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476605372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2476605372
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1011185661
Short name T381
Test name
Test status
Simulation time 41444387 ps
CPU time 0.66 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 12:59:18 PM PDT 24
Peak memory 182336 kb
Host smart-4ee59a85-c1e3-4ee2-adf7-92bbce84ec82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011185661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1011185661
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2681107033
Short name T13
Test name
Test status
Simulation time 90999750267 ps
CPU time 380.02 seconds
Started May 19 12:59:09 PM PDT 24
Finished May 19 01:05:30 PM PDT 24
Peak memory 197180 kb
Host smart-4ed4b5fe-c9aa-46d7-99d5-5fd2b7962875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681107033 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2681107033
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1985440302
Short name T178
Test name
Test status
Simulation time 297876470997 ps
CPU time 110.08 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:01:26 PM PDT 24
Peak memory 182660 kb
Host smart-3efe55b4-ffbb-48b2-8aba-c9194a240c33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985440302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1985440302
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.416286885
Short name T380
Test name
Test status
Simulation time 77471844177 ps
CPU time 125.01 seconds
Started May 19 12:59:32 PM PDT 24
Finished May 19 01:01:37 PM PDT 24
Peak memory 182656 kb
Host smart-86dd4c50-d526-43b4-80d0-baf7bc5d7248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416286885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.416286885
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3969603732
Short name T99
Test name
Test status
Simulation time 19866681565 ps
CPU time 40.15 seconds
Started May 19 12:59:31 PM PDT 24
Finished May 19 01:00:12 PM PDT 24
Peak memory 182496 kb
Host smart-2e6579a5-a0a5-49fc-b594-62a7221393ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969603732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3969603732
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.201798508
Short name T254
Test name
Test status
Simulation time 8548805665 ps
CPU time 8.72 seconds
Started May 19 12:59:31 PM PDT 24
Finished May 19 12:59:41 PM PDT 24
Peak memory 182628 kb
Host smart-459dc16e-a35e-4ddf-aa84-7c5b33ea2824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201798508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.201798508
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.623418067
Short name T290
Test name
Test status
Simulation time 74851724701 ps
CPU time 136.59 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:01:52 PM PDT 24
Peak memory 182592 kb
Host smart-83d02501-b230-413e-8287-977e09f4733e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623418067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.623418067
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4077826532
Short name T8
Test name
Test status
Simulation time 61950329648 ps
CPU time 48.41 seconds
Started May 19 12:59:33 PM PDT 24
Finished May 19 01:00:22 PM PDT 24
Peak memory 182656 kb
Host smart-599ac83f-2812-4b98-b56b-8f250dcde0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077826532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4077826532
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.297486802
Short name T437
Test name
Test status
Simulation time 127348939913 ps
CPU time 61.58 seconds
Started May 19 12:59:30 PM PDT 24
Finished May 19 01:00:32 PM PDT 24
Peak memory 182632 kb
Host smart-ca830fd7-4308-433b-9177-cbd05aa16f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297486802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.297486802
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2554270229
Short name T406
Test name
Test status
Simulation time 107688719 ps
CPU time 2.08 seconds
Started May 19 12:59:33 PM PDT 24
Finished May 19 12:59:35 PM PDT 24
Peak memory 182584 kb
Host smart-8d1be8cc-c762-48b6-ade4-e5d4f73702da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554270229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2554270229
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2515408803
Short name T452
Test name
Test status
Simulation time 903888746267 ps
CPU time 525.79 seconds
Started May 19 12:59:38 PM PDT 24
Finished May 19 01:08:24 PM PDT 24
Peak memory 182620 kb
Host smart-1e9f4a3a-02c4-45df-bb25-3b4db5b0d829
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515408803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2515408803
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3745825897
Short name T399
Test name
Test status
Simulation time 538757564525 ps
CPU time 116.47 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:01:32 PM PDT 24
Peak memory 182616 kb
Host smart-e1f426c5-7efc-4106-bbdf-1d76a8220123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745825897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3745825897
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1309637585
Short name T235
Test name
Test status
Simulation time 608201231746 ps
CPU time 290.85 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:04:28 PM PDT 24
Peak memory 190824 kb
Host smart-109c3c60-60cf-4622-9745-85cdef9bd9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309637585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1309637585
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1761808751
Short name T310
Test name
Test status
Simulation time 68803885629 ps
CPU time 188.58 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:02:46 PM PDT 24
Peak memory 190856 kb
Host smart-73e5a8d3-aae1-4f64-9041-03ccfa091439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761808751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1761808751
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2239016432
Short name T304
Test name
Test status
Simulation time 451437540980 ps
CPU time 197.56 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:02:55 PM PDT 24
Peak memory 182648 kb
Host smart-32234cce-9f69-4755-988b-9e0401cd2b56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239016432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2239016432
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3963823064
Short name T384
Test name
Test status
Simulation time 140317356953 ps
CPU time 237.42 seconds
Started May 19 12:59:35 PM PDT 24
Finished May 19 01:03:34 PM PDT 24
Peak memory 182640 kb
Host smart-680d814e-98ca-4662-94ba-10847f187722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963823064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3963823064
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3555444275
Short name T282
Test name
Test status
Simulation time 111945129651 ps
CPU time 660.48 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:10:35 PM PDT 24
Peak memory 192000 kb
Host smart-5e0d8436-7da9-455d-b018-93b120ae1c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555444275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3555444275
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3349873385
Short name T143
Test name
Test status
Simulation time 129089658509 ps
CPU time 133.21 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:01:50 PM PDT 24
Peak memory 194296 kb
Host smart-8b2da32c-bc33-4f7c-8a8c-74d05d264d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349873385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3349873385
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2341678499
Short name T426
Test name
Test status
Simulation time 203090016216 ps
CPU time 82.82 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:01:00 PM PDT 24
Peak memory 194216 kb
Host smart-01fc0192-6015-4f78-aaac-c69580025fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341678499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2341678499
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.737238654
Short name T44
Test name
Test status
Simulation time 367119141387 ps
CPU time 573.22 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:09:10 PM PDT 24
Peak memory 182616 kb
Host smart-b57b4d5b-134a-4075-ab0a-349215e839e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737238654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.737238654
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1933432740
Short name T413
Test name
Test status
Simulation time 138208284847 ps
CPU time 193.03 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:02:50 PM PDT 24
Peak memory 182592 kb
Host smart-eb091198-f3a2-4e34-89b6-e7f4c6f62ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933432740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1933432740
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3530494052
Short name T429
Test name
Test status
Simulation time 183364960530 ps
CPU time 326.47 seconds
Started May 19 12:59:35 PM PDT 24
Finished May 19 01:05:02 PM PDT 24
Peak memory 182648 kb
Host smart-f8531e91-1ca1-4771-85b7-4f1f3142e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530494052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3530494052
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.947646212
Short name T440
Test name
Test status
Simulation time 95518546088 ps
CPU time 43.82 seconds
Started May 19 12:59:34 PM PDT 24
Finished May 19 01:00:20 PM PDT 24
Peak memory 182600 kb
Host smart-feefeec4-e999-49bc-92ba-2e7d0da0319b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947646212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.947646212
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2817688273
Short name T376
Test name
Test status
Simulation time 43332862024 ps
CPU time 63.34 seconds
Started May 19 12:59:37 PM PDT 24
Finished May 19 01:00:41 PM PDT 24
Peak memory 182648 kb
Host smart-08ca3d9b-b220-4c6e-9c4f-edf8d3be1c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817688273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2817688273
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2343406159
Short name T418
Test name
Test status
Simulation time 30732100847 ps
CPU time 16.79 seconds
Started May 19 12:59:35 PM PDT 24
Finished May 19 12:59:53 PM PDT 24
Peak memory 182556 kb
Host smart-34a06b00-510d-4811-8bd9-9eb1b4f44597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343406159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2343406159
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.381776196
Short name T63
Test name
Test status
Simulation time 121849911 ps
CPU time 0.68 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 12:59:38 PM PDT 24
Peak memory 181724 kb
Host smart-570781f4-8f68-41f2-8d82-4016aba2b9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381776196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.381776196
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4282883603
Short name T253
Test name
Test status
Simulation time 552192078655 ps
CPU time 959.68 seconds
Started May 19 12:59:42 PM PDT 24
Finished May 19 01:15:42 PM PDT 24
Peak memory 182628 kb
Host smart-8ed8426c-86e7-4f3e-a1b9-6732042b3aab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282883603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4282883603
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2447553955
Short name T359
Test name
Test status
Simulation time 404091638699 ps
CPU time 173.37 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:02:31 PM PDT 24
Peak memory 182592 kb
Host smart-05d631b4-4f69-41c3-b3d7-c2c2c8d402c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447553955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2447553955
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1554054721
Short name T276
Test name
Test status
Simulation time 50896413225 ps
CPU time 304.38 seconds
Started May 19 12:59:36 PM PDT 24
Finished May 19 01:04:42 PM PDT 24
Peak memory 190780 kb
Host smart-03173291-7d95-4e26-9ab3-3a6bbc48e4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554054721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1554054721
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2226053268
Short name T306
Test name
Test status
Simulation time 387559384359 ps
CPU time 135.91 seconds
Started May 19 12:59:40 PM PDT 24
Finished May 19 01:01:57 PM PDT 24
Peak memory 194424 kb
Host smart-3c837da0-da1e-4d85-b968-eb67a66eac60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226053268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2226053268
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.107235182
Short name T433
Test name
Test status
Simulation time 103794905057 ps
CPU time 148.13 seconds
Started May 19 12:59:42 PM PDT 24
Finished May 19 01:02:11 PM PDT 24
Peak memory 182612 kb
Host smart-19c4e4ab-0cef-4a3b-89c7-5b211a851e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107235182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
107235182
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.780149244
Short name T383
Test name
Test status
Simulation time 13358055780 ps
CPU time 23.01 seconds
Started May 19 12:59:43 PM PDT 24
Finished May 19 01:00:06 PM PDT 24
Peak memory 182648 kb
Host smart-c4bac7c1-49cd-4aac-8b78-fc3a645b24fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780149244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.780149244
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1953848535
Short name T430
Test name
Test status
Simulation time 279133559440 ps
CPU time 97.33 seconds
Started May 19 12:59:43 PM PDT 24
Finished May 19 01:01:21 PM PDT 24
Peak memory 182640 kb
Host smart-3de8a135-f60c-4230-8198-fe21b6a5c4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953848535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1953848535
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3521874339
Short name T68
Test name
Test status
Simulation time 90050523981 ps
CPU time 169.54 seconds
Started May 19 12:59:42 PM PDT 24
Finished May 19 01:02:32 PM PDT 24
Peak memory 190772 kb
Host smart-e7f4eda1-a10e-451b-b54f-163d7d9ba46f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521874339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3521874339
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3257145130
Short name T330
Test name
Test status
Simulation time 91816798615 ps
CPU time 212.87 seconds
Started May 19 12:59:43 PM PDT 24
Finished May 19 01:03:17 PM PDT 24
Peak memory 182648 kb
Host smart-17d447d3-e728-4bfd-91f5-fdd8029b4025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257145130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3257145130
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3651383180
Short name T36
Test name
Test status
Simulation time 48936490587 ps
CPU time 95.79 seconds
Started May 19 12:59:41 PM PDT 24
Finished May 19 01:01:17 PM PDT 24
Peak memory 197252 kb
Host smart-00d850b4-a2a8-4b58-bebe-b06ab252b3a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651383180 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3651383180
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.661970333
Short name T363
Test name
Test status
Simulation time 152296773493 ps
CPU time 65.13 seconds
Started May 19 12:59:40 PM PDT 24
Finished May 19 01:00:46 PM PDT 24
Peak memory 182956 kb
Host smart-605b4a6e-1806-4bda-bfd9-88e40bc62a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661970333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.661970333
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3356996541
Short name T293
Test name
Test status
Simulation time 296383877653 ps
CPU time 590.33 seconds
Started May 19 12:59:41 PM PDT 24
Finished May 19 01:09:32 PM PDT 24
Peak memory 190792 kb
Host smart-11f8f6f1-1316-49d9-bb43-9c5cbef744e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356996541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3356996541
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2347294765
Short name T249
Test name
Test status
Simulation time 12702279354 ps
CPU time 17.78 seconds
Started May 19 12:59:41 PM PDT 24
Finished May 19 12:59:59 PM PDT 24
Peak memory 182624 kb
Host smart-6613ddf4-7e70-46e2-a703-5d393887f0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347294765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2347294765
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1453769788
Short name T156
Test name
Test status
Simulation time 66822934929 ps
CPU time 51.84 seconds
Started May 19 12:59:44 PM PDT 24
Finished May 19 01:00:37 PM PDT 24
Peak memory 182636 kb
Host smart-547b7933-09bb-406b-b6db-0abe69600086
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453769788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1453769788
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3369610446
Short name T397
Test name
Test status
Simulation time 505182371382 ps
CPU time 92.11 seconds
Started May 19 12:59:45 PM PDT 24
Finished May 19 01:01:17 PM PDT 24
Peak memory 182856 kb
Host smart-db0325c6-41ed-4633-b307-2fce583291f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369610446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3369610446
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1258137278
Short name T136
Test name
Test status
Simulation time 70930310183 ps
CPU time 120.91 seconds
Started May 19 12:59:45 PM PDT 24
Finished May 19 01:01:47 PM PDT 24
Peak memory 190788 kb
Host smart-92bb346a-810c-429e-a226-c7e504d700d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258137278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1258137278
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2361422508
Short name T356
Test name
Test status
Simulation time 13768187951 ps
CPU time 8.73 seconds
Started May 19 12:59:47 PM PDT 24
Finished May 19 12:59:57 PM PDT 24
Peak memory 182660 kb
Host smart-1d26cef5-878a-48c5-8727-1918718e5648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361422508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2361422508
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2846622680
Short name T37
Test name
Test status
Simulation time 67091138492 ps
CPU time 359.37 seconds
Started May 19 12:59:47 PM PDT 24
Finished May 19 01:05:47 PM PDT 24
Peak memory 205472 kb
Host smart-e0970d74-4825-4475-8760-3f5c04dfb169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846622680 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2846622680
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.225205508
Short name T285
Test name
Test status
Simulation time 248635005122 ps
CPU time 239.28 seconds
Started May 19 12:59:09 PM PDT 24
Finished May 19 01:03:09 PM PDT 24
Peak memory 182620 kb
Host smart-04b74e27-5bb2-4039-a1b1-6ce57e601ca9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225205508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.225205508
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3544851986
Short name T420
Test name
Test status
Simulation time 975650885284 ps
CPU time 142.5 seconds
Started May 19 12:59:08 PM PDT 24
Finished May 19 01:01:31 PM PDT 24
Peak memory 182576 kb
Host smart-c8f39a92-0c6a-42ea-9c5e-22e1a8e99613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544851986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3544851986
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.4033620613
Short name T117
Test name
Test status
Simulation time 522440468368 ps
CPU time 591.65 seconds
Started May 19 12:59:09 PM PDT 24
Finished May 19 01:09:02 PM PDT 24
Peak memory 190836 kb
Host smart-ae389659-defd-4ab5-9cee-27277379b48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033620613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4033620613
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.905327341
Short name T367
Test name
Test status
Simulation time 253318204 ps
CPU time 1.1 seconds
Started May 19 12:59:10 PM PDT 24
Finished May 19 12:59:11 PM PDT 24
Peak memory 182572 kb
Host smart-13f8d7a7-be4d-443e-a7e6-dbbfbf14e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905327341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.905327341
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3587064433
Short name T17
Test name
Test status
Simulation time 105495286 ps
CPU time 0.79 seconds
Started May 19 12:59:16 PM PDT 24
Finished May 19 12:59:19 PM PDT 24
Peak memory 213136 kb
Host smart-f4e9604e-2aab-41bd-ba30-36042844b544
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587064433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3587064433
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.787373127
Short name T215
Test name
Test status
Simulation time 22199027915 ps
CPU time 37.58 seconds
Started May 19 12:59:51 PM PDT 24
Finished May 19 01:00:29 PM PDT 24
Peak memory 182628 kb
Host smart-1f37a93b-a49b-4d05-a912-fd6b4b52b2e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787373127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.787373127
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2674837788
Short name T366
Test name
Test status
Simulation time 262520483719 ps
CPU time 113.35 seconds
Started May 19 12:59:51 PM PDT 24
Finished May 19 01:01:46 PM PDT 24
Peak memory 182600 kb
Host smart-4fe8061f-1c00-460b-b76d-c748c40a7082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674837788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2674837788
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.500427702
Short name T442
Test name
Test status
Simulation time 18758697536 ps
CPU time 34.17 seconds
Started May 19 12:59:53 PM PDT 24
Finished May 19 01:00:28 PM PDT 24
Peak memory 190828 kb
Host smart-650f864d-9bd9-43fe-a85e-c1b214b15122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500427702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.500427702
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2611987432
Short name T231
Test name
Test status
Simulation time 382133909127 ps
CPU time 479.14 seconds
Started May 19 12:59:53 PM PDT 24
Finished May 19 01:07:52 PM PDT 24
Peak memory 182652 kb
Host smart-f269ba09-7037-4bad-b03f-e1cc9b33faf5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611987432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2611987432
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1079208580
Short name T390
Test name
Test status
Simulation time 65969668623 ps
CPU time 97.84 seconds
Started May 19 12:59:51 PM PDT 24
Finished May 19 01:01:30 PM PDT 24
Peak memory 182640 kb
Host smart-1764788a-0982-4c43-9b2f-33b1eb77357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079208580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1079208580
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2228041416
Short name T431
Test name
Test status
Simulation time 166240675206 ps
CPU time 91.67 seconds
Started May 19 12:59:51 PM PDT 24
Finished May 19 01:01:24 PM PDT 24
Peak memory 182636 kb
Host smart-9cab66a9-9cd8-4902-987a-8e63f6e9abc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228041416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2228041416
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3938350350
Short name T301
Test name
Test status
Simulation time 82905684759 ps
CPU time 201.69 seconds
Started May 19 12:59:53 PM PDT 24
Finished May 19 01:03:15 PM PDT 24
Peak memory 190848 kb
Host smart-5e4f848e-62f8-4811-8d56-6e4ec1c34acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938350350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3938350350
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1902071930
Short name T294
Test name
Test status
Simulation time 333543618638 ps
CPU time 613.16 seconds
Started May 19 12:59:56 PM PDT 24
Finished May 19 01:10:11 PM PDT 24
Peak memory 182600 kb
Host smart-e6f540ff-857c-45c5-804c-f9976ba87847
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902071930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1902071930
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3633548998
Short name T364
Test name
Test status
Simulation time 55015872549 ps
CPU time 79.28 seconds
Started May 19 12:59:56 PM PDT 24
Finished May 19 01:01:16 PM PDT 24
Peak memory 182612 kb
Host smart-e2053a33-f1be-43b4-86e1-4b29af0aaa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633548998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3633548998
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3753181913
Short name T312
Test name
Test status
Simulation time 545375503227 ps
CPU time 1835.69 seconds
Started May 19 12:59:51 PM PDT 24
Finished May 19 01:30:28 PM PDT 24
Peak memory 190828 kb
Host smart-9ba0be3a-4ede-4249-87b5-bb0ac2f3be55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753181913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3753181913
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1969131182
Short name T5
Test name
Test status
Simulation time 1424455177 ps
CPU time 2.3 seconds
Started May 19 12:59:55 PM PDT 24
Finished May 19 12:59:58 PM PDT 24
Peak memory 182852 kb
Host smart-a3fb391c-6125-4b86-853b-914dd28010a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969131182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1969131182
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2150684456
Short name T198
Test name
Test status
Simulation time 54203478926 ps
CPU time 122.54 seconds
Started May 19 12:59:58 PM PDT 24
Finished May 19 01:02:01 PM PDT 24
Peak memory 190824 kb
Host smart-0f5d9d8e-6420-4b32-aba0-7971e4faf99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150684456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2150684456
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1855095261
Short name T292
Test name
Test status
Simulation time 5504207037 ps
CPU time 8.62 seconds
Started May 19 12:59:56 PM PDT 24
Finished May 19 01:00:06 PM PDT 24
Peak memory 182652 kb
Host smart-c9c5d73c-ecbe-478f-ae48-deeeba070e98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855095261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1855095261
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.8625633
Short name T379
Test name
Test status
Simulation time 144451623203 ps
CPU time 179.41 seconds
Started May 19 12:59:56 PM PDT 24
Finished May 19 01:02:57 PM PDT 24
Peak memory 182628 kb
Host smart-aaefe305-1a8c-4699-8404-90b556a766d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8625633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.8625633
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3757440477
Short name T313
Test name
Test status
Simulation time 22693194 ps
CPU time 0.54 seconds
Started May 19 12:59:59 PM PDT 24
Finished May 19 01:00:00 PM PDT 24
Peak memory 182380 kb
Host smart-2dd88d90-15a3-467a-b630-861a46217d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757440477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3757440477
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.4228864859
Short name T10
Test name
Test status
Simulation time 207365491 ps
CPU time 0.61 seconds
Started May 19 12:59:58 PM PDT 24
Finished May 19 01:00:00 PM PDT 24
Peak memory 182440 kb
Host smart-0baee7ff-f63b-49f3-a92b-13294f576c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228864859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.4228864859
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.849535632
Short name T445
Test name
Test status
Simulation time 2840372426740 ps
CPU time 1073.8 seconds
Started May 19 01:00:02 PM PDT 24
Finished May 19 01:17:57 PM PDT 24
Peak memory 190788 kb
Host smart-1616d8c9-3d51-45d8-bde2-bf64649b10cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849535632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
849535632
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1983408573
Short name T298
Test name
Test status
Simulation time 40429696175 ps
CPU time 76.9 seconds
Started May 19 01:00:02 PM PDT 24
Finished May 19 01:01:19 PM PDT 24
Peak memory 182644 kb
Host smart-23aeaaca-38e2-4847-958b-236b6577c7ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983408573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1983408573
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.4217290565
Short name T402
Test name
Test status
Simulation time 211393566421 ps
CPU time 178.24 seconds
Started May 19 01:00:04 PM PDT 24
Finished May 19 01:03:02 PM PDT 24
Peak memory 182604 kb
Host smart-b64f28ff-008c-4f55-be4b-b0aa02a1df82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217290565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.4217290565
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3582735815
Short name T183
Test name
Test status
Simulation time 338390618788 ps
CPU time 331.81 seconds
Started May 19 01:00:04 PM PDT 24
Finished May 19 01:05:37 PM PDT 24
Peak memory 190844 kb
Host smart-dcd3e1ce-32c5-4f60-86c6-1e2703f7a57f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582735815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3582735815
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3431630741
Short name T173
Test name
Test status
Simulation time 26317626355 ps
CPU time 12.7 seconds
Started May 19 01:00:03 PM PDT 24
Finished May 19 01:00:16 PM PDT 24
Peak memory 193044 kb
Host smart-5e703836-b490-4f80-895d-731dd65d8f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431630741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3431630741
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2206143605
Short name T391
Test name
Test status
Simulation time 5429741181 ps
CPU time 10.02 seconds
Started May 19 01:00:03 PM PDT 24
Finished May 19 01:00:13 PM PDT 24
Peak memory 182660 kb
Host smart-76576025-57cf-4d9e-b8b9-7a3b5eaa826d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206143605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2206143605
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.561207937
Short name T27
Test name
Test status
Simulation time 84135174857 ps
CPU time 69.96 seconds
Started May 19 01:00:04 PM PDT 24
Finished May 19 01:01:14 PM PDT 24
Peak memory 182656 kb
Host smart-a6b1d337-67d3-45dd-a154-ff7b031703e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561207937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.561207937
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1813491718
Short name T245
Test name
Test status
Simulation time 62309316095 ps
CPU time 105.42 seconds
Started May 19 01:00:03 PM PDT 24
Finished May 19 01:01:49 PM PDT 24
Peak memory 190772 kb
Host smart-d78c7742-9fd9-4444-a86d-cd311d2eb4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813491718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1813491718
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.247799361
Short name T414
Test name
Test status
Simulation time 735697626 ps
CPU time 0.81 seconds
Started May 19 01:00:02 PM PDT 24
Finished May 19 01:00:04 PM PDT 24
Peak memory 182360 kb
Host smart-6649f7eb-3d02-4e1c-9a34-18cb561808da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247799361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.247799361
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2935953407
Short name T189
Test name
Test status
Simulation time 1447574394616 ps
CPU time 781.77 seconds
Started May 19 01:00:07 PM PDT 24
Finished May 19 01:13:10 PM PDT 24
Peak memory 194952 kb
Host smart-aa629009-c975-42a6-aa8c-056d5dc91ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935953407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2935953407
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2151018354
Short name T321
Test name
Test status
Simulation time 359219748887 ps
CPU time 315.74 seconds
Started May 19 01:00:07 PM PDT 24
Finished May 19 01:05:23 PM PDT 24
Peak memory 182660 kb
Host smart-7a69b474-9a53-4a2a-b139-d1e6716073fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151018354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2151018354
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3730618232
Short name T398
Test name
Test status
Simulation time 543450040944 ps
CPU time 249.33 seconds
Started May 19 01:00:08 PM PDT 24
Finished May 19 01:04:18 PM PDT 24
Peak memory 182624 kb
Host smart-82d60d40-5d3b-4738-87de-5e48da461cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730618232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3730618232
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.525257517
Short name T324
Test name
Test status
Simulation time 812777221505 ps
CPU time 558.64 seconds
Started May 19 01:00:09 PM PDT 24
Finished May 19 01:09:28 PM PDT 24
Peak memory 190816 kb
Host smart-869064d8-1d24-478c-b31c-94e954643074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525257517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.525257517
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3803223118
Short name T21
Test name
Test status
Simulation time 6024442166 ps
CPU time 17.24 seconds
Started May 19 01:00:07 PM PDT 24
Finished May 19 01:00:25 PM PDT 24
Peak memory 182656 kb
Host smart-5f6a4ea2-e65d-4eae-8d80-935fb16bbfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803223118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3803223118
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1344244894
Short name T408
Test name
Test status
Simulation time 104922874314 ps
CPU time 156.67 seconds
Started May 19 01:00:07 PM PDT 24
Finished May 19 01:02:45 PM PDT 24
Peak memory 182572 kb
Host smart-5905cc6b-d1f2-406f-bb6f-93637d72e78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344244894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1344244894
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1868915817
Short name T357
Test name
Test status
Simulation time 150920366171 ps
CPU time 223.22 seconds
Started May 19 01:00:09 PM PDT 24
Finished May 19 01:03:52 PM PDT 24
Peak memory 182636 kb
Host smart-cbc7c440-41b6-469b-bbd8-15386e3d6b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868915817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1868915817
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2321433309
Short name T153
Test name
Test status
Simulation time 566181906280 ps
CPU time 603.39 seconds
Started May 19 01:00:07 PM PDT 24
Finished May 19 01:10:11 PM PDT 24
Peak memory 190836 kb
Host smart-7e161df3-c205-4eec-a422-36b6c82cea77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321433309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2321433309
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3957398821
Short name T170
Test name
Test status
Simulation time 147501143847 ps
CPU time 418.98 seconds
Started May 19 01:00:15 PM PDT 24
Finished May 19 01:07:15 PM PDT 24
Peak memory 190840 kb
Host smart-4461a7e9-ccfa-4ddd-90d6-eba5e43cf837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957398821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3957398821
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2147499786
Short name T242
Test name
Test status
Simulation time 565915475369 ps
CPU time 312.63 seconds
Started May 19 01:00:12 PM PDT 24
Finished May 19 01:05:25 PM PDT 24
Peak memory 182652 kb
Host smart-a3bf8339-9480-4792-9f6d-9c5365a65a6d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147499786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2147499786
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3590550013
Short name T361
Test name
Test status
Simulation time 630532711388 ps
CPU time 133.39 seconds
Started May 19 01:00:12 PM PDT 24
Finished May 19 01:02:25 PM PDT 24
Peak memory 182632 kb
Host smart-2e055220-e795-4452-a1c3-4cbc205bfb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590550013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3590550013
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2673658262
Short name T103
Test name
Test status
Simulation time 577135253103 ps
CPU time 573.42 seconds
Started May 19 01:00:14 PM PDT 24
Finished May 19 01:09:48 PM PDT 24
Peak memory 190828 kb
Host smart-aa4be308-dbe0-4cdb-a96b-c6070e3eaa3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673658262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2673658262
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1238294549
Short name T286
Test name
Test status
Simulation time 134738584192 ps
CPU time 246.15 seconds
Started May 19 01:00:13 PM PDT 24
Finished May 19 01:04:20 PM PDT 24
Peak memory 190848 kb
Host smart-dc0d4cca-4e3b-41d9-86d1-1bc86a115698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238294549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1238294549
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3386971497
Short name T104
Test name
Test status
Simulation time 855305756457 ps
CPU time 1275.22 seconds
Started May 19 01:00:12 PM PDT 24
Finished May 19 01:21:28 PM PDT 24
Peak memory 190840 kb
Host smart-53249b10-fd3f-4ca6-b3a5-438ff59e16e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386971497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3386971497
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.990417302
Short name T415
Test name
Test status
Simulation time 342353195949 ps
CPU time 293.29 seconds
Started May 19 01:00:15 PM PDT 24
Finished May 19 01:05:09 PM PDT 24
Peak memory 182956 kb
Host smart-39694013-0fd3-4750-b6c0-9aa9383012c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990417302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.990417302
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1664418828
Short name T299
Test name
Test status
Simulation time 9021528436 ps
CPU time 59.19 seconds
Started May 19 01:00:14 PM PDT 24
Finished May 19 01:01:14 PM PDT 24
Peak memory 182584 kb
Host smart-4a0a5bbe-8662-4495-88c5-eb4611015dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664418828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1664418828
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3968285943
Short name T274
Test name
Test status
Simulation time 33206129067 ps
CPU time 66.41 seconds
Started May 19 01:00:15 PM PDT 24
Finished May 19 01:01:22 PM PDT 24
Peak memory 190828 kb
Host smart-baef0d75-5819-48e1-b05c-5e0692768fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968285943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3968285943
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.336233258
Short name T337
Test name
Test status
Simulation time 203340747250 ps
CPU time 621.69 seconds
Started May 19 01:00:23 PM PDT 24
Finished May 19 01:10:46 PM PDT 24
Peak memory 190836 kb
Host smart-091a0e6a-5d24-43cd-b427-e667c414f642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336233258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
336233258
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1475210816
Short name T388
Test name
Test status
Simulation time 741179734249 ps
CPU time 249.46 seconds
Started May 19 12:59:16 PM PDT 24
Finished May 19 01:03:27 PM PDT 24
Peak memory 182648 kb
Host smart-4256770f-fea5-479c-b56b-ec3ee0203c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475210816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1475210816
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2410133169
Short name T307
Test name
Test status
Simulation time 85473578446 ps
CPU time 172.63 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 01:02:10 PM PDT 24
Peak memory 182636 kb
Host smart-baabb6f6-d9b5-474b-bd96-59eb0c1cd84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410133169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2410133169
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.992724787
Short name T373
Test name
Test status
Simulation time 177891103 ps
CPU time 0.72 seconds
Started May 19 12:59:16 PM PDT 24
Finished May 19 12:59:18 PM PDT 24
Peak memory 191024 kb
Host smart-76286e0f-79fe-41b7-b208-c61f6521bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992724787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.992724787
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1288151726
Short name T16
Test name
Test status
Simulation time 123215919 ps
CPU time 0.96 seconds
Started May 19 12:59:16 PM PDT 24
Finished May 19 12:59:18 PM PDT 24
Peak memory 213720 kb
Host smart-3a178df3-7b0d-44bc-8083-f3996aee0180
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288151726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1288151726
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1636074190
Short name T358
Test name
Test status
Simulation time 327794751992 ps
CPU time 137.82 seconds
Started May 19 12:59:09 PM PDT 24
Finished May 19 01:01:27 PM PDT 24
Peak memory 182588 kb
Host smart-fc7d0987-649e-4ce1-ae6f-46f2418cacf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636074190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1636074190
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1498157871
Short name T38
Test name
Test status
Simulation time 49163057003 ps
CPU time 270.65 seconds
Started May 19 12:59:16 PM PDT 24
Finished May 19 01:03:48 PM PDT 24
Peak memory 197256 kb
Host smart-ff5ea5d4-a6d6-405a-a4ad-646db1caa81d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498157871 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1498157871
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.570415308
Short name T302
Test name
Test status
Simulation time 1587822637764 ps
CPU time 637.59 seconds
Started May 19 01:00:19 PM PDT 24
Finished May 19 01:10:57 PM PDT 24
Peak memory 182912 kb
Host smart-960c5d48-39d6-46c3-b47a-c133a9f0c5a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570415308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.570415308
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3070646625
Short name T375
Test name
Test status
Simulation time 539757518717 ps
CPU time 162.64 seconds
Started May 19 01:00:18 PM PDT 24
Finished May 19 01:03:01 PM PDT 24
Peak memory 182628 kb
Host smart-111df1a2-03c6-4347-909f-cd815333d0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070646625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3070646625
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2765833983
Short name T145
Test name
Test status
Simulation time 193276486110 ps
CPU time 388.97 seconds
Started May 19 01:00:19 PM PDT 24
Finished May 19 01:06:49 PM PDT 24
Peak memory 190812 kb
Host smart-87affa23-9753-4ce0-9acf-ea7f6530fee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765833983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2765833983
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3724595245
Short name T296
Test name
Test status
Simulation time 40109256745 ps
CPU time 75.12 seconds
Started May 19 01:00:19 PM PDT 24
Finished May 19 01:01:35 PM PDT 24
Peak memory 190816 kb
Host smart-a5271abf-15b1-4245-9d4c-a5e9a9f4ff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724595245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3724595245
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.48638992
Short name T407
Test name
Test status
Simulation time 24741075856 ps
CPU time 32.3 seconds
Started May 19 01:00:23 PM PDT 24
Finished May 19 01:00:56 PM PDT 24
Peak memory 192496 kb
Host smart-b858a2e7-6d6b-43fe-b79e-9d0a7f91002e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48638992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.48638992
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2627189669
Short name T401
Test name
Test status
Simulation time 24934313235 ps
CPU time 38.32 seconds
Started May 19 01:00:26 PM PDT 24
Finished May 19 01:01:05 PM PDT 24
Peak memory 182612 kb
Host smart-34e7d1ff-e68b-4ecf-b0f5-13556d5b4085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627189669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2627189669
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1529832062
Short name T221
Test name
Test status
Simulation time 95854192605 ps
CPU time 518.15 seconds
Started May 19 01:00:23 PM PDT 24
Finished May 19 01:09:02 PM PDT 24
Peak memory 182636 kb
Host smart-a199a127-e3d5-4580-8dec-b7d473e71093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529832062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1529832062
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.942841617
Short name T264
Test name
Test status
Simulation time 484094766756 ps
CPU time 434.12 seconds
Started May 19 01:00:23 PM PDT 24
Finished May 19 01:07:38 PM PDT 24
Peak memory 182576 kb
Host smart-494ee8dc-3d03-4acd-8b70-c7cfa38dfbc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942841617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.942841617
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.4239522868
Short name T453
Test name
Test status
Simulation time 120008828678 ps
CPU time 191.58 seconds
Started May 19 01:00:23 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 182612 kb
Host smart-31a43b84-1047-4df9-ade8-f1500af0a52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239522868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.4239522868
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.190128899
Short name T279
Test name
Test status
Simulation time 350806238052 ps
CPU time 690.05 seconds
Started May 19 01:00:23 PM PDT 24
Finished May 19 01:11:54 PM PDT 24
Peak memory 190796 kb
Host smart-93154a68-eda7-4810-9e5a-e9185209cbf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190128899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.190128899
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2438383865
Short name T386
Test name
Test status
Simulation time 97739389 ps
CPU time 3.94 seconds
Started May 19 01:00:28 PM PDT 24
Finished May 19 01:00:33 PM PDT 24
Peak memory 182576 kb
Host smart-63843b84-48af-4ba6-a8ab-fbd350b54467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438383865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2438383865
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3618761547
Short name T303
Test name
Test status
Simulation time 4022552826464 ps
CPU time 997.49 seconds
Started May 19 01:00:27 PM PDT 24
Finished May 19 01:17:05 PM PDT 24
Peak memory 190788 kb
Host smart-b4ca3057-686a-46c3-bce1-2ebcae3a6d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618761547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3618761547
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3923667034
Short name T131
Test name
Test status
Simulation time 132017762781 ps
CPU time 220.28 seconds
Started May 19 01:00:27 PM PDT 24
Finished May 19 01:04:08 PM PDT 24
Peak memory 182600 kb
Host smart-9ba8ea8e-ce1b-497c-aff5-f83a41e6dd81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923667034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3923667034
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1950884359
Short name T392
Test name
Test status
Simulation time 91198170744 ps
CPU time 75.6 seconds
Started May 19 01:00:27 PM PDT 24
Finished May 19 01:01:44 PM PDT 24
Peak memory 182536 kb
Host smart-a7a59381-eb4f-4f83-8488-b588e665ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950884359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1950884359
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2418454154
Short name T389
Test name
Test status
Simulation time 1004326468408 ps
CPU time 372 seconds
Started May 19 01:00:29 PM PDT 24
Finished May 19 01:06:42 PM PDT 24
Peak memory 190804 kb
Host smart-cfde0069-ae97-4e06-878e-08b46531d9fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418454154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2418454154
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.734603171
Short name T43
Test name
Test status
Simulation time 16754053 ps
CPU time 0.54 seconds
Started May 19 01:00:28 PM PDT 24
Finished May 19 01:00:30 PM PDT 24
Peak memory 182424 kb
Host smart-37d8c327-c205-4358-9512-2ee7af65d030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734603171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.734603171
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.892741313
Short name T25
Test name
Test status
Simulation time 760479298801 ps
CPU time 322.25 seconds
Started May 19 01:00:35 PM PDT 24
Finished May 19 01:05:58 PM PDT 24
Peak memory 190832 kb
Host smart-68acde39-a954-4e73-a1eb-197d16986826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892741313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
892741313
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2324464116
Short name T101
Test name
Test status
Simulation time 322888970832 ps
CPU time 535.46 seconds
Started May 19 01:00:35 PM PDT 24
Finished May 19 01:09:31 PM PDT 24
Peak memory 182624 kb
Host smart-7b39d4b9-4e42-4bd0-94cc-02b9cdf7dfb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324464116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2324464116
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.446902804
Short name T423
Test name
Test status
Simulation time 23452059360 ps
CPU time 31.36 seconds
Started May 19 01:00:34 PM PDT 24
Finished May 19 01:01:06 PM PDT 24
Peak memory 182624 kb
Host smart-6aa4a6e1-f38e-40ed-b7cf-40f6632589f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446902804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.446902804
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1951093773
Short name T409
Test name
Test status
Simulation time 44731944861 ps
CPU time 793.89 seconds
Started May 19 01:00:35 PM PDT 24
Finished May 19 01:13:49 PM PDT 24
Peak memory 182576 kb
Host smart-c9c23b35-d0a2-4b09-9c6d-ee88defccb44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951093773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1951093773
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.42192930
Short name T434
Test name
Test status
Simulation time 57019914 ps
CPU time 0.55 seconds
Started May 19 01:00:33 PM PDT 24
Finished May 19 01:00:34 PM PDT 24
Peak memory 182436 kb
Host smart-bc706309-f65e-405d-aa29-cdf56915f557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42192930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.42192930
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.801494427
Short name T40
Test name
Test status
Simulation time 147720057599 ps
CPU time 841.63 seconds
Started May 19 01:00:34 PM PDT 24
Finished May 19 01:14:37 PM PDT 24
Peak memory 209460 kb
Host smart-6f6d71e8-a573-4250-9e1f-d1f192ee9ed9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801494427 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.801494427
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3591474015
Short name T424
Test name
Test status
Simulation time 244983310689 ps
CPU time 339.2 seconds
Started May 19 01:00:34 PM PDT 24
Finished May 19 01:06:14 PM PDT 24
Peak memory 182632 kb
Host smart-4f1c9e69-6a6d-42e9-a976-edae0ad59136
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591474015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3591474015
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1060188854
Short name T400
Test name
Test status
Simulation time 51263934705 ps
CPU time 48.61 seconds
Started May 19 01:00:35 PM PDT 24
Finished May 19 01:01:24 PM PDT 24
Peak memory 182624 kb
Host smart-7e25250e-1477-4e30-8473-ba836518fc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060188854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1060188854
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3582412358
Short name T314
Test name
Test status
Simulation time 36062427203 ps
CPU time 53.31 seconds
Started May 19 01:00:41 PM PDT 24
Finished May 19 01:01:35 PM PDT 24
Peak memory 182596 kb
Host smart-2a19e722-b9c5-4429-8637-9340a7d276e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582412358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3582412358
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2284728338
Short name T326
Test name
Test status
Simulation time 138797278826 ps
CPU time 123.82 seconds
Started May 19 01:00:38 PM PDT 24
Finished May 19 01:02:43 PM PDT 24
Peak memory 182600 kb
Host smart-3ffb42c1-4010-4dc9-9641-df85322a810b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284728338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2284728338
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.106609856
Short name T341
Test name
Test status
Simulation time 19601297540 ps
CPU time 34.62 seconds
Started May 19 01:00:41 PM PDT 24
Finished May 19 01:01:17 PM PDT 24
Peak memory 191104 kb
Host smart-cdc2ee1f-85a5-4584-8891-5cc2664f7763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106609856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.106609856
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1853060734
Short name T416
Test name
Test status
Simulation time 473813899047 ps
CPU time 696.72 seconds
Started May 19 01:00:39 PM PDT 24
Finished May 19 01:12:16 PM PDT 24
Peak memory 190832 kb
Host smart-260c4868-d37f-4a1a-a1a0-81d59e5e0574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853060734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1853060734
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.1865655652
Short name T12
Test name
Test status
Simulation time 131678207548 ps
CPU time 245.53 seconds
Started May 19 01:00:39 PM PDT 24
Finished May 19 01:04:45 PM PDT 24
Peak memory 205488 kb
Host smart-101b9409-f056-495d-9f8b-848115193ffb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865655652 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.1865655652
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1377331543
Short name T201
Test name
Test status
Simulation time 468786534315 ps
CPU time 829.04 seconds
Started May 19 01:00:37 PM PDT 24
Finished May 19 01:14:27 PM PDT 24
Peak memory 182644 kb
Host smart-d156e0d5-0b99-4118-a2d1-54425de7c068
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377331543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1377331543
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2788462227
Short name T412
Test name
Test status
Simulation time 207464548616 ps
CPU time 83.58 seconds
Started May 19 01:00:39 PM PDT 24
Finished May 19 01:02:03 PM PDT 24
Peak memory 182620 kb
Host smart-2cac1f87-a9b3-41ed-84e1-9d2ca6069897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788462227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2788462227
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.363493271
Short name T203
Test name
Test status
Simulation time 89509019685 ps
CPU time 197.69 seconds
Started May 19 01:00:41 PM PDT 24
Finished May 19 01:03:59 PM PDT 24
Peak memory 190832 kb
Host smart-a99f825b-39cc-49a3-9a56-476c4ed4b3d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363493271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.363493271
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.32096652
Short name T124
Test name
Test status
Simulation time 55323817462 ps
CPU time 27.32 seconds
Started May 19 01:00:41 PM PDT 24
Finished May 19 01:01:10 PM PDT 24
Peak memory 182648 kb
Host smart-8b98810f-1bbc-468b-ae59-0891a1671b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32096652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.32096652
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.208737262
Short name T224
Test name
Test status
Simulation time 238770825973 ps
CPU time 1266.45 seconds
Started May 19 01:00:47 PM PDT 24
Finished May 19 01:21:54 PM PDT 24
Peak memory 192768 kb
Host smart-82526960-ea9e-4b1d-ab80-f9a50e2d3e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208737262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
208737262
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2895391744
Short name T393
Test name
Test status
Simulation time 51260330729 ps
CPU time 52.4 seconds
Started May 19 01:00:46 PM PDT 24
Finished May 19 01:01:39 PM PDT 24
Peak memory 182616 kb
Host smart-570ccdef-7bf2-485f-abec-fe4daab126cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895391744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2895391744
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1645994875
Short name T421
Test name
Test status
Simulation time 684465766928 ps
CPU time 301.93 seconds
Started May 19 01:00:45 PM PDT 24
Finished May 19 01:05:47 PM PDT 24
Peak memory 182656 kb
Host smart-d781884f-5976-48bf-a962-d167ad1517f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645994875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1645994875
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.464950999
Short name T273
Test name
Test status
Simulation time 60865565436 ps
CPU time 22.73 seconds
Started May 19 01:00:43 PM PDT 24
Finished May 19 01:01:07 PM PDT 24
Peak memory 190800 kb
Host smart-7bbaecb0-2f38-4afa-bacc-14e6750a5592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464950999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.464950999
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2785907715
Short name T350
Test name
Test status
Simulation time 12910307340 ps
CPU time 24.46 seconds
Started May 19 01:00:48 PM PDT 24
Finished May 19 01:01:13 PM PDT 24
Peak memory 190816 kb
Host smart-3af23009-193a-4d5b-b709-adb835489b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785907715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2785907715
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2582999064
Short name T11
Test name
Test status
Simulation time 158524048333 ps
CPU time 313.57 seconds
Started May 19 01:00:48 PM PDT 24
Finished May 19 01:06:02 PM PDT 24
Peak memory 195176 kb
Host smart-877e54d3-2d5a-49d0-bc62-204f47825983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582999064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2582999064
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2414696975
Short name T422
Test name
Test status
Simulation time 11287628187 ps
CPU time 6.98 seconds
Started May 19 01:00:46 PM PDT 24
Finished May 19 01:00:54 PM PDT 24
Peak memory 182516 kb
Host smart-b71ced13-7efb-4ac3-80e4-c13139da8943
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414696975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2414696975
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1714578775
Short name T360
Test name
Test status
Simulation time 113553650155 ps
CPU time 178.73 seconds
Started May 19 01:00:47 PM PDT 24
Finished May 19 01:03:46 PM PDT 24
Peak memory 182640 kb
Host smart-73bf836e-581a-449c-9aa9-edcffed159ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714578775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1714578775
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3078873303
Short name T419
Test name
Test status
Simulation time 220213878335 ps
CPU time 486.42 seconds
Started May 19 01:00:48 PM PDT 24
Finished May 19 01:08:55 PM PDT 24
Peak memory 190796 kb
Host smart-078476d3-089c-46cc-b4af-21ab723199c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078873303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3078873303
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2555028644
Short name T26
Test name
Test status
Simulation time 21649242863 ps
CPU time 35.85 seconds
Started May 19 01:00:47 PM PDT 24
Finished May 19 01:01:23 PM PDT 24
Peak memory 182596 kb
Host smart-acab1252-b1d7-4970-a072-8c574671cde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555028644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2555028644
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1727534363
Short name T60
Test name
Test status
Simulation time 1585007241861 ps
CPU time 715.16 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 01:11:12 PM PDT 24
Peak memory 182536 kb
Host smart-20dafde6-a75c-48b8-8da5-38c903628e45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727534363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1727534363
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1338710435
Short name T378
Test name
Test status
Simulation time 20687135462 ps
CPU time 31.13 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 12:59:48 PM PDT 24
Peak memory 182620 kb
Host smart-200ca535-266d-428c-8d65-f850ae351c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338710435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1338710435
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.747394177
Short name T150
Test name
Test status
Simulation time 241399729967 ps
CPU time 240.59 seconds
Started May 19 12:59:13 PM PDT 24
Finished May 19 01:03:14 PM PDT 24
Peak memory 190792 kb
Host smart-78f7adaa-7d30-4d05-ac4e-25b6478e018b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747394177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.747394177
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2584268272
Short name T195
Test name
Test status
Simulation time 410909436070 ps
CPU time 1662.99 seconds
Started May 19 12:59:14 PM PDT 24
Finished May 19 01:26:58 PM PDT 24
Peak memory 191136 kb
Host smart-9fa1668b-f159-47ec-819e-94170af5e69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584268272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2584268272
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1575477210
Short name T34
Test name
Test status
Simulation time 61621787014 ps
CPU time 100.83 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 01:00:58 PM PDT 24
Peak memory 182572 kb
Host smart-c40b86d6-d654-46bc-b6da-d47f94f331a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575477210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1575477210
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.644193762
Short name T404
Test name
Test status
Simulation time 39767180779 ps
CPU time 1021.31 seconds
Started May 19 01:00:53 PM PDT 24
Finished May 19 01:17:55 PM PDT 24
Peak memory 182632 kb
Host smart-1974bd6c-07e5-4dc6-9289-343501e48910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644193762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.644193762
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3987290796
Short name T129
Test name
Test status
Simulation time 187223574057 ps
CPU time 710.79 seconds
Started May 19 01:00:50 PM PDT 24
Finished May 19 01:12:41 PM PDT 24
Peak memory 190808 kb
Host smart-c055701e-08d3-436f-9361-fe6de8e99296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987290796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3987290796
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.593713381
Short name T222
Test name
Test status
Simulation time 124388363014 ps
CPU time 204.57 seconds
Started May 19 01:00:51 PM PDT 24
Finished May 19 01:04:16 PM PDT 24
Peak memory 190852 kb
Host smart-a0a507c6-4e8e-441d-9437-1926899478ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593713381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.593713381
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3051479976
Short name T441
Test name
Test status
Simulation time 327353032671 ps
CPU time 306.05 seconds
Started May 19 01:00:50 PM PDT 24
Finished May 19 01:05:57 PM PDT 24
Peak memory 190836 kb
Host smart-00dbd690-6cc2-4d74-ae12-f21942dfbc37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051479976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3051479976
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1706537909
Short name T268
Test name
Test status
Simulation time 188254460743 ps
CPU time 193.39 seconds
Started May 19 01:00:54 PM PDT 24
Finished May 19 01:04:07 PM PDT 24
Peak memory 190832 kb
Host smart-8378cedd-15d9-4154-8b6d-1b99ae54ca2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706537909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1706537909
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2753801809
Short name T243
Test name
Test status
Simulation time 979904375651 ps
CPU time 2238.95 seconds
Started May 19 01:00:53 PM PDT 24
Finished May 19 01:38:12 PM PDT 24
Peak memory 190828 kb
Host smart-afc911c5-3989-473a-860c-4e31d4aac256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753801809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2753801809
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1691199934
Short name T311
Test name
Test status
Simulation time 352033160854 ps
CPU time 144.98 seconds
Started May 19 01:00:52 PM PDT 24
Finished May 19 01:03:18 PM PDT 24
Peak memory 190704 kb
Host smart-25ce8de1-fc5e-4b5a-8595-ffc867bed690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691199934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1691199934
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.747932252
Short name T225
Test name
Test status
Simulation time 68448744644 ps
CPU time 148 seconds
Started May 19 01:00:52 PM PDT 24
Finished May 19 01:03:20 PM PDT 24
Peak memory 190808 kb
Host smart-d5e0769c-30c1-4615-ae41-e865121796a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747932252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.747932252
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1260290855
Short name T234
Test name
Test status
Simulation time 302120016549 ps
CPU time 110.92 seconds
Started May 19 01:00:52 PM PDT 24
Finished May 19 01:02:44 PM PDT 24
Peak memory 190828 kb
Host smart-528055be-2963-4575-aee2-4013ae76aef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260290855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1260290855
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1769531339
Short name T140
Test name
Test status
Simulation time 65048254547 ps
CPU time 84.53 seconds
Started May 19 12:59:14 PM PDT 24
Finished May 19 01:00:39 PM PDT 24
Peak memory 182560 kb
Host smart-a20b0b7a-52da-4b8f-8fed-b0f9c62c19b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769531339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1769531339
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1317685549
Short name T372
Test name
Test status
Simulation time 52965861814 ps
CPU time 85.48 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 01:00:41 PM PDT 24
Peak memory 182656 kb
Host smart-c4426fd1-3c49-4397-8ed7-1cad42678dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317685549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1317685549
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2219774231
Short name T322
Test name
Test status
Simulation time 37002515950 ps
CPU time 73.65 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 01:00:30 PM PDT 24
Peak memory 182644 kb
Host smart-aa44d9bd-2575-47fa-907e-2b4ea9966e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219774231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2219774231
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3469160680
Short name T335
Test name
Test status
Simulation time 123513957500 ps
CPU time 203.04 seconds
Started May 19 01:00:51 PM PDT 24
Finished May 19 01:04:15 PM PDT 24
Peak memory 190808 kb
Host smart-4888c601-507e-4f09-9dd3-a143037151e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469160680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3469160680
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1096732965
Short name T329
Test name
Test status
Simulation time 250350325022 ps
CPU time 394.79 seconds
Started May 19 01:00:51 PM PDT 24
Finished May 19 01:07:26 PM PDT 24
Peak memory 190812 kb
Host smart-f0bdc4a8-df55-4096-98c6-e308d3d59ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096732965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1096732965
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1519082247
Short name T250
Test name
Test status
Simulation time 126956265444 ps
CPU time 304.61 seconds
Started May 19 01:00:50 PM PDT 24
Finished May 19 01:05:55 PM PDT 24
Peak memory 191820 kb
Host smart-9840c4ad-26a7-41eb-9152-b99d436dff56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519082247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1519082247
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3674025735
Short name T316
Test name
Test status
Simulation time 205861363481 ps
CPU time 163.89 seconds
Started May 19 01:00:50 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 182584 kb
Host smart-cd3bce60-ef90-45c6-9a02-3cc4b556e6fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674025735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3674025735
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2877640103
Short name T185
Test name
Test status
Simulation time 293196073432 ps
CPU time 1269.13 seconds
Started May 19 01:00:50 PM PDT 24
Finished May 19 01:22:00 PM PDT 24
Peak memory 190812 kb
Host smart-479cbe3a-54d3-4b15-a4fb-f9ab2def7410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877640103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2877640103
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3125600766
Short name T345
Test name
Test status
Simulation time 101973789503 ps
CPU time 197.84 seconds
Started May 19 01:00:52 PM PDT 24
Finished May 19 01:04:10 PM PDT 24
Peak memory 190828 kb
Host smart-88158ac3-ff58-4aff-8e9e-6c878e7c6dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125600766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3125600766
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2076562661
Short name T166
Test name
Test status
Simulation time 149435145511 ps
CPU time 134.31 seconds
Started May 19 01:00:50 PM PDT 24
Finished May 19 01:03:05 PM PDT 24
Peak memory 190780 kb
Host smart-6c82867b-095c-4851-b980-edae9d52f571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076562661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2076562661
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2432768390
Short name T106
Test name
Test status
Simulation time 38638772775 ps
CPU time 17.19 seconds
Started May 19 01:00:55 PM PDT 24
Finished May 19 01:01:12 PM PDT 24
Peak memory 182588 kb
Host smart-784b09de-0b8e-4973-ba97-8bdb5eddfcf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432768390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2432768390
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3389921003
Short name T98
Test name
Test status
Simulation time 141454276201 ps
CPU time 306.49 seconds
Started May 19 01:00:55 PM PDT 24
Finished May 19 01:06:02 PM PDT 24
Peak memory 190844 kb
Host smart-90869176-6c7c-4aef-819e-c8b2dd2439e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389921003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3389921003
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2089868930
Short name T428
Test name
Test status
Simulation time 1302495691054 ps
CPU time 738.16 seconds
Started May 19 12:59:21 PM PDT 24
Finished May 19 01:11:40 PM PDT 24
Peak memory 182636 kb
Host smart-d77a5de3-6f82-4d46-a570-b590ccf49e1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089868930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2089868930
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3515160370
Short name T365
Test name
Test status
Simulation time 813834957024 ps
CPU time 197.94 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 01:02:34 PM PDT 24
Peak memory 182640 kb
Host smart-408ed91d-339e-41e1-b2d0-a15745575e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515160370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3515160370
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.550106844
Short name T411
Test name
Test status
Simulation time 43125253149 ps
CPU time 318.59 seconds
Started May 19 12:59:15 PM PDT 24
Finished May 19 01:04:35 PM PDT 24
Peak memory 182572 kb
Host smart-990f40d3-4f70-4811-b2c3-7bad8e95eae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550106844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.550106844
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.4124905223
Short name T374
Test name
Test status
Simulation time 576667565 ps
CPU time 0.72 seconds
Started May 19 12:59:14 PM PDT 24
Finished May 19 12:59:16 PM PDT 24
Peak memory 182424 kb
Host smart-0c6427f8-aadb-402c-b4de-0015ba025c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124905223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4124905223
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.802906479
Short name T58
Test name
Test status
Simulation time 201539674714 ps
CPU time 190.44 seconds
Started May 19 12:59:32 PM PDT 24
Finished May 19 01:02:43 PM PDT 24
Peak memory 190856 kb
Host smart-1ef2bf22-2ce4-46ba-9d97-af23662ec298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802906479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.802906479
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.1627750780
Short name T438
Test name
Test status
Simulation time 31579739087 ps
CPU time 110.14 seconds
Started May 19 01:00:56 PM PDT 24
Finished May 19 01:02:46 PM PDT 24
Peak memory 182928 kb
Host smart-e808440d-1eda-4f1d-976f-26eebc2a5063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627750780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1627750780
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2801564410
Short name T297
Test name
Test status
Simulation time 2091142069795 ps
CPU time 2612.94 seconds
Started May 19 01:00:54 PM PDT 24
Finished May 19 01:44:28 PM PDT 24
Peak memory 190828 kb
Host smart-743d88f0-7caa-4569-88a6-f5857a87ee47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801564410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2801564410
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1074011814
Short name T144
Test name
Test status
Simulation time 325305974668 ps
CPU time 1408.99 seconds
Started May 19 01:00:56 PM PDT 24
Finished May 19 01:24:25 PM PDT 24
Peak memory 193272 kb
Host smart-7f479dd1-9e48-4a33-b4d4-049483da3a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074011814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1074011814
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2126226153
Short name T353
Test name
Test status
Simulation time 56016307911 ps
CPU time 229.21 seconds
Started May 19 01:00:57 PM PDT 24
Finished May 19 01:04:46 PM PDT 24
Peak memory 182644 kb
Host smart-0c2b093f-2a15-4268-ba66-a5ea6bb5f4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126226153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2126226153
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3205626038
Short name T211
Test name
Test status
Simulation time 98809879413 ps
CPU time 73.07 seconds
Started May 19 01:00:54 PM PDT 24
Finished May 19 01:02:08 PM PDT 24
Peak memory 190836 kb
Host smart-e6dce49c-5931-4671-a7d7-d0e0b983405c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205626038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3205626038
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.881853543
Short name T64
Test name
Test status
Simulation time 270710078534 ps
CPU time 129.55 seconds
Started May 19 01:01:02 PM PDT 24
Finished May 19 01:03:12 PM PDT 24
Peak memory 182572 kb
Host smart-b3db4481-bb95-498c-8e98-5ae64ba652c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881853543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.881853543
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1287950453
Short name T108
Test name
Test status
Simulation time 157472596614 ps
CPU time 141.11 seconds
Started May 19 01:01:07 PM PDT 24
Finished May 19 01:03:29 PM PDT 24
Peak memory 193984 kb
Host smart-52702996-ce5f-4667-903b-b698cbcb5dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287950453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1287950453
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2902136383
Short name T272
Test name
Test status
Simulation time 136846509002 ps
CPU time 481.25 seconds
Started May 19 01:01:00 PM PDT 24
Finished May 19 01:09:02 PM PDT 24
Peak memory 190780 kb
Host smart-08d706c4-dee0-4175-9530-faaa2b11688c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902136383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2902136383
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.4287239394
Short name T151
Test name
Test status
Simulation time 253953302370 ps
CPU time 423.63 seconds
Started May 19 12:59:21 PM PDT 24
Finished May 19 01:06:26 PM PDT 24
Peak memory 182636 kb
Host smart-973f0560-c6af-4c8a-96e1-b4ec2944a05e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287239394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.4287239394
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1038797759
Short name T371
Test name
Test status
Simulation time 189027580271 ps
CPU time 75.49 seconds
Started May 19 12:59:21 PM PDT 24
Finished May 19 01:00:38 PM PDT 24
Peak memory 182624 kb
Host smart-e7b01f82-1de5-4e90-9920-afa19f8c3cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038797759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1038797759
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3099060923
Short name T182
Test name
Test status
Simulation time 430385843139 ps
CPU time 185.42 seconds
Started May 19 12:59:19 PM PDT 24
Finished May 19 01:02:25 PM PDT 24
Peak memory 193020 kb
Host smart-aadbd120-228f-4d0a-8a3b-5966facb6c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099060923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3099060923
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2865378588
Short name T382
Test name
Test status
Simulation time 422281066 ps
CPU time 0.74 seconds
Started May 19 12:59:22 PM PDT 24
Finished May 19 12:59:24 PM PDT 24
Peak memory 182444 kb
Host smart-2b3e6333-44a2-4232-87db-822e8440594c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865378588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2865378588
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3298403257
Short name T220
Test name
Test status
Simulation time 581699812891 ps
CPU time 488.51 seconds
Started May 19 01:01:01 PM PDT 24
Finished May 19 01:09:10 PM PDT 24
Peak memory 190836 kb
Host smart-f215596b-7667-419e-9146-39fa9cd8d11f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298403257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3298403257
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2288528731
Short name T241
Test name
Test status
Simulation time 756054956389 ps
CPU time 722.65 seconds
Started May 19 01:01:07 PM PDT 24
Finished May 19 01:13:10 PM PDT 24
Peak memory 194528 kb
Host smart-83662ad6-2b97-437a-852d-b2fc4c56c766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288528731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2288528731
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3349142222
Short name T216
Test name
Test status
Simulation time 299348108216 ps
CPU time 261.05 seconds
Started May 19 01:01:07 PM PDT 24
Finished May 19 01:05:28 PM PDT 24
Peak memory 191784 kb
Host smart-f86b2f15-6fed-42ab-b3e4-ed27a17e65ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349142222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3349142222
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1006797787
Short name T261
Test name
Test status
Simulation time 136437581310 ps
CPU time 187.49 seconds
Started May 19 01:01:16 PM PDT 24
Finished May 19 01:04:24 PM PDT 24
Peak memory 190744 kb
Host smart-8810fba6-3f0a-41aa-87b5-8da8df44cc4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006797787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1006797787
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.225894874
Short name T139
Test name
Test status
Simulation time 185410172999 ps
CPU time 921.66 seconds
Started May 19 01:01:01 PM PDT 24
Finished May 19 01:16:24 PM PDT 24
Peak memory 190696 kb
Host smart-1196dd54-50ed-4cc8-8399-5d086f3b4e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225894874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.225894874
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1587695165
Short name T258
Test name
Test status
Simulation time 68231220425 ps
CPU time 668.01 seconds
Started May 19 01:01:01 PM PDT 24
Finished May 19 01:12:10 PM PDT 24
Peak memory 195040 kb
Host smart-724cb0a8-a779-44c5-a0a8-99feff8b20ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587695165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1587695165
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1346457627
Short name T202
Test name
Test status
Simulation time 458801326157 ps
CPU time 352.2 seconds
Started May 19 01:01:06 PM PDT 24
Finished May 19 01:06:58 PM PDT 24
Peak memory 190840 kb
Host smart-b0e56599-99c1-436c-a066-bf79b2a08428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346457627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1346457627
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3769462657
Short name T226
Test name
Test status
Simulation time 529611058939 ps
CPU time 759.65 seconds
Started May 19 01:01:07 PM PDT 24
Finished May 19 01:13:47 PM PDT 24
Peak memory 190836 kb
Host smart-80c3a024-9b27-4c5d-ae84-21794aed41f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769462657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3769462657
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3847743516
Short name T107
Test name
Test status
Simulation time 99649141498 ps
CPU time 1520.8 seconds
Started May 19 01:01:05 PM PDT 24
Finished May 19 01:26:26 PM PDT 24
Peak memory 194448 kb
Host smart-0d0e4b2f-d6cb-4f20-bc2e-c2cfc7248c53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847743516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3847743516
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2531778531
Short name T320
Test name
Test status
Simulation time 18014719525 ps
CPU time 16.74 seconds
Started May 19 12:59:20 PM PDT 24
Finished May 19 12:59:38 PM PDT 24
Peak memory 182636 kb
Host smart-ec41b0ef-cc27-48cb-b1bd-5f54489adc41
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531778531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2531778531
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.6475545
Short name T28
Test name
Test status
Simulation time 274089500703 ps
CPU time 111.66 seconds
Started May 19 12:59:22 PM PDT 24
Finished May 19 01:01:15 PM PDT 24
Peak memory 182556 kb
Host smart-c213398d-e366-4dbd-8103-c8325bd92f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6475545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.6475545
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1839552891
Short name T251
Test name
Test status
Simulation time 2003516759926 ps
CPU time 1948.46 seconds
Started May 19 12:59:21 PM PDT 24
Finished May 19 01:31:51 PM PDT 24
Peak memory 190744 kb
Host smart-1e2db91b-7125-4795-95a8-052adc1aba67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839552891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1839552891
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1983322256
Short name T278
Test name
Test status
Simulation time 61909207782 ps
CPU time 241.18 seconds
Started May 19 12:59:33 PM PDT 24
Finished May 19 01:03:35 PM PDT 24
Peak memory 182648 kb
Host smart-a664f081-2dab-4893-b61b-4a35c247370f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983322256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1983322256
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.509769057
Short name T127
Test name
Test status
Simulation time 726183017222 ps
CPU time 986.41 seconds
Started May 19 12:59:19 PM PDT 24
Finished May 19 01:15:46 PM PDT 24
Peak memory 195292 kb
Host smart-fe19740d-1ee8-401b-af8e-aaeb7d28c07a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509769057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.509769057
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.1807525374
Short name T138
Test name
Test status
Simulation time 743397811831 ps
CPU time 523.18 seconds
Started May 19 01:01:08 PM PDT 24
Finished May 19 01:09:51 PM PDT 24
Peak memory 190820 kb
Host smart-0cc792b2-6ee9-4534-bc43-d95c25d80bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807525374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1807525374
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1850472634
Short name T262
Test name
Test status
Simulation time 38497955069 ps
CPU time 56.84 seconds
Started May 19 01:01:06 PM PDT 24
Finished May 19 01:02:03 PM PDT 24
Peak memory 182636 kb
Host smart-5f5c9fbb-ef57-4175-bee7-aecb6aaa7afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850472634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1850472634
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3806854257
Short name T165
Test name
Test status
Simulation time 93646291044 ps
CPU time 302.11 seconds
Started May 19 01:01:07 PM PDT 24
Finished May 19 01:06:10 PM PDT 24
Peak memory 190816 kb
Host smart-c282c3af-aa2e-434a-b097-ca7bf5d3ec23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806854257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3806854257
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3382018539
Short name T449
Test name
Test status
Simulation time 68264692718 ps
CPU time 136.4 seconds
Started May 19 01:01:07 PM PDT 24
Finished May 19 01:03:24 PM PDT 24
Peak memory 190844 kb
Host smart-ec889e64-3bac-4bc2-869b-0079ee5b3a7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382018539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3382018539
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1106804395
Short name T208
Test name
Test status
Simulation time 53871416890 ps
CPU time 74.12 seconds
Started May 19 01:01:06 PM PDT 24
Finished May 19 01:02:20 PM PDT 24
Peak memory 193360 kb
Host smart-bfad34b5-fb1c-471b-a8d6-aebb25b45d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106804395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1106804395
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.4257111859
Short name T204
Test name
Test status
Simulation time 52896649142 ps
CPU time 84.87 seconds
Started May 19 01:01:08 PM PDT 24
Finished May 19 01:02:33 PM PDT 24
Peak memory 190812 kb
Host smart-b2fe671a-154d-4e85-9e94-dc41720ee72b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257111859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.4257111859
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1650791676
Short name T42
Test name
Test status
Simulation time 28300443427 ps
CPU time 154.55 seconds
Started May 19 01:01:13 PM PDT 24
Finished May 19 01:03:48 PM PDT 24
Peak memory 182576 kb
Host smart-d8193e55-d076-4083-a9d2-1a446da3d270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650791676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1650791676
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3983196439
Short name T142
Test name
Test status
Simulation time 58982374550 ps
CPU time 43.61 seconds
Started May 19 01:01:19 PM PDT 24
Finished May 19 01:02:03 PM PDT 24
Peak memory 182564 kb
Host smart-f89526e8-8490-464d-8eab-6256c5fa4179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983196439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3983196439
Directory /workspace/99.rv_timer_random/latest
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