Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
122869590 |
1 |
|
T1 |
217806 |
|
T2 |
163340 |
|
T3 |
8821 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54885832 |
1 |
|
T1 |
127107 |
|
T2 |
163163 |
|
T3 |
2434 |
auto[1] |
67983758 |
1 |
|
T1 |
90699 |
|
T2 |
1771 |
|
T3 |
6387 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
122864080 |
1 |
|
T1 |
217794 |
|
T2 |
163339 |
|
T3 |
8821 |
auto[1] |
5510 |
1 |
|
T1 |
12 |
|
T2 |
7 |
|
T4 |
12 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
54883104 |
1 |
|
T1 |
127101 |
|
T2 |
163162 |
|
T3 |
2434 |
all_values[0] |
auto[0] |
auto[1] |
2728 |
1 |
|
T1 |
6 |
|
T2 |
5 |
|
T4 |
4 |
all_values[0] |
auto[1] |
auto[0] |
67980976 |
1 |
|
T1 |
90693 |
|
T2 |
1769 |
|
T3 |
6387 |
all_values[0] |
auto[1] |
auto[1] |
2782 |
1 |
|
T1 |
6 |
|
T2 |
2 |
|
T4 |
8 |