Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 576
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T505 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2583095034 May 21 12:25:26 PM PDT 24 May 21 12:25:35 PM PDT 24 123638989 ps
T506 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2652924849 May 21 12:25:23 PM PDT 24 May 21 12:25:26 PM PDT 24 17893605 ps
T507 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3265299950 May 21 12:25:24 PM PDT 24 May 21 12:25:30 PM PDT 24 11352542 ps
T508 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1594926020 May 21 12:25:28 PM PDT 24 May 21 12:25:39 PM PDT 24 12971485 ps
T509 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1806880616 May 21 12:25:17 PM PDT 24 May 21 12:25:20 PM PDT 24 112443663 ps
T510 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.886635574 May 21 12:25:29 PM PDT 24 May 21 12:25:44 PM PDT 24 382944844 ps
T511 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1133549939 May 21 12:25:13 PM PDT 24 May 21 12:25:15 PM PDT 24 27398012 ps
T512 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3899760693 May 21 12:25:23 PM PDT 24 May 21 12:25:26 PM PDT 24 44498878 ps
T513 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.245085340 May 21 12:25:22 PM PDT 24 May 21 12:25:25 PM PDT 24 18243115 ps
T514 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1944539722 May 21 12:25:23 PM PDT 24 May 21 12:25:31 PM PDT 24 65914169 ps
T515 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.982301234 May 21 12:25:00 PM PDT 24 May 21 12:25:04 PM PDT 24 21149921 ps
T516 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2836987847 May 21 12:25:24 PM PDT 24 May 21 12:25:30 PM PDT 24 59812473 ps
T517 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.320346175 May 21 12:25:21 PM PDT 24 May 21 12:25:23 PM PDT 24 23548262 ps
T518 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1303014029 May 21 12:25:13 PM PDT 24 May 21 12:25:17 PM PDT 24 680130448 ps
T519 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2711989505 May 21 12:25:23 PM PDT 24 May 21 12:25:30 PM PDT 24 547587676 ps
T520 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2886495030 May 21 12:25:09 PM PDT 24 May 21 12:25:11 PM PDT 24 102965678 ps
T521 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3423916646 May 21 12:25:28 PM PDT 24 May 21 12:25:38 PM PDT 24 110282676 ps
T522 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2528440518 May 21 12:24:53 PM PDT 24 May 21 12:24:54 PM PDT 24 33044451 ps
T523 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3878976855 May 21 12:25:32 PM PDT 24 May 21 12:25:47 PM PDT 24 48984821 ps
T524 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2502278378 May 21 12:25:16 PM PDT 24 May 21 12:25:19 PM PDT 24 339902596 ps
T525 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3139906780 May 21 12:25:31 PM PDT 24 May 21 12:25:45 PM PDT 24 170306241 ps
T526 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1655537382 May 21 12:25:27 PM PDT 24 May 21 12:25:37 PM PDT 24 69416664 ps
T527 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1379092341 May 21 12:25:34 PM PDT 24 May 21 12:25:53 PM PDT 24 45575652 ps
T528 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3827879022 May 21 12:25:08 PM PDT 24 May 21 12:25:10 PM PDT 24 60876965 ps
T529 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3940609442 May 21 12:25:06 PM PDT 24 May 21 12:25:08 PM PDT 24 11287159 ps
T530 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2207347140 May 21 12:25:26 PM PDT 24 May 21 12:25:34 PM PDT 24 49879392 ps
T531 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2849330979 May 21 12:25:02 PM PDT 24 May 21 12:25:05 PM PDT 24 25090385 ps
T532 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.440143779 May 21 12:25:23 PM PDT 24 May 21 12:25:28 PM PDT 24 259141150 ps
T533 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1347779618 May 21 12:25:19 PM PDT 24 May 21 12:25:21 PM PDT 24 110083094 ps
T534 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3157898195 May 21 12:25:31 PM PDT 24 May 21 12:25:47 PM PDT 24 843604124 ps
T535 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3125901862 May 21 12:25:35 PM PDT 24 May 21 12:25:54 PM PDT 24 23203165 ps
T536 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3085353049 May 21 12:25:32 PM PDT 24 May 21 12:25:49 PM PDT 24 323539689 ps
T537 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3406708050 May 21 12:25:31 PM PDT 24 May 21 12:25:47 PM PDT 24 46871789 ps
T538 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.715918038 May 21 12:25:12 PM PDT 24 May 21 12:25:13 PM PDT 24 39584673 ps
T539 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2274807919 May 21 12:25:28 PM PDT 24 May 21 12:25:38 PM PDT 24 118734851 ps
T540 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1552296115 May 21 12:25:32 PM PDT 24 May 21 12:25:47 PM PDT 24 12108621 ps
T541 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1104718847 May 21 12:25:32 PM PDT 24 May 21 12:25:49 PM PDT 24 21629315 ps
T542 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1400127466 May 21 12:25:23 PM PDT 24 May 21 12:25:28 PM PDT 24 13739123 ps
T100 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.4266664869 May 21 12:25:33 PM PDT 24 May 21 12:25:51 PM PDT 24 44409088 ps
T543 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2009629843 May 21 12:25:27 PM PDT 24 May 21 12:25:36 PM PDT 24 29902520 ps
T544 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1713520069 May 21 12:25:19 PM PDT 24 May 21 12:25:21 PM PDT 24 22637163 ps
T545 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3259134824 May 21 12:25:31 PM PDT 24 May 21 12:25:50 PM PDT 24 1492639578 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4081425401 May 21 12:25:09 PM PDT 24 May 21 12:25:11 PM PDT 24 12940284 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1397077088 May 21 12:25:14 PM PDT 24 May 21 12:25:16 PM PDT 24 26561578 ps
T548 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2851409780 May 21 12:25:06 PM PDT 24 May 21 12:25:11 PM PDT 24 322412701 ps
T549 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2072486217 May 21 12:25:09 PM PDT 24 May 21 12:25:11 PM PDT 24 516697072 ps
T550 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1246383328 May 21 12:25:21 PM PDT 24 May 21 12:25:23 PM PDT 24 399021279 ps
T551 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1704125140 May 21 12:25:28 PM PDT 24 May 21 12:25:39 PM PDT 24 102200960 ps
T552 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3048109768 May 21 12:25:26 PM PDT 24 May 21 12:25:34 PM PDT 24 13307303 ps
T553 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1117367431 May 21 12:25:24 PM PDT 24 May 21 12:25:31 PM PDT 24 84991181 ps
T554 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3162111587 May 21 12:25:32 PM PDT 24 May 21 12:25:48 PM PDT 24 16490632 ps
T555 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.511079204 May 21 12:25:21 PM PDT 24 May 21 12:25:24 PM PDT 24 38538420 ps
T556 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1883964851 May 21 12:25:24 PM PDT 24 May 21 12:25:31 PM PDT 24 22095302 ps
T557 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2749988724 May 21 12:25:27 PM PDT 24 May 21 12:25:37 PM PDT 24 188317582 ps
T558 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4146023670 May 21 12:25:23 PM PDT 24 May 21 12:25:28 PM PDT 24 51366921 ps
T559 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1337139569 May 21 12:25:32 PM PDT 24 May 21 12:25:48 PM PDT 24 20227258 ps
T560 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.217002206 May 21 12:24:47 PM PDT 24 May 21 12:24:48 PM PDT 24 41105628 ps
T561 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2506199559 May 21 12:25:01 PM PDT 24 May 21 12:25:05 PM PDT 24 78603301 ps
T562 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3651482092 May 21 12:25:05 PM PDT 24 May 21 12:25:08 PM PDT 24 61101021 ps
T563 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4239495153 May 21 12:25:16 PM PDT 24 May 21 12:25:18 PM PDT 24 22390677 ps
T564 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2012596016 May 21 12:25:33 PM PDT 24 May 21 12:25:52 PM PDT 24 136305832 ps
T565 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1518551059 May 21 12:25:26 PM PDT 24 May 21 12:25:35 PM PDT 24 19512904 ps
T566 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1979284170 May 21 12:25:32 PM PDT 24 May 21 12:25:50 PM PDT 24 27661773 ps
T567 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1129335043 May 21 12:25:31 PM PDT 24 May 21 12:25:47 PM PDT 24 13334640 ps
T568 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3582694327 May 21 12:25:30 PM PDT 24 May 21 12:25:43 PM PDT 24 110593686 ps
T101 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3466716840 May 21 12:25:25 PM PDT 24 May 21 12:25:33 PM PDT 24 17807630 ps
T569 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4277691694 May 21 12:25:14 PM PDT 24 May 21 12:25:17 PM PDT 24 26697648 ps
T570 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1443052284 May 21 12:25:35 PM PDT 24 May 21 12:25:56 PM PDT 24 31313400 ps
T571 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1181021953 May 21 12:25:22 PM PDT 24 May 21 12:25:25 PM PDT 24 19482530 ps
T102 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2965190001 May 21 12:25:14 PM PDT 24 May 21 12:25:16 PM PDT 24 38635197 ps
T572 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2661851746 May 21 12:25:30 PM PDT 24 May 21 12:25:45 PM PDT 24 23193987 ps
T573 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1921315249 May 21 12:25:23 PM PDT 24 May 21 12:25:29 PM PDT 24 27711228 ps
T574 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1338056139 May 21 12:25:16 PM PDT 24 May 21 12:25:21 PM PDT 24 148562493 ps
T575 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.454016608 May 21 12:25:23 PM PDT 24 May 21 12:25:27 PM PDT 24 45001374 ps
T103 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3182629334 May 21 12:25:15 PM PDT 24 May 21 12:25:17 PM PDT 24 12037665 ps
T576 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.304472780 May 21 12:25:33 PM PDT 24 May 21 12:25:51 PM PDT 24 20139187 ps

Test location /workspace/coverage/default/193.rv_timer_random.3621931090
Short name T6
Test name
Test status
Simulation time 223050574475 ps
CPU time 118.75 seconds
Started May 21 01:48:59 PM PDT 24
Finished May 21 01:50:58 PM PDT 24
Peak memory 190844 kb
Host smart-9bca465e-ee3b-4e59-98fd-732ce46298c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621931090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3621931090
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.796542739
Short name T14
Test name
Test status
Simulation time 81694874148 ps
CPU time 605.22 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 01:56:54 PM PDT 24
Peak memory 207532 kb
Host smart-ba8e9b74-db35-424b-9a72-0ae4be8041fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796542739 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.796542739
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.137210117
Short name T33
Test name
Test status
Simulation time 519175597650 ps
CPU time 1891.75 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 02:17:56 PM PDT 24
Peak memory 190852 kb
Host smart-c928b3de-cd87-4e20-9a87-e617a3743d0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137210117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
137210117
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2868225365
Short name T29
Test name
Test status
Simulation time 339004288 ps
CPU time 1.02 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:32 PM PDT 24
Peak memory 183116 kb
Host smart-4b88a782-c327-47de-aa24-8fab565433ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868225365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2868225365
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1169101748
Short name T229
Test name
Test status
Simulation time 1482949217791 ps
CPU time 7048.41 seconds
Started May 21 01:46:20 PM PDT 24
Finished May 21 03:43:51 PM PDT 24
Peak memory 190860 kb
Host smart-2bcf718d-ebdc-4939-97ac-90240ae0568e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169101748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1169101748
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.735841390
Short name T37
Test name
Test status
Simulation time 2374152291270 ps
CPU time 2228.76 seconds
Started May 21 01:46:36 PM PDT 24
Finished May 21 02:23:48 PM PDT 24
Peak memory 190848 kb
Host smart-1def2169-ed24-458b-b37d-fc59b775ecb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735841390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
735841390
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2251294007
Short name T127
Test name
Test status
Simulation time 618298651954 ps
CPU time 3156.18 seconds
Started May 21 01:46:18 PM PDT 24
Finished May 21 02:38:55 PM PDT 24
Peak memory 190848 kb
Host smart-54bd1d4e-4a02-40be-8613-8819bdbdbac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251294007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2251294007
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.203235869
Short name T110
Test name
Test status
Simulation time 575587276464 ps
CPU time 3244.15 seconds
Started May 21 01:46:33 PM PDT 24
Finished May 21 02:40:41 PM PDT 24
Peak memory 195064 kb
Host smart-22b6a9bf-83c7-4f30-964e-3a7bc63732ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203235869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
203235869
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2024022321
Short name T124
Test name
Test status
Simulation time 755253566413 ps
CPU time 2537.19 seconds
Started May 21 01:46:34 PM PDT 24
Finished May 21 02:28:55 PM PDT 24
Peak memory 190860 kb
Host smart-516ac2be-2815-4946-a4be-77423885e1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024022321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2024022321
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4280710081
Short name T35
Test name
Test status
Simulation time 1083749534 ps
CPU time 2.63 seconds
Started May 21 12:25:08 PM PDT 24
Finished May 21 12:25:12 PM PDT 24
Peak memory 190916 kb
Host smart-ee2053a9-4f86-448f-ac38-a938c334b410
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280710081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.4280710081
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1662184161
Short name T184
Test name
Test status
Simulation time 1083207685982 ps
CPU time 2148.01 seconds
Started May 21 01:46:20 PM PDT 24
Finished May 21 02:22:09 PM PDT 24
Peak memory 190888 kb
Host smart-244beb55-904b-47fa-b2b1-f44ca6a6e124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662184161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1662184161
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2489068627
Short name T178
Test name
Test status
Simulation time 3255353241538 ps
CPU time 3068.01 seconds
Started May 21 01:46:50 PM PDT 24
Finished May 21 02:38:02 PM PDT 24
Peak memory 190840 kb
Host smart-3b65ae08-4113-412f-bbab-50055ef23d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489068627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2489068627
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.1687608357
Short name T195
Test name
Test status
Simulation time 325265727510 ps
CPU time 284 seconds
Started May 21 01:46:55 PM PDT 24
Finished May 21 01:51:43 PM PDT 24
Peak memory 190892 kb
Host smart-890089a8-0083-473b-9fc1-bf600d0a0de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687608357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1687608357
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1074622529
Short name T19
Test name
Test status
Simulation time 223699956 ps
CPU time 0.78 seconds
Started May 21 01:46:16 PM PDT 24
Finished May 21 01:46:18 PM PDT 24
Peak memory 213848 kb
Host smart-35c343c1-1d22-47ff-bb8a-aa87306f43a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074622529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1074622529
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3269434554
Short name T72
Test name
Test status
Simulation time 3378376413348 ps
CPU time 1595.02 seconds
Started May 21 01:46:22 PM PDT 24
Finished May 21 02:12:59 PM PDT 24
Peak memory 194952 kb
Host smart-be1e8341-f940-457f-8b4d-a55ae0fc4270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269434554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3269434554
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_random.417703456
Short name T191
Test name
Test status
Simulation time 1686841675186 ps
CPU time 895.11 seconds
Started May 21 01:46:17 PM PDT 24
Finished May 21 02:01:13 PM PDT 24
Peak memory 190844 kb
Host smart-322beb0d-9e0a-4384-b7c1-2fdb10311913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417703456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.417703456
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.394333855
Short name T1
Test name
Test status
Simulation time 127121539525 ps
CPU time 371.86 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:55:35 PM PDT 24
Peak memory 190828 kb
Host smart-205180de-e8f6-4a37-bcdb-6fdfaaca19d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394333855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.394333855
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3165689224
Short name T87
Test name
Test status
Simulation time 2181010513519 ps
CPU time 1522.34 seconds
Started May 21 01:46:37 PM PDT 24
Finished May 21 02:12:02 PM PDT 24
Peak memory 190852 kb
Host smart-5e774cb6-91d0-46d7-8a3b-a3ff642ebb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165689224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3165689224
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/113.rv_timer_random.858899732
Short name T282
Test name
Test status
Simulation time 160918557538 ps
CPU time 257.15 seconds
Started May 21 01:47:04 PM PDT 24
Finished May 21 01:51:23 PM PDT 24
Peak memory 190816 kb
Host smart-037cf40f-b9dc-495e-9cf7-daf5a6843c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858899732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.858899732
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.3343667472
Short name T246
Test name
Test status
Simulation time 171375822428 ps
CPU time 373.83 seconds
Started May 21 01:46:29 PM PDT 24
Finished May 21 01:52:48 PM PDT 24
Peak memory 193396 kb
Host smart-da1e3b2c-3e09-46cf-abc8-27738144116d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343667472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3343667472
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3969244463
Short name T204
Test name
Test status
Simulation time 2064453176490 ps
CPU time 1345.99 seconds
Started May 21 01:46:48 PM PDT 24
Finished May 21 02:09:16 PM PDT 24
Peak memory 195536 kb
Host smart-162fc93b-5713-42f3-a12a-7d73499b46ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969244463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3969244463
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.3278607007
Short name T131
Test name
Test status
Simulation time 109476944773 ps
CPU time 281.13 seconds
Started May 21 01:46:55 PM PDT 24
Finished May 21 01:51:41 PM PDT 24
Peak memory 190828 kb
Host smart-8fb80c1e-3524-497d-a67b-aa4f64a12174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278607007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3278607007
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3317575809
Short name T71
Test name
Test status
Simulation time 653953153431 ps
CPU time 1096.92 seconds
Started May 21 01:46:15 PM PDT 24
Finished May 21 02:04:33 PM PDT 24
Peak memory 190860 kb
Host smart-a49bba40-c7e2-4da2-be8a-564742a810a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317575809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3317575809
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/139.rv_timer_random.2741816292
Short name T111
Test name
Test status
Simulation time 430749548693 ps
CPU time 212.28 seconds
Started May 21 01:47:17 PM PDT 24
Finished May 21 01:50:51 PM PDT 24
Peak memory 190840 kb
Host smart-f751acd8-5d6c-4646-b8bd-7693e24ea24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741816292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2741816292
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1759759865
Short name T226
Test name
Test status
Simulation time 567175640204 ps
CPU time 755.67 seconds
Started May 21 01:47:23 PM PDT 24
Finished May 21 02:00:01 PM PDT 24
Peak memory 190844 kb
Host smart-d2c7e990-a2d3-4c38-9377-1229966685ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759759865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1759759865
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1236203296
Short name T193
Test name
Test status
Simulation time 594981956676 ps
CPU time 385.29 seconds
Started May 21 01:47:25 PM PDT 24
Finished May 21 01:53:51 PM PDT 24
Peak memory 190884 kb
Host smart-eb0a7c20-acbd-424d-b267-76302a87955e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236203296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1236203296
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2102985567
Short name T48
Test name
Test status
Simulation time 194250248664 ps
CPU time 303.29 seconds
Started May 21 01:49:12 PM PDT 24
Finished May 21 01:54:20 PM PDT 24
Peak memory 190852 kb
Host smart-32cf54a5-3529-4e8a-acb8-bd7daefad70a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102985567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2102985567
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3830040785
Short name T173
Test name
Test status
Simulation time 356041654227 ps
CPU time 616.56 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:56:46 PM PDT 24
Peak memory 190808 kb
Host smart-f523a7bf-1fd1-48d5-8577-07e26833b29e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830040785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3830040785
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/173.rv_timer_random.2440170292
Short name T230
Test name
Test status
Simulation time 205000767632 ps
CPU time 360.19 seconds
Started May 21 01:49:02 PM PDT 24
Finished May 21 01:55:04 PM PDT 24
Peak memory 190804 kb
Host smart-c423bb93-c25e-4345-bdbe-4e82b79dc5ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440170292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2440170292
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1689853359
Short name T163
Test name
Test status
Simulation time 196611968990 ps
CPU time 249.93 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:53:30 PM PDT 24
Peak memory 190840 kb
Host smart-c4173d05-786c-479f-beeb-e2a7af4116af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689853359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1689853359
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3039920405
Short name T169
Test name
Test status
Simulation time 664053146728 ps
CPU time 1406.22 seconds
Started May 21 01:46:20 PM PDT 24
Finished May 21 02:09:49 PM PDT 24
Peak memory 193312 kb
Host smart-43da4763-3629-4d67-a6cc-a9d6e57f7c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039920405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3039920405
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.1746288687
Short name T166
Test name
Test status
Simulation time 1144862834343 ps
CPU time 554.85 seconds
Started May 21 01:47:05 PM PDT 24
Finished May 21 01:56:22 PM PDT 24
Peak memory 190880 kb
Host smart-c30b15a8-783c-4ac1-924f-08936eb33264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746288687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1746288687
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2530547773
Short name T251
Test name
Test status
Simulation time 231131011912 ps
CPU time 383.53 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 01:52:46 PM PDT 24
Peak memory 182648 kb
Host smart-39937638-5ed5-4fc1-996b-483f4273fd35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530547773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2530547773
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/170.rv_timer_random.633329346
Short name T315
Test name
Test status
Simulation time 968791892596 ps
CPU time 571.83 seconds
Started May 21 01:48:57 PM PDT 24
Finished May 21 01:58:30 PM PDT 24
Peak memory 190784 kb
Host smart-a4f1c5be-d1f7-481d-920a-5e87b907dad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633329346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.633329346
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1234212239
Short name T243
Test name
Test status
Simulation time 587668811352 ps
CPU time 770.83 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 02:02:10 PM PDT 24
Peak memory 190824 kb
Host smart-37359447-004c-415f-a49c-7151afedbcf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234212239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1234212239
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3408168837
Short name T222
Test name
Test status
Simulation time 360317812637 ps
CPU time 529.97 seconds
Started May 21 01:46:49 PM PDT 24
Finished May 21 01:55:41 PM PDT 24
Peak memory 182644 kb
Host smart-8eb9d2d3-e1b2-4007-a426-faaabc4b72cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408168837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3408168837
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1557668901
Short name T314
Test name
Test status
Simulation time 164600396646 ps
CPU time 262.7 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 01:51:11 PM PDT 24
Peak memory 190788 kb
Host smart-6ec6babe-03ab-4b31-9dab-f0804338b990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557668901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1557668901
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3347532722
Short name T168
Test name
Test status
Simulation time 20497731688 ps
CPU time 38.35 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 01:47:33 PM PDT 24
Peak memory 182608 kb
Host smart-0dd0b426-9db1-4322-8f04-ad9426f4ce59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347532722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3347532722
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/74.rv_timer_random.1483301485
Short name T238
Test name
Test status
Simulation time 1405835201933 ps
CPU time 2016.89 seconds
Started May 21 01:46:58 PM PDT 24
Finished May 21 02:20:39 PM PDT 24
Peak memory 190820 kb
Host smart-42eaf8ad-a5be-4c5c-882b-a353ed9170ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483301485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1483301485
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3058639287
Short name T312
Test name
Test status
Simulation time 289841428087 ps
CPU time 648.08 seconds
Started May 21 01:46:59 PM PDT 24
Finished May 21 01:57:51 PM PDT 24
Peak memory 190884 kb
Host smart-864cd568-281d-4868-97dc-c61b8f5eaeca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058639287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3058639287
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.875067218
Short name T26
Test name
Test status
Simulation time 748557728198 ps
CPU time 470.35 seconds
Started May 21 01:46:14 PM PDT 24
Finished May 21 01:54:05 PM PDT 24
Peak memory 190812 kb
Host smart-65131bd4-113a-42de-8b4e-25967e78c872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875067218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
875067218
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.3577378803
Short name T146
Test name
Test status
Simulation time 246871442976 ps
CPU time 225.09 seconds
Started May 21 01:47:10 PM PDT 24
Finished May 21 01:50:56 PM PDT 24
Peak memory 190808 kb
Host smart-23b6fbdd-7812-4510-993a-a1bb084bd4ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577378803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3577378803
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.852744796
Short name T299
Test name
Test status
Simulation time 93694912058 ps
CPU time 91.66 seconds
Started May 21 01:49:10 PM PDT 24
Finished May 21 01:50:45 PM PDT 24
Peak memory 190888 kb
Host smart-b0db19ff-6dc1-4ee2-94c3-18aa1536b62a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852744796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.852744796
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.116475999
Short name T59
Test name
Test status
Simulation time 563665340771 ps
CPU time 557.95 seconds
Started May 21 01:46:48 PM PDT 24
Finished May 21 01:56:07 PM PDT 24
Peak memory 182676 kb
Host smart-4c4260aa-dedc-4391-8191-92c607a17228
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116475999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.116475999
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3197321772
Short name T266
Test name
Test status
Simulation time 223059196388 ps
CPU time 694.16 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:58:07 PM PDT 24
Peak memory 194844 kb
Host smart-f4d2988f-678b-4b43-8f6b-a2d07b47bce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197321772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3197321772
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/134.rv_timer_random.2765626166
Short name T240
Test name
Test status
Simulation time 1024011316714 ps
CPU time 627.86 seconds
Started May 21 01:47:14 PM PDT 24
Finished May 21 01:57:43 PM PDT 24
Peak memory 190876 kb
Host smart-b7e545dc-6681-4d26-a870-5a188e43ac58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765626166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2765626166
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.161213828
Short name T277
Test name
Test status
Simulation time 397742033836 ps
CPU time 214.17 seconds
Started May 21 01:47:22 PM PDT 24
Finished May 21 01:50:58 PM PDT 24
Peak memory 190820 kb
Host smart-b007bda6-e738-4856-a96e-fc332ec885ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161213828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.161213828
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3270496133
Short name T73
Test name
Test status
Simulation time 166351493731 ps
CPU time 142.4 seconds
Started May 21 01:49:11 PM PDT 24
Finished May 21 01:51:36 PM PDT 24
Peak memory 193076 kb
Host smart-8107354a-121a-4382-9299-541f160785ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270496133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3270496133
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.1768039118
Short name T160
Test name
Test status
Simulation time 780508849873 ps
CPU time 567.74 seconds
Started May 21 01:46:22 PM PDT 24
Finished May 21 01:55:53 PM PDT 24
Peak memory 190848 kb
Host smart-9cd174e2-4b36-4656-9492-ed50d896684c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768039118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1768039118
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3678760363
Short name T69
Test name
Test status
Simulation time 3242841929227 ps
CPU time 1398.48 seconds
Started May 21 01:46:17 PM PDT 24
Finished May 21 02:09:37 PM PDT 24
Peak memory 190836 kb
Host smart-bf06e62d-edf5-4c9b-bbfa-24e1b8860cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678760363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3678760363
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.3714171731
Short name T324
Test name
Test status
Simulation time 440479818787 ps
CPU time 311.37 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:54:35 PM PDT 24
Peak memory 190780 kb
Host smart-e0d76415-0194-41d1-ae69-5209dc71e2b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714171731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3714171731
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3449058287
Short name T219
Test name
Test status
Simulation time 591080911423 ps
CPU time 670.18 seconds
Started May 21 01:49:01 PM PDT 24
Finished May 21 02:00:11 PM PDT 24
Peak memory 192912 kb
Host smart-12ba69d8-bccc-41ec-9b32-d9ecec1dcbaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449058287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3449058287
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.2872099731
Short name T134
Test name
Test status
Simulation time 145715187197 ps
CPU time 2124.9 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 02:21:54 PM PDT 24
Peak memory 190844 kb
Host smart-4a5ae696-5c43-4c29-8507-be1648f1e8f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872099731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2872099731
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.1147793924
Short name T215
Test name
Test status
Simulation time 629820845281 ps
CPU time 392.59 seconds
Started May 21 01:46:31 PM PDT 24
Finished May 21 01:53:08 PM PDT 24
Peak memory 190892 kb
Host smart-a7c4a4b9-def7-4f67-a965-6bbfa447a85d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147793924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1147793924
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.29806009
Short name T212
Test name
Test status
Simulation time 1018335183170 ps
CPU time 530.16 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 01:55:13 PM PDT 24
Peak memory 182680 kb
Host smart-c97c90d8-dced-4480-8e15-09db7d6f12b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
rv_timer_cfg_update_on_fly.29806009
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/99.rv_timer_random.4133242498
Short name T217
Test name
Test status
Simulation time 762409608669 ps
CPU time 606.6 seconds
Started May 21 01:47:04 PM PDT 24
Finished May 21 01:57:13 PM PDT 24
Peak memory 190784 kb
Host smart-1f07b7a4-b7c4-41e4-b601-27c31d2c3ebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133242498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4133242498
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2587642884
Short name T105
Test name
Test status
Simulation time 15030300 ps
CPU time 0.6 seconds
Started May 21 12:25:15 PM PDT 24
Finished May 21 12:25:18 PM PDT 24
Peak memory 191196 kb
Host smart-9509c987-4a1a-4bc6-b90e-a5f72ff4648c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587642884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2587642884
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.rv_timer_random.2254802979
Short name T306
Test name
Test status
Simulation time 559335928383 ps
CPU time 558.52 seconds
Started May 21 01:46:14 PM PDT 24
Finished May 21 01:55:33 PM PDT 24
Peak memory 190812 kb
Host smart-c401cfcc-ee5e-4e62-a123-2fbb96bd2803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254802979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2254802979
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.969160884
Short name T144
Test name
Test status
Simulation time 50518069066 ps
CPU time 81.5 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 01:47:45 PM PDT 24
Peak memory 190844 kb
Host smart-5ccaeef3-7fb8-4979-b2e9-b39e9093568e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969160884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.969160884
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.929302782
Short name T115
Test name
Test status
Simulation time 140288999980 ps
CPU time 318.23 seconds
Started May 21 01:46:58 PM PDT 24
Finished May 21 01:52:20 PM PDT 24
Peak memory 190896 kb
Host smart-714decaf-536f-4691-84ea-23f994d09f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929302782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.929302782
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1008422035
Short name T129
Test name
Test status
Simulation time 551476818148 ps
CPU time 280.66 seconds
Started May 21 01:47:01 PM PDT 24
Finished May 21 01:51:45 PM PDT 24
Peak memory 190820 kb
Host smart-b19739b8-0096-47b3-9533-bc1348353272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008422035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1008422035
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.223501018
Short name T139
Test name
Test status
Simulation time 373456972382 ps
CPU time 350.55 seconds
Started May 21 01:47:03 PM PDT 24
Finished May 21 01:52:56 PM PDT 24
Peak memory 190804 kb
Host smart-1240c42d-19b8-4ed5-aab3-1832007e0cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223501018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.223501018
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3418896734
Short name T152
Test name
Test status
Simulation time 26420822502 ps
CPU time 27.55 seconds
Started May 21 01:46:15 PM PDT 24
Finished May 21 01:46:44 PM PDT 24
Peak memory 182604 kb
Host smart-ae44eab7-a1c8-4849-badb-251465f7c42d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418896734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3418896734
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/147.rv_timer_random.4289247782
Short name T125
Test name
Test status
Simulation time 650052794829 ps
CPU time 442.5 seconds
Started May 21 01:47:14 PM PDT 24
Finished May 21 01:54:38 PM PDT 24
Peak memory 190844 kb
Host smart-f0b08ead-3ac0-4df4-8f6d-03b2d79c6516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289247782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4289247782
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3969021670
Short name T272
Test name
Test status
Simulation time 131140739429 ps
CPU time 246.68 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:53:29 PM PDT 24
Peak memory 194504 kb
Host smart-63b9a346-5615-47db-bb94-d0be69c80072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969021670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3969021670
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2464803855
Short name T189
Test name
Test status
Simulation time 91334568356 ps
CPU time 183.95 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:52:26 PM PDT 24
Peak memory 190884 kb
Host smart-742de99d-440a-4885-b57c-8029b7802cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464803855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2464803855
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1439105442
Short name T268
Test name
Test status
Simulation time 188684754331 ps
CPU time 1506.28 seconds
Started May 21 01:49:07 PM PDT 24
Finished May 21 02:14:16 PM PDT 24
Peak memory 190844 kb
Host smart-09791495-e78f-497a-84cf-53ee8493f921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439105442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1439105442
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3411054798
Short name T201
Test name
Test status
Simulation time 33695979412 ps
CPU time 530.07 seconds
Started May 21 01:49:07 PM PDT 24
Finished May 21 01:57:59 PM PDT 24
Peak memory 190744 kb
Host smart-47c59965-3aa9-4432-80a8-0062680e6cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411054798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3411054798
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.325098190
Short name T297
Test name
Test status
Simulation time 370211443194 ps
CPU time 193.16 seconds
Started May 21 01:46:48 PM PDT 24
Finished May 21 01:50:03 PM PDT 24
Peak memory 182596 kb
Host smart-eec606be-a458-4824-8a3d-31c545fef4ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325098190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.325098190
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random.1376405767
Short name T180
Test name
Test status
Simulation time 167164910678 ps
CPU time 175.58 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:49:41 PM PDT 24
Peak memory 190840 kb
Host smart-7b5c2443-d1ea-4611-93cd-ad313d4b40b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376405767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1376405767
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random.90804724
Short name T151
Test name
Test status
Simulation time 181315891760 ps
CPU time 850.03 seconds
Started May 21 01:46:17 PM PDT 24
Finished May 21 02:00:28 PM PDT 24
Peak memory 191100 kb
Host smart-14039450-333e-4ef5-a3fe-dfb865487a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90804724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.90804724
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1363472944
Short name T148
Test name
Test status
Simulation time 155599061599 ps
CPU time 263.26 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 01:50:46 PM PDT 24
Peak memory 190892 kb
Host smart-3796377f-327a-4c69-9959-28f686a9221a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363472944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1363472944
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/57.rv_timer_random.2550822848
Short name T199
Test name
Test status
Simulation time 1732720350057 ps
CPU time 470.79 seconds
Started May 21 01:46:53 PM PDT 24
Finished May 21 01:54:48 PM PDT 24
Peak memory 190892 kb
Host smart-095a6320-e5f1-4a26-8aab-95fbcefce77e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550822848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2550822848
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2072486217
Short name T549
Test name
Test status
Simulation time 516697072 ps
CPU time 1.31 seconds
Started May 21 12:25:09 PM PDT 24
Finished May 21 12:25:11 PM PDT 24
Peak memory 194232 kb
Host smart-3c276a78-0afa-4e74-94ba-b4a485050154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072486217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2072486217
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/104.rv_timer_random.3562057775
Short name T322
Test name
Test status
Simulation time 84796953642 ps
CPU time 93.91 seconds
Started May 21 01:47:02 PM PDT 24
Finished May 21 01:48:39 PM PDT 24
Peak memory 190780 kb
Host smart-20833767-b20d-4e64-8004-be46e9e76486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562057775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3562057775
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2137114968
Short name T23
Test name
Test status
Simulation time 121566484365 ps
CPU time 193.78 seconds
Started May 21 01:47:03 PM PDT 24
Finished May 21 01:50:20 PM PDT 24
Peak memory 190808 kb
Host smart-275b6ccd-ce2b-43a9-916e-5a299ee133da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137114968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2137114968
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2654628435
Short name T336
Test name
Test status
Simulation time 114631453859 ps
CPU time 190.16 seconds
Started May 21 01:47:03 PM PDT 24
Finished May 21 01:50:15 PM PDT 24
Peak memory 182652 kb
Host smart-fcbdb2de-4ea3-488c-81e9-34e254e04669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654628435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2654628435
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2274205451
Short name T298
Test name
Test status
Simulation time 1017318336359 ps
CPU time 290.38 seconds
Started May 21 01:47:10 PM PDT 24
Finished May 21 01:52:02 PM PDT 24
Peak memory 190764 kb
Host smart-77014a6a-9a37-4646-89c4-7a403e6ad642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274205451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2274205451
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3261571363
Short name T356
Test name
Test status
Simulation time 810783222 ps
CPU time 0.89 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:46:28 PM PDT 24
Peak memory 192300 kb
Host smart-f02faffb-1df2-4468-a037-40d650501431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261571363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3261571363
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.3761115427
Short name T304
Test name
Test status
Simulation time 147076401039 ps
CPU time 430.18 seconds
Started May 21 01:47:16 PM PDT 24
Finished May 21 01:54:27 PM PDT 24
Peak memory 190772 kb
Host smart-4f4a268c-2e28-4f8d-a824-435acf684bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761115427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3761115427
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.949969385
Short name T62
Test name
Test status
Simulation time 1641247481302 ps
CPU time 475.11 seconds
Started May 21 01:47:15 PM PDT 24
Finished May 21 01:55:12 PM PDT 24
Peak memory 190760 kb
Host smart-7e4197d6-cfe7-45b5-af95-8f6cb3d9c792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949969385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.949969385
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2463575807
Short name T335
Test name
Test status
Simulation time 343602055011 ps
CPU time 419.04 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:56:17 PM PDT 24
Peak memory 190828 kb
Host smart-f3a079a2-3381-4502-90b5-bf59d134c7c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463575807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2463575807
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2553041994
Short name T276
Test name
Test status
Simulation time 57559402463 ps
CPU time 82.36 seconds
Started May 21 01:46:36 PM PDT 24
Finished May 21 01:48:01 PM PDT 24
Peak memory 182616 kb
Host smart-d7eecc99-1e6c-4233-8a4d-f120097ef7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553041994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2553041994
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/175.rv_timer_random.1995432902
Short name T275
Test name
Test status
Simulation time 269649084378 ps
CPU time 832.08 seconds
Started May 21 01:49:07 PM PDT 24
Finished May 21 02:03:02 PM PDT 24
Peak memory 190836 kb
Host smart-cc49cd19-f8a6-4c8c-958a-2ac73ce18447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995432902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1995432902
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.940119645
Short name T265
Test name
Test status
Simulation time 253701238909 ps
CPU time 382.93 seconds
Started May 21 01:49:14 PM PDT 24
Finished May 21 01:55:43 PM PDT 24
Peak memory 193516 kb
Host smart-164a8a00-c403-437f-8949-fed1385c9bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940119645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.940119645
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2521270512
Short name T329
Test name
Test status
Simulation time 38638088668 ps
CPU time 61.72 seconds
Started May 21 01:46:46 PM PDT 24
Finished May 21 01:47:49 PM PDT 24
Peak memory 190856 kb
Host smart-1a5a8c3f-6471-493f-aae8-f68621e35cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521270512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2521270512
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3143379500
Short name T235
Test name
Test status
Simulation time 565120629953 ps
CPU time 171.38 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:49:21 PM PDT 24
Peak memory 190820 kb
Host smart-856cadd5-21f7-4167-b29e-1e26364ddc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143379500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3143379500
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1633132079
Short name T214
Test name
Test status
Simulation time 1066409671204 ps
CPU time 848.56 seconds
Started May 21 01:46:22 PM PDT 24
Finished May 21 02:00:34 PM PDT 24
Peak memory 190788 kb
Host smart-69c6aa4c-56aa-4405-8e3a-dee5fdd837fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633132079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1633132079
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.2423768236
Short name T208
Test name
Test status
Simulation time 86293176819 ps
CPU time 150.59 seconds
Started May 21 01:46:34 PM PDT 24
Finished May 21 01:49:08 PM PDT 24
Peak memory 192876 kb
Host smart-ff8a39ca-c68f-4c8d-a03c-73e3d7750fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423768236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2423768236
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3642721102
Short name T175
Test name
Test status
Simulation time 574484490293 ps
CPU time 2250.14 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 02:24:25 PM PDT 24
Peak memory 190800 kb
Host smart-891b7a8f-29cf-4db3-866b-1357149a0eea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642721102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3642721102
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3410453261
Short name T200
Test name
Test status
Simulation time 117186310099 ps
CPU time 48.03 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 01:47:42 PM PDT 24
Peak memory 182688 kb
Host smart-2106d5bf-576b-43ef-9d83-21e1ef345499
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410453261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3410453261
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/55.rv_timer_random.1127061250
Short name T248
Test name
Test status
Simulation time 704293617573 ps
CPU time 398 seconds
Started May 21 01:46:55 PM PDT 24
Finished May 21 01:53:37 PM PDT 24
Peak memory 190848 kb
Host smart-0aaae709-d430-4a68-8e24-0975d9d17fd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127061250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1127061250
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.718474644
Short name T325
Test name
Test status
Simulation time 107917092489 ps
CPU time 194.89 seconds
Started May 21 01:46:52 PM PDT 24
Finished May 21 01:50:10 PM PDT 24
Peak memory 190872 kb
Host smart-2c49617b-6cff-4293-875b-521d31909dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718474644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.718474644
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.764087303
Short name T481
Test name
Test status
Simulation time 23920845 ps
CPU time 0.75 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:38 PM PDT 24
Peak memory 182452 kb
Host smart-d48263ca-3e26-4170-9221-5a5c1e1e230b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764087303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.764087303
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1314470671
Short name T80
Test name
Test status
Simulation time 1157561322 ps
CPU time 3.57 seconds
Started May 21 12:25:08 PM PDT 24
Finished May 21 12:25:13 PM PDT 24
Peak memory 190052 kb
Host smart-6c4d7106-4915-4a91-a9b2-12b4546679b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314470671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1314470671
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.222180446
Short name T92
Test name
Test status
Simulation time 40743709 ps
CPU time 0.58 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:26 PM PDT 24
Peak memory 182488 kb
Host smart-e0e5d5de-3be4-4a48-a93c-c5bccb7f4b62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222180446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.222180446
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3430620408
Short name T479
Test name
Test status
Simulation time 72180336 ps
CPU time 0.72 seconds
Started May 21 12:25:00 PM PDT 24
Finished May 21 12:25:02 PM PDT 24
Peak memory 195324 kb
Host smart-c5720bd8-102f-4095-826b-1ab5c62f3f67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430620408 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3430620408
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1727046315
Short name T56
Test name
Test status
Simulation time 29050580 ps
CPU time 0.58 seconds
Started May 21 12:25:06 PM PDT 24
Finished May 21 12:25:09 PM PDT 24
Peak memory 182568 kb
Host smart-8a6fb11f-dbf2-4e61-b54e-c59d14e5c91a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727046315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1727046315
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1102275759
Short name T492
Test name
Test status
Simulation time 10886851 ps
CPU time 0.55 seconds
Started May 21 12:25:18 PM PDT 24
Finished May 21 12:25:20 PM PDT 24
Peak memory 182416 kb
Host smart-eb0ca26e-b8c5-46cd-b8f0-08571788b0cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102275759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1102275759
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1944539722
Short name T514
Test name
Test status
Simulation time 65914169 ps
CPU time 2.92 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:31 PM PDT 24
Peak memory 197420 kb
Host smart-01e6f610-8fb8-4233-b0ab-531a5832a36a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944539722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1944539722
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.330013812
Short name T98
Test name
Test status
Simulation time 87666330 ps
CPU time 0.8 seconds
Started May 21 12:24:59 PM PDT 24
Finished May 21 12:25:02 PM PDT 24
Peak memory 192284 kb
Host smart-1a6c7c94-86e9-4828-bcef-6a95ccdb51a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330013812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.330013812
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.627181800
Short name T470
Test name
Test status
Simulation time 401217716 ps
CPU time 2.63 seconds
Started May 21 12:24:57 PM PDT 24
Finished May 21 12:25:01 PM PDT 24
Peak memory 193652 kb
Host smart-df83ea29-867a-4420-bc8e-4f819553986b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627181800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.627181800
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2965190001
Short name T102
Test name
Test status
Simulation time 38635197 ps
CPU time 0.64 seconds
Started May 21 12:25:14 PM PDT 24
Finished May 21 12:25:16 PM PDT 24
Peak memory 182504 kb
Host smart-41297d6b-3a55-4650-b149-bb041250b833
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965190001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2965190001
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4146023670
Short name T558
Test name
Test status
Simulation time 51366921 ps
CPU time 1.02 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:28 PM PDT 24
Peak memory 197276 kb
Host smart-1153fa75-2bf2-4605-9b77-d209dcedc7f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146023670 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4146023670
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.982301234
Short name T515
Test name
Test status
Simulation time 21149921 ps
CPU time 0.54 seconds
Started May 21 12:25:00 PM PDT 24
Finished May 21 12:25:04 PM PDT 24
Peak memory 182544 kb
Host smart-cd8a0c6b-ed20-4595-8eeb-c02d71efb3c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982301234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.982301234
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4276662737
Short name T467
Test name
Test status
Simulation time 51003172 ps
CPU time 0.55 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:54 PM PDT 24
Peak memory 182440 kb
Host smart-984af637-9b73-4960-863f-74c0f02afdc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276662737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4276662737
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3356529075
Short name T499
Test name
Test status
Simulation time 55403085 ps
CPU time 0.6 seconds
Started May 21 12:25:08 PM PDT 24
Finished May 21 12:25:10 PM PDT 24
Peak memory 191104 kb
Host smart-1c2716e7-0d10-49cf-9530-3f1282f69bf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356529075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3356529075
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.317587279
Short name T461
Test name
Test status
Simulation time 75393495 ps
CPU time 1.64 seconds
Started May 21 12:24:34 PM PDT 24
Finished May 21 12:24:36 PM PDT 24
Peak memory 197376 kb
Host smart-b0dc1390-bcd5-4a95-a00d-a857988a0c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317587279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.317587279
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2827452629
Short name T473
Test name
Test status
Simulation time 48399165 ps
CPU time 0.82 seconds
Started May 21 12:24:58 PM PDT 24
Finished May 21 12:24:59 PM PDT 24
Peak memory 182996 kb
Host smart-5ee15bfb-04e1-417f-b4ac-b0baffa076da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827452629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2827452629
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1397077088
Short name T547
Test name
Test status
Simulation time 26561578 ps
CPU time 0.81 seconds
Started May 21 12:25:14 PM PDT 24
Finished May 21 12:25:16 PM PDT 24
Peak memory 195280 kb
Host smart-7eccb438-3c88-4795-a46d-8947b3111e9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397077088 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1397077088
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.185174389
Short name T52
Test name
Test status
Simulation time 55250337 ps
CPU time 0.58 seconds
Started May 21 12:25:04 PM PDT 24
Finished May 21 12:25:06 PM PDT 24
Peak memory 182480 kb
Host smart-3e810899-21e4-4259-9520-51b8e8466aeb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185174389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.185174389
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2127788584
Short name T493
Test name
Test status
Simulation time 39291260 ps
CPU time 0.54 seconds
Started May 21 12:25:14 PM PDT 24
Finished May 21 12:25:17 PM PDT 24
Peak memory 181984 kb
Host smart-49c5f195-fb33-4df3-b438-ff161da2d13c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127788584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2127788584
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4277691694
Short name T569
Test name
Test status
Simulation time 26697648 ps
CPU time 0.7 seconds
Started May 21 12:25:14 PM PDT 24
Finished May 21 12:25:17 PM PDT 24
Peak memory 191532 kb
Host smart-fa1b271d-c96b-4f12-bd80-ba81786fd6f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277691694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4277691694
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3085353049
Short name T536
Test name
Test status
Simulation time 323539689 ps
CPU time 1.46 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:49 PM PDT 24
Peak memory 197440 kb
Host smart-f879bfb6-6a79-4e7c-8d64-c75d35480e7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085353049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3085353049
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3157898195
Short name T534
Test name
Test status
Simulation time 843604124 ps
CPU time 0.8 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:47 PM PDT 24
Peak memory 193496 kb
Host smart-da157566-4fc5-46ac-a798-72f54e0d2f64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157898195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3157898195
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3491783008
Short name T452
Test name
Test status
Simulation time 71160965 ps
CPU time 0.71 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:48 PM PDT 24
Peak memory 195312 kb
Host smart-0bcded58-69e9-45be-97b5-31595c363053
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491783008 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3491783008
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1400750078
Short name T94
Test name
Test status
Simulation time 33584661 ps
CPU time 0.57 seconds
Started May 21 12:25:05 PM PDT 24
Finished May 21 12:25:08 PM PDT 24
Peak memory 182492 kb
Host smart-52594596-e873-4c4c-8c16-e7995bfbbe42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400750078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1400750078
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.563833664
Short name T496
Test name
Test status
Simulation time 45546930 ps
CPU time 0.52 seconds
Started May 21 12:25:01 PM PDT 24
Finished May 21 12:25:04 PM PDT 24
Peak memory 182008 kb
Host smart-840eaa66-a9e9-4856-b547-ecd0200fbdca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563833664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.563833664
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2824166038
Short name T108
Test name
Test status
Simulation time 116149271 ps
CPU time 0.83 seconds
Started May 21 12:25:12 PM PDT 24
Finished May 21 12:25:15 PM PDT 24
Peak memory 193032 kb
Host smart-9d8a3626-2669-4ae3-80a5-d89e64736b0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824166038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2824166038
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2851409780
Short name T548
Test name
Test status
Simulation time 322412701 ps
CPU time 2.57 seconds
Started May 21 12:25:06 PM PDT 24
Finished May 21 12:25:11 PM PDT 24
Peak memory 197476 kb
Host smart-eb024f18-7bf1-413f-8b4b-8c40c8c7fb5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851409780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2851409780
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3543679398
Short name T483
Test name
Test status
Simulation time 86338867 ps
CPU time 0.8 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:28 PM PDT 24
Peak memory 193220 kb
Host smart-debf729d-ed68-4651-80be-f6d9e8019273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543679398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3543679398
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.289691120
Short name T485
Test name
Test status
Simulation time 26654487 ps
CPU time 1.3 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:38 PM PDT 24
Peak memory 197428 kb
Host smart-1a138cd1-20d5-4140-b586-bd46b0535e34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289691120 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.289691120
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.715918038
Short name T538
Test name
Test status
Simulation time 39584673 ps
CPU time 0.53 seconds
Started May 21 12:25:12 PM PDT 24
Finished May 21 12:25:13 PM PDT 24
Peak memory 182152 kb
Host smart-0f14e622-27ef-4f07-b665-10499927f361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715918038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.715918038
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1713520069
Short name T544
Test name
Test status
Simulation time 22637163 ps
CPU time 0.53 seconds
Started May 21 12:25:19 PM PDT 24
Finished May 21 12:25:21 PM PDT 24
Peak memory 181808 kb
Host smart-4959789d-432f-4d5d-92c2-05b375661ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713520069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1713520069
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3735430267
Short name T107
Test name
Test status
Simulation time 21773417 ps
CPU time 0.59 seconds
Started May 21 12:25:12 PM PDT 24
Finished May 21 12:25:13 PM PDT 24
Peak memory 191160 kb
Host smart-211cd1c9-301f-4667-a23c-9613df8f21ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735430267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3735430267
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.214479132
Short name T455
Test name
Test status
Simulation time 159707952 ps
CPU time 2.83 seconds
Started May 21 12:25:03 PM PDT 24
Finished May 21 12:25:07 PM PDT 24
Peak memory 197580 kb
Host smart-0b7b0143-16ed-479e-bbe4-ce94f036a770
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214479132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.214479132
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3242641849
Short name T30
Test name
Test status
Simulation time 514305130 ps
CPU time 0.8 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:39 PM PDT 24
Peak memory 182792 kb
Host smart-6ec3bcf6-fb3c-44fd-9b5d-7e92f88c8b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242641849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3242641849
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1289093201
Short name T497
Test name
Test status
Simulation time 18372238 ps
CPU time 0.74 seconds
Started May 21 12:25:04 PM PDT 24
Finished May 21 12:25:07 PM PDT 24
Peak memory 195696 kb
Host smart-12378b2c-f274-4928-8b3b-8c78751c8519
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289093201 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1289093201
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3351570297
Short name T487
Test name
Test status
Simulation time 46774305 ps
CPU time 0.54 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 182504 kb
Host smart-2730805d-cd8f-4004-85f4-7a1b0838da76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351570297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3351570297
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3940609442
Short name T529
Test name
Test status
Simulation time 11287159 ps
CPU time 0.51 seconds
Started May 21 12:25:06 PM PDT 24
Finished May 21 12:25:08 PM PDT 24
Peak memory 182096 kb
Host smart-431b3f01-43b3-430d-9058-50873a6434e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940609442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3940609442
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2012596016
Short name T564
Test name
Test status
Simulation time 136305832 ps
CPU time 0.75 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 191308 kb
Host smart-8f439cc8-f3b9-4b84-864e-62869db2d2b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012596016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2012596016
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2273064023
Short name T477
Test name
Test status
Simulation time 238619981 ps
CPU time 1.32 seconds
Started May 21 12:25:17 PM PDT 24
Finished May 21 12:25:20 PM PDT 24
Peak memory 197456 kb
Host smart-d1fb23b5-aa5d-4be6-9203-7d7350c1f51b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273064023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2273064023
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.307486222
Short name T123
Test name
Test status
Simulation time 156686810 ps
CPU time 0.81 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 183020 kb
Host smart-2a79c15c-1568-4328-b29b-a98ca7daa886
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307486222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.307486222
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4147594746
Short name T459
Test name
Test status
Simulation time 130755807 ps
CPU time 1.53 seconds
Started May 21 12:25:21 PM PDT 24
Finished May 21 12:25:25 PM PDT 24
Peak memory 197392 kb
Host smart-7e17a0f0-cfc8-4b0d-96b8-ee9dccd784f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147594746 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4147594746
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3182629334
Short name T103
Test name
Test status
Simulation time 12037665 ps
CPU time 0.61 seconds
Started May 21 12:25:15 PM PDT 24
Finished May 21 12:25:17 PM PDT 24
Peak memory 182492 kb
Host smart-55999c8c-83a9-434b-bf8b-ebb2c99320d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182629334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3182629334
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1117367431
Short name T553
Test name
Test status
Simulation time 84991181 ps
CPU time 0.54 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:31 PM PDT 24
Peak memory 182480 kb
Host smart-20cc3d64-30a6-44e0-acf3-bee8030ccb76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117367431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1117367431
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.304472780
Short name T576
Test name
Test status
Simulation time 20139187 ps
CPU time 0.66 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 192556 kb
Host smart-76a94b86-fc33-454d-87d3-af9de94d5f39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304472780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.304472780
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1338056139
Short name T574
Test name
Test status
Simulation time 148562493 ps
CPU time 3.12 seconds
Started May 21 12:25:16 PM PDT 24
Finished May 21 12:25:21 PM PDT 24
Peak memory 191268 kb
Host smart-b51d5d81-f6d2-4ef8-aacc-5694b7de6453
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338056139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1338056139
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2749988724
Short name T557
Test name
Test status
Simulation time 188317582 ps
CPU time 1.08 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:37 PM PDT 24
Peak memory 194804 kb
Host smart-27de930c-8d06-4580-b0e8-23b3137d373d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749988724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2749988724
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2886495030
Short name T520
Test name
Test status
Simulation time 102965678 ps
CPU time 0.71 seconds
Started May 21 12:25:09 PM PDT 24
Finished May 21 12:25:11 PM PDT 24
Peak memory 195184 kb
Host smart-551c6d27-841c-4f5e-9a46-ccac5edb12e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886495030 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2886495030
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2044235704
Short name T463
Test name
Test status
Simulation time 47686582 ps
CPU time 0.64 seconds
Started May 21 12:25:21 PM PDT 24
Finished May 21 12:25:23 PM PDT 24
Peak memory 182512 kb
Host smart-d84658ef-845d-4c49-bb6a-26a8ef2bebdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044235704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2044235704
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2849330979
Short name T531
Test name
Test status
Simulation time 25090385 ps
CPU time 0.6 seconds
Started May 21 12:25:02 PM PDT 24
Finished May 21 12:25:05 PM PDT 24
Peak memory 181676 kb
Host smart-d560b738-2b57-4a20-a1c1-e943f23a1270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849330979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2849330979
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3935747474
Short name T106
Test name
Test status
Simulation time 83407659 ps
CPU time 0.83 seconds
Started May 21 12:25:20 PM PDT 24
Finished May 21 12:25:22 PM PDT 24
Peak memory 191472 kb
Host smart-07b877a1-6d42-41a2-bfe5-96d85bf6e4fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935747474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3935747474
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1303014029
Short name T518
Test name
Test status
Simulation time 680130448 ps
CPU time 2.91 seconds
Started May 21 12:25:13 PM PDT 24
Finished May 21 12:25:17 PM PDT 24
Peak memory 197396 kb
Host smart-8d945942-e9e5-4ce1-b4a0-3d408a6410ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303014029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1303014029
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2064739517
Short name T118
Test name
Test status
Simulation time 88958483 ps
CPU time 1.04 seconds
Started May 21 12:25:30 PM PDT 24
Finished May 21 12:25:45 PM PDT 24
Peak memory 195296 kb
Host smart-6d636bc6-b14c-4fbe-a509-23d80f072d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064739517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2064739517
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3678101858
Short name T494
Test name
Test status
Simulation time 22777054 ps
CPU time 0.7 seconds
Started May 21 12:25:21 PM PDT 24
Finished May 21 12:25:24 PM PDT 24
Peak memory 194276 kb
Host smart-3b7b602f-c59d-4da4-a85d-7ef69afd880c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678101858 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3678101858
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2207347140
Short name T530
Test name
Test status
Simulation time 49879392 ps
CPU time 0.56 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:34 PM PDT 24
Peak memory 182552 kb
Host smart-431c5f8f-e5ec-4b25-93b9-273513cc5f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207347140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2207347140
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1379092341
Short name T527
Test name
Test status
Simulation time 45575652 ps
CPU time 0.53 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:25:53 PM PDT 24
Peak memory 181896 kb
Host smart-68065aa1-dc61-4b69-87cf-04d9774b8c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379092341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1379092341
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1001721077
Short name T504
Test name
Test status
Simulation time 52621115 ps
CPU time 0.58 seconds
Started May 21 12:25:19 PM PDT 24
Finished May 21 12:25:21 PM PDT 24
Peak memory 191176 kb
Host smart-aeb3342d-9edb-48c0-819f-9b9aed084f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001721077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1001721077
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2496801016
Short name T468
Test name
Test status
Simulation time 249166774 ps
CPU time 2.59 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:38 PM PDT 24
Peak memory 197416 kb
Host smart-0c862b2f-227d-4712-8a60-a72d5066b220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496801016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2496801016
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1747367206
Short name T31
Test name
Test status
Simulation time 123737920 ps
CPU time 1.49 seconds
Started May 21 12:25:11 PM PDT 24
Finished May 21 12:25:13 PM PDT 24
Peak memory 183240 kb
Host smart-c4340589-749c-4a9c-8154-120439806692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747367206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1747367206
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1181021953
Short name T571
Test name
Test status
Simulation time 19482530 ps
CPU time 0.62 seconds
Started May 21 12:25:22 PM PDT 24
Finished May 21 12:25:25 PM PDT 24
Peak memory 192768 kb
Host smart-e22d2789-3935-4935-abc2-d6e4248a44d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181021953 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1181021953
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1400127466
Short name T542
Test name
Test status
Simulation time 13739123 ps
CPU time 0.59 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:28 PM PDT 24
Peak memory 182572 kb
Host smart-2a539517-9bd5-474d-9793-5b94bf78445d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400127466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1400127466
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1443052284
Short name T570
Test name
Test status
Simulation time 31313400 ps
CPU time 0.62 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:56 PM PDT 24
Peak memory 182212 kb
Host smart-a4343a2f-b87d-4f32-9ce1-0ab7f2c58e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443052284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1443052284
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1337139569
Short name T559
Test name
Test status
Simulation time 20227258 ps
CPU time 0.62 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:48 PM PDT 24
Peak memory 191960 kb
Host smart-f3098b91-3388-4203-ab09-bfa9d4da77f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337139569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1337139569
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2583095034
Short name T505
Test name
Test status
Simulation time 123638989 ps
CPU time 1.65 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:35 PM PDT 24
Peak memory 197452 kb
Host smart-2dddc211-9389-4046-88ce-0625daa362c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583095034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2583095034
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2379831039
Short name T120
Test name
Test status
Simulation time 1130475952 ps
CPU time 0.83 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:31 PM PDT 24
Peak memory 182784 kb
Host smart-a173a7a8-06b8-4237-828d-1e61bb4ebeb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379831039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2379831039
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.511079204
Short name T555
Test name
Test status
Simulation time 38538420 ps
CPU time 0.94 seconds
Started May 21 12:25:21 PM PDT 24
Finished May 21 12:25:24 PM PDT 24
Peak memory 197196 kb
Host smart-9ee4832e-a226-4a5b-bf57-0507af001ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511079204 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.511079204
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1987422993
Short name T99
Test name
Test status
Simulation time 16547080 ps
CPU time 0.54 seconds
Started May 21 12:25:21 PM PDT 24
Finished May 21 12:25:23 PM PDT 24
Peak memory 182492 kb
Host smart-4ae655ab-8980-41f3-b99d-8597ab57d414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987422993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1987422993
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2836987847
Short name T516
Test name
Test status
Simulation time 59812473 ps
CPU time 0.56 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:30 PM PDT 24
Peak memory 182396 kb
Host smart-ddbfd36d-5f50-4cbe-80c0-fd9e413f03b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836987847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2836987847
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2290023395
Short name T104
Test name
Test status
Simulation time 32862495 ps
CPU time 0.74 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:37 PM PDT 24
Peak memory 191560 kb
Host smart-22f5c1eb-afca-47e5-9bca-28b837c54146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290023395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2290023395
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2112798459
Short name T500
Test name
Test status
Simulation time 37713992 ps
CPU time 1.74 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:29 PM PDT 24
Peak memory 197424 kb
Host smart-55400348-5d12-40e9-9206-3603cc2273b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112798459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2112798459
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1204983926
Short name T121
Test name
Test status
Simulation time 268318112 ps
CPU time 1.01 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:33 PM PDT 24
Peak memory 183276 kb
Host smart-574ca1e9-9e5d-4d16-8d44-763f625f8919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204983926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1204983926
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3381124480
Short name T65
Test name
Test status
Simulation time 72703805 ps
CPU time 0.7 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:28 PM PDT 24
Peak memory 194420 kb
Host smart-403bebdf-242e-49ce-b04d-07b6448f1e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381124480 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3381124480
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1129335043
Short name T567
Test name
Test status
Simulation time 13334640 ps
CPU time 0.52 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:47 PM PDT 24
Peak memory 182352 kb
Host smart-34390c73-6158-48f7-b1f2-6c5331ef6e90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129335043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1129335043
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3265299950
Short name T507
Test name
Test status
Simulation time 11352542 ps
CPU time 0.53 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:30 PM PDT 24
Peak memory 182376 kb
Host smart-4d6a562d-8c6b-4969-97c6-9bb1244b1abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265299950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3265299950
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3291688298
Short name T93
Test name
Test status
Simulation time 68694269 ps
CPU time 0.79 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:47 PM PDT 24
Peak memory 194252 kb
Host smart-eee26444-8b36-4c4d-97ad-af5726b7ba07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291688298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3291688298
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2031965932
Short name T498
Test name
Test status
Simulation time 132316880 ps
CPU time 1.31 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:36 PM PDT 24
Peak memory 197424 kb
Host smart-9ac7fd91-8415-45a5-95bf-9f8aee322c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031965932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2031965932
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1704125140
Short name T551
Test name
Test status
Simulation time 102200960 ps
CPU time 0.78 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:39 PM PDT 24
Peak memory 193240 kb
Host smart-1d5d015c-73ad-44a5-bad6-d83d51f50c21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704125140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1704125140
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.320346175
Short name T517
Test name
Test status
Simulation time 23548262 ps
CPU time 0.7 seconds
Started May 21 12:25:21 PM PDT 24
Finished May 21 12:25:23 PM PDT 24
Peak memory 182484 kb
Host smart-1cc8925f-fd88-4466-8af1-4a40e9c45abf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320346175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.320346175
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3909894737
Short name T465
Test name
Test status
Simulation time 189403558 ps
CPU time 2.5 seconds
Started May 21 12:25:13 PM PDT 24
Finished May 21 12:25:17 PM PDT 24
Peak memory 190972 kb
Host smart-02262c98-eaef-4e55-8a33-056188a45cba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909894737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3909894737
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.363625223
Short name T96
Test name
Test status
Simulation time 13927131 ps
CPU time 0.58 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 182324 kb
Host smart-d72def9b-9fd0-455f-9df4-5078948de18b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363625223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.363625223
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4080858312
Short name T475
Test name
Test status
Simulation time 25016198 ps
CPU time 0.73 seconds
Started May 21 12:25:29 PM PDT 24
Finished May 21 12:25:42 PM PDT 24
Peak memory 194940 kb
Host smart-307f4eee-5d66-4726-9e99-a8698a19fa3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080858312 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4080858312
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2453024681
Short name T34
Test name
Test status
Simulation time 49701822 ps
CPU time 0.57 seconds
Started May 21 12:24:58 PM PDT 24
Finished May 21 12:25:00 PM PDT 24
Peak memory 191664 kb
Host smart-62e32dc7-094a-4e03-a8d0-7f0f4b8fecac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453024681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2453024681
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3800682111
Short name T501
Test name
Test status
Simulation time 17875277 ps
CPU time 0.51 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:32 PM PDT 24
Peak memory 182068 kb
Host smart-48b62256-c1fa-4d0c-bb24-003805874a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800682111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3800682111
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3582694327
Short name T568
Test name
Test status
Simulation time 110593686 ps
CPU time 0.63 seconds
Started May 21 12:25:30 PM PDT 24
Finished May 21 12:25:43 PM PDT 24
Peak memory 191948 kb
Host smart-2c0a9c32-574f-4be9-a521-7f42bc68b2e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582694327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3582694327
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2506199559
Short name T561
Test name
Test status
Simulation time 78603301 ps
CPU time 1.61 seconds
Started May 21 12:25:01 PM PDT 24
Finished May 21 12:25:05 PM PDT 24
Peak memory 197396 kb
Host smart-a5b8b335-4298-42b6-8faf-2207cd1473bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506199559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2506199559
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2502278378
Short name T524
Test name
Test status
Simulation time 339902596 ps
CPU time 1.12 seconds
Started May 21 12:25:16 PM PDT 24
Finished May 21 12:25:19 PM PDT 24
Peak memory 194656 kb
Host smart-8d75237a-b106-47d5-9e8d-5d3e260d55b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502278378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2502278378
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.39472169
Short name T472
Test name
Test status
Simulation time 13033183 ps
CPU time 0.57 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:29 PM PDT 24
Peak memory 181100 kb
Host smart-bf69d440-e6a9-4e06-8ba4-8055de2a9b5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39472169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.39472169
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1921315249
Short name T573
Test name
Test status
Simulation time 27711228 ps
CPU time 0.54 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:29 PM PDT 24
Peak memory 182464 kb
Host smart-886813ed-e0a8-4450-8729-b5b6a0fdc177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921315249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1921315249
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1806880616
Short name T509
Test name
Test status
Simulation time 112443663 ps
CPU time 0.54 seconds
Started May 21 12:25:17 PM PDT 24
Finished May 21 12:25:20 PM PDT 24
Peak memory 182460 kb
Host smart-0f545284-ac07-4fc6-be4c-7e9f02b0d461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806880616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1806880616
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3048109768
Short name T552
Test name
Test status
Simulation time 13307303 ps
CPU time 0.53 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:34 PM PDT 24
Peak memory 181896 kb
Host smart-dab120ad-6f75-4120-8dcb-4c729f6e5927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048109768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3048109768
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.318788711
Short name T462
Test name
Test status
Simulation time 17820213 ps
CPU time 0.54 seconds
Started May 21 12:25:20 PM PDT 24
Finished May 21 12:25:22 PM PDT 24
Peak memory 181836 kb
Host smart-f19ca030-76ef-41ec-abe9-0069bd4fa973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318788711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.318788711
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1347779618
Short name T533
Test name
Test status
Simulation time 110083094 ps
CPU time 0.57 seconds
Started May 21 12:25:19 PM PDT 24
Finished May 21 12:25:21 PM PDT 24
Peak memory 182432 kb
Host smart-9b2705ee-aade-4de2-9461-b978c65f6705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347779618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1347779618
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2009629843
Short name T543
Test name
Test status
Simulation time 29902520 ps
CPU time 0.54 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:36 PM PDT 24
Peak memory 182428 kb
Host smart-fe87e9d0-8185-402b-87b4-fe3b076ce51c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009629843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2009629843
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3763681551
Short name T464
Test name
Test status
Simulation time 21319695 ps
CPU time 0.51 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:49 PM PDT 24
Peak memory 182028 kb
Host smart-6a46f808-9f2d-4b17-858e-02cde1a81a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763681551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3763681551
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3878976855
Short name T523
Test name
Test status
Simulation time 48984821 ps
CPU time 0.52 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:47 PM PDT 24
Peak memory 182424 kb
Host smart-b8ec535a-0e5e-4803-b9cb-63d7aec9093f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878976855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3878976855
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1343467825
Short name T471
Test name
Test status
Simulation time 43960566 ps
CPU time 0.54 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:33 PM PDT 24
Peak memory 181916 kb
Host smart-5c2d0db1-9243-4026-9fc1-0b449b2a5231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343467825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1343467825
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.454016608
Short name T575
Test name
Test status
Simulation time 45001374 ps
CPU time 0.61 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:27 PM PDT 24
Peak memory 182536 kb
Host smart-fff13bd6-e5e6-476d-be24-48e653e291dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454016608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.454016608
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2446658439
Short name T503
Test name
Test status
Simulation time 25623793 ps
CPU time 0.56 seconds
Started May 21 12:25:29 PM PDT 24
Finished May 21 12:25:42 PM PDT 24
Peak memory 182472 kb
Host smart-46968b72-685b-46fd-9b32-e8185d1cfd70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446658439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2446658439
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4239495153
Short name T563
Test name
Test status
Simulation time 22390677 ps
CPU time 0.64 seconds
Started May 21 12:25:16 PM PDT 24
Finished May 21 12:25:18 PM PDT 24
Peak memory 193532 kb
Host smart-253997c9-4889-4217-8447-6c4389f6c787
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239495153 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4239495153
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.4266664869
Short name T100
Test name
Test status
Simulation time 44409088 ps
CPU time 0.56 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 182484 kb
Host smart-1f56928c-d9a6-4085-a810-816cdb855e1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266664869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.4266664869
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3605817799
Short name T450
Test name
Test status
Simulation time 49233241 ps
CPU time 0.56 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 182480 kb
Host smart-09ce2836-9018-456e-bf62-e78d504581bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605817799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3605817799
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2528440518
Short name T522
Test name
Test status
Simulation time 33044451 ps
CPU time 0.71 seconds
Started May 21 12:24:53 PM PDT 24
Finished May 21 12:24:54 PM PDT 24
Peak memory 192892 kb
Host smart-e8f17ea4-78b4-4cc1-87de-b8e260ba6c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528440518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2528440518
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2663959920
Short name T490
Test name
Test status
Simulation time 202294294 ps
CPU time 2.42 seconds
Started May 21 12:25:06 PM PDT 24
Finished May 21 12:25:10 PM PDT 24
Peak memory 197392 kb
Host smart-14740526-215f-4d49-a9cd-227e45973ac0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663959920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2663959920
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3139906780
Short name T525
Test name
Test status
Simulation time 170306241 ps
CPU time 0.78 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:45 PM PDT 24
Peak memory 182840 kb
Host smart-f75526a2-68df-44f4-8990-6b2184d4a89d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139906780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3139906780
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1758560476
Short name T476
Test name
Test status
Simulation time 12612667 ps
CPU time 0.52 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:36 PM PDT 24
Peak memory 181868 kb
Host smart-77e81802-1eca-4a2a-becb-28be02193cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758560476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1758560476
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2406107927
Short name T451
Test name
Test status
Simulation time 13796853 ps
CPU time 0.57 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:25:53 PM PDT 24
Peak memory 182448 kb
Host smart-a6186a92-d763-475b-8613-4ca19662896a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406107927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2406107927
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4140601101
Short name T482
Test name
Test status
Simulation time 30745714 ps
CPU time 0.51 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:46 PM PDT 24
Peak memory 181908 kb
Host smart-6df616d1-3144-486f-a675-2a3c84606886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140601101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4140601101
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.245085340
Short name T513
Test name
Test status
Simulation time 18243115 ps
CPU time 0.54 seconds
Started May 21 12:25:22 PM PDT 24
Finished May 21 12:25:25 PM PDT 24
Peak memory 182428 kb
Host smart-8e4bb91b-fd96-412e-9e74-3b6d68f4cb20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245085340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.245085340
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1981216171
Short name T491
Test name
Test status
Simulation time 15900068 ps
CPU time 0.53 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:35 PM PDT 24
Peak memory 182496 kb
Host smart-efce5f8a-9a33-4c2e-ae8e-64f4a3deee14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981216171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1981216171
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1552296115
Short name T540
Test name
Test status
Simulation time 12108621 ps
CPU time 0.54 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:47 PM PDT 24
Peak memory 182400 kb
Host smart-dc74d8ad-f1cd-4469-9e07-4c1ff8569d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552296115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1552296115
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3162111587
Short name T554
Test name
Test status
Simulation time 16490632 ps
CPU time 0.55 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:48 PM PDT 24
Peak memory 182004 kb
Host smart-9f9cfa3c-8e3d-4fe9-ba52-69e371c34bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162111587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3162111587
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1033650748
Short name T495
Test name
Test status
Simulation time 55297612 ps
CPU time 0.56 seconds
Started May 21 12:25:36 PM PDT 24
Finished May 21 12:25:56 PM PDT 24
Peak memory 181876 kb
Host smart-1fb4a928-558f-4277-b93c-06e8eacfd6ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033650748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1033650748
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2661851746
Short name T572
Test name
Test status
Simulation time 23193987 ps
CPU time 0.55 seconds
Started May 21 12:25:30 PM PDT 24
Finished May 21 12:25:45 PM PDT 24
Peak memory 182452 kb
Host smart-89f33bb6-968e-4119-b913-11b93b43d9fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661851746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2661851746
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2164215331
Short name T484
Test name
Test status
Simulation time 54914660 ps
CPU time 0.53 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:52 PM PDT 24
Peak memory 182052 kb
Host smart-54ecda4a-48ab-4a2d-8806-1f69c2c32832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164215331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2164215331
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2185748368
Short name T97
Test name
Test status
Simulation time 59229052 ps
CPU time 0.69 seconds
Started May 21 12:25:00 PM PDT 24
Finished May 21 12:25:04 PM PDT 24
Peak memory 191716 kb
Host smart-bbc41d3b-61f1-45ad-86de-3bcbe8524747
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185748368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2185748368
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3259134824
Short name T545
Test name
Test status
Simulation time 1492639578 ps
CPU time 3.59 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:50 PM PDT 24
Peak memory 190976 kb
Host smart-ed448900-cd73-41d0-874f-3bd630f41ef3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259134824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3259134824
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3827879022
Short name T528
Test name
Test status
Simulation time 60876965 ps
CPU time 0.61 seconds
Started May 21 12:25:08 PM PDT 24
Finished May 21 12:25:10 PM PDT 24
Peak memory 182516 kb
Host smart-d7626d83-328a-49d5-9924-1ed680bd837a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827879022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3827879022
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2030475829
Short name T456
Test name
Test status
Simulation time 21988011 ps
CPU time 0.98 seconds
Started May 21 12:25:06 PM PDT 24
Finished May 21 12:25:10 PM PDT 24
Peak memory 196132 kb
Host smart-32409712-cc91-441a-9652-e1873d1189f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030475829 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2030475829
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3466716840
Short name T101
Test name
Test status
Simulation time 17807630 ps
CPU time 0.58 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:33 PM PDT 24
Peak memory 182564 kb
Host smart-a0656844-7a4d-4609-8e00-a55220d50a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466716840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3466716840
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3406708050
Short name T537
Test name
Test status
Simulation time 46871789 ps
CPU time 0.53 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:47 PM PDT 24
Peak memory 182332 kb
Host smart-25de3cd4-fc86-49af-8e4e-c4854082870d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406708050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3406708050
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4043730498
Short name T91
Test name
Test status
Simulation time 71323296 ps
CPU time 0.75 seconds
Started May 21 12:25:22 PM PDT 24
Finished May 21 12:25:25 PM PDT 24
Peak memory 191996 kb
Host smart-61867add-6d88-44c6-bea3-5b77441f5ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043730498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.4043730498
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2711989505
Short name T519
Test name
Test status
Simulation time 547587676 ps
CPU time 2.64 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:30 PM PDT 24
Peak memory 197432 kb
Host smart-83bb94e5-1b30-4075-9105-03200482cc42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711989505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2711989505
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1381668536
Short name T122
Test name
Test status
Simulation time 279376705 ps
CPU time 1.11 seconds
Started May 21 12:25:05 PM PDT 24
Finished May 21 12:25:08 PM PDT 24
Peak memory 194816 kb
Host smart-feee0925-51f5-443e-bd53-b278af512b75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381668536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1381668536
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2656357658
Short name T486
Test name
Test status
Simulation time 25310331 ps
CPU time 0.57 seconds
Started May 21 12:25:31 PM PDT 24
Finished May 21 12:25:46 PM PDT 24
Peak memory 182424 kb
Host smart-a317ee41-7c67-489e-a5be-fe910d6a2227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656357658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2656357658
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1149430789
Short name T474
Test name
Test status
Simulation time 38593261 ps
CPU time 0.54 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:26 PM PDT 24
Peak memory 182488 kb
Host smart-2289eceb-9e19-4934-a0ae-620f27c80af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149430789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1149430789
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1883964851
Short name T556
Test name
Test status
Simulation time 22095302 ps
CPU time 0.52 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:31 PM PDT 24
Peak memory 181868 kb
Host smart-67811da9-cc2c-45cd-aa54-81f6c559ca4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883964851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1883964851
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3124793894
Short name T466
Test name
Test status
Simulation time 14206725 ps
CPU time 0.52 seconds
Started May 21 12:25:37 PM PDT 24
Finished May 21 12:25:58 PM PDT 24
Peak memory 181912 kb
Host smart-26b39a91-c782-4223-a26f-2ca887634796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124793894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3124793894
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1979284170
Short name T566
Test name
Test status
Simulation time 27661773 ps
CPU time 0.54 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:50 PM PDT 24
Peak memory 182084 kb
Host smart-7070e0b9-c8f9-4f94-a9ee-fee2d491879f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979284170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1979284170
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.421295956
Short name T489
Test name
Test status
Simulation time 13932275 ps
CPU time 0.56 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 181076 kb
Host smart-fd89c20b-e9fe-47fd-9984-4ac3d758d086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421295956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.421295956
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3533537273
Short name T460
Test name
Test status
Simulation time 13888609 ps
CPU time 0.53 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:56 PM PDT 24
Peak memory 181848 kb
Host smart-84714c35-1996-4bb1-8d46-0266fe362aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533537273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3533537273
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2652924849
Short name T506
Test name
Test status
Simulation time 17893605 ps
CPU time 0.53 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:26 PM PDT 24
Peak memory 182544 kb
Host smart-c5ed64d5-0ff1-4dbb-b805-4f87584593e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652924849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2652924849
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.356509368
Short name T478
Test name
Test status
Simulation time 94192442 ps
CPU time 0.54 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:55 PM PDT 24
Peak memory 182380 kb
Host smart-208f667b-b597-422b-aadf-a7c3d4bc44f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356509368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.356509368
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3125901862
Short name T535
Test name
Test status
Simulation time 23203165 ps
CPU time 0.57 seconds
Started May 21 12:25:35 PM PDT 24
Finished May 21 12:25:54 PM PDT 24
Peak memory 182436 kb
Host smart-ad25facd-778a-4a34-9790-493faca53dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125901862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3125901862
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.773684386
Short name T36
Test name
Test status
Simulation time 303319806 ps
CPU time 0.95 seconds
Started May 21 12:25:03 PM PDT 24
Finished May 21 12:25:06 PM PDT 24
Peak memory 197192 kb
Host smart-ea85456b-043b-4e3b-982e-ba826aa18275
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773684386 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.773684386
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.769358121
Short name T55
Test name
Test status
Simulation time 16666503 ps
CPU time 0.55 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:38 PM PDT 24
Peak memory 182476 kb
Host smart-991c5c94-bfda-46bf-9b75-e2fd7043c409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769358121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.769358121
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3651482092
Short name T562
Test name
Test status
Simulation time 61101021 ps
CPU time 0.54 seconds
Started May 21 12:25:05 PM PDT 24
Finished May 21 12:25:08 PM PDT 24
Peak memory 182364 kb
Host smart-0ac8a3eb-c255-40fb-8295-50fce933b5a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651482092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3651482092
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.284065212
Short name T53
Test name
Test status
Simulation time 32936353 ps
CPU time 0.74 seconds
Started May 21 12:24:53 PM PDT 24
Finished May 21 12:24:55 PM PDT 24
Peak memory 193152 kb
Host smart-d3b57aac-8e0e-4499-a4b0-7aa47623afd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284065212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.284065212
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.886635574
Short name T510
Test name
Test status
Simulation time 382944844 ps
CPU time 2.11 seconds
Started May 21 12:25:29 PM PDT 24
Finished May 21 12:25:44 PM PDT 24
Peak memory 197404 kb
Host smart-514e5af5-c7b8-4db6-a860-7c626224dbcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886635574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.886635574
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1246383328
Short name T550
Test name
Test status
Simulation time 399021279 ps
CPU time 1.38 seconds
Started May 21 12:25:21 PM PDT 24
Finished May 21 12:25:23 PM PDT 24
Peak memory 183360 kb
Host smart-4cd2aa67-18e0-420c-9e3f-f9a189e46514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246383328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1246383328
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1104718847
Short name T541
Test name
Test status
Simulation time 21629315 ps
CPU time 1.03 seconds
Started May 21 12:25:32 PM PDT 24
Finished May 21 12:25:49 PM PDT 24
Peak memory 197240 kb
Host smart-ec828ce0-7f0a-49e3-bec2-4db32416136f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104718847 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1104718847
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2446255837
Short name T117
Test name
Test status
Simulation time 13442096 ps
CPU time 0.6 seconds
Started May 21 12:25:00 PM PDT 24
Finished May 21 12:25:03 PM PDT 24
Peak memory 182508 kb
Host smart-2a5bfe73-d18a-4dab-a63b-4203d8d572b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446255837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2446255837
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.217002206
Short name T560
Test name
Test status
Simulation time 41105628 ps
CPU time 0.54 seconds
Started May 21 12:24:47 PM PDT 24
Finished May 21 12:24:48 PM PDT 24
Peak memory 182296 kb
Host smart-37a636fb-2f93-43c5-8b1d-347f8974707b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217002206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.217002206
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3899760693
Short name T512
Test name
Test status
Simulation time 44498878 ps
CPU time 0.59 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:26 PM PDT 24
Peak memory 191188 kb
Host smart-67eee81f-adaa-4829-b2c0-b3d179a5215b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899760693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3899760693
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1541197370
Short name T453
Test name
Test status
Simulation time 41196316 ps
CPU time 1.86 seconds
Started May 21 12:25:03 PM PDT 24
Finished May 21 12:25:07 PM PDT 24
Peak memory 197476 kb
Host smart-74539569-2979-4856-bf8e-8818c35e73a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541197370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1541197370
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.440143779
Short name T532
Test name
Test status
Simulation time 259141150 ps
CPU time 0.81 seconds
Started May 21 12:25:23 PM PDT 24
Finished May 21 12:25:28 PM PDT 24
Peak memory 193424 kb
Host smart-7758c997-582d-42f3-b756-d31831266750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440143779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.440143779
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2274807919
Short name T539
Test name
Test status
Simulation time 118734851 ps
CPU time 0.74 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:38 PM PDT 24
Peak memory 195152 kb
Host smart-9ad034ae-60c4-4bcc-8e10-973dd9fa12e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274807919 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2274807919
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1594926020
Short name T508
Test name
Test status
Simulation time 12971485 ps
CPU time 0.52 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:39 PM PDT 24
Peak memory 182472 kb
Host smart-8a13e5fd-1455-4951-9d85-07f00300a8e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594926020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1594926020
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1163052247
Short name T502
Test name
Test status
Simulation time 19386344 ps
CPU time 0.53 seconds
Started May 21 12:25:18 PM PDT 24
Finished May 21 12:25:20 PM PDT 24
Peak memory 181928 kb
Host smart-67e75d2d-3abe-4efb-a94d-a3bad39b8b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163052247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1163052247
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2250518892
Short name T54
Test name
Test status
Simulation time 39137202 ps
CPU time 0.76 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:38 PM PDT 24
Peak memory 193040 kb
Host smart-d656b4f4-1241-4b55-96cc-f4960fbd8d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250518892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2250518892
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3213788405
Short name T480
Test name
Test status
Simulation time 56829851 ps
CPU time 1.35 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:53 PM PDT 24
Peak memory 197460 kb
Host smart-3dc3e2b8-efe6-4118-aa28-e449be00971a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213788405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3213788405
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.559012709
Short name T454
Test name
Test status
Simulation time 24173852 ps
CPU time 1.07 seconds
Started May 21 12:25:34 PM PDT 24
Finished May 21 12:25:53 PM PDT 24
Peak memory 197456 kb
Host smart-4f86cc31-2f06-49d3-b3fd-a32cc0380729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559012709 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.559012709
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4081425401
Short name T546
Test name
Test status
Simulation time 12940284 ps
CPU time 0.55 seconds
Started May 21 12:25:09 PM PDT 24
Finished May 21 12:25:11 PM PDT 24
Peak memory 182572 kb
Host smart-33869f96-4840-45b7-bc07-79248d6a82f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081425401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4081425401
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.969072097
Short name T458
Test name
Test status
Simulation time 16067262 ps
CPU time 0.52 seconds
Started May 21 12:25:24 PM PDT 24
Finished May 21 12:25:31 PM PDT 24
Peak memory 181900 kb
Host smart-0086e8dc-21e5-4695-99a5-a75ba87c9a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969072097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.969072097
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3423916646
Short name T521
Test name
Test status
Simulation time 110282676 ps
CPU time 0.6 seconds
Started May 21 12:25:28 PM PDT 24
Finished May 21 12:25:38 PM PDT 24
Peak memory 191436 kb
Host smart-4936747c-fdea-4583-912b-be2383892def
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423916646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3423916646
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2082025225
Short name T469
Test name
Test status
Simulation time 137972531 ps
CPU time 1.67 seconds
Started May 21 12:25:25 PM PDT 24
Finished May 21 12:25:33 PM PDT 24
Peak memory 197428 kb
Host smart-2ef602dc-feda-4b2b-bfb8-ac790b0984c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082025225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2082025225
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.205114549
Short name T488
Test name
Test status
Simulation time 235025500 ps
CPU time 1.08 seconds
Started May 21 12:25:18 PM PDT 24
Finished May 21 12:25:21 PM PDT 24
Peak memory 194556 kb
Host smart-778410f4-d664-4698-9e9f-2a598ee1cdc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205114549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.205114549
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1655537382
Short name T526
Test name
Test status
Simulation time 69416664 ps
CPU time 0.66 seconds
Started May 21 12:25:27 PM PDT 24
Finished May 21 12:25:37 PM PDT 24
Peak memory 193956 kb
Host smart-e57111ad-f966-4232-a9fc-8fb530178539
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655537382 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1655537382
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1518551059
Short name T565
Test name
Test status
Simulation time 19512904 ps
CPU time 0.57 seconds
Started May 21 12:25:26 PM PDT 24
Finished May 21 12:25:35 PM PDT 24
Peak memory 182344 kb
Host smart-4023ed4e-d4fb-4824-a122-e8995be945ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518551059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1518551059
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1133549939
Short name T511
Test name
Test status
Simulation time 27398012 ps
CPU time 0.56 seconds
Started May 21 12:25:13 PM PDT 24
Finished May 21 12:25:15 PM PDT 24
Peak memory 182456 kb
Host smart-f9bcb1e3-d10d-46fd-985e-a683e4a94380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133549939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1133549939
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3792237447
Short name T95
Test name
Test status
Simulation time 24867511 ps
CPU time 0.59 seconds
Started May 21 12:25:33 PM PDT 24
Finished May 21 12:25:51 PM PDT 24
Peak memory 191836 kb
Host smart-f7f571b7-0d11-499d-92fa-3b4038f685b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792237447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3792237447
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1365467774
Short name T457
Test name
Test status
Simulation time 74085917 ps
CPU time 1.57 seconds
Started May 21 12:25:03 PM PDT 24
Finished May 21 12:25:06 PM PDT 24
Peak memory 197476 kb
Host smart-ca5172f2-1488-485a-93e3-c1a456a4adf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365467774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1365467774
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4148185516
Short name T119
Test name
Test status
Simulation time 131123995 ps
CPU time 1.08 seconds
Started May 21 12:25:30 PM PDT 24
Finished May 21 12:25:45 PM PDT 24
Peak memory 183052 kb
Host smart-f3cce6cf-7a8d-4b28-a12c-190595a32293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148185516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4148185516
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1085268057
Short name T333
Test name
Test status
Simulation time 286614205404 ps
CPU time 495.8 seconds
Started May 21 01:46:13 PM PDT 24
Finished May 21 01:54:30 PM PDT 24
Peak memory 182620 kb
Host smart-ff991ae2-a71b-4946-96bd-b81979840724
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085268057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1085268057
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2109457965
Short name T415
Test name
Test status
Simulation time 47638967899 ps
CPU time 61.7 seconds
Started May 21 01:46:19 PM PDT 24
Finished May 21 01:47:21 PM PDT 24
Peak memory 182640 kb
Host smart-847a6ba5-0b7d-45e1-9fad-8b6d7d26c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109457965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2109457965
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2538320925
Short name T432
Test name
Test status
Simulation time 378373286464 ps
CPU time 196.7 seconds
Started May 21 01:46:14 PM PDT 24
Finished May 21 01:49:31 PM PDT 24
Peak memory 190856 kb
Host smart-a3f36f24-71b7-40b9-9ddd-7b8c1026e78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538320925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2538320925
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2928695643
Short name T66
Test name
Test status
Simulation time 402413461422 ps
CPU time 821.41 seconds
Started May 21 01:46:08 PM PDT 24
Finished May 21 01:59:50 PM PDT 24
Peak memory 190888 kb
Host smart-fb33ef86-32eb-4cb2-a436-3dedc47c1f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928695643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2928695643
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3387555167
Short name T157
Test name
Test status
Simulation time 147882770858 ps
CPU time 271.56 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:50:58 PM PDT 24
Peak memory 182692 kb
Host smart-bc0d8b26-7aea-49ec-b57f-71803f7c7e8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387555167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3387555167
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3192361791
Short name T365
Test name
Test status
Simulation time 319883064050 ps
CPU time 136.12 seconds
Started May 21 01:46:14 PM PDT 24
Finished May 21 01:48:31 PM PDT 24
Peak memory 182672 kb
Host smart-988d5511-3e07-4d21-b3a1-25c22d587739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192361791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3192361791
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1605275853
Short name T271
Test name
Test status
Simulation time 17845169404 ps
CPU time 77.09 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:47:43 PM PDT 24
Peak memory 193052 kb
Host smart-a607d464-0b17-4b69-8f95-60264aa8fea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605275853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1605275853
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1503948330
Short name T321
Test name
Test status
Simulation time 118228837989 ps
CPU time 180.29 seconds
Started May 21 01:46:19 PM PDT 24
Finished May 21 01:49:20 PM PDT 24
Peak memory 190852 kb
Host smart-1461508e-fcdf-40ff-bbb0-233f718d2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503948330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1503948330
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.122775520
Short name T17
Test name
Test status
Simulation time 31746619 ps
CPU time 0.74 seconds
Started May 21 01:46:13 PM PDT 24
Finished May 21 01:46:14 PM PDT 24
Peak memory 213164 kb
Host smart-87be4463-211a-4a65-a37f-d5c916db24dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122775520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.122775520
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.770824961
Short name T126
Test name
Test status
Simulation time 190981772078 ps
CPU time 330.16 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:52:02 PM PDT 24
Peak memory 182624 kb
Host smart-83ed65e9-abba-4943-b3db-808d324ea532
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770824961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.770824961
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.4237547043
Short name T427
Test name
Test status
Simulation time 8861772140 ps
CPU time 11.94 seconds
Started May 21 01:46:18 PM PDT 24
Finished May 21 01:46:31 PM PDT 24
Peak memory 182636 kb
Host smart-ebf47e00-3392-4295-b80a-63993d1d9090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237547043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.4237547043
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.889291499
Short name T190
Test name
Test status
Simulation time 186651804702 ps
CPU time 291.88 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:51:19 PM PDT 24
Peak memory 190816 kb
Host smart-2a6bf431-43fb-4dc4-bb0b-7d673d0457fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889291499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.889291499
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1323451570
Short name T409
Test name
Test status
Simulation time 47985317 ps
CPU time 0.59 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:46:29 PM PDT 24
Peak memory 182412 kb
Host smart-6277f9a3-5c41-43ec-b3dc-3d5820c973cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323451570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1323451570
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1871473895
Short name T39
Test name
Test status
Simulation time 339330681003 ps
CPU time 973.19 seconds
Started May 21 01:46:28 PM PDT 24
Finished May 21 02:02:46 PM PDT 24
Peak memory 211672 kb
Host smart-a793bbc7-8b32-4a63-834e-d224cd3c0fb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871473895 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1871473895
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.3193052796
Short name T258
Test name
Test status
Simulation time 376963203731 ps
CPU time 301.32 seconds
Started May 21 01:47:02 PM PDT 24
Finished May 21 01:52:06 PM PDT 24
Peak memory 190832 kb
Host smart-2bf21b5f-1628-4379-87f4-0bae1417099e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193052796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3193052796
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.217059671
Short name T132
Test name
Test status
Simulation time 260783863755 ps
CPU time 574.47 seconds
Started May 21 01:47:06 PM PDT 24
Finished May 21 01:56:42 PM PDT 24
Peak memory 190768 kb
Host smart-16c627f4-7092-4cb2-be61-a17b2b72bcb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217059671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.217059671
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1644516651
Short name T185
Test name
Test status
Simulation time 264355211977 ps
CPU time 931.07 seconds
Started May 21 01:46:58 PM PDT 24
Finished May 21 02:02:34 PM PDT 24
Peak memory 190764 kb
Host smart-8dd7de04-1c88-4fb1-ae07-65f5d208f723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644516651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1644516651
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.88737842
Short name T7
Test name
Test status
Simulation time 566081986651 ps
CPU time 382.84 seconds
Started May 21 01:47:04 PM PDT 24
Finished May 21 01:53:30 PM PDT 24
Peak memory 190820 kb
Host smart-7d055232-f0d3-4e0f-8abf-858b053708ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88737842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.88737842
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1984974032
Short name T225
Test name
Test status
Simulation time 51009514738 ps
CPU time 416.22 seconds
Started May 21 01:47:03 PM PDT 24
Finished May 21 01:54:02 PM PDT 24
Peak memory 194212 kb
Host smart-b09df0d5-ed25-4771-a75f-edb61010bfdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984974032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1984974032
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.768218916
Short name T311
Test name
Test status
Simulation time 25000503374 ps
CPU time 41.46 seconds
Started May 21 01:47:01 PM PDT 24
Finished May 21 01:47:46 PM PDT 24
Peak memory 182648 kb
Host smart-06c51003-3442-4f74-be53-a7f079b09eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768218916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.768218916
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2450422466
Short name T382
Test name
Test status
Simulation time 29188075369 ps
CPU time 47.9 seconds
Started May 21 01:47:06 PM PDT 24
Finished May 21 01:47:55 PM PDT 24
Peak memory 182688 kb
Host smart-cbe5abdb-cafd-4272-b347-b29ec2ee4b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450422466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2450422466
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2181273724
Short name T295
Test name
Test status
Simulation time 71531504305 ps
CPU time 106.76 seconds
Started May 21 01:47:02 PM PDT 24
Finished May 21 01:48:52 PM PDT 24
Peak memory 190888 kb
Host smart-2cf6b9a0-af1a-46b5-892a-7d52ea3751d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181273724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2181273724
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.558185793
Short name T256
Test name
Test status
Simulation time 4222618574371 ps
CPU time 1403.03 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 02:09:51 PM PDT 24
Peak memory 182648 kb
Host smart-ecca8379-613c-4fd1-a8c5-3ca504977381
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558185793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.558185793
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2539005498
Short name T357
Test name
Test status
Simulation time 202249329124 ps
CPU time 334.97 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 01:51:58 PM PDT 24
Peak memory 182636 kb
Host smart-3534aa44-758e-4669-b1a0-fdf602eb7991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539005498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2539005498
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.572136234
Short name T436
Test name
Test status
Simulation time 8055733065 ps
CPU time 21.63 seconds
Started May 21 01:46:28 PM PDT 24
Finished May 21 01:46:55 PM PDT 24
Peak memory 182644 kb
Host smart-dfab86f8-0f04-4de3-9f8c-8010e9cf719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572136234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.572136234
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.1987441198
Short name T443
Test name
Test status
Simulation time 117765111581 ps
CPU time 148.45 seconds
Started May 21 01:47:05 PM PDT 24
Finished May 21 01:49:35 PM PDT 24
Peak memory 194628 kb
Host smart-bc1973f9-a3be-48c3-84bc-7bb058ec01e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987441198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1987441198
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.74041292
Short name T354
Test name
Test status
Simulation time 71786622504 ps
CPU time 57.54 seconds
Started May 21 01:47:05 PM PDT 24
Finished May 21 01:48:05 PM PDT 24
Peak memory 190756 kb
Host smart-e6f9ba33-7331-44d7-bb87-1514b92067aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74041292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.74041292
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3345185003
Short name T203
Test name
Test status
Simulation time 56899538990 ps
CPU time 102.75 seconds
Started May 21 01:47:06 PM PDT 24
Finished May 21 01:48:50 PM PDT 24
Peak memory 190888 kb
Host smart-e6a0abad-c2b3-4337-80e9-63e957058ce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345185003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3345185003
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3826823727
Short name T211
Test name
Test status
Simulation time 73532535841 ps
CPU time 213.07 seconds
Started May 21 01:47:02 PM PDT 24
Finished May 21 01:50:38 PM PDT 24
Peak memory 190860 kb
Host smart-b4b0b88d-bff2-4ca8-b2a3-106a4d5355c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826823727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3826823727
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3231935477
Short name T281
Test name
Test status
Simulation time 293114169600 ps
CPU time 714.86 seconds
Started May 21 01:47:01 PM PDT 24
Finished May 21 01:58:59 PM PDT 24
Peak memory 190768 kb
Host smart-2681a2ad-0a44-4547-91b2-cc38fc435911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231935477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3231935477
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.898178888
Short name T253
Test name
Test status
Simulation time 383751633603 ps
CPU time 178.45 seconds
Started May 21 01:46:26 PM PDT 24
Finished May 21 01:49:30 PM PDT 24
Peak memory 182648 kb
Host smart-84f20b7a-2b1c-4d69-9445-9091235f5341
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898178888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.898178888
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3586055716
Short name T360
Test name
Test status
Simulation time 316549949862 ps
CPU time 80.48 seconds
Started May 21 01:46:15 PM PDT 24
Finished May 21 01:47:36 PM PDT 24
Peak memory 182676 kb
Host smart-13fe32c2-452f-4c74-9f2e-60e43630afd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586055716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3586055716
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3125490799
Short name T286
Test name
Test status
Simulation time 101827681013 ps
CPU time 129.36 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:48:38 PM PDT 24
Peak memory 190828 kb
Host smart-80178d2b-e2a8-4b5a-87d2-e97e945a553b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125490799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3125490799
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3884789311
Short name T379
Test name
Test status
Simulation time 117804641 ps
CPU time 0.56 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 01:46:23 PM PDT 24
Peak memory 182420 kb
Host smart-438a7911-38e5-4cf1-9771-8277df8091e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884789311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3884789311
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.463503864
Short name T50
Test name
Test status
Simulation time 66588107918 ps
CPU time 116.75 seconds
Started May 21 01:47:00 PM PDT 24
Finished May 21 01:49:00 PM PDT 24
Peak memory 190840 kb
Host smart-c4f2d9be-d3b8-4c48-9c67-a26ec0753cb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463503864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.463503864
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3453659362
Short name T332
Test name
Test status
Simulation time 26193818785 ps
CPU time 37.94 seconds
Started May 21 01:47:02 PM PDT 24
Finished May 21 01:47:43 PM PDT 24
Peak memory 182692 kb
Host smart-3f181d33-8dcc-4e9f-a490-53e980d23f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453659362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3453659362
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1018811591
Short name T183
Test name
Test status
Simulation time 460421427496 ps
CPU time 112.14 seconds
Started May 21 01:47:06 PM PDT 24
Finished May 21 01:48:59 PM PDT 24
Peak memory 182684 kb
Host smart-490f38be-763a-40e4-800e-a27c2328ae7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018811591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1018811591
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1823404750
Short name T417
Test name
Test status
Simulation time 227984138285 ps
CPU time 1097.77 seconds
Started May 21 01:47:03 PM PDT 24
Finished May 21 02:05:23 PM PDT 24
Peak memory 182684 kb
Host smart-91306d74-fe60-4dd7-a631-1b443667e5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823404750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1823404750
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.381925237
Short name T449
Test name
Test status
Simulation time 14312309732 ps
CPU time 21.84 seconds
Started May 21 01:47:10 PM PDT 24
Finished May 21 01:47:33 PM PDT 24
Peak memory 190804 kb
Host smart-77dc7009-1ac5-472d-889c-18bb538d8f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381925237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.381925237
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.216316737
Short name T220
Test name
Test status
Simulation time 76181745364 ps
CPU time 128.27 seconds
Started May 21 01:47:09 PM PDT 24
Finished May 21 01:49:18 PM PDT 24
Peak memory 190832 kb
Host smart-2470822a-d7e8-4560-89b6-d64ab4a76b1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216316737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.216316737
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.255584867
Short name T290
Test name
Test status
Simulation time 123026436591 ps
CPU time 55.22 seconds
Started May 21 01:47:13 PM PDT 24
Finished May 21 01:48:09 PM PDT 24
Peak memory 182692 kb
Host smart-eff51993-47f9-440e-b050-4a1f95fad077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255584867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.255584867
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.627291254
Short name T395
Test name
Test status
Simulation time 335632336767 ps
CPU time 137.04 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:48:44 PM PDT 24
Peak memory 182692 kb
Host smart-37486fc4-fa48-4c87-a9f8-30ab7ec3b379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627291254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.627291254
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.4292928564
Short name T318
Test name
Test status
Simulation time 300401932880 ps
CPU time 148.56 seconds
Started May 21 01:46:22 PM PDT 24
Finished May 21 01:48:53 PM PDT 24
Peak memory 190760 kb
Host smart-a5593e3f-dc62-483b-bffe-6ab59de59895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292928564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.4292928564
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2990309206
Short name T167
Test name
Test status
Simulation time 1996548005230 ps
CPU time 3983.54 seconds
Started May 21 01:46:12 PM PDT 24
Finished May 21 02:52:37 PM PDT 24
Peak memory 190848 kb
Host smart-2d1e2aca-a929-480f-907b-0e1d039a94e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990309206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2990309206
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.2085157428
Short name T419
Test name
Test status
Simulation time 97498201752 ps
CPU time 78.04 seconds
Started May 21 01:47:13 PM PDT 24
Finished May 21 01:48:32 PM PDT 24
Peak memory 182692 kb
Host smart-51fd80f0-2a03-4849-a905-0a77f0c9d01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085157428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2085157428
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2951979320
Short name T344
Test name
Test status
Simulation time 37252363722 ps
CPU time 208.63 seconds
Started May 21 01:47:17 PM PDT 24
Finished May 21 01:50:47 PM PDT 24
Peak memory 182644 kb
Host smart-e900d6a3-b398-4904-8d58-9d7a05f258ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951979320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2951979320
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3214758038
Short name T317
Test name
Test status
Simulation time 620457546766 ps
CPU time 650.09 seconds
Started May 21 01:47:16 PM PDT 24
Finished May 21 01:58:07 PM PDT 24
Peak memory 190852 kb
Host smart-d0b84b3d-b5c3-4ab4-877c-f3a0754318e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214758038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3214758038
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4289949562
Short name T340
Test name
Test status
Simulation time 83334742431 ps
CPU time 84.15 seconds
Started May 21 01:47:15 PM PDT 24
Finished May 21 01:48:40 PM PDT 24
Peak memory 190852 kb
Host smart-4558fbf4-5bc9-4025-8b27-1e564b988423
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289949562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4289949562
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.822169621
Short name T296
Test name
Test status
Simulation time 41326917549 ps
CPU time 228.58 seconds
Started May 21 01:47:16 PM PDT 24
Finished May 21 01:51:06 PM PDT 24
Peak memory 193272 kb
Host smart-2d475a9e-6617-4279-8d38-088d54ff7bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822169621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.822169621
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.599828163
Short name T387
Test name
Test status
Simulation time 40811951343 ps
CPU time 67.17 seconds
Started May 21 01:47:14 PM PDT 24
Finished May 21 01:48:22 PM PDT 24
Peak memory 182676 kb
Host smart-e4e27522-3db5-44a3-8c3f-8e282884909d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599828163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.599828163
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2851885381
Short name T263
Test name
Test status
Simulation time 1577838957335 ps
CPU time 730.63 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:58:40 PM PDT 24
Peak memory 182636 kb
Host smart-ae57b440-3527-4b8c-a805-1d6e5f530c84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851885381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2851885381
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2050031009
Short name T399
Test name
Test status
Simulation time 77537351598 ps
CPU time 115.69 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:48:27 PM PDT 24
Peak memory 182660 kb
Host smart-36f6998e-662b-4671-8d00-8824502c7703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050031009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2050031009
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.229892747
Short name T25
Test name
Test status
Simulation time 217626144516 ps
CPU time 1468.01 seconds
Started May 21 01:46:18 PM PDT 24
Finished May 21 02:10:47 PM PDT 24
Peak memory 190836 kb
Host smart-9a3904e6-d61a-4b61-92de-9614d60071e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229892747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.229892747
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1023266581
Short name T403
Test name
Test status
Simulation time 26517907793 ps
CPU time 18.7 seconds
Started May 21 01:46:28 PM PDT 24
Finished May 21 01:46:53 PM PDT 24
Peak memory 182664 kb
Host smart-ba987161-5184-4e8b-8cd5-cd81d2c72c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023266581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1023266581
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4237961725
Short name T285
Test name
Test status
Simulation time 187818491605 ps
CPU time 595.74 seconds
Started May 21 01:46:13 PM PDT 24
Finished May 21 01:56:10 PM PDT 24
Peak memory 190768 kb
Host smart-1dd04946-a5cc-458f-86be-72b1c18396f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237961725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4237961725
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.1205391419
Short name T334
Test name
Test status
Simulation time 95849516657 ps
CPU time 340.97 seconds
Started May 21 01:47:15 PM PDT 24
Finished May 21 01:52:57 PM PDT 24
Peak memory 190828 kb
Host smart-be26e8e0-2f9c-49c8-b3c9-26f9b65cd04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205391419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1205391419
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1884223708
Short name T284
Test name
Test status
Simulation time 50450458821 ps
CPU time 84.07 seconds
Started May 21 01:47:15 PM PDT 24
Finished May 21 01:48:40 PM PDT 24
Peak memory 182568 kb
Host smart-f4a2b081-9450-450d-adc0-74ab68741a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884223708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1884223708
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3282895080
Short name T316
Test name
Test status
Simulation time 191119340717 ps
CPU time 131.7 seconds
Started May 21 01:47:17 PM PDT 24
Finished May 21 01:49:29 PM PDT 24
Peak memory 190840 kb
Host smart-2c26ee45-eab6-4c7e-9f59-ab69a702b5bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282895080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3282895080
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.775606124
Short name T63
Test name
Test status
Simulation time 1581452663526 ps
CPU time 427.09 seconds
Started May 21 01:47:18 PM PDT 24
Finished May 21 01:54:26 PM PDT 24
Peak memory 190892 kb
Host smart-62138bd1-552f-4ae5-b440-bed556100dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775606124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.775606124
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3837249398
Short name T280
Test name
Test status
Simulation time 73289760290 ps
CPU time 106.46 seconds
Started May 21 01:47:14 PM PDT 24
Finished May 21 01:49:01 PM PDT 24
Peak memory 190812 kb
Host smart-110f03e4-a531-4549-b007-4a54eab5bb59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837249398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3837249398
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1782540382
Short name T330
Test name
Test status
Simulation time 21848257549 ps
CPU time 67.44 seconds
Started May 21 01:47:16 PM PDT 24
Finished May 21 01:48:25 PM PDT 24
Peak memory 182592 kb
Host smart-0d5f67b0-6053-4923-8903-8c890c21e795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782540382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1782540382
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3332481524
Short name T153
Test name
Test status
Simulation time 11776990920 ps
CPU time 10.1 seconds
Started May 21 01:47:15 PM PDT 24
Finished May 21 01:47:26 PM PDT 24
Peak memory 182644 kb
Host smart-681496b9-594a-4d40-99a1-2fe3703439d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332481524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3332481524
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3057628505
Short name T198
Test name
Test status
Simulation time 117381122810 ps
CPU time 477.37 seconds
Started May 21 01:47:26 PM PDT 24
Finished May 21 01:55:25 PM PDT 24
Peak memory 193872 kb
Host smart-cf44a987-845a-4344-a9f0-1432f4fcb77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057628505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3057628505
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3320262215
Short name T130
Test name
Test status
Simulation time 48709179904 ps
CPU time 138.04 seconds
Started May 21 01:47:23 PM PDT 24
Finished May 21 01:49:42 PM PDT 24
Peak memory 190836 kb
Host smart-4d948700-a733-48ce-aca2-a0b6a504446b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320262215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3320262215
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1232342447
Short name T177
Test name
Test status
Simulation time 192894686010 ps
CPU time 344.08 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:52:13 PM PDT 24
Peak memory 182644 kb
Host smart-2ebc1c27-72ce-4f32-8ef9-0182e27ff08c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232342447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1232342447
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.570546540
Short name T367
Test name
Test status
Simulation time 58395707859 ps
CPU time 84.66 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:47:56 PM PDT 24
Peak memory 182664 kb
Host smart-2a54fa00-cd14-4dd7-b376-cb71e2d4e61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570546540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.570546540
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2410267302
Short name T319
Test name
Test status
Simulation time 34676616879 ps
CPU time 54.63 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:47:27 PM PDT 24
Peak memory 182468 kb
Host smart-8cfba657-84f5-4266-9174-ad82078be9e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410267302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2410267302
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1967828655
Short name T371
Test name
Test status
Simulation time 580919666 ps
CPU time 0.81 seconds
Started May 21 01:46:19 PM PDT 24
Finished May 21 01:46:21 PM PDT 24
Peak memory 191084 kb
Host smart-69ca6e42-1981-41c8-9b4a-2ea748cd0a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967828655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1967828655
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1605062705
Short name T327
Test name
Test status
Simulation time 419731243002 ps
CPU time 171.99 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:49:21 PM PDT 24
Peak memory 193716 kb
Host smart-840839ea-5c9e-4a30-a5ea-4497998ce0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605062705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1605062705
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.801572624
Short name T224
Test name
Test status
Simulation time 146420203496 ps
CPU time 357.98 seconds
Started May 21 01:47:22 PM PDT 24
Finished May 21 01:53:22 PM PDT 24
Peak memory 190848 kb
Host smart-15848814-d85b-4932-ba45-094d3d701dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801572624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.801572624
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.677345922
Short name T328
Test name
Test status
Simulation time 407109799913 ps
CPU time 1405.14 seconds
Started May 21 01:47:22 PM PDT 24
Finished May 21 02:10:49 PM PDT 24
Peak memory 191832 kb
Host smart-0fbc3e35-0816-44af-b9ad-39d80c336c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677345922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.677345922
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.685439313
Short name T441
Test name
Test status
Simulation time 71676710360 ps
CPU time 139.03 seconds
Started May 21 01:47:21 PM PDT 24
Finished May 21 01:49:41 PM PDT 24
Peak memory 190868 kb
Host smart-7d0398b3-d369-4dc0-be20-510871e63cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685439313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.685439313
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2788618189
Short name T309
Test name
Test status
Simulation time 373728600454 ps
CPU time 201.83 seconds
Started May 21 01:47:21 PM PDT 24
Finished May 21 01:50:44 PM PDT 24
Peak memory 190768 kb
Host smart-33fe4619-9b49-4161-91e6-b71f74a1304e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788618189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2788618189
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1046807599
Short name T338
Test name
Test status
Simulation time 455579589060 ps
CPU time 190.55 seconds
Started May 21 01:47:22 PM PDT 24
Finished May 21 01:50:34 PM PDT 24
Peak memory 190888 kb
Host smart-4b85afbd-cc03-4f07-a124-36cfeca65495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046807599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1046807599
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.451500509
Short name T5
Test name
Test status
Simulation time 108560729168 ps
CPU time 81.08 seconds
Started May 21 01:47:23 PM PDT 24
Finished May 21 01:48:45 PM PDT 24
Peak memory 192828 kb
Host smart-466c0d1f-50ab-4989-b775-daca0fe41aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451500509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.451500509
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1013451847
Short name T389
Test name
Test status
Simulation time 609469749522 ps
CPU time 140.63 seconds
Started May 21 01:46:35 PM PDT 24
Finished May 21 01:48:58 PM PDT 24
Peak memory 182604 kb
Host smart-dea1f6a7-cb25-4860-b936-0a37d8fa178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013451847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1013451847
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2365535019
Short name T237
Test name
Test status
Simulation time 105918441028 ps
CPU time 82.71 seconds
Started May 21 01:46:17 PM PDT 24
Finished May 21 01:47:40 PM PDT 24
Peak memory 182680 kb
Host smart-b4308290-a77b-442b-aa27-011e070746dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365535019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2365535019
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2477398261
Short name T90
Test name
Test status
Simulation time 117869940088 ps
CPU time 219.64 seconds
Started May 21 01:49:06 PM PDT 24
Finished May 21 01:52:48 PM PDT 24
Peak memory 194308 kb
Host smart-581c889a-a038-4112-9933-26c6ad6b1da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477398261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2477398261
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3610671661
Short name T154
Test name
Test status
Simulation time 538501075603 ps
CPU time 252.58 seconds
Started May 21 01:49:12 PM PDT 24
Finished May 21 01:53:28 PM PDT 24
Peak memory 190864 kb
Host smart-f64f41f6-e26e-4541-9ad7-5fb8a6ce3940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610671661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3610671661
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1503720303
Short name T45
Test name
Test status
Simulation time 63000913089 ps
CPU time 108.6 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:51:08 PM PDT 24
Peak memory 190852 kb
Host smart-26770442-ba77-4e5b-acf7-97f69dc9388c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503720303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1503720303
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3145245105
Short name T445
Test name
Test status
Simulation time 8218780066 ps
CPU time 76.95 seconds
Started May 21 01:48:54 PM PDT 24
Finished May 21 01:50:12 PM PDT 24
Peak memory 182620 kb
Host smart-e732eb79-0f74-4a57-9112-80f94bfd7140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145245105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3145245105
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.496310777
Short name T303
Test name
Test status
Simulation time 144517829791 ps
CPU time 60.44 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:50:22 PM PDT 24
Peak memory 190844 kb
Host smart-e946e108-0f7b-4833-9c31-c03fc972f335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496310777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.496310777
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.870920824
Short name T342
Test name
Test status
Simulation time 38864863036 ps
CPU time 58.99 seconds
Started May 21 01:49:13 PM PDT 24
Finished May 21 01:50:19 PM PDT 24
Peak memory 190852 kb
Host smart-00c3264c-01a6-4f4e-b18c-dbf4e67d56d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870920824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.870920824
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2926542195
Short name T162
Test name
Test status
Simulation time 15530845852 ps
CPU time 180.02 seconds
Started May 21 01:49:11 PM PDT 24
Finished May 21 01:52:13 PM PDT 24
Peak memory 182684 kb
Host smart-ad8105ba-eb15-4b31-bfbd-db31ed13ef7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926542195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2926542195
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2246250561
Short name T194
Test name
Test status
Simulation time 432866442688 ps
CPU time 470.64 seconds
Started May 21 01:49:14 PM PDT 24
Finished May 21 01:57:13 PM PDT 24
Peak memory 190780 kb
Host smart-cc8d0344-066e-43e7-96cb-2a3729c24c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246250561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2246250561
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3849194556
Short name T236
Test name
Test status
Simulation time 10885550832 ps
CPU time 18.82 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:46:51 PM PDT 24
Peak memory 182668 kb
Host smart-a88134e8-5a18-441c-9d4c-65db53321765
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849194556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3849194556
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2181038635
Short name T390
Test name
Test status
Simulation time 127433696197 ps
CPU time 130.76 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:48:40 PM PDT 24
Peak memory 182632 kb
Host smart-5c8c3cab-4dfd-475d-a4b1-015a25f81f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181038635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2181038635
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1861233137
Short name T278
Test name
Test status
Simulation time 26772834026 ps
CPU time 981.87 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 02:02:45 PM PDT 24
Peak memory 182612 kb
Host smart-d2c82459-a9be-48a1-a175-139345f59a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861233137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1861233137
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3528290956
Short name T349
Test name
Test status
Simulation time 96019987790 ps
CPU time 76.94 seconds
Started May 21 01:48:55 PM PDT 24
Finished May 21 01:50:12 PM PDT 24
Peak memory 190788 kb
Host smart-635e68c9-f7b4-456f-a622-ac354f28d680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528290956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3528290956
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2412435705
Short name T158
Test name
Test status
Simulation time 94969492879 ps
CPU time 585.19 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:59:08 PM PDT 24
Peak memory 190780 kb
Host smart-1edc8bd3-917d-4dfa-b298-94427cd1a8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412435705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2412435705
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.207540284
Short name T260
Test name
Test status
Simulation time 62691417598 ps
CPU time 32.69 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:49:55 PM PDT 24
Peak memory 182592 kb
Host smart-4fa0addc-c6d2-46f2-8a47-aaca96110300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207540284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.207540284
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1115591963
Short name T346
Test name
Test status
Simulation time 85212142350 ps
CPU time 506.48 seconds
Started May 21 01:48:54 PM PDT 24
Finished May 21 01:57:21 PM PDT 24
Peak memory 190884 kb
Host smart-13172f39-dbf7-45c1-a164-c64d69c2b17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115591963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1115591963
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2324170522
Short name T444
Test name
Test status
Simulation time 13874403031 ps
CPU time 7.13 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:46:40 PM PDT 24
Peak memory 182664 kb
Host smart-d40fdf2d-0fca-4778-be9e-48a0219b477d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324170522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2324170522
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3807906585
Short name T359
Test name
Test status
Simulation time 349016570340 ps
CPU time 130.3 seconds
Started May 21 01:46:20 PM PDT 24
Finished May 21 01:48:31 PM PDT 24
Peak memory 182648 kb
Host smart-abe3edca-d7fa-46c7-874b-ed686e16c421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807906585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3807906585
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.681259474
Short name T159
Test name
Test status
Simulation time 220864975337 ps
CPU time 204 seconds
Started May 21 01:46:29 PM PDT 24
Finished May 21 01:49:58 PM PDT 24
Peak memory 190844 kb
Host smart-5e1dc379-b220-4083-bc04-cff8b4d32dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681259474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.681259474
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.4166326902
Short name T348
Test name
Test status
Simulation time 15788983577 ps
CPU time 25 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:46:51 PM PDT 24
Peak memory 182668 kb
Host smart-f2a2daf2-a117-4125-b73a-74946b396ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166326902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4166326902
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.738508586
Short name T140
Test name
Test status
Simulation time 83112088802 ps
CPU time 71.74 seconds
Started May 21 01:48:55 PM PDT 24
Finished May 21 01:50:07 PM PDT 24
Peak memory 190760 kb
Host smart-5571f18b-8621-4c79-9ce8-5d167a0b8234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738508586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.738508586
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3007880635
Short name T227
Test name
Test status
Simulation time 577873792110 ps
CPU time 1732.15 seconds
Started May 21 01:49:02 PM PDT 24
Finished May 21 02:17:55 PM PDT 24
Peak memory 190844 kb
Host smart-3060c406-d827-4915-9220-f09aba8820b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007880635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3007880635
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2780100146
Short name T339
Test name
Test status
Simulation time 143216842121 ps
CPU time 75.79 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:50:39 PM PDT 24
Peak memory 190788 kb
Host smart-3ec09442-9bb4-4034-b119-1f541644641b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780100146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2780100146
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1329599680
Short name T343
Test name
Test status
Simulation time 76819145605 ps
CPU time 128.88 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:51:31 PM PDT 24
Peak memory 190852 kb
Host smart-537f369e-b081-4cf9-af58-0f9d866b9067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329599680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1329599680
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.4156989915
Short name T232
Test name
Test status
Simulation time 178271423869 ps
CPU time 1063.49 seconds
Started May 21 01:49:08 PM PDT 24
Finished May 21 02:06:54 PM PDT 24
Peak memory 190848 kb
Host smart-352ff553-25c2-4fe2-88d3-b7566f59f32d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156989915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4156989915
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2053578796
Short name T245
Test name
Test status
Simulation time 228799422665 ps
CPU time 277.06 seconds
Started May 21 01:48:57 PM PDT 24
Finished May 21 01:53:34 PM PDT 24
Peak memory 190828 kb
Host smart-ce79f60d-45a2-48ef-82e3-07afd1c7ae4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053578796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2053578796
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1110765794
Short name T439
Test name
Test status
Simulation time 502869137971 ps
CPU time 764.69 seconds
Started May 21 01:46:22 PM PDT 24
Finished May 21 01:59:10 PM PDT 24
Peak memory 182600 kb
Host smart-8a7e1c9c-37ed-44e2-b306-6fc369e42372
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110765794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1110765794
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1578087190
Short name T437
Test name
Test status
Simulation time 95692458104 ps
CPU time 43.08 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:47:13 PM PDT 24
Peak memory 182676 kb
Host smart-01ac08fe-093c-43ee-8260-0ce3efb21da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578087190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1578087190
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2840748122
Short name T113
Test name
Test status
Simulation time 32566273193 ps
CPU time 53.39 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:47:23 PM PDT 24
Peak memory 191088 kb
Host smart-5fd68407-4fdc-4d19-a3c9-aef98c399c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840748122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2840748122
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.871179416
Short name T435
Test name
Test status
Simulation time 1553089742 ps
CPU time 1.78 seconds
Started May 21 01:46:29 PM PDT 24
Finished May 21 01:46:36 PM PDT 24
Peak memory 182448 kb
Host smart-ed6befbc-a420-4671-83f7-f887d2681a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871179416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.871179416
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3748985656
Short name T15
Test name
Test status
Simulation time 62176799398 ps
CPU time 539.9 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:55:30 PM PDT 24
Peak memory 197312 kb
Host smart-a9b83bb7-979b-4e16-9ac2-6fe5384a3317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748985656 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3748985656
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.3621393723
Short name T247
Test name
Test status
Simulation time 109635712935 ps
CPU time 379.9 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:55:43 PM PDT 24
Peak memory 190844 kb
Host smart-01b6295c-dfe7-434f-81a9-1ed919a993a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621393723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3621393723
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1107262553
Short name T305
Test name
Test status
Simulation time 353455892834 ps
CPU time 209.14 seconds
Started May 21 01:49:15 PM PDT 24
Finished May 21 01:52:52 PM PDT 24
Peak memory 190864 kb
Host smart-e74d62c5-eb2d-44c9-924d-baabdadf1f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107262553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1107262553
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2205451006
Short name T223
Test name
Test status
Simulation time 132377003598 ps
CPU time 621.81 seconds
Started May 21 01:49:07 PM PDT 24
Finished May 21 01:59:31 PM PDT 24
Peak memory 190852 kb
Host smart-4a470313-f9ea-4ecc-b35b-a144d93db56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205451006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2205451006
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.491182662
Short name T196
Test name
Test status
Simulation time 201247127303 ps
CPU time 93.13 seconds
Started May 21 01:49:16 PM PDT 24
Finished May 21 01:50:57 PM PDT 24
Peak memory 182616 kb
Host smart-2911b5ae-8baa-460d-aace-a81e8d2f657d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491182662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.491182662
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.346578056
Short name T2
Test name
Test status
Simulation time 51274432502 ps
CPU time 1288.7 seconds
Started May 21 01:49:07 PM PDT 24
Finished May 21 02:10:38 PM PDT 24
Peak memory 190700 kb
Host smart-e1d9a9ee-4c40-4a00-ab44-cfa55d20e92f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346578056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.346578056
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2051467871
Short name T27
Test name
Test status
Simulation time 226762811277 ps
CPU time 202.87 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:49:55 PM PDT 24
Peak memory 182672 kb
Host smart-ef32aac0-def0-4dfe-a269-0df5d25183ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051467871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2051467871
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.669763451
Short name T396
Test name
Test status
Simulation time 438003435110 ps
CPU time 184.66 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:49:33 PM PDT 24
Peak memory 182632 kb
Host smart-893d91ce-4122-4005-9a96-d0e3b7934aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669763451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.669763451
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3636817809
Short name T156
Test name
Test status
Simulation time 261882672449 ps
CPU time 211.58 seconds
Started May 21 01:46:16 PM PDT 24
Finished May 21 01:49:49 PM PDT 24
Peak memory 182888 kb
Host smart-f5469539-e0bc-4383-b81b-535272365373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636817809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3636817809
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1423033544
Short name T378
Test name
Test status
Simulation time 30425750 ps
CPU time 0.55 seconds
Started May 21 01:46:19 PM PDT 24
Finished May 21 01:46:20 PM PDT 24
Peak memory 182380 kb
Host smart-9707fd52-bfcb-4e90-a35e-101fff63c1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423033544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1423033544
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.793296986
Short name T18
Test name
Test status
Simulation time 81705435 ps
CPU time 1.01 seconds
Started May 21 01:46:08 PM PDT 24
Finished May 21 01:46:09 PM PDT 24
Peak memory 214328 kb
Host smart-67065886-0788-44d6-80b6-686cec59b933
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793296986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.793296986
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3926153198
Short name T137
Test name
Test status
Simulation time 414508917236 ps
CPU time 398.46 seconds
Started May 21 01:46:22 PM PDT 24
Finished May 21 01:53:04 PM PDT 24
Peak memory 182664 kb
Host smart-5efab828-6f5f-4986-8375-2d1be956804e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926153198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3926153198
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2392948263
Short name T384
Test name
Test status
Simulation time 54728056765 ps
CPU time 20.94 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:46:51 PM PDT 24
Peak memory 182684 kb
Host smart-64c16e7f-5039-496f-b991-7b42f78d55ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392948263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2392948263
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1501218157
Short name T292
Test name
Test status
Simulation time 93312988210 ps
CPU time 433.14 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:53:43 PM PDT 24
Peak memory 190884 kb
Host smart-a0f7eeec-4875-4f26-84bf-2e3e8d38a4a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501218157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1501218157
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.494845509
Short name T341
Test name
Test status
Simulation time 36719381415 ps
CPU time 61.6 seconds
Started May 21 01:46:26 PM PDT 24
Finished May 21 01:47:32 PM PDT 24
Peak memory 182648 kb
Host smart-32ba98e3-f502-47cb-bdd5-d0f65cc38985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494845509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.494845509
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.81668164
Short name T197
Test name
Test status
Simulation time 672297844740 ps
CPU time 888.76 seconds
Started May 21 01:46:28 PM PDT 24
Finished May 21 02:01:22 PM PDT 24
Peak memory 190856 kb
Host smart-dd6244ad-c9e7-4b1a-bb76-7d0bd2a52bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81668164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.81668164
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.841901652
Short name T44
Test name
Test status
Simulation time 13384313971 ps
CPU time 121.13 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:48:30 PM PDT 24
Peak memory 197312 kb
Host smart-0c364f66-06f3-4e80-8cc6-f2f34d3a51b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841901652 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.841901652
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3229850703
Short name T262
Test name
Test status
Simulation time 25379107455 ps
CPU time 30.75 seconds
Started May 21 01:46:26 PM PDT 24
Finished May 21 01:47:02 PM PDT 24
Peak memory 182660 kb
Host smart-ff3a218e-1e5b-4cba-ae24-cf214d39d27a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229850703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3229850703
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2362517489
Short name T363
Test name
Test status
Simulation time 20615566508 ps
CPU time 27.34 seconds
Started May 21 01:46:29 PM PDT 24
Finished May 21 01:47:02 PM PDT 24
Peak memory 182592 kb
Host smart-13059384-521c-4040-b312-24f0610b9297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362517489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2362517489
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2644346072
Short name T261
Test name
Test status
Simulation time 197022518379 ps
CPU time 857.38 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 02:00:46 PM PDT 24
Peak memory 190852 kb
Host smart-53f88551-6ac9-4d96-9729-e34092dcaaaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644346072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2644346072
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2386188485
Short name T10
Test name
Test status
Simulation time 15896266911 ps
CPU time 7.79 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:46:39 PM PDT 24
Peak memory 190856 kb
Host smart-9b314719-cfd3-4b60-a978-6febe6687934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386188485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2386188485
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.821153670
Short name T135
Test name
Test status
Simulation time 168166414928 ps
CPU time 85.16 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:47:54 PM PDT 24
Peak memory 182648 kb
Host smart-99badd79-3373-4a8f-8811-cfd8c82e581d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821153670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.821153670
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1125947591
Short name T3
Test name
Test status
Simulation time 121282969230 ps
CPU time 183.58 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:49:32 PM PDT 24
Peak memory 182624 kb
Host smart-758d0bc0-6d1c-4f44-902e-43462fc6e096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125947591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1125947591
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.4130514676
Short name T337
Test name
Test status
Simulation time 106913540768 ps
CPU time 1211.06 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 02:06:38 PM PDT 24
Peak memory 190860 kb
Host smart-897ffc4d-7a47-4294-bcbf-ee9b32e6f6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130514676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.4130514676
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2628625919
Short name T406
Test name
Test status
Simulation time 15975885 ps
CPU time 0.55 seconds
Started May 21 01:46:29 PM PDT 24
Finished May 21 01:46:35 PM PDT 24
Peak memory 182380 kb
Host smart-d3be8956-94a8-48fc-a8b9-835b835d3e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628625919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2628625919
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.517811584
Short name T300
Test name
Test status
Simulation time 599889736313 ps
CPU time 344.29 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:52:14 PM PDT 24
Peak memory 182568 kb
Host smart-13ab66e9-5290-4930-b9ff-76a9aa9bcd66
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517811584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.517811584
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3846201816
Short name T49
Test name
Test status
Simulation time 109292433823 ps
CPU time 169.07 seconds
Started May 21 01:46:21 PM PDT 24
Finished May 21 01:49:12 PM PDT 24
Peak memory 182596 kb
Host smart-77fb28af-6846-4d78-a61e-03edd4b721df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846201816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3846201816
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2025006934
Short name T74
Test name
Test status
Simulation time 205390242602 ps
CPU time 105.86 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:48:21 PM PDT 24
Peak memory 182592 kb
Host smart-c87cd24c-ed2b-4ded-801e-1b0372b31af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025006934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2025006934
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1822936231
Short name T302
Test name
Test status
Simulation time 270895161973 ps
CPU time 103 seconds
Started May 21 01:46:22 PM PDT 24
Finished May 21 01:48:07 PM PDT 24
Peak memory 193668 kb
Host smart-ca5815b9-52eb-4683-a9a0-0f133162c519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822936231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1822936231
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2621675087
Short name T67
Test name
Test status
Simulation time 1147357183241 ps
CPU time 485.58 seconds
Started May 21 01:46:22 PM PDT 24
Finished May 21 01:54:31 PM PDT 24
Peak memory 195324 kb
Host smart-4b357866-d846-42b4-9c44-d8b39c0b0fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621675087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2621675087
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1219314597
Short name T51
Test name
Test status
Simulation time 83759640933 ps
CPU time 505.72 seconds
Started May 21 01:46:26 PM PDT 24
Finished May 21 01:54:56 PM PDT 24
Peak memory 205516 kb
Host smart-1872fd0b-e83d-4af4-b8bc-1ee87fe570f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219314597 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.1219314597
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2468112634
Short name T216
Test name
Test status
Simulation time 133971425341 ps
CPU time 213.81 seconds
Started May 21 01:46:31 PM PDT 24
Finished May 21 01:50:09 PM PDT 24
Peak memory 182652 kb
Host smart-6624e027-c5ed-4e6e-b233-ff99f8020e70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468112634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2468112634
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3098242013
Short name T368
Test name
Test status
Simulation time 430950951987 ps
CPU time 104.97 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:48:20 PM PDT 24
Peak memory 182592 kb
Host smart-ff88de1a-433c-4cd8-8037-215b599d62c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098242013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3098242013
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1071597097
Short name T374
Test name
Test status
Simulation time 8019845764 ps
CPU time 15.13 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:46:51 PM PDT 24
Peak memory 194224 kb
Host smart-caa73955-1b05-475a-b4c4-2ea9c26baa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071597097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1071597097
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3349856878
Short name T147
Test name
Test status
Simulation time 56754027337 ps
CPU time 434.92 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:53:43 PM PDT 24
Peak memory 182704 kb
Host smart-c34f5ce7-f99f-4512-a55d-cc2ec087fdc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349856878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3349856878
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.722927675
Short name T64
Test name
Test status
Simulation time 253887952036 ps
CPU time 330.93 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 01:52:19 PM PDT 24
Peak memory 182660 kb
Host smart-922c4051-03cf-43b4-9b15-f7e79fa62b99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722927675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.722927675
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3587520168
Short name T401
Test name
Test status
Simulation time 298049293128 ps
CPU time 205.29 seconds
Started May 21 01:46:33 PM PDT 24
Finished May 21 01:50:02 PM PDT 24
Peak memory 182660 kb
Host smart-45b7ed0f-a06e-4a1f-9def-f9b5891f72e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587520168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3587520168
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3054830584
Short name T269
Test name
Test status
Simulation time 731198439433 ps
CPU time 987.31 seconds
Started May 21 01:46:26 PM PDT 24
Finished May 21 02:02:58 PM PDT 24
Peak memory 193224 kb
Host smart-4e8f1aad-1eff-4864-a6e4-07a6dd18d5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054830584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3054830584
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.4124908957
Short name T228
Test name
Test status
Simulation time 132099285491 ps
CPU time 86.71 seconds
Started May 21 01:46:40 PM PDT 24
Finished May 21 01:48:09 PM PDT 24
Peak memory 182640 kb
Host smart-04949c0b-3aa2-457a-b9b7-a447920f14d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124908957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.4124908957
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3966369127
Short name T331
Test name
Test status
Simulation time 95483040761 ps
CPU time 151.89 seconds
Started May 21 01:46:31 PM PDT 24
Finished May 21 01:49:08 PM PDT 24
Peak memory 182656 kb
Host smart-04349744-63ab-4fc8-8724-6801e855eb39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966369127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3966369127
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2937701214
Short name T448
Test name
Test status
Simulation time 495641539265 ps
CPU time 220.51 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:50:15 PM PDT 24
Peak memory 182660 kb
Host smart-83e8cca3-8846-4e7d-ae88-0e98d42eadd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937701214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2937701214
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3802927730
Short name T249
Test name
Test status
Simulation time 501631345476 ps
CPU time 391.4 seconds
Started May 21 01:46:34 PM PDT 24
Finished May 21 01:53:09 PM PDT 24
Peak memory 190820 kb
Host smart-a8e99a38-2f44-4f49-9520-7b93f43e5af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802927730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3802927730
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3772562573
Short name T369
Test name
Test status
Simulation time 875178218 ps
CPU time 1.84 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:46:33 PM PDT 24
Peak memory 190784 kb
Host smart-31d3a7a2-cd72-4450-87b4-c980cb468b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772562573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3772562573
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2076598272
Short name T109
Test name
Test status
Simulation time 101180692055 ps
CPU time 38.81 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:47:14 PM PDT 24
Peak memory 182672 kb
Host smart-9a8b003e-e4e6-4380-94f9-568161e6fd11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076598272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2076598272
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.531175205
Short name T179
Test name
Test status
Simulation time 92183217453 ps
CPU time 87.93 seconds
Started May 21 01:46:38 PM PDT 24
Finished May 21 01:48:08 PM PDT 24
Peak memory 182636 kb
Host smart-b4fae83e-d852-4aa9-b4aa-ebe13fb009cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531175205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.531175205
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.4103796442
Short name T397
Test name
Test status
Simulation time 93434481041 ps
CPU time 127.58 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:48:43 PM PDT 24
Peak memory 182632 kb
Host smart-9a8f9459-fe9d-477b-ad87-5d6ed06b1bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103796442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.4103796442
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1306827039
Short name T350
Test name
Test status
Simulation time 123799146827 ps
CPU time 913.29 seconds
Started May 21 01:46:41 PM PDT 24
Finished May 21 02:01:56 PM PDT 24
Peak memory 193880 kb
Host smart-d8b85d23-61fa-446c-9fc9-74d31d04b758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306827039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1306827039
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1767179649
Short name T400
Test name
Test status
Simulation time 1710269739 ps
CPU time 0.98 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:46:46 PM PDT 24
Peak memory 182436 kb
Host smart-6b549f8b-6882-4ec3-a1dd-14122fba0313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767179649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1767179649
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.4293651275
Short name T440
Test name
Test status
Simulation time 33836130 ps
CPU time 0.77 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:46:36 PM PDT 24
Peak memory 182332 kb
Host smart-f0fe0e1b-c7e3-40b0-a03e-72b23cbcab2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293651275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.4293651275
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2572482822
Short name T60
Test name
Test status
Simulation time 115267209216 ps
CPU time 184.82 seconds
Started May 21 01:46:36 PM PDT 24
Finished May 21 01:49:43 PM PDT 24
Peak memory 182664 kb
Host smart-629c9cca-a529-4a67-a1c3-9db2aea70b86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572482822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2572482822
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.578312990
Short name T75
Test name
Test status
Simulation time 218364683866 ps
CPU time 112.72 seconds
Started May 21 01:46:46 PM PDT 24
Finished May 21 01:48:40 PM PDT 24
Peak memory 182660 kb
Host smart-0364d383-73bd-4c09-8b92-f42dca636e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578312990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.578312990
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3032101345
Short name T414
Test name
Test status
Simulation time 816375872 ps
CPU time 4.04 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:46:36 PM PDT 24
Peak memory 193340 kb
Host smart-0a0a0e5f-037a-4e21-87d3-39640ef18c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032101345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3032101345
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1909691899
Short name T381
Test name
Test status
Simulation time 573501151800 ps
CPU time 240.85 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:50:33 PM PDT 24
Peak memory 182668 kb
Host smart-7e8f2797-25c1-480e-aded-45eac02c6637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909691899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1909691899
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1370497097
Short name T361
Test name
Test status
Simulation time 79668335096 ps
CPU time 121.86 seconds
Started May 21 01:46:34 PM PDT 24
Finished May 21 01:48:39 PM PDT 24
Peak memory 182672 kb
Host smart-a4c93089-3a26-4bf2-9e5e-9aab9d4d08bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370497097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1370497097
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.870002397
Short name T393
Test name
Test status
Simulation time 291427752978 ps
CPU time 98.02 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:48:05 PM PDT 24
Peak memory 182660 kb
Host smart-ff010c69-3e5f-4fc8-836a-f8f9b496eea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870002397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.870002397
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1398799630
Short name T394
Test name
Test status
Simulation time 747520349 ps
CPU time 1.71 seconds
Started May 21 01:46:28 PM PDT 24
Finished May 21 01:46:35 PM PDT 24
Peak memory 182420 kb
Host smart-413ca44b-157b-4dec-a1e5-867b2d1374b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398799630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1398799630
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.155001567
Short name T320
Test name
Test status
Simulation time 1442833115866 ps
CPU time 788.54 seconds
Started May 21 01:46:15 PM PDT 24
Finished May 21 01:59:25 PM PDT 24
Peak memory 182648 kb
Host smart-b535ac8d-ecaf-4ec1-9720-30846c9a5005
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155001567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.155001567
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.261410600
Short name T373
Test name
Test status
Simulation time 26813910391 ps
CPU time 37.53 seconds
Started May 21 01:46:03 PM PDT 24
Finished May 21 01:46:41 PM PDT 24
Peak memory 182664 kb
Host smart-523f7fe0-7928-4407-a541-bc3241df0303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261410600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.261410600
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.276105419
Short name T22
Test name
Test status
Simulation time 220910949223 ps
CPU time 263.34 seconds
Started May 21 01:46:13 PM PDT 24
Finished May 21 01:50:38 PM PDT 24
Peak memory 190880 kb
Host smart-39db58c0-35e0-4703-b60e-f6a704ac5716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276105419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.276105419
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1588049508
Short name T142
Test name
Test status
Simulation time 77975268970 ps
CPU time 56.87 seconds
Started May 21 01:46:08 PM PDT 24
Finished May 21 01:47:05 PM PDT 24
Peak memory 194520 kb
Host smart-6f8da1df-7ca7-41e3-a375-c2c17cde61c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588049508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1588049508
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2500387742
Short name T16
Test name
Test status
Simulation time 385039819 ps
CPU time 1.27 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:46:36 PM PDT 24
Peak memory 213140 kb
Host smart-7adb09f3-15ec-4ec4-80fe-de818b0f6919
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500387742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2500387742
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2861296930
Short name T145
Test name
Test status
Simulation time 88654504529 ps
CPU time 41.98 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:47:10 PM PDT 24
Peak memory 182668 kb
Host smart-3284e74c-5857-4aee-b13d-1f90dfedc70d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861296930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2861296930
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.668342814
Short name T81
Test name
Test status
Simulation time 749711404984 ps
CPU time 289.17 seconds
Started May 21 01:46:37 PM PDT 24
Finished May 21 01:51:29 PM PDT 24
Peak memory 182636 kb
Host smart-e4b0cd3a-af3e-4532-8da8-90384066428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668342814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.668342814
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2495249794
Short name T233
Test name
Test status
Simulation time 182398724489 ps
CPU time 28.1 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:47:03 PM PDT 24
Peak memory 190796 kb
Host smart-68ac242d-2fdc-4bde-bb6e-a2589835f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495249794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2495249794
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2575217479
Short name T241
Test name
Test status
Simulation time 100261925346 ps
CPU time 169.71 seconds
Started May 21 01:46:31 PM PDT 24
Finished May 21 01:49:26 PM PDT 24
Peak memory 182664 kb
Host smart-c4832be7-1bde-433f-931c-69ecd110e3fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575217479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2575217479
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.126072234
Short name T376
Test name
Test status
Simulation time 393658790160 ps
CPU time 151.5 seconds
Started May 21 01:46:38 PM PDT 24
Finished May 21 01:49:12 PM PDT 24
Peak memory 182684 kb
Host smart-4e8fb147-2537-4435-a88c-edf4f9acaa38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126072234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.126072234
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2131959074
Short name T313
Test name
Test status
Simulation time 450095310054 ps
CPU time 294.06 seconds
Started May 21 01:46:32 PM PDT 24
Finished May 21 01:51:30 PM PDT 24
Peak memory 193252 kb
Host smart-4dfb583d-b804-499c-9d44-32b5325ddf52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131959074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2131959074
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.525489962
Short name T250
Test name
Test status
Simulation time 123778905008 ps
CPU time 72.43 seconds
Started May 21 01:46:29 PM PDT 24
Finished May 21 01:47:46 PM PDT 24
Peak memory 182680 kb
Host smart-3003305b-f2b2-4c05-9edf-2c72c2bb501d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525489962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.525489962
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2571709601
Short name T392
Test name
Test status
Simulation time 1779319796762 ps
CPU time 529.68 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:55:18 PM PDT 24
Peak memory 190868 kb
Host smart-d105c6da-4d0b-4580-aaf4-f7c957a58ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571709601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2571709601
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2994373538
Short name T161
Test name
Test status
Simulation time 54828320250 ps
CPU time 87.98 seconds
Started May 21 01:46:44 PM PDT 24
Finished May 21 01:48:14 PM PDT 24
Peak memory 182652 kb
Host smart-f1752ffd-e33c-423c-8909-8b435f867146
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994373538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2994373538
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3911288039
Short name T385
Test name
Test status
Simulation time 144808303988 ps
CPU time 210.89 seconds
Started May 21 01:46:31 PM PDT 24
Finished May 21 01:50:07 PM PDT 24
Peak memory 182660 kb
Host smart-fe39f7ca-aebf-406d-a6a6-2e1d366b5aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911288039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3911288039
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2916200274
Short name T273
Test name
Test status
Simulation time 74020151264 ps
CPU time 387.02 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:53:12 PM PDT 24
Peak memory 190880 kb
Host smart-e5a76fac-80f2-4921-afb8-389e42b5244d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916200274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2916200274
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2454891387
Short name T402
Test name
Test status
Simulation time 122378867 ps
CPU time 0.74 seconds
Started May 21 01:46:29 PM PDT 24
Finished May 21 01:46:35 PM PDT 24
Peak memory 182460 kb
Host smart-f05d90d8-f3d6-4f0e-8da4-88f29f21ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454891387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2454891387
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1410987665
Short name T192
Test name
Test status
Simulation time 635320774498 ps
CPU time 1052.91 seconds
Started May 21 01:46:45 PM PDT 24
Finished May 21 02:04:20 PM PDT 24
Peak memory 195012 kb
Host smart-fbdaba9f-0859-4dd6-a446-5e5a0e7a6bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410987665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1410987665
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.1041852193
Short name T43
Test name
Test status
Simulation time 159900784511 ps
CPU time 1593.39 seconds
Started May 21 01:46:38 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 219836 kb
Host smart-b18cc026-9e1f-478a-b92f-2b589f08c038
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041852193 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.1041852193
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3275307481
Short name T430
Test name
Test status
Simulation time 1724814553271 ps
CPU time 560.84 seconds
Started May 21 01:46:40 PM PDT 24
Finished May 21 01:56:03 PM PDT 24
Peak memory 182656 kb
Host smart-174b9d92-86bf-4d2e-a22a-655cc9dce22a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275307481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3275307481
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3877076842
Short name T398
Test name
Test status
Simulation time 72143779038 ps
CPU time 112.48 seconds
Started May 21 01:46:44 PM PDT 24
Finished May 21 01:48:39 PM PDT 24
Peak memory 182680 kb
Host smart-feec2bb9-a8c7-4f59-ac44-7694d4ebc423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877076842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3877076842
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1695722133
Short name T293
Test name
Test status
Simulation time 589662716241 ps
CPU time 339.9 seconds
Started May 21 01:46:32 PM PDT 24
Finished May 21 01:52:16 PM PDT 24
Peak memory 190840 kb
Host smart-95c2ff23-d767-4c8d-8de9-392d08453672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695722133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1695722133
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.922127245
Short name T405
Test name
Test status
Simulation time 37398888 ps
CPU time 0.56 seconds
Started May 21 01:46:56 PM PDT 24
Finished May 21 01:47:01 PM PDT 24
Peak memory 181900 kb
Host smart-62bb4b55-a461-42be-a79b-6fa8eefb9261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922127245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
922127245
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.665346623
Short name T362
Test name
Test status
Simulation time 219780066507 ps
CPU time 163.18 seconds
Started May 21 01:46:38 PM PDT 24
Finished May 21 01:49:24 PM PDT 24
Peak memory 182640 kb
Host smart-2c772e43-02b6-42d0-92d8-2f3845f6f8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665346623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.665346623
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3708933253
Short name T234
Test name
Test status
Simulation time 172382803106 ps
CPU time 2459.07 seconds
Started May 21 01:46:40 PM PDT 24
Finished May 21 02:27:41 PM PDT 24
Peak memory 190812 kb
Host smart-f4f2c001-379c-417d-bb97-04d0712ed59b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708933253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3708933253
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2688669007
Short name T433
Test name
Test status
Simulation time 163519153923 ps
CPU time 77.52 seconds
Started May 21 01:46:44 PM PDT 24
Finished May 21 01:48:04 PM PDT 24
Peak memory 182656 kb
Host smart-41b96d62-4e44-4a38-9a6a-29b38ce93936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688669007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2688669007
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1641415874
Short name T446
Test name
Test status
Simulation time 71571066830 ps
CPU time 39.05 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 01:47:33 PM PDT 24
Peak memory 182700 kb
Host smart-b8466450-7b28-4736-810a-136e351f8f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641415874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1641415874
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.4248637271
Short name T326
Test name
Test status
Simulation time 62725940484 ps
CPU time 116.91 seconds
Started May 21 01:46:31 PM PDT 24
Finished May 21 01:48:32 PM PDT 24
Peak memory 182652 kb
Host smart-8fdcbbed-a85a-44b8-8d35-3e93ec5f8489
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248637271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.4248637271
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2106640732
Short name T370
Test name
Test status
Simulation time 97682740834 ps
CPU time 74.62 seconds
Started May 21 01:46:38 PM PDT 24
Finished May 21 01:47:55 PM PDT 24
Peak memory 182648 kb
Host smart-8d7e4991-2e53-4c47-9d9d-01bdd79a05d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106640732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2106640732
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3516570612
Short name T257
Test name
Test status
Simulation time 39757840574 ps
CPU time 65.46 seconds
Started May 21 01:46:49 PM PDT 24
Finished May 21 01:47:57 PM PDT 24
Peak memory 182596 kb
Host smart-c0030e2a-5525-4fb0-a2a8-61cdac933f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516570612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3516570612
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3572194464
Short name T429
Test name
Test status
Simulation time 705098996168 ps
CPU time 286.91 seconds
Started May 21 01:46:49 PM PDT 24
Finished May 21 01:51:38 PM PDT 24
Peak memory 182624 kb
Host smart-380e86b0-2ae1-4043-9054-b3584c7849d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572194464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3572194464
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2630263304
Short name T136
Test name
Test status
Simulation time 243399003674 ps
CPU time 377.12 seconds
Started May 21 01:46:44 PM PDT 24
Finished May 21 01:53:03 PM PDT 24
Peak memory 190880 kb
Host smart-0f3c1855-4778-47fe-89a9-be4f03a7a885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630263304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2630263304
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1393317780
Short name T242
Test name
Test status
Simulation time 42660743881 ps
CPU time 330.46 seconds
Started May 21 01:46:50 PM PDT 24
Finished May 21 01:52:23 PM PDT 24
Peak memory 182628 kb
Host smart-67f02fbd-2831-46ef-a558-d35384533072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393317780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1393317780
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.478104537
Short name T38
Test name
Test status
Simulation time 51450181992 ps
CPU time 105.4 seconds
Started May 21 01:46:48 PM PDT 24
Finished May 21 01:48:35 PM PDT 24
Peak memory 197268 kb
Host smart-3c5c6208-c17a-46c5-a451-807184c9e5bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478104537 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.478104537
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.6487982
Short name T252
Test name
Test status
Simulation time 47526733132 ps
CPU time 25.38 seconds
Started May 21 01:46:40 PM PDT 24
Finished May 21 01:47:07 PM PDT 24
Peak memory 182676 kb
Host smart-e625c1eb-3d1b-4fa7-b329-995620b9ac77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6487982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
rv_timer_cfg_update_on_fly.6487982
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3485915902
Short name T420
Test name
Test status
Simulation time 39060725653 ps
CPU time 32.47 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:47:17 PM PDT 24
Peak memory 182652 kb
Host smart-9d8d6aab-d41b-42d6-bab8-c4e42d3a2555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485915902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3485915902
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.951566137
Short name T82
Test name
Test status
Simulation time 162864960600 ps
CPU time 759.18 seconds
Started May 21 01:46:32 PM PDT 24
Finished May 21 01:59:16 PM PDT 24
Peak memory 190880 kb
Host smart-9993341d-9f1b-4c63-9531-60dbffe4b8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951566137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.951566137
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.4070089843
Short name T283
Test name
Test status
Simulation time 51672512782 ps
CPU time 92.14 seconds
Started May 21 01:46:45 PM PDT 24
Finished May 21 01:48:19 PM PDT 24
Peak memory 190840 kb
Host smart-b15f64dc-0c61-4d61-b968-f12a5d787737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070089843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.4070089843
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4137980847
Short name T210
Test name
Test status
Simulation time 483437132291 ps
CPU time 173.93 seconds
Started May 21 01:46:41 PM PDT 24
Finished May 21 01:49:36 PM PDT 24
Peak memory 182608 kb
Host smart-ed052b54-ba7f-4ebe-a0a1-11d2f65f731e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137980847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4137980847
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1556103760
Short name T386
Test name
Test status
Simulation time 37940482889 ps
CPU time 51.4 seconds
Started May 21 01:46:37 PM PDT 24
Finished May 21 01:47:31 PM PDT 24
Peak memory 182692 kb
Host smart-545dc74a-e48f-4591-8bdd-3dc141655d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556103760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1556103760
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2767405670
Short name T133
Test name
Test status
Simulation time 147843995763 ps
CPU time 548.8 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 01:56:03 PM PDT 24
Peak memory 190788 kb
Host smart-81567adf-df11-48f3-bdec-f84167f648e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767405670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2767405670
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.18062354
Short name T404
Test name
Test status
Simulation time 56690246429 ps
CPU time 43.82 seconds
Started May 21 01:46:36 PM PDT 24
Finished May 21 01:47:22 PM PDT 24
Peak memory 182624 kb
Host smart-905c4db2-92a1-4df9-892d-985f36cb25c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18062354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.18062354
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1687356164
Short name T411
Test name
Test status
Simulation time 8359879820 ps
CPU time 4.2 seconds
Started May 21 01:46:31 PM PDT 24
Finished May 21 01:46:40 PM PDT 24
Peak memory 182652 kb
Host smart-3d18b9b0-b50a-46c5-930c-a9f1ec1e78e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687356164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1687356164
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.400741094
Short name T11
Test name
Test status
Simulation time 40236759 ps
CPU time 0.52 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:46:45 PM PDT 24
Peak memory 182464 kb
Host smart-2ab254a6-be0f-46f8-a3dd-f6a7dad62c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400741094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.400741094
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2057861093
Short name T244
Test name
Test status
Simulation time 708243995323 ps
CPU time 412.22 seconds
Started May 21 01:46:40 PM PDT 24
Finished May 21 01:53:34 PM PDT 24
Peak memory 190888 kb
Host smart-df09fb60-2830-4ff0-a994-bf5d0015c956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057861093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2057861093
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.431647632
Short name T188
Test name
Test status
Simulation time 100665358479 ps
CPU time 163.66 seconds
Started May 21 01:46:26 PM PDT 24
Finished May 21 01:49:14 PM PDT 24
Peak memory 182640 kb
Host smart-4708edab-e43a-4132-8fb6-7e75b6be0ef4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431647632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.431647632
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3421354116
Short name T413
Test name
Test status
Simulation time 131364023150 ps
CPU time 108.18 seconds
Started May 21 01:46:13 PM PDT 24
Finished May 21 01:48:02 PM PDT 24
Peak memory 182636 kb
Host smart-19466f7e-61d1-4c85-8d3c-e96a6a537ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421354116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3421354116
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1111236647
Short name T83
Test name
Test status
Simulation time 68153145305 ps
CPU time 266.91 seconds
Started May 21 01:46:38 PM PDT 24
Finished May 21 01:51:07 PM PDT 24
Peak memory 190844 kb
Host smart-aa9545c5-27a3-4024-b2ef-4449e6444dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111236647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1111236647
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4161941695
Short name T20
Test name
Test status
Simulation time 51405104 ps
CPU time 0.73 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:46:45 PM PDT 24
Peak memory 213788 kb
Host smart-cca751c1-e4c7-4afa-be7d-e1f0466fa6c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161941695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4161941695
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.779453796
Short name T264
Test name
Test status
Simulation time 338212097515 ps
CPU time 324.7 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:52:09 PM PDT 24
Peak memory 182648 kb
Host smart-deffae1a-b069-44dd-beac-84cfc94f9e66
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779453796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.779453796
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.994438082
Short name T114
Test name
Test status
Simulation time 409877529674 ps
CPU time 175.86 seconds
Started May 21 01:46:52 PM PDT 24
Finished May 21 01:49:52 PM PDT 24
Peak memory 182688 kb
Host smart-9e572b1d-aa02-4311-a9ca-13a18251e141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994438082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.994438082
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1189904983
Short name T218
Test name
Test status
Simulation time 57291458622 ps
CPU time 136.5 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:49:02 PM PDT 24
Peak memory 194324 kb
Host smart-1f2c3424-e83b-44e3-a3f5-453aa2e06ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189904983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1189904983
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3122732392
Short name T209
Test name
Test status
Simulation time 286182288778 ps
CPU time 279 seconds
Started May 21 01:46:52 PM PDT 24
Finished May 21 01:51:35 PM PDT 24
Peak memory 182632 kb
Host smart-45a2ae9b-e83d-4f74-a652-264cc1263bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122732392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3122732392
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1776274163
Short name T288
Test name
Test status
Simulation time 1005240630688 ps
CPU time 1943.44 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 02:19:18 PM PDT 24
Peak memory 190836 kb
Host smart-2f15a91c-7f8b-4fb0-870e-f103c3a4003a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776274163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1776274163
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1173049665
Short name T58
Test name
Test status
Simulation time 1136644081354 ps
CPU time 650.5 seconds
Started May 21 01:46:44 PM PDT 24
Finished May 21 01:57:36 PM PDT 24
Peak memory 182696 kb
Host smart-e2c01b2a-0f27-44ac-9e07-9f593392e8dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173049665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1173049665
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3089713626
Short name T375
Test name
Test status
Simulation time 155198743896 ps
CPU time 207.75 seconds
Started May 21 01:46:43 PM PDT 24
Finished May 21 01:50:11 PM PDT 24
Peak memory 182680 kb
Host smart-2788dac2-7f85-4b76-8115-bc0b5c807728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089713626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3089713626
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1830305799
Short name T323
Test name
Test status
Simulation time 163132529210 ps
CPU time 158.51 seconds
Started May 21 01:46:50 PM PDT 24
Finished May 21 01:49:31 PM PDT 24
Peak memory 190784 kb
Host smart-ca2ebb80-91c3-45a4-9331-244a0d808a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830305799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1830305799
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.209791175
Short name T412
Test name
Test status
Simulation time 184876634 ps
CPU time 0.69 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 01:46:49 PM PDT 24
Peak memory 182412 kb
Host smart-50f31c1e-5f9e-493d-a8c5-48fde7d2f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209791175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.209791175
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3480266121
Short name T347
Test name
Test status
Simulation time 53503487745 ps
CPU time 14.89 seconds
Started May 21 01:46:52 PM PDT 24
Finished May 21 01:47:10 PM PDT 24
Peak memory 182664 kb
Host smart-0b25a3e4-3672-4c62-b284-033f584b5021
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480266121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3480266121
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3503260519
Short name T372
Test name
Test status
Simulation time 190633505359 ps
CPU time 82.46 seconds
Started May 21 01:46:54 PM PDT 24
Finished May 21 01:48:21 PM PDT 24
Peak memory 182032 kb
Host smart-013e8e7e-fb16-493b-852d-e0a9b9156741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503260519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3503260519
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.963402122
Short name T164
Test name
Test status
Simulation time 14058056956 ps
CPU time 16.14 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 01:47:10 PM PDT 24
Peak memory 182632 kb
Host smart-91a511f6-2cb2-4986-8407-0704433bb58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963402122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.963402122
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2547962053
Short name T32
Test name
Test status
Simulation time 128777914560 ps
CPU time 176.11 seconds
Started May 21 01:46:35 PM PDT 24
Finished May 21 01:49:34 PM PDT 24
Peak memory 194352 kb
Host smart-11ce4bc2-52bf-4935-a333-9015d24169d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547962053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2547962053
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2998130425
Short name T174
Test name
Test status
Simulation time 238661189833 ps
CPU time 125.76 seconds
Started May 21 01:46:44 PM PDT 24
Finished May 21 01:48:52 PM PDT 24
Peak memory 182696 kb
Host smart-bb865ae9-4e79-42ba-aba5-1c77ae73d5fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998130425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2998130425
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1423142909
Short name T421
Test name
Test status
Simulation time 398573194316 ps
CPU time 173.56 seconds
Started May 21 01:46:39 PM PDT 24
Finished May 21 01:49:35 PM PDT 24
Peak memory 182636 kb
Host smart-5fe2672d-f32c-4523-9e16-f1fa5d39eb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423142909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1423142909
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.4198975484
Short name T422
Test name
Test status
Simulation time 295865798529 ps
CPU time 90.99 seconds
Started May 21 01:46:45 PM PDT 24
Finished May 21 01:48:18 PM PDT 24
Peak memory 182676 kb
Host smart-d894a035-2971-4613-a817-5b4dfb14f3a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198975484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4198975484
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2563147101
Short name T254
Test name
Test status
Simulation time 73348603617 ps
CPU time 83.47 seconds
Started May 21 01:46:35 PM PDT 24
Finished May 21 01:48:01 PM PDT 24
Peak memory 190836 kb
Host smart-c04bc35a-bc77-4b05-ae14-eb591bcb2c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563147101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2563147101
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1300781528
Short name T28
Test name
Test status
Simulation time 1136311793234 ps
CPU time 1002.55 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 02:03:37 PM PDT 24
Peak memory 190872 kb
Host smart-60abdad0-f267-441c-9765-cef259b7e654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300781528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1300781528
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.504383930
Short name T42
Test name
Test status
Simulation time 103075909338 ps
CPU time 289.13 seconds
Started May 21 01:46:39 PM PDT 24
Finished May 21 01:51:30 PM PDT 24
Peak memory 206792 kb
Host smart-969522ce-5fe9-4386-ae9b-0b7d56b6f05d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504383930 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.504383930
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1978206364
Short name T383
Test name
Test status
Simulation time 51876733990 ps
CPU time 77.52 seconds
Started May 21 01:46:54 PM PDT 24
Finished May 21 01:48:15 PM PDT 24
Peak memory 182588 kb
Host smart-84fdafef-6402-4d6d-ac58-4d1de460f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978206364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1978206364
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3516674718
Short name T407
Test name
Test status
Simulation time 393818764005 ps
CPU time 369.95 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 01:52:58 PM PDT 24
Peak memory 182648 kb
Host smart-f156b1b0-11a8-4f13-aa56-0572b2cfe2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516674718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3516674718
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3302282463
Short name T352
Test name
Test status
Simulation time 34895748679 ps
CPU time 50.59 seconds
Started May 21 01:46:41 PM PDT 24
Finished May 21 01:47:33 PM PDT 24
Peak memory 182648 kb
Host smart-79f44f0a-4f56-4326-9570-0335949bf7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302282463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3302282463
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1832933830
Short name T289
Test name
Test status
Simulation time 138715548635 ps
CPU time 197.84 seconds
Started May 21 01:46:54 PM PDT 24
Finished May 21 01:50:17 PM PDT 24
Peak memory 190728 kb
Host smart-253e86f9-b86f-4b8f-a0bf-f5cdf89e633a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832933830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1832933830
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4202107684
Short name T76
Test name
Test status
Simulation time 141024123831 ps
CPU time 247.9 seconds
Started May 21 01:46:49 PM PDT 24
Finished May 21 01:51:00 PM PDT 24
Peak memory 182576 kb
Host smart-7368f29f-8ad3-491d-b3fb-b61470a58b3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202107684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4202107684
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3371207570
Short name T78
Test name
Test status
Simulation time 723603931582 ps
CPU time 319.91 seconds
Started May 21 01:46:55 PM PDT 24
Finished May 21 01:52:20 PM PDT 24
Peak memory 182580 kb
Host smart-258fba57-23b3-439f-9896-9caa525a77d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371207570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3371207570
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.322324645
Short name T259
Test name
Test status
Simulation time 84436020868 ps
CPU time 102.64 seconds
Started May 21 01:46:40 PM PDT 24
Finished May 21 01:48:24 PM PDT 24
Peak memory 182608 kb
Host smart-92fbe4ed-8e91-4823-8f42-f733c8199e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322324645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.322324645
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2262929389
Short name T310
Test name
Test status
Simulation time 336284381788 ps
CPU time 189.44 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 01:49:58 PM PDT 24
Peak memory 182660 kb
Host smart-048321d8-6355-4cd6-bb01-9c3ed1ef4eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262929389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2262929389
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2844760693
Short name T79
Test name
Test status
Simulation time 470580101567 ps
CPU time 198.95 seconds
Started May 21 01:46:46 PM PDT 24
Finished May 21 01:50:06 PM PDT 24
Peak memory 182696 kb
Host smart-75e0f964-46ee-4ef1-84ba-50317f6b5c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844760693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2844760693
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1142706153
Short name T355
Test name
Test status
Simulation time 747260883473 ps
CPU time 406.5 seconds
Started May 21 01:46:45 PM PDT 24
Finished May 21 01:53:34 PM PDT 24
Peak memory 182664 kb
Host smart-5c3a9ca0-92c1-4aad-a9e8-eaefa41d4162
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142706153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1142706153
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.630116247
Short name T377
Test name
Test status
Simulation time 72045989400 ps
CPU time 97.03 seconds
Started May 21 01:46:46 PM PDT 24
Finished May 21 01:48:24 PM PDT 24
Peak memory 182676 kb
Host smart-e4341df4-d94f-440d-84ee-141d494c0557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630116247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.630116247
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.305858202
Short name T85
Test name
Test status
Simulation time 109885538469 ps
CPU time 175.76 seconds
Started May 21 01:46:46 PM PDT 24
Finished May 21 01:49:43 PM PDT 24
Peak memory 193548 kb
Host smart-e24394da-4d67-43be-8d4a-8cecff730062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305858202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.305858202
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.561307035
Short name T12
Test name
Test status
Simulation time 44002405009 ps
CPU time 846.81 seconds
Started May 21 01:46:54 PM PDT 24
Finished May 21 02:01:04 PM PDT 24
Peak memory 190824 kb
Host smart-d9406ff1-d20f-4d76-8532-917147b66c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561307035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.561307035
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3565587844
Short name T202
Test name
Test status
Simulation time 1091811469736 ps
CPU time 584.71 seconds
Started May 21 01:46:57 PM PDT 24
Finished May 21 01:56:46 PM PDT 24
Peak memory 182584 kb
Host smart-2ce7e551-7d03-4409-bdb5-f6185b0d07b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565587844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3565587844
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.959213354
Short name T442
Test name
Test status
Simulation time 197287494205 ps
CPU time 88.79 seconds
Started May 21 01:46:55 PM PDT 24
Finished May 21 01:48:29 PM PDT 24
Peak memory 182572 kb
Host smart-b34e15a5-cb44-42d0-aa7f-0b33a5cb7a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959213354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.959213354
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1597429873
Short name T128
Test name
Test status
Simulation time 116295595678 ps
CPU time 565.98 seconds
Started May 21 01:46:57 PM PDT 24
Finished May 21 01:56:27 PM PDT 24
Peak memory 194332 kb
Host smart-bc36f15a-edfb-4a4e-9de1-b1ae9940f77d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597429873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1597429873
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2329379856
Short name T434
Test name
Test status
Simulation time 720153048 ps
CPU time 6.82 seconds
Started May 21 01:46:53 PM PDT 24
Finished May 21 01:47:04 PM PDT 24
Peak memory 191392 kb
Host smart-f68e9969-857d-474b-ab7c-55e0091ea6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329379856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2329379856
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1274834685
Short name T150
Test name
Test status
Simulation time 208369599999 ps
CPU time 747.18 seconds
Started May 21 01:46:48 PM PDT 24
Finished May 21 01:59:17 PM PDT 24
Peak memory 190852 kb
Host smart-1fd7c6e8-f27e-4365-9658-1376c6759c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274834685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1274834685
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1523127090
Short name T410
Test name
Test status
Simulation time 124668560857 ps
CPU time 202.36 seconds
Started May 21 01:46:59 PM PDT 24
Finished May 21 01:50:25 PM PDT 24
Peak memory 182640 kb
Host smart-1c0f7335-4cde-4f5a-b399-7a34f5d5ffa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523127090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1523127090
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2795606007
Short name T165
Test name
Test status
Simulation time 92761516108 ps
CPU time 326.69 seconds
Started May 21 01:46:56 PM PDT 24
Finished May 21 01:52:27 PM PDT 24
Peak memory 190848 kb
Host smart-1e4b152a-454c-4e04-838a-c28079105b28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795606007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2795606007
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3019993203
Short name T274
Test name
Test status
Simulation time 138670966292 ps
CPU time 390.45 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 01:53:18 PM PDT 24
Peak memory 194272 kb
Host smart-233b033b-17e5-455e-87fd-3d429fab4faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019993203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3019993203
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.801801968
Short name T68
Test name
Test status
Simulation time 687997411724 ps
CPU time 734.04 seconds
Started May 21 01:46:50 PM PDT 24
Finished May 21 01:59:07 PM PDT 24
Peak memory 190868 kb
Host smart-bd60c6b4-8998-412c-9461-02b29537542b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801801968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
801801968
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.222255620
Short name T205
Test name
Test status
Simulation time 1536755348594 ps
CPU time 761.4 seconds
Started May 21 01:46:56 PM PDT 24
Finished May 21 01:59:42 PM PDT 24
Peak memory 182628 kb
Host smart-0d8cb46f-ed5c-4123-9b0f-d81265c0e23a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222255620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.222255620
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.201777162
Short name T380
Test name
Test status
Simulation time 639584473067 ps
CPU time 291.33 seconds
Started May 21 01:46:51 PM PDT 24
Finished May 21 01:51:45 PM PDT 24
Peak memory 182688 kb
Host smart-922cb44d-82b7-4487-aa41-f004bf30a895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201777162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.201777162
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2958513631
Short name T418
Test name
Test status
Simulation time 268947243033 ps
CPU time 134.53 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 01:49:03 PM PDT 24
Peak memory 190868 kb
Host smart-998ebb82-7cb9-480d-a53e-b0efff924da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958513631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2958513631
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2025051576
Short name T366
Test name
Test status
Simulation time 222617563 ps
CPU time 0.76 seconds
Started May 21 01:46:57 PM PDT 24
Finished May 21 01:47:02 PM PDT 24
Peak memory 182372 kb
Host smart-e6987c8c-c259-4ecd-931f-de691f7449c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025051576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2025051576
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2333059330
Short name T70
Test name
Test status
Simulation time 83354718 ps
CPU time 0.67 seconds
Started May 21 01:46:45 PM PDT 24
Finished May 21 01:46:47 PM PDT 24
Peak memory 182404 kb
Host smart-021287fa-6950-470b-84e8-0b18233ae029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333059330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2333059330
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2948799991
Short name T41
Test name
Test status
Simulation time 99345231255 ps
CPU time 882.65 seconds
Started May 21 01:46:47 PM PDT 24
Finished May 21 02:01:31 PM PDT 24
Peak memory 207564 kb
Host smart-67be3e7a-958b-4133-817f-9a9645eaf0a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948799991 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2948799991
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3314631845
Short name T425
Test name
Test status
Simulation time 624109711573 ps
CPU time 273.64 seconds
Started May 21 01:46:28 PM PDT 24
Finished May 21 01:51:07 PM PDT 24
Peak memory 182648 kb
Host smart-99bd3bad-2074-46ba-912e-d5e2bade2431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314631845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3314631845
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3216464411
Short name T287
Test name
Test status
Simulation time 8173327190 ps
CPU time 12.05 seconds
Started May 21 01:46:15 PM PDT 24
Finished May 21 01:46:28 PM PDT 24
Peak memory 182648 kb
Host smart-6e914f89-269a-4c4c-8001-7896de486cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216464411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3216464411
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3719996205
Short name T307
Test name
Test status
Simulation time 117523887272 ps
CPU time 104.44 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:48:11 PM PDT 24
Peak memory 190848 kb
Host smart-1e18e375-fc11-48c4-89be-b7d998af48c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719996205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3719996205
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1013999260
Short name T112
Test name
Test status
Simulation time 25503331383 ps
CPU time 25.88 seconds
Started May 21 01:46:54 PM PDT 24
Finished May 21 01:47:24 PM PDT 24
Peak memory 182580 kb
Host smart-4d2eb288-47a0-449c-a9b3-7e7ba0dd9239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013999260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1013999260
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1466168221
Short name T9
Test name
Test status
Simulation time 496772725 ps
CPU time 1.31 seconds
Started May 21 01:46:50 PM PDT 24
Finished May 21 01:46:55 PM PDT 24
Peak memory 182428 kb
Host smart-8f0b465e-e77b-4c57-9a1c-045e0c6d4623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466168221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1466168221
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1354441659
Short name T57
Test name
Test status
Simulation time 773297415764 ps
CPU time 836.31 seconds
Started May 21 01:46:50 PM PDT 24
Finished May 21 02:00:50 PM PDT 24
Peak memory 190876 kb
Host smart-7d9fe723-3532-4142-9f0d-a3a8a5e0207d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354441659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1354441659
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1281415433
Short name T408
Test name
Test status
Simulation time 479654409386 ps
CPU time 218.44 seconds
Started May 21 01:46:50 PM PDT 24
Finished May 21 01:50:31 PM PDT 24
Peak memory 193052 kb
Host smart-b0d36e71-232b-46e1-8313-3f29bc7c2aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281415433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1281415433
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2282690655
Short name T423
Test name
Test status
Simulation time 461596931938 ps
CPU time 1083.67 seconds
Started May 21 01:46:55 PM PDT 24
Finished May 21 02:05:03 PM PDT 24
Peak memory 190776 kb
Host smart-4761ee0c-3b80-45fc-a9b4-54ee4d20b73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282690655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2282690655
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3971426774
Short name T143
Test name
Test status
Simulation time 90066933027 ps
CPU time 3409.13 seconds
Started May 21 01:46:57 PM PDT 24
Finished May 21 02:43:51 PM PDT 24
Peak memory 190764 kb
Host smart-6f3eabbe-5f69-42fa-b876-e66fa36afa64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971426774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3971426774
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3358923404
Short name T24
Test name
Test status
Simulation time 137476837112 ps
CPU time 207.45 seconds
Started May 21 01:46:55 PM PDT 24
Finished May 21 01:50:27 PM PDT 24
Peak memory 190844 kb
Host smart-abb8e798-cdcc-4ca4-ab2a-97b0b2b9a8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358923404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3358923404
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1859697564
Short name T428
Test name
Test status
Simulation time 39590716322 ps
CPU time 66.76 seconds
Started May 21 01:46:54 PM PDT 24
Finished May 21 01:48:04 PM PDT 24
Peak memory 182692 kb
Host smart-01486a0d-0659-422c-acd5-09af732ad859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859697564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1859697564
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3717643236
Short name T77
Test name
Test status
Simulation time 282528207631 ps
CPU time 278.34 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:51:05 PM PDT 24
Peak memory 182684 kb
Host smart-e4355452-7678-4ddb-898f-a071f4d02c92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717643236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3717643236
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.756883834
Short name T391
Test name
Test status
Simulation time 921901737423 ps
CPU time 213.34 seconds
Started May 21 01:46:40 PM PDT 24
Finished May 21 01:50:15 PM PDT 24
Peak memory 182652 kb
Host smart-df1ecbdf-5399-4aa9-89fe-728cba26eea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756883834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.756883834
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.319069974
Short name T141
Test name
Test status
Simulation time 89611617800 ps
CPU time 147.75 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 01:49:01 PM PDT 24
Peak memory 190832 kb
Host smart-bc6da5b3-1878-414f-ba97-7a76f5c24b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319069974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.319069974
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2424248806
Short name T438
Test name
Test status
Simulation time 108790774894 ps
CPU time 433.53 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:53:40 PM PDT 24
Peak memory 190860 kb
Host smart-2018a7f7-0e97-4e17-8922-e3b75cc6572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424248806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2424248806
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1866808185
Short name T255
Test name
Test status
Simulation time 887324402902 ps
CPU time 524.56 seconds
Started May 21 01:46:07 PM PDT 24
Finished May 21 01:54:52 PM PDT 24
Peak memory 190884 kb
Host smart-ae487c88-1bc5-40c7-9008-f69791f3462f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866808185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1866808185
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.1882325701
Short name T40
Test name
Test status
Simulation time 34201292898 ps
CPU time 349.65 seconds
Started May 21 01:46:20 PM PDT 24
Finished May 21 01:52:11 PM PDT 24
Peak memory 205440 kb
Host smart-aadcc223-a7d3-40b6-9544-9adf9de32cab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882325701 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.1882325701
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3537066988
Short name T86
Test name
Test status
Simulation time 45957598670 ps
CPU time 357.11 seconds
Started May 21 01:47:00 PM PDT 24
Finished May 21 01:53:01 PM PDT 24
Peak memory 191860 kb
Host smart-e749e291-5a2d-4afa-98c6-46d5dec7ba41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537066988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3537066988
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3440526795
Short name T426
Test name
Test status
Simulation time 144673684514 ps
CPU time 867.64 seconds
Started May 21 01:46:52 PM PDT 24
Finished May 21 02:01:24 PM PDT 24
Peak memory 190772 kb
Host smart-fd810a3f-b938-41d6-a204-c24657e56a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440526795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3440526795
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3921981852
Short name T21
Test name
Test status
Simulation time 36500989928 ps
CPU time 101.99 seconds
Started May 21 01:46:57 PM PDT 24
Finished May 21 01:48:43 PM PDT 24
Peak memory 182652 kb
Host smart-7862c2e1-6c3c-4980-a8e9-d5badb05308d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921981852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3921981852
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3433813730
Short name T231
Test name
Test status
Simulation time 52446543617 ps
CPU time 77.31 seconds
Started May 21 01:46:58 PM PDT 24
Finished May 21 01:48:19 PM PDT 24
Peak memory 190844 kb
Host smart-16a30a8d-4647-4026-84a7-10c7617e59c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433813730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3433813730
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1673235981
Short name T207
Test name
Test status
Simulation time 182201631688 ps
CPU time 90.56 seconds
Started May 21 01:47:02 PM PDT 24
Finished May 21 01:48:36 PM PDT 24
Peak memory 190844 kb
Host smart-82c097fe-c49d-40e8-bb35-bcac0d11278a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673235981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1673235981
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.980891443
Short name T176
Test name
Test status
Simulation time 79996137463 ps
CPU time 90.79 seconds
Started May 21 01:46:53 PM PDT 24
Finished May 21 01:48:27 PM PDT 24
Peak memory 190880 kb
Host smart-ea968780-d1a1-4a74-b945-301d21a20694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980891443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.980891443
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3409590199
Short name T424
Test name
Test status
Simulation time 64134261762 ps
CPU time 30.63 seconds
Started May 21 01:46:59 PM PDT 24
Finished May 21 01:47:34 PM PDT 24
Peak memory 182692 kb
Host smart-8a1b4d1a-3592-4806-a7d7-56b45f1a94e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409590199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3409590199
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3604354917
Short name T294
Test name
Test status
Simulation time 96778449785 ps
CPU time 156.77 seconds
Started May 21 01:46:54 PM PDT 24
Finished May 21 01:49:35 PM PDT 24
Peak memory 190772 kb
Host smart-0b4fb8b6-0bc0-4861-be58-26843553b090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604354917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3604354917
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1589393894
Short name T270
Test name
Test status
Simulation time 17791414737 ps
CPU time 29.29 seconds
Started May 21 01:46:24 PM PDT 24
Finished May 21 01:46:57 PM PDT 24
Peak memory 182688 kb
Host smart-0a69aebf-d94f-4ce8-a8be-4d4a7ebae3e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589393894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1589393894
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.274265648
Short name T61
Test name
Test status
Simulation time 48079748112 ps
CPU time 35.88 seconds
Started May 21 01:46:30 PM PDT 24
Finished May 21 01:47:11 PM PDT 24
Peak memory 182656 kb
Host smart-f189636f-e9a0-4908-af6a-fdcc7942a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274265648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.274265648
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2481844556
Short name T353
Test name
Test status
Simulation time 123102632348 ps
CPU time 65.49 seconds
Started May 21 01:46:18 PM PDT 24
Finished May 21 01:47:25 PM PDT 24
Peak memory 190864 kb
Host smart-c95999e3-32ff-429f-b2be-7da0332ee5e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481844556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2481844556
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1474274688
Short name T388
Test name
Test status
Simulation time 317806359 ps
CPU time 0.56 seconds
Started May 21 01:46:16 PM PDT 24
Finished May 21 01:46:18 PM PDT 24
Peak memory 182444 kb
Host smart-b105c42f-43ec-407c-9c98-bcf6898d3422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474274688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1474274688
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.969016394
Short name T213
Test name
Test status
Simulation time 161631827379 ps
CPU time 769.95 seconds
Started May 21 01:46:54 PM PDT 24
Finished May 21 01:59:49 PM PDT 24
Peak memory 191084 kb
Host smart-92760371-7813-44d3-9786-388804c884bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969016394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.969016394
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2187168672
Short name T8
Test name
Test status
Simulation time 49015765097 ps
CPU time 87.17 seconds
Started May 21 01:47:02 PM PDT 24
Finished May 21 01:48:32 PM PDT 24
Peak memory 182688 kb
Host smart-e03eda00-0aca-4026-900d-2a58d05d8135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187168672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2187168672
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3470756206
Short name T4
Test name
Test status
Simulation time 633778842464 ps
CPU time 794.89 seconds
Started May 21 01:47:03 PM PDT 24
Finished May 21 02:00:20 PM PDT 24
Peak memory 190792 kb
Host smart-0b2567b8-adbc-40b0-9e67-cb7c685e936e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470756206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3470756206
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.997340980
Short name T170
Test name
Test status
Simulation time 53752047148 ps
CPU time 244.62 seconds
Started May 21 01:46:57 PM PDT 24
Finished May 21 01:51:06 PM PDT 24
Peak memory 190764 kb
Host smart-9dcb4ff1-763b-482c-a59f-766a5ca290e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997340980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.997340980
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2302681665
Short name T149
Test name
Test status
Simulation time 773520662497 ps
CPU time 525.28 seconds
Started May 21 01:46:59 PM PDT 24
Finished May 21 01:55:48 PM PDT 24
Peak memory 190892 kb
Host smart-a3625863-894a-4865-b96e-aca3b548244d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302681665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2302681665
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2691651142
Short name T46
Test name
Test status
Simulation time 352197246724 ps
CPU time 869.38 seconds
Started May 21 01:46:57 PM PDT 24
Finished May 21 02:01:30 PM PDT 24
Peak memory 190852 kb
Host smart-a967f615-20fd-4f4f-9c9d-623b9a4ab512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691651142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2691651142
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2420344592
Short name T345
Test name
Test status
Simulation time 133697597915 ps
CPU time 286.77 seconds
Started May 21 01:46:59 PM PDT 24
Finished May 21 01:51:49 PM PDT 24
Peak memory 190760 kb
Host smart-6edd1680-e5b4-4e9a-8137-d5ba64239056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420344592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2420344592
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3773892506
Short name T206
Test name
Test status
Simulation time 48360336457 ps
CPU time 69.85 seconds
Started May 21 01:46:55 PM PDT 24
Finished May 21 01:48:09 PM PDT 24
Peak memory 190812 kb
Host smart-c657ea73-9f85-4a68-bffc-75a73339f421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773892506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3773892506
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.616592974
Short name T279
Test name
Test status
Simulation time 439173448853 ps
CPU time 289.55 seconds
Started May 21 01:46:59 PM PDT 24
Finished May 21 01:51:52 PM PDT 24
Peak memory 190888 kb
Host smart-d9335aa8-b940-4560-8071-42119afe6ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616592974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.616592974
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2149549359
Short name T267
Test name
Test status
Simulation time 3942950471 ps
CPU time 7.66 seconds
Started May 21 01:46:10 PM PDT 24
Finished May 21 01:46:18 PM PDT 24
Peak memory 182652 kb
Host smart-3975815a-419e-48e7-8cc7-3c1a3dfafef1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149549359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2149549359
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.4272272454
Short name T358
Test name
Test status
Simulation time 325373355123 ps
CPU time 203.2 seconds
Started May 21 01:46:23 PM PDT 24
Finished May 21 01:49:50 PM PDT 24
Peak memory 182584 kb
Host smart-e71c2c99-f233-408b-b256-ab35212422f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272272454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.4272272454
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3738070414
Short name T291
Test name
Test status
Simulation time 376525898332 ps
CPU time 180.23 seconds
Started May 21 01:46:12 PM PDT 24
Finished May 21 01:49:13 PM PDT 24
Peak memory 194260 kb
Host smart-f3e995a4-42f6-49bc-9db5-fbf8fe046088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738070414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3738070414
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2787343932
Short name T186
Test name
Test status
Simulation time 219882742521 ps
CPU time 899.14 seconds
Started May 21 01:46:27 PM PDT 24
Finished May 21 02:01:32 PM PDT 24
Peak memory 190832 kb
Host smart-f2e8824b-f11b-4fc6-80a8-354d2f09ba96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787343932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2787343932
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2365682997
Short name T181
Test name
Test status
Simulation time 591531904844 ps
CPU time 357.33 seconds
Started May 21 01:47:01 PM PDT 24
Finished May 21 01:53:02 PM PDT 24
Peak memory 194276 kb
Host smart-75fddc9d-9fa3-4f1a-b1b0-7d073df396f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365682997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2365682997
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3951437054
Short name T89
Test name
Test status
Simulation time 121425007751 ps
CPU time 1209.73 seconds
Started May 21 01:47:00 PM PDT 24
Finished May 21 02:07:13 PM PDT 24
Peak memory 190884 kb
Host smart-a6057712-d9f4-4fe8-96b0-a5b1e6f743c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951437054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3951437054
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.580667047
Short name T351
Test name
Test status
Simulation time 557629063779 ps
CPU time 3546.34 seconds
Started May 21 01:47:04 PM PDT 24
Finished May 21 02:46:13 PM PDT 24
Peak memory 190756 kb
Host smart-1cf80659-8a11-4d25-af06-db44f05dc0c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580667047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.580667047
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.881249246
Short name T308
Test name
Test status
Simulation time 29721704275 ps
CPU time 62.14 seconds
Started May 21 01:47:01 PM PDT 24
Finished May 21 01:48:07 PM PDT 24
Peak memory 182636 kb
Host smart-1e3d43a4-71bb-4a53-a376-377afc6f93e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881249246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.881249246
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.84424686
Short name T155
Test name
Test status
Simulation time 90384202068 ps
CPU time 202.28 seconds
Started May 21 01:46:58 PM PDT 24
Finished May 21 01:50:25 PM PDT 24
Peak memory 194356 kb
Host smart-53064e31-f946-4104-a29a-89c0edef6347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84424686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.84424686
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3895574175
Short name T239
Test name
Test status
Simulation time 151730330958 ps
CPU time 215.42 seconds
Started May 21 01:47:05 PM PDT 24
Finished May 21 01:50:42 PM PDT 24
Peak memory 190824 kb
Host smart-6b137edb-4889-45ec-aeb8-5cd483e4960b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895574175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3895574175
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2751389425
Short name T172
Test name
Test status
Simulation time 171341838647 ps
CPU time 297.51 seconds
Started May 21 01:47:03 PM PDT 24
Finished May 21 01:52:03 PM PDT 24
Peak memory 190824 kb
Host smart-9771d3f6-3d26-4df3-a20e-1bc94b74e0f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751389425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2751389425
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2109866009
Short name T431
Test name
Test status
Simulation time 109752186325 ps
CPU time 59.5 seconds
Started May 21 01:46:57 PM PDT 24
Finished May 21 01:48:01 PM PDT 24
Peak memory 182684 kb
Host smart-b7dd14d9-7207-4943-9c61-a3acd3044c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109866009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2109866009
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.385191859
Short name T88
Test name
Test status
Simulation time 58537668230 ps
CPU time 52.61 seconds
Started May 21 01:46:58 PM PDT 24
Finished May 21 01:47:54 PM PDT 24
Peak memory 182628 kb
Host smart-63d46c24-b344-4291-89c7-f329a00c1c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385191859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.385191859
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3338997651
Short name T447
Test name
Test status
Simulation time 16290096260 ps
CPU time 9.44 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:46:38 PM PDT 24
Peak memory 182636 kb
Host smart-1e43fb36-6ed4-43fd-81c0-819909b2daf2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338997651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3338997651
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_random.3370530020
Short name T47
Test name
Test status
Simulation time 165397503876 ps
CPU time 246.1 seconds
Started May 21 01:46:18 PM PDT 24
Finished May 21 01:50:25 PM PDT 24
Peak memory 190824 kb
Host smart-5cc088dd-cbaf-4540-86d5-36d77e3b98a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370530020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3370530020
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.525637811
Short name T416
Test name
Test status
Simulation time 180393916 ps
CPU time 1.87 seconds
Started May 21 01:46:25 PM PDT 24
Finished May 21 01:46:31 PM PDT 24
Peak memory 192868 kb
Host smart-3872933e-cce6-402a-af21-e9b26171a462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525637811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.525637811
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2082156560
Short name T364
Test name
Test status
Simulation time 56464275 ps
CPU time 0.66 seconds
Started May 21 01:46:15 PM PDT 24
Finished May 21 01:46:17 PM PDT 24
Peak memory 182420 kb
Host smart-b252b7fe-2a48-4411-9e2a-fe4acd2e151f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082156560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2082156560
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1319620372
Short name T13
Test name
Test status
Simulation time 87563873097 ps
CPU time 258.95 seconds
Started May 21 01:46:28 PM PDT 24
Finished May 21 01:50:53 PM PDT 24
Peak memory 205456 kb
Host smart-1e7910e3-2cba-43e7-82e5-6813b02be9b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319620372 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1319620372
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1238906474
Short name T116
Test name
Test status
Simulation time 306286991272 ps
CPU time 327.88 seconds
Started May 21 01:46:58 PM PDT 24
Finished May 21 01:52:30 PM PDT 24
Peak memory 190840 kb
Host smart-5b2f0dd9-4ba8-415d-bac4-40caef55bc62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238906474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1238906474
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3834938041
Short name T221
Test name
Test status
Simulation time 112579405420 ps
CPU time 257.64 seconds
Started May 21 01:47:04 PM PDT 24
Finished May 21 01:51:24 PM PDT 24
Peak memory 190844 kb
Host smart-07ba7965-3c1c-4111-b5c8-60897964ad6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834938041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3834938041
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3799450788
Short name T301
Test name
Test status
Simulation time 78201107232 ps
CPU time 186.66 seconds
Started May 21 01:47:02 PM PDT 24
Finished May 21 01:50:11 PM PDT 24
Peak memory 182672 kb
Host smart-ddf91bb7-e6a7-4f2f-aa9a-42eca2662bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799450788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3799450788
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1244182231
Short name T84
Test name
Test status
Simulation time 158230225070 ps
CPU time 17.3 seconds
Started May 21 01:47:01 PM PDT 24
Finished May 21 01:47:21 PM PDT 24
Peak memory 182612 kb
Host smart-49317e31-a4dc-41d7-97bb-e9955692796d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244182231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1244182231
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3040752484
Short name T182
Test name
Test status
Simulation time 573269457785 ps
CPU time 431.13 seconds
Started May 21 01:47:05 PM PDT 24
Finished May 21 01:54:18 PM PDT 24
Peak memory 193884 kb
Host smart-077547e2-50c5-4e43-83c9-2c095c82875d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040752484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3040752484
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1952325075
Short name T187
Test name
Test status
Simulation time 350209749340 ps
CPU time 160.48 seconds
Started May 21 01:47:05 PM PDT 24
Finished May 21 01:49:47 PM PDT 24
Peak memory 190824 kb
Host smart-2b146bea-f479-4cc6-952a-4a700dc20c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952325075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1952325075
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3206066001
Short name T138
Test name
Test status
Simulation time 312414715214 ps
CPU time 129.14 seconds
Started May 21 01:47:06 PM PDT 24
Finished May 21 01:49:17 PM PDT 24
Peak memory 194420 kb
Host smart-d10db337-1e90-4add-941b-ab596f02a311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206066001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3206066001
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1542514458
Short name T171
Test name
Test status
Simulation time 505413431054 ps
CPU time 347.01 seconds
Started May 21 01:47:01 PM PDT 24
Finished May 21 01:52:51 PM PDT 24
Peak memory 190820 kb
Host smart-9b383af8-6da6-4bc7-911f-edafbb247d2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542514458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1542514458
Directory /workspace/98.rv_timer_random/latest
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