Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 573
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4121317243 May 23 12:27:19 PM PDT 24 May 23 12:27:23 PM PDT 24 54040478 ps
T508 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2076344317 May 23 12:27:16 PM PDT 24 May 23 12:27:20 PM PDT 24 14069521 ps
T509 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3941428179 May 23 12:27:18 PM PDT 24 May 23 12:27:23 PM PDT 24 31742627 ps
T510 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2054988525 May 23 12:27:02 PM PDT 24 May 23 12:27:09 PM PDT 24 203592362 ps
T511 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1502446055 May 23 12:27:35 PM PDT 24 May 23 12:27:39 PM PDT 24 13254787 ps
T512 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1424743498 May 23 12:27:23 PM PDT 24 May 23 12:27:26 PM PDT 24 25496456 ps
T118 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2591586824 May 23 12:27:17 PM PDT 24 May 23 12:27:21 PM PDT 24 48355654 ps
T513 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1302504168 May 23 12:27:16 PM PDT 24 May 23 12:27:20 PM PDT 24 15026181 ps
T514 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2182640543 May 23 12:27:24 PM PDT 24 May 23 12:27:27 PM PDT 24 19628394 ps
T515 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1085998653 May 23 12:27:20 PM PDT 24 May 23 12:27:26 PM PDT 24 155963905 ps
T516 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.468025516 May 23 12:27:15 PM PDT 24 May 23 12:27:19 PM PDT 24 86146513 ps
T115 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3381533965 May 23 12:27:04 PM PDT 24 May 23 12:27:10 PM PDT 24 82261907 ps
T94 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3960287036 May 23 12:27:12 PM PDT 24 May 23 12:27:19 PM PDT 24 91568880 ps
T517 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.566316772 May 23 12:27:28 PM PDT 24 May 23 12:27:31 PM PDT 24 43636974 ps
T518 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1818741846 May 23 12:27:03 PM PDT 24 May 23 12:27:09 PM PDT 24 48877487 ps
T519 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1390426625 May 23 12:27:18 PM PDT 24 May 23 12:27:23 PM PDT 24 22771718 ps
T520 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.696880676 May 23 12:27:15 PM PDT 24 May 23 12:27:19 PM PDT 24 50119905 ps
T521 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4104236524 May 23 12:27:28 PM PDT 24 May 23 12:27:29 PM PDT 24 33807157 ps
T95 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.342776229 May 23 12:27:10 PM PDT 24 May 23 12:27:15 PM PDT 24 19570841 ps
T522 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1225583187 May 23 12:27:06 PM PDT 24 May 23 12:27:12 PM PDT 24 428781155 ps
T523 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.49096174 May 23 12:27:10 PM PDT 24 May 23 12:27:15 PM PDT 24 324215133 ps
T524 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2049757006 May 23 12:27:18 PM PDT 24 May 23 12:27:24 PM PDT 24 331280776 ps
T525 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2016167977 May 23 12:27:15 PM PDT 24 May 23 12:27:19 PM PDT 24 57126288 ps
T526 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3602765048 May 23 12:27:17 PM PDT 24 May 23 12:27:24 PM PDT 24 427420672 ps
T527 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.674958992 May 23 12:27:20 PM PDT 24 May 23 12:27:25 PM PDT 24 77374347 ps
T528 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1304940331 May 23 12:27:39 PM PDT 24 May 23 12:27:47 PM PDT 24 15190992 ps
T529 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1162439961 May 23 12:27:38 PM PDT 24 May 23 12:27:43 PM PDT 24 427099189 ps
T96 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2944159875 May 23 12:27:03 PM PDT 24 May 23 12:27:09 PM PDT 24 66235637 ps
T530 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3215822500 May 23 12:27:37 PM PDT 24 May 23 12:27:42 PM PDT 24 53085580 ps
T531 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1835944140 May 23 12:27:35 PM PDT 24 May 23 12:27:40 PM PDT 24 27647970 ps
T532 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1266092214 May 23 12:27:29 PM PDT 24 May 23 12:27:31 PM PDT 24 45059923 ps
T533 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.175114174 May 23 12:27:13 PM PDT 24 May 23 12:27:17 PM PDT 24 40046177 ps
T534 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4257352540 May 23 12:27:03 PM PDT 24 May 23 12:27:09 PM PDT 24 56710822 ps
T535 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3055053326 May 23 12:27:14 PM PDT 24 May 23 12:27:17 PM PDT 24 26248584 ps
T536 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4207892866 May 23 12:27:17 PM PDT 24 May 23 12:27:20 PM PDT 24 35046135 ps
T537 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1701045159 May 23 12:27:16 PM PDT 24 May 23 12:27:20 PM PDT 24 32693990 ps
T538 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.862608955 May 23 12:27:42 PM PDT 24 May 23 12:27:45 PM PDT 24 64740709 ps
T539 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.411129678 May 23 12:27:21 PM PDT 24 May 23 12:27:25 PM PDT 24 16733127 ps
T540 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1976181159 May 23 12:27:42 PM PDT 24 May 23 12:27:45 PM PDT 24 42271313 ps
T541 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1994361645 May 23 12:27:32 PM PDT 24 May 23 12:27:35 PM PDT 24 43916794 ps
T542 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.675744293 May 23 12:27:35 PM PDT 24 May 23 12:27:40 PM PDT 24 174389250 ps
T543 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3501804803 May 23 12:27:16 PM PDT 24 May 23 12:27:22 PM PDT 24 51562705 ps
T544 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2328327471 May 23 12:27:31 PM PDT 24 May 23 12:27:33 PM PDT 24 134904520 ps
T545 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1538408231 May 23 12:27:16 PM PDT 24 May 23 12:27:20 PM PDT 24 14796771 ps
T546 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3240806650 May 23 12:27:12 PM PDT 24 May 23 12:27:17 PM PDT 24 43329702 ps
T547 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4026678335 May 23 12:27:26 PM PDT 24 May 23 12:27:28 PM PDT 24 15220785 ps
T548 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1656735066 May 23 12:27:31 PM PDT 24 May 23 12:27:34 PM PDT 24 89171858 ps
T549 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2256647035 May 23 12:27:02 PM PDT 24 May 23 12:27:06 PM PDT 24 46728325 ps
T550 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3019896732 May 23 12:27:16 PM PDT 24 May 23 12:27:20 PM PDT 24 32025928 ps
T97 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3503393718 May 23 12:27:09 PM PDT 24 May 23 12:27:14 PM PDT 24 17151117 ps
T551 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2618627413 May 23 12:27:49 PM PDT 24 May 23 12:27:51 PM PDT 24 15859075 ps
T552 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.338406417 May 23 12:27:10 PM PDT 24 May 23 12:27:15 PM PDT 24 16837159 ps
T553 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2953205746 May 23 12:27:31 PM PDT 24 May 23 12:27:35 PM PDT 24 140187269 ps
T554 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1173947065 May 23 12:27:26 PM PDT 24 May 23 12:27:29 PM PDT 24 220528742 ps
T555 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1546419145 May 23 12:27:22 PM PDT 24 May 23 12:27:27 PM PDT 24 415722589 ps
T556 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2243785177 May 23 12:27:15 PM PDT 24 May 23 12:27:20 PM PDT 24 36176749 ps
T557 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3023417598 May 23 12:27:17 PM PDT 24 May 23 12:27:22 PM PDT 24 86423932 ps
T558 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1092990577 May 23 12:27:17 PM PDT 24 May 23 12:27:23 PM PDT 24 52718467 ps
T559 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2389480483 May 23 12:27:16 PM PDT 24 May 23 12:27:20 PM PDT 24 34718949 ps
T560 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2701746125 May 23 12:27:41 PM PDT 24 May 23 12:27:44 PM PDT 24 43167538 ps
T561 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3701768406 May 23 12:27:16 PM PDT 24 May 23 12:27:21 PM PDT 24 70489253 ps
T562 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2268580793 May 23 12:27:25 PM PDT 24 May 23 12:27:27 PM PDT 24 15850822 ps
T563 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2530818686 May 23 12:27:16 PM PDT 24 May 23 12:27:20 PM PDT 24 49933580 ps
T564 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.60564494 May 23 12:27:32 PM PDT 24 May 23 12:27:36 PM PDT 24 60067669 ps
T565 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1523825545 May 23 12:27:27 PM PDT 24 May 23 12:27:29 PM PDT 24 20165033 ps
T566 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3932304888 May 23 12:27:15 PM PDT 24 May 23 12:27:19 PM PDT 24 147791233 ps
T567 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3041518096 May 23 12:27:03 PM PDT 24 May 23 12:27:10 PM PDT 24 490958286 ps
T568 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1329294751 May 23 12:27:09 PM PDT 24 May 23 12:27:14 PM PDT 24 32998570 ps
T569 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3094454536 May 23 12:27:44 PM PDT 24 May 23 12:27:46 PM PDT 24 17202203 ps
T570 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.616585506 May 23 12:27:14 PM PDT 24 May 23 12:27:18 PM PDT 24 23732390 ps
T571 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.412420734 May 23 12:27:22 PM PDT 24 May 23 12:27:26 PM PDT 24 41230333 ps
T572 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2854289024 May 23 12:27:16 PM PDT 24 May 23 12:27:21 PM PDT 24 45202181 ps
T573 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1763807250 May 23 12:27:21 PM PDT 24 May 23 12:27:27 PM PDT 24 16900847 ps

Test location /workspace/coverage/default/48.rv_timer_stress_all.87554991
Short name T7
Test name
Test status
Simulation time 847079811046 ps
CPU time 892.43 seconds
Started May 23 12:28:16 PM PDT 24
Finished May 23 12:43:09 PM PDT 24
Peak memory 190708 kb
Host smart-4c4355b7-ac3b-4148-a9eb-02f51623e898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87554991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.87554991
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.1148345136
Short name T36
Test name
Test status
Simulation time 132896129818 ps
CPU time 720.55 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:39:53 PM PDT 24
Peak memory 208128 kb
Host smart-836dd4f1-5b09-4f48-a568-e943c66261fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148345136 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.1148345136
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2714111749
Short name T158
Test name
Test status
Simulation time 785709743813 ps
CPU time 2188.29 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 01:04:31 PM PDT 24
Peak memory 190656 kb
Host smart-d0633be9-81a1-4d16-9e21-279a940f6e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714111749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2714111749
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3630814512
Short name T29
Test name
Test status
Simulation time 433661177 ps
CPU time 1.23 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:27 PM PDT 24
Peak memory 195196 kb
Host smart-a8be2367-3c70-4847-8c16-c8eeb1c26729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630814512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3630814512
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2469823199
Short name T120
Test name
Test status
Simulation time 643158998732 ps
CPU time 2262.91 seconds
Started May 23 12:28:00 PM PDT 24
Finished May 23 01:05:46 PM PDT 24
Peak memory 190664 kb
Host smart-62352fd2-9cf4-4a09-bef9-233cf7f7f327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469823199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2469823199
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.309896780
Short name T151
Test name
Test status
Simulation time 8360517554183 ps
CPU time 4402.63 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 01:41:19 PM PDT 24
Peak memory 190652 kb
Host smart-5de331e4-5617-463d-996a-3b6d69668406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309896780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
309896780
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1551060157
Short name T174
Test name
Test status
Simulation time 3022856646347 ps
CPU time 1601.74 seconds
Started May 23 12:28:05 PM PDT 24
Finished May 23 12:54:51 PM PDT 24
Peak memory 190704 kb
Host smart-09191585-abfe-4b0d-b064-1c028b000dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551060157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1551060157
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1088240174
Short name T132
Test name
Test status
Simulation time 456851701452 ps
CPU time 5266 seconds
Started May 23 12:28:17 PM PDT 24
Finished May 23 01:56:05 PM PDT 24
Peak memory 195708 kb
Host smart-d33efdee-fc06-4654-a7ce-4b40a2e34fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088240174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1088240174
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.4279860068
Short name T8
Test name
Test status
Simulation time 279062219441 ps
CPU time 1100.33 seconds
Started May 23 12:28:22 PM PDT 24
Finished May 23 12:46:45 PM PDT 24
Peak memory 195284 kb
Host smart-9813de6e-6d3e-4ad7-9bbf-1142d5940eb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279860068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.4279860068
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.198171378
Short name T62
Test name
Test status
Simulation time 1876473101524 ps
CPU time 1007.58 seconds
Started May 23 12:28:24 PM PDT 24
Finished May 23 12:45:15 PM PDT 24
Peak memory 190672 kb
Host smart-e85c8e52-e396-4e2b-a029-1c648f3a78cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198171378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
198171378
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3667191816
Short name T156
Test name
Test status
Simulation time 606195898197 ps
CPU time 4627.23 seconds
Started May 23 12:27:35 PM PDT 24
Finished May 23 01:44:47 PM PDT 24
Peak memory 190668 kb
Host smart-3613385d-e76b-4e4e-863d-1aa388018620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667191816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3667191816
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3717025090
Short name T153
Test name
Test status
Simulation time 1453458060135 ps
CPU time 1995.79 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 01:01:16 PM PDT 24
Peak memory 194888 kb
Host smart-dd31bb17-75dc-49da-8eac-cf2c34af9183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717025090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3717025090
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.274748961
Short name T48
Test name
Test status
Simulation time 877629025230 ps
CPU time 1196.24 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:47:50 PM PDT 24
Peak memory 195164 kb
Host smart-3a0df1fd-b3c3-468e-b015-747585c10611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274748961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.274748961
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.66835044
Short name T163
Test name
Test status
Simulation time 723737389103 ps
CPU time 820.74 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:41:47 PM PDT 24
Peak memory 190660 kb
Host smart-7d474700-7b5f-4b0f-9d76-d9a175bda397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66835044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.66835044
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1189140619
Short name T16
Test name
Test status
Simulation time 209259186 ps
CPU time 0.96 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:27:35 PM PDT 24
Peak memory 214012 kb
Host smart-b4841917-4194-4845-a055-465b0d557f5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189140619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1189140619
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4191805550
Short name T55
Test name
Test status
Simulation time 15804507 ps
CPU time 0.62 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:21 PM PDT 24
Peak memory 182608 kb
Host smart-0401509d-ee73-4fde-84cc-a1129a7b98c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191805550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4191805550
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.4118234515
Short name T166
Test name
Test status
Simulation time 1011234550408 ps
CPU time 1395.27 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:51:11 PM PDT 24
Peak memory 190660 kb
Host smart-f0e358c2-69bd-43c1-9279-a6892ed21259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118234515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.4118234515
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.822311134
Short name T167
Test name
Test status
Simulation time 798905562796 ps
CPU time 657.69 seconds
Started May 23 12:28:08 PM PDT 24
Finished May 23 12:39:07 PM PDT 24
Peak memory 190688 kb
Host smart-3a801b88-2906-446a-9c2c-ef78ccc6fb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822311134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
822311134
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.395549773
Short name T140
Test name
Test status
Simulation time 989525812075 ps
CPU time 482.07 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:35:58 PM PDT 24
Peak memory 182484 kb
Host smart-1eaedbff-57f9-45ca-a999-4eff0b596c55
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395549773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.395549773
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/181.rv_timer_random.3278855163
Short name T25
Test name
Test status
Simulation time 962298658902 ps
CPU time 931.78 seconds
Started May 23 12:28:37 PM PDT 24
Finished May 23 12:44:11 PM PDT 24
Peak memory 190660 kb
Host smart-06222d99-0240-4410-b3f4-24fc7bee78f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278855163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3278855163
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.4252695982
Short name T217
Test name
Test status
Simulation time 268023977230 ps
CPU time 1190.18 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:47:45 PM PDT 24
Peak memory 190464 kb
Host smart-595d7443-8bba-47fc-9fd4-9ba85893c786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252695982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.4252695982
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/54.rv_timer_random.3496584298
Short name T199
Test name
Test status
Simulation time 952940573070 ps
CPU time 479.63 seconds
Started May 23 12:28:14 PM PDT 24
Finished May 23 12:36:14 PM PDT 24
Peak memory 190680 kb
Host smart-49b87d85-7731-4a02-b711-28d97261596a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496584298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3496584298
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1451312932
Short name T233
Test name
Test status
Simulation time 307912051515 ps
CPU time 571.26 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:37:26 PM PDT 24
Peak memory 190660 kb
Host smart-f0de64af-312d-41db-859c-fc465e6e45c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451312932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1451312932
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2002053932
Short name T323
Test name
Test status
Simulation time 256232842028 ps
CPU time 1703.8 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:56:29 PM PDT 24
Peak memory 190704 kb
Host smart-f4176021-c1af-4017-8fdf-cfd581a24067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002053932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2002053932
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random.221590179
Short name T45
Test name
Test status
Simulation time 303675023850 ps
CPU time 408.99 seconds
Started May 23 12:27:44 PM PDT 24
Finished May 23 12:34:35 PM PDT 24
Peak memory 190644 kb
Host smart-55f5550f-2848-46de-8bfd-7e57be57679b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221590179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.221590179
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3898195544
Short name T232
Test name
Test status
Simulation time 187729978070 ps
CPU time 169.81 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:30:46 PM PDT 24
Peak memory 194820 kb
Host smart-7e1638ca-5b33-471a-a5fe-21fd80012f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898195544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3898195544
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2210559001
Short name T247
Test name
Test status
Simulation time 357439447116 ps
CPU time 1418.03 seconds
Started May 23 12:27:31 PM PDT 24
Finished May 23 12:51:12 PM PDT 24
Peak memory 190656 kb
Host smart-56d6cbda-6be7-4d5c-8f31-87dc3d41b5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210559001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2210559001
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2874962542
Short name T196
Test name
Test status
Simulation time 999701562380 ps
CPU time 1025.61 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:45:13 PM PDT 24
Peak memory 190824 kb
Host smart-a8e45a8f-9a74-4523-b3df-87a78a285ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874962542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2874962542
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.3634550919
Short name T67
Test name
Test status
Simulation time 572917278320 ps
CPU time 3191.18 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 01:21:49 PM PDT 24
Peak memory 190660 kb
Host smart-2ab126b8-17ab-4437-8cc9-cae5f1bb927a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634550919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3634550919
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.919570218
Short name T186
Test name
Test status
Simulation time 133861958069 ps
CPU time 736.52 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:40:52 PM PDT 24
Peak memory 190668 kb
Host smart-4f968d7b-25ef-487b-8a73-56d2cab37e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919570218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.919570218
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3270434971
Short name T200
Test name
Test status
Simulation time 341977808937 ps
CPU time 278.9 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:32:44 PM PDT 24
Peak memory 190548 kb
Host smart-5dda1f2f-7d77-4031-bcf1-44405fafbad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270434971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3270434971
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2872483588
Short name T178
Test name
Test status
Simulation time 340041336955 ps
CPU time 895.49 seconds
Started May 23 12:28:10 PM PDT 24
Finished May 23 12:43:07 PM PDT 24
Peak memory 190696 kb
Host smart-badf2eb6-35fe-49fb-bdbe-7700313c4bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872483588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2872483588
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3504503046
Short name T136
Test name
Test status
Simulation time 382476993399 ps
CPU time 192.91 seconds
Started May 23 12:28:14 PM PDT 24
Finished May 23 12:31:28 PM PDT 24
Peak memory 190660 kb
Host smart-b0f69129-c4d2-4297-ad0b-e53bdf3f2ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504503046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3504503046
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1484342974
Short name T331
Test name
Test status
Simulation time 1939193324072 ps
CPU time 370.81 seconds
Started May 23 12:27:56 PM PDT 24
Finished May 23 12:34:15 PM PDT 24
Peak memory 190676 kb
Host smart-68c173dc-24b4-4439-b92d-674debf8c507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484342974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1484342974
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1904052218
Short name T351
Test name
Test status
Simulation time 1622397981737 ps
CPU time 1111.27 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:46:23 PM PDT 24
Peak memory 190628 kb
Host smart-1a025ab0-781d-4c9d-82c5-37eb1f041577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904052218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1904052218
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2884470060
Short name T325
Test name
Test status
Simulation time 873730986270 ps
CPU time 1246.57 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:48:52 PM PDT 24
Peak memory 190684 kb
Host smart-34d2d8c0-7062-46f2-907b-d6785d626846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884470060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2884470060
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/197.rv_timer_random.3341662117
Short name T276
Test name
Test status
Simulation time 384044338636 ps
CPU time 301.67 seconds
Started May 23 12:28:38 PM PDT 24
Finished May 23 12:33:41 PM PDT 24
Peak memory 193208 kb
Host smart-474c83e0-f000-4c29-a74e-c928ddfff0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341662117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3341662117
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3640065252
Short name T61
Test name
Test status
Simulation time 725007075695 ps
CPU time 441.05 seconds
Started May 23 12:27:47 PM PDT 24
Finished May 23 12:35:10 PM PDT 24
Peak memory 190644 kb
Host smart-fcd30eab-9157-4b1e-9c9b-2799258bf47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640065252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3640065252
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.1743088932
Short name T239
Test name
Test status
Simulation time 604564181499 ps
CPU time 904.74 seconds
Started May 23 12:27:56 PM PDT 24
Finished May 23 12:43:03 PM PDT 24
Peak memory 190676 kb
Host smart-d6d5b00f-acb9-4470-978f-747de5a21cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743088932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1743088932
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.105726003
Short name T109
Test name
Test status
Simulation time 561971829725 ps
CPU time 345.38 seconds
Started May 23 12:28:41 PM PDT 24
Finished May 23 12:34:29 PM PDT 24
Peak memory 190648 kb
Host smart-7ae13c25-d488-48bb-afa9-8acd933d0fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105726003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.105726003
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.976821135
Short name T133
Test name
Test status
Simulation time 443685364544 ps
CPU time 252.95 seconds
Started May 23 12:28:06 PM PDT 24
Finished May 23 12:32:21 PM PDT 24
Peak memory 190724 kb
Host smart-bcbeed6b-6723-4077-87b0-586b07cffcff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976821135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.976821135
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3558934491
Short name T246
Test name
Test status
Simulation time 321523572737 ps
CPU time 524.48 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:36:50 PM PDT 24
Peak memory 182452 kb
Host smart-255e29e3-5242-46de-af2d-6b6497902294
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558934491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3558934491
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.529060435
Short name T248
Test name
Test status
Simulation time 299691229845 ps
CPU time 288.1 seconds
Started May 23 12:28:25 PM PDT 24
Finished May 23 12:33:16 PM PDT 24
Peak memory 190676 kb
Host smart-493c889c-2094-4cf9-b989-9a8b8aa3d217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529060435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.529060435
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2297960602
Short name T249
Test name
Test status
Simulation time 240712832741 ps
CPU time 342.04 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:33:45 PM PDT 24
Peak memory 190664 kb
Host smart-aa2a62f4-9a49-4034-a1e5-fa02f8c87d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297960602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2297960602
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/117.rv_timer_random.2249764870
Short name T207
Test name
Test status
Simulation time 637436218700 ps
CPU time 374.36 seconds
Started May 23 12:28:05 PM PDT 24
Finished May 23 12:34:25 PM PDT 24
Peak memory 190624 kb
Host smart-7ac7b38c-728e-4c44-bfd5-3b162ad1e1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249764870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2249764870
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.4230653625
Short name T278
Test name
Test status
Simulation time 352589832596 ps
CPU time 576.39 seconds
Started May 23 12:28:40 PM PDT 24
Finished May 23 12:38:18 PM PDT 24
Peak memory 190688 kb
Host smart-cbdd1c47-8d18-4170-a063-d073851d3ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230653625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.4230653625
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2361255697
Short name T313
Test name
Test status
Simulation time 61842328842 ps
CPU time 282.06 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:33:23 PM PDT 24
Peak memory 190660 kb
Host smart-93745de4-ac92-4986-8a8d-e80a2b86c00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361255697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2361255697
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2217982561
Short name T42
Test name
Test status
Simulation time 254230877746 ps
CPU time 312.72 seconds
Started May 23 12:28:36 PM PDT 24
Finished May 23 12:33:51 PM PDT 24
Peak memory 190648 kb
Host smart-790914b7-7b69-4b19-ba63-b7c0eb64df2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217982561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2217982561
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.1698895646
Short name T219
Test name
Test status
Simulation time 376685672942 ps
CPU time 315.57 seconds
Started May 23 12:28:43 PM PDT 24
Finished May 23 12:33:59 PM PDT 24
Peak memory 190696 kb
Host smart-cc663f26-7bf8-48c1-a796-1af80d74f0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698895646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1698895646
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3582638004
Short name T281
Test name
Test status
Simulation time 168473045002 ps
CPU time 418.48 seconds
Started May 23 12:28:36 PM PDT 24
Finished May 23 12:35:38 PM PDT 24
Peak memory 192676 kb
Host smart-52a5e5b9-d68c-4fee-84a7-6670a87beed4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582638004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3582638004
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2724346734
Short name T144
Test name
Test status
Simulation time 521452870525 ps
CPU time 271.74 seconds
Started May 23 12:28:37 PM PDT 24
Finished May 23 12:33:11 PM PDT 24
Peak memory 190620 kb
Host smart-543c99a8-24ba-4a4e-8269-a636e7b9ff69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724346734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2724346734
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.2229104891
Short name T2
Test name
Test status
Simulation time 86198067512 ps
CPU time 355.24 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:33:56 PM PDT 24
Peak memory 190672 kb
Host smart-673e279a-84f6-46eb-9f5b-e78d39272e83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229104891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2229104891
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random.771341382
Short name T291
Test name
Test status
Simulation time 274563327614 ps
CPU time 514.47 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:37:16 PM PDT 24
Peak memory 190684 kb
Host smart-6fb0b446-a45e-4207-8ffc-c91db94d2adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771341382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.771341382
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1967902445
Short name T157
Test name
Test status
Simulation time 1396844479178 ps
CPU time 453.66 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:36:06 PM PDT 24
Peak memory 190688 kb
Host smart-7a5938d1-83fa-49b9-af87-8c69d8f95315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967902445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1967902445
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1472427612
Short name T172
Test name
Test status
Simulation time 83187036148 ps
CPU time 305.96 seconds
Started May 23 12:28:38 PM PDT 24
Finished May 23 12:33:46 PM PDT 24
Peak memory 190688 kb
Host smart-3b6387b2-5c36-423d-ad08-061677e6e867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472427612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1472427612
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.1942334930
Short name T257
Test name
Test status
Simulation time 383628067756 ps
CPU time 859.87 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:42:20 PM PDT 24
Peak memory 190188 kb
Host smart-a9d1370d-2523-4b2f-a28b-d507d2f8c718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942334930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1942334930
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.333227450
Short name T89
Test name
Test status
Simulation time 85784800 ps
CPU time 0.63 seconds
Started May 23 12:27:12 PM PDT 24
Finished May 23 12:27:16 PM PDT 24
Peak memory 182276 kb
Host smart-0cbf89b4-0d5a-4a60-81ff-1df49172e926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333227450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.333227450
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/10.rv_timer_random.192419346
Short name T290
Test name
Test status
Simulation time 181116262114 ps
CPU time 129.8 seconds
Started May 23 12:27:49 PM PDT 24
Finished May 23 12:30:00 PM PDT 24
Peak memory 190648 kb
Host smart-e5363a72-9c21-40c4-bc32-11946b4481e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192419346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.192419346
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1179772302
Short name T227
Test name
Test status
Simulation time 186471324053 ps
CPU time 598.3 seconds
Started May 23 12:28:17 PM PDT 24
Finished May 23 12:38:16 PM PDT 24
Peak memory 190660 kb
Host smart-4c15daef-6bbc-44f6-baa6-fb951cc021e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179772302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1179772302
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.714582746
Short name T289
Test name
Test status
Simulation time 70836590578 ps
CPU time 116.53 seconds
Started May 23 12:28:41 PM PDT 24
Finished May 23 12:30:39 PM PDT 24
Peak memory 190696 kb
Host smart-a02de5d5-d927-412c-9bca-c598fb572298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714582746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.714582746
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3843056220
Short name T270
Test name
Test status
Simulation time 81125885948 ps
CPU time 455.16 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:35:41 PM PDT 24
Peak memory 182608 kb
Host smart-d3942d67-26b7-4ee4-8dce-12a0ff6e687b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843056220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3843056220
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/146.rv_timer_random.4170199325
Short name T311
Test name
Test status
Simulation time 41972374919 ps
CPU time 59.29 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:29:33 PM PDT 24
Peak memory 190628 kb
Host smart-78c89800-5e27-4459-b1ec-08b24d5219fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170199325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4170199325
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4216791424
Short name T242
Test name
Test status
Simulation time 936962910558 ps
CPU time 918.42 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:43:19 PM PDT 24
Peak memory 182500 kb
Host smart-41522f62-f505-4f42-baf9-1b254c4776f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216791424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.4216791424
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_random.274299163
Short name T263
Test name
Test status
Simulation time 689926445596 ps
CPU time 802.37 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:41:15 PM PDT 24
Peak memory 190636 kb
Host smart-8f18cc7d-7840-4747-b58b-e588950d88df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274299163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.274299163
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3333783376
Short name T123
Test name
Test status
Simulation time 434112562083 ps
CPU time 377.68 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:34:58 PM PDT 24
Peak memory 190708 kb
Host smart-6a43c7c5-6aec-44e8-b902-bc18dc60bfdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333783376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3333783376
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2397854428
Short name T126
Test name
Test status
Simulation time 171649073779 ps
CPU time 300.32 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:33:06 PM PDT 24
Peak memory 182500 kb
Host smart-2ec9c601-f9bf-4b7a-8c29-fa721b7c50ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397854428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2397854428
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/188.rv_timer_random.1966118907
Short name T449
Test name
Test status
Simulation time 506074639383 ps
CPU time 331 seconds
Started May 23 12:28:48 PM PDT 24
Finished May 23 12:34:20 PM PDT 24
Peak memory 190728 kb
Host smart-1a7a4bcd-8d6b-4312-882e-91ab4228537d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966118907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1966118907
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.3098797882
Short name T259
Test name
Test status
Simulation time 443780126577 ps
CPU time 572.71 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:37:39 PM PDT 24
Peak memory 190600 kb
Host smart-b8f2b5b1-e4c6-406a-8b74-010253b0a831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098797882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3098797882
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2439060583
Short name T273
Test name
Test status
Simulation time 39305078749 ps
CPU time 64.29 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:29:00 PM PDT 24
Peak memory 182520 kb
Host smart-a137e0e3-0e3a-4c01-b081-45525a740c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439060583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2439060583
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.322889860
Short name T223
Test name
Test status
Simulation time 477894876857 ps
CPU time 802.27 seconds
Started May 23 12:27:47 PM PDT 24
Finished May 23 12:41:11 PM PDT 24
Peak memory 182536 kb
Host smart-05d5d869-8816-47e2-8cca-eed03fef272b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322889860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.322889860
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3940615489
Short name T64
Test name
Test status
Simulation time 4335517145553 ps
CPU time 1311.73 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:49:54 PM PDT 24
Peak memory 190828 kb
Host smart-9f6edd69-14e4-445c-a08b-8f1ce067da0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940615489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3940615489
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2942721368
Short name T80
Test name
Test status
Simulation time 263742869467 ps
CPU time 160.64 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:30:45 PM PDT 24
Peak memory 190676 kb
Host smart-70610e5c-bde9-4087-b74b-a3694e17d431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942721368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2942721368
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.4256251065
Short name T419
Test name
Test status
Simulation time 19711356891 ps
CPU time 39.38 seconds
Started May 23 12:28:19 PM PDT 24
Finished May 23 12:29:00 PM PDT 24
Peak memory 190668 kb
Host smart-ea072dcc-8082-444a-9871-44538d0f90a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256251065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4256251065
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3006966721
Short name T114
Test name
Test status
Simulation time 765893626 ps
CPU time 1.09 seconds
Started May 23 12:27:12 PM PDT 24
Finished May 23 12:27:17 PM PDT 24
Peak memory 194468 kb
Host smart-930cff1c-cb8c-4417-a5ea-1da2700ff1c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006966721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3006966721
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.2687916118
Short name T164
Test name
Test status
Simulation time 226948617236 ps
CPU time 268.25 seconds
Started May 23 12:27:47 PM PDT 24
Finished May 23 12:32:17 PM PDT 24
Peak memory 190680 kb
Host smart-5e871476-e214-41a7-b851-8d8dedd0f39a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687916118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2687916118
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.550382303
Short name T360
Test name
Test status
Simulation time 331450221235 ps
CPU time 115.12 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:29:30 PM PDT 24
Peak memory 190688 kb
Host smart-9129831b-1f1e-4b6a-92ae-dab21b3a25a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550382303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.550382303
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3919313755
Short name T155
Test name
Test status
Simulation time 59467013293 ps
CPU time 256.73 seconds
Started May 23 12:27:35 PM PDT 24
Finished May 23 12:31:56 PM PDT 24
Peak memory 190684 kb
Host smart-c4f8fc82-76cf-48be-9689-51270bf15d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919313755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3919313755
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/103.rv_timer_random.306431564
Short name T189
Test name
Test status
Simulation time 529316883487 ps
CPU time 845.64 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:42:37 PM PDT 24
Peak memory 190712 kb
Host smart-48992260-cf79-4904-a692-ef359b51bd90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306431564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.306431564
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.744705653
Short name T286
Test name
Test status
Simulation time 407224126450 ps
CPU time 282.64 seconds
Started May 23 12:28:05 PM PDT 24
Finished May 23 12:32:50 PM PDT 24
Peak memory 190652 kb
Host smart-ed849518-ef8b-4dd5-b59d-5ede7c00a49a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744705653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.744705653
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3873005840
Short name T49
Test name
Test status
Simulation time 45240999296 ps
CPU time 24.23 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:28:29 PM PDT 24
Peak memory 182488 kb
Host smart-e3f394b1-534c-4806-bda6-3bbbf25d138a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873005840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3873005840
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/114.rv_timer_random.2351361353
Short name T338
Test name
Test status
Simulation time 515193188532 ps
CPU time 240.35 seconds
Started May 23 12:28:19 PM PDT 24
Finished May 23 12:32:21 PM PDT 24
Peak memory 194280 kb
Host smart-d348a79b-86bd-40b6-b7c6-e95ae2f76716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351361353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2351361353
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.247411999
Short name T79
Test name
Test status
Simulation time 419220881932 ps
CPU time 1716.9 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:57:13 PM PDT 24
Peak memory 190676 kb
Host smart-8009c367-788d-4f86-b8ac-9db4bcc88d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247411999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.247411999
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2609776538
Short name T82
Test name
Test status
Simulation time 220171029680 ps
CPU time 114.36 seconds
Started May 23 12:28:35 PM PDT 24
Finished May 23 12:30:32 PM PDT 24
Peak memory 190628 kb
Host smart-6247d213-072c-410f-ad91-e9a7b9949484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609776538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2609776538
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3225550622
Short name T348
Test name
Test status
Simulation time 87055031334 ps
CPU time 377.63 seconds
Started May 23 12:28:28 PM PDT 24
Finished May 23 12:34:48 PM PDT 24
Peak memory 182552 kb
Host smart-be7187a0-2abe-4756-a83b-cd55f8be9f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225550622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3225550622
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2526873799
Short name T149
Test name
Test status
Simulation time 317879813756 ps
CPU time 297.78 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:33:35 PM PDT 24
Peak memory 190828 kb
Host smart-75ea9d64-b6a8-44e7-8d8f-7b154e70ef5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526873799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2526873799
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.4115087988
Short name T262
Test name
Test status
Simulation time 3095594550 ps
CPU time 1.78 seconds
Started May 23 12:28:31 PM PDT 24
Finished May 23 12:28:34 PM PDT 24
Peak memory 182328 kb
Host smart-79dc4062-2916-45cd-af96-58abe7988e03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115087988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.4115087988
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3634393570
Short name T216
Test name
Test status
Simulation time 78056901570 ps
CPU time 140.98 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:30:57 PM PDT 24
Peak memory 190636 kb
Host smart-046f645f-076b-4992-93db-36d73ce52f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634393570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3634393570
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3490005362
Short name T332
Test name
Test status
Simulation time 2895675174546 ps
CPU time 1052.04 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:45:32 PM PDT 24
Peak memory 182476 kb
Host smart-15325be6-5f8e-45fb-9360-52ad3caa6cce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490005362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3490005362
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/174.rv_timer_random.2816274300
Short name T321
Test name
Test status
Simulation time 241353054090 ps
CPU time 127.76 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:30:45 PM PDT 24
Peak memory 190660 kb
Host smart-74527b9f-f8c4-4d67-83b2-189c3581fcde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816274300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2816274300
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3334593659
Short name T125
Test name
Test status
Simulation time 190061254698 ps
CPU time 194.1 seconds
Started May 23 12:28:38 PM PDT 24
Finished May 23 12:31:54 PM PDT 24
Peak memory 190796 kb
Host smart-19d824ba-1e23-40c8-ade3-def1eb7ae307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334593659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3334593659
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.443834711
Short name T344
Test name
Test status
Simulation time 134731579675 ps
CPU time 123.07 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:29:57 PM PDT 24
Peak memory 190652 kb
Host smart-66c9aa6a-3fa4-441d-910c-9b009231c221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443834711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.443834711
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_random.2866811007
Short name T75
Test name
Test status
Simulation time 142803576702 ps
CPU time 341.37 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:33:42 PM PDT 24
Peak memory 190668 kb
Host smart-49f5a787-db7e-4476-9447-89deab1c61bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866811007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2866811007
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2970835965
Short name T354
Test name
Test status
Simulation time 967686540985 ps
CPU time 525.14 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:36:48 PM PDT 24
Peak memory 182472 kb
Host smart-9de18a5c-c96e-4dd3-85ed-fe2a829333e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970835965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2970835965
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3131030694
Short name T312
Test name
Test status
Simulation time 67791686450 ps
CPU time 122.49 seconds
Started May 23 12:27:56 PM PDT 24
Finished May 23 12:30:01 PM PDT 24
Peak memory 182496 kb
Host smart-1c6898d3-c5b0-4508-855f-44cab3a61512
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131030694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3131030694
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_random.989208129
Short name T124
Test name
Test status
Simulation time 178308681777 ps
CPU time 166.4 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:30:42 PM PDT 24
Peak memory 190560 kb
Host smart-19dfb272-0cd4-4921-869a-8c16f69dfdba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989208129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.989208129
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.976146537
Short name T105
Test name
Test status
Simulation time 38972202486 ps
CPU time 65.22 seconds
Started May 23 12:27:38 PM PDT 24
Finished May 23 12:28:47 PM PDT 24
Peak memory 190740 kb
Host smart-48d0ef8c-ffba-4127-b76e-8c95b14fb9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976146537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.976146537
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_random.1236198806
Short name T340
Test name
Test status
Simulation time 690569336966 ps
CPU time 1487.12 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:52:51 PM PDT 24
Peak memory 190668 kb
Host smart-84c62784-8eea-46bb-a26e-65cd0f1e78d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236198806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1236198806
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2131535974
Short name T335
Test name
Test status
Simulation time 167087817272 ps
CPU time 285.32 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:32:52 PM PDT 24
Peak memory 182496 kb
Host smart-dd0eba54-11e1-453a-a5c1-93f86590d380
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131535974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2131535974
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/52.rv_timer_random.1112073183
Short name T213
Test name
Test status
Simulation time 241381068030 ps
CPU time 1105.33 seconds
Started May 23 12:28:20 PM PDT 24
Finished May 23 12:46:47 PM PDT 24
Peak memory 190680 kb
Host smart-93e75c27-0736-43ac-b07a-92ca4ea17f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112073183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1112073183
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2824619093
Short name T106
Test name
Test status
Simulation time 180440405387 ps
CPU time 432.97 seconds
Started May 23 12:28:06 PM PDT 24
Finished May 23 12:35:21 PM PDT 24
Peak memory 190248 kb
Host smart-4524520c-fd76-4f26-971a-f9b1074e6ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824619093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2824619093
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2422895501
Short name T141
Test name
Test status
Simulation time 194304298806 ps
CPU time 498.85 seconds
Started May 23 12:28:12 PM PDT 24
Finished May 23 12:36:32 PM PDT 24
Peak memory 190652 kb
Host smart-e4989e02-0a59-49f3-9cb8-24cf96b66756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422895501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2422895501
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.2817924161
Short name T234
Test name
Test status
Simulation time 335491833160 ps
CPU time 791.26 seconds
Started May 23 12:28:35 PM PDT 24
Finished May 23 12:41:49 PM PDT 24
Peak memory 190640 kb
Host smart-4ed21b24-b92a-4010-8a1a-344472796ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817924161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2817924161
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1981646027
Short name T339
Test name
Test status
Simulation time 103054669805 ps
CPU time 232.41 seconds
Started May 23 12:28:20 PM PDT 24
Finished May 23 12:32:15 PM PDT 24
Peak memory 190672 kb
Host smart-9bcd8dd4-4da8-45ae-89bb-631c470ac6d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981646027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1981646027
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4257352540
Short name T534
Test name
Test status
Simulation time 56710822 ps
CPU time 0.58 seconds
Started May 23 12:27:03 PM PDT 24
Finished May 23 12:27:09 PM PDT 24
Peak memory 182556 kb
Host smart-9f839048-b892-4a8d-bf90-45153245ecf6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257352540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4257352540
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3960287036
Short name T94
Test name
Test status
Simulation time 91568880 ps
CPU time 3.07 seconds
Started May 23 12:27:12 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 190440 kb
Host smart-1dedae6e-5916-4257-883f-7b1883b746ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960287036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3960287036
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1408608492
Short name T483
Test name
Test status
Simulation time 23687064 ps
CPU time 0.54 seconds
Started May 23 12:27:12 PM PDT 24
Finished May 23 12:27:16 PM PDT 24
Peak memory 182280 kb
Host smart-32237dc4-d8a3-4a65-a90c-28eff9aab967
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408608492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1408608492
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2919251279
Short name T56
Test name
Test status
Simulation time 28473161 ps
CPU time 0.76 seconds
Started May 23 12:27:12 PM PDT 24
Finished May 23 12:27:16 PM PDT 24
Peak memory 195136 kb
Host smart-50ad7c21-e1fb-4a70-9468-34bb8b8ca086
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919251279 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2919251279
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2515105118
Short name T471
Test name
Test status
Simulation time 18910803 ps
CPU time 0.55 seconds
Started May 23 12:27:11 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 181276 kb
Host smart-db902970-6ff8-460e-8fa9-7c0840efa6cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515105118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2515105118
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.458063480
Short name T86
Test name
Test status
Simulation time 59323272 ps
CPU time 0.78 seconds
Started May 23 12:27:11 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 193248 kb
Host smart-aac21813-be7e-4bad-9a7e-968d5411ef02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458063480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.458063480
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.49096174
Short name T523
Test name
Test status
Simulation time 324215133 ps
CPU time 1.55 seconds
Started May 23 12:27:10 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 197508 kb
Host smart-3935796f-560a-4724-969e-b5bff9fd26a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49096174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.49096174
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2944159875
Short name T96
Test name
Test status
Simulation time 66235637 ps
CPU time 0.67 seconds
Started May 23 12:27:03 PM PDT 24
Finished May 23 12:27:09 PM PDT 24
Peak memory 191828 kb
Host smart-018529b8-67cc-487d-84b8-850336a5e21e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944159875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2944159875
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2054988525
Short name T510
Test name
Test status
Simulation time 203592362 ps
CPU time 2.35 seconds
Started May 23 12:27:02 PM PDT 24
Finished May 23 12:27:09 PM PDT 24
Peak memory 190936 kb
Host smart-8e81e96e-f13e-448e-a8ee-d19f0a57757e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054988525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2054988525
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2072843623
Short name T90
Test name
Test status
Simulation time 57092245 ps
CPU time 0.59 seconds
Started May 23 12:27:02 PM PDT 24
Finished May 23 12:27:07 PM PDT 24
Peak memory 182508 kb
Host smart-7d0c6241-6fa6-494b-b2a4-7601dfc6e209
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072843623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2072843623
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2881236482
Short name T496
Test name
Test status
Simulation time 30712702 ps
CPU time 0.72 seconds
Started May 23 12:27:10 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 190408 kb
Host smart-b1ec4eb9-9168-4e70-a116-27a2af9185b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881236482 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2881236482
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2256647035
Short name T549
Test name
Test status
Simulation time 46728325 ps
CPU time 0.59 seconds
Started May 23 12:27:02 PM PDT 24
Finished May 23 12:27:06 PM PDT 24
Peak memory 182532 kb
Host smart-170726d3-ede2-42bf-a459-fea6c327f07f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256647035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2256647035
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3240557988
Short name T473
Test name
Test status
Simulation time 21202509 ps
CPU time 0.56 seconds
Started May 23 12:27:03 PM PDT 24
Finished May 23 12:27:09 PM PDT 24
Peak memory 182480 kb
Host smart-58cf96d9-016b-4543-a4d6-1e28846b835f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240557988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3240557988
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2915018835
Short name T101
Test name
Test status
Simulation time 207403996 ps
CPU time 0.76 seconds
Started May 23 12:27:10 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 189784 kb
Host smart-4a247ec5-79e0-477e-8792-5a9cb4ba5876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915018835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2915018835
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.267533719
Short name T484
Test name
Test status
Simulation time 122854953 ps
CPU time 1.27 seconds
Started May 23 12:27:03 PM PDT 24
Finished May 23 12:27:10 PM PDT 24
Peak memory 195996 kb
Host smart-84f0483b-8cd6-4f8b-8c8a-02e3c02b6234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267533719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.267533719
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1225583187
Short name T522
Test name
Test status
Simulation time 428781155 ps
CPU time 1.48 seconds
Started May 23 12:27:06 PM PDT 24
Finished May 23 12:27:12 PM PDT 24
Peak memory 183236 kb
Host smart-f8c1b4c5-4624-4acd-9e76-96bf1656b7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225583187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1225583187
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1646184154
Short name T53
Test name
Test status
Simulation time 147371448 ps
CPU time 0.9 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:22 PM PDT 24
Peak memory 197312 kb
Host smart-876868f2-1f3c-432f-ad48-99e1bc07848e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646184154 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1646184154
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2076344317
Short name T508
Test name
Test status
Simulation time 14069521 ps
CPU time 0.62 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 182668 kb
Host smart-408f92e3-a5e1-4ca5-8a47-85ded003479e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076344317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2076344317
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1670646197
Short name T455
Test name
Test status
Simulation time 41406152 ps
CPU time 0.53 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:21 PM PDT 24
Peak memory 182100 kb
Host smart-9622948c-0dab-4531-b74f-5136e3448636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670646197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1670646197
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3603133762
Short name T504
Test name
Test status
Simulation time 107481447 ps
CPU time 0.63 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 191204 kb
Host smart-7172a9b5-1a9e-4d2f-bed0-643e10af1d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603133762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3603133762
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3602765048
Short name T526
Test name
Test status
Simulation time 427420672 ps
CPU time 2.98 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 197484 kb
Host smart-01c1f455-dd27-4e8e-944f-252b5b10cc37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602765048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3602765048
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1546419145
Short name T555
Test name
Test status
Simulation time 415722589 ps
CPU time 1.3 seconds
Started May 23 12:27:22 PM PDT 24
Finished May 23 12:27:27 PM PDT 24
Peak memory 195180 kb
Host smart-717c55e1-9d21-4acd-bceb-717d78675873
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546419145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1546419145
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1031971266
Short name T54
Test name
Test status
Simulation time 40401102 ps
CPU time 0.69 seconds
Started May 23 12:27:21 PM PDT 24
Finished May 23 12:27:25 PM PDT 24
Peak memory 194864 kb
Host smart-4f83fe7a-d09c-48a5-99f5-b80ee799149c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031971266 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1031971266
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1440339976
Short name T489
Test name
Test status
Simulation time 18552882 ps
CPU time 0.59 seconds
Started May 23 12:27:24 PM PDT 24
Finished May 23 12:27:27 PM PDT 24
Peak memory 182520 kb
Host smart-8902ee6b-bdc0-4dc8-ad00-7b83e131c395
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440339976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1440339976
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3266025750
Short name T486
Test name
Test status
Simulation time 10631569 ps
CPU time 0.54 seconds
Started May 23 12:27:30 PM PDT 24
Finished May 23 12:27:33 PM PDT 24
Peak memory 182552 kb
Host smart-4d94725f-f01d-46f5-901f-bbec9b276add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266025750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3266025750
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.412420734
Short name T571
Test name
Test status
Simulation time 41230333 ps
CPU time 0.61 seconds
Started May 23 12:27:22 PM PDT 24
Finished May 23 12:27:26 PM PDT 24
Peak memory 191444 kb
Host smart-d1167fb8-fef9-44d9-94a2-2cc9293d43ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412420734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.412420734
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2338108268
Short name T503
Test name
Test status
Simulation time 245768355 ps
CPU time 1.92 seconds
Started May 23 12:27:19 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 197500 kb
Host smart-8fb64259-63d0-42ef-8f3c-ac665c6c4fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338108268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2338108268
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1390426625
Short name T519
Test name
Test status
Simulation time 22771718 ps
CPU time 0.94 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 196912 kb
Host smart-93f453b0-8765-4460-9b51-cd5f179de710
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390426625 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1390426625
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1475864327
Short name T456
Test name
Test status
Simulation time 20918793 ps
CPU time 0.54 seconds
Started May 23 12:27:25 PM PDT 24
Finished May 23 12:27:27 PM PDT 24
Peak memory 182380 kb
Host smart-0cc4a444-c13b-4408-ab03-d254e987c9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475864327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1475864327
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2836992997
Short name T498
Test name
Test status
Simulation time 51631255 ps
CPU time 0.7 seconds
Started May 23 12:27:19 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 191508 kb
Host smart-f16fd9b1-3d3e-426f-adf0-63cb30f1ad20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836992997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2836992997
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1085998653
Short name T515
Test name
Test status
Simulation time 155963905 ps
CPU time 2.04 seconds
Started May 23 12:27:20 PM PDT 24
Finished May 23 12:27:26 PM PDT 24
Peak memory 197428 kb
Host smart-284162a7-e870-46e0-846d-bf3d64fecf35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085998653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1085998653
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2591586824
Short name T118
Test name
Test status
Simulation time 48355654 ps
CPU time 0.81 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:21 PM PDT 24
Peak memory 182840 kb
Host smart-a5575d58-457e-46ca-adfc-cb57e6e70804
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591586824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2591586824
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2268580793
Short name T562
Test name
Test status
Simulation time 15850822 ps
CPU time 0.75 seconds
Started May 23 12:27:25 PM PDT 24
Finished May 23 12:27:27 PM PDT 24
Peak memory 195032 kb
Host smart-41e9a1b9-7af4-425c-a64e-11cecbe06b3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268580793 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2268580793
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3264783918
Short name T505
Test name
Test status
Simulation time 25374153 ps
CPU time 0.55 seconds
Started May 23 12:27:26 PM PDT 24
Finished May 23 12:27:28 PM PDT 24
Peak memory 182304 kb
Host smart-53eb7dda-c351-4645-b38c-7c7982d37be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264783918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3264783918
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3019896732
Short name T550
Test name
Test status
Simulation time 32025928 ps
CPU time 0.56 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 182388 kb
Host smart-c2bb2a75-7e53-45c1-a6bb-d22060d7ad70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019896732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3019896732
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3701768406
Short name T561
Test name
Test status
Simulation time 70489253 ps
CPU time 0.77 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:21 PM PDT 24
Peak memory 193168 kb
Host smart-3d4c2bfc-14e9-46b2-a6ae-eb5e842d22a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701768406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3701768406
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3023417598
Short name T557
Test name
Test status
Simulation time 86423932 ps
CPU time 1.18 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:22 PM PDT 24
Peak memory 197232 kb
Host smart-6b6f9fe9-20e0-4455-a4d3-220bbccd66c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023417598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3023417598
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1553272897
Short name T464
Test name
Test status
Simulation time 47658708 ps
CPU time 0.83 seconds
Started May 23 12:27:19 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 182920 kb
Host smart-c31ad15e-52b8-4151-91db-dbe055ec0d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553272897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1553272897
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3710379220
Short name T58
Test name
Test status
Simulation time 75539387 ps
CPU time 0.65 seconds
Started May 23 12:27:13 PM PDT 24
Finished May 23 12:27:17 PM PDT 24
Peak memory 194496 kb
Host smart-c0288d9b-bad1-4cbf-bcdb-bf12f8d48494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710379220 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3710379220
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1795770319
Short name T467
Test name
Test status
Simulation time 12926283 ps
CPU time 0.55 seconds
Started May 23 12:27:21 PM PDT 24
Finished May 23 12:27:25 PM PDT 24
Peak memory 182544 kb
Host smart-d1c0c904-6157-43b4-b9db-042f6ddf1f75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795770319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1795770319
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1701045159
Short name T537
Test name
Test status
Simulation time 32693990 ps
CPU time 0.54 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 182344 kb
Host smart-b6c23f10-9dda-4cb5-aea9-70e8cfa9ba9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701045159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1701045159
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.468025516
Short name T516
Test name
Test status
Simulation time 86146513 ps
CPU time 0.59 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 191208 kb
Host smart-43426515-8769-4944-8e1d-7f6e3d3e1b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468025516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.468025516
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2610428630
Short name T481
Test name
Test status
Simulation time 33630422 ps
CPU time 1.73 seconds
Started May 23 12:27:19 PM PDT 24
Finished May 23 12:27:28 PM PDT 24
Peak memory 197444 kb
Host smart-34b7045a-4b34-4ac1-983d-f826d9802763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610428630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2610428630
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2491914835
Short name T31
Test name
Test status
Simulation time 309867633 ps
CPU time 1.05 seconds
Started May 23 12:27:20 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 183236 kb
Host smart-2cace680-f082-4a5b-816e-66d487bbefdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491914835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2491914835
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2196530011
Short name T52
Test name
Test status
Simulation time 28115335 ps
CPU time 0.72 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 195008 kb
Host smart-991e5774-5ce5-4b33-abe0-220b56f3f66a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196530011 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2196530011
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3422612940
Short name T50
Test name
Test status
Simulation time 16601434 ps
CPU time 0.58 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 182268 kb
Host smart-250f0990-feeb-47f8-aa2f-286ab028de30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422612940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3422612940
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1424743498
Short name T512
Test name
Test status
Simulation time 25496456 ps
CPU time 0.55 seconds
Started May 23 12:27:23 PM PDT 24
Finished May 23 12:27:26 PM PDT 24
Peak memory 181896 kb
Host smart-b9ce3724-63ef-4ec9-9d25-d76c3758c68e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424743498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1424743498
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.461978546
Short name T51
Test name
Test status
Simulation time 30756888 ps
CPU time 0.71 seconds
Started May 23 12:27:20 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 192468 kb
Host smart-ee0f1abf-14ed-491f-a283-d02ddfd57fc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461978546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.461978546
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1572506110
Short name T475
Test name
Test status
Simulation time 125462797 ps
CPU time 0.94 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:22 PM PDT 24
Peak memory 197124 kb
Host smart-b4f73328-9442-4a0b-b207-5d5253e978c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572506110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1572506110
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2953205746
Short name T553
Test name
Test status
Simulation time 140187269 ps
CPU time 1.08 seconds
Started May 23 12:27:31 PM PDT 24
Finished May 23 12:27:35 PM PDT 24
Peak memory 195124 kb
Host smart-7c6fec45-b3a0-40be-9ce3-002d6c24d8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953205746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2953205746
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3932304888
Short name T566
Test name
Test status
Simulation time 147791233 ps
CPU time 0.93 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 196604 kb
Host smart-dbafe73b-c7de-4957-b7aa-4239b088b70a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932304888 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3932304888
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1763807250
Short name T573
Test name
Test status
Simulation time 16900847 ps
CPU time 0.58 seconds
Started May 23 12:27:21 PM PDT 24
Finished May 23 12:27:27 PM PDT 24
Peak memory 182692 kb
Host smart-22bd04ed-5e4e-4284-9f92-b6a6eccd7955
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763807250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1763807250
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.411129678
Short name T539
Test name
Test status
Simulation time 16733127 ps
CPU time 0.53 seconds
Started May 23 12:27:21 PM PDT 24
Finished May 23 12:27:25 PM PDT 24
Peak memory 182440 kb
Host smart-23ef4e4f-55ad-4e8c-97f4-59c2c28dbb10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411129678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.411129678
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3169810227
Short name T103
Test name
Test status
Simulation time 181080473 ps
CPU time 0.76 seconds
Started May 23 12:27:20 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 191616 kb
Host smart-bd80ee5c-c241-48d0-a13a-c3bb7c6876b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169810227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3169810227
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3501804803
Short name T543
Test name
Test status
Simulation time 51562705 ps
CPU time 2.27 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:22 PM PDT 24
Peak memory 197468 kb
Host smart-cf03d993-5352-4e68-9e3f-a8f8f6c564b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501804803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3501804803
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3250800084
Short name T117
Test name
Test status
Simulation time 216501708 ps
CPU time 1.27 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 194800 kb
Host smart-f3e42632-b5a4-4276-8dfc-196d8a7c04d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250800084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3250800084
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.185424804
Short name T465
Test name
Test status
Simulation time 114823945 ps
CPU time 1.26 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 197052 kb
Host smart-3a8d9361-12db-4925-b690-e529746cd99b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185424804 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.185424804
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3195777681
Short name T92
Test name
Test status
Simulation time 42690118 ps
CPU time 0.57 seconds
Started May 23 12:27:20 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 182556 kb
Host smart-2094ddfa-1317-45c3-a629-58de5bf569b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195777681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3195777681
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1469137847
Short name T458
Test name
Test status
Simulation time 13322992 ps
CPU time 0.53 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:18 PM PDT 24
Peak memory 182500 kb
Host smart-60c2f249-2c9d-4c62-b19c-0ef3af1dc5dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469137847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1469137847
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3941428179
Short name T509
Test name
Test status
Simulation time 31742627 ps
CPU time 0.75 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 192952 kb
Host smart-2059a4de-f79f-4983-9172-96e76a7aeb44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941428179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3941428179
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3281149272
Short name T468
Test name
Test status
Simulation time 175779754 ps
CPU time 2.1 seconds
Started May 23 12:27:20 PM PDT 24
Finished May 23 12:27:26 PM PDT 24
Peak memory 197572 kb
Host smart-ec708c89-dcd0-4030-8990-52640cb5709e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281149272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3281149272
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.674958992
Short name T527
Test name
Test status
Simulation time 77374347 ps
CPU time 0.83 seconds
Started May 23 12:27:20 PM PDT 24
Finished May 23 12:27:25 PM PDT 24
Peak memory 193772 kb
Host smart-43e0be17-7348-4216-bde8-7ca4184fd050
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674958992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.674958992
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1835944140
Short name T531
Test name
Test status
Simulation time 27647970 ps
CPU time 0.83 seconds
Started May 23 12:27:35 PM PDT 24
Finished May 23 12:27:40 PM PDT 24
Peak memory 195588 kb
Host smart-37ce53d4-b49d-4268-a440-68cfe5053f02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835944140 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1835944140
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3873815158
Short name T494
Test name
Test status
Simulation time 40985021 ps
CPU time 0.54 seconds
Started May 23 12:27:33 PM PDT 24
Finished May 23 12:27:38 PM PDT 24
Peak memory 182256 kb
Host smart-edf32f78-88dd-4fd6-adc9-93a4cfd30ffc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873815158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3873815158
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.476265898
Short name T476
Test name
Test status
Simulation time 34526310 ps
CPU time 0.53 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:27:36 PM PDT 24
Peak memory 181900 kb
Host smart-a5612cf4-079d-4076-be57-684eba8e1940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476265898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.476265898
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.835356665
Short name T102
Test name
Test status
Simulation time 37002182 ps
CPU time 0.59 seconds
Started May 23 12:27:30 PM PDT 24
Finished May 23 12:27:32 PM PDT 24
Peak memory 191704 kb
Host smart-1ff60f91-8955-4c1e-be3d-eac3d89455d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835356665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.835356665
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1173947065
Short name T554
Test name
Test status
Simulation time 220528742 ps
CPU time 1.36 seconds
Started May 23 12:27:26 PM PDT 24
Finished May 23 12:27:29 PM PDT 24
Peak memory 197452 kb
Host smart-753f6044-7706-45a1-8b5a-f92f72a896ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173947065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1173947065
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4158276927
Short name T116
Test name
Test status
Simulation time 41675221 ps
CPU time 0.78 seconds
Started May 23 12:27:30 PM PDT 24
Finished May 23 12:27:33 PM PDT 24
Peak memory 192568 kb
Host smart-8581a65a-81f4-4f0a-a909-05439cb91e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158276927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4158276927
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4104236524
Short name T521
Test name
Test status
Simulation time 33807157 ps
CPU time 0.78 seconds
Started May 23 12:27:28 PM PDT 24
Finished May 23 12:27:29 PM PDT 24
Peak memory 196268 kb
Host smart-0f1cb618-80d5-41d5-9771-6c6d11b7f70c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104236524 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4104236524
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1458285447
Short name T32
Test name
Test status
Simulation time 30064271 ps
CPU time 0.56 seconds
Started May 23 12:27:34 PM PDT 24
Finished May 23 12:27:38 PM PDT 24
Peak memory 182604 kb
Host smart-30762d71-68c1-40af-b4b5-004075993269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458285447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1458285447
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1976181159
Short name T540
Test name
Test status
Simulation time 42271313 ps
CPU time 0.55 seconds
Started May 23 12:27:42 PM PDT 24
Finished May 23 12:27:45 PM PDT 24
Peak memory 182100 kb
Host smart-053dd2fc-309d-4a94-86ff-1c9ca8f2ff09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976181159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1976181159
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2328327471
Short name T544
Test name
Test status
Simulation time 134904520 ps
CPU time 0.85 seconds
Started May 23 12:27:31 PM PDT 24
Finished May 23 12:27:33 PM PDT 24
Peak memory 194416 kb
Host smart-090ed6e7-3af4-4655-86e6-9d35ce3d843d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328327471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2328327471
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.385266880
Short name T482
Test name
Test status
Simulation time 111932078 ps
CPU time 2.94 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:27:38 PM PDT 24
Peak memory 197444 kb
Host smart-b3747312-06c5-4acf-9562-4e201c34a755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385266880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.385266880
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1162439961
Short name T529
Test name
Test status
Simulation time 427099189 ps
CPU time 0.81 seconds
Started May 23 12:27:38 PM PDT 24
Finished May 23 12:27:43 PM PDT 24
Peak memory 193612 kb
Host smart-9afde127-73d3-46d6-b107-7f0773e4e2e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162439961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1162439961
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.342776229
Short name T95
Test name
Test status
Simulation time 19570841 ps
CPU time 0.94 seconds
Started May 23 12:27:10 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 189976 kb
Host smart-78ccf938-1ffb-4c8a-8193-e0cb35ee9475
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342776229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.342776229
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2977100475
Short name T472
Test name
Test status
Simulation time 726852297 ps
CPU time 2.5 seconds
Started May 23 12:27:10 PM PDT 24
Finished May 23 12:27:16 PM PDT 24
Peak memory 190908 kb
Host smart-cd86ad02-f83a-441f-9883-82b49cfde77b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977100475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2977100475
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.679460511
Short name T470
Test name
Test status
Simulation time 29468513 ps
CPU time 0.65 seconds
Started May 23 12:27:10 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 179204 kb
Host smart-4031b058-45c8-456a-9741-7519661ac6f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679460511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.679460511
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2611819365
Short name T40
Test name
Test status
Simulation time 35447336 ps
CPU time 0.94 seconds
Started May 23 12:27:05 PM PDT 24
Finished May 23 12:27:11 PM PDT 24
Peak memory 196884 kb
Host smart-24cdbdf5-7fb0-4e08-b1cb-d8d915c33cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611819365 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2611819365
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.175114174
Short name T533
Test name
Test status
Simulation time 40046177 ps
CPU time 0.53 seconds
Started May 23 12:27:13 PM PDT 24
Finished May 23 12:27:17 PM PDT 24
Peak memory 182184 kb
Host smart-b1ce6793-d188-45e9-a2c0-c8d97db4a6e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175114174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.175114174
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.338406417
Short name T552
Test name
Test status
Simulation time 16837159 ps
CPU time 0.64 seconds
Started May 23 12:27:10 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 179340 kb
Host smart-38e3d046-12d2-46b1-99dc-657db494506e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338406417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.338406417
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3760318087
Short name T34
Test name
Test status
Simulation time 27420502 ps
CPU time 0.74 seconds
Started May 23 12:27:04 PM PDT 24
Finished May 23 12:27:09 PM PDT 24
Peak memory 191512 kb
Host smart-a1227334-28b1-4e95-8af5-590e740d7cf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760318087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3760318087
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1818741846
Short name T518
Test name
Test status
Simulation time 48877487 ps
CPU time 1.31 seconds
Started May 23 12:27:03 PM PDT 24
Finished May 23 12:27:09 PM PDT 24
Peak memory 197400 kb
Host smart-e2f6a1b2-8591-40f8-a2a9-93788942bdc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818741846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1818741846
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3381533965
Short name T115
Test name
Test status
Simulation time 82261907 ps
CPU time 1.1 seconds
Started May 23 12:27:04 PM PDT 24
Finished May 23 12:27:10 PM PDT 24
Peak memory 183364 kb
Host smart-03430214-6f5f-4985-8717-81bfcaad4e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381533965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3381533965
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3215822500
Short name T530
Test name
Test status
Simulation time 53085580 ps
CPU time 0.56 seconds
Started May 23 12:27:37 PM PDT 24
Finished May 23 12:27:42 PM PDT 24
Peak memory 182400 kb
Host smart-2ea091e8-e22c-4bc5-a9bc-29d182d55624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215822500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3215822500
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2750624457
Short name T453
Test name
Test status
Simulation time 47588329 ps
CPU time 0.53 seconds
Started May 23 12:27:28 PM PDT 24
Finished May 23 12:27:30 PM PDT 24
Peak memory 182236 kb
Host smart-7d2bdd32-5567-4b33-a87f-dc96f0555823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750624457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2750624457
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.675744293
Short name T542
Test name
Test status
Simulation time 174389250 ps
CPU time 0.52 seconds
Started May 23 12:27:35 PM PDT 24
Finished May 23 12:27:40 PM PDT 24
Peak memory 182064 kb
Host smart-d3bd19ca-1b78-4b70-bfac-ad68f7d5d7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675744293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.675744293
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1994361645
Short name T541
Test name
Test status
Simulation time 43916794 ps
CPU time 0.57 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:27:35 PM PDT 24
Peak memory 182492 kb
Host smart-da455654-6c56-4bd7-98b0-7dc07f63acf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994361645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1994361645
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1221394535
Short name T495
Test name
Test status
Simulation time 45716199 ps
CPU time 0.5 seconds
Started May 23 12:27:27 PM PDT 24
Finished May 23 12:27:29 PM PDT 24
Peak memory 181884 kb
Host smart-61dc1928-c260-4d53-ae6b-aa4c87e09457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221394535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1221394535
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4026678335
Short name T547
Test name
Test status
Simulation time 15220785 ps
CPU time 0.52 seconds
Started May 23 12:27:26 PM PDT 24
Finished May 23 12:27:28 PM PDT 24
Peak memory 182428 kb
Host smart-c3490270-2627-4581-bb4d-d71c2851c1ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026678335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4026678335
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1304940331
Short name T528
Test name
Test status
Simulation time 15190992 ps
CPU time 0.58 seconds
Started May 23 12:27:39 PM PDT 24
Finished May 23 12:27:47 PM PDT 24
Peak memory 182540 kb
Host smart-f58d1a4c-bc4c-4256-85ec-0d3578d7cb91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304940331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1304940331
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.566316772
Short name T517
Test name
Test status
Simulation time 43636974 ps
CPU time 0.52 seconds
Started May 23 12:27:28 PM PDT 24
Finished May 23 12:27:31 PM PDT 24
Peak memory 181964 kb
Host smart-defaa08e-8fba-4468-bab9-9a6cb98dd170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566316772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.566316772
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.862608955
Short name T538
Test name
Test status
Simulation time 64740709 ps
CPU time 0.56 seconds
Started May 23 12:27:42 PM PDT 24
Finished May 23 12:27:45 PM PDT 24
Peak memory 182616 kb
Host smart-e2de2fe3-4976-49f0-94b8-55176349d562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862608955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.862608955
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.737457948
Short name T474
Test name
Test status
Simulation time 20297659 ps
CPU time 0.57 seconds
Started May 23 12:27:40 PM PDT 24
Finished May 23 12:27:44 PM PDT 24
Peak memory 181820 kb
Host smart-05f68561-038f-4396-a21a-26372126824e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737457948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.737457948
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3503393718
Short name T97
Test name
Test status
Simulation time 17151117 ps
CPU time 0.71 seconds
Started May 23 12:27:09 PM PDT 24
Finished May 23 12:27:14 PM PDT 24
Peak memory 182536 kb
Host smart-05f7226f-931d-4060-9deb-712b8cd176de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503393718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3503393718
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2702866096
Short name T87
Test name
Test status
Simulation time 263589729 ps
CPU time 2.32 seconds
Started May 23 12:27:09 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 190908 kb
Host smart-6ef82366-9e96-40f2-b706-7cf8c42e0135
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702866096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2702866096
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3726205238
Short name T33
Test name
Test status
Simulation time 66971747 ps
CPU time 0.58 seconds
Started May 23 12:27:04 PM PDT 24
Finished May 23 12:27:09 PM PDT 24
Peak memory 182472 kb
Host smart-65a93444-5291-455a-bc1b-60958a04d42d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726205238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3726205238
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.889809217
Short name T39
Test name
Test status
Simulation time 26834055 ps
CPU time 1.07 seconds
Started May 23 12:27:09 PM PDT 24
Finished May 23 12:27:14 PM PDT 24
Peak memory 197448 kb
Host smart-b4b3b1a5-8f9f-451a-b7a7-34839d7b3251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889809217 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.889809217
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2356374022
Short name T497
Test name
Test status
Simulation time 16423890 ps
CPU time 0.54 seconds
Started May 23 12:27:03 PM PDT 24
Finished May 23 12:27:08 PM PDT 24
Peak memory 182548 kb
Host smart-91af14f1-34a0-495d-84a4-ca6a1b6b5495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356374022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2356374022
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3172831665
Short name T492
Test name
Test status
Simulation time 56368286 ps
CPU time 0.65 seconds
Started May 23 12:27:10 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 179964 kb
Host smart-49ec0261-0dc3-41a4-a181-07a2bc1ee955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172831665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3172831665
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1900744351
Short name T88
Test name
Test status
Simulation time 35680745 ps
CPU time 0.71 seconds
Started May 23 12:27:01 PM PDT 24
Finished May 23 12:27:06 PM PDT 24
Peak memory 191524 kb
Host smart-43b16e17-6d70-41f4-a3cc-76628c6a1578
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900744351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1900744351
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1329294751
Short name T568
Test name
Test status
Simulation time 32998570 ps
CPU time 1.59 seconds
Started May 23 12:27:09 PM PDT 24
Finished May 23 12:27:14 PM PDT 24
Peak memory 197476 kb
Host smart-a9dd379b-d9cd-4814-aa47-1027e0b046b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329294751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1329294751
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3041518096
Short name T567
Test name
Test status
Simulation time 490958286 ps
CPU time 1.4 seconds
Started May 23 12:27:03 PM PDT 24
Finished May 23 12:27:10 PM PDT 24
Peak memory 183036 kb
Host smart-c11cb870-b4b3-4e46-a8ae-f03d67b3aca3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041518096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3041518096
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.4142828730
Short name T461
Test name
Test status
Simulation time 127282875 ps
CPU time 0.59 seconds
Started May 23 12:27:44 PM PDT 24
Finished May 23 12:27:46 PM PDT 24
Peak memory 182488 kb
Host smart-4a0ec748-6b12-4521-9dbb-2f67574a9b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142828730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.4142828730
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2418422851
Short name T506
Test name
Test status
Simulation time 21691076 ps
CPU time 0.54 seconds
Started May 23 12:27:29 PM PDT 24
Finished May 23 12:27:31 PM PDT 24
Peak memory 181996 kb
Host smart-a2dacbb4-1f78-46bd-a857-e2fa1f8bdfd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418422851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2418422851
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.449620237
Short name T462
Test name
Test status
Simulation time 44778495 ps
CPU time 0.59 seconds
Started May 23 12:27:33 PM PDT 24
Finished May 23 12:27:37 PM PDT 24
Peak memory 182412 kb
Host smart-db3217a4-7bac-462d-a406-483ed18fc318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449620237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.449620237
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2701746125
Short name T560
Test name
Test status
Simulation time 43167538 ps
CPU time 0.53 seconds
Started May 23 12:27:41 PM PDT 24
Finished May 23 12:27:44 PM PDT 24
Peak memory 182016 kb
Host smart-fc1d4d34-2605-44cc-9fb2-a8a0a1fd6c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701746125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2701746125
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4211709877
Short name T501
Test name
Test status
Simulation time 52176653 ps
CPU time 0.55 seconds
Started May 23 12:27:43 PM PDT 24
Finished May 23 12:27:46 PM PDT 24
Peak memory 182612 kb
Host smart-da78d770-8d28-4346-a21f-eb09d4920f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211709877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4211709877
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2970351098
Short name T488
Test name
Test status
Simulation time 44297735 ps
CPU time 0.56 seconds
Started May 23 12:27:31 PM PDT 24
Finished May 23 12:27:34 PM PDT 24
Peak memory 182548 kb
Host smart-c3d4dfaa-5dc4-4bc3-8be3-5850374d4c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970351098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2970351098
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3094454536
Short name T569
Test name
Test status
Simulation time 17202203 ps
CPU time 0.55 seconds
Started May 23 12:27:44 PM PDT 24
Finished May 23 12:27:46 PM PDT 24
Peak memory 182436 kb
Host smart-d0342554-0393-44ed-8128-8735db78c497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094454536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3094454536
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1656735066
Short name T548
Test name
Test status
Simulation time 89171858 ps
CPU time 0.54 seconds
Started May 23 12:27:31 PM PDT 24
Finished May 23 12:27:34 PM PDT 24
Peak memory 182348 kb
Host smart-0e1a4b37-1d1e-4c0e-b218-2b69c87f611c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656735066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1656735066
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2618627413
Short name T551
Test name
Test status
Simulation time 15859075 ps
CPU time 0.55 seconds
Started May 23 12:27:49 PM PDT 24
Finished May 23 12:27:51 PM PDT 24
Peak memory 182424 kb
Host smart-5c98ed6d-1b8e-4dfd-8889-e95f2672aa5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618627413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2618627413
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3720045682
Short name T466
Test name
Test status
Simulation time 18859038 ps
CPU time 0.59 seconds
Started May 23 12:27:33 PM PDT 24
Finished May 23 12:27:37 PM PDT 24
Peak memory 182448 kb
Host smart-d5f0cee2-4381-4c12-b4b8-8d33f86e0f1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720045682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3720045682
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1264584429
Short name T98
Test name
Test status
Simulation time 46513127 ps
CPU time 0.7 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 182560 kb
Host smart-6431c5ae-27c6-4a8a-94b5-16477e83db5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264584429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1264584429
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1814502502
Short name T490
Test name
Test status
Simulation time 315852758 ps
CPU time 1.52 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 182732 kb
Host smart-b6f99d0c-0bb8-47d0-9b38-3cb40126de5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814502502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1814502502
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3055053326
Short name T535
Test name
Test status
Simulation time 26248584 ps
CPU time 0.53 seconds
Started May 23 12:27:14 PM PDT 24
Finished May 23 12:27:17 PM PDT 24
Peak memory 182548 kb
Host smart-711668c1-5a53-42cb-b746-cab4545f6611
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055053326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3055053326
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2389480483
Short name T559
Test name
Test status
Simulation time 34718949 ps
CPU time 0.95 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 196792 kb
Host smart-ca8edcbe-50da-44ff-babb-a87bcfc80ef1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389480483 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2389480483
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3580870202
Short name T85
Test name
Test status
Simulation time 16109716 ps
CPU time 0.59 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 182528 kb
Host smart-25fd2ce5-f7fc-4c89-8000-6cb13a5b1f5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580870202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3580870202
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3484599300
Short name T457
Test name
Test status
Simulation time 28365664 ps
CPU time 0.53 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:21 PM PDT 24
Peak memory 181900 kb
Host smart-3c8aa975-5e55-4e43-ae15-851dafbaa6f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484599300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3484599300
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2095537068
Short name T100
Test name
Test status
Simulation time 32215641 ps
CPU time 0.81 seconds
Started May 23 12:27:11 PM PDT 24
Finished May 23 12:27:15 PM PDT 24
Peak memory 193368 kb
Host smart-8aeb41be-64c9-44dc-bdee-c8479766061d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095537068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2095537068
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1490539421
Short name T469
Test name
Test status
Simulation time 139697651 ps
CPU time 1.74 seconds
Started May 23 12:27:01 PM PDT 24
Finished May 23 12:27:07 PM PDT 24
Peak memory 197296 kb
Host smart-039a20e5-3aeb-4924-9cac-04b755b4cccd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490539421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1490539421
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1784278840
Short name T30
Test name
Test status
Simulation time 183879274 ps
CPU time 0.77 seconds
Started May 23 12:27:03 PM PDT 24
Finished May 23 12:27:09 PM PDT 24
Peak memory 193160 kb
Host smart-8f954584-a52e-4842-b1d8-4573689f2a4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784278840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1784278840
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2726468677
Short name T480
Test name
Test status
Simulation time 45313628 ps
CPU time 0.57 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:27:35 PM PDT 24
Peak memory 182408 kb
Host smart-01aec461-8b27-429b-aa5a-5fcf8a218ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726468677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2726468677
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1266092214
Short name T532
Test name
Test status
Simulation time 45059923 ps
CPU time 0.51 seconds
Started May 23 12:27:29 PM PDT 24
Finished May 23 12:27:31 PM PDT 24
Peak memory 181848 kb
Host smart-1607fe76-acce-41ce-a55d-7ac725a15cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266092214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1266092214
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3348362113
Short name T451
Test name
Test status
Simulation time 23086230 ps
CPU time 0.53 seconds
Started May 23 12:27:35 PM PDT 24
Finished May 23 12:27:39 PM PDT 24
Peak memory 181972 kb
Host smart-640ccf35-3766-459c-b394-ac381c8cba89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348362113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3348362113
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1523825545
Short name T565
Test name
Test status
Simulation time 20165033 ps
CPU time 0.51 seconds
Started May 23 12:27:27 PM PDT 24
Finished May 23 12:27:29 PM PDT 24
Peak memory 182492 kb
Host smart-aba3f5d7-c9b5-4d1b-bfc7-e378cfe927f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523825545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1523825545
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.60564494
Short name T564
Test name
Test status
Simulation time 60067669 ps
CPU time 0.56 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:27:36 PM PDT 24
Peak memory 182544 kb
Host smart-de0df6c5-de36-44d7-b083-faae77d286fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60564494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.60564494
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3200550262
Short name T452
Test name
Test status
Simulation time 17576179 ps
CPU time 0.56 seconds
Started May 23 12:27:47 PM PDT 24
Finished May 23 12:27:49 PM PDT 24
Peak memory 182440 kb
Host smart-f891cdb4-65b0-4606-888c-b56cb731ad1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200550262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3200550262
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1502446055
Short name T511
Test name
Test status
Simulation time 13254787 ps
CPU time 0.53 seconds
Started May 23 12:27:35 PM PDT 24
Finished May 23 12:27:39 PM PDT 24
Peak memory 182112 kb
Host smart-c9e2a042-31e0-4039-b1e2-6af6a8b4a43f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502446055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1502446055
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.175830938
Short name T478
Test name
Test status
Simulation time 34589478 ps
CPU time 0.55 seconds
Started May 23 12:27:41 PM PDT 24
Finished May 23 12:27:44 PM PDT 24
Peak memory 182516 kb
Host smart-d28d1221-9c3e-4153-a0c3-a303ff283409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175830938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.175830938
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3454175911
Short name T454
Test name
Test status
Simulation time 12843648 ps
CPU time 0.54 seconds
Started May 23 12:27:37 PM PDT 24
Finished May 23 12:27:42 PM PDT 24
Peak memory 181928 kb
Host smart-3c433987-eb32-4809-a478-c40a58f568b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454175911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3454175911
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.371840912
Short name T460
Test name
Test status
Simulation time 12338045 ps
CPU time 0.54 seconds
Started May 23 12:27:36 PM PDT 24
Finished May 23 12:27:41 PM PDT 24
Peak memory 181928 kb
Host smart-71768935-6b9a-415c-a70f-2dc573a67f1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371840912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.371840912
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2243785177
Short name T556
Test name
Test status
Simulation time 36176749 ps
CPU time 1.53 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 197408 kb
Host smart-d7e54864-3d58-4592-9242-2687d1475c2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243785177 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2243785177
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1527043209
Short name T487
Test name
Test status
Simulation time 25346431 ps
CPU time 0.63 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 182528 kb
Host smart-84fcf914-441c-4a0b-8093-f86fa12f5d70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527043209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1527043209
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2981094294
Short name T491
Test name
Test status
Simulation time 40321254 ps
CPU time 0.54 seconds
Started May 23 12:27:19 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 182432 kb
Host smart-91556c5b-3bdf-4c3d-ab9a-b5a0b0e51270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981094294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2981094294
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.549947471
Short name T99
Test name
Test status
Simulation time 21093725 ps
CPU time 0.85 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 194384 kb
Host smart-2f0d0ff4-9cd2-4d17-ae35-2266118c4d33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549947471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.549947471
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3431266543
Short name T499
Test name
Test status
Simulation time 58009339 ps
CPU time 1.32 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:22 PM PDT 24
Peak memory 197448 kb
Host smart-75319d67-9984-4ca9-a16e-ab5c6158b056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431266543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3431266543
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2974369943
Short name T113
Test name
Test status
Simulation time 165339430 ps
CPU time 0.81 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 193328 kb
Host smart-77c0b96d-f704-4b58-990b-72795c096aed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974369943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2974369943
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.696880676
Short name T520
Test name
Test status
Simulation time 50119905 ps
CPU time 0.77 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 195248 kb
Host smart-e49b69f7-2da0-4465-91a9-94e116b76b25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696880676 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.696880676
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1302504168
Short name T513
Test name
Test status
Simulation time 15026181 ps
CPU time 0.57 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 182560 kb
Host smart-67201a59-f66b-4edd-bf85-40d2e3426b45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302504168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1302504168
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4128723344
Short name T459
Test name
Test status
Simulation time 39383626 ps
CPU time 0.53 seconds
Started May 23 12:27:19 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 182404 kb
Host smart-758a8b3a-5fda-4bb0-a214-1d8f2c0b7647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128723344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4128723344
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2182640543
Short name T514
Test name
Test status
Simulation time 19628394 ps
CPU time 0.62 seconds
Started May 23 12:27:24 PM PDT 24
Finished May 23 12:27:27 PM PDT 24
Peak memory 191332 kb
Host smart-9a72468b-7058-4997-9f39-36195c216b45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182640543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2182640543
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3170051186
Short name T500
Test name
Test status
Simulation time 581837602 ps
CPU time 2.41 seconds
Started May 23 12:27:20 PM PDT 24
Finished May 23 12:27:26 PM PDT 24
Peak memory 197488 kb
Host smart-9af138cf-ba68-486e-9895-105be188d379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170051186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3170051186
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2049757006
Short name T524
Test name
Test status
Simulation time 331280776 ps
CPU time 1.37 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:24 PM PDT 24
Peak memory 194896 kb
Host smart-29f3258b-5c56-4a27-8086-baf00802ce95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049757006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2049757006
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2854289024
Short name T572
Test name
Test status
Simulation time 45202181 ps
CPU time 0.95 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:21 PM PDT 24
Peak memory 197040 kb
Host smart-2466bef0-28f2-45df-8fd5-07984e608373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854289024 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2854289024
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4207892866
Short name T536
Test name
Test status
Simulation time 35046135 ps
CPU time 0.54 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 182324 kb
Host smart-8d059dae-143e-44eb-b362-3dab97b4373d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207892866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.4207892866
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3135550663
Short name T479
Test name
Test status
Simulation time 17405056 ps
CPU time 0.52 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:26 PM PDT 24
Peak memory 181872 kb
Host smart-0b1474ee-0e8a-47dd-aacf-cbd0aad4e4c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135550663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3135550663
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3240806650
Short name T546
Test name
Test status
Simulation time 43329702 ps
CPU time 0.8 seconds
Started May 23 12:27:12 PM PDT 24
Finished May 23 12:27:17 PM PDT 24
Peak memory 193396 kb
Host smart-f60ab79c-4341-4fa9-81a6-468f730a0b9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240806650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3240806650
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1092990577
Short name T558
Test name
Test status
Simulation time 52718467 ps
CPU time 2.44 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 197488 kb
Host smart-1177f74c-cfcf-4562-a380-cce616a52b75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092990577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1092990577
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2530818686
Short name T563
Test name
Test status
Simulation time 49933580 ps
CPU time 0.8 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 193244 kb
Host smart-4281f0e6-fd83-4a24-806b-fa9645a36996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530818686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2530818686
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4121317243
Short name T507
Test name
Test status
Simulation time 54040478 ps
CPU time 0.62 seconds
Started May 23 12:27:19 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 193512 kb
Host smart-95707119-4a98-4599-9a9d-739a710a7cf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121317243 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4121317243
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1159842474
Short name T91
Test name
Test status
Simulation time 31736622 ps
CPU time 0.57 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:22 PM PDT 24
Peak memory 182556 kb
Host smart-75af643c-0ddf-4a3c-a727-8e571b73cba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159842474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1159842474
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1538408231
Short name T545
Test name
Test status
Simulation time 14796771 ps
CPU time 0.56 seconds
Started May 23 12:27:16 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 182504 kb
Host smart-8f6e1fc7-14e3-4032-b4b4-610cca6d944e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538408231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1538408231
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1126877977
Short name T493
Test name
Test status
Simulation time 48839450 ps
CPU time 0.75 seconds
Started May 23 12:27:26 PM PDT 24
Finished May 23 12:27:28 PM PDT 24
Peak memory 192128 kb
Host smart-ef530e0e-296f-4180-a1b8-2556cbeee430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126877977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1126877977
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.981197293
Short name T57
Test name
Test status
Simulation time 147381900 ps
CPU time 1.45 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:20 PM PDT 24
Peak memory 197428 kb
Host smart-3986df99-863f-44fa-ad91-34729a8772f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981197293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.981197293
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2882370051
Short name T502
Test name
Test status
Simulation time 126353406 ps
CPU time 1.1 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 194808 kb
Host smart-a0aa39a7-7b9b-4ffe-b1e0-704df256360a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882370051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2882370051
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.616585506
Short name T570
Test name
Test status
Simulation time 23732390 ps
CPU time 0.73 seconds
Started May 23 12:27:14 PM PDT 24
Finished May 23 12:27:18 PM PDT 24
Peak memory 195000 kb
Host smart-7375bfb1-d4ce-48f3-b2a8-1a6bc546ac7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616585506 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.616585506
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1968034828
Short name T93
Test name
Test status
Simulation time 12777673 ps
CPU time 0.63 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:22 PM PDT 24
Peak memory 182560 kb
Host smart-cf01d370-62f0-43e6-86f8-0a5e9fac86ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968034828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1968034828
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2919162697
Short name T485
Test name
Test status
Simulation time 18164842 ps
CPU time 0.57 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:21 PM PDT 24
Peak memory 182344 kb
Host smart-46daef5c-86f9-4c24-8690-746a92322793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919162697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2919162697
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2016167977
Short name T525
Test name
Test status
Simulation time 57126288 ps
CPU time 0.8 seconds
Started May 23 12:27:15 PM PDT 24
Finished May 23 12:27:19 PM PDT 24
Peak memory 191560 kb
Host smart-ebc4d2e7-e95e-4ec4-bbd5-d59082f562ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016167977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2016167977
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.204127450
Short name T463
Test name
Test status
Simulation time 99476869 ps
CPU time 2.62 seconds
Started May 23 12:27:17 PM PDT 24
Finished May 23 12:27:23 PM PDT 24
Peak memory 197452 kb
Host smart-13fff611-c9ad-4ad4-9d5e-9bbafc290293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204127450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.204127450
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.717666334
Short name T477
Test name
Test status
Simulation time 81302019 ps
CPU time 1.03 seconds
Started May 23 12:27:18 PM PDT 24
Finished May 23 12:27:22 PM PDT 24
Peak memory 194968 kb
Host smart-293aae78-1244-4db6-9531-bb753f33a4fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717666334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.717666334
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2485994440
Short name T394
Test name
Test status
Simulation time 1928256862108 ps
CPU time 465.65 seconds
Started May 23 12:27:45 PM PDT 24
Finished May 23 12:35:32 PM PDT 24
Peak memory 182476 kb
Host smart-9b20f095-3db2-4709-bd6f-169f60a968b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485994440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2485994440
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1583055272
Short name T421
Test name
Test status
Simulation time 132959140432 ps
CPU time 210.89 seconds
Started May 23 12:27:38 PM PDT 24
Finished May 23 12:31:13 PM PDT 24
Peak memory 182464 kb
Host smart-4eb65ab6-b377-4880-80d6-82d2703e1b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583055272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1583055272
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.4004055201
Short name T23
Test name
Test status
Simulation time 770295459822 ps
CPU time 720.89 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:39:55 PM PDT 24
Peak memory 182468 kb
Host smart-545f46b6-14db-4995-95c3-607d55a63278
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004055201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.4004055201
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3902145814
Short name T392
Test name
Test status
Simulation time 128085781914 ps
CPU time 116.97 seconds
Started May 23 12:27:29 PM PDT 24
Finished May 23 12:29:27 PM PDT 24
Peak memory 182408 kb
Host smart-51e288c3-dcbc-4b70-99fc-b98e351cb36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902145814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3902145814
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.280151979
Short name T15
Test name
Test status
Simulation time 61364153 ps
CPU time 0.82 seconds
Started May 23 12:27:35 PM PDT 24
Finished May 23 12:27:40 PM PDT 24
Peak memory 213540 kb
Host smart-0f5197c8-160e-4267-b159-291aaf6d33e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280151979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.280151979
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2172678957
Short name T59
Test name
Test status
Simulation time 508167917684 ps
CPU time 1181.45 seconds
Started May 23 12:27:39 PM PDT 24
Finished May 23 12:47:24 PM PDT 24
Peak memory 190656 kb
Host smart-fd5c50cc-ad85-4ee1-b1e0-bd9f1af62574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172678957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2172678957
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.345262313
Short name T12
Test name
Test status
Simulation time 175008528669 ps
CPU time 232.2 seconds
Started May 23 12:27:48 PM PDT 24
Finished May 23 12:31:42 PM PDT 24
Peak memory 197148 kb
Host smart-12d3d030-85b1-435f-9d5a-65a471dbeb3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345262313 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.345262313
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3056771056
Short name T104
Test name
Test status
Simulation time 388434625732 ps
CPU time 166.19 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:30:50 PM PDT 24
Peak memory 182476 kb
Host smart-f513cf7e-3df3-4cfa-9c33-dc03d08a7cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056771056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3056771056
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3067184901
Short name T435
Test name
Test status
Simulation time 114034763 ps
CPU time 1.36 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:28:01 PM PDT 24
Peak memory 181972 kb
Host smart-3c51b4e8-8731-4253-aeeb-5b3fd7b59a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067184901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3067184901
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/104.rv_timer_random.583195867
Short name T428
Test name
Test status
Simulation time 367615147026 ps
CPU time 139.97 seconds
Started May 23 12:28:13 PM PDT 24
Finished May 23 12:30:34 PM PDT 24
Peak memory 190652 kb
Host smart-48ed9a0f-12fa-4001-907f-2be7beb734f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583195867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.583195867
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3672899388
Short name T293
Test name
Test status
Simulation time 585252477069 ps
CPU time 1522.69 seconds
Started May 23 12:28:08 PM PDT 24
Finished May 23 12:53:32 PM PDT 24
Peak memory 190676 kb
Host smart-5689a9bb-28af-4e29-bf9f-f3d6fb3038a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672899388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3672899388
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1812149632
Short name T266
Test name
Test status
Simulation time 118931643031 ps
CPU time 154.5 seconds
Started May 23 12:28:12 PM PDT 24
Finished May 23 12:30:48 PM PDT 24
Peak memory 190672 kb
Host smart-2c680e64-5772-4a26-a742-e095d89c9ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812149632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1812149632
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2248604819
Short name T356
Test name
Test status
Simulation time 17721591872 ps
CPU time 57.84 seconds
Started May 23 12:28:20 PM PDT 24
Finished May 23 12:29:20 PM PDT 24
Peak memory 182448 kb
Host smart-32f519ba-1844-454b-822e-ec3db3bc8167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248604819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2248604819
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3569642133
Short name T431
Test name
Test status
Simulation time 953392588223 ps
CPU time 159.58 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:31:21 PM PDT 24
Peak memory 182468 kb
Host smart-022af0d6-d102-455d-be30-927c4cbd1d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569642133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3569642133
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2739471788
Short name T387
Test name
Test status
Simulation time 179524698973 ps
CPU time 70.79 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:29:13 PM PDT 24
Peak memory 182488 kb
Host smart-db4fc12e-78bb-4b59-a806-d3f780efa202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739471788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2739471788
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2322904330
Short name T437
Test name
Test status
Simulation time 433838953522 ps
CPU time 963.27 seconds
Started May 23 12:27:55 PM PDT 24
Finished May 23 12:44:07 PM PDT 24
Peak memory 194404 kb
Host smart-0c993052-93c1-445c-8f0e-2e9dfb49e8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322904330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2322904330
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2483910696
Short name T296
Test name
Test status
Simulation time 277047100672 ps
CPU time 111.99 seconds
Started May 23 12:28:17 PM PDT 24
Finished May 23 12:30:10 PM PDT 24
Peak memory 190672 kb
Host smart-d6b3d24b-7020-489f-9dc4-70c3fe157fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483910696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2483910696
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3817706301
Short name T433
Test name
Test status
Simulation time 133307759126 ps
CPU time 86.42 seconds
Started May 23 12:28:11 PM PDT 24
Finished May 23 12:29:39 PM PDT 24
Peak memory 182448 kb
Host smart-280a8f2d-4e7d-4235-9016-f608ae091e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817706301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3817706301
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.428716886
Short name T237
Test name
Test status
Simulation time 152057626004 ps
CPU time 624.76 seconds
Started May 23 12:28:23 PM PDT 24
Finished May 23 12:38:51 PM PDT 24
Peak memory 190696 kb
Host smart-b2756674-16ae-4579-b296-9f839589bc65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428716886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.428716886
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2542988627
Short name T320
Test name
Test status
Simulation time 4628174717 ps
CPU time 8.53 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:28:40 PM PDT 24
Peak memory 182472 kb
Host smart-6e9c63c2-4c37-443a-922d-f740ab87f2aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542988627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2542988627
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1701857770
Short name T77
Test name
Test status
Simulation time 77687617909 ps
CPU time 126.32 seconds
Started May 23 12:28:13 PM PDT 24
Finished May 23 12:30:20 PM PDT 24
Peak memory 190664 kb
Host smart-697f9350-b298-4b01-98b6-9f46639272e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701857770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1701857770
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2859327316
Short name T432
Test name
Test status
Simulation time 78369644558 ps
CPU time 111.36 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:30:28 PM PDT 24
Peak memory 190668 kb
Host smart-21f47949-03ed-4a9a-b9c3-9dad36efb882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859327316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2859327316
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2286811076
Short name T159
Test name
Test status
Simulation time 235238700109 ps
CPU time 449.06 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:36:03 PM PDT 24
Peak memory 190668 kb
Host smart-cd7dbc46-5297-4d9d-b72c-630054a23556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286811076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2286811076
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3242806719
Short name T131
Test name
Test status
Simulation time 1556706908965 ps
CPU time 766.98 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:40:49 PM PDT 24
Peak memory 182416 kb
Host smart-b3e7ca2f-626e-4782-a9da-4f28ba0e8b45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242806719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3242806719
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3641325553
Short name T423
Test name
Test status
Simulation time 9401121229 ps
CPU time 15.21 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:28:11 PM PDT 24
Peak memory 182488 kb
Host smart-1589f1ba-0322-46ee-becf-976af77717f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641325553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3641325553
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3446165131
Short name T145
Test name
Test status
Simulation time 60288233488 ps
CPU time 287.83 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:32:53 PM PDT 24
Peak memory 190816 kb
Host smart-ba974398-0589-472e-b4f2-1073643f01d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446165131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3446165131
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3959463526
Short name T411
Test name
Test status
Simulation time 155614335 ps
CPU time 1.39 seconds
Started May 23 12:28:19 PM PDT 24
Finished May 23 12:28:21 PM PDT 24
Peak memory 182392 kb
Host smart-280538df-89ac-4d51-8282-ea17c8cce9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959463526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3959463526
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1753920190
Short name T43
Test name
Test status
Simulation time 474545351453 ps
CPU time 321.17 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:33:58 PM PDT 24
Peak memory 190676 kb
Host smart-1433ec44-6306-4e2a-87d5-daceae67456c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753920190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1753920190
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2237583257
Short name T212
Test name
Test status
Simulation time 551052589279 ps
CPU time 76.35 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:29:54 PM PDT 24
Peak memory 182448 kb
Host smart-13732ebd-de38-4703-ba39-92dde5cda10a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237583257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2237583257
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3619031504
Short name T448
Test name
Test status
Simulation time 239107254022 ps
CPU time 259.28 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:32:55 PM PDT 24
Peak memory 190616 kb
Host smart-d11e0ba7-3624-414a-9008-b2c90c7d016b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619031504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3619031504
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3761707457
Short name T121
Test name
Test status
Simulation time 507135697755 ps
CPU time 787.57 seconds
Started May 23 12:28:40 PM PDT 24
Finished May 23 12:41:49 PM PDT 24
Peak memory 193164 kb
Host smart-b2ab84d0-51c8-4a78-b087-4f46052bdd5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761707457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3761707457
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.277473736
Short name T194
Test name
Test status
Simulation time 58202255248 ps
CPU time 451.19 seconds
Started May 23 12:28:48 PM PDT 24
Finished May 23 12:36:20 PM PDT 24
Peak memory 190664 kb
Host smart-6c2c524c-99c4-435d-8bd7-750e9134bae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277473736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.277473736
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1358065742
Short name T443
Test name
Test status
Simulation time 146610403071 ps
CPU time 690.47 seconds
Started May 23 12:28:41 PM PDT 24
Finished May 23 12:40:13 PM PDT 24
Peak memory 182424 kb
Host smart-f1bdc812-2968-4149-80d2-f6efd40dc0a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358065742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1358065742
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2939437511
Short name T294
Test name
Test status
Simulation time 391588814822 ps
CPU time 826.83 seconds
Started May 23 12:28:37 PM PDT 24
Finished May 23 12:42:26 PM PDT 24
Peak memory 190696 kb
Host smart-560c28ce-3e06-468b-ab7c-af6516c40338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939437511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2939437511
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2914607090
Short name T204
Test name
Test status
Simulation time 450644784867 ps
CPU time 110.54 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:30:25 PM PDT 24
Peak memory 190720 kb
Host smart-34143579-d1a1-4621-b425-8efb2cb48db4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914607090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2914607090
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2812327732
Short name T169
Test name
Test status
Simulation time 91387135688 ps
CPU time 147.45 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:30:28 PM PDT 24
Peak memory 182428 kb
Host smart-45790925-e69d-47e5-839c-b49597ca5a1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812327732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2812327732
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1174956179
Short name T78
Test name
Test status
Simulation time 37642515797 ps
CPU time 57.28 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:29:00 PM PDT 24
Peak memory 182476 kb
Host smart-5774a76e-4e29-4a92-a489-175de332af85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174956179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1174956179
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1285714263
Short name T424
Test name
Test status
Simulation time 1341281924 ps
CPU time 2.59 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:28:03 PM PDT 24
Peak memory 194124 kb
Host smart-d5b5a2cf-99a8-40e0-a8d0-501e9d20f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285714263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1285714263
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.766431052
Short name T407
Test name
Test status
Simulation time 29881197284 ps
CPU time 52.57 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:29:34 PM PDT 24
Peak memory 190640 kb
Host smart-af6815d9-b600-46e6-bf17-87fd4996307b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766431052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.766431052
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2785219181
Short name T130
Test name
Test status
Simulation time 527008049131 ps
CPU time 278.88 seconds
Started May 23 12:28:25 PM PDT 24
Finished May 23 12:33:08 PM PDT 24
Peak memory 190612 kb
Host smart-80e5074a-f7ae-4b0c-b814-cf5207fac9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785219181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2785219181
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2118922243
Short name T198
Test name
Test status
Simulation time 18987929116 ps
CPU time 133.74 seconds
Started May 23 12:28:28 PM PDT 24
Finished May 23 12:30:44 PM PDT 24
Peak memory 190636 kb
Host smart-4094d5c6-b2e8-4fcf-bb88-de12cc33eec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118922243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2118922243
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3699024875
Short name T188
Test name
Test status
Simulation time 501721297362 ps
CPU time 306.29 seconds
Started May 23 12:28:27 PM PDT 24
Finished May 23 12:33:36 PM PDT 24
Peak memory 190600 kb
Host smart-2ad4cf2c-72f6-4f58-8420-298632750880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699024875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3699024875
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.978959436
Short name T445
Test name
Test status
Simulation time 63619643089 ps
CPU time 55.85 seconds
Started May 23 12:28:31 PM PDT 24
Finished May 23 12:29:29 PM PDT 24
Peak memory 182456 kb
Host smart-09f8e7ff-bfcf-4e1b-95f7-484bd38dfdaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978959436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.978959436
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.859316977
Short name T284
Test name
Test status
Simulation time 68544836791 ps
CPU time 109.84 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:30:30 PM PDT 24
Peak memory 190624 kb
Host smart-48b92a63-95c7-46d7-980a-7678f0f8a98a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859316977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.859316977
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3756490186
Short name T71
Test name
Test status
Simulation time 442644866244 ps
CPU time 270.18 seconds
Started May 23 12:28:26 PM PDT 24
Finished May 23 12:33:00 PM PDT 24
Peak memory 190640 kb
Host smart-f1a78b50-a7da-4087-b597-9d698f243665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756490186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3756490186
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.261318627
Short name T275
Test name
Test status
Simulation time 429174963274 ps
CPU time 426.77 seconds
Started May 23 12:28:35 PM PDT 24
Finished May 23 12:35:44 PM PDT 24
Peak memory 190668 kb
Host smart-b5c81e47-00f5-45d0-b768-f508b84ee2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261318627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.261318627
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3793861678
Short name T309
Test name
Test status
Simulation time 10524471991 ps
CPU time 17.7 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:28:11 PM PDT 24
Peak memory 182580 kb
Host smart-71d9faf9-fba5-47d3-8825-06d154460169
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793861678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3793861678
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3579888234
Short name T401
Test name
Test status
Simulation time 180421014990 ps
CPU time 257.99 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:32:17 PM PDT 24
Peak memory 182492 kb
Host smart-7356ae2c-a21e-45e7-8378-3693520ff7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579888234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3579888234
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.803258098
Short name T142
Test name
Test status
Simulation time 58207859751 ps
CPU time 92.26 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:29:38 PM PDT 24
Peak memory 190728 kb
Host smart-a7051fa8-57e5-44e0-8379-e3ef1e8b78f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803258098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.803258098
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.2111489038
Short name T84
Test name
Test status
Simulation time 336490565691 ps
CPU time 194.13 seconds
Started May 23 12:28:35 PM PDT 24
Finished May 23 12:31:52 PM PDT 24
Peak memory 190616 kb
Host smart-d2dbae45-8a35-43fb-8aed-9e5ec890881c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111489038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2111489038
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3294620353
Short name T280
Test name
Test status
Simulation time 152723534159 ps
CPU time 258.58 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:32:54 PM PDT 24
Peak memory 190696 kb
Host smart-3870b49c-c0e6-41c6-9b9f-74ed0a88f4a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294620353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3294620353
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1044563139
Short name T352
Test name
Test status
Simulation time 167666982915 ps
CPU time 158.92 seconds
Started May 23 12:28:25 PM PDT 24
Finished May 23 12:31:11 PM PDT 24
Peak memory 190648 kb
Host smart-8ca9ee30-2126-4e82-9d45-18a0d7ebf2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044563139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1044563139
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3715714800
Short name T168
Test name
Test status
Simulation time 652943649321 ps
CPU time 437.5 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:35:54 PM PDT 24
Peak memory 190796 kb
Host smart-5e7da541-306f-4b0a-ab7c-0a9465be46b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715714800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3715714800
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.73777095
Short name T225
Test name
Test status
Simulation time 118931767356 ps
CPU time 406.27 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:35:22 PM PDT 24
Peak memory 190636 kb
Host smart-8b9b538f-8ddc-4f93-b292-f8f3f1ebbaa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73777095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.73777095
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2001486322
Short name T271
Test name
Test status
Simulation time 339199821863 ps
CPU time 643.08 seconds
Started May 23 12:28:37 PM PDT 24
Finished May 23 12:39:23 PM PDT 24
Peak memory 194112 kb
Host smart-cff7e956-6d70-4a29-8954-c8ef4d773197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001486322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2001486322
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1317663166
Short name T218
Test name
Test status
Simulation time 298922694174 ps
CPU time 194.99 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 193116 kb
Host smart-ca64d39b-85a5-4c39-ae09-955fe81bdadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317663166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1317663166
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2470849581
Short name T252
Test name
Test status
Simulation time 268292611544 ps
CPU time 238.68 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:32:33 PM PDT 24
Peak memory 190676 kb
Host smart-c49ecf92-c78c-4724-8781-50ba23dd035b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470849581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2470849581
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.713909879
Short name T367
Test name
Test status
Simulation time 145837964861 ps
CPU time 52.43 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:28:56 PM PDT 24
Peak memory 182476 kb
Host smart-e7a213a9-9e59-4363-83c9-efa4349ed403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713909879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.713909879
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3633106638
Short name T268
Test name
Test status
Simulation time 141635881029 ps
CPU time 309.99 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:33:14 PM PDT 24
Peak memory 190688 kb
Host smart-9fedc98a-4e24-44a4-a4b3-58dcf7a63e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633106638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3633106638
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2646272574
Short name T361
Test name
Test status
Simulation time 23100498 ps
CPU time 0.57 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:27:56 PM PDT 24
Peak memory 182192 kb
Host smart-5cff4937-ecf2-48fd-b082-23c48a49cad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646272574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2646272574
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.2765754735
Short name T390
Test name
Test status
Simulation time 43691163726 ps
CPU time 43.69 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:29:20 PM PDT 24
Peak memory 182544 kb
Host smart-84eb1c2c-8f55-454d-8d4f-43b67004af4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765754735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2765754735
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1228302153
Short name T192
Test name
Test status
Simulation time 87329255464 ps
CPU time 454.84 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:36:11 PM PDT 24
Peak memory 182468 kb
Host smart-a8978893-c422-4a0b-8995-65cbc6026e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228302153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1228302153
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2026656713
Short name T310
Test name
Test status
Simulation time 291656612539 ps
CPU time 685.03 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:39:59 PM PDT 24
Peak memory 190656 kb
Host smart-c7341358-7089-49bb-81c9-94dc3a7ca8fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026656713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2026656713
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2733066874
Short name T404
Test name
Test status
Simulation time 88125022517 ps
CPU time 85.31 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:30:02 PM PDT 24
Peak memory 182468 kb
Host smart-7e957f16-6332-4f26-8ea6-3031f60905e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733066874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2733066874
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2383394005
Short name T345
Test name
Test status
Simulation time 149999212754 ps
CPU time 143.73 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:30:23 PM PDT 24
Peak memory 182432 kb
Host smart-148797c5-fef7-4ebc-8d56-8d4fbb00293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383394005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2383394005
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1578979813
Short name T256
Test name
Test status
Simulation time 99835829065 ps
CPU time 432.81 seconds
Started May 23 12:28:00 PM PDT 24
Finished May 23 12:35:16 PM PDT 24
Peak memory 190900 kb
Host smart-2f5c7dad-a5dc-477a-b9fa-acd184810a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578979813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1578979813
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.3342889261
Short name T235
Test name
Test status
Simulation time 137373611353 ps
CPU time 920.22 seconds
Started May 23 12:28:25 PM PDT 24
Finished May 23 12:43:49 PM PDT 24
Peak memory 190728 kb
Host smart-27d5a9a2-b245-42c3-bf7b-243831143bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342889261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3342889261
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3839976223
Short name T267
Test name
Test status
Simulation time 275582094845 ps
CPU time 154.78 seconds
Started May 23 12:28:37 PM PDT 24
Finished May 23 12:31:14 PM PDT 24
Peak memory 190728 kb
Host smart-00d9a772-575c-42cb-964a-79b3c35db8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839976223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3839976223
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2069157573
Short name T137
Test name
Test status
Simulation time 790821430249 ps
CPU time 554.92 seconds
Started May 23 12:28:37 PM PDT 24
Finished May 23 12:37:54 PM PDT 24
Peak memory 190652 kb
Host smart-193e5b5d-c76b-48a6-97c2-ccce0c73f1b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069157573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2069157573
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3455181887
Short name T28
Test name
Test status
Simulation time 112860459716 ps
CPU time 212.25 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:32:04 PM PDT 24
Peak memory 190660 kb
Host smart-289e34ff-49ed-479b-92db-371e21f546fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455181887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3455181887
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3248083083
Short name T24
Test name
Test status
Simulation time 62075074749 ps
CPU time 177.84 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:31:39 PM PDT 24
Peak memory 190664 kb
Host smart-a59c9997-c711-447f-a874-09e39e4435aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248083083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3248083083
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2582082186
Short name T228
Test name
Test status
Simulation time 276533409243 ps
CPU time 280.11 seconds
Started May 23 12:28:36 PM PDT 24
Finished May 23 12:33:19 PM PDT 24
Peak memory 190652 kb
Host smart-3b6d429b-63d5-4a51-96ae-aa055303d45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582082186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2582082186
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.357407826
Short name T329
Test name
Test status
Simulation time 73975555162 ps
CPU time 129.25 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:30:45 PM PDT 24
Peak memory 190712 kb
Host smart-08842448-f454-4488-af41-9d00a3c04963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357407826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.357407826
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3471404900
Short name T72
Test name
Test status
Simulation time 1612372461271 ps
CPU time 773 seconds
Started May 23 12:28:41 PM PDT 24
Finished May 23 12:41:36 PM PDT 24
Peak memory 193224 kb
Host smart-9e8c8f2c-d1f8-49dc-b1a3-9cf0db292c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471404900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3471404900
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3726917265
Short name T231
Test name
Test status
Simulation time 126755521175 ps
CPU time 1068.19 seconds
Started May 23 12:28:25 PM PDT 24
Finished May 23 12:46:17 PM PDT 24
Peak memory 190660 kb
Host smart-d0fdc93f-f6ae-410b-b32e-b3ceb366da9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726917265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3726917265
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1109921020
Short name T328
Test name
Test status
Simulation time 30167895928 ps
CPU time 47.39 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:29:25 PM PDT 24
Peak memory 182424 kb
Host smart-71c246dc-d49d-4e69-b450-9ac29851713e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109921020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1109921020
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1603745811
Short name T397
Test name
Test status
Simulation time 121415125701 ps
CPU time 195.41 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:31:15 PM PDT 24
Peak memory 182520 kb
Host smart-367ef2ac-6860-49e9-bf8e-4d15b970d72c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603745811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1603745811
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.4174705360
Short name T107
Test name
Test status
Simulation time 175675007064 ps
CPU time 73.67 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:29:06 PM PDT 24
Peak memory 182456 kb
Host smart-1507b0c2-90d1-4485-a08f-62567749c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174705360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.4174705360
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2189535449
Short name T68
Test name
Test status
Simulation time 166093506413 ps
CPU time 244.24 seconds
Started May 23 12:27:55 PM PDT 24
Finished May 23 12:32:01 PM PDT 24
Peak memory 193252 kb
Host smart-31036846-80a6-4382-99c1-0e05156b2618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189535449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2189535449
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.817496069
Short name T240
Test name
Test status
Simulation time 95446458718 ps
CPU time 91.89 seconds
Started May 23 12:27:55 PM PDT 24
Finished May 23 12:29:29 PM PDT 24
Peak memory 190652 kb
Host smart-5cd278f4-2904-420a-a907-a17b666c96ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817496069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.817496069
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3329945578
Short name T65
Test name
Test status
Simulation time 50455198014 ps
CPU time 69.02 seconds
Started May 23 12:27:55 PM PDT 24
Finished May 23 12:29:06 PM PDT 24
Peak memory 192900 kb
Host smart-fb3d0826-dc73-4f17-9e9a-b9b151402637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329945578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3329945578
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.604865708
Short name T245
Test name
Test status
Simulation time 21843739962 ps
CPU time 89.6 seconds
Started May 23 12:28:44 PM PDT 24
Finished May 23 12:30:15 PM PDT 24
Peak memory 190676 kb
Host smart-56114b2b-e4b6-41b6-b625-a75e992fb030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604865708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.604865708
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2421594944
Short name T41
Test name
Test status
Simulation time 382736330533 ps
CPU time 1745.3 seconds
Started May 23 12:28:43 PM PDT 24
Finished May 23 12:57:49 PM PDT 24
Peak memory 190652 kb
Host smart-4343f7ed-bfeb-4043-af77-428e985caa03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421594944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2421594944
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1091542202
Short name T5
Test name
Test status
Simulation time 107599650324 ps
CPU time 70.49 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:29:45 PM PDT 24
Peak memory 190672 kb
Host smart-104c1e53-0446-4735-81ef-357632dfbae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091542202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1091542202
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2870654278
Short name T251
Test name
Test status
Simulation time 24733809355 ps
CPU time 39.4 seconds
Started May 23 12:28:38 PM PDT 24
Finished May 23 12:29:20 PM PDT 24
Peak memory 190716 kb
Host smart-cbe8aee8-324a-4a21-97ab-d2ea72dfb71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870654278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2870654278
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3627360703
Short name T150
Test name
Test status
Simulation time 204161052777 ps
CPU time 976.43 seconds
Started May 23 12:28:31 PM PDT 24
Finished May 23 12:44:50 PM PDT 24
Peak memory 190808 kb
Host smart-dc630ce8-4037-4df8-86f5-36f3adf51f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627360703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3627360703
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1407106913
Short name T277
Test name
Test status
Simulation time 245062562327 ps
CPU time 115.74 seconds
Started May 23 12:28:30 PM PDT 24
Finished May 23 12:30:28 PM PDT 24
Peak memory 190640 kb
Host smart-e9773c6f-c0bd-4a95-8990-320e8e67190f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407106913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1407106913
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.706323748
Short name T302
Test name
Test status
Simulation time 302160462942 ps
CPU time 160.49 seconds
Started May 23 12:28:42 PM PDT 24
Finished May 23 12:31:24 PM PDT 24
Peak memory 190704 kb
Host smart-519ef1ae-68ec-4601-838b-1d4eed347f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706323748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.706323748
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.228332193
Short name T20
Test name
Test status
Simulation time 106286428025 ps
CPU time 84.52 seconds
Started May 23 12:28:17 PM PDT 24
Finished May 23 12:29:42 PM PDT 24
Peak memory 182488 kb
Host smart-ffc32666-7b57-4079-ae55-35cbe5fbeb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228332193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.228332193
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3184586402
Short name T176
Test name
Test status
Simulation time 77472666620 ps
CPU time 175.18 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:30:50 PM PDT 24
Peak memory 190664 kb
Host smart-51a6a4d9-df6b-473c-b763-2efc22a05aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184586402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3184586402
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2711336009
Short name T143
Test name
Test status
Simulation time 260712858737 ps
CPU time 315.31 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:33:11 PM PDT 24
Peak memory 190736 kb
Host smart-eececbf1-0021-45d1-a273-4654c82837a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711336009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2711336009
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3903007222
Short name T66
Test name
Test status
Simulation time 94648764530 ps
CPU time 45.26 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:28:41 PM PDT 24
Peak memory 182488 kb
Host smart-b17a22ed-8415-4793-8cc4-a8f0ebe20290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903007222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3903007222
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.1416697660
Short name T146
Test name
Test status
Simulation time 477710204259 ps
CPU time 262.72 seconds
Started May 23 12:28:47 PM PDT 24
Finished May 23 12:33:11 PM PDT 24
Peak memory 193168 kb
Host smart-67ffa099-2a1e-4082-847d-a7064443920b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416697660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1416697660
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1109280367
Short name T160
Test name
Test status
Simulation time 2648438291 ps
CPU time 19.16 seconds
Started May 23 12:28:26 PM PDT 24
Finished May 23 12:28:49 PM PDT 24
Peak memory 182452 kb
Host smart-89f866c8-fad2-4e0d-bacd-21223707554b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109280367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1109280367
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1162967078
Short name T337
Test name
Test status
Simulation time 111260542615 ps
CPU time 178.23 seconds
Started May 23 12:28:42 PM PDT 24
Finished May 23 12:31:42 PM PDT 24
Peak memory 190704 kb
Host smart-e3ab06eb-8564-4b2f-9aab-46d1e8edec46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162967078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1162967078
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2421625086
Short name T274
Test name
Test status
Simulation time 96168857513 ps
CPU time 571.7 seconds
Started May 23 12:28:26 PM PDT 24
Finished May 23 12:38:01 PM PDT 24
Peak memory 190644 kb
Host smart-abeb4374-2923-45ae-98fb-e3c144e5fdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421625086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2421625086
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1580691512
Short name T264
Test name
Test status
Simulation time 105109903236 ps
CPU time 39.93 seconds
Started May 23 12:28:40 PM PDT 24
Finished May 23 12:29:22 PM PDT 24
Peak memory 182596 kb
Host smart-cc8d11cc-4c6f-4518-8b49-b74cfa7324c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580691512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1580691512
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2141017108
Short name T215
Test name
Test status
Simulation time 82965230935 ps
CPU time 119.1 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:30:36 PM PDT 24
Peak memory 193688 kb
Host smart-4b00ce8b-2e3e-404d-8357-3278e10ea277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141017108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2141017108
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3914522825
Short name T171
Test name
Test status
Simulation time 725997221008 ps
CPU time 469.9 seconds
Started May 23 12:28:35 PM PDT 24
Finished May 23 12:36:28 PM PDT 24
Peak memory 190676 kb
Host smart-08a419a5-d557-477f-902f-c84a05cc7453
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914522825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3914522825
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2979714725
Short name T314
Test name
Test status
Simulation time 826880851097 ps
CPU time 775.85 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:40:50 PM PDT 24
Peak memory 182476 kb
Host smart-f6f5e620-eae3-48c4-8bcf-92df444d11a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979714725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2979714725
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2358763796
Short name T402
Test name
Test status
Simulation time 529958298458 ps
CPU time 173.77 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:30:56 PM PDT 24
Peak memory 182464 kb
Host smart-e7ccbd11-762a-4404-b407-ceafa76c2328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358763796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2358763796
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3747906278
Short name T415
Test name
Test status
Simulation time 101983326 ps
CPU time 0.7 seconds
Started May 23 12:27:55 PM PDT 24
Finished May 23 12:27:58 PM PDT 24
Peak memory 182192 kb
Host smart-35165b80-a725-45ce-9dd9-ceb1360156d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747906278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3747906278
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.4216165300
Short name T139
Test name
Test status
Simulation time 509087578107 ps
CPU time 360.97 seconds
Started May 23 12:28:51 PM PDT 24
Finished May 23 12:34:52 PM PDT 24
Peak memory 193192 kb
Host smart-5c625801-e503-46ac-b80e-2eb5cc97c893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216165300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4216165300
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2573571340
Short name T165
Test name
Test status
Simulation time 66544479465 ps
CPU time 104.83 seconds
Started May 23 12:28:37 PM PDT 24
Finished May 23 12:30:24 PM PDT 24
Peak memory 190676 kb
Host smart-c43d9531-c2a5-4b37-9a4d-99510d22c86b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573571340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2573571340
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2118038340
Short name T241
Test name
Test status
Simulation time 78078331058 ps
CPU time 133.51 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:30:49 PM PDT 24
Peak memory 190784 kb
Host smart-22dee98c-6b18-4b80-bf10-519e9ef3fe9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118038340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2118038340
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1677735060
Short name T279
Test name
Test status
Simulation time 128481015248 ps
CPU time 1611.14 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:55:23 PM PDT 24
Peak memory 190676 kb
Host smart-6491dd83-03f0-478b-b29a-5e096edc5e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677735060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1677735060
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1362029082
Short name T385
Test name
Test status
Simulation time 23874207838 ps
CPU time 626.08 seconds
Started May 23 12:28:49 PM PDT 24
Finished May 23 12:39:16 PM PDT 24
Peak memory 182248 kb
Host smart-9a88fc89-7ee3-4213-a5db-151c8ea153fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362029082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1362029082
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3856362345
Short name T308
Test name
Test status
Simulation time 72926248267 ps
CPU time 128.66 seconds
Started May 23 12:28:49 PM PDT 24
Finished May 23 12:30:59 PM PDT 24
Peak memory 190432 kb
Host smart-f62e5846-5ad3-4f8f-b47c-001942ed252e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856362345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3856362345
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1737202953
Short name T414
Test name
Test status
Simulation time 196893991791 ps
CPU time 320.06 seconds
Started May 23 12:27:29 PM PDT 24
Finished May 23 12:32:51 PM PDT 24
Peak memory 182464 kb
Host smart-d3825a56-c891-454f-ae28-530833eec76f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737202953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1737202953
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3032021592
Short name T368
Test name
Test status
Simulation time 117362005241 ps
CPU time 171 seconds
Started May 23 12:27:50 PM PDT 24
Finished May 23 12:30:42 PM PDT 24
Peak memory 182488 kb
Host smart-26c929a9-0559-439b-be77-11afc6e0a8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032021592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3032021592
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1653755012
Short name T418
Test name
Test status
Simulation time 206138033015 ps
CPU time 1418.43 seconds
Started May 23 12:27:34 PM PDT 24
Finished May 23 12:51:17 PM PDT 24
Peak memory 190704 kb
Host smart-d0fb8772-aa2b-4682-9f49-b80689d87730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653755012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1653755012
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3370064060
Short name T129
Test name
Test status
Simulation time 535352354 ps
CPU time 2.41 seconds
Started May 23 12:27:41 PM PDT 24
Finished May 23 12:27:47 PM PDT 24
Peak memory 190620 kb
Host smart-77570069-be0e-4461-951a-52b413ff35ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370064060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3370064060
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4071991811
Short name T19
Test name
Test status
Simulation time 65746864 ps
CPU time 0.75 seconds
Started May 23 12:27:40 PM PDT 24
Finished May 23 12:27:44 PM PDT 24
Peak memory 212844 kb
Host smart-04f165ab-ef0c-4933-90bc-acd8bc90e2b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071991811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4071991811
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2864650420
Short name T187
Test name
Test status
Simulation time 299285565919 ps
CPU time 667.61 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:39:12 PM PDT 24
Peak memory 190672 kb
Host smart-1cce8344-013d-4b2a-879d-eefa20e08b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864650420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2864650420
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2694391196
Short name T272
Test name
Test status
Simulation time 1088173763824 ps
CPU time 603.88 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:38:05 PM PDT 24
Peak memory 182424 kb
Host smart-c7a9b8ae-b53c-40d9-8f18-bf90f9ecf0cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694391196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2694391196
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1036644034
Short name T403
Test name
Test status
Simulation time 488798500925 ps
CPU time 103.82 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:29:52 PM PDT 24
Peak memory 182416 kb
Host smart-11b50645-9287-48c9-ab42-f205f34693b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036644034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1036644034
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3646209330
Short name T346
Test name
Test status
Simulation time 941176528112 ps
CPU time 198.73 seconds
Started May 23 12:28:00 PM PDT 24
Finished May 23 12:31:21 PM PDT 24
Peak memory 190648 kb
Host smart-8ed9140a-cf99-4a5a-aee1-184d2e0b8e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646209330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3646209330
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1708130106
Short name T444
Test name
Test status
Simulation time 109809212 ps
CPU time 0.54 seconds
Started May 23 12:27:56 PM PDT 24
Finished May 23 12:27:58 PM PDT 24
Peak memory 182204 kb
Host smart-d88b92fb-8b4f-4fec-9b34-3354ed505db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708130106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1708130106
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3207101032
Short name T193
Test name
Test status
Simulation time 713029445666 ps
CPU time 378.36 seconds
Started May 23 12:27:50 PM PDT 24
Finished May 23 12:34:10 PM PDT 24
Peak memory 182480 kb
Host smart-8dce506e-d742-42e3-a80d-f222876ae9bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207101032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3207101032
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.336461057
Short name T406
Test name
Test status
Simulation time 40597308195 ps
CPU time 18.38 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:28:13 PM PDT 24
Peak memory 182476 kb
Host smart-21fbbce7-3ba3-4ba9-b87d-46461e0cf492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336461057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.336461057
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.4185512959
Short name T147
Test name
Test status
Simulation time 6354697657 ps
CPU time 10.27 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:28:11 PM PDT 24
Peak memory 182408 kb
Host smart-9e1c61ef-5939-4b80-aedf-707b07f9f7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185512959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.4185512959
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.967143309
Short name T254
Test name
Test status
Simulation time 158314095569 ps
CPU time 74.11 seconds
Started May 23 12:28:05 PM PDT 24
Finished May 23 12:29:21 PM PDT 24
Peak memory 193756 kb
Host smart-ffcea0cd-054a-4579-9bac-0edc7ff05b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967143309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.967143309
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.956275952
Short name T434
Test name
Test status
Simulation time 444181092268 ps
CPU time 182.54 seconds
Started May 23 12:28:00 PM PDT 24
Finished May 23 12:31:06 PM PDT 24
Peak memory 190608 kb
Host smart-9d477d78-7fae-4aa6-a0c0-3275f35e055d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956275952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
956275952
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.351221983
Short name T230
Test name
Test status
Simulation time 445377544412 ps
CPU time 339.12 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:33:44 PM PDT 24
Peak memory 182488 kb
Host smart-4610bc3f-e5f0-47fe-9dbf-59849750be05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351221983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.351221983
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1083256912
Short name T426
Test name
Test status
Simulation time 252876566789 ps
CPU time 202.6 seconds
Started May 23 12:28:00 PM PDT 24
Finished May 23 12:31:26 PM PDT 24
Peak memory 182488 kb
Host smart-9d17e8da-871b-4340-a185-8eabc7274bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083256912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1083256912
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.231920032
Short name T224
Test name
Test status
Simulation time 648189157811 ps
CPU time 146.27 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:30:26 PM PDT 24
Peak memory 192924 kb
Host smart-569587a8-1d2b-4368-bd8b-b89f3df9016f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231920032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.231920032
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3960632731
Short name T416
Test name
Test status
Simulation time 6238589019 ps
CPU time 3.81 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:28:06 PM PDT 24
Peak memory 182520 kb
Host smart-83dd51ce-c100-4af2-8902-d1dd8ea9dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960632731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3960632731
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1059378644
Short name T222
Test name
Test status
Simulation time 200050426961 ps
CPU time 186.83 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:31:15 PM PDT 24
Peak memory 182500 kb
Host smart-87ea4800-6752-47a1-9219-e7d13785db43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059378644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1059378644
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.395517355
Short name T83
Test name
Test status
Simulation time 128643150618 ps
CPU time 53.52 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:28:49 PM PDT 24
Peak memory 182516 kb
Host smart-ae1d6f99-cad0-4e5c-b47b-30423137b4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395517355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.395517355
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2605258204
Short name T226
Test name
Test status
Simulation time 52978308270 ps
CPU time 79.7 seconds
Started May 23 12:28:11 PM PDT 24
Finished May 23 12:29:31 PM PDT 24
Peak memory 190672 kb
Host smart-64a1bfcd-cb3e-4a29-bf29-b315e6a388a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605258204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2605258204
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.803024435
Short name T70
Test name
Test status
Simulation time 236353961227 ps
CPU time 543.79 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:37:05 PM PDT 24
Peak memory 190720 kb
Host smart-7dcc8501-e2fd-4038-abc5-c38eb01c4876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803024435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
803024435
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1058465446
Short name T191
Test name
Test status
Simulation time 204674931233 ps
CPU time 337.17 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:33:32 PM PDT 24
Peak memory 182500 kb
Host smart-66f5153f-2072-46ff-ab13-f40764f30caa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058465446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1058465446
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3657320861
Short name T389
Test name
Test status
Simulation time 113856324449 ps
CPU time 148.71 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:30:24 PM PDT 24
Peak memory 182476 kb
Host smart-2425ff6b-e411-41ce-868d-3df0f1d41782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657320861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3657320861
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.4067923356
Short name T243
Test name
Test status
Simulation time 152938984224 ps
CPU time 95.12 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:29:37 PM PDT 24
Peak memory 182500 kb
Host smart-c1d7437b-4916-4975-81af-f9b780ca0d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067923356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4067923356
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1165761844
Short name T413
Test name
Test status
Simulation time 451152709678 ps
CPU time 381.49 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:34:23 PM PDT 24
Peak memory 190896 kb
Host smart-752879f7-3731-42a8-b44b-e03039040b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165761844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1165761844
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.394589536
Short name T386
Test name
Test status
Simulation time 237557634674 ps
CPU time 165.08 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:30:50 PM PDT 24
Peak memory 182488 kb
Host smart-dece5cf6-c318-4828-937c-3b1361d3601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394589536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.394589536
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1317055260
Short name T1
Test name
Test status
Simulation time 87014712167 ps
CPU time 71.69 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:29:12 PM PDT 24
Peak memory 182680 kb
Host smart-3b31eefb-34d3-4820-a6ba-cad0555441df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317055260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1317055260
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1888061867
Short name T221
Test name
Test status
Simulation time 307412188825 ps
CPU time 1094.25 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:46:20 PM PDT 24
Peak memory 194648 kb
Host smart-c671fcc4-0e3f-443a-a539-127ec89b34a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888061867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1888061867
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2836025785
Short name T63
Test name
Test status
Simulation time 458999396443 ps
CPU time 971.11 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:44:14 PM PDT 24
Peak memory 190568 kb
Host smart-0f4eb255-0fc6-4acd-98ab-66df5b206a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836025785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2836025785
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3036088498
Short name T347
Test name
Test status
Simulation time 62957454480 ps
CPU time 103.76 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:29:39 PM PDT 24
Peak memory 182488 kb
Host smart-d6e73129-294b-4847-9f79-6397e3082ff7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036088498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3036088498
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2518276336
Short name T371
Test name
Test status
Simulation time 37676660389 ps
CPU time 58.49 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:28:55 PM PDT 24
Peak memory 182468 kb
Host smart-77ee756e-ea2e-4779-96cb-973fa6ba3ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518276336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2518276336
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2738297265
Short name T161
Test name
Test status
Simulation time 8827261824 ps
CPU time 32.59 seconds
Started May 23 12:27:50 PM PDT 24
Finished May 23 12:28:24 PM PDT 24
Peak memory 190668 kb
Host smart-e52b607e-a12b-41bf-b836-de9ef0bcfd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738297265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2738297265
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.502385112
Short name T22
Test name
Test status
Simulation time 686462295454 ps
CPU time 153.65 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:30:37 PM PDT 24
Peak memory 182452 kb
Host smart-7db68a6a-8aec-4bfd-a6b1-b195f5bc3e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502385112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
502385112
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.26317333
Short name T375
Test name
Test status
Simulation time 178610779988 ps
CPU time 133.67 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:30:10 PM PDT 24
Peak memory 182492 kb
Host smart-76db0b15-80af-4f26-9055-d4a24c8d5249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26317333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.26317333
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2038243136
Short name T430
Test name
Test status
Simulation time 9113957004 ps
CPU time 11.07 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:28:06 PM PDT 24
Peak memory 182428 kb
Host smart-634a0be2-732a-47b3-bc11-96afd2d53b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038243136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2038243136
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2570822600
Short name T440
Test name
Test status
Simulation time 300311009603 ps
CPU time 142.81 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:30:24 PM PDT 24
Peak memory 193300 kb
Host smart-fb2b084c-8eea-4528-816c-87527a0e63f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570822600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2570822600
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2393296136
Short name T380
Test name
Test status
Simulation time 1594227591255 ps
CPU time 831.65 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:41:56 PM PDT 24
Peak memory 182436 kb
Host smart-fd147fb3-b342-4787-84a0-9577109bc811
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393296136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2393296136
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1342489012
Short name T396
Test name
Test status
Simulation time 151136549138 ps
CPU time 207.19 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:31:22 PM PDT 24
Peak memory 182268 kb
Host smart-ddcc6e16-d018-431b-b401-013368ca0bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342489012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1342489012
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3883002179
Short name T122
Test name
Test status
Simulation time 174961928179 ps
CPU time 457.28 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:35:40 PM PDT 24
Peak memory 190644 kb
Host smart-db699176-80a0-4b8e-8df6-1d1eb58ebe7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883002179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3883002179
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1320701718
Short name T388
Test name
Test status
Simulation time 29931170506 ps
CPU time 3.81 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:28:03 PM PDT 24
Peak memory 182256 kb
Host smart-8c3c2c41-6ad2-48d0-a1c0-f1936d1625fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320701718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1320701718
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.3418475404
Short name T35
Test name
Test status
Simulation time 50621049179 ps
CPU time 379.37 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:34:12 PM PDT 24
Peak memory 197076 kb
Host smart-fe18bbee-5856-4a75-b46d-fc8576087816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418475404 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.3418475404
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.4231838652
Short name T441
Test name
Test status
Simulation time 68681764584 ps
CPU time 94.56 seconds
Started May 23 12:27:55 PM PDT 24
Finished May 23 12:29:32 PM PDT 24
Peak memory 182476 kb
Host smart-55d18047-149d-4619-9058-556473ae9b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231838652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4231838652
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2593174005
Short name T81
Test name
Test status
Simulation time 68018557272 ps
CPU time 85.89 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:29:28 PM PDT 24
Peak memory 194624 kb
Host smart-aa886299-c0f2-475d-87bf-86f95b085a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593174005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2593174005
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2873331518
Short name T108
Test name
Test status
Simulation time 169612983774 ps
CPU time 591.63 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:37:47 PM PDT 24
Peak memory 190676 kb
Host smart-8a1c3450-be5b-4216-905c-de48247551a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873331518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2873331518
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3632188804
Short name T27
Test name
Test status
Simulation time 844145442935 ps
CPU time 457.82 seconds
Started May 23 12:27:34 PM PDT 24
Finished May 23 12:35:15 PM PDT 24
Peak memory 182532 kb
Host smart-348daff9-1e3f-4b8e-ba58-179de1328bc2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632188804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3632188804
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2866896986
Short name T382
Test name
Test status
Simulation time 168103371215 ps
CPU time 61.85 seconds
Started May 23 12:27:36 PM PDT 24
Finished May 23 12:28:42 PM PDT 24
Peak memory 182520 kb
Host smart-0437c6fc-04e7-429e-af34-9a7f05b182e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866896986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2866896986
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3787416429
Short name T439
Test name
Test status
Simulation time 270941754521 ps
CPU time 647.13 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:38:42 PM PDT 24
Peak memory 182460 kb
Host smart-7cd6eb68-2005-4fc3-96dd-5abf4ef95cbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787416429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3787416429
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1380214773
Short name T18
Test name
Test status
Simulation time 73056786 ps
CPU time 0.76 seconds
Started May 23 12:27:33 PM PDT 24
Finished May 23 12:27:37 PM PDT 24
Peak memory 212844 kb
Host smart-5c06229b-c764-4075-971b-c98c2b52d97e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380214773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1380214773
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2443797316
Short name T285
Test name
Test status
Simulation time 1244893900446 ps
CPU time 609.01 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:38:10 PM PDT 24
Peak memory 182532 kb
Host smart-c21a791e-98c8-44d6-bd37-4a1e9a6eab9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443797316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2443797316
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2971211426
Short name T438
Test name
Test status
Simulation time 693080041313 ps
CPU time 232.15 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:31:53 PM PDT 24
Peak memory 182420 kb
Host smart-afa6a845-c275-4538-9a79-25d14a28249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971211426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2971211426
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.627077592
Short name T26
Test name
Test status
Simulation time 72721399594 ps
CPU time 113.04 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:29:55 PM PDT 24
Peak memory 190660 kb
Host smart-5e4ede6d-efbf-49a5-b1a9-d0a5e1fcc9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627077592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.627077592
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.944774514
Short name T74
Test name
Test status
Simulation time 147616884927 ps
CPU time 120.93 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:29:54 PM PDT 24
Peak memory 190672 kb
Host smart-22b46e3f-726f-4948-97e7-c2b22b0a10d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944774514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.944774514
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.4104029000
Short name T229
Test name
Test status
Simulation time 692484994087 ps
CPU time 484.12 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:36:06 PM PDT 24
Peak memory 182500 kb
Host smart-305a43f7-08f9-4d17-be87-aa776b241714
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104029000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.4104029000
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3387025616
Short name T364
Test name
Test status
Simulation time 104837993123 ps
CPU time 40.32 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:28:39 PM PDT 24
Peak memory 182520 kb
Host smart-f90e9331-fe55-41d7-8c16-e542a036d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387025616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3387025616
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1048374010
Short name T400
Test name
Test status
Simulation time 51364512 ps
CPU time 0.6 seconds
Started May 23 12:28:10 PM PDT 24
Finished May 23 12:28:12 PM PDT 24
Peak memory 182492 kb
Host smart-9861a8f8-42da-4e5b-a778-f53351942181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048374010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1048374010
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.4222348402
Short name T110
Test name
Test status
Simulation time 37951746 ps
CPU time 0.56 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:28:05 PM PDT 24
Peak memory 182160 kb
Host smart-3c500a45-cd4f-4b5c-b660-1252520807c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222348402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.4222348402
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3276690240
Short name T265
Test name
Test status
Simulation time 769074104376 ps
CPU time 404.44 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:34:49 PM PDT 24
Peak memory 182496 kb
Host smart-d6c7e362-1e54-4612-93a6-bd5a16cc6711
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276690240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3276690240
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1341270603
Short name T425
Test name
Test status
Simulation time 457742722431 ps
CPU time 211.21 seconds
Started May 23 12:28:00 PM PDT 24
Finished May 23 12:31:34 PM PDT 24
Peak memory 182532 kb
Host smart-2d885bb8-1151-47cc-8fbc-d995945b125d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341270603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1341270603
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3377901243
Short name T250
Test name
Test status
Simulation time 2715314952416 ps
CPU time 597.91 seconds
Started May 23 12:27:53 PM PDT 24
Finished May 23 12:37:53 PM PDT 24
Peak memory 190552 kb
Host smart-5e6b2a13-a402-453b-8aa3-91edde302540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377901243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3377901243
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.911322304
Short name T420
Test name
Test status
Simulation time 943392609 ps
CPU time 1.05 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:28:01 PM PDT 24
Peak memory 182268 kb
Host smart-654481f9-28b9-42b7-90c9-cd6fd9815bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911322304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.911322304
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1173728221
Short name T175
Test name
Test status
Simulation time 227478913144 ps
CPU time 132.07 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:30:12 PM PDT 24
Peak memory 182520 kb
Host smart-8d7f9351-6910-41d2-befd-1307322feabd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173728221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1173728221
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2274412676
Short name T374
Test name
Test status
Simulation time 113985827533 ps
CPU time 50.83 seconds
Started May 23 12:27:51 PM PDT 24
Finished May 23 12:28:44 PM PDT 24
Peak memory 182532 kb
Host smart-255b011b-3fb9-4645-8ed0-59f06d180786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274412676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2274412676
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2118593712
Short name T152
Test name
Test status
Simulation time 402851390309 ps
CPU time 396.94 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:34:42 PM PDT 24
Peak memory 190664 kb
Host smart-006377af-f78c-43f5-9c0b-c3a1f14ecfee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118593712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2118593712
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1998379529
Short name T376
Test name
Test status
Simulation time 720729858 ps
CPU time 2.44 seconds
Started May 23 12:27:49 PM PDT 24
Finished May 23 12:27:53 PM PDT 24
Peak memory 182336 kb
Host smart-68a8f1a2-d498-4807-88dc-3c93288c2307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998379529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1998379529
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1354944154
Short name T447
Test name
Test status
Simulation time 162265593924 ps
CPU time 263.88 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:32:29 PM PDT 24
Peak memory 193944 kb
Host smart-d51ad09e-2eb6-458e-a469-7c9f4777b636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354944154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1354944154
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.4012373365
Short name T38
Test name
Test status
Simulation time 109512947311 ps
CPU time 225.9 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:31:47 PM PDT 24
Peak memory 197136 kb
Host smart-f9e3dac2-09f1-44dd-8100-47286804b345
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012373365 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.4012373365
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2138061220
Short name T436
Test name
Test status
Simulation time 239019194036 ps
CPU time 193.46 seconds
Started May 23 12:28:05 PM PDT 24
Finished May 23 12:31:21 PM PDT 24
Peak memory 182476 kb
Host smart-a1b42b06-7575-42b4-a86b-3a2167107384
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138061220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2138061220
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1065035438
Short name T372
Test name
Test status
Simulation time 99032495376 ps
CPU time 142.72 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:30:29 PM PDT 24
Peak memory 182456 kb
Host smart-7a4b3a8f-009f-471b-a2c3-49c458c6f712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065035438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1065035438
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.122810855
Short name T119
Test name
Test status
Simulation time 435432239385 ps
CPU time 369.31 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:34:14 PM PDT 24
Peak memory 190824 kb
Host smart-7511701b-4032-4c08-987f-d6ba8f661baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122810855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.122810855
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3197026020
Short name T282
Test name
Test status
Simulation time 836534513464 ps
CPU time 1554.6 seconds
Started May 23 12:28:05 PM PDT 24
Finished May 23 12:54:02 PM PDT 24
Peak memory 190732 kb
Host smart-dcc2bb42-1e3a-4f41-aa05-30550a5b489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197026020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3197026020
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3335240576
Short name T210
Test name
Test status
Simulation time 2254052061237 ps
CPU time 851.73 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:42:16 PM PDT 24
Peak memory 182436 kb
Host smart-455b56e3-17f6-4d73-8b0e-0b6d01a7fdc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335240576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3335240576
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1274494754
Short name T379
Test name
Test status
Simulation time 13098908792 ps
CPU time 5.45 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:28:11 PM PDT 24
Peak memory 182464 kb
Host smart-7e871c40-384e-41a6-8de6-17eff92a09cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274494754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1274494754
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1122357733
Short name T446
Test name
Test status
Simulation time 79949865693 ps
CPU time 204.69 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:31:31 PM PDT 24
Peak memory 190644 kb
Host smart-d737740d-e15c-476d-ac33-2f795523d783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122357733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1122357733
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.808539918
Short name T297
Test name
Test status
Simulation time 66971769254 ps
CPU time 149.16 seconds
Started May 23 12:28:24 PM PDT 24
Finished May 23 12:30:57 PM PDT 24
Peak memory 190652 kb
Host smart-b8eafac0-8404-4672-9e57-008efa436fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808539918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.808539918
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3925600986
Short name T37
Test name
Test status
Simulation time 16875784415 ps
CPU time 56.55 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:29:02 PM PDT 24
Peak memory 197116 kb
Host smart-9c535062-26b3-476f-b650-2ab03c26de83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925600986 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3925600986
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.761556149
Short name T183
Test name
Test status
Simulation time 693102595990 ps
CPU time 406.49 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:34:51 PM PDT 24
Peak memory 182452 kb
Host smart-edfaa01a-833d-4d76-81a3-338fa1ed3f80
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761556149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.761556149
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.282983519
Short name T6
Test name
Test status
Simulation time 315850733892 ps
CPU time 135.8 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:30:51 PM PDT 24
Peak memory 182424 kb
Host smart-697c0d68-9650-44c2-9ea9-8992e4117988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282983519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.282983519
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2465076721
Short name T201
Test name
Test status
Simulation time 606535367153 ps
CPU time 397.82 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:34:44 PM PDT 24
Peak memory 190676 kb
Host smart-ff6ba4dc-5fdd-497b-b3ff-43bbb9cb3617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465076721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2465076721
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2347966586
Short name T326
Test name
Test status
Simulation time 19537840304 ps
CPU time 35.55 seconds
Started May 23 12:28:09 PM PDT 24
Finished May 23 12:28:46 PM PDT 24
Peak memory 182480 kb
Host smart-af8535cc-d4ca-42cf-b960-34cd20282911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347966586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2347966586
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1243225085
Short name T261
Test name
Test status
Simulation time 494068084729 ps
CPU time 595.45 seconds
Started May 23 12:28:06 PM PDT 24
Finished May 23 12:38:03 PM PDT 24
Peak memory 194728 kb
Host smart-380193bd-3959-45cf-91e5-25b0c41554cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243225085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1243225085
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1297241424
Short name T288
Test name
Test status
Simulation time 5177267129432 ps
CPU time 1346.51 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:50:31 PM PDT 24
Peak memory 182472 kb
Host smart-71b12977-56e9-4b97-b173-8819f03e93d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297241424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1297241424
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.538014176
Short name T417
Test name
Test status
Simulation time 329427615657 ps
CPU time 134.47 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:30:20 PM PDT 24
Peak memory 182456 kb
Host smart-33208a3c-cc4f-4fce-9117-64828fbc5219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538014176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.538014176
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3066528225
Short name T369
Test name
Test status
Simulation time 24660702720 ps
CPU time 78.91 seconds
Started May 23 12:28:23 PM PDT 24
Finished May 23 12:29:45 PM PDT 24
Peak memory 192808 kb
Host smart-1d2a7db5-48c4-46d6-81a7-0fa692ec4b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066528225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3066528225
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2056891428
Short name T342
Test name
Test status
Simulation time 28253437509 ps
CPU time 42.08 seconds
Started May 23 12:28:21 PM PDT 24
Finished May 23 12:29:05 PM PDT 24
Peak memory 182500 kb
Host smart-5693e3ec-bcc7-4972-b080-a0c537d06ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056891428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2056891428
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3874055532
Short name T343
Test name
Test status
Simulation time 378752992787 ps
CPU time 254.67 seconds
Started May 23 12:28:09 PM PDT 24
Finished May 23 12:32:25 PM PDT 24
Peak memory 182500 kb
Host smart-1187bdd6-db20-452a-84eb-6a8907bd9a91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874055532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3874055532
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.803267813
Short name T393
Test name
Test status
Simulation time 114411454412 ps
CPU time 92.71 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:29:39 PM PDT 24
Peak memory 182416 kb
Host smart-72a24f2b-3742-49eb-b9ea-04ddc28ed0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803267813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.803267813
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1591066785
Short name T111
Test name
Test status
Simulation time 136282276824 ps
CPU time 90.19 seconds
Started May 23 12:28:18 PM PDT 24
Finished May 23 12:29:49 PM PDT 24
Peak memory 190676 kb
Host smart-f75455dc-0906-42cb-8ee0-f890bf9b9a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591066785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1591066785
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2344907340
Short name T399
Test name
Test status
Simulation time 186391858427 ps
CPU time 260.68 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:32:27 PM PDT 24
Peak memory 193908 kb
Host smart-eac2f37d-8e71-4759-b568-54b0f958c90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344907340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2344907340
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1388873911
Short name T190
Test name
Test status
Simulation time 873888713679 ps
CPU time 612.42 seconds
Started May 23 12:28:22 PM PDT 24
Finished May 23 12:38:37 PM PDT 24
Peak memory 182412 kb
Host smart-b4224048-1163-4cae-915f-bccea1e393b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388873911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1388873911
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.249138986
Short name T450
Test name
Test status
Simulation time 194394731465 ps
CPU time 85.78 seconds
Started May 23 12:28:35 PM PDT 24
Finished May 23 12:30:04 PM PDT 24
Peak memory 182544 kb
Host smart-801c50a1-606e-4c7a-8a95-712e2617dd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249138986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.249138986
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3109848089
Short name T303
Test name
Test status
Simulation time 60257308049 ps
CPU time 219.95 seconds
Started May 23 12:28:07 PM PDT 24
Finished May 23 12:31:48 PM PDT 24
Peak memory 190740 kb
Host smart-718e065a-d57e-4c53-9e26-f321e95a0d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109848089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3109848089
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.455668960
Short name T255
Test name
Test status
Simulation time 838417682906 ps
CPU time 553.74 seconds
Started May 23 12:28:07 PM PDT 24
Finished May 23 12:37:22 PM PDT 24
Peak memory 190668 kb
Host smart-474dd88a-c891-4951-baa2-044e253c442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455668960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.455668960
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1262065382
Short name T409
Test name
Test status
Simulation time 481587078969 ps
CPU time 192.64 seconds
Started May 23 12:27:43 PM PDT 24
Finished May 23 12:30:58 PM PDT 24
Peak memory 182396 kb
Host smart-8a4fdbfc-8592-48a0-b9ed-98d1bc6da3ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262065382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1262065382
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1608548049
Short name T391
Test name
Test status
Simulation time 144649981918 ps
CPU time 133.59 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:29:48 PM PDT 24
Peak memory 182464 kb
Host smart-01bbaadf-a547-4c83-baa7-a2fc2d1a079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608548049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1608548049
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.569442168
Short name T269
Test name
Test status
Simulation time 88558857949 ps
CPU time 87.81 seconds
Started May 23 12:27:35 PM PDT 24
Finished May 23 12:29:07 PM PDT 24
Peak memory 190708 kb
Host smart-069ec7ee-0879-4ea1-bf46-ca08a5a24e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569442168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.569442168
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1311459298
Short name T300
Test name
Test status
Simulation time 42702848468 ps
CPU time 67.17 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:29:02 PM PDT 24
Peak memory 182692 kb
Host smart-9b0bbfab-7f76-45a2-afac-af39a0766389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311459298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1311459298
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2486712844
Short name T17
Test name
Test status
Simulation time 173587175 ps
CPU time 0.78 seconds
Started May 23 12:27:47 PM PDT 24
Finished May 23 12:27:50 PM PDT 24
Peak memory 213692 kb
Host smart-80d7ebd9-0012-455b-93c2-3720bb947f3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486712844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2486712844
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_random.2544148414
Short name T283
Test name
Test status
Simulation time 87252415273 ps
CPU time 154.78 seconds
Started May 23 12:28:19 PM PDT 24
Finished May 23 12:30:56 PM PDT 24
Peak memory 190676 kb
Host smart-63f79eb3-1905-4baa-a52b-4f2df07e457c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544148414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2544148414
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.914294635
Short name T10
Test name
Test status
Simulation time 421155824078 ps
CPU time 1394.81 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:51:22 PM PDT 24
Peak memory 190628 kb
Host smart-d8702a63-cea8-4c92-92be-09a721345f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914294635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
914294635
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_random.3970472135
Short name T298
Test name
Test status
Simulation time 1091131910 ps
CPU time 2.05 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:28:07 PM PDT 24
Peak memory 182272 kb
Host smart-830148c3-2b4f-46ef-b684-693caf2dd2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970472135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3970472135
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.45786678
Short name T236
Test name
Test status
Simulation time 80041537346 ps
CPU time 135.67 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:30:23 PM PDT 24
Peak memory 190724 kb
Host smart-0ab63cb3-d880-4611-8034-b9580a6039dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45786678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.45786678
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.1749324538
Short name T14
Test name
Test status
Simulation time 139515721742 ps
CPU time 607.52 seconds
Started May 23 12:28:48 PM PDT 24
Finished May 23 12:38:56 PM PDT 24
Peak memory 206128 kb
Host smart-4e1c8a97-54aa-4c70-b14c-fc9511d2884d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749324538 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.1749324538
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.75268928
Short name T398
Test name
Test status
Simulation time 133708955221 ps
CPU time 197.01 seconds
Started May 23 12:28:22 PM PDT 24
Finished May 23 12:31:42 PM PDT 24
Peak memory 182448 kb
Host smart-ae0a4a3f-9d3b-4400-a641-b30144affbbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75268928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.rv_timer_cfg_update_on_fly.75268928
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.278483602
Short name T427
Test name
Test status
Simulation time 316551655368 ps
CPU time 120.71 seconds
Started May 23 12:28:22 PM PDT 24
Finished May 23 12:30:25 PM PDT 24
Peak memory 182460 kb
Host smart-cc0c32cd-1b28-41c1-9847-c43b1b7dcc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278483602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.278483602
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.4221323152
Short name T73
Test name
Test status
Simulation time 225688153336 ps
CPU time 830.66 seconds
Started May 23 12:28:26 PM PDT 24
Finished May 23 12:42:20 PM PDT 24
Peak memory 190640 kb
Host smart-1fc16b59-5e67-4a38-8b19-d2b4ecdd748b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221323152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4221323152
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1754927677
Short name T355
Test name
Test status
Simulation time 973534538901 ps
CPU time 452.04 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:35:38 PM PDT 24
Peak memory 193864 kb
Host smart-6a0fb0b8-42f2-4a2d-83ab-fce9c123b480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754927677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1754927677
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.326639696
Short name T317
Test name
Test status
Simulation time 127743927193 ps
CPU time 54.48 seconds
Started May 23 12:28:08 PM PDT 24
Finished May 23 12:29:04 PM PDT 24
Peak memory 182480 kb
Host smart-c21d6a2d-cdd1-4b93-828e-a78a7e8eb0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326639696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
326639696
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1014500088
Short name T195
Test name
Test status
Simulation time 589166479477 ps
CPU time 284.23 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:33:19 PM PDT 24
Peak memory 182520 kb
Host smart-2f73e565-78a1-4732-bc09-861fda34296e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014500088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1014500088
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.741459353
Short name T363
Test name
Test status
Simulation time 511652149027 ps
CPU time 266.66 seconds
Started May 23 12:28:12 PM PDT 24
Finished May 23 12:32:40 PM PDT 24
Peak memory 182480 kb
Host smart-f072c804-6aa9-4de4-869f-a7179f8539e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741459353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.741459353
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1805441679
Short name T203
Test name
Test status
Simulation time 55759384857 ps
CPU time 93.44 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:29:38 PM PDT 24
Peak memory 190644 kb
Host smart-3d116eb8-2878-4ad5-811f-4d8ebb142efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805441679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1805441679
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2183003635
Short name T76
Test name
Test status
Simulation time 256440675477 ps
CPU time 194.81 seconds
Started May 23 12:28:38 PM PDT 24
Finished May 23 12:31:55 PM PDT 24
Peak memory 193936 kb
Host smart-353e7d01-84a7-4ad7-8f41-e1c8d324118d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183003635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2183003635
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1640586128
Short name T148
Test name
Test status
Simulation time 662012088705 ps
CPU time 2704.75 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 01:13:42 PM PDT 24
Peak memory 190676 kb
Host smart-40943c17-0b97-4ecc-8c6c-dc0fa7ecb87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640586128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1640586128
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.693223201
Short name T206
Test name
Test status
Simulation time 338603555947 ps
CPU time 604.19 seconds
Started May 23 12:28:19 PM PDT 24
Finished May 23 12:38:24 PM PDT 24
Peak memory 182592 kb
Host smart-5cbdadcd-6a78-4806-a69a-f2edd5631630
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693223201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.693223201
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.754069005
Short name T44
Test name
Test status
Simulation time 176042686109 ps
CPU time 149.56 seconds
Started May 23 12:28:34 PM PDT 24
Finished May 23 12:31:07 PM PDT 24
Peak memory 182492 kb
Host smart-db2344e8-ad59-449a-b6f0-ee3b14ee1af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754069005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.754069005
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1624475175
Short name T304
Test name
Test status
Simulation time 23004015286 ps
CPU time 9.74 seconds
Started May 23 12:28:19 PM PDT 24
Finished May 23 12:28:30 PM PDT 24
Peak memory 182336 kb
Host smart-2da31af0-bde0-4bed-a882-8449b323632d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624475175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1624475175
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1988995378
Short name T315
Test name
Test status
Simulation time 250665238927 ps
CPU time 646.33 seconds
Started May 23 12:28:17 PM PDT 24
Finished May 23 12:39:05 PM PDT 24
Peak memory 190672 kb
Host smart-374df7cd-d9f8-46de-bc61-0e47fcafc24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988995378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1988995378
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3981021812
Short name T170
Test name
Test status
Simulation time 1347348997801 ps
CPU time 271.88 seconds
Started May 23 12:28:20 PM PDT 24
Finished May 23 12:32:53 PM PDT 24
Peak memory 182500 kb
Host smart-1b4207d2-2080-4958-8b78-e2f2f02c3dd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981021812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3981021812
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3841215977
Short name T370
Test name
Test status
Simulation time 238133965931 ps
CPU time 180.09 seconds
Started May 23 12:28:04 PM PDT 24
Finished May 23 12:31:07 PM PDT 24
Peak memory 182488 kb
Host smart-69c34b74-85ea-4bfd-8a05-4f2c771eb49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841215977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3841215977
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1913913043
Short name T21
Test name
Test status
Simulation time 108061345916 ps
CPU time 466.76 seconds
Started May 23 12:28:30 PM PDT 24
Finished May 23 12:36:19 PM PDT 24
Peak memory 190672 kb
Host smart-f9f8758d-e1a4-4a80-90e4-8dcf7b9b3a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913913043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1913913043
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.246752694
Short name T410
Test name
Test status
Simulation time 44794646 ps
CPU time 0.55 seconds
Started May 23 12:28:26 PM PDT 24
Finished May 23 12:28:30 PM PDT 24
Peak memory 182260 kb
Host smart-df7ae47e-5cc8-4924-b2e9-779c4dd7b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246752694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.246752694
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.3948949744
Short name T13
Test name
Test status
Simulation time 237486780733 ps
CPU time 496.33 seconds
Started May 23 12:28:35 PM PDT 24
Finished May 23 12:36:54 PM PDT 24
Peak memory 205296 kb
Host smart-ef5c5257-1ee3-439f-917c-da73dd8442a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948949744 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.3948949744
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.855198098
Short name T211
Test name
Test status
Simulation time 124852843611 ps
CPU time 225.63 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:32:20 PM PDT 24
Peak memory 182444 kb
Host smart-8ba0d3b7-9cbd-432e-adcc-7af059b3ee9c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855198098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.855198098
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3658454257
Short name T405
Test name
Test status
Simulation time 560126635344 ps
CPU time 192.4 seconds
Started May 23 12:28:26 PM PDT 24
Finished May 23 12:31:42 PM PDT 24
Peak memory 182456 kb
Host smart-827d46cb-842c-4742-a94d-250f3d950248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658454257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3658454257
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2177146955
Short name T154
Test name
Test status
Simulation time 151379847033 ps
CPU time 324.44 seconds
Started May 23 12:28:26 PM PDT 24
Finished May 23 12:33:54 PM PDT 24
Peak memory 190688 kb
Host smart-b81cd063-edbf-46af-965b-def4921f5ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177146955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2177146955
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3976913275
Short name T316
Test name
Test status
Simulation time 14683008009 ps
CPU time 23.06 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:28:54 PM PDT 24
Peak memory 182488 kb
Host smart-e378c077-8ed8-4dff-979c-1631f4123742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976913275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3976913275
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1508771229
Short name T442
Test name
Test status
Simulation time 256725215481 ps
CPU time 392.95 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:35:04 PM PDT 24
Peak memory 194028 kb
Host smart-183af2d2-cfdb-462d-a4b0-81f58e756bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508771229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1508771229
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.4149321015
Short name T306
Test name
Test status
Simulation time 193236320131 ps
CPU time 179.18 seconds
Started May 23 12:28:21 PM PDT 24
Finished May 23 12:31:22 PM PDT 24
Peak memory 182500 kb
Host smart-308b0812-9636-4b5b-bed2-5e041cc489af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149321015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.4149321015
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1839251666
Short name T378
Test name
Test status
Simulation time 212190192771 ps
CPU time 321.71 seconds
Started May 23 12:28:19 PM PDT 24
Finished May 23 12:33:41 PM PDT 24
Peak memory 182480 kb
Host smart-6c3050be-bc6d-4ee0-819b-5dd1c7bc4cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839251666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1839251666
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3687409641
Short name T258
Test name
Test status
Simulation time 247284072890 ps
CPU time 102.26 seconds
Started May 23 12:28:30 PM PDT 24
Finished May 23 12:30:14 PM PDT 24
Peak memory 190644 kb
Host smart-398e3f08-678f-4136-8bdb-d479a81d48f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687409641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3687409641
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2191683730
Short name T357
Test name
Test status
Simulation time 244316622554 ps
CPU time 83.06 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:29:57 PM PDT 24
Peak memory 182492 kb
Host smart-2a945015-0038-42e7-8bef-4a232d6ffa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191683730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2191683730
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2495241042
Short name T238
Test name
Test status
Simulation time 1613303012154 ps
CPU time 1812.06 seconds
Started May 23 12:28:10 PM PDT 24
Finished May 23 12:58:24 PM PDT 24
Peak memory 190704 kb
Host smart-761aaab1-8643-4a80-868d-83eed474c0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495241042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2495241042
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.723835435
Short name T327
Test name
Test status
Simulation time 224636895172 ps
CPU time 411.65 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:35:28 PM PDT 24
Peak memory 182476 kb
Host smart-645e6eb4-52dc-4857-98d4-0bf9c3e518e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723835435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.723835435
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1171122536
Short name T365
Test name
Test status
Simulation time 526689682213 ps
CPU time 184.13 seconds
Started May 23 12:28:38 PM PDT 24
Finished May 23 12:31:44 PM PDT 24
Peak memory 182492 kb
Host smart-3be34bd9-c69f-470f-ae35-bfd0cce3cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171122536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1171122536
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.4014584056
Short name T377
Test name
Test status
Simulation time 230881002106 ps
CPU time 72.83 seconds
Started May 23 12:28:24 PM PDT 24
Finished May 23 12:29:40 PM PDT 24
Peak memory 182416 kb
Host smart-ee67ba49-6452-4a58-841e-4c9049a7a0d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014584056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.4014584056
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1671006824
Short name T301
Test name
Test status
Simulation time 89522810289 ps
CPU time 158.02 seconds
Started May 23 12:28:31 PM PDT 24
Finished May 23 12:31:11 PM PDT 24
Peak memory 190660 kb
Host smart-f159c0d0-acae-4349-856b-a4608264024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671006824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1671006824
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2070149843
Short name T184
Test name
Test status
Simulation time 1065724611134 ps
CPU time 515.02 seconds
Started May 23 12:28:10 PM PDT 24
Finished May 23 12:36:46 PM PDT 24
Peak memory 182520 kb
Host smart-7ff37528-b9c8-4eeb-9a79-6b43292345b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070149843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2070149843
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2446930746
Short name T381
Test name
Test status
Simulation time 587173005308 ps
CPU time 250.22 seconds
Started May 23 12:28:17 PM PDT 24
Finished May 23 12:32:28 PM PDT 24
Peak memory 182492 kb
Host smart-36ff65f7-70da-4860-aa61-c2c7e98dc0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446930746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2446930746
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1267961500
Short name T69
Test name
Test status
Simulation time 27470246803 ps
CPU time 37.87 seconds
Started May 23 12:28:16 PM PDT 24
Finished May 23 12:29:01 PM PDT 24
Peak memory 182484 kb
Host smart-886e5cc4-96ab-4bf3-8297-7e54923dc238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267961500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1267961500
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1238073811
Short name T429
Test name
Test status
Simulation time 320790341066 ps
CPU time 85.26 seconds
Started May 23 12:28:31 PM PDT 24
Finished May 23 12:29:59 PM PDT 24
Peak memory 182440 kb
Host smart-dffc0830-f450-48a9-b559-fc98fa66e375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238073811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1238073811
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.729361603
Short name T295
Test name
Test status
Simulation time 330359305405 ps
CPU time 274.24 seconds
Started May 23 12:27:50 PM PDT 24
Finished May 23 12:32:26 PM PDT 24
Peak memory 182412 kb
Host smart-e1594cdb-e763-4072-985f-b299b7d83c69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729361603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.729361603
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2783961284
Short name T384
Test name
Test status
Simulation time 521208458480 ps
CPU time 213.69 seconds
Started May 23 12:27:41 PM PDT 24
Finished May 23 12:31:17 PM PDT 24
Peak memory 182428 kb
Host smart-ffeb49c9-bd3c-4336-8ade-cd7c468d97c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783961284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2783961284
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.623892149
Short name T205
Test name
Test status
Simulation time 51252640107 ps
CPU time 43.44 seconds
Started May 23 12:27:40 PM PDT 24
Finished May 23 12:28:27 PM PDT 24
Peak memory 182308 kb
Host smart-258a91f3-1f23-4561-962e-ed7adaaa8d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623892149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.623892149
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3416888247
Short name T353
Test name
Test status
Simulation time 142122813515 ps
CPU time 67.71 seconds
Started May 23 12:27:34 PM PDT 24
Finished May 23 12:28:45 PM PDT 24
Peak memory 182520 kb
Host smart-38864148-3e2a-4a2d-963e-d256da592d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416888247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3416888247
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2693058338
Short name T60
Test name
Test status
Simulation time 2327361963666 ps
CPU time 1082.15 seconds
Started May 23 12:27:31 PM PDT 24
Finished May 23 12:45:36 PM PDT 24
Peak memory 195400 kb
Host smart-cb1cc82f-4ef6-4416-8d69-1f85684832b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693058338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2693058338
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.38021353
Short name T408
Test name
Test status
Simulation time 1761818950425 ps
CPU time 559.69 seconds
Started May 23 12:28:38 PM PDT 24
Finished May 23 12:37:59 PM PDT 24
Peak memory 190692 kb
Host smart-e81670b8-b7c6-41ba-a576-1c091a88466a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38021353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.38021353
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3433778582
Short name T244
Test name
Test status
Simulation time 162390101781 ps
CPU time 124.52 seconds
Started May 23 12:28:31 PM PDT 24
Finished May 23 12:30:37 PM PDT 24
Peak memory 190632 kb
Host smart-d9889ece-d304-47db-a0d7-90c9865a3fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433778582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3433778582
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2531034079
Short name T349
Test name
Test status
Simulation time 490389819287 ps
CPU time 316.26 seconds
Started May 23 12:28:25 PM PDT 24
Finished May 23 12:33:45 PM PDT 24
Peak memory 190688 kb
Host smart-339b5f44-16d8-429f-8905-0a0ae6f94dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531034079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2531034079
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2420802386
Short name T112
Test name
Test status
Simulation time 1452414820895 ps
CPU time 724.67 seconds
Started May 23 12:28:18 PM PDT 24
Finished May 23 12:40:24 PM PDT 24
Peak memory 190696 kb
Host smart-e38c457a-7feb-498d-aac1-e2f97d6693a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420802386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2420802386
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3884008565
Short name T134
Test name
Test status
Simulation time 114582811685 ps
CPU time 1217.09 seconds
Started May 23 12:28:10 PM PDT 24
Finished May 23 12:48:28 PM PDT 24
Peak memory 190644 kb
Host smart-76749b8b-e4db-4cd8-a1d5-2cdd9a28eddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884008565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3884008565
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2551733277
Short name T127
Test name
Test status
Simulation time 2457764728055 ps
CPU time 736.3 seconds
Started May 23 12:28:13 PM PDT 24
Finished May 23 12:40:30 PM PDT 24
Peak memory 190672 kb
Host smart-b7cbebeb-a2c4-4568-bc16-ba8741979b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551733277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2551733277
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3738837538
Short name T336
Test name
Test status
Simulation time 556310874894 ps
CPU time 472.83 seconds
Started May 23 12:27:58 PM PDT 24
Finished May 23 12:35:53 PM PDT 24
Peak memory 182432 kb
Host smart-f6842f1b-1335-4114-9158-41a7e56f856c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738837538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3738837538
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random.2346146453
Short name T412
Test name
Test status
Simulation time 33069989935 ps
CPU time 140.1 seconds
Started May 23 12:27:47 PM PDT 24
Finished May 23 12:30:09 PM PDT 24
Peak memory 182420 kb
Host smart-071ad260-cad6-4586-9794-c6b19de6bc7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346146453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2346146453
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4211616373
Short name T362
Test name
Test status
Simulation time 818601450 ps
CPU time 0.81 seconds
Started May 23 12:27:46 PM PDT 24
Finished May 23 12:27:48 PM PDT 24
Peak memory 182224 kb
Host smart-33ee1954-875a-44d8-8b27-42ef9610fe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211616373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4211616373
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1071827304
Short name T220
Test name
Test status
Simulation time 144303023956 ps
CPU time 895.2 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:43:27 PM PDT 24
Peak memory 190652 kb
Host smart-5935fa01-2c95-489f-9cc5-fad84f49ff2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071827304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1071827304
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2428216355
Short name T333
Test name
Test status
Simulation time 221983513633 ps
CPU time 1719.9 seconds
Started May 23 12:28:26 PM PDT 24
Finished May 23 12:57:10 PM PDT 24
Peak memory 190652 kb
Host smart-b31e36d8-4259-4374-ad92-df58c09bd9cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428216355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2428216355
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3418896884
Short name T334
Test name
Test status
Simulation time 13673524193 ps
CPU time 12.35 seconds
Started May 23 12:28:16 PM PDT 24
Finished May 23 12:28:29 PM PDT 24
Peak memory 182596 kb
Host smart-4fa554ae-c7f3-4724-91b6-93a27e67f5f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418896884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3418896884
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1835188333
Short name T319
Test name
Test status
Simulation time 46756957740 ps
CPU time 22.31 seconds
Started May 23 12:28:12 PM PDT 24
Finished May 23 12:28:36 PM PDT 24
Peak memory 182480 kb
Host smart-91d74869-255c-48dc-a996-ffc4cbe1dd8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835188333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1835188333
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1763762644
Short name T341
Test name
Test status
Simulation time 69668901979 ps
CPU time 410.55 seconds
Started May 23 12:28:09 PM PDT 24
Finished May 23 12:35:01 PM PDT 24
Peak memory 193276 kb
Host smart-a6b8ce35-be84-467a-8200-069eac47567d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763762644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1763762644
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2961735984
Short name T202
Test name
Test status
Simulation time 116363865999 ps
CPU time 223.69 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:32:19 PM PDT 24
Peak memory 190700 kb
Host smart-5fa6b23d-207e-477f-a195-9290a3acd9d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961735984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2961735984
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1867877220
Short name T292
Test name
Test status
Simulation time 543695341161 ps
CPU time 204 seconds
Started May 23 12:28:06 PM PDT 24
Finished May 23 12:31:32 PM PDT 24
Peak memory 190160 kb
Host smart-d8ffd41b-17ec-4f72-a0ee-60df455f9b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867877220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1867877220
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3954908973
Short name T3
Test name
Test status
Simulation time 199457872149 ps
CPU time 193.38 seconds
Started May 23 12:28:10 PM PDT 24
Finished May 23 12:31:24 PM PDT 24
Peak memory 190712 kb
Host smart-d4f477a5-7825-4537-8e0c-76d66fefb14f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954908973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3954908973
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3212399415
Short name T330
Test name
Test status
Simulation time 78602531266 ps
CPU time 99.28 seconds
Started May 23 12:28:24 PM PDT 24
Finished May 23 12:30:06 PM PDT 24
Peak memory 190676 kb
Host smart-68c478f9-a03f-4bb2-842a-8b756a9f971b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212399415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3212399415
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1569632624
Short name T287
Test name
Test status
Simulation time 724187996952 ps
CPU time 329.08 seconds
Started May 23 12:27:40 PM PDT 24
Finished May 23 12:33:13 PM PDT 24
Peak memory 182396 kb
Host smart-fb99ca8a-d414-41e5-abf0-b8b35cff3d8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569632624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1569632624
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3060138112
Short name T366
Test name
Test status
Simulation time 187024429315 ps
CPU time 237.94 seconds
Started May 23 12:27:32 PM PDT 24
Finished May 23 12:31:32 PM PDT 24
Peak memory 182440 kb
Host smart-41a6dcd5-74bb-4f60-a629-53e4667e8a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060138112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3060138112
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.591306501
Short name T318
Test name
Test status
Simulation time 633470675411 ps
CPU time 161.21 seconds
Started May 23 12:27:45 PM PDT 24
Finished May 23 12:30:28 PM PDT 24
Peak memory 190608 kb
Host smart-dd443255-1d79-448e-afb2-9ffeb21e5e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591306501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.591306501
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.705105559
Short name T373
Test name
Test status
Simulation time 104631202 ps
CPU time 0.69 seconds
Started May 23 12:27:59 PM PDT 24
Finished May 23 12:28:03 PM PDT 24
Peak memory 182280 kb
Host smart-aff42872-7b49-4581-a4ee-354d793dc4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705105559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.705105559
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3485818517
Short name T209
Test name
Test status
Simulation time 1615778366431 ps
CPU time 1052.39 seconds
Started May 23 12:28:15 PM PDT 24
Finished May 23 12:45:48 PM PDT 24
Peak memory 190796 kb
Host smart-eb75b203-64ae-4326-b347-faae14282f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485818517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3485818517
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3029991836
Short name T128
Test name
Test status
Simulation time 149306691093 ps
CPU time 231.54 seconds
Started May 23 12:28:08 PM PDT 24
Finished May 23 12:32:01 PM PDT 24
Peak memory 190708 kb
Host smart-0bdd1ebf-6704-4226-847d-2df2ab553cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029991836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3029991836
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3694879464
Short name T305
Test name
Test status
Simulation time 6210551826 ps
CPU time 25.37 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:28:59 PM PDT 24
Peak memory 192884 kb
Host smart-5fb8163e-4d01-4145-b788-4acffd14b14f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694879464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3694879464
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.4040905497
Short name T299
Test name
Test status
Simulation time 126706880133 ps
CPU time 94.22 seconds
Started May 23 12:28:41 PM PDT 24
Finished May 23 12:30:17 PM PDT 24
Peak memory 190680 kb
Host smart-e35e836e-01f2-427e-9390-ff590a22af4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040905497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.4040905497
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.404200817
Short name T358
Test name
Test status
Simulation time 91057631219 ps
CPU time 155.82 seconds
Started May 23 12:28:29 PM PDT 24
Finished May 23 12:31:07 PM PDT 24
Peak memory 190640 kb
Host smart-c8763f35-c9b2-44bf-a309-54bee631420f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404200817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.404200817
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3468094428
Short name T359
Test name
Test status
Simulation time 1342699194995 ps
CPU time 756.32 seconds
Started May 23 12:28:22 PM PDT 24
Finished May 23 12:41:00 PM PDT 24
Peak memory 190632 kb
Host smart-37dbb547-0018-4e27-88e9-65c9d36e4974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468094428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3468094428
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.382930028
Short name T173
Test name
Test status
Simulation time 242206988998 ps
CPU time 108.39 seconds
Started May 23 12:28:39 PM PDT 24
Finished May 23 12:30:30 PM PDT 24
Peak memory 190640 kb
Host smart-7672d822-b21e-40f6-8034-03e9fc52dbae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382930028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.382930028
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2976586947
Short name T181
Test name
Test status
Simulation time 606168814090 ps
CPU time 677.04 seconds
Started May 23 12:28:15 PM PDT 24
Finished May 23 12:39:33 PM PDT 24
Peak memory 190664 kb
Host smart-936bc169-3ad4-4675-a26d-610bc49af0ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976586947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2976586947
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3187615348
Short name T322
Test name
Test status
Simulation time 110363434802 ps
CPU time 463.79 seconds
Started May 23 12:28:22 PM PDT 24
Finished May 23 12:36:07 PM PDT 24
Peak memory 190672 kb
Host smart-51cd7501-5804-4239-89df-37f9e2d800f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187615348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3187615348
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3247865495
Short name T47
Test name
Test status
Simulation time 174235599923 ps
CPU time 252.42 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:32:16 PM PDT 24
Peak memory 182444 kb
Host smart-648c2e62-b232-40a8-b8fc-7f44a5743a50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247865495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3247865495
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1980960283
Short name T395
Test name
Test status
Simulation time 589184613010 ps
CPU time 231.25 seconds
Started May 23 12:27:50 PM PDT 24
Finished May 23 12:31:43 PM PDT 24
Peak memory 182568 kb
Host smart-c28ee865-abc9-4fb0-bf25-662307d54712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980960283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1980960283
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3069870918
Short name T350
Test name
Test status
Simulation time 99833671771 ps
CPU time 295.14 seconds
Started May 23 12:27:57 PM PDT 24
Finished May 23 12:32:54 PM PDT 24
Peak memory 190616 kb
Host smart-6a40dc29-c6f1-467b-ae97-31829c0e739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069870918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3069870918
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.6885197
Short name T307
Test name
Test status
Simulation time 271048569551 ps
CPU time 423.9 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:35:38 PM PDT 24
Peak memory 190644 kb
Host smart-36489c5f-83f0-49ff-bfe3-16f0ff4abf36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6885197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.6885197
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.941013023
Short name T180
Test name
Test status
Simulation time 28653140328 ps
CPU time 59.79 seconds
Started May 23 12:28:01 PM PDT 24
Finished May 23 12:29:08 PM PDT 24
Peak memory 190660 kb
Host smart-2f8b3b9d-28ac-45d0-b313-5195180470aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941013023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.941013023
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.384129741
Short name T185
Test name
Test status
Simulation time 40427322830 ps
CPU time 981.84 seconds
Started May 23 12:28:12 PM PDT 24
Finished May 23 12:44:35 PM PDT 24
Peak memory 190700 kb
Host smart-aa56250f-7099-45ed-9fa2-a6da66a88a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384129741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.384129741
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2069561906
Short name T208
Test name
Test status
Simulation time 8006918885 ps
CPU time 68.88 seconds
Started May 23 12:28:14 PM PDT 24
Finished May 23 12:29:24 PM PDT 24
Peak memory 182496 kb
Host smart-e3ad70d8-5666-4549-9c71-f9740111edce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069561906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2069561906
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4175357421
Short name T11
Test name
Test status
Simulation time 827162597626 ps
CPU time 727.12 seconds
Started May 23 12:28:02 PM PDT 24
Finished May 23 12:40:17 PM PDT 24
Peak memory 190648 kb
Host smart-6e1e7bb6-aadf-4e45-8b54-b4e272f0dce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175357421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4175357421
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1469179152
Short name T422
Test name
Test status
Simulation time 181969200365 ps
CPU time 172.82 seconds
Started May 23 12:28:25 PM PDT 24
Finished May 23 12:31:22 PM PDT 24
Peak memory 190688 kb
Host smart-04c76692-10bc-4f21-85f2-a6d58a3e8366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469179152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1469179152
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3218840940
Short name T197
Test name
Test status
Simulation time 94833006056 ps
CPU time 1131.76 seconds
Started May 23 12:28:32 PM PDT 24
Finished May 23 12:47:26 PM PDT 24
Peak memory 190636 kb
Host smart-415b7729-3de9-486e-87f7-021a68efa238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218840940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3218840940
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.531839101
Short name T182
Test name
Test status
Simulation time 172228980761 ps
CPU time 1595.19 seconds
Started May 23 12:28:12 PM PDT 24
Finished May 23 12:54:48 PM PDT 24
Peak memory 190676 kb
Host smart-a909df62-c39d-403b-88b5-3f99ffafcdfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531839101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.531839101
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1210799100
Short name T177
Test name
Test status
Simulation time 621447225864 ps
CPU time 353.91 seconds
Started May 23 12:27:56 PM PDT 24
Finished May 23 12:33:52 PM PDT 24
Peak memory 182620 kb
Host smart-a4f4f5f3-300c-4ef9-a90a-7bc9833ecb96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210799100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1210799100
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.911215777
Short name T383
Test name
Test status
Simulation time 163479386412 ps
CPU time 214.32 seconds
Started May 23 12:27:52 PM PDT 24
Finished May 23 12:31:29 PM PDT 24
Peak memory 182492 kb
Host smart-3cfe3302-9fb2-4264-bee7-55b7354511b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911215777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.911215777
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4042865393
Short name T46
Test name
Test status
Simulation time 550131328195 ps
CPU time 307.59 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:33:14 PM PDT 24
Peak memory 192876 kb
Host smart-bda24ab1-2929-4b77-84e9-cf530b6fd626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042865393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4042865393
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2145974419
Short name T260
Test name
Test status
Simulation time 158332980720 ps
CPU time 41.47 seconds
Started May 23 12:27:56 PM PDT 24
Finished May 23 12:28:39 PM PDT 24
Peak memory 193980 kb
Host smart-0c0b76dd-5b26-46a8-99f4-7d469f545ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145974419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2145974419
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1946639529
Short name T9
Test name
Test status
Simulation time 80036351154 ps
CPU time 574.58 seconds
Started May 23 12:28:00 PM PDT 24
Finished May 23 12:37:42 PM PDT 24
Peak memory 182544 kb
Host smart-bb16ca9c-518d-40ec-b42b-db3f6fa739c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946639529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1946639529
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.2003611987
Short name T135
Test name
Test status
Simulation time 149871850612 ps
CPU time 366.52 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:34:42 PM PDT 24
Peak memory 190640 kb
Host smart-bfbe6915-344c-40c6-8127-4503cb471359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003611987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2003611987
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.4043746431
Short name T324
Test name
Test status
Simulation time 163178812660 ps
CPU time 1837.73 seconds
Started May 23 12:28:19 PM PDT 24
Finished May 23 12:58:59 PM PDT 24
Peak memory 190668 kb
Host smart-618abe6e-1e5e-4bcf-945b-63107639390c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043746431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.4043746431
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2222916593
Short name T138
Test name
Test status
Simulation time 44654791742 ps
CPU time 92.95 seconds
Started May 23 12:28:33 PM PDT 24
Finished May 23 12:30:09 PM PDT 24
Peak memory 182440 kb
Host smart-9e521aae-0b5b-44e6-81e1-6c88512e0965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222916593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2222916593
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.320301397
Short name T179
Test name
Test status
Simulation time 130759649149 ps
CPU time 384.06 seconds
Started May 23 12:28:12 PM PDT 24
Finished May 23 12:34:38 PM PDT 24
Peak memory 190616 kb
Host smart-1c263afc-79e7-427c-9852-b7cf5e15f3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320301397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.320301397
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3387551156
Short name T4
Test name
Test status
Simulation time 80793460216 ps
CPU time 152.91 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:30:39 PM PDT 24
Peak memory 190732 kb
Host smart-0cd084c3-8cea-4eda-836e-4ca0c998a9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387551156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3387551156
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1283143159
Short name T214
Test name
Test status
Simulation time 324265505093 ps
CPU time 565.8 seconds
Started May 23 12:28:03 PM PDT 24
Finished May 23 12:37:32 PM PDT 24
Peak memory 190724 kb
Host smart-66f41b2c-f334-4073-8de9-58f26a828434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283143159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1283143159
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.403677500
Short name T253
Test name
Test status
Simulation time 351482357465 ps
CPU time 1851.17 seconds
Started May 23 12:28:24 PM PDT 24
Finished May 23 12:59:19 PM PDT 24
Peak memory 190624 kb
Host smart-f7183478-6536-4fdd-b1d9-4385c36a88d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403677500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.403677500
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1458274184
Short name T162
Test name
Test status
Simulation time 1493770459 ps
CPU time 2.77 seconds
Started May 23 12:28:20 PM PDT 24
Finished May 23 12:28:24 PM PDT 24
Peak memory 182272 kb
Host smart-a4933de1-252f-4c60-b757-8ea1dae1c269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458274184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1458274184
Directory /workspace/99.rv_timer_random/latest
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