Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 578
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2449249238 May 26 01:09:14 PM PDT 24 May 26 01:09:17 PM PDT 24 46838345 ps
T512 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.483943337 May 26 01:09:20 PM PDT 24 May 26 01:09:22 PM PDT 24 39862776 ps
T513 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2684239804 May 26 01:09:14 PM PDT 24 May 26 01:09:16 PM PDT 24 17730192 ps
T514 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1209803668 May 26 01:09:35 PM PDT 24 May 26 01:09:38 PM PDT 24 43266029 ps
T515 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1926577756 May 26 01:09:09 PM PDT 24 May 26 01:09:12 PM PDT 24 308835161 ps
T88 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3443712889 May 26 01:09:15 PM PDT 24 May 26 01:09:18 PM PDT 24 33963095 ps
T516 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.777456316 May 26 01:09:37 PM PDT 24 May 26 01:09:40 PM PDT 24 20826932 ps
T517 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3784661262 May 26 01:09:42 PM PDT 24 May 26 01:09:45 PM PDT 24 81548371 ps
T518 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1221217303 May 26 01:09:22 PM PDT 24 May 26 01:09:25 PM PDT 24 19018475 ps
T519 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.119420644 May 26 01:09:15 PM PDT 24 May 26 01:09:17 PM PDT 24 30843223 ps
T520 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2633804204 May 26 01:09:21 PM PDT 24 May 26 01:09:24 PM PDT 24 37640255 ps
T521 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2133115775 May 26 01:09:21 PM PDT 24 May 26 01:09:26 PM PDT 24 233687522 ps
T522 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4241105356 May 26 01:09:21 PM PDT 24 May 26 01:09:24 PM PDT 24 13616983 ps
T523 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.787166176 May 26 01:09:19 PM PDT 24 May 26 01:09:21 PM PDT 24 91993638 ps
T524 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.824746001 May 26 01:09:23 PM PDT 24 May 26 01:09:25 PM PDT 24 16403939 ps
T525 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1682303987 May 26 01:09:16 PM PDT 24 May 26 01:09:19 PM PDT 24 229282584 ps
T526 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2479212874 May 26 01:09:13 PM PDT 24 May 26 01:09:15 PM PDT 24 68658779 ps
T527 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1139861275 May 26 01:09:26 PM PDT 24 May 26 01:09:28 PM PDT 24 75606902 ps
T528 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1212146974 May 26 01:09:15 PM PDT 24 May 26 01:09:19 PM PDT 24 49269419 ps
T111 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.87016337 May 26 01:09:18 PM PDT 24 May 26 01:09:20 PM PDT 24 88899390 ps
T112 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.938505872 May 26 01:09:01 PM PDT 24 May 26 01:09:04 PM PDT 24 243760472 ps
T529 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2315020924 May 26 01:09:23 PM PDT 24 May 26 01:09:25 PM PDT 24 20208910 ps
T530 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1946963136 May 26 01:09:25 PM PDT 24 May 26 01:09:27 PM PDT 24 42836824 ps
T531 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4095996462 May 26 01:09:21 PM PDT 24 May 26 01:09:24 PM PDT 24 12065713 ps
T532 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3762812893 May 26 01:09:19 PM PDT 24 May 26 01:09:22 PM PDT 24 90165678 ps
T533 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.45452323 May 26 01:09:39 PM PDT 24 May 26 01:09:43 PM PDT 24 31507453 ps
T534 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2284470824 May 26 01:09:45 PM PDT 24 May 26 01:09:52 PM PDT 24 16170408 ps
T535 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4182901108 May 26 01:09:27 PM PDT 24 May 26 01:09:29 PM PDT 24 109335951 ps
T536 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2383446189 May 26 01:09:14 PM PDT 24 May 26 01:09:17 PM PDT 24 23969817 ps
T537 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4070506532 May 26 01:09:14 PM PDT 24 May 26 01:09:17 PM PDT 24 146968388 ps
T89 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2237804621 May 26 01:09:14 PM PDT 24 May 26 01:09:16 PM PDT 24 155212471 ps
T90 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1399454013 May 26 01:09:16 PM PDT 24 May 26 01:09:18 PM PDT 24 194624065 ps
T538 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.403208326 May 26 01:09:06 PM PDT 24 May 26 01:09:08 PM PDT 24 37197197 ps
T91 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1433039397 May 26 01:09:20 PM PDT 24 May 26 01:09:22 PM PDT 24 22582963 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2288277697 May 26 01:09:26 PM PDT 24 May 26 01:09:30 PM PDT 24 171719461 ps
T540 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3428172770 May 26 01:09:20 PM PDT 24 May 26 01:09:21 PM PDT 24 13553634 ps
T541 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3133897826 May 26 01:09:47 PM PDT 24 May 26 01:09:49 PM PDT 24 23498521 ps
T542 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2635566314 May 26 01:09:22 PM PDT 24 May 26 01:09:25 PM PDT 24 16491868 ps
T543 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2304682462 May 26 01:09:38 PM PDT 24 May 26 01:09:41 PM PDT 24 17462848 ps
T544 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.783456043 May 26 01:09:13 PM PDT 24 May 26 01:09:15 PM PDT 24 172582364 ps
T545 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1353006854 May 26 01:09:15 PM PDT 24 May 26 01:09:18 PM PDT 24 43493190 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.896262612 May 26 01:09:14 PM PDT 24 May 26 01:09:16 PM PDT 24 95110656 ps
T547 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.499159576 May 26 01:09:23 PM PDT 24 May 26 01:09:25 PM PDT 24 82695529 ps
T548 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2005039121 May 26 01:09:14 PM PDT 24 May 26 01:09:16 PM PDT 24 107683605 ps
T92 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.249378618 May 26 01:09:09 PM PDT 24 May 26 01:09:11 PM PDT 24 16171866 ps
T549 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2995206780 May 26 01:09:26 PM PDT 24 May 26 01:09:28 PM PDT 24 17048262 ps
T550 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1300941248 May 26 01:09:08 PM PDT 24 May 26 01:09:11 PM PDT 24 57650720 ps
T551 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2543704015 May 26 01:09:23 PM PDT 24 May 26 01:09:25 PM PDT 24 103626282 ps
T552 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2722231483 May 26 01:09:22 PM PDT 24 May 26 01:09:24 PM PDT 24 16100427 ps
T553 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1438063168 May 26 01:09:30 PM PDT 24 May 26 01:09:33 PM PDT 24 14949390 ps
T554 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3217089810 May 26 01:09:21 PM PDT 24 May 26 01:09:24 PM PDT 24 23097748 ps
T555 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2953473088 May 26 01:09:48 PM PDT 24 May 26 01:09:49 PM PDT 24 19928788 ps
T556 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2131957764 May 26 01:09:07 PM PDT 24 May 26 01:09:10 PM PDT 24 2078592311 ps
T557 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.986459943 May 26 01:09:27 PM PDT 24 May 26 01:09:28 PM PDT 24 45075305 ps
T558 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1299178328 May 26 01:09:39 PM PDT 24 May 26 01:09:43 PM PDT 24 349651446 ps
T559 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1268328769 May 26 01:09:22 PM PDT 24 May 26 01:09:24 PM PDT 24 14033908 ps
T560 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4013806516 May 26 01:09:20 PM PDT 24 May 26 01:09:22 PM PDT 24 15038517 ps
T561 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3634219230 May 26 01:09:21 PM PDT 24 May 26 01:09:24 PM PDT 24 26392464 ps
T562 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3814219899 May 26 01:09:11 PM PDT 24 May 26 01:09:13 PM PDT 24 239327066 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2926897751 May 26 01:09:56 PM PDT 24 May 26 01:09:59 PM PDT 24 50172689 ps
T564 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1633731270 May 26 01:09:20 PM PDT 24 May 26 01:09:22 PM PDT 24 91293765 ps
T93 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3343464512 May 26 01:09:09 PM PDT 24 May 26 01:09:11 PM PDT 24 18392108 ps
T565 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2476706649 May 26 01:09:22 PM PDT 24 May 26 01:09:25 PM PDT 24 19128097 ps
T566 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3135871715 May 26 01:09:06 PM PDT 24 May 26 01:09:08 PM PDT 24 12668642 ps
T567 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2739600989 May 26 01:09:07 PM PDT 24 May 26 01:09:09 PM PDT 24 177403019 ps
T568 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2846059168 May 26 01:09:14 PM PDT 24 May 26 01:09:16 PM PDT 24 43667080 ps
T569 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1955080840 May 26 01:09:26 PM PDT 24 May 26 01:09:31 PM PDT 24 177168908 ps
T570 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3993087137 May 26 01:09:29 PM PDT 24 May 26 01:09:31 PM PDT 24 31738615 ps
T571 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.281675880 May 26 01:09:52 PM PDT 24 May 26 01:09:55 PM PDT 24 130774840 ps
T94 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3621462419 May 26 01:09:20 PM PDT 24 May 26 01:09:22 PM PDT 24 29886764 ps
T95 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2648028504 May 26 01:09:23 PM PDT 24 May 26 01:09:26 PM PDT 24 18637889 ps
T572 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.954918155 May 26 01:09:21 PM PDT 24 May 26 01:09:24 PM PDT 24 101799972 ps
T573 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2542928516 May 26 01:09:32 PM PDT 24 May 26 01:09:35 PM PDT 24 15334694 ps
T574 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2250503519 May 26 01:09:57 PM PDT 24 May 26 01:10:01 PM PDT 24 498253753 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3034981332 May 26 01:09:02 PM PDT 24 May 26 01:09:04 PM PDT 24 17755132 ps
T576 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3090834017 May 26 01:09:06 PM PDT 24 May 26 01:09:08 PM PDT 24 99017327 ps
T577 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2540196135 May 26 01:09:26 PM PDT 24 May 26 01:09:30 PM PDT 24 158260564 ps
T578 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1988789655 May 26 01:09:04 PM PDT 24 May 26 01:09:06 PM PDT 24 39864556 ps

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1229952495
Short name T9
Test name
Test status
Simulation time 91465683709 ps
CPU time 274.93 seconds
Started May 26 02:27:08 PM PDT 24
Finished May 26 02:31:43 PM PDT 24
Peak memory 197344 kb
Host smart-0bd4a9b0-ef0d-49df-a68e-43e56d4dab29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229952495 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1229952495
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1706411277
Short name T41
Test name
Test status
Simulation time 722763603360 ps
CPU time 1366.93 seconds
Started May 26 02:28:04 PM PDT 24
Finished May 26 02:50:52 PM PDT 24
Peak memory 195428 kb
Host smart-780e06ba-0c63-4c58-8414-92e67fe9f709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706411277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1706411277
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.4171418654
Short name T65
Test name
Test status
Simulation time 1813194852007 ps
CPU time 2447.12 seconds
Started May 26 02:27:26 PM PDT 24
Finished May 26 03:08:15 PM PDT 24
Peak memory 190900 kb
Host smart-b7034fd3-6512-49ff-919b-6e83e31b3265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171418654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.4171418654
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3770782768
Short name T27
Test name
Test status
Simulation time 402093809 ps
CPU time 1.34 seconds
Started May 26 01:09:33 PM PDT 24
Finished May 26 01:09:36 PM PDT 24
Peak memory 195484 kb
Host smart-a51b7773-f52f-4019-a411-f8d0362f6c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770782768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3770782768
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.268520739
Short name T7
Test name
Test status
Simulation time 1467194579298 ps
CPU time 967.82 seconds
Started May 26 02:27:26 PM PDT 24
Finished May 26 02:43:35 PM PDT 24
Peak memory 190904 kb
Host smart-1f3254ad-04d1-45bb-b6f2-0bfb111c9ee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268520739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
268520739
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3419391135
Short name T117
Test name
Test status
Simulation time 7874779748448 ps
CPU time 2650.12 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 03:11:48 PM PDT 24
Peak memory 190900 kb
Host smart-16d47eee-eb0f-463d-ab0e-508bdcc02ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419391135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3419391135
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1430343140
Short name T217
Test name
Test status
Simulation time 595624550983 ps
CPU time 2360.08 seconds
Started May 26 02:27:27 PM PDT 24
Finished May 26 03:06:49 PM PDT 24
Peak memory 190904 kb
Host smart-15b89e7f-3067-4d78-926d-a8033f50ff16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430343140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1430343140
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3450787069
Short name T291
Test name
Test status
Simulation time 3160054352276 ps
CPU time 2246.45 seconds
Started May 26 02:27:23 PM PDT 24
Finished May 26 03:04:51 PM PDT 24
Peak memory 190832 kb
Host smart-2a5444be-26ca-4daa-8b56-2a137a3a1a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450787069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3450787069
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2045964478
Short name T83
Test name
Test status
Simulation time 24635011 ps
CPU time 0.64 seconds
Started May 26 01:09:44 PM PDT 24
Finished May 26 01:09:47 PM PDT 24
Peak memory 182180 kb
Host smart-1ae8c897-5070-449d-a4d9-d6419f81afc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045964478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2045964478
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1155677795
Short name T67
Test name
Test status
Simulation time 279840881887 ps
CPU time 514.27 seconds
Started May 26 02:27:28 PM PDT 24
Finished May 26 02:36:03 PM PDT 24
Peak memory 190932 kb
Host smart-f449f9e0-a11b-47a7-b259-e9a742be30a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155677795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1155677795
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.835788017
Short name T170
Test name
Test status
Simulation time 273603934587 ps
CPU time 736.41 seconds
Started May 26 02:27:18 PM PDT 24
Finished May 26 02:39:36 PM PDT 24
Peak memory 190916 kb
Host smart-cb60905f-6f5b-4f59-8b7a-777d517c3fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835788017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
835788017
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.616197956
Short name T71
Test name
Test status
Simulation time 713556930912 ps
CPU time 1810.8 seconds
Started May 26 02:27:32 PM PDT 24
Finished May 26 02:57:44 PM PDT 24
Peak memory 190908 kb
Host smart-41f3d302-7913-4226-be9c-627ac4adb26e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616197956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
616197956
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3099487573
Short name T118
Test name
Test status
Simulation time 713310338172 ps
CPU time 1442.42 seconds
Started May 26 02:28:17 PM PDT 24
Finished May 26 02:52:20 PM PDT 24
Peak memory 190908 kb
Host smart-0b2a5bd2-47f3-4bba-b148-74e5b5a4171e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099487573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3099487573
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3831092921
Short name T15
Test name
Test status
Simulation time 67876297 ps
CPU time 0.91 seconds
Started May 26 02:27:02 PM PDT 24
Finished May 26 02:27:04 PM PDT 24
Peak memory 213228 kb
Host smart-8045881a-a880-4e4a-9fba-c784dbc7041a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831092921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3831092921
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/136.rv_timer_random.2961879438
Short name T131
Test name
Test status
Simulation time 211354383823 ps
CPU time 332.99 seconds
Started May 26 02:29:06 PM PDT 24
Finished May 26 02:34:40 PM PDT 24
Peak memory 191088 kb
Host smart-bb214201-d119-4e33-893d-d66f6c125510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961879438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2961879438
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.234257423
Short name T184
Test name
Test status
Simulation time 464599642420 ps
CPU time 1107.15 seconds
Started May 26 02:27:28 PM PDT 24
Finished May 26 02:45:57 PM PDT 24
Peak memory 190900 kb
Host smart-d5cead6c-d336-417f-9ddb-9484f473e9f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234257423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
234257423
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.626862946
Short name T69
Test name
Test status
Simulation time 311836835766 ps
CPU time 588.8 seconds
Started May 26 02:27:12 PM PDT 24
Finished May 26 02:37:01 PM PDT 24
Peak memory 191100 kb
Host smart-bfc8fbd4-f7af-4d2a-bb9f-b4df611e23ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626862946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
626862946
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3856661352
Short name T48
Test name
Test status
Simulation time 68440384 ps
CPU time 0.84 seconds
Started May 26 01:09:13 PM PDT 24
Finished May 26 01:09:15 PM PDT 24
Peak memory 196756 kb
Host smart-caaa3a20-e346-4d09-a308-bf2643a8b220
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856661352 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3856661352
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4097402701
Short name T253
Test name
Test status
Simulation time 393965089101 ps
CPU time 4859.51 seconds
Started May 26 02:27:25 PM PDT 24
Finished May 26 03:48:27 PM PDT 24
Peak memory 190904 kb
Host smart-fc32d222-3d42-4b4c-9553-4ff29340d2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097402701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4097402701
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.3922936241
Short name T339
Test name
Test status
Simulation time 894401210307 ps
CPU time 904.27 seconds
Started May 26 02:29:30 PM PDT 24
Finished May 26 02:44:35 PM PDT 24
Peak memory 190904 kb
Host smart-d57fead3-071d-4a33-9354-5ab864260e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922936241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3922936241
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3032694181
Short name T8
Test name
Test status
Simulation time 118357064133 ps
CPU time 1145.26 seconds
Started May 26 02:28:15 PM PDT 24
Finished May 26 02:47:21 PM PDT 24
Peak memory 190892 kb
Host smart-65cf2dcd-5ca8-4932-8975-dd622a44c2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032694181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3032694181
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.595009080
Short name T219
Test name
Test status
Simulation time 280858236512 ps
CPU time 145.27 seconds
Started May 26 02:28:30 PM PDT 24
Finished May 26 02:30:56 PM PDT 24
Peak memory 190888 kb
Host smart-449da9ce-8282-45ec-b4bf-9fe24cf33cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595009080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.595009080
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3663326883
Short name T306
Test name
Test status
Simulation time 2982577542672 ps
CPU time 2510.05 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 03:09:04 PM PDT 24
Peak memory 190896 kb
Host smart-eec98123-c7a3-43c7-8fa6-b846f023647d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663326883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3663326883
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3955714649
Short name T260
Test name
Test status
Simulation time 2131276506530 ps
CPU time 1654.93 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:55:12 PM PDT 24
Peak memory 190844 kb
Host smart-19e0698e-e807-4a27-bb0a-ccffdaf7f799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955714649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3955714649
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/146.rv_timer_random.3405722072
Short name T271
Test name
Test status
Simulation time 195565932646 ps
CPU time 412.7 seconds
Started May 26 02:29:15 PM PDT 24
Finished May 26 02:36:09 PM PDT 24
Peak memory 190952 kb
Host smart-8b66a12b-6857-41dc-9036-daff09705f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405722072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3405722072
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1734007993
Short name T163
Test name
Test status
Simulation time 527735079963 ps
CPU time 382.26 seconds
Started May 26 02:28:30 PM PDT 24
Finished May 26 02:34:53 PM PDT 24
Peak memory 190900 kb
Host smart-9443afe4-bd41-4bc9-9fe7-ba811a64e58d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734007993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1734007993
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3110986853
Short name T307
Test name
Test status
Simulation time 645316537772 ps
CPU time 317.93 seconds
Started May 26 02:28:45 PM PDT 24
Finished May 26 02:34:03 PM PDT 24
Peak memory 190832 kb
Host smart-f4d9e2f1-3f08-4774-a142-9dc6835dccb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110986853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3110986853
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.3208369944
Short name T330
Test name
Test status
Simulation time 169964332716 ps
CPU time 565.4 seconds
Started May 26 02:26:57 PM PDT 24
Finished May 26 02:36:24 PM PDT 24
Peak memory 190900 kb
Host smart-2499372b-d637-4e2f-942a-5d9e5956f552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208369944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3208369944
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random.1021041928
Short name T231
Test name
Test status
Simulation time 102823898102 ps
CPU time 186.33 seconds
Started May 26 02:27:41 PM PDT 24
Finished May 26 02:30:48 PM PDT 24
Peak memory 190892 kb
Host smart-5258bfb0-9495-4980-bd8a-981c8dcc3566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021041928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1021041928
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3683270419
Short name T38
Test name
Test status
Simulation time 370355943183 ps
CPU time 1157.44 seconds
Started May 26 02:27:02 PM PDT 24
Finished May 26 02:46:20 PM PDT 24
Peak memory 205484 kb
Host smart-09cb7278-8a05-4313-8299-15f63ad93630
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683270419 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3683270419
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.rv_timer_random.3023758728
Short name T119
Test name
Test status
Simulation time 105609183517 ps
CPU time 586.35 seconds
Started May 26 02:29:10 PM PDT 24
Finished May 26 02:38:57 PM PDT 24
Peak memory 190880 kb
Host smart-0957c3f8-ffdd-4635-bbbe-60f9060f7ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023758728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3023758728
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.956351103
Short name T164
Test name
Test status
Simulation time 1672408075797 ps
CPU time 1248.09 seconds
Started May 26 02:28:01 PM PDT 24
Finished May 26 02:48:50 PM PDT 24
Peak memory 190900 kb
Host smart-4b189e49-1136-4b32-9400-04b54db68212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956351103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
956351103
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.434353285
Short name T232
Test name
Test status
Simulation time 552737363315 ps
CPU time 1375.35 seconds
Started May 26 02:29:09 PM PDT 24
Finished May 26 02:52:05 PM PDT 24
Peak memory 190908 kb
Host smart-eb1ce922-17fa-44ae-9349-cb0e76274a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434353285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.434353285
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.442739733
Short name T211
Test name
Test status
Simulation time 44803041451 ps
CPU time 100.57 seconds
Started May 26 02:29:17 PM PDT 24
Finished May 26 02:30:58 PM PDT 24
Peak memory 190864 kb
Host smart-12ca59b7-39d5-45ea-b457-dceff9d740c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442739733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.442739733
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2867249816
Short name T196
Test name
Test status
Simulation time 456127171746 ps
CPU time 296.11 seconds
Started May 26 02:29:17 PM PDT 24
Finished May 26 02:34:14 PM PDT 24
Peak memory 190852 kb
Host smart-ae8a4410-b689-4462-8cd5-575b63b4ca10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867249816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2867249816
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3020889925
Short name T177
Test name
Test status
Simulation time 1085914563873 ps
CPU time 840.07 seconds
Started May 26 02:27:02 PM PDT 24
Finished May 26 02:41:03 PM PDT 24
Peak memory 190904 kb
Host smart-cc58cb64-fcbc-4f01-be36-b492e7b40cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020889925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3020889925
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.768733041
Short name T222
Test name
Test status
Simulation time 890436263694 ps
CPU time 333.31 seconds
Started May 26 02:28:31 PM PDT 24
Finished May 26 02:34:05 PM PDT 24
Peak memory 194180 kb
Host smart-26c61b27-2456-495c-bebe-37edf74ac10a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768733041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.768733041
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3145968959
Short name T143
Test name
Test status
Simulation time 65385444210 ps
CPU time 339.48 seconds
Started May 26 02:28:37 PM PDT 24
Finished May 26 02:34:18 PM PDT 24
Peak memory 190904 kb
Host smart-dac10a7b-3dcb-46da-897e-893da6c1ede8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145968959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3145968959
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1449137205
Short name T450
Test name
Test status
Simulation time 121164540200 ps
CPU time 211.23 seconds
Started May 26 02:28:55 PM PDT 24
Finished May 26 02:32:27 PM PDT 24
Peak memory 191072 kb
Host smart-b826cf85-2701-4a0f-a18c-36a47013de30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449137205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1449137205
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2633753744
Short name T237
Test name
Test status
Simulation time 487572979503 ps
CPU time 260.42 seconds
Started May 26 02:27:05 PM PDT 24
Finished May 26 02:31:26 PM PDT 24
Peak memory 182688 kb
Host smart-e1c38cfe-d398-4457-8bf1-5878882a5bc2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633753744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2633753744
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.752018389
Short name T320
Test name
Test status
Simulation time 201559801868 ps
CPU time 333.28 seconds
Started May 26 02:27:17 PM PDT 24
Finished May 26 02:32:51 PM PDT 24
Peak memory 182720 kb
Host smart-dd741fe0-8056-494f-97bc-c1ec5f18139c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752018389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.752018389
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/156.rv_timer_random.2230010393
Short name T229
Test name
Test status
Simulation time 102691178875 ps
CPU time 170.23 seconds
Started May 26 02:29:14 PM PDT 24
Finished May 26 02:32:05 PM PDT 24
Peak memory 190900 kb
Host smart-955bb859-ad42-408e-8078-bf05421ce2d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230010393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2230010393
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.775941024
Short name T235
Test name
Test status
Simulation time 470596287981 ps
CPU time 3089.2 seconds
Started May 26 02:29:21 PM PDT 24
Finished May 26 03:20:51 PM PDT 24
Peak memory 190836 kb
Host smart-3785e346-4258-4da1-a9c2-6558877c68cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775941024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.775941024
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.312504979
Short name T6
Test name
Test status
Simulation time 426277013663 ps
CPU time 221.14 seconds
Started May 26 02:29:38 PM PDT 24
Finished May 26 02:33:19 PM PDT 24
Peak memory 190900 kb
Host smart-21fe3a1f-e8fc-4418-9621-9fc362355511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312504979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.312504979
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.588810489
Short name T370
Test name
Test status
Simulation time 96911335200 ps
CPU time 502.88 seconds
Started May 26 02:27:46 PM PDT 24
Finished May 26 02:36:09 PM PDT 24
Peak memory 194456 kb
Host smart-3868c700-9e80-43b2-8391-da00340bcf89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588810489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
588810489
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.1868401279
Short name T210
Test name
Test status
Simulation time 467546773057 ps
CPU time 393.66 seconds
Started May 26 02:28:55 PM PDT 24
Finished May 26 02:35:29 PM PDT 24
Peak memory 190952 kb
Host smart-32925dae-8d0f-4a40-88d1-4f130c0841b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868401279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1868401279
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.240494230
Short name T234
Test name
Test status
Simulation time 525810815751 ps
CPU time 257.96 seconds
Started May 26 02:29:15 PM PDT 24
Finished May 26 02:33:34 PM PDT 24
Peak memory 190900 kb
Host smart-28b39245-8917-4043-8e2e-714c511aa11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240494230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.240494230
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.2343637017
Short name T284
Test name
Test status
Simulation time 1570983598198 ps
CPU time 2094.55 seconds
Started May 26 02:27:17 PM PDT 24
Finished May 26 03:02:13 PM PDT 24
Peak memory 190924 kb
Host smart-1ba3bbe2-2fda-4fb5-a9c8-e8cb08c6ae76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343637017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2343637017
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2275305730
Short name T130
Test name
Test status
Simulation time 732312126571 ps
CPU time 2520.28 seconds
Started May 26 02:29:15 PM PDT 24
Finished May 26 03:11:16 PM PDT 24
Peak memory 191072 kb
Host smart-7fb0af74-5b63-49ea-b003-2d02ea870d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275305730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2275305730
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.836881920
Short name T263
Test name
Test status
Simulation time 195843482100 ps
CPU time 787.37 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 02:40:21 PM PDT 24
Peak memory 190888 kb
Host smart-5e586e1e-3501-4197-94fe-7010a03393c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836881920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.836881920
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1041119824
Short name T124
Test name
Test status
Simulation time 285388664573 ps
CPU time 213.47 seconds
Started May 26 02:27:11 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 190928 kb
Host smart-e9c4bb2d-4092-4a90-8a98-e67b8846fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041119824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1041119824
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_random.3994363101
Short name T268
Test name
Test status
Simulation time 806279652589 ps
CPU time 487.12 seconds
Started May 26 02:27:27 PM PDT 24
Finished May 26 02:35:36 PM PDT 24
Peak memory 190892 kb
Host smart-42b55280-713b-4361-a566-0bbdd5c068b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994363101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3994363101
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2456340251
Short name T167
Test name
Test status
Simulation time 226923490664 ps
CPU time 349.49 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:33:27 PM PDT 24
Peak memory 190860 kb
Host smart-4af5d395-9819-46a0-a33f-041f71821769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456340251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2456340251
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2751926496
Short name T68
Test name
Test status
Simulation time 2275341157550 ps
CPU time 759.62 seconds
Started May 26 02:28:03 PM PDT 24
Finished May 26 02:40:43 PM PDT 24
Peak memory 194656 kb
Host smart-202f62ee-fead-40ef-a6fc-8fe1297f9e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751926496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2751926496
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2111113524
Short name T29
Test name
Test status
Simulation time 525624413 ps
CPU time 1.54 seconds
Started May 26 01:09:05 PM PDT 24
Finished May 26 01:09:08 PM PDT 24
Peak memory 195180 kb
Host smart-e239dadf-2151-4466-985a-07e8f572f7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111113524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2111113524
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/104.rv_timer_random.1946034897
Short name T76
Test name
Test status
Simulation time 497157795984 ps
CPU time 613.41 seconds
Started May 26 02:28:55 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 190904 kb
Host smart-fe174dcc-5dfa-43f7-abd0-bb865a91ae83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946034897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1946034897
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1942430948
Short name T272
Test name
Test status
Simulation time 200815647861 ps
CPU time 176.01 seconds
Started May 26 02:29:03 PM PDT 24
Finished May 26 02:31:59 PM PDT 24
Peak memory 190856 kb
Host smart-0b7227c8-b6db-4f87-a24a-ccb4e56e22bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942430948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1942430948
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3504427880
Short name T137
Test name
Test status
Simulation time 713264660217 ps
CPU time 556.81 seconds
Started May 26 02:29:01 PM PDT 24
Finished May 26 02:38:18 PM PDT 24
Peak memory 190896 kb
Host smart-b71eaa05-c94e-4cab-915c-52c34577c504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504427880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3504427880
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.4107555497
Short name T223
Test name
Test status
Simulation time 649826095053 ps
CPU time 877.78 seconds
Started May 26 02:29:01 PM PDT 24
Finished May 26 02:43:39 PM PDT 24
Peak memory 190904 kb
Host smart-d3b760b6-fba7-4f75-b6bc-145e9d6a840d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107555497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.4107555497
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1573110406
Short name T187
Test name
Test status
Simulation time 136847897192 ps
CPU time 28.79 seconds
Started May 26 02:27:03 PM PDT 24
Finished May 26 02:27:32 PM PDT 24
Peak memory 194332 kb
Host smart-a3a272a7-5e0e-42a9-a7ef-b7b735c64711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573110406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1573110406
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/134.rv_timer_random.4122567762
Short name T215
Test name
Test status
Simulation time 736286136618 ps
CPU time 3284.41 seconds
Started May 26 02:29:08 PM PDT 24
Finished May 26 03:23:53 PM PDT 24
Peak memory 190852 kb
Host smart-6add7d12-59bf-46ba-9d60-475f53b3cab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122567762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.4122567762
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1057316900
Short name T364
Test name
Test status
Simulation time 129201120243 ps
CPU time 221.01 seconds
Started May 26 02:29:15 PM PDT 24
Finished May 26 02:32:57 PM PDT 24
Peak memory 190860 kb
Host smart-ba751c2e-a7fb-47b9-8cd9-a3c9a892bc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057316900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1057316900
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3196831152
Short name T362
Test name
Test status
Simulation time 278799790759 ps
CPU time 204.82 seconds
Started May 26 02:29:14 PM PDT 24
Finished May 26 02:32:40 PM PDT 24
Peak memory 190872 kb
Host smart-4cdb86df-f134-4a8a-88ee-45f73ad4f0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196831152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3196831152
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3080811985
Short name T326
Test name
Test status
Simulation time 105118086176 ps
CPU time 115.81 seconds
Started May 26 02:29:14 PM PDT 24
Finished May 26 02:31:11 PM PDT 24
Peak memory 190828 kb
Host smart-83bee944-7ef4-4b57-a889-b14d805edc7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080811985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3080811985
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2251884975
Short name T276
Test name
Test status
Simulation time 281877829211 ps
CPU time 229.01 seconds
Started May 26 02:29:16 PM PDT 24
Finished May 26 02:33:06 PM PDT 24
Peak memory 190888 kb
Host smart-041c4c94-cfe0-44f8-a03a-032a18663435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251884975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2251884975
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1652430753
Short name T182
Test name
Test status
Simulation time 2926606794799 ps
CPU time 1221.52 seconds
Started May 26 02:29:30 PM PDT 24
Finished May 26 02:49:52 PM PDT 24
Peak memory 190896 kb
Host smart-2fedf8bd-4fe3-4341-9c02-ea67441adb48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652430753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1652430753
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1096511450
Short name T102
Test name
Test status
Simulation time 4682577689991 ps
CPU time 1068.75 seconds
Started May 26 02:27:35 PM PDT 24
Finished May 26 02:45:25 PM PDT 24
Peak memory 190836 kb
Host smart-45aa7472-511e-45a3-b194-852f8e43ff58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096511450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1096511450
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_random.4215349922
Short name T173
Test name
Test status
Simulation time 731095915710 ps
CPU time 670 seconds
Started May 26 02:27:34 PM PDT 24
Finished May 26 02:38:45 PM PDT 24
Peak memory 190900 kb
Host smart-ba5346ef-82bc-4eff-b851-85f660728594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215349922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4215349922
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1042537533
Short name T103
Test name
Test status
Simulation time 970121780515 ps
CPU time 373.56 seconds
Started May 26 02:27:35 PM PDT 24
Finished May 26 02:33:50 PM PDT 24
Peak memory 182728 kb
Host smart-ef330845-91dc-45dc-b4c8-5394f5328b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042537533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1042537533
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2456842195
Short name T174
Test name
Test status
Simulation time 286561829120 ps
CPU time 433.92 seconds
Started May 26 02:27:59 PM PDT 24
Finished May 26 02:35:14 PM PDT 24
Peak memory 182724 kb
Host smart-1775f815-5914-4947-8362-bb0dd56bfa1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456842195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2456842195
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1327531233
Short name T294
Test name
Test status
Simulation time 401960547775 ps
CPU time 189.95 seconds
Started May 26 02:27:00 PM PDT 24
Finished May 26 02:30:12 PM PDT 24
Peak memory 190908 kb
Host smart-3adda664-11c8-49ca-bf6a-8450f0f018e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327531233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1327531233
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.766661476
Short name T238
Test name
Test status
Simulation time 308087976609 ps
CPU time 292.89 seconds
Started May 26 02:27:01 PM PDT 24
Finished May 26 02:31:55 PM PDT 24
Peak memory 182656 kb
Host smart-f78351ce-21f8-4c18-bf2f-75d409463890
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766661476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.766661476
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/94.rv_timer_random.1133192076
Short name T329
Test name
Test status
Simulation time 157020118997 ps
CPU time 432.62 seconds
Started May 26 02:28:45 PM PDT 24
Finished May 26 02:35:58 PM PDT 24
Peak memory 190928 kb
Host smart-3a69148f-6ea1-40bc-8d68-49a58ebbe9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133192076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1133192076
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1056695193
Short name T129
Test name
Test status
Simulation time 130913985630 ps
CPU time 253.86 seconds
Started May 26 02:28:47 PM PDT 24
Finished May 26 02:33:02 PM PDT 24
Peak memory 190908 kb
Host smart-f0bb4361-b74b-4d71-9c68-4768f52616ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056695193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1056695193
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1045356833
Short name T328
Test name
Test status
Simulation time 289251327379 ps
CPU time 224.37 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:30:45 PM PDT 24
Peak memory 182720 kb
Host smart-31bafa0a-4855-49a2-9a83-60c36005c95d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045356833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1045356833
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.718090369
Short name T162
Test name
Test status
Simulation time 275094854324 ps
CPU time 300.71 seconds
Started May 26 02:27:04 PM PDT 24
Finished May 26 02:32:06 PM PDT 24
Peak memory 182708 kb
Host smart-bfde4620-bbb3-4fe9-951a-c7699562baad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718090369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.718090369
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2545305208
Short name T331
Test name
Test status
Simulation time 31575222027 ps
CPU time 27.8 seconds
Started May 26 02:27:17 PM PDT 24
Finished May 26 02:27:45 PM PDT 24
Peak memory 190892 kb
Host smart-1341bfdf-e510-4f64-bf3e-b5e2e27c20e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545305208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2545305208
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/105.rv_timer_random.2388529017
Short name T109
Test name
Test status
Simulation time 594180707472 ps
CPU time 797.49 seconds
Started May 26 02:28:53 PM PDT 24
Finished May 26 02:42:11 PM PDT 24
Peak memory 190896 kb
Host smart-e18f5142-509b-41bc-aba0-abced952e107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388529017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2388529017
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.4191765780
Short name T288
Test name
Test status
Simulation time 174251946588 ps
CPU time 293.94 seconds
Started May 26 02:28:53 PM PDT 24
Finished May 26 02:33:48 PM PDT 24
Peak memory 190888 kb
Host smart-38c8743d-2370-4f37-8588-a902172ea2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191765780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.4191765780
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1373743124
Short name T171
Test name
Test status
Simulation time 561411702455 ps
CPU time 601.02 seconds
Started May 26 02:27:05 PM PDT 24
Finished May 26 02:37:07 PM PDT 24
Peak memory 190932 kb
Host smart-0c2bfc03-fe21-4f19-ad7b-835f484566a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373743124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1373743124
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1866836898
Short name T301
Test name
Test status
Simulation time 86215151453 ps
CPU time 420.11 seconds
Started May 26 02:29:01 PM PDT 24
Finished May 26 02:36:02 PM PDT 24
Peak memory 190900 kb
Host smart-ce825867-0757-4312-9fe7-58b84a091b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866836898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1866836898
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3674302788
Short name T367
Test name
Test status
Simulation time 9324812300 ps
CPU time 37.83 seconds
Started May 26 02:29:00 PM PDT 24
Finished May 26 02:29:38 PM PDT 24
Peak memory 193500 kb
Host smart-a4fe007c-76c4-48ee-a219-31e487d80092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674302788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3674302788
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1856710245
Short name T298
Test name
Test status
Simulation time 322025773824 ps
CPU time 698.23 seconds
Started May 26 02:27:06 PM PDT 24
Finished May 26 02:38:45 PM PDT 24
Peak memory 190904 kb
Host smart-02e31dfa-4789-4107-93a5-e855c2545019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856710245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1856710245
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/127.rv_timer_random.1126229659
Short name T248
Test name
Test status
Simulation time 81097783 ps
CPU time 0.66 seconds
Started May 26 02:29:02 PM PDT 24
Finished May 26 02:29:03 PM PDT 24
Peak memory 182476 kb
Host smart-23fa8d5b-e76c-4537-9e0e-f8e3a7a72205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126229659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1126229659
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.461059788
Short name T279
Test name
Test status
Simulation time 152218976966 ps
CPU time 1351.32 seconds
Started May 26 02:29:16 PM PDT 24
Finished May 26 02:51:48 PM PDT 24
Peak memory 182636 kb
Host smart-76cd8ce2-f20a-400b-9190-cd24071e4f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461059788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.461059788
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2440430540
Short name T434
Test name
Test status
Simulation time 207943432960 ps
CPU time 174.88 seconds
Started May 26 02:29:22 PM PDT 24
Finished May 26 02:32:18 PM PDT 24
Peak memory 190888 kb
Host smart-26b80468-3148-4826-82e5-7fe0306a05a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440430540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2440430540
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1201943255
Short name T73
Test name
Test status
Simulation time 217971864019 ps
CPU time 391.36 seconds
Started May 26 02:27:19 PM PDT 24
Finished May 26 02:33:51 PM PDT 24
Peak memory 182744 kb
Host smart-6ac547a3-c3dd-41bb-9845-4de1bd5a67cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201943255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1201943255
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_random.4170850970
Short name T154
Test name
Test status
Simulation time 128400585770 ps
CPU time 438.78 seconds
Started May 26 02:27:12 PM PDT 24
Finished May 26 02:34:32 PM PDT 24
Peak memory 190856 kb
Host smart-46ef2c68-6730-45b6-8927-91bfd5657d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170850970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4170850970
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3909325332
Short name T314
Test name
Test status
Simulation time 80908754683 ps
CPU time 100.81 seconds
Started May 26 02:29:23 PM PDT 24
Finished May 26 02:31:05 PM PDT 24
Peak memory 190888 kb
Host smart-eb5a165b-9670-44bb-8ec2-8c2832184baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909325332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3909325332
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3208812148
Short name T243
Test name
Test status
Simulation time 117318097248 ps
CPU time 414.86 seconds
Started May 26 02:29:29 PM PDT 24
Finished May 26 02:36:25 PM PDT 24
Peak memory 194460 kb
Host smart-f9910eff-31fd-4507-92df-a24cc6d97c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208812148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3208812148
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.2913221680
Short name T185
Test name
Test status
Simulation time 148130697632 ps
CPU time 508.45 seconds
Started May 26 02:29:29 PM PDT 24
Finished May 26 02:37:59 PM PDT 24
Peak memory 190892 kb
Host smart-5a9cc1a9-0ae9-49ec-816a-f2e82d169881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913221680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2913221680
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.4134991652
Short name T258
Test name
Test status
Simulation time 414618540577 ps
CPU time 431.06 seconds
Started May 26 02:29:30 PM PDT 24
Finished May 26 02:36:41 PM PDT 24
Peak memory 190876 kb
Host smart-d4a2003b-14d9-4ab9-8e65-4db3ddc0bd15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134991652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.4134991652
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.322773300
Short name T245
Test name
Test status
Simulation time 75329029543 ps
CPU time 866.97 seconds
Started May 26 02:29:30 PM PDT 24
Finished May 26 02:43:58 PM PDT 24
Peak memory 190900 kb
Host smart-963e3e90-162a-4f77-b59c-75be2eee52e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322773300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.322773300
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2128998253
Short name T200
Test name
Test status
Simulation time 1088437406588 ps
CPU time 930.28 seconds
Started May 26 02:26:57 PM PDT 24
Finished May 26 02:42:28 PM PDT 24
Peak memory 182696 kb
Host smart-32c8a109-fa48-4de5-8e1f-fb15ffa9259d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128998253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2128998253
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.2385098784
Short name T150
Test name
Test status
Simulation time 192367560946 ps
CPU time 150.65 seconds
Started May 26 02:27:22 PM PDT 24
Finished May 26 02:29:54 PM PDT 24
Peak memory 190900 kb
Host smart-7dca94ae-9897-457b-b314-031a39930145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385098784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2385098784
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1510526469
Short name T269
Test name
Test status
Simulation time 117379026776 ps
CPU time 201.35 seconds
Started May 26 02:27:22 PM PDT 24
Finished May 26 02:30:44 PM PDT 24
Peak memory 182744 kb
Host smart-28d30ee6-65d0-4214-9541-4c4cb4044ad0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510526469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1510526469
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.3290936755
Short name T169
Test name
Test status
Simulation time 138165129415 ps
CPU time 313.99 seconds
Started May 26 02:27:25 PM PDT 24
Finished May 26 02:32:40 PM PDT 24
Peak memory 193024 kb
Host smart-b9f95c60-94c0-4fd8-b728-9918498c16bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290936755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3290936755
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.2889395714
Short name T321
Test name
Test status
Simulation time 126571308498 ps
CPU time 128.65 seconds
Started May 26 02:27:28 PM PDT 24
Finished May 26 02:29:38 PM PDT 24
Peak memory 190904 kb
Host smart-e228acf2-a4f8-4c81-846c-192b60e05856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889395714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2889395714
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2176671982
Short name T311
Test name
Test status
Simulation time 411407895395 ps
CPU time 632.95 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:37:34 PM PDT 24
Peak memory 182564 kb
Host smart-dd5c420d-5646-45da-9929-7f43dbbb26d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176671982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2176671982
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.3504286443
Short name T194
Test name
Test status
Simulation time 202044336242 ps
CPU time 104.01 seconds
Started May 26 02:27:28 PM PDT 24
Finished May 26 02:29:13 PM PDT 24
Peak memory 190884 kb
Host smart-4ee31734-dd5c-49a5-b815-fff8c5b93608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504286443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3504286443
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3448987548
Short name T275
Test name
Test status
Simulation time 185587888947 ps
CPU time 279.34 seconds
Started May 26 02:28:02 PM PDT 24
Finished May 26 02:32:42 PM PDT 24
Peak memory 182716 kb
Host smart-a3042a1f-31d8-4760-a334-55c654ae2c6d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448987548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3448987548
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2827423562
Short name T244
Test name
Test status
Simulation time 363185728566 ps
CPU time 317.67 seconds
Started May 26 02:28:06 PM PDT 24
Finished May 26 02:33:25 PM PDT 24
Peak memory 182720 kb
Host smart-b0175ca0-31d7-4aac-9aab-8bac7f552de6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827423562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2827423562
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/63.rv_timer_random.2299365184
Short name T319
Test name
Test status
Simulation time 73252388379 ps
CPU time 65.78 seconds
Started May 26 02:28:21 PM PDT 24
Finished May 26 02:29:27 PM PDT 24
Peak memory 182732 kb
Host smart-412cfa3d-69d4-4397-a09f-d379a7b208f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299365184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2299365184
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3382388049
Short name T322
Test name
Test status
Simulation time 74606553556 ps
CPU time 121.27 seconds
Started May 26 02:28:30 PM PDT 24
Finished May 26 02:30:32 PM PDT 24
Peak memory 190892 kb
Host smart-e9252c8c-3a84-426c-a1d9-28f3d0a31eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382388049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3382388049
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3874698380
Short name T241
Test name
Test status
Simulation time 71246592229 ps
CPU time 524.8 seconds
Started May 26 02:28:30 PM PDT 24
Finished May 26 02:37:15 PM PDT 24
Peak memory 190904 kb
Host smart-1ab820a0-b74c-4c7c-83c3-0a8f90b88a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874698380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3874698380
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1704228847
Short name T287
Test name
Test status
Simulation time 338057356531 ps
CPU time 55.93 seconds
Started May 26 02:28:40 PM PDT 24
Finished May 26 02:29:36 PM PDT 24
Peak memory 190860 kb
Host smart-e0cf7e79-7086-425f-91a4-87c57b5e5555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704228847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1704228847
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3343464512
Short name T93
Test name
Test status
Simulation time 18392108 ps
CPU time 0.74 seconds
Started May 26 01:09:09 PM PDT 24
Finished May 26 01:09:11 PM PDT 24
Peak memory 192520 kb
Host smart-6870b067-a984-4945-8bd1-e6c8131d4d56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343464512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3343464512
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2967841719
Short name T472
Test name
Test status
Simulation time 130734693 ps
CPU time 1.43 seconds
Started May 26 01:09:04 PM PDT 24
Finished May 26 01:09:07 PM PDT 24
Peak memory 192868 kb
Host smart-9b1315f5-d20b-49ea-90b8-89c54bd62945
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967841719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2967841719
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2846059168
Short name T568
Test name
Test status
Simulation time 43667080 ps
CPU time 0.55 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:16 PM PDT 24
Peak memory 182620 kb
Host smart-266848db-a07b-441c-a4ee-3c6464574623
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846059168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2846059168
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3762540797
Short name T471
Test name
Test status
Simulation time 44512205 ps
CPU time 0.95 seconds
Started May 26 01:09:01 PM PDT 24
Finished May 26 01:09:04 PM PDT 24
Peak memory 196896 kb
Host smart-fd45e5f0-22cf-46ff-b443-1a2261e67a1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762540797 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3762540797
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.121639532
Short name T503
Test name
Test status
Simulation time 14187379 ps
CPU time 0.56 seconds
Started May 26 01:08:57 PM PDT 24
Finished May 26 01:08:58 PM PDT 24
Peak memory 182628 kb
Host smart-d6bc4fc9-34b4-4f42-a911-bbfd955f40be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121639532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.121639532
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2503152117
Short name T478
Test name
Test status
Simulation time 46660600 ps
CPU time 0.55 seconds
Started May 26 01:09:08 PM PDT 24
Finished May 26 01:09:10 PM PDT 24
Peak memory 182508 kb
Host smart-f4c47f2a-13eb-4a1d-a274-be103750e9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503152117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2503152117
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1988789655
Short name T578
Test name
Test status
Simulation time 39864556 ps
CPU time 0.79 seconds
Started May 26 01:09:04 PM PDT 24
Finished May 26 01:09:06 PM PDT 24
Peak memory 193236 kb
Host smart-d5c6e099-3b6b-42e1-9aca-7a336e434770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988789655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1988789655
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3861568243
Short name T487
Test name
Test status
Simulation time 276354597 ps
CPU time 1.53 seconds
Started May 26 01:09:06 PM PDT 24
Finished May 26 01:09:09 PM PDT 24
Peak memory 197560 kb
Host smart-30b9e24b-e0cc-4b15-91ad-8fa872757e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861568243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3861568243
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3621462419
Short name T94
Test name
Test status
Simulation time 29886764 ps
CPU time 0.74 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 182644 kb
Host smart-42be1da9-5fd3-4be5-87c9-96f267e07e4e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621462419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3621462419
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3169276471
Short name T81
Test name
Test status
Simulation time 121324958 ps
CPU time 2.32 seconds
Started May 26 01:08:56 PM PDT 24
Finished May 26 01:08:59 PM PDT 24
Peak memory 192176 kb
Host smart-72e335b3-072f-473d-a736-d70890e7d120
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169276471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3169276471
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3034981332
Short name T575
Test name
Test status
Simulation time 17755132 ps
CPU time 0.58 seconds
Started May 26 01:09:02 PM PDT 24
Finished May 26 01:09:04 PM PDT 24
Peak memory 182744 kb
Host smart-6c88cb4a-96e2-440f-884a-4b4326ee06c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034981332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3034981332
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1353006854
Short name T545
Test name
Test status
Simulation time 43493190 ps
CPU time 0.99 seconds
Started May 26 01:09:15 PM PDT 24
Finished May 26 01:09:18 PM PDT 24
Peak memory 196672 kb
Host smart-f4caaf8b-3f3f-49db-8b4a-3bb8648471a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353006854 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1353006854
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1433039397
Short name T91
Test name
Test status
Simulation time 22582963 ps
CPU time 0.59 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 182640 kb
Host smart-da0774c3-306e-4b64-aa0d-4480ba7d68b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433039397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1433039397
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3362228357
Short name T497
Test name
Test status
Simulation time 26702422 ps
CPU time 0.59 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:23 PM PDT 24
Peak memory 182500 kb
Host smart-df022ec6-2b3d-4c3d-a2f9-8ce2fb65741b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362228357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3362228357
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3814219899
Short name T562
Test name
Test status
Simulation time 239327066 ps
CPU time 0.7 seconds
Started May 26 01:09:11 PM PDT 24
Finished May 26 01:09:13 PM PDT 24
Peak memory 192080 kb
Host smart-40105af5-f945-450b-8017-da98d6e250a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814219899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3814219899
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.610591711
Short name T500
Test name
Test status
Simulation time 188787499 ps
CPU time 1.73 seconds
Started May 26 01:09:01 PM PDT 24
Finished May 26 01:09:04 PM PDT 24
Peak memory 197560 kb
Host smart-c9564c89-8b3e-4bd8-a79f-0bfce90309bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610591711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.610591711
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.938505872
Short name T112
Test name
Test status
Simulation time 243760472 ps
CPU time 0.88 seconds
Started May 26 01:09:01 PM PDT 24
Finished May 26 01:09:04 PM PDT 24
Peak memory 183156 kb
Host smart-79835eda-3f98-4219-b3d7-f4c08618e46b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938505872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.938505872
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.46591001
Short name T485
Test name
Test status
Simulation time 38252968 ps
CPU time 0.55 seconds
Started May 26 01:09:17 PM PDT 24
Finished May 26 01:09:19 PM PDT 24
Peak memory 182368 kb
Host smart-78bbcaa4-0772-4d44-ae08-e3fc0e3120d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46591001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.46591001
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2843895715
Short name T459
Test name
Test status
Simulation time 17690879 ps
CPU time 0.56 seconds
Started May 26 01:09:19 PM PDT 24
Finished May 26 01:09:21 PM PDT 24
Peak memory 182616 kb
Host smart-5630122c-0335-434d-8bbe-ffe9d73f9415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843895715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2843895715
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2383446189
Short name T536
Test name
Test status
Simulation time 23969817 ps
CPU time 0.68 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:17 PM PDT 24
Peak memory 191948 kb
Host smart-9f941988-f727-4ad0-99e1-8563ba3c00f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383446189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2383446189
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1212146974
Short name T528
Test name
Test status
Simulation time 49269419 ps
CPU time 2.31 seconds
Started May 26 01:09:15 PM PDT 24
Finished May 26 01:09:19 PM PDT 24
Peak memory 197816 kb
Host smart-69a6fa3e-634f-4153-b18d-7e6c363fce0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212146974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1212146974
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2132314792
Short name T498
Test name
Test status
Simulation time 247755315 ps
CPU time 0.83 seconds
Started May 26 01:09:23 PM PDT 24
Finished May 26 01:09:26 PM PDT 24
Peak memory 193648 kb
Host smart-a16f01e8-0eac-4571-bcee-b264c10abe11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132314792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2132314792
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.795308552
Short name T510
Test name
Test status
Simulation time 168262787 ps
CPU time 1.28 seconds
Started May 26 01:09:17 PM PDT 24
Finished May 26 01:09:20 PM PDT 24
Peak memory 197532 kb
Host smart-9e229f1d-5c6b-4f36-a3eb-d42f65143cd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795308552 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.795308552
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1266638520
Short name T464
Test name
Test status
Simulation time 60253838 ps
CPU time 0.58 seconds
Started May 26 01:09:16 PM PDT 24
Finished May 26 01:09:19 PM PDT 24
Peak memory 182652 kb
Host smart-ee2c5db5-76d6-412b-956c-6f46dcb5f1a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266638520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1266638520
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3725690507
Short name T495
Test name
Test status
Simulation time 38236880 ps
CPU time 0.52 seconds
Started May 26 01:09:17 PM PDT 24
Finished May 26 01:09:19 PM PDT 24
Peak memory 182108 kb
Host smart-ff964ada-f726-48fa-9c84-ed48e1609d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725690507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3725690507
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.59075939
Short name T506
Test name
Test status
Simulation time 230295409 ps
CPU time 0.64 seconds
Started May 26 01:09:25 PM PDT 24
Finished May 26 01:09:27 PM PDT 24
Peak memory 191396 kb
Host smart-87b30f95-6976-47d9-a3de-de8ed72f3216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59075939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_tim
er_same_csr_outstanding.59075939
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3762812893
Short name T532
Test name
Test status
Simulation time 90165678 ps
CPU time 1.86 seconds
Started May 26 01:09:19 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 197616 kb
Host smart-4d78e0d1-a1d6-4f74-903c-634002ddaf7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762812893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3762812893
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3777702540
Short name T113
Test name
Test status
Simulation time 47539492 ps
CPU time 0.86 seconds
Started May 26 01:09:07 PM PDT 24
Finished May 26 01:09:09 PM PDT 24
Peak memory 193524 kb
Host smart-5e3afda9-e9a9-49d2-8cd7-e982ec4313f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777702540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3777702540
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1139861275
Short name T527
Test name
Test status
Simulation time 75606902 ps
CPU time 0.85 seconds
Started May 26 01:09:26 PM PDT 24
Finished May 26 01:09:28 PM PDT 24
Peak memory 197328 kb
Host smart-9d4f72c8-4463-4e0e-8056-c69cf1c62156
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139861275 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1139861275
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2543704015
Short name T551
Test name
Test status
Simulation time 103626282 ps
CPU time 0.59 seconds
Started May 26 01:09:23 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 182728 kb
Host smart-b2718d98-9a73-41e7-997a-5cc6ed25b07e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543704015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2543704015
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2547873655
Short name T451
Test name
Test status
Simulation time 39587050 ps
CPU time 0.56 seconds
Started May 26 01:09:41 PM PDT 24
Finished May 26 01:09:44 PM PDT 24
Peak memory 182696 kb
Host smart-a065e1d5-241b-422c-9c55-7c917cc8b536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547873655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2547873655
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.45452323
Short name T533
Test name
Test status
Simulation time 31507453 ps
CPU time 0.73 seconds
Started May 26 01:09:39 PM PDT 24
Finished May 26 01:09:43 PM PDT 24
Peak memory 193308 kb
Host smart-b0c827d6-c213-4922-b384-c4eb2eb60efb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45452323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_tim
er_same_csr_outstanding.45452323
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4040186096
Short name T489
Test name
Test status
Simulation time 215261091 ps
CPU time 2.69 seconds
Started May 26 01:09:32 PM PDT 24
Finished May 26 01:09:38 PM PDT 24
Peak memory 197528 kb
Host smart-1ee4cbf1-ab0a-4d20-82c9-05eca3e39843
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040186096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4040186096
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.954918155
Short name T572
Test name
Test status
Simulation time 101799972 ps
CPU time 1.29 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 195336 kb
Host smart-f25ced08-c9c9-4feb-baae-4fcb8ebcc957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954918155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.954918155
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3966573805
Short name T461
Test name
Test status
Simulation time 92191956 ps
CPU time 1.2 seconds
Started May 26 01:09:44 PM PDT 24
Finished May 26 01:09:47 PM PDT 24
Peak memory 196940 kb
Host smart-65984ad8-b406-4a5f-9e8a-debcd1da31d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966573805 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3966573805
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.4013806516
Short name T560
Test name
Test status
Simulation time 15038517 ps
CPU time 0.62 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 182668 kb
Host smart-4f92e6e4-c9bd-4455-9e23-02f1ed7d334b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013806516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.4013806516
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2633804204
Short name T520
Test name
Test status
Simulation time 37640255 ps
CPU time 0.59 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 182500 kb
Host smart-ef1595c9-89af-455a-add1-40f6a171162e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633804204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2633804204
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2540196135
Short name T577
Test name
Test status
Simulation time 158260564 ps
CPU time 0.78 seconds
Started May 26 01:09:26 PM PDT 24
Finished May 26 01:09:30 PM PDT 24
Peak memory 191608 kb
Host smart-81717612-b3ab-4b06-90b8-f038ea6d1070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540196135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2540196135
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1093513115
Short name T494
Test name
Test status
Simulation time 897942045 ps
CPU time 1.71 seconds
Started May 26 01:09:46 PM PDT 24
Finished May 26 01:09:49 PM PDT 24
Peak memory 197704 kb
Host smart-6ce60b36-7924-4732-8cb7-254dd1a50957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093513115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1093513115
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2926897751
Short name T563
Test name
Test status
Simulation time 50172689 ps
CPU time 0.85 seconds
Started May 26 01:09:56 PM PDT 24
Finished May 26 01:09:59 PM PDT 24
Peak memory 183024 kb
Host smart-8a81c135-80be-4ed9-888f-0eb182146bc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926897751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2926897751
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3993087137
Short name T570
Test name
Test status
Simulation time 31738615 ps
CPU time 0.82 seconds
Started May 26 01:09:29 PM PDT 24
Finished May 26 01:09:31 PM PDT 24
Peak memory 196484 kb
Host smart-074b8814-6d52-4a31-a92d-6730f6994212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993087137 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3993087137
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.85264741
Short name T30
Test name
Test status
Simulation time 16128867 ps
CPU time 0.6 seconds
Started May 26 01:09:52 PM PDT 24
Finished May 26 01:09:54 PM PDT 24
Peak memory 182620 kb
Host smart-257273d2-b1b3-432d-a068-6ebc679bbc73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85264741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.85264741
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1221217303
Short name T518
Test name
Test status
Simulation time 19018475 ps
CPU time 0.57 seconds
Started May 26 01:09:22 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 182620 kb
Host smart-088c0734-7d99-4202-87c5-ca15dbb4ee5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221217303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1221217303
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3920421391
Short name T99
Test name
Test status
Simulation time 94515463 ps
CPU time 0.71 seconds
Started May 26 01:09:31 PM PDT 24
Finished May 26 01:09:34 PM PDT 24
Peak memory 193136 kb
Host smart-c479e2fb-1401-4467-a59c-b7af1ab37518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920421391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3920421391
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1955080840
Short name T569
Test name
Test status
Simulation time 177168908 ps
CPU time 3.36 seconds
Started May 26 01:09:26 PM PDT 24
Finished May 26 01:09:31 PM PDT 24
Peak memory 192432 kb
Host smart-f7404551-f769-431a-8ec3-4e311ae90427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955080840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1955080840
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1299178328
Short name T558
Test name
Test status
Simulation time 349651446 ps
CPU time 1.39 seconds
Started May 26 01:09:39 PM PDT 24
Finished May 26 01:09:43 PM PDT 24
Peak memory 195312 kb
Host smart-c71fff5c-b72a-4963-97f8-98941469ec1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299178328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1299178328
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3133897826
Short name T541
Test name
Test status
Simulation time 23498521 ps
CPU time 0.74 seconds
Started May 26 01:09:47 PM PDT 24
Finished May 26 01:09:49 PM PDT 24
Peak memory 195272 kb
Host smart-df96e240-0367-43d5-9ffb-86c94d2961e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133897826 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3133897826
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3761228713
Short name T460
Test name
Test status
Simulation time 20287061 ps
CPU time 0.58 seconds
Started May 26 01:09:47 PM PDT 24
Finished May 26 01:09:48 PM PDT 24
Peak memory 182712 kb
Host smart-38353dbd-84ac-4cc2-9d64-13b596ec4f5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761228713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3761228713
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2284101757
Short name T467
Test name
Test status
Simulation time 14761042 ps
CPU time 0.53 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 182180 kb
Host smart-4c9c6b70-c226-40d1-a026-7c7c85551bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284101757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2284101757
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4065440050
Short name T98
Test name
Test status
Simulation time 52568992 ps
CPU time 0.68 seconds
Started May 26 01:09:19 PM PDT 24
Finished May 26 01:09:21 PM PDT 24
Peak memory 191996 kb
Host smart-58a66ae1-006d-4d30-b292-fc91a31f18e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065440050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4065440050
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3217089810
Short name T554
Test name
Test status
Simulation time 23097748 ps
CPU time 1.1 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 197144 kb
Host smart-6db6bb31-11e6-47b4-8aef-ab887b36ff64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217089810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3217089810
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3784661262
Short name T517
Test name
Test status
Simulation time 81548371 ps
CPU time 1.03 seconds
Started May 26 01:09:42 PM PDT 24
Finished May 26 01:09:45 PM PDT 24
Peak memory 197300 kb
Host smart-2cb761a5-e6d9-4de7-a771-e2468d19e208
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784661262 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3784661262
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3428172770
Short name T540
Test name
Test status
Simulation time 13553634 ps
CPU time 0.57 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:21 PM PDT 24
Peak memory 182684 kb
Host smart-c6728726-3fbb-4fae-93b9-49dfaf18c756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428172770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3428172770
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2338505090
Short name T507
Test name
Test status
Simulation time 33094986 ps
CPU time 0.8 seconds
Started May 26 01:09:37 PM PDT 24
Finished May 26 01:09:41 PM PDT 24
Peak memory 193436 kb
Host smart-b8ae7237-d707-4d46-8ed2-b9c429c7ae77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338505090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2338505090
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.111426860
Short name T49
Test name
Test status
Simulation time 61286654 ps
CPU time 1.16 seconds
Started May 26 01:10:02 PM PDT 24
Finished May 26 01:10:05 PM PDT 24
Peak memory 197148 kb
Host smart-87716ee2-a96f-4dcf-acc0-704bc755f43d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111426860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.111426860
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.281675880
Short name T571
Test name
Test status
Simulation time 130774840 ps
CPU time 1.33 seconds
Started May 26 01:09:52 PM PDT 24
Finished May 26 01:09:55 PM PDT 24
Peak memory 195724 kb
Host smart-52f1f4a6-42e7-45c4-ad0e-324193634058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281675880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.281675880
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1418934736
Short name T501
Test name
Test status
Simulation time 16373045 ps
CPU time 0.79 seconds
Started May 26 01:09:41 PM PDT 24
Finished May 26 01:09:44 PM PDT 24
Peak memory 196400 kb
Host smart-034fdc41-0b7e-423c-a45f-26dda2d6db2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418934736 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1418934736
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.944936935
Short name T457
Test name
Test status
Simulation time 15430617 ps
CPU time 0.55 seconds
Started May 26 01:09:22 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 182636 kb
Host smart-419b737c-dd62-46ad-b60f-15abba3cec58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944936935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.944936935
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.746238440
Short name T452
Test name
Test status
Simulation time 18636353 ps
CPU time 0.58 seconds
Started May 26 01:09:32 PM PDT 24
Finished May 26 01:09:36 PM PDT 24
Peak memory 182848 kb
Host smart-79507411-0fec-4eb2-97a8-9f59f5c64724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746238440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.746238440
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.827880933
Short name T84
Test name
Test status
Simulation time 17043576 ps
CPU time 0.6 seconds
Started May 26 01:09:47 PM PDT 24
Finished May 26 01:09:49 PM PDT 24
Peak memory 191884 kb
Host smart-fc2cf3d4-e098-4c80-8d7c-cd9f043b0c88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827880933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.827880933
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2264995278
Short name T476
Test name
Test status
Simulation time 103653423 ps
CPU time 1.76 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 197460 kb
Host smart-0d9a3821-eda9-41af-8532-541d6068d2d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264995278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2264995278
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1475462090
Short name T28
Test name
Test status
Simulation time 506522769 ps
CPU time 1.14 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:23 PM PDT 24
Peak memory 194792 kb
Host smart-57de4d89-40e5-432f-9799-cca38c3b97f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475462090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1475462090
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2769662572
Short name T473
Test name
Test status
Simulation time 28464860 ps
CPU time 0.83 seconds
Started May 26 01:09:31 PM PDT 24
Finished May 26 01:09:34 PM PDT 24
Peak memory 195932 kb
Host smart-303ea6de-32a1-4f70-be50-2c405452b4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769662572 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2769662572
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2315020924
Short name T529
Test name
Test status
Simulation time 20208910 ps
CPU time 0.56 seconds
Started May 26 01:09:23 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 182652 kb
Host smart-1f138a70-6f31-4717-8dc0-a167b1e7c2e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315020924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2315020924
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2304682462
Short name T543
Test name
Test status
Simulation time 17462848 ps
CPU time 0.54 seconds
Started May 26 01:09:38 PM PDT 24
Finished May 26 01:09:41 PM PDT 24
Peak memory 182640 kb
Host smart-63b91d1a-8262-48de-ac2c-57a3fa028093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304682462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2304682462
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3124845594
Short name T86
Test name
Test status
Simulation time 126202855 ps
CPU time 0.86 seconds
Started May 26 01:10:02 PM PDT 24
Finished May 26 01:10:05 PM PDT 24
Peak memory 193544 kb
Host smart-5ad29293-5fbe-460e-a20d-871e2781e22f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124845594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3124845594
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3205367755
Short name T64
Test name
Test status
Simulation time 164707060 ps
CPU time 1.08 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 197348 kb
Host smart-0cfa8c55-aeeb-44ec-9ef0-8d4cbac24b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205367755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3205367755
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2250503519
Short name T574
Test name
Test status
Simulation time 498253753 ps
CPU time 1.11 seconds
Started May 26 01:09:57 PM PDT 24
Finished May 26 01:10:01 PM PDT 24
Peak memory 183416 kb
Host smart-e8698776-6dbf-448b-8ded-c8720f79d9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250503519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2250503519
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2288277697
Short name T539
Test name
Test status
Simulation time 171719461 ps
CPU time 0.65 seconds
Started May 26 01:09:26 PM PDT 24
Finished May 26 01:09:30 PM PDT 24
Peak memory 194240 kb
Host smart-3669bc2b-e2be-499f-b2b7-e1aecd22d03b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288277697 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2288277697
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1427496941
Short name T82
Test name
Test status
Simulation time 27691120 ps
CPU time 0.57 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 182652 kb
Host smart-ded0b307-ae1a-4928-9f1a-bb1115acccdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427496941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1427496941
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1633731270
Short name T564
Test name
Test status
Simulation time 91293765 ps
CPU time 0.57 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 182552 kb
Host smart-c26253e7-0c10-43b4-84af-3192bf5d2d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633731270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1633731270
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2476706649
Short name T565
Test name
Test status
Simulation time 19128097 ps
CPU time 0.61 seconds
Started May 26 01:09:22 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 191568 kb
Host smart-4bcaa705-4ded-413d-90d1-78de1382d70a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476706649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2476706649
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1094392463
Short name T504
Test name
Test status
Simulation time 128218676 ps
CPU time 2.05 seconds
Started May 26 01:09:32 PM PDT 24
Finished May 26 01:09:37 PM PDT 24
Peak memory 197524 kb
Host smart-ca37a558-29b8-43ad-b715-70826fec2038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094392463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1094392463
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.787166176
Short name T523
Test name
Test status
Simulation time 91993638 ps
CPU time 0.83 seconds
Started May 26 01:09:19 PM PDT 24
Finished May 26 01:09:21 PM PDT 24
Peak memory 183288 kb
Host smart-e487a019-1505-4c8a-9261-a499d0224201
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787166176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.787166176
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2648028504
Short name T95
Test name
Test status
Simulation time 18637889 ps
CPU time 0.58 seconds
Started May 26 01:09:23 PM PDT 24
Finished May 26 01:09:26 PM PDT 24
Peak memory 182584 kb
Host smart-6a2c8ae4-e4e0-4bb4-ac79-f8e4dc9d0aba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648028504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2648028504
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.48959946
Short name T462
Test name
Test status
Simulation time 190085730 ps
CPU time 2.49 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 191048 kb
Host smart-29dd9129-7078-4a3a-8fab-77383ffb7b03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48959946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ba
sh.48959946
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1323920839
Short name T499
Test name
Test status
Simulation time 18716689 ps
CPU time 0.53 seconds
Started May 26 01:09:10 PM PDT 24
Finished May 26 01:09:12 PM PDT 24
Peak memory 182572 kb
Host smart-66037b40-1948-4618-8e1d-5c67746dde27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323920839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1323920839
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3751618207
Short name T62
Test name
Test status
Simulation time 83200184 ps
CPU time 0.73 seconds
Started May 26 01:09:05 PM PDT 24
Finished May 26 01:09:07 PM PDT 24
Peak memory 194296 kb
Host smart-79d31987-5621-4be2-9ed9-28e4e7609228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751618207 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3751618207
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4117634383
Short name T96
Test name
Test status
Simulation time 22177087 ps
CPU time 0.58 seconds
Started May 26 01:09:13 PM PDT 24
Finished May 26 01:09:14 PM PDT 24
Peak memory 191860 kb
Host smart-3ae61265-f086-4f53-af31-e28f69e254ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117634383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.4117634383
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2684239804
Short name T513
Test name
Test status
Simulation time 17730192 ps
CPU time 0.57 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:16 PM PDT 24
Peak memory 182576 kb
Host smart-cfc3d11f-73d7-49d7-805b-f396aa62fd76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684239804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2684239804
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2479212874
Short name T526
Test name
Test status
Simulation time 68658779 ps
CPU time 0.61 seconds
Started May 26 01:09:13 PM PDT 24
Finished May 26 01:09:15 PM PDT 24
Peak memory 191596 kb
Host smart-60774d55-e51e-469b-844a-ea8a5a26933f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479212874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2479212874
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.400904088
Short name T474
Test name
Test status
Simulation time 482642399 ps
CPU time 2.51 seconds
Started May 26 01:09:13 PM PDT 24
Finished May 26 01:09:17 PM PDT 24
Peak memory 197540 kb
Host smart-8b698de2-c20b-4dd0-a61b-e214c5434214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400904088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.400904088
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.87016337
Short name T111
Test name
Test status
Simulation time 88899390 ps
CPU time 1.08 seconds
Started May 26 01:09:18 PM PDT 24
Finished May 26 01:09:20 PM PDT 24
Peak memory 183172 kb
Host smart-2b9e9818-dac1-4631-a3ad-9e7d373723ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87016337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg
_err.87016337
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3505977498
Short name T453
Test name
Test status
Simulation time 60761105 ps
CPU time 0.54 seconds
Started May 26 01:09:22 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 181996 kb
Host smart-9224e9bc-c376-418e-84c2-bac1e706bedf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505977498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3505977498
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.454053545
Short name T458
Test name
Test status
Simulation time 12706957 ps
CPU time 0.55 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 182160 kb
Host smart-debfa082-0d2f-48f1-82c6-0353da9f15bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454053545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.454053545
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.777456316
Short name T516
Test name
Test status
Simulation time 20826932 ps
CPU time 0.56 seconds
Started May 26 01:09:37 PM PDT 24
Finished May 26 01:09:40 PM PDT 24
Peak memory 182456 kb
Host smart-926561c3-e1fa-4898-af5d-3df71362d18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777456316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.777456316
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2722231483
Short name T552
Test name
Test status
Simulation time 16100427 ps
CPU time 0.58 seconds
Started May 26 01:09:22 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 182512 kb
Host smart-03259795-2fea-417a-946b-8b9aa3f9aa4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722231483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2722231483
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.824746001
Short name T524
Test name
Test status
Simulation time 16403939 ps
CPU time 0.58 seconds
Started May 26 01:09:23 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 182576 kb
Host smart-ea460f69-6035-44db-8d1c-1dc0dd55e8dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824746001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.824746001
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1280993244
Short name T496
Test name
Test status
Simulation time 17385202 ps
CPU time 0.54 seconds
Started May 26 01:09:33 PM PDT 24
Finished May 26 01:09:37 PM PDT 24
Peak memory 182544 kb
Host smart-03444f8f-83c3-4357-819c-c7f6f69af6c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280993244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1280993244
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2995206780
Short name T549
Test name
Test status
Simulation time 17048262 ps
CPU time 0.58 seconds
Started May 26 01:09:26 PM PDT 24
Finished May 26 01:09:28 PM PDT 24
Peak memory 182492 kb
Host smart-b10eb79b-e335-4cae-a02e-c38deed484cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995206780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2995206780
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2405318499
Short name T482
Test name
Test status
Simulation time 95991594 ps
CPU time 0.56 seconds
Started May 26 01:09:22 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 182596 kb
Host smart-209547ea-3832-40d2-af77-82427f28e713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405318499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2405318499
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1268328769
Short name T559
Test name
Test status
Simulation time 14033908 ps
CPU time 0.52 seconds
Started May 26 01:09:22 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 181996 kb
Host smart-2e325c4d-2e89-49b9-b96a-e11eb0c8a800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268328769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1268328769
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4095996462
Short name T531
Test name
Test status
Simulation time 12065713 ps
CPU time 0.53 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 182684 kb
Host smart-9618fd4a-269e-4bf8-8cc5-b6c3ee6fc6bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095996462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4095996462
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.249378618
Short name T92
Test name
Test status
Simulation time 16171866 ps
CPU time 0.71 seconds
Started May 26 01:09:09 PM PDT 24
Finished May 26 01:09:11 PM PDT 24
Peak memory 182740 kb
Host smart-6574a221-78e2-4e7f-8b03-f4911b0b51fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249378618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.249378618
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.47916980
Short name T31
Test name
Test status
Simulation time 1110771470 ps
CPU time 3.57 seconds
Started May 26 01:09:04 PM PDT 24
Finished May 26 01:09:09 PM PDT 24
Peak memory 191056 kb
Host smart-4535552c-4535-4970-88bd-cd1da147bb42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47916980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ba
sh.47916980
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4157482534
Short name T61
Test name
Test status
Simulation time 49475450 ps
CPU time 0.58 seconds
Started May 26 01:09:08 PM PDT 24
Finished May 26 01:09:10 PM PDT 24
Peak memory 182644 kb
Host smart-50379c40-08c2-4111-8fc8-dc8cafa45a62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157482534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4157482534
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1300941248
Short name T550
Test name
Test status
Simulation time 57650720 ps
CPU time 1.28 seconds
Started May 26 01:09:08 PM PDT 24
Finished May 26 01:09:11 PM PDT 24
Peak memory 197648 kb
Host smart-8914ed31-fd0e-402a-80da-c6681bd144e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300941248 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1300941248
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3800666531
Short name T87
Test name
Test status
Simulation time 41258522 ps
CPU time 0.56 seconds
Started May 26 01:09:16 PM PDT 24
Finished May 26 01:09:18 PM PDT 24
Peak memory 182612 kb
Host smart-5a29360c-a17d-4890-91df-8551fd671cec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800666531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3800666531
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2047835087
Short name T470
Test name
Test status
Simulation time 14475281 ps
CPU time 0.54 seconds
Started May 26 01:09:04 PM PDT 24
Finished May 26 01:09:06 PM PDT 24
Peak memory 182208 kb
Host smart-fcaa5c6b-a19b-4849-91be-132d7284905e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047835087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2047835087
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.783456043
Short name T544
Test name
Test status
Simulation time 172582364 ps
CPU time 0.79 seconds
Started May 26 01:09:13 PM PDT 24
Finished May 26 01:09:15 PM PDT 24
Peak memory 193428 kb
Host smart-c42aab79-f965-4797-9ba9-8672f3278dd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783456043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.783456043
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2886157704
Short name T492
Test name
Test status
Simulation time 59226005 ps
CPU time 1.2 seconds
Started May 26 01:09:17 PM PDT 24
Finished May 26 01:09:19 PM PDT 24
Peak memory 197480 kb
Host smart-f6b92b21-bef7-4bcf-88c6-65091072f246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886157704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2886157704
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.499159576
Short name T547
Test name
Test status
Simulation time 82695529 ps
CPU time 0.78 seconds
Started May 26 01:09:23 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 193668 kb
Host smart-551e0669-aab1-47f9-b45d-24224cf91d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499159576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.499159576
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3634219230
Short name T561
Test name
Test status
Simulation time 26392464 ps
CPU time 0.57 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 182596 kb
Host smart-796a84ab-f989-46ae-839a-05731a39b3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634219230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3634219230
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4241105356
Short name T522
Test name
Test status
Simulation time 13616983 ps
CPU time 0.57 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:24 PM PDT 24
Peak memory 182532 kb
Host smart-cf45b11b-2767-408e-ab1a-f924df343658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241105356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4241105356
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.821352923
Short name T493
Test name
Test status
Simulation time 31515655 ps
CPU time 0.58 seconds
Started May 26 01:09:40 PM PDT 24
Finished May 26 01:09:43 PM PDT 24
Peak memory 182524 kb
Host smart-294e5671-f340-4fc3-a5b0-6033732271f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821352923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.821352923
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1438063168
Short name T553
Test name
Test status
Simulation time 14949390 ps
CPU time 0.59 seconds
Started May 26 01:09:30 PM PDT 24
Finished May 26 01:09:33 PM PDT 24
Peak memory 182716 kb
Host smart-723c51dd-e35d-4b61-b29c-5abec3831f92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438063168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1438063168
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1042787483
Short name T454
Test name
Test status
Simulation time 11480733 ps
CPU time 0.52 seconds
Started May 26 01:09:47 PM PDT 24
Finished May 26 01:09:49 PM PDT 24
Peak memory 182408 kb
Host smart-09bde8b3-4a53-433c-968a-4a612e0f763a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042787483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1042787483
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.483943337
Short name T512
Test name
Test status
Simulation time 39862776 ps
CPU time 0.52 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 182016 kb
Host smart-10a2d93d-d105-493e-a744-d6f94f672211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483943337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.483943337
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3615712355
Short name T479
Test name
Test status
Simulation time 12100385 ps
CPU time 0.55 seconds
Started May 26 01:09:20 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 181996 kb
Host smart-42f1d215-28d8-4acf-82de-e322445a8249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615712355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3615712355
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3314256110
Short name T475
Test name
Test status
Simulation time 16081518 ps
CPU time 0.54 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:23 PM PDT 24
Peak memory 182012 kb
Host smart-4d54781f-c187-4392-a3b7-0ea7030d4fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314256110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3314256110
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2593669079
Short name T469
Test name
Test status
Simulation time 17387094 ps
CPU time 0.61 seconds
Started May 26 01:09:30 PM PDT 24
Finished May 26 01:09:32 PM PDT 24
Peak memory 182676 kb
Host smart-00cc9d1d-5b55-42d2-91af-3ecf787d8497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593669079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2593669079
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3071524469
Short name T455
Test name
Test status
Simulation time 33400657 ps
CPU time 0.55 seconds
Started May 26 01:09:27 PM PDT 24
Finished May 26 01:09:29 PM PDT 24
Peak memory 182516 kb
Host smart-a6c9c7c0-42cb-436e-94ec-e694a36a9323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071524469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3071524469
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1124505131
Short name T85
Test name
Test status
Simulation time 51682315 ps
CPU time 0.69 seconds
Started May 26 01:09:16 PM PDT 24
Finished May 26 01:09:18 PM PDT 24
Peak memory 192376 kb
Host smart-bd518e94-927d-49a2-829b-dc65b5f5bf39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124505131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1124505131
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1134466452
Short name T491
Test name
Test status
Simulation time 102263878 ps
CPU time 1.54 seconds
Started May 26 01:09:17 PM PDT 24
Finished May 26 01:09:20 PM PDT 24
Peak memory 192768 kb
Host smart-b7089bf3-b25b-4176-ad31-a4582b60f29f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134466452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1134466452
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1399454013
Short name T90
Test name
Test status
Simulation time 194624065 ps
CPU time 0.63 seconds
Started May 26 01:09:16 PM PDT 24
Finished May 26 01:09:18 PM PDT 24
Peak memory 182752 kb
Host smart-5e7d4fb0-9fb4-4569-8509-aa8d7c82c3f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399454013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1399454013
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2918873098
Short name T51
Test name
Test status
Simulation time 81912272 ps
CPU time 0.7 seconds
Started May 26 01:09:08 PM PDT 24
Finished May 26 01:09:10 PM PDT 24
Peak memory 195280 kb
Host smart-21f26510-9571-4370-9fd5-4b3f8982fda9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918873098 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2918873098
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.119420644
Short name T519
Test name
Test status
Simulation time 30843223 ps
CPU time 0.58 seconds
Started May 26 01:09:15 PM PDT 24
Finished May 26 01:09:17 PM PDT 24
Peak memory 182648 kb
Host smart-d37dd1ed-99cc-400b-9a3e-b9ecbe9fe13d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119420644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.119420644
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2896679854
Short name T463
Test name
Test status
Simulation time 16542676 ps
CPU time 0.56 seconds
Started May 26 01:09:17 PM PDT 24
Finished May 26 01:09:19 PM PDT 24
Peak memory 182492 kb
Host smart-19cc818f-688d-4417-b637-4ab261e4ce29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896679854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2896679854
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1406509640
Short name T100
Test name
Test status
Simulation time 33452262 ps
CPU time 0.79 seconds
Started May 26 01:09:07 PM PDT 24
Finished May 26 01:09:10 PM PDT 24
Peak memory 193272 kb
Host smart-1ade9df2-8fc7-4451-9ecd-1432ee8d99f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406509640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1406509640
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2449249238
Short name T511
Test name
Test status
Simulation time 46838345 ps
CPU time 1.29 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:17 PM PDT 24
Peak memory 197552 kb
Host smart-6ac86669-489a-4052-8abe-a3c510e1a3b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449249238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2449249238
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3790030214
Short name T505
Test name
Test status
Simulation time 167488586 ps
CPU time 1.22 seconds
Started May 26 01:09:13 PM PDT 24
Finished May 26 01:09:15 PM PDT 24
Peak memory 195184 kb
Host smart-82d8a565-2722-4afc-a622-6b4d25a2ab14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790030214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3790030214
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1946963136
Short name T530
Test name
Test status
Simulation time 42836824 ps
CPU time 0.55 seconds
Started May 26 01:09:25 PM PDT 24
Finished May 26 01:09:27 PM PDT 24
Peak memory 182164 kb
Host smart-dd3dae86-394c-40fa-9525-40b27c39645b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946963136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1946963136
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1669231576
Short name T484
Test name
Test status
Simulation time 10991681 ps
CPU time 0.56 seconds
Started May 26 01:09:46 PM PDT 24
Finished May 26 01:09:48 PM PDT 24
Peak memory 182624 kb
Host smart-939e2b38-84f5-46af-85d5-26ab74cf7041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669231576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1669231576
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1603376783
Short name T481
Test name
Test status
Simulation time 10741916 ps
CPU time 0.53 seconds
Started May 26 01:09:42 PM PDT 24
Finished May 26 01:09:44 PM PDT 24
Peak memory 182188 kb
Host smart-129cca11-2ae2-4a63-8d91-4108d7d34679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603376783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1603376783
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2284470824
Short name T534
Test name
Test status
Simulation time 16170408 ps
CPU time 0.56 seconds
Started May 26 01:09:45 PM PDT 24
Finished May 26 01:09:52 PM PDT 24
Peak memory 182480 kb
Host smart-4c8ca3d4-4972-4350-b78e-3203acd3192a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284470824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2284470824
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1209803668
Short name T514
Test name
Test status
Simulation time 43266029 ps
CPU time 0.55 seconds
Started May 26 01:09:35 PM PDT 24
Finished May 26 01:09:38 PM PDT 24
Peak memory 182544 kb
Host smart-e0c096e4-af8d-452e-9225-077f6bf43190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209803668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1209803668
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.978788968
Short name T502
Test name
Test status
Simulation time 16930003 ps
CPU time 0.56 seconds
Started May 26 01:09:35 PM PDT 24
Finished May 26 01:09:38 PM PDT 24
Peak memory 182596 kb
Host smart-71a980e7-7d04-4fab-94c1-b770cad71a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978788968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.978788968
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2600023631
Short name T465
Test name
Test status
Simulation time 11523865 ps
CPU time 0.62 seconds
Started May 26 01:09:41 PM PDT 24
Finished May 26 01:09:44 PM PDT 24
Peak memory 182476 kb
Host smart-332854a8-9eb0-46ad-8722-34907a195615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600023631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2600023631
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2953473088
Short name T555
Test name
Test status
Simulation time 19928788 ps
CPU time 0.62 seconds
Started May 26 01:09:48 PM PDT 24
Finished May 26 01:09:49 PM PDT 24
Peak memory 182704 kb
Host smart-0d50b299-83cd-4aea-9595-63b05c6e908c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953473088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2953473088
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1103111369
Short name T480
Test name
Test status
Simulation time 21214946 ps
CPU time 0.53 seconds
Started May 26 01:09:35 PM PDT 24
Finished May 26 01:09:38 PM PDT 24
Peak memory 182004 kb
Host smart-716ea543-9c51-4cde-bc3f-ef5e06dddaaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103111369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1103111369
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2542928516
Short name T573
Test name
Test status
Simulation time 15334694 ps
CPU time 0.58 seconds
Started May 26 01:09:32 PM PDT 24
Finished May 26 01:09:35 PM PDT 24
Peak memory 182300 kb
Host smart-75d94afb-0260-4773-8eab-0ca2e534b823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542928516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2542928516
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.27663035
Short name T483
Test name
Test status
Simulation time 104454548 ps
CPU time 1.38 seconds
Started May 26 01:09:23 PM PDT 24
Finished May 26 01:09:26 PM PDT 24
Peak memory 197556 kb
Host smart-55fb0ec4-7b02-46e6-8a69-14826f625c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27663035 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.27663035
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.728783127
Short name T50
Test name
Test status
Simulation time 23153084 ps
CPU time 0.58 seconds
Started May 26 01:09:07 PM PDT 24
Finished May 26 01:09:09 PM PDT 24
Peak memory 182648 kb
Host smart-689a2619-3c53-4a43-8b25-d2c82ae11de4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728783127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.728783127
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3135871715
Short name T566
Test name
Test status
Simulation time 12668642 ps
CPU time 0.6 seconds
Started May 26 01:09:06 PM PDT 24
Finished May 26 01:09:08 PM PDT 24
Peak memory 182592 kb
Host smart-838a059c-a677-4738-9693-2a1825ef105f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135871715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3135871715
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3443712889
Short name T88
Test name
Test status
Simulation time 33963095 ps
CPU time 0.8 seconds
Started May 26 01:09:15 PM PDT 24
Finished May 26 01:09:18 PM PDT 24
Peak memory 191588 kb
Host smart-92f4e799-b170-4841-b07b-8f29ba11d0f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443712889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3443712889
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4250593506
Short name T477
Test name
Test status
Simulation time 53872228 ps
CPU time 2.4 seconds
Started May 26 01:09:18 PM PDT 24
Finished May 26 01:09:22 PM PDT 24
Peak memory 197612 kb
Host smart-3250461f-15b2-4ae6-a67a-909e54584561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250593506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4250593506
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4070506532
Short name T537
Test name
Test status
Simulation time 146968388 ps
CPU time 1.11 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:17 PM PDT 24
Peak memory 195156 kb
Host smart-3cf2bbd7-dc28-44ac-a2de-67699841f2bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070506532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.4070506532
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3588305992
Short name T486
Test name
Test status
Simulation time 180241671 ps
CPU time 0.81 seconds
Started May 26 01:09:09 PM PDT 24
Finished May 26 01:09:12 PM PDT 24
Peak memory 195624 kb
Host smart-8bd6ad0f-02fb-469d-a33a-3d94db425004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588305992 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3588305992
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2545178161
Short name T490
Test name
Test status
Simulation time 98749373 ps
CPU time 0.6 seconds
Started May 26 01:09:18 PM PDT 24
Finished May 26 01:09:20 PM PDT 24
Peak memory 191840 kb
Host smart-859bd1f0-0896-4247-94a2-60f180468df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545178161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2545178161
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1946512182
Short name T509
Test name
Test status
Simulation time 24021287 ps
CPU time 0.53 seconds
Started May 26 01:09:08 PM PDT 24
Finished May 26 01:09:10 PM PDT 24
Peak memory 182560 kb
Host smart-0db2c10f-4d3b-4d6a-9f76-2ff111d042ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946512182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1946512182
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1756591494
Short name T101
Test name
Test status
Simulation time 24188618 ps
CPU time 0.77 seconds
Started May 26 01:09:07 PM PDT 24
Finished May 26 01:09:10 PM PDT 24
Peak memory 193280 kb
Host smart-30308cd3-441a-4055-953e-7c529e5fa1ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756591494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1756591494
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3090834017
Short name T576
Test name
Test status
Simulation time 99017327 ps
CPU time 1.64 seconds
Started May 26 01:09:06 PM PDT 24
Finished May 26 01:09:08 PM PDT 24
Peak memory 197536 kb
Host smart-95bb3a5b-52b0-436a-ae45-dcb7e5bdd225
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090834017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3090834017
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2005039121
Short name T548
Test name
Test status
Simulation time 107683605 ps
CPU time 0.82 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:16 PM PDT 24
Peak memory 183008 kb
Host smart-f5a218e7-06b0-452e-832d-d414110f414a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005039121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2005039121
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.998785146
Short name T468
Test name
Test status
Simulation time 21956740 ps
CPU time 0.71 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:16 PM PDT 24
Peak memory 194284 kb
Host smart-8a56456d-d326-478f-953d-6a84cbb64050
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998785146 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.998785146
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.986459943
Short name T557
Test name
Test status
Simulation time 45075305 ps
CPU time 0.54 seconds
Started May 26 01:09:27 PM PDT 24
Finished May 26 01:09:28 PM PDT 24
Peak memory 182608 kb
Host smart-88ff8e45-abcf-463f-8955-d546162734f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986459943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.986459943
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.403208326
Short name T538
Test name
Test status
Simulation time 37197197 ps
CPU time 0.52 seconds
Started May 26 01:09:06 PM PDT 24
Finished May 26 01:09:08 PM PDT 24
Peak memory 181976 kb
Host smart-1bd63ae1-a27f-4638-bc41-e5eff42170ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403208326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.403208326
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.737097321
Short name T63
Test name
Test status
Simulation time 39782717 ps
CPU time 0.81 seconds
Started May 26 01:09:10 PM PDT 24
Finished May 26 01:09:13 PM PDT 24
Peak memory 193520 kb
Host smart-e40f1d97-cf6e-4c5d-b789-8806564a3eb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737097321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.737097321
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2739600989
Short name T567
Test name
Test status
Simulation time 177403019 ps
CPU time 1.27 seconds
Started May 26 01:09:07 PM PDT 24
Finished May 26 01:09:09 PM PDT 24
Peak memory 197548 kb
Host smart-2dbc81e0-d036-4041-a86a-64743529288c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739600989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2739600989
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2131957764
Short name T556
Test name
Test status
Simulation time 2078592311 ps
CPU time 1.49 seconds
Started May 26 01:09:07 PM PDT 24
Finished May 26 01:09:10 PM PDT 24
Peak memory 194516 kb
Host smart-4869a513-3109-41d3-add6-cbb7884326b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131957764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2131957764
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1926577756
Short name T515
Test name
Test status
Simulation time 308835161 ps
CPU time 0.9 seconds
Started May 26 01:09:09 PM PDT 24
Finished May 26 01:09:12 PM PDT 24
Peak memory 196840 kb
Host smart-8449895f-41e3-4bf0-93bb-e480237c5468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926577756 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1926577756
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3292637522
Short name T488
Test name
Test status
Simulation time 59326103 ps
CPU time 0.53 seconds
Started May 26 01:09:24 PM PDT 24
Finished May 26 01:09:27 PM PDT 24
Peak memory 182616 kb
Host smart-a2490585-d574-46db-bc71-506cbaed4984
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292637522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3292637522
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2142190047
Short name T456
Test name
Test status
Simulation time 13559618 ps
CPU time 0.56 seconds
Started May 26 01:09:13 PM PDT 24
Finished May 26 01:09:15 PM PDT 24
Peak memory 182208 kb
Host smart-16a12979-dd64-4521-a93c-0b8fbaf4d54e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142190047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2142190047
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2635566314
Short name T542
Test name
Test status
Simulation time 16491868 ps
CPU time 0.63 seconds
Started May 26 01:09:22 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 192080 kb
Host smart-6d68379c-dfa3-481d-bd42-f928a14cad3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635566314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2635566314
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2133115775
Short name T521
Test name
Test status
Simulation time 233687522 ps
CPU time 2.87 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:26 PM PDT 24
Peak memory 197560 kb
Host smart-2bf9e5fe-945d-4c4a-b934-41d9d2f1b3ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133115775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2133115775
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.896262612
Short name T546
Test name
Test status
Simulation time 95110656 ps
CPU time 0.86 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:16 PM PDT 24
Peak memory 193452 kb
Host smart-00a4076f-61d7-4024-8895-55728bf83eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896262612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.896262612
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2982762428
Short name T508
Test name
Test status
Simulation time 131657409 ps
CPU time 1.09 seconds
Started May 26 01:09:21 PM PDT 24
Finished May 26 01:09:25 PM PDT 24
Peak memory 197468 kb
Host smart-6d204786-c4ae-45d6-81aa-b012026c9e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982762428 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2982762428
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2237804621
Short name T89
Test name
Test status
Simulation time 155212471 ps
CPU time 0.59 seconds
Started May 26 01:09:14 PM PDT 24
Finished May 26 01:09:16 PM PDT 24
Peak memory 182644 kb
Host smart-ed40b1d7-0647-4fdf-aea6-511ff19546fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237804621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2237804621
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3941265715
Short name T466
Test name
Test status
Simulation time 14380047 ps
CPU time 0.59 seconds
Started May 26 01:09:09 PM PDT 24
Finished May 26 01:09:11 PM PDT 24
Peak memory 182656 kb
Host smart-cefa7515-aaec-43e4-80f2-46f39a4af42f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941265715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3941265715
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4126065365
Short name T97
Test name
Test status
Simulation time 121475094 ps
CPU time 0.59 seconds
Started May 26 01:09:24 PM PDT 24
Finished May 26 01:09:27 PM PDT 24
Peak memory 191544 kb
Host smart-9a6afe5f-4b61-445d-adc3-2274fe8e46bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126065365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.4126065365
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4182901108
Short name T535
Test name
Test status
Simulation time 109335951 ps
CPU time 1.27 seconds
Started May 26 01:09:27 PM PDT 24
Finished May 26 01:09:29 PM PDT 24
Peak memory 197540 kb
Host smart-bd9c7fc8-62f8-405c-ac70-7ac412c5c9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182901108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4182901108
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1682303987
Short name T525
Test name
Test status
Simulation time 229282584 ps
CPU time 1.05 seconds
Started May 26 01:09:16 PM PDT 24
Finished May 26 01:09:19 PM PDT 24
Peak memory 183480 kb
Host smart-dbac5b55-874f-481b-a681-b8a4f462332a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682303987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1682303987
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.319114789
Short name T178
Test name
Test status
Simulation time 19605147276 ps
CPU time 27.02 seconds
Started May 26 02:26:57 PM PDT 24
Finished May 26 02:27:26 PM PDT 24
Peak memory 182640 kb
Host smart-7b60f63b-a42a-436c-9c92-49ffad7191d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319114789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.319114789
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2585565402
Short name T420
Test name
Test status
Simulation time 398152964217 ps
CPU time 155.98 seconds
Started May 26 02:27:01 PM PDT 24
Finished May 26 02:29:38 PM PDT 24
Peak memory 182712 kb
Host smart-11d35c2b-04da-4c4d-88c9-c4700be4111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585565402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2585565402
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.225510196
Short name T315
Test name
Test status
Simulation time 1006194720338 ps
CPU time 349.73 seconds
Started May 26 02:26:58 PM PDT 24
Finished May 26 02:32:49 PM PDT 24
Peak memory 190904 kb
Host smart-18e9b1d8-ccfa-40a5-b9a1-954ec150c637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225510196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.225510196
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.4021723565
Short name T400
Test name
Test status
Simulation time 3105161239 ps
CPU time 2.29 seconds
Started May 26 02:26:58 PM PDT 24
Finished May 26 02:27:02 PM PDT 24
Peak memory 193908 kb
Host smart-cf94896f-6fdf-4497-ae92-10082f695874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021723565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4021723565
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1454436343
Short name T262
Test name
Test status
Simulation time 8917978197 ps
CPU time 8.36 seconds
Started May 26 02:26:58 PM PDT 24
Finished May 26 02:27:07 PM PDT 24
Peak memory 182644 kb
Host smart-8d8f5887-2f78-49a2-87dd-a02380156ec4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454436343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1454436343
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3885809350
Short name T438
Test name
Test status
Simulation time 641590634119 ps
CPU time 112.4 seconds
Started May 26 02:27:02 PM PDT 24
Finished May 26 02:28:55 PM PDT 24
Peak memory 182712 kb
Host smart-d7d01f29-df39-47e3-b046-1213d9544e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885809350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3885809350
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2932219960
Short name T296
Test name
Test status
Simulation time 151414009697 ps
CPU time 1919.55 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:59:00 PM PDT 24
Peak memory 190872 kb
Host smart-bb44dc2a-f30a-4877-97da-09fb0db11781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932219960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2932219960
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.946998080
Short name T361
Test name
Test status
Simulation time 70525628362 ps
CPU time 122.44 seconds
Started May 26 02:26:57 PM PDT 24
Finished May 26 02:29:01 PM PDT 24
Peak memory 190776 kb
Host smart-43a012d9-4158-4bf6-b2c2-a9803552794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946998080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.946998080
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1680357381
Short name T16
Test name
Test status
Simulation time 532116192 ps
CPU time 0.96 seconds
Started May 26 02:26:58 PM PDT 24
Finished May 26 02:27:00 PM PDT 24
Peak memory 214348 kb
Host smart-feb6e957-18ab-4a78-a4a5-52e453c69d04
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680357381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1680357381
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1855835836
Short name T374
Test name
Test status
Simulation time 2786595506522 ps
CPU time 913.3 seconds
Started May 26 02:27:00 PM PDT 24
Finished May 26 02:42:15 PM PDT 24
Peak memory 190784 kb
Host smart-21da876c-a9e4-481c-a2c3-892391463f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855835836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1855835836
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2159968770
Short name T397
Test name
Test status
Simulation time 55723016148 ps
CPU time 93.82 seconds
Started May 26 02:27:02 PM PDT 24
Finished May 26 02:28:37 PM PDT 24
Peak memory 182704 kb
Host smart-0c2f1ccd-1564-4356-a2c1-c12ab3dfded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159968770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2159968770
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.773582708
Short name T225
Test name
Test status
Simulation time 99298267223 ps
CPU time 148.96 seconds
Started May 26 02:27:06 PM PDT 24
Finished May 26 02:29:36 PM PDT 24
Peak memory 190892 kb
Host smart-d8feeca8-4f5e-40a7-a15b-bb3a77f80aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773582708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.773582708
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3075948553
Short name T387
Test name
Test status
Simulation time 334153409347 ps
CPU time 136.52 seconds
Started May 26 02:27:06 PM PDT 24
Finished May 26 02:29:23 PM PDT 24
Peak memory 182708 kb
Host smart-ff0b9fb1-6633-432f-ad9e-0208c11777cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075948553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3075948553
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.384416044
Short name T247
Test name
Test status
Simulation time 227487822511 ps
CPU time 122.48 seconds
Started May 26 02:28:54 PM PDT 24
Finished May 26 02:30:57 PM PDT 24
Peak memory 190892 kb
Host smart-e72edb44-b6d2-4be5-85f8-4c968d6201c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384416044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.384416044
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3757382456
Short name T108
Test name
Test status
Simulation time 167071526750 ps
CPU time 179.88 seconds
Started May 26 02:28:50 PM PDT 24
Finished May 26 02:31:50 PM PDT 24
Peak memory 190780 kb
Host smart-06f5fef5-3b3c-4d9b-951e-57cf352dbcb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757382456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3757382456
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1352136008
Short name T176
Test name
Test status
Simulation time 70752530600 ps
CPU time 70.59 seconds
Started May 26 02:28:54 PM PDT 24
Finished May 26 02:30:05 PM PDT 24
Peak memory 190840 kb
Host smart-87ff3b90-de2b-49bc-a29c-e4fa3b8e5681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352136008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1352136008
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2452118613
Short name T309
Test name
Test status
Simulation time 132469811504 ps
CPU time 638.22 seconds
Started May 26 02:28:54 PM PDT 24
Finished May 26 02:39:32 PM PDT 24
Peak memory 190868 kb
Host smart-d7e56a32-0737-42e7-b386-036d93f746b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452118613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2452118613
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.4196188350
Short name T267
Test name
Test status
Simulation time 192786809646 ps
CPU time 96.69 seconds
Started May 26 02:28:52 PM PDT 24
Finished May 26 02:30:30 PM PDT 24
Peak memory 190904 kb
Host smart-8da64422-6dc1-4909-b189-98af3a7b3c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196188350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.4196188350
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1236850773
Short name T40
Test name
Test status
Simulation time 6616910715 ps
CPU time 10.08 seconds
Started May 26 02:27:04 PM PDT 24
Finished May 26 02:27:15 PM PDT 24
Peak memory 182716 kb
Host smart-f65d4819-6947-4c41-938a-06c90388d1dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236850773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1236850773
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.211641093
Short name T405
Test name
Test status
Simulation time 103885545303 ps
CPU time 148.7 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:29:46 PM PDT 24
Peak memory 182720 kb
Host smart-1a68300d-20fc-422a-9338-9bdbe38897d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211641093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.211641093
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2683759931
Short name T207
Test name
Test status
Simulation time 207986741964 ps
CPU time 107.17 seconds
Started May 26 02:27:02 PM PDT 24
Finished May 26 02:28:51 PM PDT 24
Peak memory 190916 kb
Host smart-4d2c7741-42b4-4e87-8c8f-a71dec745de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683759931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2683759931
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3921936843
Short name T341
Test name
Test status
Simulation time 244094822274 ps
CPU time 499.62 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:35:36 PM PDT 24
Peak memory 190908 kb
Host smart-b6716fee-8632-4461-ac39-4828f8c0a5bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921936843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3921936843
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.2033840750
Short name T324
Test name
Test status
Simulation time 218607714147 ps
CPU time 117.87 seconds
Started May 26 02:28:53 PM PDT 24
Finished May 26 02:30:51 PM PDT 24
Peak memory 190892 kb
Host smart-14b64d76-c13b-415c-a4b7-937108f74340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033840750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2033840750
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1382032035
Short name T350
Test name
Test status
Simulation time 89208638771 ps
CPU time 50.34 seconds
Started May 26 02:28:52 PM PDT 24
Finished May 26 02:29:43 PM PDT 24
Peak memory 182752 kb
Host smart-6d9aa6e7-70ac-4915-ac39-dda22aa4b8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382032035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1382032035
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2940328970
Short name T204
Test name
Test status
Simulation time 125358323188 ps
CPU time 445.09 seconds
Started May 26 02:28:56 PM PDT 24
Finished May 26 02:36:21 PM PDT 24
Peak memory 194512 kb
Host smart-3aa934ff-b509-4eb5-9349-48761df297b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940328970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2940328970
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.478269331
Short name T114
Test name
Test status
Simulation time 68693464882 ps
CPU time 107.89 seconds
Started May 26 02:28:55 PM PDT 24
Finished May 26 02:30:43 PM PDT 24
Peak memory 190896 kb
Host smart-ed31d44b-629c-4c82-99b6-c408a0ecd105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478269331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.478269331
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2075802701
Short name T110
Test name
Test status
Simulation time 38310770581 ps
CPU time 65.71 seconds
Started May 26 02:28:55 PM PDT 24
Finished May 26 02:30:02 PM PDT 24
Peak memory 182872 kb
Host smart-7416b1c2-6dc5-4d07-b88f-5bee28107554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075802701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2075802701
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4273207016
Short name T290
Test name
Test status
Simulation time 421301751188 ps
CPU time 3266.5 seconds
Started May 26 02:29:01 PM PDT 24
Finished May 26 03:23:28 PM PDT 24
Peak memory 190900 kb
Host smart-07f44b64-ddc8-4327-a892-f781b7206f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273207016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4273207016
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.340154529
Short name T142
Test name
Test status
Simulation time 24611350903 ps
CPU time 41.49 seconds
Started May 26 02:29:02 PM PDT 24
Finished May 26 02:29:45 PM PDT 24
Peak memory 191056 kb
Host smart-f5b217ef-d543-4e34-9ded-7aae4690bff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340154529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.340154529
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3082836148
Short name T449
Test name
Test status
Simulation time 755346801128 ps
CPU time 132.49 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:29:29 PM PDT 24
Peak memory 182712 kb
Host smart-f8b3ed8c-9045-4be8-ad43-549f5c7eabff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082836148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3082836148
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3918291494
Short name T265
Test name
Test status
Simulation time 115597989432 ps
CPU time 235.06 seconds
Started May 26 02:27:05 PM PDT 24
Finished May 26 02:31:01 PM PDT 24
Peak memory 190900 kb
Host smart-5d08400b-59f3-440e-a700-72eb1f6f3b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918291494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3918291494
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2723987711
Short name T285
Test name
Test status
Simulation time 17119618774 ps
CPU time 33.55 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:27:51 PM PDT 24
Peak memory 190920 kb
Host smart-1589bd70-667f-475b-8e6e-4a34d5ab30af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723987711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2723987711
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.2150830119
Short name T152
Test name
Test status
Simulation time 189318745903 ps
CPU time 198.53 seconds
Started May 26 02:29:01 PM PDT 24
Finished May 26 02:32:21 PM PDT 24
Peak memory 190856 kb
Host smart-63bd80bd-caf0-4f4c-8390-f2f1c9fb351c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150830119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2150830119
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.542631391
Short name T44
Test name
Test status
Simulation time 83355407999 ps
CPU time 121.42 seconds
Started May 26 02:29:00 PM PDT 24
Finished May 26 02:31:02 PM PDT 24
Peak memory 190896 kb
Host smart-e7ae6a85-eeb2-41b5-b21d-b341033abd4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542631391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.542631391
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1584959801
Short name T165
Test name
Test status
Simulation time 84330165458 ps
CPU time 139.16 seconds
Started May 26 02:29:01 PM PDT 24
Finished May 26 02:31:21 PM PDT 24
Peak memory 190896 kb
Host smart-302b0daf-cb40-4198-bb38-e83bbddad7dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584959801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1584959801
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1917125761
Short name T206
Test name
Test status
Simulation time 70266497534 ps
CPU time 74.98 seconds
Started May 26 02:29:01 PM PDT 24
Finished May 26 02:30:17 PM PDT 24
Peak memory 190868 kb
Host smart-464c3a78-8883-4358-9659-785d022ed46c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917125761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1917125761
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1956878227
Short name T20
Test name
Test status
Simulation time 205774754369 ps
CPU time 294.49 seconds
Started May 26 02:29:02 PM PDT 24
Finished May 26 02:33:57 PM PDT 24
Peak memory 190872 kb
Host smart-d8f626b1-928a-4b2b-b00a-ef0c5113774b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956878227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1956878227
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1835197504
Short name T259
Test name
Test status
Simulation time 124699388201 ps
CPU time 1792.87 seconds
Started May 26 02:29:08 PM PDT 24
Finished May 26 02:59:02 PM PDT 24
Peak memory 194428 kb
Host smart-b8b4d2fd-7697-405a-9935-789e5d28236c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835197504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1835197504
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3904577771
Short name T408
Test name
Test status
Simulation time 340057343477 ps
CPU time 126.6 seconds
Started May 26 02:27:03 PM PDT 24
Finished May 26 02:29:10 PM PDT 24
Peak memory 182672 kb
Host smart-edcc5bcc-2f58-46cb-9d10-1cbb5e714180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904577771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3904577771
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2776940049
Short name T337
Test name
Test status
Simulation time 48274531692 ps
CPU time 94.74 seconds
Started May 26 02:27:02 PM PDT 24
Finished May 26 02:28:38 PM PDT 24
Peak memory 182704 kb
Host smart-aae23129-8687-4649-ae8b-30bd414b9146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776940049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2776940049
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.333986068
Short name T79
Test name
Test status
Simulation time 104015390710 ps
CPU time 573.08 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 02:36:47 PM PDT 24
Peak memory 190916 kb
Host smart-c9bd72f6-6789-4e19-bf3b-ed66009f4925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333986068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
333986068
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.1147081178
Short name T310
Test name
Test status
Simulation time 526652589981 ps
CPU time 253.5 seconds
Started May 26 02:29:07 PM PDT 24
Finished May 26 02:33:21 PM PDT 24
Peak memory 190856 kb
Host smart-1d64e74c-3832-402f-bb65-90093be9dc0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147081178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1147081178
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.4250171799
Short name T355
Test name
Test status
Simulation time 80678010114 ps
CPU time 307.37 seconds
Started May 26 02:29:08 PM PDT 24
Finished May 26 02:34:16 PM PDT 24
Peak memory 190832 kb
Host smart-02030aa7-92d1-4145-890a-0cd10baf0a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250171799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.4250171799
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1462541250
Short name T280
Test name
Test status
Simulation time 605984600673 ps
CPU time 99.03 seconds
Started May 26 02:29:10 PM PDT 24
Finished May 26 02:30:50 PM PDT 24
Peak memory 190832 kb
Host smart-fe540381-ef54-4961-af1f-312af684f0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462541250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1462541250
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1523050108
Short name T21
Test name
Test status
Simulation time 130082596475 ps
CPU time 186.88 seconds
Started May 26 02:29:07 PM PDT 24
Finished May 26 02:32:15 PM PDT 24
Peak memory 190860 kb
Host smart-b69b984f-2a2f-449a-b23b-aa0e66ac50c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523050108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1523050108
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.862550573
Short name T344
Test name
Test status
Simulation time 86476615735 ps
CPU time 53.52 seconds
Started May 26 02:27:14 PM PDT 24
Finished May 26 02:28:09 PM PDT 24
Peak memory 182660 kb
Host smart-7d89cc1e-34c3-42db-9f5d-ec75c8ff06f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862550573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.862550573
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2240243609
Short name T78
Test name
Test status
Simulation time 260788281914 ps
CPU time 199.8 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:30:37 PM PDT 24
Peak memory 182684 kb
Host smart-ce9751c9-7685-4bd5-8817-4d2c204f5836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240243609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2240243609
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.4049583145
Short name T357
Test name
Test status
Simulation time 121441360008 ps
CPU time 1708.73 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 02:55:43 PM PDT 24
Peak memory 190908 kb
Host smart-6dc8ccad-243e-4b70-8b7f-2f5814926282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049583145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.4049583145
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2891025457
Short name T122
Test name
Test status
Simulation time 438090374256 ps
CPU time 157.15 seconds
Started May 26 02:27:14 PM PDT 24
Finished May 26 02:29:52 PM PDT 24
Peak memory 194484 kb
Host smart-39ffc083-c61c-46fa-95f0-1ad4f54a9d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891025457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2891025457
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.2876417880
Short name T368
Test name
Test status
Simulation time 1796985460 ps
CPU time 3.06 seconds
Started May 26 02:29:16 PM PDT 24
Finished May 26 02:29:20 PM PDT 24
Peak memory 182448 kb
Host smart-132014b6-199e-403c-97ba-a76f79493156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876417880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2876417880
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1748391187
Short name T332
Test name
Test status
Simulation time 8433837022 ps
CPU time 12.73 seconds
Started May 26 02:29:16 PM PDT 24
Finished May 26 02:29:30 PM PDT 24
Peak memory 182680 kb
Host smart-ee97e5c4-5471-4d04-8a67-4f16a5c83e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748391187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1748391187
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3941874206
Short name T239
Test name
Test status
Simulation time 82531779732 ps
CPU time 110.76 seconds
Started May 26 02:29:14 PM PDT 24
Finished May 26 02:31:05 PM PDT 24
Peak memory 194676 kb
Host smart-5837797d-83f4-4cef-a2ef-852f73ca7b83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941874206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3941874206
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2983177101
Short name T365
Test name
Test status
Simulation time 477109193336 ps
CPU time 790.91 seconds
Started May 26 02:29:16 PM PDT 24
Finished May 26 02:42:28 PM PDT 24
Peak memory 190920 kb
Host smart-84825def-baba-47f8-bbdb-ef547e04cf77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983177101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2983177101
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1008717286
Short name T431
Test name
Test status
Simulation time 52158860363 ps
CPU time 79.17 seconds
Started May 26 02:29:15 PM PDT 24
Finished May 26 02:30:35 PM PDT 24
Peak memory 190900 kb
Host smart-fb84a57f-b39d-4c7b-a461-a4cf9a7f25e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008717286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1008717286
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1465765097
Short name T72
Test name
Test status
Simulation time 6244471921 ps
CPU time 12.88 seconds
Started May 26 02:29:15 PM PDT 24
Finished May 26 02:29:28 PM PDT 24
Peak memory 182700 kb
Host smart-1eaa8c50-110b-44da-8f4d-6ab84e53031c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465765097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1465765097
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3405125299
Short name T242
Test name
Test status
Simulation time 606572463793 ps
CPU time 347.94 seconds
Started May 26 02:27:18 PM PDT 24
Finished May 26 02:33:07 PM PDT 24
Peak memory 182724 kb
Host smart-8a398540-a036-4c00-b8f3-63a4411347cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405125299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3405125299
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.4117358183
Short name T411
Test name
Test status
Simulation time 133219093300 ps
CPU time 92.5 seconds
Started May 26 02:27:14 PM PDT 24
Finished May 26 02:28:48 PM PDT 24
Peak memory 182720 kb
Host smart-3d01dd80-e867-4611-b555-89f9141d825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117358183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.4117358183
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.145701909
Short name T25
Test name
Test status
Simulation time 186075361 ps
CPU time 0.91 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 02:27:15 PM PDT 24
Peak memory 191096 kb
Host smart-fd58338f-9f7a-4f5a-8fdb-f62d5cce6acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145701909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.145701909
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2985725158
Short name T283
Test name
Test status
Simulation time 1820174693485 ps
CPU time 577.25 seconds
Started May 26 02:27:12 PM PDT 24
Finished May 26 02:36:50 PM PDT 24
Peak memory 190876 kb
Host smart-187d273c-5449-44a5-98ef-7d918cb94b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985725158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2985725158
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/152.rv_timer_random.1923608377
Short name T158
Test name
Test status
Simulation time 55123455047 ps
CPU time 106.03 seconds
Started May 26 02:29:14 PM PDT 24
Finished May 26 02:31:01 PM PDT 24
Peak memory 190904 kb
Host smart-5e26330b-554b-47f4-8b6b-a47267c76de9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923608377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1923608377
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3395170278
Short name T255
Test name
Test status
Simulation time 394015403205 ps
CPU time 463.82 seconds
Started May 26 02:29:14 PM PDT 24
Finished May 26 02:36:58 PM PDT 24
Peak memory 190904 kb
Host smart-e7370ebe-8587-4641-9d76-62ed2c91bb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395170278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3395170278
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.331099224
Short name T293
Test name
Test status
Simulation time 370541329593 ps
CPU time 1911.24 seconds
Started May 26 02:29:22 PM PDT 24
Finished May 26 03:01:14 PM PDT 24
Peak memory 190872 kb
Host smart-178d93a5-e79a-4a3f-b986-3c3936f83f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331099224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.331099224
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.314527771
Short name T289
Test name
Test status
Simulation time 87940317652 ps
CPU time 145.61 seconds
Started May 26 02:29:23 PM PDT 24
Finished May 26 02:31:49 PM PDT 24
Peak memory 191052 kb
Host smart-a991c356-3e1a-4cc2-8237-1f2df6c41ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314527771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.314527771
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2159811058
Short name T381
Test name
Test status
Simulation time 439390487313 ps
CPU time 192.92 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:30:29 PM PDT 24
Peak memory 182708 kb
Host smart-8b331427-c7f3-42f6-9df7-baed334f5658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159811058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2159811058
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2838483772
Short name T340
Test name
Test status
Simulation time 182120206989 ps
CPU time 79.73 seconds
Started May 26 02:27:21 PM PDT 24
Finished May 26 02:28:42 PM PDT 24
Peak memory 190876 kb
Host smart-990ee4fb-f318-4a4d-8777-4d8f841adf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838483772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2838483772
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.417281129
Short name T338
Test name
Test status
Simulation time 135666782968 ps
CPU time 167.46 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 02:30:02 PM PDT 24
Peak memory 194664 kb
Host smart-1368500a-c8b2-479d-a273-f65d445e6c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417281129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
417281129
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1029813084
Short name T396
Test name
Test status
Simulation time 194881613539 ps
CPU time 137.71 seconds
Started May 26 02:29:21 PM PDT 24
Finished May 26 02:31:40 PM PDT 24
Peak memory 182688 kb
Host smart-63c3e5a7-f3b7-49e4-94a0-7233026fe093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029813084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1029813084
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2830564043
Short name T186
Test name
Test status
Simulation time 471720496993 ps
CPU time 305.14 seconds
Started May 26 02:29:22 PM PDT 24
Finished May 26 02:34:28 PM PDT 24
Peak memory 190904 kb
Host smart-b232fe9f-c14b-421e-8298-119ad1ebcefb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830564043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2830564043
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.4036846767
Short name T254
Test name
Test status
Simulation time 225044620721 ps
CPU time 100.93 seconds
Started May 26 02:29:23 PM PDT 24
Finished May 26 02:31:05 PM PDT 24
Peak memory 190896 kb
Host smart-4ff21e7a-3a2c-4a33-a87b-55a33ad5fc44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036846767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4036846767
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3229205371
Short name T198
Test name
Test status
Simulation time 775196806657 ps
CPU time 415.72 seconds
Started May 26 02:29:24 PM PDT 24
Finished May 26 02:36:20 PM PDT 24
Peak memory 190920 kb
Host smart-509b3286-422e-460f-a48d-5bf3dd7b1d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229205371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3229205371
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1503671029
Short name T157
Test name
Test status
Simulation time 288937192820 ps
CPU time 108.43 seconds
Started May 26 02:29:22 PM PDT 24
Finished May 26 02:31:11 PM PDT 24
Peak memory 182672 kb
Host smart-15542313-2804-4cd0-8525-8ab0eeb23b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503671029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1503671029
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1294590576
Short name T300
Test name
Test status
Simulation time 117611379408 ps
CPU time 176.52 seconds
Started May 26 02:29:21 PM PDT 24
Finished May 26 02:32:18 PM PDT 24
Peak memory 190896 kb
Host smart-f9dbc01c-f7b7-4da6-bd42-bac2c73b59c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294590576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1294590576
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.4267593652
Short name T19
Test name
Test status
Simulation time 326151055852 ps
CPU time 160.12 seconds
Started May 26 02:29:22 PM PDT 24
Finished May 26 02:32:03 PM PDT 24
Peak memory 193320 kb
Host smart-24317f94-73f6-4697-90aa-4331c1d1c45e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267593652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.4267593652
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2581362936
Short name T226
Test name
Test status
Simulation time 65950466750 ps
CPU time 111.88 seconds
Started May 26 02:29:23 PM PDT 24
Finished May 26 02:31:15 PM PDT 24
Peak memory 193984 kb
Host smart-99089993-e0b5-495d-b219-836cc3e8aeaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581362936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2581362936
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3082947868
Short name T160
Test name
Test status
Simulation time 1301275192179 ps
CPU time 701.65 seconds
Started May 26 02:29:21 PM PDT 24
Finished May 26 02:41:03 PM PDT 24
Peak memory 190896 kb
Host smart-75964809-468c-4bcf-9711-2321f6fcb99a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082947868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3082947868
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2995050508
Short name T393
Test name
Test status
Simulation time 154722153805 ps
CPU time 76.32 seconds
Started May 26 02:27:11 PM PDT 24
Finished May 26 02:28:29 PM PDT 24
Peak memory 182676 kb
Host smart-0f8eff1b-8e4c-45a6-a097-168ee7c9606b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995050508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2995050508
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3907617960
Short name T404
Test name
Test status
Simulation time 279749222116 ps
CPU time 110.03 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 02:29:04 PM PDT 24
Peak memory 182736 kb
Host smart-44727943-559e-42a4-a2cb-f4de57d027a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907617960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3907617960
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3245394281
Short name T75
Test name
Test status
Simulation time 35554270225 ps
CPU time 11.71 seconds
Started May 26 02:27:20 PM PDT 24
Finished May 26 02:27:33 PM PDT 24
Peak memory 182676 kb
Host smart-f1f6f943-66f4-4593-8ee7-b1e6d26dcce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245394281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3245394281
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.3309275149
Short name T35
Test name
Test status
Simulation time 38874940362 ps
CPU time 277.05 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 02:31:52 PM PDT 24
Peak memory 205544 kb
Host smart-0559630d-75c9-4a2f-8cef-a6071b64b28b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309275149 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.3309275149
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4015615893
Short name T347
Test name
Test status
Simulation time 605727116046 ps
CPU time 171.67 seconds
Started May 26 02:29:21 PM PDT 24
Finished May 26 02:32:13 PM PDT 24
Peak memory 190900 kb
Host smart-ec417ff7-7725-43c0-b4a4-ef5e5f96851f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015615893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4015615893
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2975615819
Short name T348
Test name
Test status
Simulation time 441039458106 ps
CPU time 204.1 seconds
Started May 26 02:29:42 PM PDT 24
Finished May 26 02:33:06 PM PDT 24
Peak memory 190876 kb
Host smart-383b85ae-300c-4d47-b27c-f77e5665faac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975615819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2975615819
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1759484695
Short name T54
Test name
Test status
Simulation time 198520641865 ps
CPU time 184.3 seconds
Started May 26 02:29:23 PM PDT 24
Finished May 26 02:32:28 PM PDT 24
Peak memory 190904 kb
Host smart-b3322a21-4b9e-45af-9610-ce0eb1e75fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759484695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1759484695
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1724204259
Short name T156
Test name
Test status
Simulation time 530408245188 ps
CPU time 1132.19 seconds
Started May 26 02:29:22 PM PDT 24
Finished May 26 02:48:15 PM PDT 24
Peak memory 190888 kb
Host smart-78275770-1c96-4bbd-9742-ed2c4ab48c6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724204259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1724204259
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3624267363
Short name T155
Test name
Test status
Simulation time 135154486249 ps
CPU time 56.09 seconds
Started May 26 02:29:22 PM PDT 24
Finished May 26 02:30:18 PM PDT 24
Peak memory 182696 kb
Host smart-fd633a23-49b4-4032-9ede-90a30d91006c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624267363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3624267363
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.863286199
Short name T336
Test name
Test status
Simulation time 244480246590 ps
CPU time 306.36 seconds
Started May 26 02:29:21 PM PDT 24
Finished May 26 02:34:28 PM PDT 24
Peak memory 190904 kb
Host smart-38d809c5-be5b-455d-aa01-214e73589350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863286199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.863286199
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3137050421
Short name T228
Test name
Test status
Simulation time 159511038246 ps
CPU time 241.91 seconds
Started May 26 02:29:28 PM PDT 24
Finished May 26 02:33:31 PM PDT 24
Peak memory 194184 kb
Host smart-9b8aa19d-4ff3-42ba-9399-91e7e52ed907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137050421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3137050421
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3927839416
Short name T208
Test name
Test status
Simulation time 215172156047 ps
CPU time 97.96 seconds
Started May 26 02:29:31 PM PDT 24
Finished May 26 02:31:09 PM PDT 24
Peak memory 190892 kb
Host smart-d42d82f9-e984-4883-b799-ffd73f1bb922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927839416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3927839416
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.477487104
Short name T183
Test name
Test status
Simulation time 176992318304 ps
CPU time 61.59 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:28:18 PM PDT 24
Peak memory 182708 kb
Host smart-27189c33-e054-487d-84a5-72b5fba82264
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477487104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.477487104
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3447998208
Short name T445
Test name
Test status
Simulation time 60568442976 ps
CPU time 81.04 seconds
Started May 26 02:27:18 PM PDT 24
Finished May 26 02:28:39 PM PDT 24
Peak memory 182676 kb
Host smart-b05e08e6-f68d-4704-ad2d-474cddedacda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447998208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3447998208
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2190119044
Short name T104
Test name
Test status
Simulation time 22670792818 ps
CPU time 16.29 seconds
Started May 26 02:27:13 PM PDT 24
Finished May 26 02:27:31 PM PDT 24
Peak memory 182700 kb
Host smart-fde00e8c-8a7c-4ba5-8b84-e79bb0514cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190119044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2190119044
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2663134900
Short name T313
Test name
Test status
Simulation time 393591475303 ps
CPU time 542.04 seconds
Started May 26 02:27:11 PM PDT 24
Finished May 26 02:36:14 PM PDT 24
Peak memory 190896 kb
Host smart-4c6e7fd3-3f9e-45ac-a569-dde2fe135e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663134900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2663134900
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3074249227
Short name T297
Test name
Test status
Simulation time 458000109228 ps
CPU time 1293.71 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:48:51 PM PDT 24
Peak memory 190916 kb
Host smart-77faea59-6c48-4650-802e-bad1ba6d0975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074249227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3074249227
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.1953820599
Short name T4
Test name
Test status
Simulation time 6212038490 ps
CPU time 3.48 seconds
Started May 26 02:29:28 PM PDT 24
Finished May 26 02:29:32 PM PDT 24
Peak memory 182692 kb
Host smart-c319df59-fe5b-4e7e-843c-8a95bee4c569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953820599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1953820599
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.273969322
Short name T168
Test name
Test status
Simulation time 76786894238 ps
CPU time 68.22 seconds
Started May 26 02:29:29 PM PDT 24
Finished May 26 02:30:38 PM PDT 24
Peak memory 190892 kb
Host smart-c6870cdd-1872-47c8-9879-7df7c12e52d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273969322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.273969322
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1946952699
Short name T144
Test name
Test status
Simulation time 45698159351 ps
CPU time 467.64 seconds
Started May 26 02:29:29 PM PDT 24
Finished May 26 02:37:17 PM PDT 24
Peak memory 190896 kb
Host smart-4319f19d-82ac-48b2-9522-75e76eee3b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946952699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1946952699
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.181241572
Short name T277
Test name
Test status
Simulation time 92871947765 ps
CPU time 143.61 seconds
Started May 26 02:29:29 PM PDT 24
Finished May 26 02:31:53 PM PDT 24
Peak memory 190852 kb
Host smart-904f4605-ef9a-4832-a6e5-aa0275537d64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181241572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.181241572
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2014008811
Short name T180
Test name
Test status
Simulation time 48282778272 ps
CPU time 311.57 seconds
Started May 26 02:29:30 PM PDT 24
Finished May 26 02:34:42 PM PDT 24
Peak memory 190892 kb
Host smart-ee9d2e5b-b240-47da-865c-369bb1f798d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014008811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2014008811
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3321685663
Short name T166
Test name
Test status
Simulation time 64792817557 ps
CPU time 63.72 seconds
Started May 26 02:29:28 PM PDT 24
Finished May 26 02:30:33 PM PDT 24
Peak memory 190952 kb
Host smart-df468ddc-414e-4477-8018-2fa7c4f5f833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321685663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3321685663
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2268064093
Short name T342
Test name
Test status
Simulation time 1146903796546 ps
CPU time 468.24 seconds
Started May 26 02:29:31 PM PDT 24
Finished May 26 02:37:20 PM PDT 24
Peak memory 190896 kb
Host smart-37618469-d83b-4f04-8e57-f9a1c959654c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268064093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2268064093
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.4033962583
Short name T193
Test name
Test status
Simulation time 182255194860 ps
CPU time 260.87 seconds
Started May 26 02:29:28 PM PDT 24
Finished May 26 02:33:50 PM PDT 24
Peak memory 190904 kb
Host smart-a4c79653-4e20-4e75-816c-dadf8ba50408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033962583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4033962583
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.850304459
Short name T45
Test name
Test status
Simulation time 188427159778 ps
CPU time 50.95 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:28:08 PM PDT 24
Peak memory 182676 kb
Host smart-1211e409-42de-42c5-a4c1-5827757bb7d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850304459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.850304459
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_random.1146998017
Short name T363
Test name
Test status
Simulation time 48529307320 ps
CPU time 75.72 seconds
Started May 26 02:27:18 PM PDT 24
Finished May 26 02:28:35 PM PDT 24
Peak memory 190900 kb
Host smart-c3dd0741-8617-4dbf-81de-ba491299e1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146998017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1146998017
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.174154256
Short name T23
Test name
Test status
Simulation time 42500720622 ps
CPU time 28.84 seconds
Started May 26 02:27:18 PM PDT 24
Finished May 26 02:27:48 PM PDT 24
Peak memory 194184 kb
Host smart-64306701-7da7-4c2c-bf8c-e9b7e649bcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174154256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.174154256
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.713739224
Short name T10
Test name
Test status
Simulation time 299963004642 ps
CPU time 452.1 seconds
Started May 26 02:27:16 PM PDT 24
Finished May 26 02:34:49 PM PDT 24
Peak memory 190908 kb
Host smart-40a9af85-85d5-4dfe-a1ce-6a9ad2c85b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713739224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
713739224
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.961744795
Short name T11
Test name
Test status
Simulation time 191995176985 ps
CPU time 366.37 seconds
Started May 26 02:27:11 PM PDT 24
Finished May 26 02:33:19 PM PDT 24
Peak memory 205564 kb
Host smart-9ad5be0b-4bf2-4d37-8b6d-3d64e0d01dc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961744795 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.961744795
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.rv_timer_random.3823578861
Short name T181
Test name
Test status
Simulation time 706168351441 ps
CPU time 779.76 seconds
Started May 26 02:29:28 PM PDT 24
Finished May 26 02:42:29 PM PDT 24
Peak memory 190892 kb
Host smart-58d0d8c7-6c0b-4e6d-adf4-655a24b7d2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823578861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3823578861
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4294289873
Short name T147
Test name
Test status
Simulation time 115508710159 ps
CPU time 337.32 seconds
Started May 26 02:29:36 PM PDT 24
Finished May 26 02:35:14 PM PDT 24
Peak memory 190852 kb
Host smart-f40b2569-0227-482a-bccd-bc1525c96e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294289873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4294289873
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2611832419
Short name T121
Test name
Test status
Simulation time 378212528519 ps
CPU time 355.92 seconds
Started May 26 02:29:36 PM PDT 24
Finished May 26 02:35:32 PM PDT 24
Peak memory 190900 kb
Host smart-799d9bb3-6963-41e9-bf7c-685a0551c810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611832419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2611832419
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.452553887
Short name T151
Test name
Test status
Simulation time 87320530327 ps
CPU time 624.06 seconds
Started May 26 02:29:37 PM PDT 24
Finished May 26 02:40:02 PM PDT 24
Peak memory 190908 kb
Host smart-cdbc2276-e275-4024-999a-6064f2fa859d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452553887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.452553887
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3014244716
Short name T135
Test name
Test status
Simulation time 130012219398 ps
CPU time 227.22 seconds
Started May 26 02:29:35 PM PDT 24
Finished May 26 02:33:23 PM PDT 24
Peak memory 190780 kb
Host smart-0c105666-bf3c-421d-9f21-39d14fea9ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014244716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3014244716
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3504050871
Short name T201
Test name
Test status
Simulation time 691323635714 ps
CPU time 1696.35 seconds
Started May 26 02:29:36 PM PDT 24
Finished May 26 02:57:53 PM PDT 24
Peak memory 190852 kb
Host smart-4d206f4b-d28f-4958-8c34-1221388e6056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504050871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3504050871
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2610038621
Short name T388
Test name
Test status
Simulation time 94221084067 ps
CPU time 138.74 seconds
Started May 26 02:26:57 PM PDT 24
Finished May 26 02:29:18 PM PDT 24
Peak memory 182672 kb
Host smart-9f2bb9b1-b0a7-4e82-827b-e51bc10c3b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610038621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2610038621
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.177351224
Short name T59
Test name
Test status
Simulation time 27310654 ps
CPU time 0.56 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:27:01 PM PDT 24
Peak memory 182008 kb
Host smart-903ca66b-25ed-414d-a934-ac1fb23f8c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177351224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.177351224
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1562457012
Short name T13
Test name
Test status
Simulation time 165356473 ps
CPU time 0.89 seconds
Started May 26 02:26:58 PM PDT 24
Finished May 26 02:27:01 PM PDT 24
Peak memory 214264 kb
Host smart-2f21ba1f-cf35-4f58-8a90-d787f8c33781
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562457012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1562457012
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2443343443
Short name T70
Test name
Test status
Simulation time 242470192626 ps
CPU time 728.93 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:39:10 PM PDT 24
Peak memory 190728 kb
Host smart-21e42fd6-2a1d-4c6a-9d2c-07a80b0e5766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443343443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2443343443
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2322143143
Short name T448
Test name
Test status
Simulation time 158861843952 ps
CPU time 189.75 seconds
Started May 26 02:26:57 PM PDT 24
Finished May 26 02:30:07 PM PDT 24
Peak memory 206116 kb
Host smart-721d51dc-a0bc-4e70-88f6-5dae2ac66228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322143143 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2322143143
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2792503689
Short name T192
Test name
Test status
Simulation time 37563430973 ps
CPU time 37.82 seconds
Started May 26 02:27:14 PM PDT 24
Finished May 26 02:27:53 PM PDT 24
Peak memory 182716 kb
Host smart-a71ac9cb-18e8-4845-a24c-2a5823f288b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792503689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2792503689
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3385984431
Short name T395
Test name
Test status
Simulation time 59664056348 ps
CPU time 94.42 seconds
Started May 26 02:27:12 PM PDT 24
Finished May 26 02:28:47 PM PDT 24
Peak memory 182712 kb
Host smart-e9281215-c447-4a75-9cad-7f264c939472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385984431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3385984431
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3524773381
Short name T209
Test name
Test status
Simulation time 151135482606 ps
CPU time 145.11 seconds
Started May 26 02:27:19 PM PDT 24
Finished May 26 02:29:45 PM PDT 24
Peak memory 193408 kb
Host smart-9f9aad31-123c-4d18-9aaa-09656c2192a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524773381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3524773381
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1646187972
Short name T224
Test name
Test status
Simulation time 566259239666 ps
CPU time 796.76 seconds
Started May 26 02:27:21 PM PDT 24
Finished May 26 02:40:39 PM PDT 24
Peak memory 190908 kb
Host smart-92923a10-aa70-4a59-a06c-d6bc94d79bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646187972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1646187972
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3663653149
Short name T195
Test name
Test status
Simulation time 26606571295 ps
CPU time 37.69 seconds
Started May 26 02:27:22 PM PDT 24
Finished May 26 02:28:00 PM PDT 24
Peak memory 182724 kb
Host smart-00c55287-2263-4fca-ad70-8c21906e986c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663653149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3663653149
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.380604081
Short name T423
Test name
Test status
Simulation time 54814736263 ps
CPU time 90.23 seconds
Started May 26 02:27:19 PM PDT 24
Finished May 26 02:28:50 PM PDT 24
Peak memory 182700 kb
Host smart-cd57bd4c-4ae2-4046-8683-07d6ecd3f818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380604081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.380604081
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.193874800
Short name T132
Test name
Test status
Simulation time 33893693452 ps
CPU time 52.1 seconds
Started May 26 02:27:20 PM PDT 24
Finished May 26 02:28:13 PM PDT 24
Peak memory 182556 kb
Host smart-699627cb-0f9d-42c2-bdab-9a7788d73d08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193874800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.193874800
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.246188571
Short name T335
Test name
Test status
Simulation time 180201146029 ps
CPU time 335.07 seconds
Started May 26 02:27:20 PM PDT 24
Finished May 26 02:32:57 PM PDT 24
Peak memory 190888 kb
Host smart-58763295-a1eb-4db3-b414-35022b22801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246188571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.246188571
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3037239608
Short name T153
Test name
Test status
Simulation time 90520207963 ps
CPU time 160.01 seconds
Started May 26 02:27:21 PM PDT 24
Finished May 26 02:30:02 PM PDT 24
Peak memory 182760 kb
Host smart-822f3404-b591-40a8-bcee-dff5f79dd9bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037239608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3037239608
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.4055719604
Short name T444
Test name
Test status
Simulation time 463635954058 ps
CPU time 162.66 seconds
Started May 26 02:27:20 PM PDT 24
Finished May 26 02:30:04 PM PDT 24
Peak memory 182864 kb
Host smart-855f892f-9361-46b1-8757-795ed8e2887b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055719604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.4055719604
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.4069928773
Short name T2
Test name
Test status
Simulation time 223352069222 ps
CPU time 206.78 seconds
Started May 26 02:27:18 PM PDT 24
Finished May 26 02:30:46 PM PDT 24
Peak memory 190892 kb
Host smart-f3898304-a1ca-476a-905e-6bd73fe0c1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069928773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.4069928773
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3325770191
Short name T148
Test name
Test status
Simulation time 41175226626 ps
CPU time 416.26 seconds
Started May 26 02:27:22 PM PDT 24
Finished May 26 02:34:19 PM PDT 24
Peak memory 194504 kb
Host smart-d683934d-ab9d-49e6-8cc6-c28b8dbaa3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325770191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3325770191
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3292147763
Short name T415
Test name
Test status
Simulation time 2726599459 ps
CPU time 4.99 seconds
Started May 26 02:27:21 PM PDT 24
Finished May 26 02:27:27 PM PDT 24
Peak memory 182696 kb
Host smart-3301bdc3-fbe7-4110-8fec-81453e284719
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292147763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3292147763
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2314215913
Short name T403
Test name
Test status
Simulation time 124555357011 ps
CPU time 207.88 seconds
Started May 26 02:27:25 PM PDT 24
Finished May 26 02:30:54 PM PDT 24
Peak memory 182716 kb
Host smart-06ad6e76-6724-4d11-ac66-4b79e8c0946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314215913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2314215913
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.19545367
Short name T149
Test name
Test status
Simulation time 105242763116 ps
CPU time 168.41 seconds
Started May 26 02:27:19 PM PDT 24
Finished May 26 02:30:08 PM PDT 24
Peak memory 190868 kb
Host smart-2cc9fc59-3732-4d11-b502-155767319014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19545367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.19545367
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1672129451
Short name T141
Test name
Test status
Simulation time 188892010038 ps
CPU time 101.43 seconds
Started May 26 02:27:23 PM PDT 24
Finished May 26 02:29:05 PM PDT 24
Peak memory 190904 kb
Host smart-3ead2ce8-41bb-4516-b517-a15dc5dbf33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672129451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1672129451
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.886081501
Short name T37
Test name
Test status
Simulation time 75520949156 ps
CPU time 130.24 seconds
Started May 26 02:27:19 PM PDT 24
Finished May 26 02:29:30 PM PDT 24
Peak memory 197372 kb
Host smart-b488b062-611c-4ea5-81f1-de730654786a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886081501 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.886081501
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2955970771
Short name T366
Test name
Test status
Simulation time 131592149565 ps
CPU time 128.78 seconds
Started May 26 02:27:19 PM PDT 24
Finished May 26 02:29:29 PM PDT 24
Peak memory 182696 kb
Host smart-cd30de45-b81f-4322-aba6-2be0da86948b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955970771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2955970771
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1603301432
Short name T428
Test name
Test status
Simulation time 11581702678 ps
CPU time 22.05 seconds
Started May 26 02:27:25 PM PDT 24
Finished May 26 02:27:48 PM PDT 24
Peak memory 190916 kb
Host smart-bc3b33ee-98fb-48f7-aa1b-9ac8d454d213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603301432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1603301432
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.6661357
Short name T302
Test name
Test status
Simulation time 1054645631672 ps
CPU time 469.02 seconds
Started May 26 02:27:22 PM PDT 24
Finished May 26 02:35:12 PM PDT 24
Peak memory 182704 kb
Host smart-f08d2a09-9426-4693-8553-1c4e0aed5107
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6661357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
rv_timer_cfg_update_on_fly.6661357
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.684260126
Short name T295
Test name
Test status
Simulation time 68740036974 ps
CPU time 573.64 seconds
Started May 26 02:27:18 PM PDT 24
Finished May 26 02:36:53 PM PDT 24
Peak memory 190892 kb
Host smart-66956175-edcd-4fdb-bdb1-4904ca147805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684260126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.684260126
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.639325915
Short name T128
Test name
Test status
Simulation time 199892060227 ps
CPU time 104.37 seconds
Started May 26 02:27:20 PM PDT 24
Finished May 26 02:29:05 PM PDT 24
Peak memory 190880 kb
Host smart-9b854868-5a07-44c1-8690-b66a1cb41662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639325915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.639325915
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.4283419766
Short name T436
Test name
Test status
Simulation time 823815918173 ps
CPU time 326.03 seconds
Started May 26 02:27:19 PM PDT 24
Finished May 26 02:32:46 PM PDT 24
Peak memory 194340 kb
Host smart-c57da6d0-b09e-475c-a6ec-daca31d74392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283419766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.4283419766
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2369588554
Short name T376
Test name
Test status
Simulation time 798151482132 ps
CPU time 254.19 seconds
Started May 26 02:27:33 PM PDT 24
Finished May 26 02:31:48 PM PDT 24
Peak memory 182684 kb
Host smart-8b286147-734b-4368-ab0e-6586394f1fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369588554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2369588554
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3598140233
Short name T123
Test name
Test status
Simulation time 244548910121 ps
CPU time 107.04 seconds
Started May 26 02:27:22 PM PDT 24
Finished May 26 02:29:10 PM PDT 24
Peak memory 190900 kb
Host smart-f650076b-699d-41e5-9b74-d8b247eda655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598140233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3598140233
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2135362664
Short name T46
Test name
Test status
Simulation time 123112359 ps
CPU time 0.67 seconds
Started May 26 02:27:20 PM PDT 24
Finished May 26 02:27:22 PM PDT 24
Peak memory 182508 kb
Host smart-d1bbf651-cb40-49c9-8cf1-32d0237db106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135362664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2135362664
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3969029223
Short name T401
Test name
Test status
Simulation time 38279465476 ps
CPU time 55.7 seconds
Started May 26 02:27:20 PM PDT 24
Finished May 26 02:28:17 PM PDT 24
Peak memory 182708 kb
Host smart-9d2ab656-9b7e-44eb-9042-cd501e50e20f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969029223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3969029223
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.398898365
Short name T323
Test name
Test status
Simulation time 334950128889 ps
CPU time 185.69 seconds
Started May 26 02:27:21 PM PDT 24
Finished May 26 02:30:28 PM PDT 24
Peak memory 182712 kb
Host smart-f1ecdad8-fe08-4d0f-99ab-017fbf83810f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398898365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.398898365
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1925877991
Short name T58
Test name
Test status
Simulation time 263652750810 ps
CPU time 87.04 seconds
Started May 26 02:27:19 PM PDT 24
Finished May 26 02:28:47 PM PDT 24
Peak memory 182704 kb
Host smart-830270db-4566-4d85-8016-00d86363bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925877991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1925877991
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.891610198
Short name T378
Test name
Test status
Simulation time 183786272 ps
CPU time 0.79 seconds
Started May 26 02:27:20 PM PDT 24
Finished May 26 02:27:22 PM PDT 24
Peak memory 182508 kb
Host smart-c2901bec-f873-4460-bb61-1b6958f48ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891610198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.891610198
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1265627952
Short name T57
Test name
Test status
Simulation time 738663764039 ps
CPU time 690.38 seconds
Started May 26 02:27:31 PM PDT 24
Finished May 26 02:39:02 PM PDT 24
Peak memory 182732 kb
Host smart-87d7ff19-5be0-4401-9b77-dc66d834a0e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265627952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1265627952
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1029384467
Short name T380
Test name
Test status
Simulation time 334597906408 ps
CPU time 149.42 seconds
Started May 26 02:27:27 PM PDT 24
Finished May 26 02:29:58 PM PDT 24
Peak memory 182668 kb
Host smart-2f456b74-2f69-4449-aec4-0aaccb8e43b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029384467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1029384467
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1624644190
Short name T426
Test name
Test status
Simulation time 46460617825 ps
CPU time 27.07 seconds
Started May 26 02:27:27 PM PDT 24
Finished May 26 02:27:56 PM PDT 24
Peak memory 190888 kb
Host smart-a78a1252-42fc-4266-bb0c-24774e99415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624644190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1624644190
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2205648166
Short name T66
Test name
Test status
Simulation time 339054206040 ps
CPU time 48.28 seconds
Started May 26 02:27:28 PM PDT 24
Finished May 26 02:28:17 PM PDT 24
Peak memory 182708 kb
Host smart-6e42b70b-f44d-48ad-ab55-a93333865835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205648166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2205648166
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.678344839
Short name T146
Test name
Test status
Simulation time 1380738702065 ps
CPU time 710.35 seconds
Started May 26 02:27:28 PM PDT 24
Finished May 26 02:39:20 PM PDT 24
Peak memory 182712 kb
Host smart-1e448d5d-7cee-418d-8c7e-f527930fab83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678344839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.678344839
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1553849362
Short name T439
Test name
Test status
Simulation time 98993216769 ps
CPU time 152.3 seconds
Started May 26 02:27:32 PM PDT 24
Finished May 26 02:30:04 PM PDT 24
Peak memory 182716 kb
Host smart-60de1d17-eea9-43d4-91e3-2a7038823ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553849362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1553849362
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.817768482
Short name T345
Test name
Test status
Simulation time 73275321482 ps
CPU time 131.32 seconds
Started May 26 02:27:32 PM PDT 24
Finished May 26 02:29:43 PM PDT 24
Peak memory 194168 kb
Host smart-1f83ed02-da84-4aeb-8068-9461249a93cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817768482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.817768482
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1017629749
Short name T304
Test name
Test status
Simulation time 394874071204 ps
CPU time 616.42 seconds
Started May 26 02:27:28 PM PDT 24
Finished May 26 02:37:46 PM PDT 24
Peak memory 194532 kb
Host smart-b34269d0-9b76-4ad3-b583-d8b5627143f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017629749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1017629749
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.298555403
Short name T18
Test name
Test status
Simulation time 221970439455 ps
CPU time 108.01 seconds
Started May 26 02:26:55 PM PDT 24
Finished May 26 02:28:44 PM PDT 24
Peak memory 182700 kb
Host smart-d25623fd-326c-4ec8-973a-25d8464008ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298555403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.298555403
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3701395937
Short name T286
Test name
Test status
Simulation time 646814079368 ps
CPU time 708.06 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:38:49 PM PDT 24
Peak memory 190908 kb
Host smart-ed4b0681-93cc-4be5-b830-fa2fc9caaf14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701395937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3701395937
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3485343827
Short name T417
Test name
Test status
Simulation time 82945975 ps
CPU time 0.54 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:27:02 PM PDT 24
Peak memory 182496 kb
Host smart-6aba542c-a84d-4e04-a989-8d2379cee042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485343827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3485343827
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2297833792
Short name T17
Test name
Test status
Simulation time 139262167 ps
CPU time 0.99 seconds
Started May 26 02:26:56 PM PDT 24
Finished May 26 02:26:57 PM PDT 24
Peak memory 214096 kb
Host smart-9681e12f-cb8b-4549-9374-0f2716c65eea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297833792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2297833792
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3918657868
Short name T212
Test name
Test status
Simulation time 2298526695667 ps
CPU time 1384.57 seconds
Started May 26 02:27:00 PM PDT 24
Finished May 26 02:50:06 PM PDT 24
Peak memory 190836 kb
Host smart-f824d0d8-d015-46ba-9235-844060494b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918657868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3918657868
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.64139005
Short name T33
Test name
Test status
Simulation time 55509770871 ps
CPU time 377.23 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:33:18 PM PDT 24
Peak memory 196676 kb
Host smart-50317453-7af2-42bc-ab1e-f09d2cee478a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64139005 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.64139005
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.931618838
Short name T251
Test name
Test status
Simulation time 50777444358 ps
CPU time 87.25 seconds
Started May 26 02:27:26 PM PDT 24
Finished May 26 02:28:55 PM PDT 24
Peak memory 182700 kb
Host smart-61ec7361-fa9f-4f10-8261-02c0eebcb44e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931618838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.931618838
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1094711599
Short name T74
Test name
Test status
Simulation time 47825945802 ps
CPU time 66.79 seconds
Started May 26 02:27:31 PM PDT 24
Finished May 26 02:28:38 PM PDT 24
Peak memory 182720 kb
Host smart-a13cecf2-8beb-4324-8202-dcaa66a05dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094711599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1094711599
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3381493552
Short name T410
Test name
Test status
Simulation time 810551059 ps
CPU time 0.89 seconds
Started May 26 02:27:32 PM PDT 24
Finished May 26 02:27:34 PM PDT 24
Peak memory 182508 kb
Host smart-cd76fd29-188a-4047-88b1-59220d027dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381493552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3381493552
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3180211205
Short name T325
Test name
Test status
Simulation time 1485316893195 ps
CPU time 383.93 seconds
Started May 26 02:27:27 PM PDT 24
Finished May 26 02:33:52 PM PDT 24
Peak memory 182720 kb
Host smart-5431b773-f197-4c1c-9302-906a3565fdbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180211205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3180211205
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.23059984
Short name T383
Test name
Test status
Simulation time 50089180045 ps
CPU time 70.6 seconds
Started May 26 02:27:25 PM PDT 24
Finished May 26 02:28:38 PM PDT 24
Peak memory 182700 kb
Host smart-d15458d8-e965-44fd-9c01-3619a7c6739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23059984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.23059984
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1426159839
Short name T197
Test name
Test status
Simulation time 145225261253 ps
CPU time 246.42 seconds
Started May 26 02:27:30 PM PDT 24
Finished May 26 02:31:38 PM PDT 24
Peak memory 190860 kb
Host smart-99859e8c-7b00-4753-a2e3-2e80063f0110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426159839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1426159839
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2067589396
Short name T179
Test name
Test status
Simulation time 59224989324 ps
CPU time 26.6 seconds
Started May 26 02:27:27 PM PDT 24
Finished May 26 02:27:55 PM PDT 24
Peak memory 182712 kb
Host smart-92f49403-38cb-4e69-85ea-1577358a5b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067589396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2067589396
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3778381275
Short name T252
Test name
Test status
Simulation time 59568239607 ps
CPU time 102.51 seconds
Started May 26 02:27:28 PM PDT 24
Finished May 26 02:29:11 PM PDT 24
Peak memory 182600 kb
Host smart-04208df1-33bc-4ceb-92bc-b1df9fc56d96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778381275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3778381275
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2075292834
Short name T390
Test name
Test status
Simulation time 163844828911 ps
CPU time 256.58 seconds
Started May 26 02:27:33 PM PDT 24
Finished May 26 02:31:50 PM PDT 24
Peak memory 182684 kb
Host smart-6edfab8a-2a8a-4b3d-9da5-1314e3ffdcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075292834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2075292834
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3304542304
Short name T136
Test name
Test status
Simulation time 168216069313 ps
CPU time 1127.75 seconds
Started May 26 02:27:31 PM PDT 24
Finished May 26 02:46:19 PM PDT 24
Peak memory 190908 kb
Host smart-d04c9744-af1c-44d0-b6bf-a7a6a2c15aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304542304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3304542304
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.505886446
Short name T159
Test name
Test status
Simulation time 401164222430 ps
CPU time 383.05 seconds
Started May 26 02:27:30 PM PDT 24
Finished May 26 02:33:54 PM PDT 24
Peak memory 190872 kb
Host smart-96d3772e-1f9a-44ac-808f-8535b1659365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505886446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.505886446
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.881986678
Short name T256
Test name
Test status
Simulation time 547590101117 ps
CPU time 403.56 seconds
Started May 26 02:27:27 PM PDT 24
Finished May 26 02:34:12 PM PDT 24
Peak memory 182708 kb
Host smart-f45ee7ff-6e07-47ea-9fd0-b2df805f1ff2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881986678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.881986678
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3191487758
Short name T394
Test name
Test status
Simulation time 799932825728 ps
CPU time 170.51 seconds
Started May 26 02:27:33 PM PDT 24
Finished May 26 02:30:24 PM PDT 24
Peak memory 182676 kb
Host smart-4d19dc75-c989-4d63-bd39-a2f4585a0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191487758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3191487758
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.448067394
Short name T414
Test name
Test status
Simulation time 13242490017 ps
CPU time 22.37 seconds
Started May 26 02:27:32 PM PDT 24
Finished May 26 02:27:55 PM PDT 24
Peak memory 194048 kb
Host smart-ee07c41e-140e-46a9-b7cf-0417b4fa37b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448067394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.448067394
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.86134644
Short name T39
Test name
Test status
Simulation time 922169793433 ps
CPU time 525.97 seconds
Started May 26 02:27:33 PM PDT 24
Finished May 26 02:36:19 PM PDT 24
Peak memory 182880 kb
Host smart-505112fa-b6e3-41ed-aff5-28d0172a0ab6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86134644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.rv_timer_cfg_update_on_fly.86134644
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1262421553
Short name T377
Test name
Test status
Simulation time 45000846796 ps
CPU time 64.69 seconds
Started May 26 02:27:34 PM PDT 24
Finished May 26 02:28:39 PM PDT 24
Peak memory 182720 kb
Host smart-7fc3ccd4-f716-4fda-9e27-eacca8e5c899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262421553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1262421553
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2582099102
Short name T303
Test name
Test status
Simulation time 325399207004 ps
CPU time 111.85 seconds
Started May 26 02:27:34 PM PDT 24
Finished May 26 02:29:26 PM PDT 24
Peak memory 182688 kb
Host smart-b0bc3f89-0539-497a-ad9e-7d7d2599621e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582099102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2582099102
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3198220869
Short name T356
Test name
Test status
Simulation time 19403802844 ps
CPU time 231.97 seconds
Started May 26 02:27:35 PM PDT 24
Finished May 26 02:31:29 PM PDT 24
Peak memory 182740 kb
Host smart-1b494b5d-41fa-4c16-bc21-78628b329659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198220869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3198220869
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1181087822
Short name T55
Test name
Test status
Simulation time 62284091 ps
CPU time 0.53 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:27:38 PM PDT 24
Peak memory 181932 kb
Host smart-c964df2b-3719-4486-a75c-fe000c5c8207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181087822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1181087822
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.124029811
Short name T138
Test name
Test status
Simulation time 387469138830 ps
CPU time 608.76 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:37:46 PM PDT 24
Peak memory 182692 kb
Host smart-fc9262d5-b7cf-44bc-84be-f6164d94f202
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124029811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.124029811
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2001226015
Short name T435
Test name
Test status
Simulation time 47503088348 ps
CPU time 69.54 seconds
Started May 26 02:27:37 PM PDT 24
Finished May 26 02:28:47 PM PDT 24
Peak memory 182648 kb
Host smart-9c8ed811-3dc5-4903-9ac9-b0c594817ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001226015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2001226015
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1003282822
Short name T409
Test name
Test status
Simulation time 30925264147 ps
CPU time 32.98 seconds
Started May 26 02:27:33 PM PDT 24
Finished May 26 02:28:07 PM PDT 24
Peak memory 182524 kb
Host smart-833aedd2-abd9-4670-a75a-d7d4b3883ca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003282822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1003282822
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.615894767
Short name T430
Test name
Test status
Simulation time 1622372628 ps
CPU time 1.19 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:27:38 PM PDT 24
Peak memory 182528 kb
Host smart-07452a7b-e289-4bad-9541-73fac628f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615894767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.615894767
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1825147110
Short name T257
Test name
Test status
Simulation time 884171679878 ps
CPU time 1298.69 seconds
Started May 26 02:27:34 PM PDT 24
Finished May 26 02:49:13 PM PDT 24
Peak memory 194292 kb
Host smart-90513fc4-23e3-4482-ad6d-838133f09a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825147110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1825147110
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4061285133
Short name T373
Test name
Test status
Simulation time 337984875084 ps
CPU time 457.21 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:35:14 PM PDT 24
Peak memory 182704 kb
Host smart-14a90891-9a8d-44c6-9fc2-e4691f492195
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061285133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4061285133
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.827355118
Short name T386
Test name
Test status
Simulation time 76152283151 ps
CPU time 118.76 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:29:36 PM PDT 24
Peak memory 182720 kb
Host smart-7d871799-bed0-4a8c-bc0a-ce73bc59faab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827355118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.827355118
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3282908296
Short name T24
Test name
Test status
Simulation time 861586872 ps
CPU time 4.25 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:27:41 PM PDT 24
Peak memory 193572 kb
Host smart-5f999b95-6012-4a18-b41e-5c71cd34713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282908296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3282908296
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3969579987
Short name T32
Test name
Test status
Simulation time 81736833381 ps
CPU time 161.04 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:30:18 PM PDT 24
Peak memory 197272 kb
Host smart-768ae97d-863c-4dfe-86a0-ed43605c0c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969579987 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3969579987
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3445914070
Short name T236
Test name
Test status
Simulation time 311856055389 ps
CPU time 297.24 seconds
Started May 26 02:27:35 PM PDT 24
Finished May 26 02:32:33 PM PDT 24
Peak memory 182712 kb
Host smart-9f9a16d0-e87a-4a6a-9333-29f16c8bf803
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445914070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3445914070
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2971486618
Short name T375
Test name
Test status
Simulation time 808634743846 ps
CPU time 365.94 seconds
Started May 26 02:27:34 PM PDT 24
Finished May 26 02:33:40 PM PDT 24
Peak memory 182704 kb
Host smart-a8e24621-2f35-480d-8161-b1f9350fe802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971486618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2971486618
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3666227939
Short name T371
Test name
Test status
Simulation time 316641813612 ps
CPU time 307.71 seconds
Started May 26 02:27:34 PM PDT 24
Finished May 26 02:32:43 PM PDT 24
Peak memory 190872 kb
Host smart-cf97393c-1874-48d0-b9f3-ae8db730b97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666227939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3666227939
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.142946171
Short name T334
Test name
Test status
Simulation time 37302607472 ps
CPU time 30.93 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:28:08 PM PDT 24
Peak memory 182680 kb
Host smart-f82d4dd4-372e-4815-8b47-e4fd34d641d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142946171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.142946171
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.31927359
Short name T360
Test name
Test status
Simulation time 48567232051 ps
CPU time 89.95 seconds
Started May 26 02:27:37 PM PDT 24
Finished May 26 02:29:08 PM PDT 24
Peak memory 182672 kb
Host smart-174e4385-bbf0-4456-adc9-1ab2db68a96e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31927359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.rv_timer_cfg_update_on_fly.31927359
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.333542112
Short name T42
Test name
Test status
Simulation time 70940234136 ps
CPU time 101.25 seconds
Started May 26 02:27:37 PM PDT 24
Finished May 26 02:29:19 PM PDT 24
Peak memory 182668 kb
Host smart-3e9e4f2d-b9eb-4581-a772-ee2dd1c9f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333542112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.333542112
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3621894084
Short name T246
Test name
Test status
Simulation time 48071681299 ps
CPU time 73.82 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:28:51 PM PDT 24
Peak memory 182652 kb
Host smart-acc0e4de-22f6-4040-8118-b73dbba0898c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621894084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3621894084
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2108221908
Short name T446
Test name
Test status
Simulation time 67575221566 ps
CPU time 60.59 seconds
Started May 26 02:27:36 PM PDT 24
Finished May 26 02:28:38 PM PDT 24
Peak memory 182688 kb
Host smart-b89442a5-48d0-4449-b44e-3960c5ddd787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108221908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2108221908
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.341645987
Short name T12
Test name
Test status
Simulation time 223984775417 ps
CPU time 731.38 seconds
Started May 26 02:27:37 PM PDT 24
Finished May 26 02:39:50 PM PDT 24
Peak memory 207896 kb
Host smart-4b9e8804-0ab2-4957-8e19-762a592d6938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341645987 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.341645987
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.599097208
Short name T189
Test name
Test status
Simulation time 1220272771604 ps
CPU time 645.03 seconds
Started May 26 02:27:37 PM PDT 24
Finished May 26 02:38:23 PM PDT 24
Peak memory 182668 kb
Host smart-e3ea4bd4-da45-4a7f-ac1c-9176e0024283
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599097208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.599097208
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2437518809
Short name T418
Test name
Test status
Simulation time 312332996459 ps
CPU time 244.91 seconds
Started May 26 02:27:38 PM PDT 24
Finished May 26 02:31:43 PM PDT 24
Peak memory 182716 kb
Host smart-e4a23a34-3c85-4976-b1fc-46c9c123017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437518809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2437518809
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.181132882
Short name T312
Test name
Test status
Simulation time 219392326738 ps
CPU time 601.79 seconds
Started May 26 02:27:33 PM PDT 24
Finished May 26 02:37:35 PM PDT 24
Peak memory 190884 kb
Host smart-a75913dd-faa5-42cf-a8fe-7d117b9ab424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181132882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.181132882
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2445054148
Short name T120
Test name
Test status
Simulation time 1631343502103 ps
CPU time 685.06 seconds
Started May 26 02:27:43 PM PDT 24
Finished May 26 02:39:09 PM PDT 24
Peak memory 190908 kb
Host smart-0b2c8fa5-f9ee-414a-a5a5-26cb9102e5c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445054148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2445054148
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3188726073
Short name T359
Test name
Test status
Simulation time 66145730827 ps
CPU time 111.93 seconds
Started May 26 02:27:03 PM PDT 24
Finished May 26 02:28:56 PM PDT 24
Peak memory 182688 kb
Host smart-6fa89038-8d54-444f-9073-ae93fcd04307
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188726073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3188726073
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2299664445
Short name T406
Test name
Test status
Simulation time 432065363447 ps
CPU time 149.83 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:29:31 PM PDT 24
Peak memory 182720 kb
Host smart-b55887d5-9462-4101-8411-fafcf8d31b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299664445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2299664445
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1030549934
Short name T60
Test name
Test status
Simulation time 12510375433 ps
CPU time 22.33 seconds
Started May 26 02:27:01 PM PDT 24
Finished May 26 02:27:25 PM PDT 24
Peak memory 182688 kb
Host smart-b09d9321-dacf-4e0c-a326-6f8ba0db7309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030549934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1030549934
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3443775197
Short name T308
Test name
Test status
Simulation time 94212467456 ps
CPU time 859.79 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:41:21 PM PDT 24
Peak memory 194772 kb
Host smart-f0514590-a97a-418e-9d04-8992f3592d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443775197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3443775197
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1166314536
Short name T14
Test name
Test status
Simulation time 199572041 ps
CPU time 0.91 seconds
Started May 26 02:27:02 PM PDT 24
Finished May 26 02:27:04 PM PDT 24
Peak memory 213216 kb
Host smart-1347a696-b8f6-43de-8c36-b017f3f74903
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166314536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1166314536
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1726505573
Short name T416
Test name
Test status
Simulation time 557894013114 ps
CPU time 367.84 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:33:09 PM PDT 24
Peak memory 190904 kb
Host smart-4d4caee3-d8d7-42ab-90bf-6f31b0039ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726505573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1726505573
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2326393202
Short name T433
Test name
Test status
Simulation time 100225447671 ps
CPU time 176.6 seconds
Started May 26 02:27:41 PM PDT 24
Finished May 26 02:30:39 PM PDT 24
Peak memory 182716 kb
Host smart-202f5333-6ea8-4f45-b690-90d9ec729098
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326393202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2326393202
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1475904958
Short name T52
Test name
Test status
Simulation time 12049512103 ps
CPU time 17.82 seconds
Started May 26 02:27:45 PM PDT 24
Finished May 26 02:28:04 PM PDT 24
Peak memory 182648 kb
Host smart-7247e94c-0114-4d63-a130-53f71baff7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475904958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1475904958
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3825185040
Short name T199
Test name
Test status
Simulation time 72854836317 ps
CPU time 116.98 seconds
Started May 26 02:27:42 PM PDT 24
Finished May 26 02:29:40 PM PDT 24
Peak memory 182708 kb
Host smart-28fe8437-5407-4e7d-8c1d-4bd92f4c0213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825185040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3825185040
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2598000655
Short name T427
Test name
Test status
Simulation time 376229089 ps
CPU time 0.69 seconds
Started May 26 02:27:43 PM PDT 24
Finished May 26 02:27:44 PM PDT 24
Peak memory 182512 kb
Host smart-78aa4d1a-b1bb-4ad1-97dd-7ac9f6007d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598000655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2598000655
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1670548306
Short name T216
Test name
Test status
Simulation time 265225785946 ps
CPU time 1257.94 seconds
Started May 26 02:27:41 PM PDT 24
Finished May 26 02:48:40 PM PDT 24
Peak memory 195052 kb
Host smart-c71eab82-3f41-4da6-a931-743018f7249c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670548306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1670548306
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1156394644
Short name T369
Test name
Test status
Simulation time 12108897256 ps
CPU time 12.4 seconds
Started May 26 02:27:42 PM PDT 24
Finished May 26 02:27:55 PM PDT 24
Peak memory 182728 kb
Host smart-0a84a271-a63e-456e-9acc-d96b08f46759
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156394644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1156394644
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3205717565
Short name T412
Test name
Test status
Simulation time 137752298774 ps
CPU time 223.5 seconds
Started May 26 02:27:40 PM PDT 24
Finished May 26 02:31:24 PM PDT 24
Peak memory 182716 kb
Host smart-3dc071cb-3552-4de5-a435-2e1b02b63105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205717565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3205717565
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1857266359
Short name T429
Test name
Test status
Simulation time 310332248 ps
CPU time 0.74 seconds
Started May 26 02:27:42 PM PDT 24
Finished May 26 02:27:43 PM PDT 24
Peak memory 182384 kb
Host smart-f4ee5afd-a0fa-4816-8a9f-485d368fedd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857266359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1857266359
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2702086851
Short name T333
Test name
Test status
Simulation time 187837020043 ps
CPU time 320.02 seconds
Started May 26 02:27:41 PM PDT 24
Finished May 26 02:33:02 PM PDT 24
Peak memory 182696 kb
Host smart-938993ea-a96a-48f3-8182-c14815ddb064
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702086851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2702086851
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.114408526
Short name T382
Test name
Test status
Simulation time 369871588427 ps
CPU time 157.29 seconds
Started May 26 02:27:44 PM PDT 24
Finished May 26 02:30:21 PM PDT 24
Peak memory 182640 kb
Host smart-5210d6d8-e9ef-4edc-b59a-94f66d220d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114408526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.114408526
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.912906214
Short name T343
Test name
Test status
Simulation time 96048725583 ps
CPU time 314.08 seconds
Started May 26 02:27:41 PM PDT 24
Finished May 26 02:32:55 PM PDT 24
Peak memory 190896 kb
Host smart-9c9e6259-5907-467d-bca7-51ffb99a4208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912906214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.912906214
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2894070821
Short name T230
Test name
Test status
Simulation time 62588425034 ps
CPU time 37.18 seconds
Started May 26 02:27:43 PM PDT 24
Finished May 26 02:28:21 PM PDT 24
Peak memory 190884 kb
Host smart-cf8e7a41-12e3-4ab4-abfd-5844ef472d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894070821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2894070821
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3129533190
Short name T250
Test name
Test status
Simulation time 400534884324 ps
CPU time 864.14 seconds
Started May 26 02:27:40 PM PDT 24
Finished May 26 02:42:05 PM PDT 24
Peak memory 190900 kb
Host smart-57a3ed35-e08a-403f-9398-f497012ef21d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129533190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3129533190
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.842781268
Short name T218
Test name
Test status
Simulation time 183053436817 ps
CPU time 183.84 seconds
Started May 26 02:27:43 PM PDT 24
Finished May 26 02:30:47 PM PDT 24
Peak memory 182704 kb
Host smart-5f99cc83-c4f5-4453-a2c1-392168647b8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842781268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.842781268
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.637161403
Short name T399
Test name
Test status
Simulation time 219113229974 ps
CPU time 295.64 seconds
Started May 26 02:27:45 PM PDT 24
Finished May 26 02:32:42 PM PDT 24
Peak memory 182656 kb
Host smart-4a54813b-e6eb-4ce3-9202-aafa0046d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637161403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.637161403
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.4186065188
Short name T213
Test name
Test status
Simulation time 229050051935 ps
CPU time 593.62 seconds
Started May 26 02:27:42 PM PDT 24
Finished May 26 02:37:37 PM PDT 24
Peak memory 190908 kb
Host smart-92badc95-9b06-4fcb-9383-044afea32994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186065188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4186065188
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.563214149
Short name T1
Test name
Test status
Simulation time 40771547220 ps
CPU time 272.58 seconds
Started May 26 02:27:53 PM PDT 24
Finished May 26 02:32:26 PM PDT 24
Peak memory 190896 kb
Host smart-a693ca36-881d-43bc-8ba9-57d33d207d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563214149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.563214149
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3723766933
Short name T391
Test name
Test status
Simulation time 19037307209 ps
CPU time 14.26 seconds
Started May 26 02:27:52 PM PDT 24
Finished May 26 02:28:07 PM PDT 24
Peak memory 193844 kb
Host smart-2ef5ce69-acdb-4a66-bbe9-9545faf8e5e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723766933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3723766933
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.533013177
Short name T161
Test name
Test status
Simulation time 2118732561088 ps
CPU time 1169.75 seconds
Started May 26 02:27:54 PM PDT 24
Finished May 26 02:47:25 PM PDT 24
Peak memory 182636 kb
Host smart-639c114d-4282-4dcd-977e-71d116a1cf53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533013177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.533013177
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1257144069
Short name T440
Test name
Test status
Simulation time 98342670732 ps
CPU time 106.54 seconds
Started May 26 02:27:52 PM PDT 24
Finished May 26 02:29:39 PM PDT 24
Peak memory 182716 kb
Host smart-7ab96a1c-03d6-4838-b99e-2534dfa63198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257144069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1257144069
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3304529593
Short name T419
Test name
Test status
Simulation time 167564106060 ps
CPU time 92.54 seconds
Started May 26 02:27:52 PM PDT 24
Finished May 26 02:29:25 PM PDT 24
Peak memory 190844 kb
Host smart-751c11c0-b6ec-4ef6-9e95-aa469104a478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304529593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3304529593
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3336642266
Short name T421
Test name
Test status
Simulation time 115358454 ps
CPU time 0.63 seconds
Started May 26 02:27:52 PM PDT 24
Finished May 26 02:27:53 PM PDT 24
Peak memory 182464 kb
Host smart-b5677d99-772f-42e7-865d-fa99d4cab76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336642266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3336642266
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.4196444432
Short name T106
Test name
Test status
Simulation time 673626994534 ps
CPU time 625.65 seconds
Started May 26 02:28:01 PM PDT 24
Finished May 26 02:38:28 PM PDT 24
Peak memory 195376 kb
Host smart-4e190dd2-21d1-4373-bd0f-825b1c5fbe58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196444432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.4196444432
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2605046884
Short name T36
Test name
Test status
Simulation time 45360073052 ps
CPU time 164.36 seconds
Started May 26 02:27:54 PM PDT 24
Finished May 26 02:30:40 PM PDT 24
Peak memory 197172 kb
Host smart-954144c0-b04c-46cd-8dbf-588be8c5c71f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605046884 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2605046884
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_random.2966121824
Short name T278
Test name
Test status
Simulation time 495780069670 ps
CPU time 215.13 seconds
Started May 26 02:27:59 PM PDT 24
Finished May 26 02:31:35 PM PDT 24
Peak memory 190896 kb
Host smart-98ea49a6-4cb0-4534-b9c7-03b74ac777ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966121824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2966121824
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1701934577
Short name T407
Test name
Test status
Simulation time 1169311481 ps
CPU time 10.98 seconds
Started May 26 02:28:02 PM PDT 24
Finished May 26 02:28:14 PM PDT 24
Peak memory 182584 kb
Host smart-120c5e75-58b8-4b2c-98d3-739371a33756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701934577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1701934577
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3858124121
Short name T385
Test name
Test status
Simulation time 37933907 ps
CPU time 0.61 seconds
Started May 26 02:28:01 PM PDT 24
Finished May 26 02:28:02 PM PDT 24
Peak memory 182412 kb
Host smart-8e503056-cd1a-4337-b1cd-848143533e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858124121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3858124121
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1891627348
Short name T34
Test name
Test status
Simulation time 422329108547 ps
CPU time 840.79 seconds
Started May 26 02:28:00 PM PDT 24
Finished May 26 02:42:01 PM PDT 24
Peak memory 205564 kb
Host smart-32567408-771b-421d-918d-1b2c6746ab21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891627348 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1891627348
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.272869305
Short name T299
Test name
Test status
Simulation time 255816381494 ps
CPU time 418.04 seconds
Started May 26 02:28:01 PM PDT 24
Finished May 26 02:35:00 PM PDT 24
Peak memory 182688 kb
Host smart-17420543-ce25-45ab-84bc-6fd72ca3d1f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272869305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.272869305
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.545056260
Short name T447
Test name
Test status
Simulation time 138127485535 ps
CPU time 197.38 seconds
Started May 26 02:27:59 PM PDT 24
Finished May 26 02:31:17 PM PDT 24
Peak memory 182720 kb
Host smart-16c0c53d-694a-4da0-8f3f-0e6be0a046d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545056260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.545056260
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1169704767
Short name T227
Test name
Test status
Simulation time 128970160856 ps
CPU time 130.99 seconds
Started May 26 02:28:00 PM PDT 24
Finished May 26 02:30:12 PM PDT 24
Peak memory 190896 kb
Host smart-c4233289-e4ff-43a0-a3bc-212350e14751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169704767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1169704767
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1477064138
Short name T233
Test name
Test status
Simulation time 21258798157 ps
CPU time 32.1 seconds
Started May 26 02:28:02 PM PDT 24
Finished May 26 02:28:35 PM PDT 24
Peak memory 190828 kb
Host smart-9d883863-4191-4525-90cb-f3f54f9852b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477064138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1477064138
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.4257070653
Short name T441
Test name
Test status
Simulation time 105876621324 ps
CPU time 164.56 seconds
Started May 26 02:28:02 PM PDT 24
Finished May 26 02:30:47 PM PDT 24
Peak memory 182640 kb
Host smart-566b04e0-4595-4603-91ce-ca65ea523833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257070653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.4257070653
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3434278814
Short name T188
Test name
Test status
Simulation time 57162894689 ps
CPU time 102.21 seconds
Started May 26 02:28:02 PM PDT 24
Finished May 26 02:29:45 PM PDT 24
Peak memory 190900 kb
Host smart-cf5a8a15-8fcb-45f4-98cd-e3766b5e930f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434278814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3434278814
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1295286890
Short name T305
Test name
Test status
Simulation time 6274503581 ps
CPU time 10.56 seconds
Started May 26 02:28:02 PM PDT 24
Finished May 26 02:28:14 PM PDT 24
Peak memory 182572 kb
Host smart-861b04de-45cd-4b9c-89cf-d33c029d9bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295286890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1295286890
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.1839238543
Short name T47
Test name
Test status
Simulation time 45648830315 ps
CPU time 146.51 seconds
Started May 26 02:28:00 PM PDT 24
Finished May 26 02:30:28 PM PDT 24
Peak memory 197316 kb
Host smart-de0221fa-361f-45d4-9f0c-cf1718350dfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839238543 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.1839238543
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3278587457
Short name T392
Test name
Test status
Simulation time 35580171466 ps
CPU time 28.65 seconds
Started May 26 02:28:06 PM PDT 24
Finished May 26 02:28:35 PM PDT 24
Peak memory 182720 kb
Host smart-31d45c20-d13c-4670-8db7-4e572d3126e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278587457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3278587457
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.321317973
Short name T240
Test name
Test status
Simulation time 352988739740 ps
CPU time 207.06 seconds
Started May 26 02:27:58 PM PDT 24
Finished May 26 02:31:26 PM PDT 24
Peak memory 190896 kb
Host smart-d32e93cf-1f10-4aba-8f20-2dac26677147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321317973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.321317973
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1624338442
Short name T384
Test name
Test status
Simulation time 4611614428 ps
CPU time 8.82 seconds
Started May 26 02:28:06 PM PDT 24
Finished May 26 02:28:15 PM PDT 24
Peak memory 182720 kb
Host smart-80bb1b55-a205-443a-9de4-d148bf47c303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624338442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1624338442
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2858174537
Short name T133
Test name
Test status
Simulation time 1335366515431 ps
CPU time 722.94 seconds
Started May 26 02:28:08 PM PDT 24
Finished May 26 02:40:12 PM PDT 24
Peak memory 182720 kb
Host smart-c5cee516-5697-4cd1-9be3-4ebb83fa04a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858174537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2858174537
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3679906069
Short name T3
Test name
Test status
Simulation time 193394248522 ps
CPU time 145.91 seconds
Started May 26 02:28:06 PM PDT 24
Finished May 26 02:30:33 PM PDT 24
Peak memory 182668 kb
Host smart-e8e863a2-17e5-4fe0-a9af-02e2c37838e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679906069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3679906069
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.708369935
Short name T282
Test name
Test status
Simulation time 193292468354 ps
CPU time 166.98 seconds
Started May 26 02:28:07 PM PDT 24
Finished May 26 02:30:55 PM PDT 24
Peak memory 190876 kb
Host smart-879d1267-0fb1-4ab1-af5d-c8b820b2cfda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708369935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.708369935
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2009236421
Short name T107
Test name
Test status
Simulation time 124665763016 ps
CPU time 126.23 seconds
Started May 26 02:28:08 PM PDT 24
Finished May 26 02:30:15 PM PDT 24
Peak memory 182724 kb
Host smart-f30b3f0c-6f76-41d6-a946-282c3e929d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009236421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2009236421
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3236549185
Short name T352
Test name
Test status
Simulation time 15064878110 ps
CPU time 16.04 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:27:16 PM PDT 24
Peak memory 182668 kb
Host smart-037568c4-483a-4b47-9ba3-f53904013908
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236549185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3236549185
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3338343662
Short name T26
Test name
Test status
Simulation time 846131876036 ps
CPU time 287.13 seconds
Started May 26 02:26:56 PM PDT 24
Finished May 26 02:31:44 PM PDT 24
Peak memory 182704 kb
Host smart-9c2e4999-657b-4643-81e3-c8cee50d7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338343662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3338343662
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2541072114
Short name T140
Test name
Test status
Simulation time 154677357496 ps
CPU time 152.65 seconds
Started May 26 02:27:00 PM PDT 24
Finished May 26 02:29:34 PM PDT 24
Peak memory 190908 kb
Host smart-440ecc73-9e7c-4aeb-8251-9c4c3cda3a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541072114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2541072114
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1245744915
Short name T379
Test name
Test status
Simulation time 57549300 ps
CPU time 0.65 seconds
Started May 26 02:26:58 PM PDT 24
Finished May 26 02:27:00 PM PDT 24
Peak memory 182384 kb
Host smart-b236cf84-556a-469b-acb9-da188fc4ddda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245744915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1245744915
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2233418790
Short name T422
Test name
Test status
Simulation time 15440855203 ps
CPU time 27.39 seconds
Started May 26 02:28:17 PM PDT 24
Finished May 26 02:28:45 PM PDT 24
Peak memory 182692 kb
Host smart-14a9dbf7-66c9-4822-b049-09393cdf782d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233418790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2233418790
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.436698573
Short name T220
Test name
Test status
Simulation time 400215569426 ps
CPU time 436.13 seconds
Started May 26 02:28:17 PM PDT 24
Finished May 26 02:35:34 PM PDT 24
Peak memory 190856 kb
Host smart-381069ca-0543-4197-90a0-aa2522411bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436698573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.436698573
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2635096677
Short name T264
Test name
Test status
Simulation time 34184920915 ps
CPU time 24.66 seconds
Started May 26 02:28:16 PM PDT 24
Finished May 26 02:28:41 PM PDT 24
Peak memory 182516 kb
Host smart-1d3abb44-da30-4276-95b9-1688eb420655
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635096677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2635096677
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2970181952
Short name T115
Test name
Test status
Simulation time 78738276089 ps
CPU time 848.41 seconds
Started May 26 02:28:15 PM PDT 24
Finished May 26 02:42:23 PM PDT 24
Peak memory 190900 kb
Host smart-acc44b9c-2e55-4a98-849b-ff2245bfbc52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970181952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2970181952
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4089937210
Short name T221
Test name
Test status
Simulation time 226574520156 ps
CPU time 225.8 seconds
Started May 26 02:28:15 PM PDT 24
Finished May 26 02:32:02 PM PDT 24
Peak memory 190872 kb
Host smart-4a767b30-6899-44e4-afe3-c5e87d821e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089937210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4089937210
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3196989966
Short name T424
Test name
Test status
Simulation time 38583273788 ps
CPU time 63.32 seconds
Started May 26 02:28:17 PM PDT 24
Finished May 26 02:29:21 PM PDT 24
Peak memory 190932 kb
Host smart-8446fd2d-57ca-4a08-80a6-bc4d4cee3a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196989966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3196989966
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2482971713
Short name T145
Test name
Test status
Simulation time 356933613875 ps
CPU time 294.09 seconds
Started May 26 02:28:16 PM PDT 24
Finished May 26 02:33:10 PM PDT 24
Peak memory 190872 kb
Host smart-cf9737cb-67c4-434c-b166-192d23317921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482971713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2482971713
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1761471514
Short name T125
Test name
Test status
Simulation time 174125309024 ps
CPU time 100.7 seconds
Started May 26 02:28:23 PM PDT 24
Finished May 26 02:30:04 PM PDT 24
Peak memory 190908 kb
Host smart-a0568315-dee8-49cc-9c71-6751a8d4c820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761471514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1761471514
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4195643659
Short name T116
Test name
Test status
Simulation time 529545188762 ps
CPU time 300.38 seconds
Started May 26 02:28:23 PM PDT 24
Finished May 26 02:33:24 PM PDT 24
Peak memory 190892 kb
Host smart-bea34010-41c3-4235-b3cd-a0f8df056952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195643659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4195643659
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2478237837
Short name T389
Test name
Test status
Simulation time 96632825505 ps
CPU time 39.3 seconds
Started May 26 02:26:59 PM PDT 24
Finished May 26 02:27:40 PM PDT 24
Peak memory 182716 kb
Host smart-3c8a2c79-1991-4b1a-ae3e-1e01cc31680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478237837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2478237837
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3959851440
Short name T413
Test name
Test status
Simulation time 235156157056 ps
CPU time 108.44 seconds
Started May 26 02:26:58 PM PDT 24
Finished May 26 02:28:48 PM PDT 24
Peak memory 190904 kb
Host smart-94400db2-a8a9-4ab0-a397-ef002dec6484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959851440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3959851440
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2240407917
Short name T202
Test name
Test status
Simulation time 237557046807 ps
CPU time 97.92 seconds
Started May 26 02:27:00 PM PDT 24
Finished May 26 02:28:39 PM PDT 24
Peak memory 190796 kb
Host smart-489ee316-7db2-439f-a7b9-52b2cb3dd5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240407917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2240407917
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.975182293
Short name T318
Test name
Test status
Simulation time 1178617508346 ps
CPU time 458.39 seconds
Started May 26 02:27:01 PM PDT 24
Finished May 26 02:34:41 PM PDT 24
Peak memory 190928 kb
Host smart-58280d93-6a70-49d7-a30f-b8393b13f5b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975182293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.975182293
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3027155560
Short name T172
Test name
Test status
Simulation time 605451616160 ps
CPU time 657.74 seconds
Started May 26 02:28:23 PM PDT 24
Finished May 26 02:39:22 PM PDT 24
Peak memory 190900 kb
Host smart-6804e76b-c128-4404-925a-0bf1ba5ae8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027155560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3027155560
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.749152831
Short name T175
Test name
Test status
Simulation time 602309761237 ps
CPU time 286.98 seconds
Started May 26 02:28:23 PM PDT 24
Finished May 26 02:33:11 PM PDT 24
Peak memory 190900 kb
Host smart-a60feb9f-9007-4e35-9084-86075b1288a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749152831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.749152831
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4282044028
Short name T105
Test name
Test status
Simulation time 203423922384 ps
CPU time 85.89 seconds
Started May 26 02:28:24 PM PDT 24
Finished May 26 02:29:50 PM PDT 24
Peak memory 182708 kb
Host smart-a804595f-0ef6-4317-b0b3-8163e10f3c1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282044028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4282044028
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.660935049
Short name T190
Test name
Test status
Simulation time 173202083325 ps
CPU time 312.67 seconds
Started May 26 02:28:22 PM PDT 24
Finished May 26 02:33:35 PM PDT 24
Peak memory 190772 kb
Host smart-871c97cf-9b3c-4206-bdd8-ca7948e0b670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660935049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.660935049
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2988782037
Short name T281
Test name
Test status
Simulation time 1509564397545 ps
CPU time 474.26 seconds
Started May 26 02:28:23 PM PDT 24
Finished May 26 02:36:18 PM PDT 24
Peak memory 190908 kb
Host smart-c96a3478-9b6c-4c9a-b545-d81e4a8bedb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988782037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2988782037
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1979969974
Short name T126
Test name
Test status
Simulation time 507213395375 ps
CPU time 579.24 seconds
Started May 26 02:28:23 PM PDT 24
Finished May 26 02:38:03 PM PDT 24
Peak memory 191100 kb
Host smart-758cf3af-85c4-454c-85a2-883c7feea7aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979969974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1979969974
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.341482509
Short name T261
Test name
Test status
Simulation time 218359883236 ps
CPU time 908.22 seconds
Started May 26 02:28:25 PM PDT 24
Finished May 26 02:43:33 PM PDT 24
Peak memory 190856 kb
Host smart-d4d17142-5a4a-4985-a1ba-8e6088198b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341482509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.341482509
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2212678868
Short name T346
Test name
Test status
Simulation time 385404504528 ps
CPU time 171.37 seconds
Started May 26 02:28:23 PM PDT 24
Finished May 26 02:31:15 PM PDT 24
Peak memory 190888 kb
Host smart-af873e19-b8a0-4ee4-a0bf-0081aa22ce62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212678868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2212678868
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3570554047
Short name T349
Test name
Test status
Simulation time 149619024712 ps
CPU time 224.21 seconds
Started May 26 02:28:31 PM PDT 24
Finished May 26 02:32:16 PM PDT 24
Peak memory 191924 kb
Host smart-18c9ace5-fa83-46f1-9745-f285a469b81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570554047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3570554047
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1662013545
Short name T358
Test name
Test status
Simulation time 179191074969 ps
CPU time 315.28 seconds
Started May 26 02:27:03 PM PDT 24
Finished May 26 02:32:19 PM PDT 24
Peak memory 182688 kb
Host smart-e99edd4e-22e4-4225-86d6-312023461042
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662013545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1662013545
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1447008570
Short name T425
Test name
Test status
Simulation time 141426598936 ps
CPU time 208.27 seconds
Started May 26 02:27:03 PM PDT 24
Finished May 26 02:30:32 PM PDT 24
Peak memory 182700 kb
Host smart-65d62484-db2d-46b6-aabd-ef26f9285aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447008570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1447008570
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3247892638
Short name T205
Test name
Test status
Simulation time 314149904300 ps
CPU time 2690.22 seconds
Started May 26 02:27:00 PM PDT 24
Finished May 26 03:11:52 PM PDT 24
Peak memory 194344 kb
Host smart-0eec7551-1724-45e9-a736-bdc249b49d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247892638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3247892638
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.386420371
Short name T5
Test name
Test status
Simulation time 16859318009 ps
CPU time 34.76 seconds
Started May 26 02:27:01 PM PDT 24
Finished May 26 02:27:37 PM PDT 24
Peak memory 182672 kb
Host smart-68024317-7e47-490d-b767-80b54a36a669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386420371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.386420371
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.505182924
Short name T249
Test name
Test status
Simulation time 2129894935343 ps
CPU time 422.43 seconds
Started May 26 02:27:04 PM PDT 24
Finished May 26 02:34:07 PM PDT 24
Peak memory 190908 kb
Host smart-18c351e8-989e-47bd-a64c-01bef5f46524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505182924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.505182924
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.69872502
Short name T191
Test name
Test status
Simulation time 147566164641 ps
CPU time 330.85 seconds
Started May 26 02:28:33 PM PDT 24
Finished May 26 02:34:04 PM PDT 24
Peak memory 194436 kb
Host smart-f9572744-c1de-41c1-83ab-b0afc147723d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69872502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.69872502
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.522968753
Short name T56
Test name
Test status
Simulation time 402334953128 ps
CPU time 336.84 seconds
Started May 26 02:28:29 PM PDT 24
Finished May 26 02:34:06 PM PDT 24
Peak memory 190892 kb
Host smart-6c4b2d48-0960-4e21-8425-b9899b834fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522968753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.522968753
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.673328298
Short name T317
Test name
Test status
Simulation time 151827806398 ps
CPU time 136.24 seconds
Started May 26 02:28:31 PM PDT 24
Finished May 26 02:30:48 PM PDT 24
Peak memory 190856 kb
Host smart-99ff6751-b4e5-421e-8a3e-c5c81aa45975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673328298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.673328298
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1146787879
Short name T316
Test name
Test status
Simulation time 77363909219 ps
CPU time 1281.49 seconds
Started May 26 02:28:32 PM PDT 24
Finished May 26 02:49:54 PM PDT 24
Peak memory 190908 kb
Host smart-898dbad4-169c-4b3a-b6cc-cade3bc3898e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146787879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1146787879
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2449606782
Short name T22
Test name
Test status
Simulation time 43593110356 ps
CPU time 70.18 seconds
Started May 26 02:28:32 PM PDT 24
Finished May 26 02:29:43 PM PDT 24
Peak memory 182704 kb
Host smart-458e144f-f2db-4d74-9c95-2e08c72db030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449606782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2449606782
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3717696618
Short name T353
Test name
Test status
Simulation time 165240817484 ps
CPU time 167.97 seconds
Started May 26 02:28:33 PM PDT 24
Finished May 26 02:31:21 PM PDT 24
Peak memory 190904 kb
Host smart-c25af75a-3627-435c-b5c7-0c266cad4a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717696618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3717696618
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1068815978
Short name T53
Test name
Test status
Simulation time 13676080954 ps
CPU time 12.4 seconds
Started May 26 02:27:05 PM PDT 24
Finished May 26 02:27:19 PM PDT 24
Peak memory 182684 kb
Host smart-45a78357-f9a3-4212-848d-4714472f67f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068815978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1068815978
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.740288604
Short name T402
Test name
Test status
Simulation time 200146518131 ps
CPU time 161.6 seconds
Started May 26 02:27:04 PM PDT 24
Finished May 26 02:29:47 PM PDT 24
Peak memory 182752 kb
Host smart-0ab3cea3-6d0f-4b98-bc5e-3e8a8fd46ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740288604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.740288604
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1868835441
Short name T354
Test name
Test status
Simulation time 102137477653 ps
CPU time 176.08 seconds
Started May 26 02:27:06 PM PDT 24
Finished May 26 02:30:04 PM PDT 24
Peak memory 190920 kb
Host smart-c64f9e15-591f-45c1-9b33-2c5101fd4904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868835441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1868835441
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3689601384
Short name T443
Test name
Test status
Simulation time 870598498 ps
CPU time 3.28 seconds
Started May 26 02:27:05 PM PDT 24
Finished May 26 02:27:09 PM PDT 24
Peak memory 182656 kb
Host smart-d77ffd42-abbc-4409-933c-ad9cc8fc9328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689601384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3689601384
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/82.rv_timer_random.3987640069
Short name T77
Test name
Test status
Simulation time 581087113476 ps
CPU time 1435.75 seconds
Started May 26 02:28:40 PM PDT 24
Finished May 26 02:52:36 PM PDT 24
Peak memory 182700 kb
Host smart-12943cac-d34b-47ec-b937-600c334dca30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987640069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3987640069
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3598354876
Short name T437
Test name
Test status
Simulation time 113821259466 ps
CPU time 221.99 seconds
Started May 26 02:28:38 PM PDT 24
Finished May 26 02:32:21 PM PDT 24
Peak memory 182636 kb
Host smart-3e2ff8a0-bfe9-4af2-a4b5-ee0e15b3ec60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598354876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3598354876
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3513245354
Short name T214
Test name
Test status
Simulation time 93748419548 ps
CPU time 368.08 seconds
Started May 26 02:28:39 PM PDT 24
Finished May 26 02:34:48 PM PDT 24
Peak memory 190900 kb
Host smart-2b108f9d-28ed-4db7-8746-5d91995ed48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513245354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3513245354
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3800152369
Short name T80
Test name
Test status
Simulation time 223286128670 ps
CPU time 525.53 seconds
Started May 26 02:28:36 PM PDT 24
Finished May 26 02:37:22 PM PDT 24
Peak memory 190900 kb
Host smart-e005f446-e2ab-45a5-9f1e-af953b2bc7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800152369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3800152369
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3853918891
Short name T274
Test name
Test status
Simulation time 555243245861 ps
CPU time 595.22 seconds
Started May 26 02:28:37 PM PDT 24
Finished May 26 02:38:33 PM PDT 24
Peak memory 190900 kb
Host smart-9c45d18f-9d51-49c9-b5d0-8fefeb9d6335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853918891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3853918891
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.307215926
Short name T273
Test name
Test status
Simulation time 55630363060 ps
CPU time 1421.71 seconds
Started May 26 02:28:36 PM PDT 24
Finished May 26 02:52:18 PM PDT 24
Peak memory 190888 kb
Host smart-fd186019-13d7-47b9-a4f2-44c4b61fdf83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307215926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.307215926
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.254944691
Short name T292
Test name
Test status
Simulation time 14094584162 ps
CPU time 10.79 seconds
Started May 26 02:28:37 PM PDT 24
Finished May 26 02:28:49 PM PDT 24
Peak memory 182696 kb
Host smart-5483dafe-1296-4491-8f50-023fa4e8ff00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254944691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.254944691
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.566283102
Short name T127
Test name
Test status
Simulation time 275661750766 ps
CPU time 428.34 seconds
Started May 26 02:27:06 PM PDT 24
Finished May 26 02:34:16 PM PDT 24
Peak memory 182704 kb
Host smart-112a1962-a7d5-486b-852c-6f6e9a87e508
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566283102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.566283102
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1686940810
Short name T442
Test name
Test status
Simulation time 344796844307 ps
CPU time 137.19 seconds
Started May 26 02:27:17 PM PDT 24
Finished May 26 02:29:35 PM PDT 24
Peak memory 182720 kb
Host smart-090d0ba8-95c4-46d8-b2b5-14e6fe2b028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686940810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1686940810
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3541181213
Short name T139
Test name
Test status
Simulation time 398223586982 ps
CPU time 145.39 seconds
Started May 26 02:27:07 PM PDT 24
Finished May 26 02:29:33 PM PDT 24
Peak memory 194152 kb
Host smart-3a11051e-2325-4915-abec-9a0da20f56be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541181213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3541181213
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.234399628
Short name T351
Test name
Test status
Simulation time 39480256005 ps
CPU time 63.91 seconds
Started May 26 02:27:05 PM PDT 24
Finished May 26 02:28:11 PM PDT 24
Peak memory 182748 kb
Host smart-e410fe55-db49-42fd-bf3e-cef7bd2df4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234399628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.234399628
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3320384396
Short name T398
Test name
Test status
Simulation time 658387033161 ps
CPU time 81.52 seconds
Started May 26 02:27:06 PM PDT 24
Finished May 26 02:28:28 PM PDT 24
Peak memory 182628 kb
Host smart-da18e3b6-a58c-44b7-a5a9-333cf583e624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320384396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3320384396
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1038939536
Short name T203
Test name
Test status
Simulation time 561386316485 ps
CPU time 706.78 seconds
Started May 26 02:28:45 PM PDT 24
Finished May 26 02:40:32 PM PDT 24
Peak memory 190900 kb
Host smart-11b8ffe5-b79c-4ffe-ae4d-533fbff6269b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038939536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1038939536
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2277372201
Short name T266
Test name
Test status
Simulation time 58717559205 ps
CPU time 99.15 seconds
Started May 26 02:28:45 PM PDT 24
Finished May 26 02:30:25 PM PDT 24
Peak memory 190872 kb
Host smart-61003aa1-29a9-44a3-99d9-a9f5eac6de38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277372201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2277372201
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3736846122
Short name T134
Test name
Test status
Simulation time 77567565384 ps
CPU time 136.83 seconds
Started May 26 02:28:45 PM PDT 24
Finished May 26 02:31:03 PM PDT 24
Peak memory 182708 kb
Host smart-e0e75bac-d1b8-4d51-acfd-5c1ca4cd0c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736846122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3736846122
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.103083373
Short name T327
Test name
Test status
Simulation time 210439718 ps
CPU time 0.89 seconds
Started May 26 02:28:45 PM PDT 24
Finished May 26 02:28:47 PM PDT 24
Peak memory 182488 kb
Host smart-08a9bb20-da9c-44bf-97aa-529adce0a608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103083373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.103083373
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.740262416
Short name T270
Test name
Test status
Simulation time 216636123685 ps
CPU time 150.56 seconds
Started May 26 02:28:47 PM PDT 24
Finished May 26 02:31:18 PM PDT 24
Peak memory 190856 kb
Host smart-37b9282f-0328-4d39-b163-757e459a6554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740262416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.740262416
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.335827297
Short name T372
Test name
Test status
Simulation time 185373352272 ps
CPU time 86.56 seconds
Started May 26 02:28:45 PM PDT 24
Finished May 26 02:30:12 PM PDT 24
Peak memory 182680 kb
Host smart-22e7e075-e4e1-4dd7-ac66-705adbb49cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335827297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.335827297
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1154662949
Short name T432
Test name
Test status
Simulation time 83626490074 ps
CPU time 75.07 seconds
Started May 26 02:28:44 PM PDT 24
Finished May 26 02:29:59 PM PDT 24
Peak memory 182672 kb
Host smart-b64db115-c448-49e9-a77f-15f82d009d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154662949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1154662949
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.919302770
Short name T43
Test name
Test status
Simulation time 25923449808 ps
CPU time 152.03 seconds
Started May 26 02:28:44 PM PDT 24
Finished May 26 02:31:17 PM PDT 24
Peak memory 190904 kb
Host smart-3ccfc7c4-27bd-4922-92af-95d3191408e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919302770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.919302770
Directory /workspace/99.rv_timer_random/latest
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