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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 577
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.589971608 May 28 01:10:05 PM PDT 24 May 28 01:10:08 PM PDT 24 161857390 ps
T507 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1328408736 May 28 01:09:34 PM PDT 24 May 28 01:09:38 PM PDT 24 91436566 ps
T508 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4207822008 May 28 01:09:48 PM PDT 24 May 28 01:09:53 PM PDT 24 29623438 ps
T509 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1440105526 May 28 01:10:18 PM PDT 24 May 28 01:10:24 PM PDT 24 15694236 ps
T510 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2754708520 May 28 01:10:14 PM PDT 24 May 28 01:10:23 PM PDT 24 38957237 ps
T511 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.598681357 May 28 01:10:09 PM PDT 24 May 28 01:10:15 PM PDT 24 14220581 ps
T512 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3750724098 May 28 01:10:05 PM PDT 24 May 28 01:10:09 PM PDT 24 121281802 ps
T513 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.403891337 May 28 01:10:05 PM PDT 24 May 28 01:10:07 PM PDT 24 21605513 ps
T514 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3649143544 May 28 01:09:43 PM PDT 24 May 28 01:09:48 PM PDT 24 103081389 ps
T515 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1258826658 May 28 01:10:05 PM PDT 24 May 28 01:10:08 PM PDT 24 90062428 ps
T516 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3464226832 May 28 01:10:06 PM PDT 24 May 28 01:10:08 PM PDT 24 95390016 ps
T73 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.977261361 May 28 01:09:40 PM PDT 24 May 28 01:09:43 PM PDT 24 28965700 ps
T517 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3256943408 May 28 01:10:09 PM PDT 24 May 28 01:10:17 PM PDT 24 889210386 ps
T518 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.188155909 May 28 01:09:47 PM PDT 24 May 28 01:09:52 PM PDT 24 18486207 ps
T519 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1351521541 May 28 01:10:01 PM PDT 24 May 28 01:10:03 PM PDT 24 84559465 ps
T520 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2805403854 May 28 01:10:11 PM PDT 24 May 28 01:10:20 PM PDT 24 18903290 ps
T521 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.970143295 May 28 01:09:43 PM PDT 24 May 28 01:09:47 PM PDT 24 364426415 ps
T75 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2467444490 May 28 01:09:50 PM PDT 24 May 28 01:09:59 PM PDT 24 2382985647 ps
T522 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2691812305 May 28 01:09:45 PM PDT 24 May 28 01:09:49 PM PDT 24 88524431 ps
T523 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1282318397 May 28 01:10:17 PM PDT 24 May 28 01:10:25 PM PDT 24 157654756 ps
T524 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3489589870 May 28 01:09:45 PM PDT 24 May 28 01:09:50 PM PDT 24 19918629 ps
T525 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3518129397 May 28 01:10:06 PM PDT 24 May 28 01:10:09 PM PDT 24 57052616 ps
T526 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1410126589 May 28 01:10:07 PM PDT 24 May 28 01:10:10 PM PDT 24 41358600 ps
T527 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1762368206 May 28 01:09:52 PM PDT 24 May 28 01:09:58 PM PDT 24 29621777 ps
T528 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3154741429 May 28 01:10:06 PM PDT 24 May 28 01:10:09 PM PDT 24 13350649 ps
T529 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3275354674 May 28 01:10:14 PM PDT 24 May 28 01:10:22 PM PDT 24 44017297 ps
T530 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.395802876 May 28 01:09:55 PM PDT 24 May 28 01:09:59 PM PDT 24 16782958 ps
T531 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2829274180 May 28 01:10:06 PM PDT 24 May 28 01:10:08 PM PDT 24 14870303 ps
T532 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2289033576 May 28 01:10:11 PM PDT 24 May 28 01:10:19 PM PDT 24 14983735 ps
T533 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.968892211 May 28 01:10:09 PM PDT 24 May 28 01:10:15 PM PDT 24 14567363 ps
T534 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.285729812 May 28 01:10:09 PM PDT 24 May 28 01:10:15 PM PDT 24 16692663 ps
T535 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3495898612 May 28 01:09:58 PM PDT 24 May 28 01:10:01 PM PDT 24 151043944 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.607794858 May 28 01:09:56 PM PDT 24 May 28 01:10:00 PM PDT 24 75403190 ps
T85 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1264823565 May 28 01:10:11 PM PDT 24 May 28 01:10:19 PM PDT 24 238225040 ps
T537 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.576083457 May 28 01:10:02 PM PDT 24 May 28 01:10:03 PM PDT 24 37917228 ps
T538 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2025773668 May 28 01:10:03 PM PDT 24 May 28 01:10:05 PM PDT 24 24116369 ps
T539 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.4197464951 May 28 01:09:48 PM PDT 24 May 28 01:09:53 PM PDT 24 58754029 ps
T540 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4161941944 May 28 01:10:07 PM PDT 24 May 28 01:10:10 PM PDT 24 14558341 ps
T541 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3421018377 May 28 01:10:08 PM PDT 24 May 28 01:10:14 PM PDT 24 330731570 ps
T542 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.872522797 May 28 01:10:05 PM PDT 24 May 28 01:10:07 PM PDT 24 12938350 ps
T543 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.917771046 May 28 01:10:17 PM PDT 24 May 28 01:10:24 PM PDT 24 28216570 ps
T544 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2203065643 May 28 01:10:07 PM PDT 24 May 28 01:10:12 PM PDT 24 29893952 ps
T545 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3431518049 May 28 01:09:44 PM PDT 24 May 28 01:09:48 PM PDT 24 218453906 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3140436936 May 28 01:10:00 PM PDT 24 May 28 01:10:03 PM PDT 24 129429749 ps
T547 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.51904360 May 28 01:09:42 PM PDT 24 May 28 01:09:45 PM PDT 24 117598701 ps
T548 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.277484827 May 28 01:10:09 PM PDT 24 May 28 01:10:15 PM PDT 24 104937092 ps
T549 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2970492644 May 28 01:10:09 PM PDT 24 May 28 01:10:16 PM PDT 24 29916538 ps
T550 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2893611237 May 28 01:10:10 PM PDT 24 May 28 01:10:17 PM PDT 24 43088109 ps
T551 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1761581356 May 28 01:10:04 PM PDT 24 May 28 01:10:06 PM PDT 24 160010648 ps
T552 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2990774399 May 28 01:10:09 PM PDT 24 May 28 01:10:15 PM PDT 24 23562251 ps
T553 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.607050877 May 28 01:09:40 PM PDT 24 May 28 01:09:44 PM PDT 24 72802750 ps
T554 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3347388652 May 28 01:09:48 PM PDT 24 May 28 01:09:53 PM PDT 24 24284825 ps
T555 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.789879968 May 28 01:10:09 PM PDT 24 May 28 01:10:15 PM PDT 24 67081577 ps
T556 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.585133122 May 28 01:10:14 PM PDT 24 May 28 01:10:22 PM PDT 24 18857552 ps
T557 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.93492069 May 28 01:09:48 PM PDT 24 May 28 01:09:54 PM PDT 24 122951311 ps
T558 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2945737062 May 28 01:09:44 PM PDT 24 May 28 01:09:48 PM PDT 24 28443776 ps
T559 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.324821810 May 28 01:09:40 PM PDT 24 May 28 01:09:42 PM PDT 24 18206127 ps
T86 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1014252920 May 28 01:09:52 PM PDT 24 May 28 01:09:59 PM PDT 24 366317793 ps
T560 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2796624102 May 28 01:09:43 PM PDT 24 May 28 01:09:47 PM PDT 24 25604003 ps
T561 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.954443256 May 28 01:09:37 PM PDT 24 May 28 01:09:41 PM PDT 24 16184275 ps
T562 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2889279860 May 28 01:09:41 PM PDT 24 May 28 01:09:44 PM PDT 24 96404994 ps
T563 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1843533479 May 28 01:10:05 PM PDT 24 May 28 01:10:07 PM PDT 24 62511224 ps
T564 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3979663709 May 28 01:09:55 PM PDT 24 May 28 01:09:59 PM PDT 24 62846295 ps
T565 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3702034904 May 28 01:10:06 PM PDT 24 May 28 01:10:09 PM PDT 24 101378871 ps
T89 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.731100727 May 28 01:10:04 PM PDT 24 May 28 01:10:05 PM PDT 24 116210366 ps
T566 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2921361134 May 28 01:10:08 PM PDT 24 May 28 01:10:13 PM PDT 24 518407741 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.268206146 May 28 01:10:08 PM PDT 24 May 28 01:10:16 PM PDT 24 221331651 ps
T568 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3010044263 May 28 01:09:48 PM PDT 24 May 28 01:09:53 PM PDT 24 55111313 ps
T569 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4275595691 May 28 01:09:36 PM PDT 24 May 28 01:09:40 PM PDT 24 22718311 ps
T570 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.260552670 May 28 01:10:08 PM PDT 24 May 28 01:10:14 PM PDT 24 45708846 ps
T571 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2076356860 May 28 01:10:05 PM PDT 24 May 28 01:10:09 PM PDT 24 154278372 ps
T572 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2608851788 May 28 01:09:44 PM PDT 24 May 28 01:09:48 PM PDT 24 40900296 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.721291806 May 28 01:09:43 PM PDT 24 May 28 01:09:46 PM PDT 24 14834329 ps
T574 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3268197351 May 28 01:09:51 PM PDT 24 May 28 01:09:56 PM PDT 24 24198302 ps
T575 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4260919291 May 28 01:10:13 PM PDT 24 May 28 01:10:21 PM PDT 24 14968062 ps
T576 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3029317278 May 28 01:09:43 PM PDT 24 May 28 01:09:48 PM PDT 24 557792687 ps
T577 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2146757036 May 28 01:10:07 PM PDT 24 May 28 01:10:11 PM PDT 24 13915173 ps

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.3321864725
Short name T6
Test name
Test status
Simulation time 751816504325 ps
CPU time 739.79 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:25:04 PM PDT 24
Peak memory 208000 kb
Host smart-02a9f3d4-fd1f-468e-b160-144952b8ca22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321864725 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.3321864725
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1926449979
Short name T10
Test name
Test status
Simulation time 375570715600 ps
CPU time 940.06 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:28:24 PM PDT 24
Peak memory 195304 kb
Host smart-b7089a88-1b33-4498-8c61-9dbbaead5938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926449979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1926449979
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2893639774
Short name T94
Test name
Test status
Simulation time 695003613418 ps
CPU time 1696.83 seconds
Started May 28 01:12:58 PM PDT 24
Finished May 28 01:41:16 PM PDT 24
Peak memory 190836 kb
Host smart-a3151833-dec2-4dbf-aa7d-8cfa2cae4d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893639774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2893639774
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3224598521
Short name T96
Test name
Test status
Simulation time 933194775033 ps
CPU time 2860.88 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 02:00:53 PM PDT 24
Peak memory 190724 kb
Host smart-113c4db7-5171-4570-be5a-ef069016542e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224598521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3224598521
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1517562568
Short name T15
Test name
Test status
Simulation time 32214961 ps
CPU time 0.79 seconds
Started May 28 01:12:19 PM PDT 24
Finished May 28 01:12:21 PM PDT 24
Peak memory 212932 kb
Host smart-a71e12ea-7e48-4187-a53f-70009d29c9b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517562568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1517562568
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.570133610
Short name T54
Test name
Test status
Simulation time 7939548758584 ps
CPU time 2546.08 seconds
Started May 28 01:12:42 PM PDT 24
Finished May 28 01:55:11 PM PDT 24
Peak memory 190740 kb
Host smart-01cd03b5-cbba-43d4-93f0-31eae7771c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570133610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
570133610
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3689263974
Short name T112
Test name
Test status
Simulation time 1661083688371 ps
CPU time 2475.72 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:54:31 PM PDT 24
Peak memory 190836 kb
Host smart-ce9318ec-e8c8-4b26-9188-5ffac1c0c30a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689263974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3689263974
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3907074306
Short name T46
Test name
Test status
Simulation time 16417921 ps
CPU time 0.59 seconds
Started May 28 01:10:06 PM PDT 24
Finished May 28 01:10:08 PM PDT 24
Peak memory 182760 kb
Host smart-53af0ae8-9f42-4dd0-bc35-fe901a77c16b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907074306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3907074306
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3591722723
Short name T293
Test name
Test status
Simulation time 772437088964 ps
CPU time 1516.36 seconds
Started May 28 01:13:07 PM PDT 24
Finished May 28 01:38:33 PM PDT 24
Peak memory 190716 kb
Host smart-9ee4e376-aad6-422d-92e6-54dbf37e12db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591722723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3591722723
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.4256799990
Short name T162
Test name
Test status
Simulation time 1196792926288 ps
CPU time 2177.48 seconds
Started May 28 01:13:12 PM PDT 24
Finished May 28 01:49:35 PM PDT 24
Peak memory 190844 kb
Host smart-fd93d4e0-abf4-4e4c-98cd-84d185ac9000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256799990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.4256799990
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2972903732
Short name T26
Test name
Test status
Simulation time 784902152512 ps
CPU time 1240.02 seconds
Started May 28 01:12:25 PM PDT 24
Finished May 28 01:33:08 PM PDT 24
Peak memory 190844 kb
Host smart-1a63e6a8-d458-4dd9-b19b-8f9320fdc5d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972903732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2972903732
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3630838343
Short name T208
Test name
Test status
Simulation time 3162203812303 ps
CPU time 2712.64 seconds
Started May 28 01:12:24 PM PDT 24
Finished May 28 01:57:39 PM PDT 24
Peak memory 190768 kb
Host smart-456df9e2-5dc7-4448-ab0a-305826ea6718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630838343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3630838343
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4013705454
Short name T29
Test name
Test status
Simulation time 1003913110 ps
CPU time 1.37 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:18 PM PDT 24
Peak memory 194468 kb
Host smart-39271b1f-0498-42fb-b545-f419b847d184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013705454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4013705454
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3511206881
Short name T148
Test name
Test status
Simulation time 1075520043102 ps
CPU time 1959.72 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:45:31 PM PDT 24
Peak memory 190112 kb
Host smart-e2b5b143-2c8a-4cec-8674-1c805a6845c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511206881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3511206881
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1636324633
Short name T167
Test name
Test status
Simulation time 855902528297 ps
CPU time 788.74 seconds
Started May 28 01:12:06 PM PDT 24
Finished May 28 01:25:20 PM PDT 24
Peak memory 194304 kb
Host smart-4889ff29-9f64-4650-94e1-c6b8a4aff60b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636324633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1636324633
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1024971693
Short name T180
Test name
Test status
Simulation time 515109567238 ps
CPU time 982.86 seconds
Started May 28 01:13:00 PM PDT 24
Finished May 28 01:29:25 PM PDT 24
Peak memory 195252 kb
Host smart-cbe1c714-3b76-40b8-8e5c-96995ab92f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024971693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1024971693
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.757704272
Short name T90
Test name
Test status
Simulation time 132909139262 ps
CPU time 216.34 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:16:55 PM PDT 24
Peak memory 190712 kb
Host smart-3e29d3b8-b699-4430-9422-3da61debe6e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757704272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.757704272
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1123966628
Short name T198
Test name
Test status
Simulation time 2765787037910 ps
CPU time 2220.91 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:49:43 PM PDT 24
Peak memory 190768 kb
Host smart-10609b79-c574-4a57-9575-3499e1c8db5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123966628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1123966628
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2049429399
Short name T126
Test name
Test status
Simulation time 1455000643494 ps
CPU time 678.49 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:24:00 PM PDT 24
Peak memory 182612 kb
Host smart-60dc7b48-c20a-4ff9-b39f-3243b1e40386
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049429399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2049429399
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/138.rv_timer_random.1506459789
Short name T5
Test name
Test status
Simulation time 158682612687 ps
CPU time 471.84 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:21:13 PM PDT 24
Peak memory 190764 kb
Host smart-abe0f9dc-2cca-4502-aefd-7625beb3ede4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506459789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1506459789
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random.217971287
Short name T229
Test name
Test status
Simulation time 100383192017 ps
CPU time 217.26 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:16:49 PM PDT 24
Peak memory 190768 kb
Host smart-1b2787bb-ade9-4793-ba41-51ea5ce98c0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217971287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.217971287
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1176562728
Short name T270
Test name
Test status
Simulation time 142950757063 ps
CPU time 446.15 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:20:46 PM PDT 24
Peak memory 190704 kb
Host smart-d5036070-2958-4a91-bae4-a9ebca6cd652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176562728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1176562728
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1202216389
Short name T143
Test name
Test status
Simulation time 464356382789 ps
CPU time 1322.03 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:34:27 PM PDT 24
Peak memory 190748 kb
Host smart-0b56e4aa-a9af-45a1-a05e-671f423d1e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202216389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1202216389
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.2335546184
Short name T260
Test name
Test status
Simulation time 349068680322 ps
CPU time 1701.51 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:41:35 PM PDT 24
Peak memory 190824 kb
Host smart-6f0726ff-3dff-4c4a-aacf-2184fb4cbe81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335546184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2335546184
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2108132008
Short name T145
Test name
Test status
Simulation time 630301448111 ps
CPU time 497.37 seconds
Started May 28 01:13:05 PM PDT 24
Finished May 28 01:21:25 PM PDT 24
Peak memory 190748 kb
Host smart-0a981adb-13e6-4ad0-a1be-a1f248538405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108132008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2108132008
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3077090733
Short name T226
Test name
Test status
Simulation time 1296606698359 ps
CPU time 1353.69 seconds
Started May 28 01:12:07 PM PDT 24
Finished May 28 01:34:46 PM PDT 24
Peak memory 190828 kb
Host smart-041f553d-6248-48c1-adad-abdedc89c8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077090733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3077090733
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1854829223
Short name T228
Test name
Test status
Simulation time 2565484325349 ps
CPU time 1645.02 seconds
Started May 28 01:12:08 PM PDT 24
Finished May 28 01:39:38 PM PDT 24
Peak memory 190728 kb
Host smart-246f3056-f9f2-474a-93f4-3393b6bc7cac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854829223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1854829223
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1325298897
Short name T263
Test name
Test status
Simulation time 1049758056593 ps
CPU time 1060.17 seconds
Started May 28 01:12:51 PM PDT 24
Finished May 28 01:30:33 PM PDT 24
Peak memory 190816 kb
Host smart-309322be-df79-4710-a67b-551ea3378771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325298897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1325298897
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/176.rv_timer_random.1172422531
Short name T175
Test name
Test status
Simulation time 196370525685 ps
CPU time 748.89 seconds
Started May 28 01:13:30 PM PDT 24
Finished May 28 01:26:01 PM PDT 24
Peak memory 190764 kb
Host smart-2bffc4b2-a67e-4e3b-9ed0-706805759a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172422531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1172422531
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.89669268
Short name T118
Test name
Test status
Simulation time 450795563771 ps
CPU time 619.97 seconds
Started May 28 01:12:53 PM PDT 24
Finished May 28 01:23:14 PM PDT 24
Peak memory 190756 kb
Host smart-e10f9370-eb5f-4e39-8ae7-91a9be42e3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89669268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.89669268
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1951636335
Short name T56
Test name
Test status
Simulation time 779045077020 ps
CPU time 415.37 seconds
Started May 28 01:13:03 PM PDT 24
Finished May 28 01:20:02 PM PDT 24
Peak memory 182652 kb
Host smart-8cfdbe5a-76c7-4189-9b18-17f58f88cdbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951636335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1951636335
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3296534306
Short name T218
Test name
Test status
Simulation time 989975238933 ps
CPU time 281.8 seconds
Started May 28 01:12:10 PM PDT 24
Finished May 28 01:16:57 PM PDT 24
Peak memory 182644 kb
Host smart-34d812e1-f933-4c18-a912-259783aa7e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296534306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3296534306
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2527786399
Short name T213
Test name
Test status
Simulation time 130179292778 ps
CPU time 51.83 seconds
Started May 28 01:12:44 PM PDT 24
Finished May 28 01:13:39 PM PDT 24
Peak memory 182652 kb
Host smart-503517bb-f77f-4799-b387-f7d1ed0260b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527786399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2527786399
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3624775565
Short name T280
Test name
Test status
Simulation time 63476206210 ps
CPU time 639.28 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:23:52 PM PDT 24
Peak memory 190768 kb
Host smart-d5be5fa7-54da-49b4-9189-5f171ac62e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624775565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3624775565
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/108.rv_timer_random.2521019842
Short name T185
Test name
Test status
Simulation time 101612408681 ps
CPU time 1338.11 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:35:37 PM PDT 24
Peak memory 190700 kb
Host smart-7a33acf0-1f0b-4d54-bdca-0af241ced37c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521019842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2521019842
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.2405660849
Short name T254
Test name
Test status
Simulation time 357814085581 ps
CPU time 826.06 seconds
Started May 28 01:13:31 PM PDT 24
Finished May 28 01:27:19 PM PDT 24
Peak memory 194688 kb
Host smart-a2d4e6fc-cba2-4f27-89d2-412d2bbecce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405660849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2405660849
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.290333390
Short name T237
Test name
Test status
Simulation time 153812014659 ps
CPU time 143.57 seconds
Started May 28 01:13:39 PM PDT 24
Finished May 28 01:16:04 PM PDT 24
Peak memory 190808 kb
Host smart-c12df6a7-ad5f-4292-be13-9fdbf6f62cb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290333390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.290333390
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.3402520557
Short name T210
Test name
Test status
Simulation time 101789050671 ps
CPU time 176.75 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:15:37 PM PDT 24
Peak memory 190832 kb
Host smart-65bf1ccd-909d-4a31-9bf1-64e296d5ba19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402520557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3402520557
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.889800232
Short name T104
Test name
Test status
Simulation time 2149659122423 ps
CPU time 1569.34 seconds
Started May 28 01:13:30 PM PDT 24
Finished May 28 01:39:42 PM PDT 24
Peak memory 190768 kb
Host smart-99fc4eef-764d-4f1c-b323-12fedb2ca792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889800232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.889800232
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2535655567
Short name T149
Test name
Test status
Simulation time 497875349145 ps
CPU time 763.78 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:25:50 PM PDT 24
Peak memory 190844 kb
Host smart-f91b3950-4954-4491-9fa5-e70f992412f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535655567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2535655567
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3002269375
Short name T215
Test name
Test status
Simulation time 201757938062 ps
CPU time 339.06 seconds
Started May 28 01:12:54 PM PDT 24
Finished May 28 01:18:35 PM PDT 24
Peak memory 182604 kb
Host smart-562196fa-ac27-434b-a5b2-e4129c509feb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002269375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3002269375
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/74.rv_timer_random.2761600038
Short name T25
Test name
Test status
Simulation time 186654601502 ps
CPU time 447.37 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:20:50 PM PDT 24
Peak memory 190704 kb
Host smart-947dac04-555c-447b-ba30-55f65fc6ca06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761600038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2761600038
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3485353460
Short name T51
Test name
Test status
Simulation time 237540789362 ps
CPU time 407.26 seconds
Started May 28 01:12:28 PM PDT 24
Finished May 28 01:19:18 PM PDT 24
Peak memory 195280 kb
Host smart-64e9c571-564a-4467-a318-eedbf4fe0b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485353460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3485353460
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/134.rv_timer_random.8587955
Short name T156
Test name
Test status
Simulation time 313611572374 ps
CPU time 589.86 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:23:13 PM PDT 24
Peak memory 190804 kb
Host smart-49bd4b6f-af5a-4b16-8153-3ec515d7e41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8587955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.8587955
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1286148508
Short name T335
Test name
Test status
Simulation time 170067350141 ps
CPU time 81.35 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:14:44 PM PDT 24
Peak memory 190708 kb
Host smart-c0a2ab24-b5d5-413e-aba1-0929287e25d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286148508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1286148508
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.3347012290
Short name T166
Test name
Test status
Simulation time 151951263750 ps
CPU time 178.05 seconds
Started May 28 01:13:18 PM PDT 24
Finished May 28 01:16:22 PM PDT 24
Peak memory 190808 kb
Host smart-a60796f6-ac0b-4623-a430-f4d3f4ad4119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347012290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3347012290
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2158220944
Short name T289
Test name
Test status
Simulation time 262741002181 ps
CPU time 590.65 seconds
Started May 28 01:13:32 PM PDT 24
Finished May 28 01:23:24 PM PDT 24
Peak memory 190752 kb
Host smart-7b0d1e72-24b3-44db-a1dd-f920ae5e7cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158220944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2158220944
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1044839391
Short name T322
Test name
Test status
Simulation time 117584736853 ps
CPU time 219.68 seconds
Started May 28 01:13:23 PM PDT 24
Finished May 28 01:17:06 PM PDT 24
Peak memory 190768 kb
Host smart-30c33cfd-6743-4721-a93c-0ac3a259178a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044839391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1044839391
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3759389028
Short name T115
Test name
Test status
Simulation time 1192835147885 ps
CPU time 934.51 seconds
Started May 28 01:12:43 PM PDT 24
Finished May 28 01:28:20 PM PDT 24
Peak memory 195816 kb
Host smart-32caddee-cbad-4f62-a02b-2d2395a6291a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759389028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3759389028
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4011564199
Short name T2
Test name
Test status
Simulation time 69594785013 ps
CPU time 141.2 seconds
Started May 28 01:12:42 PM PDT 24
Finished May 28 01:15:06 PM PDT 24
Peak memory 190744 kb
Host smart-7ff014d0-7598-4a85-a6b9-31213e785ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011564199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4011564199
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_random.2835882368
Short name T146
Test name
Test status
Simulation time 65734411799 ps
CPU time 217.68 seconds
Started May 28 01:13:20 PM PDT 24
Finished May 28 01:17:03 PM PDT 24
Peak memory 190800 kb
Host smart-3ac370c8-0039-4a57-a424-8e44f22f6691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835882368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2835882368
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.654292969
Short name T159
Test name
Test status
Simulation time 445032382038 ps
CPU time 311.2 seconds
Started May 28 01:12:59 PM PDT 24
Finished May 28 01:18:12 PM PDT 24
Peak memory 190820 kb
Host smart-8e677afd-4ee9-4754-bed0-73589fb22edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654292969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.654292969
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.355744878
Short name T171
Test name
Test status
Simulation time 178524320029 ps
CPU time 2017.44 seconds
Started May 28 01:12:26 PM PDT 24
Finished May 28 01:46:06 PM PDT 24
Peak memory 190756 kb
Host smart-dad2a572-50d9-4fb8-b6be-645b354f9122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355744878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.355744878
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1372181741
Short name T396
Test name
Test status
Simulation time 298604756114 ps
CPU time 947.01 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:29:12 PM PDT 24
Peak memory 192904 kb
Host smart-d3ee255a-3907-4342-87df-fa30a21831d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372181741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1372181741
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.355590084
Short name T79
Test name
Test status
Simulation time 65507346 ps
CPU time 0.72 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:46 PM PDT 24
Peak memory 193060 kb
Host smart-def7c7a4-878b-401f-9335-a0095151884a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355590084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.355590084
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_random.3039422798
Short name T216
Test name
Test status
Simulation time 16880148377 ps
CPU time 109.13 seconds
Started May 28 01:12:07 PM PDT 24
Finished May 28 01:14:01 PM PDT 24
Peak memory 190768 kb
Host smart-bdc8932e-02fc-4ddd-9bd1-8aef1b3f155f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039422798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3039422798
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3892545575
Short name T249
Test name
Test status
Simulation time 286025543420 ps
CPU time 190.13 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:16:33 PM PDT 24
Peak memory 190764 kb
Host smart-6fa3bf01-9302-43fe-bb8f-70ef2512ee6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892545575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3892545575
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1448256936
Short name T110
Test name
Test status
Simulation time 121146997116 ps
CPU time 488.68 seconds
Started May 28 01:12:48 PM PDT 24
Finished May 28 01:21:01 PM PDT 24
Peak memory 190836 kb
Host smart-862de55b-287c-4fe5-8549-0d732eb6a893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448256936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1448256936
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3422352425
Short name T23
Test name
Test status
Simulation time 49048302463 ps
CPU time 63.66 seconds
Started May 28 01:13:12 PM PDT 24
Finished May 28 01:14:20 PM PDT 24
Peak memory 182568 kb
Host smart-f68b9543-0fc6-4ac2-ae4f-8cf257f67134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422352425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3422352425
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1176049301
Short name T130
Test name
Test status
Simulation time 75763236151 ps
CPU time 31.48 seconds
Started May 28 01:13:20 PM PDT 24
Finished May 28 01:13:56 PM PDT 24
Peak memory 182632 kb
Host smart-12758012-6937-4d36-b040-2e7c32b97fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176049301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1176049301
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3087815901
Short name T250
Test name
Test status
Simulation time 61408744821 ps
CPU time 278.27 seconds
Started May 28 01:13:32 PM PDT 24
Finished May 28 01:18:12 PM PDT 24
Peak memory 190764 kb
Host smart-9379cdd6-bb26-44ae-8c32-d68515e171dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087815901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3087815901
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1531437295
Short name T273
Test name
Test status
Simulation time 86979833491 ps
CPU time 119.83 seconds
Started May 28 01:13:26 PM PDT 24
Finished May 28 01:15:27 PM PDT 24
Peak memory 182640 kb
Host smart-e4e45c84-f4bf-432b-a377-8134b57c93ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531437295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1531437295
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2810183302
Short name T251
Test name
Test status
Simulation time 451987056024 ps
CPU time 944.4 seconds
Started May 28 01:13:31 PM PDT 24
Finished May 28 01:29:17 PM PDT 24
Peak memory 190760 kb
Host smart-7330018a-7604-445b-ba52-f1920fd59cbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810183302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2810183302
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2029018430
Short name T346
Test name
Test status
Simulation time 247882514541 ps
CPU time 591.09 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:23:22 PM PDT 24
Peak memory 190756 kb
Host smart-d0f675dc-ba6e-4e79-816b-f8220216c25f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029018430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2029018430
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.861843660
Short name T154
Test name
Test status
Simulation time 167293853991 ps
CPU time 355.63 seconds
Started May 28 01:13:23 PM PDT 24
Finished May 28 01:19:22 PM PDT 24
Peak memory 190764 kb
Host smart-592b8c20-7edc-44fa-a814-8f14bac102ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861843660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.861843660
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.153742871
Short name T152
Test name
Test status
Simulation time 489283116413 ps
CPU time 1059.39 seconds
Started May 28 01:13:30 PM PDT 24
Finished May 28 01:31:12 PM PDT 24
Peak memory 190760 kb
Host smart-e9e3b146-529e-4063-a701-4b9da9531e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153742871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.153742871
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.2214815460
Short name T163
Test name
Test status
Simulation time 131070652052 ps
CPU time 740.08 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:25:03 PM PDT 24
Peak memory 190860 kb
Host smart-948d2427-8a8f-4f0b-8873-ef1b9f2ca64f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214815460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2214815460
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3395299895
Short name T99
Test name
Test status
Simulation time 11892605973 ps
CPU time 6.81 seconds
Started May 28 01:13:05 PM PDT 24
Finished May 28 01:13:15 PM PDT 24
Peak memory 182600 kb
Host smart-1a4a8129-df66-4f15-a772-cbf9a192d2dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395299895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3395299895
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_random.343176287
Short name T138
Test name
Test status
Simulation time 308372111981 ps
CPU time 574.64 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:22:47 PM PDT 24
Peak memory 192836 kb
Host smart-fc5676fe-bcbc-4eed-8272-3cebaedcde42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343176287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.343176287
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1978924545
Short name T296
Test name
Test status
Simulation time 263984207268 ps
CPU time 186.01 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:16:27 PM PDT 24
Peak memory 190712 kb
Host smart-98f74ded-7e6d-461f-8283-d1bf4dbf2b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978924545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1978924545
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2113221462
Short name T315
Test name
Test status
Simulation time 65633163299 ps
CPU time 114.5 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:15:20 PM PDT 24
Peak memory 190836 kb
Host smart-4cb7982c-95ef-47a7-acfe-080a2e75dde9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113221462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2113221462
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2608851788
Short name T572
Test name
Test status
Simulation time 40900296 ps
CPU time 0.79 seconds
Started May 28 01:09:44 PM PDT 24
Finished May 28 01:09:48 PM PDT 24
Peak memory 193372 kb
Host smart-92f8488a-6528-4ed6-8e73-5b7ea0d0a0f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608851788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2608851788
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.511065569
Short name T168
Test name
Test status
Simulation time 779293153950 ps
CPU time 873.2 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:26:58 PM PDT 24
Peak memory 190748 kb
Host smart-59bdcb4d-c903-4a9c-8e0d-61446d38717a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511065569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.511065569
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2526561627
Short name T267
Test name
Test status
Simulation time 432138152683 ps
CPU time 434.54 seconds
Started May 28 01:12:21 PM PDT 24
Finished May 28 01:19:38 PM PDT 24
Peak memory 182520 kb
Host smart-c7355956-c305-4070-b91e-5fa315a13ccd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526561627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2526561627
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/107.rv_timer_random.3840577374
Short name T24
Test name
Test status
Simulation time 666392777523 ps
CPU time 291.61 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:18:11 PM PDT 24
Peak memory 190672 kb
Host smart-f1aa31f1-33a6-4cac-8bda-bfa5224416d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840577374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3840577374
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.366747031
Short name T97
Test name
Test status
Simulation time 166546262287 ps
CPU time 296.31 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:18:12 PM PDT 24
Peak memory 190760 kb
Host smart-3a42469c-004f-41a9-a9cd-61e4e644c6f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366747031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.366747031
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.2762194349
Short name T320
Test name
Test status
Simulation time 32769976163 ps
CPU time 188.63 seconds
Started May 28 01:12:24 PM PDT 24
Finished May 28 01:15:35 PM PDT 24
Peak memory 182636 kb
Host smart-19ea4b3a-3216-4b94-8ffc-5d36a83d6400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762194349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2762194349
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2684361503
Short name T200
Test name
Test status
Simulation time 69995048969 ps
CPU time 58.1 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:14:13 PM PDT 24
Peak memory 190764 kb
Host smart-5433d5be-b3dc-4f4d-bbfc-8b27fac26270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684361503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2684361503
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.996333772
Short name T232
Test name
Test status
Simulation time 103028499267 ps
CPU time 56.77 seconds
Started May 28 01:12:49 PM PDT 24
Finished May 28 01:13:49 PM PDT 24
Peak memory 182552 kb
Host smart-3e36b3d4-d0ce-4682-878c-74366f977ca3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996333772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.996333772
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_random.1281583058
Short name T182
Test name
Test status
Simulation time 185384598386 ps
CPU time 116.02 seconds
Started May 28 01:12:38 PM PDT 24
Finished May 28 01:14:35 PM PDT 24
Peak memory 190800 kb
Host smart-d33c2561-05b5-4810-9bf5-5a7f741708b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281583058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1281583058
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3814837841
Short name T204
Test name
Test status
Simulation time 1813266061004 ps
CPU time 733.64 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:25:29 PM PDT 24
Peak memory 190812 kb
Host smart-66ba0af6-877c-496c-86b3-fd89a04480e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814837841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3814837841
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.451174485
Short name T345
Test name
Test status
Simulation time 60499876972 ps
CPU time 745.19 seconds
Started May 28 01:13:13 PM PDT 24
Finished May 28 01:25:42 PM PDT 24
Peak memory 190772 kb
Host smart-5e7f492c-070f-4dcb-b4fd-72eb7b3cbccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451174485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.451174485
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.954190052
Short name T139
Test name
Test status
Simulation time 270665994268 ps
CPU time 143.62 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:15:46 PM PDT 24
Peak memory 193152 kb
Host smart-049600d9-c3c0-4524-91a1-273d104f8b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954190052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.954190052
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2792220411
Short name T326
Test name
Test status
Simulation time 239625186384 ps
CPU time 976.71 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:29:47 PM PDT 24
Peak memory 190740 kb
Host smart-e99d5319-cec5-441a-ab44-2b870d32da34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792220411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2792220411
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4077461367
Short name T93
Test name
Test status
Simulation time 149498375557 ps
CPU time 98.39 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:14:22 PM PDT 24
Peak memory 182584 kb
Host smart-e49c7bc8-29c8-464c-abb4-27afc7fe2eb7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077461367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4077461367
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1179681065
Short name T246
Test name
Test status
Simulation time 426328659977 ps
CPU time 984.96 seconds
Started May 28 01:12:43 PM PDT 24
Finished May 28 01:29:12 PM PDT 24
Peak memory 196100 kb
Host smart-789513b5-e46d-4271-b2bd-5ade5cef3b15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179681065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1179681065
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2038345076
Short name T271
Test name
Test status
Simulation time 334378809737 ps
CPU time 2367.36 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:52:11 PM PDT 24
Peak memory 195400 kb
Host smart-212a329f-10ea-4e17-9f2e-6785b53b4edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038345076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2038345076
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/193.rv_timer_random.3634633643
Short name T266
Test name
Test status
Simulation time 575586909334 ps
CPU time 1067.14 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:31:18 PM PDT 24
Peak memory 190764 kb
Host smart-3428b90b-53d0-4f05-8a6a-10bc7b63d04d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634633643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3634633643
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3667235340
Short name T98
Test name
Test status
Simulation time 64222819563 ps
CPU time 119.64 seconds
Started May 28 01:13:30 PM PDT 24
Finished May 28 01:15:32 PM PDT 24
Peak memory 192864 kb
Host smart-aeea9cce-0107-4fff-99a1-9d713de4b3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667235340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3667235340
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4256377596
Short name T123
Test name
Test status
Simulation time 135133145487 ps
CPU time 96.79 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:14:27 PM PDT 24
Peak memory 182584 kb
Host smart-6bd7c4a7-3620-4ace-b49f-d45a71cf50a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256377596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4256377596
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.61093063
Short name T225
Test name
Test status
Simulation time 109385087597 ps
CPU time 204.04 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:16:07 PM PDT 24
Peak memory 190836 kb
Host smart-60b48e34-8475-467e-9457-0c776ab97518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61093063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.61093063
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2011484672
Short name T278
Test name
Test status
Simulation time 240058123228 ps
CPU time 406.03 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:19:30 PM PDT 24
Peak memory 182648 kb
Host smart-eca1ff5f-afa0-4c31-8ecf-67266ad73a02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011484672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2011484672
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.1829590945
Short name T307
Test name
Test status
Simulation time 132584509581 ps
CPU time 253.89 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:17:05 PM PDT 24
Peak memory 190824 kb
Host smart-50af2866-a056-44ef-b293-564c71ed07c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829590945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1829590945
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3667115332
Short name T333
Test name
Test status
Simulation time 61977513095 ps
CPU time 1816.71 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:43:29 PM PDT 24
Peak memory 190840 kb
Host smart-3295dbd1-d592-45c5-823d-f595b903df4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667115332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3667115332
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_random.4063150360
Short name T190
Test name
Test status
Simulation time 965645289045 ps
CPU time 564.32 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:22:45 PM PDT 24
Peak memory 190876 kb
Host smart-13d25771-1891-49b9-bdaa-a08a93c71754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063150360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4063150360
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1386706661
Short name T281
Test name
Test status
Simulation time 362583505567 ps
CPU time 200.01 seconds
Started May 28 01:12:58 PM PDT 24
Finished May 28 01:16:19 PM PDT 24
Peak memory 190764 kb
Host smart-635aeb64-6781-442e-91e2-aa446922af20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386706661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1386706661
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2246138569
Short name T223
Test name
Test status
Simulation time 815794058130 ps
CPU time 432.76 seconds
Started May 28 01:12:09 PM PDT 24
Finished May 28 01:19:27 PM PDT 24
Peak memory 182636 kb
Host smart-d15c252c-c4f9-4433-8499-cc01ae5cf824
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246138569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2246138569
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3134983180
Short name T227
Test name
Test status
Simulation time 68753556161 ps
CPU time 113.72 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:15:06 PM PDT 24
Peak memory 182652 kb
Host smart-8a7016af-a441-40b5-b274-fb18c1ca231d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134983180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3134983180
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/91.rv_timer_random.2381678355
Short name T234
Test name
Test status
Simulation time 441862918680 ps
CPU time 272.61 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:17:55 PM PDT 24
Peak memory 193460 kb
Host smart-42f849de-0cbd-481d-a229-5ee88b2e3b40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381678355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2381678355
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4185973405
Short name T65
Test name
Test status
Simulation time 129326298 ps
CPU time 0.62 seconds
Started May 28 01:09:46 PM PDT 24
Finished May 28 01:09:51 PM PDT 24
Peak memory 182580 kb
Host smart-12f69f91-36f6-48e2-8f07-60bc16ac34c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185973405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4185973405
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.746416610
Short name T74
Test name
Test status
Simulation time 148643632 ps
CPU time 1.61 seconds
Started May 28 01:09:49 PM PDT 24
Finished May 28 01:09:55 PM PDT 24
Peak memory 191164 kb
Host smart-fd27cb2e-e7a1-4c9a-bce8-f7b228244d34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746416610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.746416610
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2790837756
Short name T48
Test name
Test status
Simulation time 77740204 ps
CPU time 0.53 seconds
Started May 28 01:09:31 PM PDT 24
Finished May 28 01:09:36 PM PDT 24
Peak memory 182116 kb
Host smart-2ca78295-64a9-4f64-9fd0-190e6bde6fac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790837756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2790837756
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3030898517
Short name T488
Test name
Test status
Simulation time 110505463 ps
CPU time 0.7 seconds
Started May 28 01:09:47 PM PDT 24
Finished May 28 01:09:52 PM PDT 24
Peak memory 194312 kb
Host smart-65250602-e984-4112-8332-002200c916cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030898517 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3030898517
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1409621527
Short name T481
Test name
Test status
Simulation time 110942674 ps
CPU time 0.62 seconds
Started May 28 01:09:45 PM PDT 24
Finished May 28 01:09:50 PM PDT 24
Peak memory 182676 kb
Host smart-94adc33d-45ff-40dd-bcad-4cf8a7dfd701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409621527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1409621527
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3894444154
Short name T500
Test name
Test status
Simulation time 18828189 ps
CPU time 0.52 seconds
Started May 28 01:09:49 PM PDT 24
Finished May 28 01:09:54 PM PDT 24
Peak memory 181972 kb
Host smart-bb486cd1-c145-41d3-842a-14565da10f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894444154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3894444154
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.78478406
Short name T472
Test name
Test status
Simulation time 57755923 ps
CPU time 1.2 seconds
Started May 28 01:09:41 PM PDT 24
Finished May 28 01:09:44 PM PDT 24
Peak memory 197476 kb
Host smart-8c0fe888-f712-4513-9fa4-09b138e779a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78478406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.78478406
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.4197464951
Short name T539
Test name
Test status
Simulation time 58754029 ps
CPU time 0.73 seconds
Started May 28 01:09:48 PM PDT 24
Finished May 28 01:09:53 PM PDT 24
Peak memory 182656 kb
Host smart-a70fcb1b-073d-49a8-a44c-085dd7bfa997
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197464951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.4197464951
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2467444490
Short name T75
Test name
Test status
Simulation time 2382985647 ps
CPU time 3.56 seconds
Started May 28 01:09:50 PM PDT 24
Finished May 28 01:09:59 PM PDT 24
Peak memory 192876 kb
Host smart-e1e67c18-4da3-409a-81a3-e75d59bf6135
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467444490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2467444490
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.721291806
Short name T573
Test name
Test status
Simulation time 14834329 ps
CPU time 0.55 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:46 PM PDT 24
Peak memory 182536 kb
Host smart-7e94a2a1-235f-43a1-8cec-a6bd6dbafe84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721291806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.721291806
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2796624102
Short name T560
Test name
Test status
Simulation time 25604003 ps
CPU time 0.7 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:47 PM PDT 24
Peak memory 194464 kb
Host smart-3975accc-d31f-4f36-afad-9f3802902e12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796624102 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2796624102
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4160417976
Short name T487
Test name
Test status
Simulation time 15076981 ps
CPU time 0.63 seconds
Started May 28 01:09:56 PM PDT 24
Finished May 28 01:10:00 PM PDT 24
Peak memory 182520 kb
Host smart-5854c4eb-f3c0-4bd1-bc3d-b6bf1b729f74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160417976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.4160417976
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.188155909
Short name T518
Test name
Test status
Simulation time 18486207 ps
CPU time 0.52 seconds
Started May 28 01:09:47 PM PDT 24
Finished May 28 01:09:52 PM PDT 24
Peak memory 182580 kb
Host smart-95a0eac7-34f1-4971-afc7-4a3ddeafb18a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188155909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.188155909
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1755648366
Short name T498
Test name
Test status
Simulation time 19292411 ps
CPU time 0.86 seconds
Started May 28 01:09:41 PM PDT 24
Finished May 28 01:09:43 PM PDT 24
Peak memory 194136 kb
Host smart-df1ed671-ee23-482b-9372-3df4c682ab2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755648366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1755648366
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1696950332
Short name T45
Test name
Test status
Simulation time 258727618 ps
CPU time 2.73 seconds
Started May 28 01:09:49 PM PDT 24
Finished May 28 01:09:56 PM PDT 24
Peak memory 197556 kb
Host smart-51db3217-1996-4604-8945-a84c5547ad0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696950332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1696950332
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1014252920
Short name T86
Test name
Test status
Simulation time 366317793 ps
CPU time 1.39 seconds
Started May 28 01:09:52 PM PDT 24
Finished May 28 01:09:59 PM PDT 24
Peak memory 183664 kb
Host smart-b47bfc0f-0193-4dcf-80bd-1866f25727ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014252920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1014252920
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2754708520
Short name T510
Test name
Test status
Simulation time 38957237 ps
CPU time 1.66 seconds
Started May 28 01:10:14 PM PDT 24
Finished May 28 01:10:23 PM PDT 24
Peak memory 197552 kb
Host smart-ceb1e404-a600-42e6-adc3-366c8f6030f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754708520 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2754708520
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4260919291
Short name T575
Test name
Test status
Simulation time 14968062 ps
CPU time 0.61 seconds
Started May 28 01:10:13 PM PDT 24
Finished May 28 01:10:21 PM PDT 24
Peak memory 182764 kb
Host smart-5e89dd29-0237-415f-81f6-6166c010d837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260919291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4260919291
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3979663709
Short name T564
Test name
Test status
Simulation time 62846295 ps
CPU time 0.58 seconds
Started May 28 01:09:55 PM PDT 24
Finished May 28 01:09:59 PM PDT 24
Peak memory 182480 kb
Host smart-b58700f8-53de-453c-9ae0-fcb95345aa5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979663709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3979663709
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1761581356
Short name T551
Test name
Test status
Simulation time 160010648 ps
CPU time 0.83 seconds
Started May 28 01:10:04 PM PDT 24
Finished May 28 01:10:06 PM PDT 24
Peak memory 193388 kb
Host smart-630c562d-dbb6-4fc7-bfb4-b6b898eca72b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761581356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1761581356
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1948319456
Short name T492
Test name
Test status
Simulation time 128142680 ps
CPU time 2.22 seconds
Started May 28 01:09:50 PM PDT 24
Finished May 28 01:09:57 PM PDT 24
Peak memory 197500 kb
Host smart-3fe2ce0f-6cdd-48a9-90aa-0e6e625bbc81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948319456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1948319456
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4218484015
Short name T455
Test name
Test status
Simulation time 152986891 ps
CPU time 1.47 seconds
Started May 28 01:10:12 PM PDT 24
Finished May 28 01:10:21 PM PDT 24
Peak memory 197908 kb
Host smart-cb03719e-3a96-4ebe-8fd7-946883ca9c24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218484015 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4218484015
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2289033576
Short name T532
Test name
Test status
Simulation time 14983735 ps
CPU time 0.58 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:10:19 PM PDT 24
Peak memory 182668 kb
Host smart-33a5ad2b-bc59-4859-89ef-0ba6719e96c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289033576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2289033576
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3154741429
Short name T528
Test name
Test status
Simulation time 13350649 ps
CPU time 0.58 seconds
Started May 28 01:10:06 PM PDT 24
Finished May 28 01:10:09 PM PDT 24
Peak memory 182484 kb
Host smart-4a54e7fc-c2dc-4d30-84ce-a92e0ef68b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154741429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3154741429
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3702034904
Short name T565
Test name
Test status
Simulation time 101378871 ps
CPU time 0.87 seconds
Started May 28 01:10:06 PM PDT 24
Finished May 28 01:10:09 PM PDT 24
Peak memory 193460 kb
Host smart-525bbc63-b296-48d1-9df8-01369676b662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702034904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3702034904
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.814491896
Short name T451
Test name
Test status
Simulation time 33541641 ps
CPU time 1.78 seconds
Started May 28 01:10:04 PM PDT 24
Finished May 28 01:10:08 PM PDT 24
Peak memory 197564 kb
Host smart-bd98be9b-ba9b-4369-9bf8-e3bb95f83454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814491896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.814491896
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.731100727
Short name T89
Test name
Test status
Simulation time 116210366 ps
CPU time 0.81 seconds
Started May 28 01:10:04 PM PDT 24
Finished May 28 01:10:05 PM PDT 24
Peak memory 193696 kb
Host smart-ff184b80-ab96-46f1-af1c-4303414f71ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731100727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.731100727
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1593149149
Short name T47
Test name
Test status
Simulation time 37846798 ps
CPU time 0.81 seconds
Started May 28 01:10:16 PM PDT 24
Finished May 28 01:10:24 PM PDT 24
Peak memory 195524 kb
Host smart-dddd0eed-f3e3-4c47-9606-4e5c2f9cdbb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593149149 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1593149149
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2940248997
Short name T50
Test name
Test status
Simulation time 28663083 ps
CPU time 0.57 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:14 PM PDT 24
Peak memory 182640 kb
Host smart-3a8a25a3-e286-4d9f-8bdd-40a4ca1a02e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940248997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2940248997
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3418342255
Short name T493
Test name
Test status
Simulation time 40930709 ps
CPU time 0.53 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:13 PM PDT 24
Peak memory 182528 kb
Host smart-22d5eb6b-3cf9-48ca-8d5b-b11bd5f84858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418342255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3418342255
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.576083457
Short name T537
Test name
Test status
Simulation time 37917228 ps
CPU time 0.84 seconds
Started May 28 01:10:02 PM PDT 24
Finished May 28 01:10:03 PM PDT 24
Peak memory 193352 kb
Host smart-50ed60ad-2590-4acf-8457-6f11f0b29b5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576083457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.576083457
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3750724098
Short name T512
Test name
Test status
Simulation time 121281802 ps
CPU time 2.41 seconds
Started May 28 01:10:05 PM PDT 24
Finished May 28 01:10:09 PM PDT 24
Peak memory 197660 kb
Host smart-a85104b7-c2b7-4dd5-92cb-04fa38610eac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750724098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3750724098
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4114792833
Short name T27
Test name
Test status
Simulation time 480133380 ps
CPU time 1.08 seconds
Started May 28 01:10:04 PM PDT 24
Finished May 28 01:10:06 PM PDT 24
Peak memory 194920 kb
Host smart-514348d7-cc89-4255-b003-88b21677d6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114792833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4114792833
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.610849830
Short name T458
Test name
Test status
Simulation time 74445703 ps
CPU time 0.79 seconds
Started May 28 01:10:01 PM PDT 24
Finished May 28 01:10:03 PM PDT 24
Peak memory 195028 kb
Host smart-b77047db-4d10-4065-9f30-6ddbd88c9d37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610849830 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.610849830
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.152762426
Short name T67
Test name
Test status
Simulation time 40131465 ps
CPU time 0.63 seconds
Started May 28 01:10:14 PM PDT 24
Finished May 28 01:10:22 PM PDT 24
Peak memory 182676 kb
Host smart-8ba7fde4-1c4d-4593-9f4d-10d9244b8eae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152762426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.152762426
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1914531375
Short name T457
Test name
Test status
Simulation time 15002978 ps
CPU time 0.58 seconds
Started May 28 01:10:04 PM PDT 24
Finished May 28 01:10:05 PM PDT 24
Peak memory 182600 kb
Host smart-572aa96e-a751-4e98-8a86-00f12de10acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914531375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1914531375
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.277484827
Short name T548
Test name
Test status
Simulation time 104937092 ps
CPU time 0.61 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 191440 kb
Host smart-12ace0a5-2284-4d51-857f-7e743b595da3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277484827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.277484827
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1102201281
Short name T482
Test name
Test status
Simulation time 131217696 ps
CPU time 2.11 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:19 PM PDT 24
Peak memory 197524 kb
Host smart-4a8c920d-8559-4b91-93f8-3fc622bf1e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102201281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1102201281
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2799798444
Short name T471
Test name
Test status
Simulation time 80180713 ps
CPU time 0.82 seconds
Started May 28 01:09:58 PM PDT 24
Finished May 28 01:10:00 PM PDT 24
Peak memory 182896 kb
Host smart-39e242e7-4d59-4c66-ac85-b6848d07977c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799798444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2799798444
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2203065643
Short name T544
Test name
Test status
Simulation time 29893952 ps
CPU time 0.74 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:12 PM PDT 24
Peak memory 195008 kb
Host smart-2a3c504b-7e90-4a5e-9373-03f2a6853017
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203065643 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2203065643
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2146757036
Short name T577
Test name
Test status
Simulation time 13915173 ps
CPU time 0.58 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:11 PM PDT 24
Peak memory 182720 kb
Host smart-f4388357-e673-400c-83f6-be01de235217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146757036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2146757036
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1395792806
Short name T459
Test name
Test status
Simulation time 45057863 ps
CPU time 0.54 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:16 PM PDT 24
Peak memory 182336 kb
Host smart-0b73e27b-44ad-4444-a107-b378664b501d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395792806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1395792806
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.655726642
Short name T489
Test name
Test status
Simulation time 145537241 ps
CPU time 0.79 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:18 PM PDT 24
Peak memory 193140 kb
Host smart-a117115e-0ad7-4481-afa6-0834a7985bc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655726642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.655726642
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2076356860
Short name T571
Test name
Test status
Simulation time 154278372 ps
CPU time 2.66 seconds
Started May 28 01:10:05 PM PDT 24
Finished May 28 01:10:09 PM PDT 24
Peak memory 197632 kb
Host smart-bc1dd390-8a44-423f-a107-f7b7667a0f43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076356860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2076356860
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1264823565
Short name T85
Test name
Test status
Simulation time 238225040 ps
CPU time 1.04 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:10:19 PM PDT 24
Peak memory 195176 kb
Host smart-63491fc5-8018-4170-96c3-48558a9d69db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264823565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1264823565
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3421018377
Short name T541
Test name
Test status
Simulation time 330731570 ps
CPU time 0.74 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:14 PM PDT 24
Peak memory 194592 kb
Host smart-ad2b2f72-7da3-4872-ba44-40994748740f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421018377 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3421018377
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3239190849
Short name T68
Test name
Test status
Simulation time 48386136 ps
CPU time 0.58 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:12 PM PDT 24
Peak memory 182664 kb
Host smart-1c466281-c683-44f6-b28c-974d6c87b715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239190849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3239190849
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1351521541
Short name T519
Test name
Test status
Simulation time 84559465 ps
CPU time 0.53 seconds
Started May 28 01:10:01 PM PDT 24
Finished May 28 01:10:03 PM PDT 24
Peak memory 182000 kb
Host smart-017313c3-05c2-4271-b26c-b3ee302dc6ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351521541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1351521541
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3132634572
Short name T80
Test name
Test status
Simulation time 113820835 ps
CPU time 0.84 seconds
Started May 28 01:10:12 PM PDT 24
Finished May 28 01:10:20 PM PDT 24
Peak memory 193528 kb
Host smart-ac1c71d5-fa44-4163-a524-aca3cd8a1869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132634572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3132634572
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3256943408
Short name T517
Test name
Test status
Simulation time 889210386 ps
CPU time 2.7 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:17 PM PDT 24
Peak memory 197580 kb
Host smart-9c583462-e98f-44b0-807f-f538fd5b2cac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256943408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3256943408
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.589971608
Short name T506
Test name
Test status
Simulation time 161857390 ps
CPU time 0.87 seconds
Started May 28 01:10:05 PM PDT 24
Finished May 28 01:10:08 PM PDT 24
Peak memory 192052 kb
Host smart-448c1f67-6418-4941-821c-3ef214e3b459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589971608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.589971608
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3275354674
Short name T529
Test name
Test status
Simulation time 44017297 ps
CPU time 0.99 seconds
Started May 28 01:10:14 PM PDT 24
Finished May 28 01:10:22 PM PDT 24
Peak memory 197348 kb
Host smart-7e235e9d-476e-474a-9c6f-61d05ebf9ca3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275354674 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3275354674
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.872522797
Short name T542
Test name
Test status
Simulation time 12938350 ps
CPU time 0.61 seconds
Started May 28 01:10:05 PM PDT 24
Finished May 28 01:10:07 PM PDT 24
Peak memory 182740 kb
Host smart-efdd3d46-50ac-43b7-8e17-94af0ff41f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872522797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.872522797
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2870025199
Short name T454
Test name
Test status
Simulation time 12395732 ps
CPU time 0.56 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 182592 kb
Host smart-59d86084-fd5c-4ded-a670-7bc13b2e5eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870025199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2870025199
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.917771046
Short name T543
Test name
Test status
Simulation time 28216570 ps
CPU time 0.74 seconds
Started May 28 01:10:17 PM PDT 24
Finished May 28 01:10:24 PM PDT 24
Peak memory 193100 kb
Host smart-cdbf9814-a153-4509-8b97-ca942c0d2a77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917771046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.917771046
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.971172969
Short name T469
Test name
Test status
Simulation time 61178385 ps
CPU time 1.72 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:17 PM PDT 24
Peak memory 197520 kb
Host smart-8a9a783e-7eba-4791-8698-47dc5c79ae97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971172969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.971172969
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2921361134
Short name T566
Test name
Test status
Simulation time 518407741 ps
CPU time 1.41 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:13 PM PDT 24
Peak memory 194404 kb
Host smart-0fa84e6f-cb7f-4474-a303-1d8e41a97a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921361134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2921361134
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4025571058
Short name T473
Test name
Test status
Simulation time 43421518 ps
CPU time 1.1 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:16 PM PDT 24
Peak memory 197380 kb
Host smart-09314735-aa5d-48b3-8837-0903a1209d6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025571058 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4025571058
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2893611237
Short name T550
Test name
Test status
Simulation time 43088109 ps
CPU time 0.58 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:17 PM PDT 24
Peak memory 182704 kb
Host smart-541d44cd-a6b6-4c5c-aa1f-fd97cec20652
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893611237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2893611237
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.395802876
Short name T530
Test name
Test status
Simulation time 16782958 ps
CPU time 0.55 seconds
Started May 28 01:09:55 PM PDT 24
Finished May 28 01:09:59 PM PDT 24
Peak memory 182124 kb
Host smart-f0e437d3-e9ea-47af-8c44-7997822feafa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395802876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.395802876
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2338519916
Short name T66
Test name
Test status
Simulation time 22883416 ps
CPU time 0.88 seconds
Started May 28 01:09:58 PM PDT 24
Finished May 28 01:10:01 PM PDT 24
Peak memory 193460 kb
Host smart-1deb54c4-9fc5-4261-b604-3666c02e1892
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338519916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2338519916
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.268206146
Short name T567
Test name
Test status
Simulation time 221331651 ps
CPU time 2.25 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:16 PM PDT 24
Peak memory 197516 kb
Host smart-18f31030-3aa2-4dac-8924-454c6e7f82b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268206146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.268206146
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1282318397
Short name T523
Test name
Test status
Simulation time 157654756 ps
CPU time 1.11 seconds
Started May 28 01:10:17 PM PDT 24
Finished May 28 01:10:25 PM PDT 24
Peak memory 183440 kb
Host smart-a512bf4e-7ecb-4816-9fdb-76566edc352f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282318397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1282318397
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3373930665
Short name T470
Test name
Test status
Simulation time 161662791 ps
CPU time 0.65 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:10:18 PM PDT 24
Peak memory 194684 kb
Host smart-efc22424-4142-42f5-a7c0-91e9602479f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373930665 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3373930665
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1739032551
Short name T479
Test name
Test status
Simulation time 18048834 ps
CPU time 0.55 seconds
Started May 28 01:10:17 PM PDT 24
Finished May 28 01:10:24 PM PDT 24
Peak memory 182596 kb
Host smart-e9028cc8-b3df-4c2b-a497-2d64ff69f29b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739032551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1739032551
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2805403854
Short name T520
Test name
Test status
Simulation time 18903290 ps
CPU time 0.69 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:10:20 PM PDT 24
Peak memory 193152 kb
Host smart-490c92e0-5cca-4ecb-a55f-349a63d663b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805403854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2805403854
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.266591090
Short name T499
Test name
Test status
Simulation time 236663701 ps
CPU time 2.39 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:14 PM PDT 24
Peak memory 197704 kb
Host smart-38d69a7b-a2e9-4fe4-a36e-7eba9cde8e4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266591090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.266591090
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1258826658
Short name T515
Test name
Test status
Simulation time 90062428 ps
CPU time 0.85 seconds
Started May 28 01:10:05 PM PDT 24
Finished May 28 01:10:08 PM PDT 24
Peak memory 183012 kb
Host smart-63b947d5-a9ce-41be-b3a4-fc4b0cb096ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258826658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1258826658
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3495898612
Short name T535
Test name
Test status
Simulation time 151043944 ps
CPU time 0.91 seconds
Started May 28 01:09:58 PM PDT 24
Finished May 28 01:10:01 PM PDT 24
Peak memory 197044 kb
Host smart-d22d0190-8d68-465a-96db-37b949490fea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495898612 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3495898612
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2829274180
Short name T531
Test name
Test status
Simulation time 14870303 ps
CPU time 0.61 seconds
Started May 28 01:10:06 PM PDT 24
Finished May 28 01:10:08 PM PDT 24
Peak memory 182760 kb
Host smart-367e2e38-9cbb-4a61-9528-3b077f2bb7ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829274180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2829274180
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2908865429
Short name T460
Test name
Test status
Simulation time 14862922 ps
CPU time 0.58 seconds
Started May 28 01:10:05 PM PDT 24
Finished May 28 01:10:06 PM PDT 24
Peak memory 182544 kb
Host smart-d31efc93-b4e0-4967-8226-e16da925a8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908865429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2908865429
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.285248530
Short name T82
Test name
Test status
Simulation time 80936854 ps
CPU time 0.84 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:11 PM PDT 24
Peak memory 191712 kb
Host smart-6b8cd2da-9c70-4d75-99bb-d110aec2a865
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285248530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.285248530
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3124999263
Short name T484
Test name
Test status
Simulation time 57240241 ps
CPU time 2.61 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:16 PM PDT 24
Peak memory 197580 kb
Host smart-d6fc10db-ff59-444b-b471-40006e7708c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124999263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3124999263
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2262741365
Short name T28
Test name
Test status
Simulation time 72251474 ps
CPU time 1.1 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:14 PM PDT 24
Peak memory 183348 kb
Host smart-45a7cde1-a4ea-4e36-8a2e-2625e2032a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262741365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2262741365
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1538630608
Short name T70
Test name
Test status
Simulation time 14893704 ps
CPU time 0.71 seconds
Started May 28 01:09:45 PM PDT 24
Finished May 28 01:09:49 PM PDT 24
Peak memory 182652 kb
Host smart-dd366a2a-5be8-496d-ad1f-18ebfcb6619e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538630608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1538630608
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1743186230
Short name T64
Test name
Test status
Simulation time 75827625 ps
CPU time 1.41 seconds
Started May 28 01:09:40 PM PDT 24
Finished May 28 01:09:43 PM PDT 24
Peak memory 193752 kb
Host smart-e8f6d3bf-55cb-4dea-94d9-f8c19f05dfa9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743186230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1743186230
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3347388652
Short name T554
Test name
Test status
Simulation time 24284825 ps
CPU time 0.57 seconds
Started May 28 01:09:48 PM PDT 24
Finished May 28 01:09:53 PM PDT 24
Peak memory 182756 kb
Host smart-633690b9-31ef-47b8-8eaf-88e56c6dc80b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347388652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3347388652
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.862752785
Short name T32
Test name
Test status
Simulation time 23947979 ps
CPU time 0.72 seconds
Started May 28 01:09:42 PM PDT 24
Finished May 28 01:09:45 PM PDT 24
Peak memory 195316 kb
Host smart-03fcee5a-3c00-4d20-8e0f-e3a04d2dcf85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862752785 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.862752785
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4275595691
Short name T569
Test name
Test status
Simulation time 22718311 ps
CPU time 0.56 seconds
Started May 28 01:09:36 PM PDT 24
Finished May 28 01:09:40 PM PDT 24
Peak memory 182612 kb
Host smart-87fbc4f9-6269-455a-9517-daefbdbb5aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275595691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.4275595691
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.576877215
Short name T465
Test name
Test status
Simulation time 30497919 ps
CPU time 0.54 seconds
Started May 28 01:09:45 PM PDT 24
Finished May 28 01:09:50 PM PDT 24
Peak memory 182112 kb
Host smart-0d573987-6632-4e72-9618-fcfcfd86a416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576877215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.576877215
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1595192300
Short name T49
Test name
Test status
Simulation time 257066555 ps
CPU time 0.79 seconds
Started May 28 01:09:49 PM PDT 24
Finished May 28 01:09:54 PM PDT 24
Peak memory 191764 kb
Host smart-178b7925-49d9-48b6-8c27-15b6f30e0440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595192300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1595192300
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3431518049
Short name T545
Test name
Test status
Simulation time 218453906 ps
CPU time 0.91 seconds
Started May 28 01:09:44 PM PDT 24
Finished May 28 01:09:48 PM PDT 24
Peak memory 195800 kb
Host smart-14940687-f702-49c6-b891-c889c6cfe187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431518049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3431518049
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1854813679
Short name T88
Test name
Test status
Simulation time 88177667 ps
CPU time 1.08 seconds
Started May 28 01:09:44 PM PDT 24
Finished May 28 01:09:49 PM PDT 24
Peak memory 195124 kb
Host smart-0801d559-d6d4-4633-aca5-5c5a6e45dbba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854813679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1854813679
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2465219148
Short name T476
Test name
Test status
Simulation time 38006563 ps
CPU time 0.55 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:10 PM PDT 24
Peak memory 182608 kb
Host smart-4477f7da-a99b-4772-a0a4-77260cada8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465219148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2465219148
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3518129397
Short name T525
Test name
Test status
Simulation time 57052616 ps
CPU time 0.6 seconds
Started May 28 01:10:06 PM PDT 24
Finished May 28 01:10:09 PM PDT 24
Peak memory 182564 kb
Host smart-d1a4bcf7-0243-4d7e-8894-19ee93db07ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518129397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3518129397
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.598681357
Short name T511
Test name
Test status
Simulation time 14220581 ps
CPU time 0.54 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 182116 kb
Host smart-42970dc5-f29a-4281-b895-86be73bdbeb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598681357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.598681357
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.260552670
Short name T570
Test name
Test status
Simulation time 45708846 ps
CPU time 0.57 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:14 PM PDT 24
Peak memory 182672 kb
Host smart-5ebe3bfd-c31e-4d65-a4d3-091699b31dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260552670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.260552670
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.968892211
Short name T533
Test name
Test status
Simulation time 14567363 ps
CPU time 0.55 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 182516 kb
Host smart-f0e7b0b9-7f9b-4018-9de1-98746b0a586b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968892211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.968892211
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1843533479
Short name T563
Test name
Test status
Simulation time 62511224 ps
CPU time 0.58 seconds
Started May 28 01:10:05 PM PDT 24
Finished May 28 01:10:07 PM PDT 24
Peak memory 182616 kb
Host smart-d224803e-811c-40fc-aaa4-57b37b7f787c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843533479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1843533479
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3010943046
Short name T464
Test name
Test status
Simulation time 40420254 ps
CPU time 0.55 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:18 PM PDT 24
Peak memory 182624 kb
Host smart-1971af44-5425-497e-aeb9-28266764621a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010943046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3010943046
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.706339474
Short name T456
Test name
Test status
Simulation time 34172490 ps
CPU time 0.54 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:18 PM PDT 24
Peak memory 182492 kb
Host smart-9ed9da99-f46e-4f0a-935f-99a3395c21ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706339474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.706339474
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1410126589
Short name T526
Test name
Test status
Simulation time 41358600 ps
CPU time 0.57 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:10 PM PDT 24
Peak memory 182896 kb
Host smart-8bf0578b-7046-448b-b592-50784a165764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410126589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1410126589
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.285729812
Short name T534
Test name
Test status
Simulation time 16692663 ps
CPU time 0.59 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 182744 kb
Host smart-9d00c8d3-8150-4403-8f72-16dfd95b335a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285729812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.285729812
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.977261361
Short name T73
Test name
Test status
Simulation time 28965700 ps
CPU time 0.83 seconds
Started May 28 01:09:40 PM PDT 24
Finished May 28 01:09:43 PM PDT 24
Peak memory 192464 kb
Host smart-6f21ca7f-a0ac-450a-8003-e59b8940f97b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977261361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.977261361
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.93492069
Short name T557
Test name
Test status
Simulation time 122951311 ps
CPU time 2.24 seconds
Started May 28 01:09:48 PM PDT 24
Finished May 28 01:09:54 PM PDT 24
Peak memory 191236 kb
Host smart-4326c3e5-021a-49fb-90af-9f28bd08437a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93492069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ba
sh.93492069
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.954443256
Short name T561
Test name
Test status
Simulation time 16184275 ps
CPU time 0.56 seconds
Started May 28 01:09:37 PM PDT 24
Finished May 28 01:09:41 PM PDT 24
Peak memory 182720 kb
Host smart-db1eda1f-8514-4a0f-8aac-02cd579ef67d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954443256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.954443256
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.607794858
Short name T536
Test name
Test status
Simulation time 75403190 ps
CPU time 0.93 seconds
Started May 28 01:09:56 PM PDT 24
Finished May 28 01:10:00 PM PDT 24
Peak memory 197436 kb
Host smart-cbabbee4-5525-4ca1-b330-e47b899afd93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607794858 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.607794858
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2031583208
Short name T30
Test name
Test status
Simulation time 65052639 ps
CPU time 0.61 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:46 PM PDT 24
Peak memory 182664 kb
Host smart-44820076-8496-4f83-81f4-71de50919bbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031583208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2031583208
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2563758857
Short name T491
Test name
Test status
Simulation time 51676937 ps
CPU time 0.55 seconds
Started May 28 01:09:41 PM PDT 24
Finished May 28 01:09:43 PM PDT 24
Peak memory 182536 kb
Host smart-94526668-badc-46d5-8f64-24dd51118fb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563758857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2563758857
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3010044263
Short name T568
Test name
Test status
Simulation time 55111313 ps
CPU time 0.75 seconds
Started May 28 01:09:48 PM PDT 24
Finished May 28 01:09:53 PM PDT 24
Peak memory 193328 kb
Host smart-9e221705-7016-4003-b119-bf1c0a99ee83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010044263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3010044263
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2110255139
Short name T474
Test name
Test status
Simulation time 964380813 ps
CPU time 1.49 seconds
Started May 28 01:09:53 PM PDT 24
Finished May 28 01:10:00 PM PDT 24
Peak memory 197560 kb
Host smart-a6b224e7-0f05-457c-ac10-374891994405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110255139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2110255139
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3324390818
Short name T468
Test name
Test status
Simulation time 89580888 ps
CPU time 0.84 seconds
Started May 28 01:09:46 PM PDT 24
Finished May 28 01:09:52 PM PDT 24
Peak memory 192928 kb
Host smart-7f3896ef-c50d-47e2-a1b1-2c9b1aada090
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324390818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3324390818
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.585133122
Short name T556
Test name
Test status
Simulation time 18857552 ps
CPU time 0.59 seconds
Started May 28 01:10:14 PM PDT 24
Finished May 28 01:10:22 PM PDT 24
Peak memory 182556 kb
Host smart-2f17d8cd-62bc-46a3-9066-9c9ddf0a766a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585133122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.585133122
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1396569632
Short name T480
Test name
Test status
Simulation time 31996274 ps
CPU time 0.57 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:18 PM PDT 24
Peak memory 182572 kb
Host smart-b197e0ad-e460-48dd-a2a3-ccb13f0dcd6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396569632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1396569632
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2245679281
Short name T475
Test name
Test status
Simulation time 14832689 ps
CPU time 0.57 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:12 PM PDT 24
Peak memory 182516 kb
Host smart-08b3eaa0-9484-42ad-adae-1e7fd6c2a94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245679281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2245679281
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2416326368
Short name T503
Test name
Test status
Simulation time 14999492 ps
CPU time 0.57 seconds
Started May 28 01:10:11 PM PDT 24
Finished May 28 01:10:19 PM PDT 24
Peak memory 182208 kb
Host smart-b5c19e82-d5d5-42a1-93e8-1680b2cf6d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416326368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2416326368
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.403891337
Short name T513
Test name
Test status
Simulation time 21605513 ps
CPU time 0.56 seconds
Started May 28 01:10:05 PM PDT 24
Finished May 28 01:10:07 PM PDT 24
Peak memory 182648 kb
Host smart-c40671d0-2de6-4c0e-9f35-cbd1c3407b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403891337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.403891337
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3464226832
Short name T516
Test name
Test status
Simulation time 95390016 ps
CPU time 0.54 seconds
Started May 28 01:10:06 PM PDT 24
Finished May 28 01:10:08 PM PDT 24
Peak memory 181984 kb
Host smart-b1dc7047-ef84-4ada-b724-d86cb5832740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464226832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3464226832
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1663428207
Short name T502
Test name
Test status
Simulation time 32769735 ps
CPU time 0.54 seconds
Started May 28 01:10:16 PM PDT 24
Finished May 28 01:10:23 PM PDT 24
Peak memory 182000 kb
Host smart-e6eb1487-6000-4374-90ba-8862a5d27769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663428207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1663428207
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.319956724
Short name T485
Test name
Test status
Simulation time 112790769 ps
CPU time 0.56 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 182632 kb
Host smart-e2b49ff7-c5d8-41a3-b820-4bab7c5953de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319956724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.319956724
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2055300205
Short name T477
Test name
Test status
Simulation time 58955368 ps
CPU time 0.58 seconds
Started May 28 01:10:14 PM PDT 24
Finished May 28 01:10:22 PM PDT 24
Peak memory 182544 kb
Host smart-fd37124e-85f7-4026-b4a2-f08ba80ec84d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055300205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2055300205
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.674121218
Short name T497
Test name
Test status
Simulation time 39127544 ps
CPU time 0.56 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:13 PM PDT 24
Peak memory 182600 kb
Host smart-b4090ba1-0304-4905-b6b1-a162e9f69701
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674121218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.674121218
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.40516700
Short name T69
Test name
Test status
Simulation time 31850089 ps
CPU time 0.84 seconds
Started May 28 01:09:47 PM PDT 24
Finished May 28 01:09:52 PM PDT 24
Peak memory 192428 kb
Host smart-7fd886d4-ecca-4a92-b4dd-199e5bcfe008
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40516700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasi
ng.40516700
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3649143544
Short name T514
Test name
Test status
Simulation time 103081389 ps
CPU time 1.56 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:48 PM PDT 24
Peak memory 191068 kb
Host smart-0f0c96e3-aa28-4825-baf0-a2010341c1f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649143544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3649143544
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.844627910
Short name T84
Test name
Test status
Simulation time 29218938 ps
CPU time 0.54 seconds
Started May 28 01:09:45 PM PDT 24
Finished May 28 01:09:49 PM PDT 24
Peak memory 182632 kb
Host smart-95a313b4-2a61-4dde-9f4a-e199d64485ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844627910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.844627910
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3268197351
Short name T574
Test name
Test status
Simulation time 24198302 ps
CPU time 0.61 seconds
Started May 28 01:09:51 PM PDT 24
Finished May 28 01:09:56 PM PDT 24
Peak memory 192908 kb
Host smart-b245366c-88bd-4e0c-b586-bd1b98fdf0c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268197351 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3268197351
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1762368206
Short name T527
Test name
Test status
Simulation time 29621777 ps
CPU time 0.55 seconds
Started May 28 01:09:52 PM PDT 24
Finished May 28 01:09:58 PM PDT 24
Peak memory 182356 kb
Host smart-6d042843-3fb7-4676-bd86-b2a74c725e8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762368206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1762368206
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.549123000
Short name T461
Test name
Test status
Simulation time 23855253 ps
CPU time 0.55 seconds
Started May 28 01:09:42 PM PDT 24
Finished May 28 01:09:43 PM PDT 24
Peak memory 182112 kb
Host smart-fbce173d-3bb6-40ec-ae7d-f92042a5a21e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549123000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.549123000
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2058636285
Short name T77
Test name
Test status
Simulation time 16435049 ps
CPU time 0.77 seconds
Started May 28 01:09:52 PM PDT 24
Finished May 28 01:09:57 PM PDT 24
Peak memory 192004 kb
Host smart-e1469183-1e13-46ce-95a7-30cadebe484e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058636285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2058636285
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.285626644
Short name T478
Test name
Test status
Simulation time 58236623 ps
CPU time 1.22 seconds
Started May 28 01:09:47 PM PDT 24
Finished May 28 01:09:53 PM PDT 24
Peak memory 197548 kb
Host smart-522232ff-a17a-4e91-8f86-24ea066a8e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285626644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.285626644
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3029317278
Short name T576
Test name
Test status
Simulation time 557792687 ps
CPU time 1.38 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:48 PM PDT 24
Peak memory 195444 kb
Host smart-3ffe58bc-8816-4801-8a48-01a7661bafd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029317278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3029317278
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2025773668
Short name T538
Test name
Test status
Simulation time 24116369 ps
CPU time 0.56 seconds
Started May 28 01:10:03 PM PDT 24
Finished May 28 01:10:05 PM PDT 24
Peak memory 182560 kb
Host smart-545adcd8-0796-4c30-92de-76da088490c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025773668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2025773668
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2290277077
Short name T453
Test name
Test status
Simulation time 97412898 ps
CPU time 0.56 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:18 PM PDT 24
Peak memory 181984 kb
Host smart-099571ea-fa1a-464c-a637-7f4c8e46eee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290277077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2290277077
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.789879968
Short name T555
Test name
Test status
Simulation time 67081577 ps
CPU time 0.55 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 182604 kb
Host smart-596e3ac5-f96f-4a1e-abb8-3b63a6e3b1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789879968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.789879968
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4161941944
Short name T540
Test name
Test status
Simulation time 14558341 ps
CPU time 0.54 seconds
Started May 28 01:10:07 PM PDT 24
Finished May 28 01:10:10 PM PDT 24
Peak memory 182056 kb
Host smart-5f0c21fb-c0b6-44f6-9eae-a56c11d8eff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161941944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4161941944
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4208171462
Short name T483
Test name
Test status
Simulation time 18042360 ps
CPU time 0.54 seconds
Started May 28 01:10:10 PM PDT 24
Finished May 28 01:10:18 PM PDT 24
Peak memory 182040 kb
Host smart-fdc86378-a47d-446a-bde5-aa23bb7885cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208171462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4208171462
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1766843357
Short name T490
Test name
Test status
Simulation time 48346358 ps
CPU time 0.56 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 182508 kb
Host smart-d3de6572-9189-4f51-b65b-cc5716e9c7f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766843357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1766843357
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1440105526
Short name T509
Test name
Test status
Simulation time 15694236 ps
CPU time 0.55 seconds
Started May 28 01:10:18 PM PDT 24
Finished May 28 01:10:24 PM PDT 24
Peak memory 182196 kb
Host smart-97451c0a-3abc-4061-bbfb-662c1f072fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440105526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1440105526
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2990774399
Short name T552
Test name
Test status
Simulation time 23562251 ps
CPU time 0.54 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:15 PM PDT 24
Peak memory 182144 kb
Host smart-f2ad2940-6bbd-4863-a941-61d76872d4e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990774399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2990774399
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3359844217
Short name T452
Test name
Test status
Simulation time 20787777 ps
CPU time 0.53 seconds
Started May 28 01:10:08 PM PDT 24
Finished May 28 01:10:14 PM PDT 24
Peak memory 182000 kb
Host smart-fa81f523-32ac-4034-a1c5-9755b4167ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359844217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3359844217
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2970492644
Short name T549
Test name
Test status
Simulation time 29916538 ps
CPU time 0.54 seconds
Started May 28 01:10:09 PM PDT 24
Finished May 28 01:10:16 PM PDT 24
Peak memory 182620 kb
Host smart-fa0e7d08-483d-4182-8398-eda0cbb3f12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970492644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2970492644
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3111709292
Short name T467
Test name
Test status
Simulation time 97230883 ps
CPU time 0.88 seconds
Started May 28 01:09:44 PM PDT 24
Finished May 28 01:09:49 PM PDT 24
Peak memory 197248 kb
Host smart-6c57b783-5090-4bb4-890d-53e128863d81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111709292 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3111709292
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3441439125
Short name T81
Test name
Test status
Simulation time 55221830 ps
CPU time 0.61 seconds
Started May 28 01:09:52 PM PDT 24
Finished May 28 01:09:57 PM PDT 24
Peak memory 182988 kb
Host smart-c4696e6c-90cc-4d13-aa04-4c1455298f42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441439125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3441439125
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.324821810
Short name T559
Test name
Test status
Simulation time 18206127 ps
CPU time 0.58 seconds
Started May 28 01:09:40 PM PDT 24
Finished May 28 01:09:42 PM PDT 24
Peak memory 182492 kb
Host smart-a13f319e-573d-4279-bd6d-ce83595a75c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324821810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.324821810
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2513526696
Short name T31
Test name
Test status
Simulation time 38951803 ps
CPU time 0.78 seconds
Started May 28 01:09:48 PM PDT 24
Finished May 28 01:09:53 PM PDT 24
Peak memory 193328 kb
Host smart-6679fc94-a875-4e4e-8cb4-8688519d9292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513526696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2513526696
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.970143295
Short name T521
Test name
Test status
Simulation time 364426415 ps
CPU time 1.85 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:47 PM PDT 24
Peak memory 197544 kb
Host smart-62b94ba9-d6e6-4f93-8a15-170d17040609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970143295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.970143295
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1328408736
Short name T507
Test name
Test status
Simulation time 91436566 ps
CPU time 0.91 seconds
Started May 28 01:09:34 PM PDT 24
Finished May 28 01:09:38 PM PDT 24
Peak memory 193916 kb
Host smart-10a1dfeb-c01e-47a2-a9d8-0aa3694b2a37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328408736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1328408736
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3489589870
Short name T524
Test name
Test status
Simulation time 19918629 ps
CPU time 0.65 seconds
Started May 28 01:09:45 PM PDT 24
Finished May 28 01:09:50 PM PDT 24
Peak memory 194100 kb
Host smart-42166648-c373-4724-965e-588969d45fb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489589870 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3489589870
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.837393535
Short name T72
Test name
Test status
Simulation time 45460071 ps
CPU time 0.54 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:47 PM PDT 24
Peak memory 182628 kb
Host smart-db9fc599-5248-475a-ade9-c84c10c84d25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837393535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.837393535
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2815103867
Short name T494
Test name
Test status
Simulation time 14272149 ps
CPU time 0.59 seconds
Started May 28 01:09:52 PM PDT 24
Finished May 28 01:09:58 PM PDT 24
Peak memory 182572 kb
Host smart-1b766da0-edb2-4bb4-9f06-c70e736b3a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815103867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2815103867
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.984228648
Short name T76
Test name
Test status
Simulation time 33982170 ps
CPU time 0.74 seconds
Started May 28 01:09:54 PM PDT 24
Finished May 28 01:09:59 PM PDT 24
Peak memory 193172 kb
Host smart-c2521c07-635f-4989-ad27-a06b5fc3b27a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984228648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.984228648
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3132998569
Short name T505
Test name
Test status
Simulation time 767818036 ps
CPU time 3.23 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:50 PM PDT 24
Peak memory 197672 kb
Host smart-b5fbed84-ee0e-4b8f-87ec-53529471fb2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132998569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3132998569
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2889279860
Short name T562
Test name
Test status
Simulation time 96404994 ps
CPU time 1.38 seconds
Started May 28 01:09:41 PM PDT 24
Finished May 28 01:09:44 PM PDT 24
Peak memory 183288 kb
Host smart-9927352e-d26e-40f8-bf87-4354686f3f07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889279860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2889279860
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3482220191
Short name T486
Test name
Test status
Simulation time 16312430 ps
CPU time 0.63 seconds
Started May 28 01:09:50 PM PDT 24
Finished May 28 01:09:55 PM PDT 24
Peak memory 193252 kb
Host smart-87b5c96f-aab9-4227-9a62-ab262e3dbfdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482220191 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3482220191
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1610612153
Short name T71
Test name
Test status
Simulation time 12044529 ps
CPU time 0.55 seconds
Started May 28 01:09:34 PM PDT 24
Finished May 28 01:09:38 PM PDT 24
Peak memory 182580 kb
Host smart-0ed4b484-6d71-4422-a552-036aef0e5de5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610612153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1610612153
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1380239636
Short name T496
Test name
Test status
Simulation time 21198886 ps
CPU time 0.58 seconds
Started May 28 01:09:39 PM PDT 24
Finished May 28 01:09:42 PM PDT 24
Peak memory 182600 kb
Host smart-f273e9ab-1196-47f9-8f25-de2638b0c568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380239636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1380239636
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2945737062
Short name T558
Test name
Test status
Simulation time 28443776 ps
CPU time 0.71 seconds
Started May 28 01:09:44 PM PDT 24
Finished May 28 01:09:48 PM PDT 24
Peak memory 193384 kb
Host smart-685ce953-adda-4d22-982b-aa6ce307feb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945737062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2945737062
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.426756680
Short name T495
Test name
Test status
Simulation time 34353284 ps
CPU time 1.69 seconds
Started May 28 01:09:44 PM PDT 24
Finished May 28 01:09:49 PM PDT 24
Peak memory 191288 kb
Host smart-d083bc57-7859-4b78-8645-9c4e00b20e26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426756680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.426756680
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3710641864
Short name T87
Test name
Test status
Simulation time 203162350 ps
CPU time 1.29 seconds
Started May 28 01:09:48 PM PDT 24
Finished May 28 01:09:55 PM PDT 24
Peak memory 183148 kb
Host smart-97559345-d4f1-4e6a-bdff-e07e9c2e8a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710641864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3710641864
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1918342405
Short name T462
Test name
Test status
Simulation time 70375804 ps
CPU time 0.67 seconds
Started May 28 01:09:46 PM PDT 24
Finished May 28 01:09:51 PM PDT 24
Peak memory 193464 kb
Host smart-2a9d249a-610f-432f-96fd-b6445a828f1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918342405 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1918342405
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.809152827
Short name T83
Test name
Test status
Simulation time 25264768 ps
CPU time 0.57 seconds
Started May 28 01:09:53 PM PDT 24
Finished May 28 01:09:58 PM PDT 24
Peak memory 182636 kb
Host smart-9f8c0ef7-7980-483f-b3a7-65a27a372be9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809152827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.809152827
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2332809555
Short name T463
Test name
Test status
Simulation time 11980136 ps
CPU time 0.54 seconds
Started May 28 01:09:46 PM PDT 24
Finished May 28 01:09:51 PM PDT 24
Peak memory 182312 kb
Host smart-8aa1c744-dff1-4173-8192-804bb1218f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332809555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2332809555
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1372791515
Short name T78
Test name
Test status
Simulation time 57968608 ps
CPU time 0.82 seconds
Started May 28 01:09:43 PM PDT 24
Finished May 28 01:09:46 PM PDT 24
Peak memory 193240 kb
Host smart-6b95609d-1ea8-4f76-b5f6-b1b0e2f0028b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372791515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1372791515
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3140436936
Short name T546
Test name
Test status
Simulation time 129429749 ps
CPU time 1.82 seconds
Started May 28 01:10:00 PM PDT 24
Finished May 28 01:10:03 PM PDT 24
Peak memory 197544 kb
Host smart-1f5f833a-a398-47dd-99c8-9db9466772f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140436936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3140436936
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2035292231
Short name T466
Test name
Test status
Simulation time 214926570 ps
CPU time 0.85 seconds
Started May 28 01:09:50 PM PDT 24
Finished May 28 01:09:56 PM PDT 24
Peak memory 183196 kb
Host smart-282a3902-93ad-46bc-9a39-e3780ba7329a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035292231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2035292231
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.607050877
Short name T553
Test name
Test status
Simulation time 72802750 ps
CPU time 1.76 seconds
Started May 28 01:09:40 PM PDT 24
Finished May 28 01:09:44 PM PDT 24
Peak memory 197544 kb
Host smart-d90a15fa-6a43-468f-8161-dedb868c7c90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607050877 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.607050877
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3917828348
Short name T501
Test name
Test status
Simulation time 35379103 ps
CPU time 0.57 seconds
Started May 28 01:09:50 PM PDT 24
Finished May 28 01:09:55 PM PDT 24
Peak memory 182636 kb
Host smart-95df6ff9-c9a1-4b20-8448-42c1adc98580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917828348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3917828348
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2574318919
Short name T504
Test name
Test status
Simulation time 13571230 ps
CPU time 0.56 seconds
Started May 28 01:09:52 PM PDT 24
Finished May 28 01:09:58 PM PDT 24
Peak memory 181892 kb
Host smart-25af96e3-d17d-460f-9063-2986b3d384c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574318919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2574318919
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4207822008
Short name T508
Test name
Test status
Simulation time 29623438 ps
CPU time 0.64 seconds
Started May 28 01:09:48 PM PDT 24
Finished May 28 01:09:53 PM PDT 24
Peak memory 191984 kb
Host smart-afd32a24-bc2a-4e9c-8dac-d85495b11885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207822008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.4207822008
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.51904360
Short name T547
Test name
Test status
Simulation time 117598701 ps
CPU time 2.47 seconds
Started May 28 01:09:42 PM PDT 24
Finished May 28 01:09:45 PM PDT 24
Peak memory 197520 kb
Host smart-d88f5a0d-8b4a-4154-8a34-e26afa92fb8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51904360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.51904360
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2691812305
Short name T522
Test name
Test status
Simulation time 88524431 ps
CPU time 1.04 seconds
Started May 28 01:09:45 PM PDT 24
Finished May 28 01:09:49 PM PDT 24
Peak memory 194984 kb
Host smart-eacb7830-c65b-4cba-843f-143126edcb5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691812305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2691812305
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4146497169
Short name T414
Test name
Test status
Simulation time 612270879924 ps
CPU time 291.12 seconds
Started May 28 01:12:22 PM PDT 24
Finished May 28 01:17:15 PM PDT 24
Peak memory 182568 kb
Host smart-a59abd8c-63d6-4667-9b40-3a446e584c21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146497169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4146497169
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.873614122
Short name T370
Test name
Test status
Simulation time 107259494383 ps
CPU time 68.61 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:13:33 PM PDT 24
Peak memory 182584 kb
Host smart-a2261b6b-7651-40a8-9067-7020439910f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873614122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.873614122
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.275997864
Short name T367
Test name
Test status
Simulation time 148597468681 ps
CPU time 203.22 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:15:48 PM PDT 24
Peak memory 182400 kb
Host smart-c38100b7-58b3-4c2a-a8a2-bc917b0ed9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275997864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.275997864
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.229340443
Short name T420
Test name
Test status
Simulation time 70497133 ps
CPU time 0.62 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:12:26 PM PDT 24
Peak memory 182340 kb
Host smart-5fe97f7c-8268-44f7-9fb6-7f58a01825fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229340443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.229340443
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1347122237
Short name T16
Test name
Test status
Simulation time 118805930 ps
CPU time 0.84 seconds
Started May 28 01:12:07 PM PDT 24
Finished May 28 01:12:14 PM PDT 24
Peak memory 213116 kb
Host smart-2e51e603-156d-4f4f-ba48-4bf6e3e3cb11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347122237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1347122237
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.454849283
Short name T188
Test name
Test status
Simulation time 938571721560 ps
CPU time 197.07 seconds
Started May 28 01:12:28 PM PDT 24
Finished May 28 01:15:48 PM PDT 24
Peak memory 182640 kb
Host smart-1b0ee000-71a1-4bac-9f40-ecb2e044897d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454849283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.454849283
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2925801096
Short name T384
Test name
Test status
Simulation time 142006553031 ps
CPU time 216.06 seconds
Started May 28 01:12:25 PM PDT 24
Finished May 28 01:16:04 PM PDT 24
Peak memory 182584 kb
Host smart-f0ffd3cc-5b72-4b4e-824f-14d92dd4cac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925801096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2925801096
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3321133900
Short name T173
Test name
Test status
Simulation time 219192771665 ps
CPU time 372.83 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:18:38 PM PDT 24
Peak memory 190808 kb
Host smart-eddc09ab-5901-40a5-aa6e-0646a9de6362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321133900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3321133900
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3306467194
Short name T377
Test name
Test status
Simulation time 43063941188 ps
CPU time 67.8 seconds
Started May 28 01:12:25 PM PDT 24
Finished May 28 01:13:35 PM PDT 24
Peak memory 190844 kb
Host smart-879125b8-f23c-49a9-a55a-a401cc7cc2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306467194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3306467194
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1314777795
Short name T214
Test name
Test status
Simulation time 122779098530 ps
CPU time 299.6 seconds
Started May 28 01:13:13 PM PDT 24
Finished May 28 01:18:18 PM PDT 24
Peak memory 194240 kb
Host smart-7593c157-9ec1-49a4-9529-05047a270f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314777795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1314777795
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.157072743
Short name T408
Test name
Test status
Simulation time 316135743138 ps
CPU time 1016.4 seconds
Started May 28 01:13:25 PM PDT 24
Finished May 28 01:30:24 PM PDT 24
Peak memory 190768 kb
Host smart-048a4a9f-bbcb-4abc-a5b1-00f894667787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157072743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.157072743
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1281739102
Short name T287
Test name
Test status
Simulation time 81495180827 ps
CPU time 289.46 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:18:02 PM PDT 24
Peak memory 190764 kb
Host smart-0ec92bdb-5c01-4c4b-9e11-43003a2f1994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281739102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1281739102
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2022636389
Short name T212
Test name
Test status
Simulation time 280439261965 ps
CPU time 260.42 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:17:43 PM PDT 24
Peak memory 190832 kb
Host smart-51961a1f-164d-4e76-b17b-7b2c30fc5e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022636389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2022636389
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1656674840
Short name T179
Test name
Test status
Simulation time 191047199176 ps
CPU time 785.71 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:26:25 PM PDT 24
Peak memory 192856 kb
Host smart-5c550569-ed5d-495d-a840-8a8bc0708999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656674840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1656674840
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3901440145
Short name T317
Test name
Test status
Simulation time 85385777240 ps
CPU time 148.54 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:15:54 PM PDT 24
Peak memory 190796 kb
Host smart-a125234c-6ace-4ad2-a5eb-4eccb05da4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901440145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3901440145
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3949936267
Short name T164
Test name
Test status
Simulation time 159477434483 ps
CPU time 137.14 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:15:38 PM PDT 24
Peak memory 190708 kb
Host smart-f017ce3d-25e3-4e21-b461-ddb6f4a051d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949936267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3949936267
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1635263366
Short name T303
Test name
Test status
Simulation time 133105358018 ps
CPU time 76.28 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:14:32 PM PDT 24
Peak memory 190764 kb
Host smart-56691439-c48b-49e9-97a6-336b45ac305a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635263366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1635263366
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1175655955
Short name T409
Test name
Test status
Simulation time 145709340362 ps
CPU time 269.67 seconds
Started May 28 01:12:25 PM PDT 24
Finished May 28 01:16:57 PM PDT 24
Peak memory 182572 kb
Host smart-3761646d-db5c-4b10-95cd-1a110ce9cd83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175655955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1175655955
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2910773040
Short name T366
Test name
Test status
Simulation time 45904594491 ps
CPU time 32.84 seconds
Started May 28 01:12:24 PM PDT 24
Finished May 28 01:12:59 PM PDT 24
Peak memory 182648 kb
Host smart-1e469125-2584-49eb-9d7b-745f11abd53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910773040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2910773040
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.588007136
Short name T132
Test name
Test status
Simulation time 91381388452 ps
CPU time 78.48 seconds
Started May 28 01:12:21 PM PDT 24
Finished May 28 01:13:41 PM PDT 24
Peak memory 190740 kb
Host smart-36c013b1-825a-4576-8cf5-e1956e020544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588007136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.588007136
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4264779758
Short name T142
Test name
Test status
Simulation time 96640292583 ps
CPU time 102.83 seconds
Started May 28 01:12:26 PM PDT 24
Finished May 28 01:14:16 PM PDT 24
Peak memory 182640 kb
Host smart-5ebf3600-a8da-49b9-ad76-22d58df03c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264779758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4264779758
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.390593183
Short name T101
Test name
Test status
Simulation time 336697403159 ps
CPU time 275.28 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:17:51 PM PDT 24
Peak memory 190832 kb
Host smart-12937959-b64e-44f9-a3e8-21fa6a049f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390593183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.390593183
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3596404735
Short name T277
Test name
Test status
Simulation time 525149481973 ps
CPU time 292.62 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:18:16 PM PDT 24
Peak memory 190796 kb
Host smart-eb69d83c-e30e-4ad5-aac9-918a3c9ea9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596404735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3596404735
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1590663634
Short name T41
Test name
Test status
Simulation time 174521261934 ps
CPU time 68.79 seconds
Started May 28 01:13:13 PM PDT 24
Finished May 28 01:14:26 PM PDT 24
Peak memory 182564 kb
Host smart-af8458de-ca79-422a-8d2f-c8348c95e676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590663634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1590663634
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2108997816
Short name T191
Test name
Test status
Simulation time 1005871829006 ps
CPU time 601.66 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:23:23 PM PDT 24
Peak memory 190700 kb
Host smart-6387244b-3109-4eb9-8237-af9a03555e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108997816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2108997816
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1983898896
Short name T318
Test name
Test status
Simulation time 82915426442 ps
CPU time 83.48 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:14:43 PM PDT 24
Peak memory 182508 kb
Host smart-48901dfa-cffd-4206-a155-f82f76a179c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983898896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1983898896
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1978573478
Short name T331
Test name
Test status
Simulation time 131626651256 ps
CPU time 116.26 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:15:17 PM PDT 24
Peak memory 190616 kb
Host smart-60871e63-5794-4115-b9f4-87c4f2be50a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978573478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1978573478
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.53012028
Short name T258
Test name
Test status
Simulation time 9775365400 ps
CPU time 15.17 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:13:41 PM PDT 24
Peak memory 182564 kb
Host smart-d7de22b0-25bc-46f1-ad7e-3970b608ebac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53012028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.53012028
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1429356507
Short name T328
Test name
Test status
Simulation time 299417488319 ps
CPU time 347.88 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:19:07 PM PDT 24
Peak memory 190812 kb
Host smart-9dd46c29-00ba-4c70-913a-3fab332c32ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429356507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1429356507
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3124467605
Short name T205
Test name
Test status
Simulation time 17638833869 ps
CPU time 10.5 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:13:01 PM PDT 24
Peak memory 182636 kb
Host smart-63fd657f-effa-47f2-a625-25948f8c8c9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124467605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3124467605
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.229137556
Short name T387
Test name
Test status
Simulation time 219623462204 ps
CPU time 109.17 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:14:33 PM PDT 24
Peak memory 182572 kb
Host smart-76e216ca-97cd-4030-b429-0096c263cb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229137556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.229137556
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.601276583
Short name T291
Test name
Test status
Simulation time 89030162873 ps
CPU time 100.92 seconds
Started May 28 01:12:37 PM PDT 24
Finished May 28 01:14:19 PM PDT 24
Peak memory 194892 kb
Host smart-805554b3-3720-407a-89eb-ef0b8514b9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601276583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.601276583
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1154731977
Short name T247
Test name
Test status
Simulation time 149858131803 ps
CPU time 187.84 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:16:27 PM PDT 24
Peak memory 190772 kb
Host smart-eec9d5d1-1305-4665-b959-b7d453179dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154731977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1154731977
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.345680757
Short name T351
Test name
Test status
Simulation time 110747098367 ps
CPU time 186.63 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:16:30 PM PDT 24
Peak memory 182600 kb
Host smart-b840e5f9-3e73-4265-996f-e4f6dbd9bcca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345680757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.345680757
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.966395047
Short name T195
Test name
Test status
Simulation time 355506821277 ps
CPU time 135.23 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:15:36 PM PDT 24
Peak memory 192908 kb
Host smart-5c5b52a3-92ce-41d4-98bd-04145fa295a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966395047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.966395047
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.332370196
Short name T298
Test name
Test status
Simulation time 11898296717 ps
CPU time 12.05 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:13:34 PM PDT 24
Peak memory 182504 kb
Host smart-73026baf-61cf-407d-b303-85bd79cc1dab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332370196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.332370196
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.312082886
Short name T304
Test name
Test status
Simulation time 50807711703 ps
CPU time 439.17 seconds
Started May 28 01:13:26 PM PDT 24
Finished May 28 01:20:47 PM PDT 24
Peak memory 182636 kb
Host smart-3e5fbe78-73a7-402c-afb4-0d1e9c5cf270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312082886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.312082886
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2367189020
Short name T282
Test name
Test status
Simulation time 136621355947 ps
CPU time 187.99 seconds
Started May 28 01:13:04 PM PDT 24
Finished May 28 01:16:15 PM PDT 24
Peak memory 193132 kb
Host smart-aabd6371-b459-4b7f-ac6c-5bd655409411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367189020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2367189020
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1945982970
Short name T242
Test name
Test status
Simulation time 435528638510 ps
CPU time 1280.66 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:34:37 PM PDT 24
Peak memory 190700 kb
Host smart-c39d03a8-fe75-4e25-8d46-47767a958014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945982970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1945982970
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4221104654
Short name T177
Test name
Test status
Simulation time 199831305157 ps
CPU time 249.32 seconds
Started May 28 01:13:22 PM PDT 24
Finished May 28 01:17:36 PM PDT 24
Peak memory 190832 kb
Host smart-76086181-24e5-436e-a9d3-402557712bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221104654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4221104654
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2926360261
Short name T386
Test name
Test status
Simulation time 106667408284 ps
CPU time 160.88 seconds
Started May 28 01:12:35 PM PDT 24
Finished May 28 01:15:17 PM PDT 24
Peak memory 182580 kb
Host smart-39bd4583-c878-4b01-8fbe-0c27f00634ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926360261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2926360261
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2979817632
Short name T18
Test name
Test status
Simulation time 4779510543 ps
CPU time 9.35 seconds
Started May 28 01:12:45 PM PDT 24
Finished May 28 01:12:58 PM PDT 24
Peak memory 182620 kb
Host smart-5653c04b-cc2c-4928-a511-c0274cc2454d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979817632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2979817632
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2907736609
Short name T430
Test name
Test status
Simulation time 62528560142 ps
CPU time 99.91 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:14:23 PM PDT 24
Peak memory 182588 kb
Host smart-343cb28b-08b1-4a87-be72-2cf44b846bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907736609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2907736609
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.4134938947
Short name T37
Test name
Test status
Simulation time 49414765554 ps
CPU time 411.84 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:19:34 PM PDT 24
Peak memory 197220 kb
Host smart-ec934564-92a4-4521-804c-7d2bb7f9f19d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134938947 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.4134938947
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1255024855
Short name T125
Test name
Test status
Simulation time 846768478313 ps
CPU time 443.69 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:20:45 PM PDT 24
Peak memory 190756 kb
Host smart-ad4f5c1b-2cc6-49a6-b80a-f02762aaee3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255024855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1255024855
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2464510484
Short name T329
Test name
Test status
Simulation time 288620941473 ps
CPU time 202.91 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:16:42 PM PDT 24
Peak memory 190684 kb
Host smart-606b3157-0fa2-48a0-affb-662c42679aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464510484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2464510484
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2123393338
Short name T295
Test name
Test status
Simulation time 731806947729 ps
CPU time 398.08 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:19:58 PM PDT 24
Peak memory 190756 kb
Host smart-222d6302-beb3-41e6-b46c-fcc296c94537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123393338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2123393338
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.321343275
Short name T217
Test name
Test status
Simulation time 810251563867 ps
CPU time 1577.66 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:39:39 PM PDT 24
Peak memory 190816 kb
Host smart-6abd57ec-1fa1-4352-a299-a6643a550bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321343275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.321343275
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2336056159
Short name T300
Test name
Test status
Simulation time 15617023216 ps
CPU time 28.76 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:13:54 PM PDT 24
Peak memory 182596 kb
Host smart-11205174-2720-4bdd-81b9-ea09141421cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336056159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2336056159
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1442035960
Short name T401
Test name
Test status
Simulation time 21452829596 ps
CPU time 222.73 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:17:03 PM PDT 24
Peak memory 182612 kb
Host smart-80aa0524-c304-412e-9dc8-2c2891471268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442035960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1442035960
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2283092647
Short name T184
Test name
Test status
Simulation time 223635245896 ps
CPU time 554.15 seconds
Started May 28 01:13:03 PM PDT 24
Finished May 28 01:22:21 PM PDT 24
Peak memory 190832 kb
Host smart-d6c7bc4d-af57-4d90-923f-2955640bc000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283092647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2283092647
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1474348883
Short name T292
Test name
Test status
Simulation time 572026025848 ps
CPU time 306.98 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:17:48 PM PDT 24
Peak memory 182584 kb
Host smart-0acfc0fd-eee8-4cf2-9496-a60166f439c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474348883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1474348883
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3515612972
Short name T443
Test name
Test status
Simulation time 297135115145 ps
CPU time 222.15 seconds
Started May 28 01:12:50 PM PDT 24
Finished May 28 01:16:35 PM PDT 24
Peak memory 182568 kb
Host smart-2f0980ef-2b24-4eca-83e7-0f531560d067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515612972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3515612972
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2846218945
Short name T141
Test name
Test status
Simulation time 39932371755 ps
CPU time 126.91 seconds
Started May 28 01:12:43 PM PDT 24
Finished May 28 01:14:54 PM PDT 24
Peak memory 194244 kb
Host smart-1b4e2970-4f2a-431d-b833-8ff2ebd61c6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846218945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2846218945
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3983664520
Short name T391
Test name
Test status
Simulation time 104371384 ps
CPU time 1.57 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:12:44 PM PDT 24
Peak memory 182516 kb
Host smart-aafab52c-df12-4173-8939-5c26b66723ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983664520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3983664520
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4223910332
Short name T374
Test name
Test status
Simulation time 69217292759 ps
CPU time 91.07 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:14:22 PM PDT 24
Peak memory 182636 kb
Host smart-b589bce8-df43-4be1-9d5a-cd757f006173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223910332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4223910332
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.354509074
Short name T309
Test name
Test status
Simulation time 80103073905 ps
CPU time 425.2 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 190800 kb
Host smart-886e9b06-d52d-4df0-bca8-a9e9d0dfa28d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354509074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.354509074
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.285890647
Short name T147
Test name
Test status
Simulation time 80734823141 ps
CPU time 447.18 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:20:49 PM PDT 24
Peak memory 190768 kb
Host smart-7b1bac8e-f7fb-45cc-a0c0-b02d1bff8a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285890647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.285890647
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3734687297
Short name T310
Test name
Test status
Simulation time 54013491111 ps
CPU time 42.79 seconds
Started May 28 01:13:12 PM PDT 24
Finished May 28 01:14:00 PM PDT 24
Peak memory 182568 kb
Host smart-2839011e-a58a-4dde-a807-24f1981cafd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734687297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3734687297
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1127733700
Short name T338
Test name
Test status
Simulation time 49062029723 ps
CPU time 82.56 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:14:43 PM PDT 24
Peak memory 182508 kb
Host smart-daa101ba-1732-4625-a99b-1087b7c5ab45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127733700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1127733700
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2080551767
Short name T299
Test name
Test status
Simulation time 177787687989 ps
CPU time 91.91 seconds
Started May 28 01:13:13 PM PDT 24
Finished May 28 01:14:49 PM PDT 24
Peak memory 190760 kb
Host smart-b96f0a5f-c619-4c6d-b3b0-16c2e442b1a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080551767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2080551767
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3204468550
Short name T106
Test name
Test status
Simulation time 58752147301 ps
CPU time 96.05 seconds
Started May 28 01:13:31 PM PDT 24
Finished May 28 01:15:09 PM PDT 24
Peak memory 194232 kb
Host smart-65961491-732a-43e6-bd00-9dcc2e1cfb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204468550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3204468550
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4139034895
Short name T405
Test name
Test status
Simulation time 74176413650 ps
CPU time 124.56 seconds
Started May 28 01:13:31 PM PDT 24
Finished May 28 01:15:38 PM PDT 24
Peak memory 190764 kb
Host smart-5570f159-c7f0-4f87-88f0-b3d419d9e4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139034895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4139034895
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3416457847
Short name T240
Test name
Test status
Simulation time 17021833619 ps
CPU time 10.33 seconds
Started May 28 01:12:34 PM PDT 24
Finished May 28 01:12:46 PM PDT 24
Peak memory 182660 kb
Host smart-e826ec57-6dcd-4f15-9662-f6b4ecf7bdc9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416457847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3416457847
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2802750331
Short name T368
Test name
Test status
Simulation time 506710361477 ps
CPU time 150.18 seconds
Started May 28 01:12:49 PM PDT 24
Finished May 28 01:15:22 PM PDT 24
Peak memory 182648 kb
Host smart-a84f3a09-3156-45e1-a27a-d58bb56e62ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802750331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2802750331
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3181739384
Short name T55
Test name
Test status
Simulation time 44124283203 ps
CPU time 25.5 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:13:07 PM PDT 24
Peak memory 182572 kb
Host smart-e00ce207-7692-4092-8bdb-edf6633fe351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181739384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3181739384
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.3346662117
Short name T413
Test name
Test status
Simulation time 146743222982 ps
CPU time 326.16 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:18:42 PM PDT 24
Peak memory 182484 kb
Host smart-1b260f3c-23f3-48ca-8742-d38fda50cfaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346662117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3346662117
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1557753748
Short name T290
Test name
Test status
Simulation time 173636072146 ps
CPU time 300.8 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:18:30 PM PDT 24
Peak memory 190764 kb
Host smart-97b1480a-d091-4ced-8f22-4baa5988559a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557753748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1557753748
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1581888682
Short name T3
Test name
Test status
Simulation time 613606714385 ps
CPU time 306 seconds
Started May 28 01:13:28 PM PDT 24
Finished May 28 01:18:34 PM PDT 24
Peak memory 190764 kb
Host smart-b342a1e7-8558-49ed-8c8d-83a497ba4b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581888682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1581888682
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1150992823
Short name T397
Test name
Test status
Simulation time 221560717394 ps
CPU time 49.89 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:14:09 PM PDT 24
Peak memory 182564 kb
Host smart-a9d490e6-285e-48c0-abce-77d1aa12991e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150992823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1150992823
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3116454317
Short name T107
Test name
Test status
Simulation time 263378213146 ps
CPU time 306.8 seconds
Started May 28 01:13:18 PM PDT 24
Finished May 28 01:18:30 PM PDT 24
Peak memory 190756 kb
Host smart-7fded9e8-38a9-4016-af80-a8d08d1569b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116454317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3116454317
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2160807706
Short name T423
Test name
Test status
Simulation time 873159940452 ps
CPU time 167.02 seconds
Started May 28 01:12:49 PM PDT 24
Finished May 28 01:15:39 PM PDT 24
Peak memory 182648 kb
Host smart-67bed80d-91fe-4f19-8efc-e522a69772f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160807706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2160807706
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.7572311
Short name T449
Test name
Test status
Simulation time 71613198100 ps
CPU time 28.33 seconds
Started May 28 01:12:38 PM PDT 24
Finished May 28 01:13:08 PM PDT 24
Peak memory 182588 kb
Host smart-7457ca04-8857-421a-8cb3-f02a719882fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7572311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.7572311
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.790534172
Short name T435
Test name
Test status
Simulation time 157240666 ps
CPU time 0.7 seconds
Started May 28 01:12:44 PM PDT 24
Finished May 28 01:12:49 PM PDT 24
Peak memory 182428 kb
Host smart-09bb780f-7a2f-42e0-91ac-922a408d32d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790534172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.790534172
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2807910779
Short name T103
Test name
Test status
Simulation time 543571057296 ps
CPU time 429.52 seconds
Started May 28 01:12:48 PM PDT 24
Finished May 28 01:20:02 PM PDT 24
Peak memory 193484 kb
Host smart-c6109b5f-ca97-4e36-8b1b-2fdbb458cb22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807910779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2807910779
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.1011708610
Short name T426
Test name
Test status
Simulation time 509656529164 ps
CPU time 716.57 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:25:28 PM PDT 24
Peak memory 190756 kb
Host smart-6b6859cf-15af-413d-98c5-8aff2e24eca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011708610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1011708610
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3748577993
Short name T201
Test name
Test status
Simulation time 153762639204 ps
CPU time 1242.86 seconds
Started May 28 01:13:37 PM PDT 24
Finished May 28 01:34:21 PM PDT 24
Peak memory 190824 kb
Host smart-b3ad9fa2-c273-49ec-8b38-114dd927dab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748577993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3748577993
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1345026688
Short name T349
Test name
Test status
Simulation time 5770755457 ps
CPU time 3.12 seconds
Started May 28 01:13:41 PM PDT 24
Finished May 28 01:13:45 PM PDT 24
Peak memory 182548 kb
Host smart-c2dbba3a-9086-4c3b-b41b-e6a54c4616b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345026688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1345026688
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1251470122
Short name T394
Test name
Test status
Simulation time 125564153726 ps
CPU time 70.65 seconds
Started May 28 01:13:47 PM PDT 24
Finished May 28 01:15:00 PM PDT 24
Peak memory 182616 kb
Host smart-322eea59-5c3e-4ce8-b0b7-16cf9014b725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251470122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1251470122
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3202759182
Short name T22
Test name
Test status
Simulation time 56258733663 ps
CPU time 157.95 seconds
Started May 28 01:13:46 PM PDT 24
Finished May 28 01:16:25 PM PDT 24
Peak memory 190824 kb
Host smart-3c15fae8-b13a-4aa0-89f5-3bbf6282e8fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202759182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3202759182
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3998354184
Short name T209
Test name
Test status
Simulation time 13844350887 ps
CPU time 31.09 seconds
Started May 28 01:13:35 PM PDT 24
Finished May 28 01:14:07 PM PDT 24
Peak memory 182632 kb
Host smart-2178ee68-aeae-47c2-8342-b8553f8eaabf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998354184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3998354184
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1139926801
Short name T373
Test name
Test status
Simulation time 260860993575 ps
CPU time 141.33 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:15:13 PM PDT 24
Peak memory 182648 kb
Host smart-239373fa-52cb-4602-af06-448cd8c13284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139926801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1139926801
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3436515223
Short name T236
Test name
Test status
Simulation time 234679025301 ps
CPU time 519.77 seconds
Started May 28 01:12:49 PM PDT 24
Finished May 28 01:21:32 PM PDT 24
Peak memory 190824 kb
Host smart-f2e88667-095f-4007-b8e2-69501f377e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436515223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3436515223
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.454116434
Short name T438
Test name
Test status
Simulation time 34111860297 ps
CPU time 53.2 seconds
Started May 28 01:12:43 PM PDT 24
Finished May 28 01:13:40 PM PDT 24
Peak memory 194656 kb
Host smart-e6e6f8c4-ee44-4fa8-b65d-26ca027bbbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454116434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.454116434
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/172.rv_timer_random.2392397869
Short name T302
Test name
Test status
Simulation time 41937269871 ps
CPU time 76.99 seconds
Started May 28 01:13:33 PM PDT 24
Finished May 28 01:14:51 PM PDT 24
Peak memory 182624 kb
Host smart-4055e406-c4b3-4c15-b529-7af10b05cbdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392397869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2392397869
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1878005429
Short name T433
Test name
Test status
Simulation time 41767206772 ps
CPU time 62.98 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:14:34 PM PDT 24
Peak memory 182268 kb
Host smart-86824b5f-ce2c-4fca-88c8-5adc8ef327bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878005429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1878005429
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.569811066
Short name T314
Test name
Test status
Simulation time 325531617784 ps
CPU time 186.02 seconds
Started May 28 01:13:32 PM PDT 24
Finished May 28 01:16:40 PM PDT 24
Peak memory 190828 kb
Host smart-9d2a5e8f-41ff-414d-8869-ff145dd9c84e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569811066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.569811066
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1269861925
Short name T417
Test name
Test status
Simulation time 268801876585 ps
CPU time 1609.74 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:40:20 PM PDT 24
Peak memory 190832 kb
Host smart-422acf18-e271-490a-a0ee-f15bc945d41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269861925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1269861925
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3462124619
Short name T100
Test name
Test status
Simulation time 26398242853 ps
CPU time 20.72 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:13:12 PM PDT 24
Peak memory 182600 kb
Host smart-f93cb482-411e-4d3c-84a2-8231023e1a28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462124619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3462124619
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1605010190
Short name T429
Test name
Test status
Simulation time 112065250088 ps
CPU time 145.63 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:15:08 PM PDT 24
Peak memory 182576 kb
Host smart-50b11d83-1b7c-43d9-8673-c0a333600cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605010190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1605010190
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.4050879151
Short name T406
Test name
Test status
Simulation time 1442824748 ps
CPU time 1.5 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:12:52 PM PDT 24
Peak memory 192828 kb
Host smart-41c8146c-3913-4b2a-9b70-77ec6b32c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050879151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.4050879151
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2483612470
Short name T239
Test name
Test status
Simulation time 124511541864 ps
CPU time 899.99 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:28:23 PM PDT 24
Peak memory 190824 kb
Host smart-b9753e93-bc01-445d-9bfe-b9dddd7564ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483612470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2483612470
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3625400988
Short name T306
Test name
Test status
Simulation time 138583699053 ps
CPU time 236.8 seconds
Started May 28 01:13:20 PM PDT 24
Finished May 28 01:17:22 PM PDT 24
Peak memory 190640 kb
Host smart-23e84612-99d7-4fc1-92c6-9018ced8984a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625400988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3625400988
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1119119333
Short name T275
Test name
Test status
Simulation time 109757571945 ps
CPU time 180.74 seconds
Started May 28 01:13:30 PM PDT 24
Finished May 28 01:16:33 PM PDT 24
Peak memory 190764 kb
Host smart-b54ef80f-da3d-4f19-8392-93801012c354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119119333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1119119333
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2360288793
Short name T176
Test name
Test status
Simulation time 28919189891 ps
CPU time 543.53 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:22:29 PM PDT 24
Peak memory 190764 kb
Host smart-89f379d8-1dd2-445e-a9d1-3dacf92d1252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360288793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2360288793
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1426664964
Short name T312
Test name
Test status
Simulation time 135839858988 ps
CPU time 69.02 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:14:40 PM PDT 24
Peak memory 182460 kb
Host smart-12e82512-bb27-49e3-8531-64c27c74110b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426664964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1426664964
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3671350396
Short name T288
Test name
Test status
Simulation time 164140587918 ps
CPU time 73.94 seconds
Started May 28 01:13:38 PM PDT 24
Finished May 28 01:14:53 PM PDT 24
Peak memory 190764 kb
Host smart-971ed282-775b-458b-a380-d70aafdc8045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671350396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3671350396
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1429491951
Short name T359
Test name
Test status
Simulation time 164029142257 ps
CPU time 67.47 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:13:50 PM PDT 24
Peak memory 182584 kb
Host smart-abb2b3ab-b7e3-4255-8983-57fbbb2472e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429491951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1429491951
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1555389706
Short name T121
Test name
Test status
Simulation time 278751559767 ps
CPU time 1311.11 seconds
Started May 28 01:12:44 PM PDT 24
Finished May 28 01:34:38 PM PDT 24
Peak memory 192144 kb
Host smart-cd346e62-9d2b-4e32-8c62-49b76a5585f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555389706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1555389706
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2297861710
Short name T153
Test name
Test status
Simulation time 185708710816 ps
CPU time 105.97 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:14:30 PM PDT 24
Peak memory 193396 kb
Host smart-347e42ff-a690-4bfa-8d6a-d8645c0a7e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297861710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2297861710
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1536791077
Short name T170
Test name
Test status
Simulation time 129052546116 ps
CPU time 181.33 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:16:26 PM PDT 24
Peak memory 190768 kb
Host smart-02b26fa2-571f-4ca9-b862-63a477f4ff6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536791077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1536791077
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.4045004859
Short name T187
Test name
Test status
Simulation time 84039347606 ps
CPU time 453.21 seconds
Started May 28 01:13:32 PM PDT 24
Finished May 28 01:21:07 PM PDT 24
Peak memory 190756 kb
Host smart-7072b1cb-f6b9-4a1f-a47f-0cb5dbbeab46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045004859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.4045004859
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.23733839
Short name T311
Test name
Test status
Simulation time 97977217054 ps
CPU time 166.27 seconds
Started May 28 01:13:35 PM PDT 24
Finished May 28 01:16:22 PM PDT 24
Peak memory 190832 kb
Host smart-477262bd-e87f-4f34-a5b8-de583c293e14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23733839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.23733839
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2141356688
Short name T272
Test name
Test status
Simulation time 54395686658 ps
CPU time 45.04 seconds
Started May 28 01:13:41 PM PDT 24
Finished May 28 01:14:27 PM PDT 24
Peak memory 182564 kb
Host smart-9010bea0-e655-4177-b5a2-c7045b731c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141356688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2141356688
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.801681310
Short name T419
Test name
Test status
Simulation time 95097892483 ps
CPU time 85.86 seconds
Started May 28 01:13:40 PM PDT 24
Finished May 28 01:15:07 PM PDT 24
Peak memory 182520 kb
Host smart-71fba314-5707-4a59-98ab-e7b94492aadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801681310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.801681310
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4286866948
Short name T324
Test name
Test status
Simulation time 129605095467 ps
CPU time 160.5 seconds
Started May 28 01:13:20 PM PDT 24
Finished May 28 01:16:06 PM PDT 24
Peak memory 190556 kb
Host smart-8395a8a3-772b-4953-85d5-0e90e0244b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286866948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4286866948
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2187679810
Short name T256
Test name
Test status
Simulation time 97743985701 ps
CPU time 222.22 seconds
Started May 28 01:13:42 PM PDT 24
Finished May 28 01:17:25 PM PDT 24
Peak memory 190824 kb
Host smart-04e03763-763e-4b46-9be6-c7e05c85291f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187679810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2187679810
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.480317156
Short name T340
Test name
Test status
Simulation time 103919188827 ps
CPU time 355.42 seconds
Started May 28 01:13:46 PM PDT 24
Finished May 28 01:19:42 PM PDT 24
Peak memory 190836 kb
Host smart-cbba31a6-60af-40ae-a048-e9804a4d7b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480317156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.480317156
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1012089121
Short name T122
Test name
Test status
Simulation time 369501096081 ps
CPU time 345.87 seconds
Started May 28 01:12:12 PM PDT 24
Finished May 28 01:18:01 PM PDT 24
Peak memory 182600 kb
Host smart-c521d65c-392a-4e10-8bac-7f6ba9a43260
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012089121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1012089121
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1444426384
Short name T403
Test name
Test status
Simulation time 582567926132 ps
CPU time 226.45 seconds
Started May 28 01:12:22 PM PDT 24
Finished May 28 01:16:10 PM PDT 24
Peak memory 182648 kb
Host smart-5228ae3f-2427-4942-bbd9-fde426b99494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444426384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1444426384
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.70586199
Short name T181
Test name
Test status
Simulation time 76111016294 ps
CPU time 128.59 seconds
Started May 28 01:12:21 PM PDT 24
Finished May 28 01:14:32 PM PDT 24
Peak memory 190836 kb
Host smart-d6b87706-1145-40ed-bf0e-e366f2b51268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70586199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.70586199
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3385576847
Short name T404
Test name
Test status
Simulation time 5735809629 ps
CPU time 4.36 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:12:30 PM PDT 24
Peak memory 182412 kb
Host smart-aa459531-fd5f-41c8-8651-4ce9b0cebdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385576847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3385576847
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.341928126
Short name T14
Test name
Test status
Simulation time 57350014 ps
CPU time 0.77 seconds
Started May 28 01:12:06 PM PDT 24
Finished May 28 01:12:12 PM PDT 24
Peak memory 213380 kb
Host smart-6fcb1ac8-70c8-4f3f-b8cc-330f0024af22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341928126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.341928126
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1564092096
Short name T189
Test name
Test status
Simulation time 80014430066 ps
CPU time 32.64 seconds
Started May 28 01:12:48 PM PDT 24
Finished May 28 01:13:25 PM PDT 24
Peak memory 182648 kb
Host smart-e78e7376-9306-4ab4-a958-96455f4fdaf8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564092096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1564092096
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2748576687
Short name T133
Test name
Test status
Simulation time 11817835257 ps
CPU time 13.93 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:13:05 PM PDT 24
Peak memory 193792 kb
Host smart-0bee1c78-ce2d-4896-bd95-1df6a7d0c459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748576687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2748576687
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3360592183
Short name T172
Test name
Test status
Simulation time 369097270595 ps
CPU time 343.93 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:18:36 PM PDT 24
Peak memory 182640 kb
Host smart-a2cac7f6-bc98-4db5-889e-ed9561ef4e2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360592183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3360592183
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1966389001
Short name T375
Test name
Test status
Simulation time 109067329481 ps
CPU time 45.3 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:13:28 PM PDT 24
Peak memory 182628 kb
Host smart-cecb163a-aaf7-4bed-a592-04481927dbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966389001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1966389001
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1352320695
Short name T220
Test name
Test status
Simulation time 96849020765 ps
CPU time 302.09 seconds
Started May 28 01:12:44 PM PDT 24
Finished May 28 01:17:50 PM PDT 24
Peak memory 190836 kb
Host smart-de522837-b9cc-47ca-af68-054b8f58d334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352320695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1352320695
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1384765697
Short name T221
Test name
Test status
Simulation time 244783042313 ps
CPU time 2286.74 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:50:49 PM PDT 24
Peak memory 194400 kb
Host smart-cbb70506-9c09-450a-91cc-695e66846347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384765697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1384765697
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2247138956
Short name T399
Test name
Test status
Simulation time 35372047807 ps
CPU time 23.37 seconds
Started May 28 01:12:45 PM PDT 24
Finished May 28 01:13:13 PM PDT 24
Peak memory 182556 kb
Host smart-a9539d29-424b-4df6-87cf-6aa765479de9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247138956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2247138956
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3932417171
Short name T400
Test name
Test status
Simulation time 504125183845 ps
CPU time 324.19 seconds
Started May 28 01:12:48 PM PDT 24
Finished May 28 01:18:16 PM PDT 24
Peak memory 182532 kb
Host smart-2f1ef634-3714-40cf-ae10-7d3bd37ee7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932417171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3932417171
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2860278313
Short name T268
Test name
Test status
Simulation time 17534672920 ps
CPU time 34.99 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:13:17 PM PDT 24
Peak memory 182572 kb
Host smart-47ccdd73-ed69-4704-9ace-ffdad82924b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860278313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2860278313
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4254849365
Short name T412
Test name
Test status
Simulation time 672142291 ps
CPU time 0.92 seconds
Started May 28 01:12:42 PM PDT 24
Finished May 28 01:12:46 PM PDT 24
Peak memory 190944 kb
Host smart-9a8bc69f-b936-454c-add1-11be036e2c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254849365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4254849365
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.49962686
Short name T52
Test name
Test status
Simulation time 353325447631 ps
CPU time 172.3 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:15:44 PM PDT 24
Peak memory 190792 kb
Host smart-d5613fd1-f75a-4fb8-b975-49d4c6b9bf61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49962686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.49962686
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3035957202
Short name T363
Test name
Test status
Simulation time 696266385573 ps
CPU time 204.34 seconds
Started May 28 01:12:50 PM PDT 24
Finished May 28 01:16:17 PM PDT 24
Peak memory 182580 kb
Host smart-141835d4-8bc5-45b9-a45f-acdbba58843d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035957202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3035957202
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.418753791
Short name T197
Test name
Test status
Simulation time 174783954109 ps
CPU time 584.07 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:22:35 PM PDT 24
Peak memory 190756 kb
Host smart-f66b31a2-59f2-48a9-aa17-25201592bf91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418753791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.418753791
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1823233913
Short name T283
Test name
Test status
Simulation time 21033019991 ps
CPU time 36.27 seconds
Started May 28 01:12:44 PM PDT 24
Finished May 28 01:13:24 PM PDT 24
Peak memory 190848 kb
Host smart-3446c9b0-1efa-43e2-8299-d2bf56ce2f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823233913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1823233913
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3763938755
Short name T388
Test name
Test status
Simulation time 974366259918 ps
CPU time 707.6 seconds
Started May 28 01:12:49 PM PDT 24
Finished May 28 01:24:40 PM PDT 24
Peak memory 190764 kb
Host smart-dca064f4-e4cf-4ffd-a50b-975e9770b1e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763938755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3763938755
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3368411900
Short name T136
Test name
Test status
Simulation time 776595035360 ps
CPU time 318.73 seconds
Started May 28 01:12:44 PM PDT 24
Finished May 28 01:18:06 PM PDT 24
Peak memory 182648 kb
Host smart-89bc7830-830e-44f2-a2fb-5c552d638902
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368411900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3368411900
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.664802974
Short name T436
Test name
Test status
Simulation time 193727633504 ps
CPU time 148.81 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:15:13 PM PDT 24
Peak memory 181968 kb
Host smart-dfc90e19-6e29-4658-8735-16e360f8808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664802974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.664802974
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3627018656
Short name T321
Test name
Test status
Simulation time 7403581224 ps
CPU time 62.89 seconds
Started May 28 01:12:44 PM PDT 24
Finished May 28 01:13:50 PM PDT 24
Peak memory 182628 kb
Host smart-e04b005f-f738-4a09-bd52-043ffdc989e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627018656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3627018656
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.148052582
Short name T60
Test name
Test status
Simulation time 604028838705 ps
CPU time 859.49 seconds
Started May 28 01:12:36 PM PDT 24
Finished May 28 01:26:56 PM PDT 24
Peak memory 190764 kb
Host smart-7e2ac022-ee94-4fb4-83a9-7379468fdccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148052582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
148052582
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.286479639
Short name T392
Test name
Test status
Simulation time 163688427986 ps
CPU time 189.11 seconds
Started May 28 01:12:50 PM PDT 24
Finished May 28 01:16:02 PM PDT 24
Peak memory 182600 kb
Host smart-32c79924-9f6b-424f-a784-4573d410d520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286479639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.286479639
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.734629727
Short name T262
Test name
Test status
Simulation time 1915587686063 ps
CPU time 592.41 seconds
Started May 28 01:12:43 PM PDT 24
Finished May 28 01:22:39 PM PDT 24
Peak memory 190764 kb
Host smart-ededd917-92b7-4fe0-9ef1-9dab645ed5e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734629727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.734629727
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.71845479
Short name T252
Test name
Test status
Simulation time 44460093997 ps
CPU time 79.74 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:14:03 PM PDT 24
Peak memory 182600 kb
Host smart-e004104b-9741-432c-8671-3259a3fcedc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71845479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.71845479
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3565536206
Short name T358
Test name
Test status
Simulation time 20843778 ps
CPU time 0.57 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:12:42 PM PDT 24
Peak memory 182288 kb
Host smart-f8522370-09e8-43f8-84bf-0c826988ee75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565536206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3565536206
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.2499567712
Short name T12
Test name
Test status
Simulation time 25535427129 ps
CPU time 120.51 seconds
Started May 28 01:12:44 PM PDT 24
Finished May 28 01:14:48 PM PDT 24
Peak memory 197276 kb
Host smart-c745da4f-8f69-4743-bb7f-a98f8bb6e82a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499567712 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.2499567712
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3612727656
Short name T264
Test name
Test status
Simulation time 43684783140 ps
CPU time 69.51 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:13:53 PM PDT 24
Peak memory 182648 kb
Host smart-12a01b2e-4f66-418e-8821-a5fc15ca7430
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612727656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3612727656
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2351065061
Short name T424
Test name
Test status
Simulation time 25153048079 ps
CPU time 33.58 seconds
Started May 28 01:12:45 PM PDT 24
Finished May 28 01:13:23 PM PDT 24
Peak memory 182664 kb
Host smart-a9a3a7b3-c724-49ea-8edc-d17bde6ea932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351065061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2351065061
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1781443306
Short name T202
Test name
Test status
Simulation time 112679778143 ps
CPU time 186.2 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:15:57 PM PDT 24
Peak memory 190768 kb
Host smart-9a21a56e-4334-48fa-84ca-5d189789db73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781443306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1781443306
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1887914769
Short name T442
Test name
Test status
Simulation time 645144945 ps
CPU time 0.83 seconds
Started May 28 01:12:45 PM PDT 24
Finished May 28 01:12:50 PM PDT 24
Peak memory 190976 kb
Host smart-b4cf0a0c-78fb-4d2e-a2c4-18b47ebf5bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887914769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1887914769
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3349224701
Short name T36
Test name
Test status
Simulation time 33611001315 ps
CPU time 248.54 seconds
Started May 28 01:12:39 PM PDT 24
Finished May 28 01:16:49 PM PDT 24
Peak memory 205488 kb
Host smart-d32ec0d9-5236-4c93-a3b6-4808210770c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349224701 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3349224701
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.608604516
Short name T313
Test name
Test status
Simulation time 377099623156 ps
CPU time 655.24 seconds
Started May 28 01:12:49 PM PDT 24
Finished May 28 01:23:48 PM PDT 24
Peak memory 182604 kb
Host smart-54c06e9d-0371-4389-8c22-96b7164b4340
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608604516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.608604516
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2114579279
Short name T428
Test name
Test status
Simulation time 63190889940 ps
CPU time 46.57 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:13:38 PM PDT 24
Peak memory 182580 kb
Host smart-1f15dba7-977a-4133-b249-c2498b976699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114579279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2114579279
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3912986943
Short name T425
Test name
Test status
Simulation time 5864288195 ps
CPU time 12.78 seconds
Started May 28 01:12:45 PM PDT 24
Finished May 28 01:13:02 PM PDT 24
Peak memory 182640 kb
Host smart-5ac45443-f99d-4d31-b12d-33e59ab0dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912986943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3912986943
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.838625665
Short name T441
Test name
Test status
Simulation time 185184760 ps
CPU time 0.65 seconds
Started May 28 01:12:50 PM PDT 24
Finished May 28 01:12:53 PM PDT 24
Peak memory 182228 kb
Host smart-8fc453e7-6464-48d2-860b-6453167edc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838625665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
838625665
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.12399398
Short name T325
Test name
Test status
Simulation time 9664123041 ps
CPU time 15.52 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:13:07 PM PDT 24
Peak memory 182568 kb
Host smart-fe61c2fe-5d0c-4cb4-a873-bcd5d8a7cd03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12399398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.rv_timer_cfg_update_on_fly.12399398
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.4286283702
Short name T61
Test name
Test status
Simulation time 51658562546 ps
CPU time 74.3 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:13:58 PM PDT 24
Peak memory 182644 kb
Host smart-f5a311e4-5dbd-45c6-98b6-ec8913386156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286283702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.4286283702
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1496606086
Short name T248
Test name
Test status
Simulation time 60601649910 ps
CPU time 54.81 seconds
Started May 28 01:12:45 PM PDT 24
Finished May 28 01:13:44 PM PDT 24
Peak memory 182620 kb
Host smart-98a3bb26-83c3-415f-aee0-32c291f60a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496606086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1496606086
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1756563076
Short name T381
Test name
Test status
Simulation time 971763372 ps
CPU time 0.7 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:12:52 PM PDT 24
Peak memory 182368 kb
Host smart-5a0667bc-b661-4831-bbfb-9e03e3ae2be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756563076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1756563076
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1890223990
Short name T261
Test name
Test status
Simulation time 3304892440850 ps
CPU time 1449.31 seconds
Started May 28 01:12:42 PM PDT 24
Finished May 28 01:36:54 PM PDT 24
Peak memory 193416 kb
Host smart-fc5109b5-2fac-491d-a05d-a193e0c294b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890223990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1890223990
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2111908000
Short name T63
Test name
Test status
Simulation time 36014773353 ps
CPU time 318.91 seconds
Started May 28 01:12:43 PM PDT 24
Finished May 28 01:18:05 PM PDT 24
Peak memory 205416 kb
Host smart-867d44c0-34ae-42f3-adbe-39775cbc7945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111908000 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2111908000
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.517766612
Short name T350
Test name
Test status
Simulation time 5346213621 ps
CPU time 9.7 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:13:00 PM PDT 24
Peak memory 182620 kb
Host smart-007747a1-f289-4ea3-89c3-633f8f0c4fda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517766612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.517766612
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.402666860
Short name T365
Test name
Test status
Simulation time 66670300852 ps
CPU time 47.65 seconds
Started May 28 01:12:40 PM PDT 24
Finished May 28 01:13:31 PM PDT 24
Peak memory 182564 kb
Host smart-afa01ff1-5c40-4b3f-9a62-0b7cedee316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402666860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.402666860
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1190246064
Short name T186
Test name
Test status
Simulation time 327469494937 ps
CPU time 196.74 seconds
Started May 28 01:12:42 PM PDT 24
Finished May 28 01:16:02 PM PDT 24
Peak memory 190752 kb
Host smart-7cb55014-36ab-4b7e-afb5-db483479ec79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190246064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1190246064
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2445468958
Short name T364
Test name
Test status
Simulation time 35705758 ps
CPU time 0.52 seconds
Started May 28 01:12:41 PM PDT 24
Finished May 28 01:12:44 PM PDT 24
Peak memory 182432 kb
Host smart-bd3bf0a3-9ef9-4c00-8c8b-2a13b5757b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445468958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2445468958
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3855316783
Short name T332
Test name
Test status
Simulation time 5670707406323 ps
CPU time 1515.92 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:38:08 PM PDT 24
Peak memory 190820 kb
Host smart-b99fdced-5339-476f-9892-a7b05f4618d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855316783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3855316783
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.47323439
Short name T11
Test name
Test status
Simulation time 21413661391 ps
CPU time 241.15 seconds
Started May 28 01:12:43 PM PDT 24
Finished May 28 01:16:47 PM PDT 24
Peak memory 197216 kb
Host smart-bb26a1b1-9df8-4f54-bfbc-1d01a431e606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47323439 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.47323439
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2770921766
Short name T224
Test name
Test status
Simulation time 100035941389 ps
CPU time 179.09 seconds
Started May 28 01:12:20 PM PDT 24
Finished May 28 01:15:21 PM PDT 24
Peak memory 182636 kb
Host smart-bad70b50-31bd-4b41-bd8b-938c7a2ae6aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770921766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2770921766
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3396565381
Short name T415
Test name
Test status
Simulation time 159270580964 ps
CPU time 232.65 seconds
Started May 28 01:12:06 PM PDT 24
Finished May 28 01:16:04 PM PDT 24
Peak memory 182592 kb
Host smart-2874ef65-be6b-45c6-9308-2b0298946cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396565381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3396565381
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.817455382
Short name T439
Test name
Test status
Simulation time 77454282516 ps
CPU time 387.35 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:18:52 PM PDT 24
Peak memory 182632 kb
Host smart-ac648ea4-3bf3-4e9e-b6c4-4e824f19020d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817455382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.817455382
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3798616656
Short name T269
Test name
Test status
Simulation time 23235367361 ps
CPU time 35.11 seconds
Started May 28 01:12:21 PM PDT 24
Finished May 28 01:12:58 PM PDT 24
Peak memory 190844 kb
Host smart-017dac80-9255-4bf7-984a-488deb71b857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798616656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3798616656
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3927845908
Short name T17
Test name
Test status
Simulation time 260476346 ps
CPU time 0.87 seconds
Started May 28 01:12:20 PM PDT 24
Finished May 28 01:12:23 PM PDT 24
Peak memory 213788 kb
Host smart-872e6eaf-a3d3-4533-942d-7ad2d285cccf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927845908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3927845908
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.794642375
Short name T124
Test name
Test status
Simulation time 744315299588 ps
CPU time 664.75 seconds
Started May 28 01:12:21 PM PDT 24
Finished May 28 01:23:28 PM PDT 24
Peak memory 190756 kb
Host smart-514cc844-d4b0-452e-a56c-3659317f4afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794642375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.794642375
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2350725932
Short name T102
Test name
Test status
Simulation time 414063652362 ps
CPU time 469 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:20:40 PM PDT 24
Peak memory 182652 kb
Host smart-89902571-2707-4972-b914-4c7285384d16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350725932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2350725932
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1330976581
Short name T372
Test name
Test status
Simulation time 118089466903 ps
CPU time 189.89 seconds
Started May 28 01:12:47 PM PDT 24
Finished May 28 01:16:01 PM PDT 24
Peak memory 182648 kb
Host smart-c2cf0217-ef56-437c-a474-9ba2495421c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330976581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1330976581
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1021323339
Short name T169
Test name
Test status
Simulation time 117191185283 ps
CPU time 417.84 seconds
Started May 28 01:12:46 PM PDT 24
Finished May 28 01:19:48 PM PDT 24
Peak memory 190836 kb
Host smart-86429a61-b0e2-4a15-bcad-031372c1eb0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021323339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1021323339
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.942164168
Short name T109
Test name
Test status
Simulation time 60744030326 ps
CPU time 110.54 seconds
Started May 28 01:13:00 PM PDT 24
Finished May 28 01:14:53 PM PDT 24
Peak memory 190832 kb
Host smart-484574f0-a3ef-484e-a8ff-bd5cc2f912ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942164168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.942164168
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2578538945
Short name T19
Test name
Test status
Simulation time 161300552510 ps
CPU time 351.24 seconds
Started May 28 01:13:00 PM PDT 24
Finished May 28 01:18:53 PM PDT 24
Peak memory 190764 kb
Host smart-ae91c504-ab40-451c-9e6d-fd5e4514d997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578538945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2578538945
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2048493412
Short name T62
Test name
Test status
Simulation time 41986507578 ps
CPU time 23.15 seconds
Started May 28 01:13:05 PM PDT 24
Finished May 28 01:13:31 PM PDT 24
Peak memory 182648 kb
Host smart-6c9c1d91-1c13-4565-b60e-4d1fa9cec17e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048493412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2048493412
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3555942707
Short name T378
Test name
Test status
Simulation time 136505408345 ps
CPU time 115.77 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:15:07 PM PDT 24
Peak memory 182632 kb
Host smart-dfaa7e63-3442-4b93-83ad-a54a83eaf289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555942707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3555942707
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3760868808
Short name T352
Test name
Test status
Simulation time 123663440 ps
CPU time 0.55 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:13:06 PM PDT 24
Peak memory 182308 kb
Host smart-3b0cd5cc-6ba9-4918-8274-03ba4816c257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760868808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3760868808
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.1988229709
Short name T35
Test name
Test status
Simulation time 173853134987 ps
CPU time 657.95 seconds
Started May 28 01:12:56 PM PDT 24
Finished May 28 01:23:55 PM PDT 24
Peak memory 206944 kb
Host smart-d8363a6f-28fc-4e82-a3b3-d57aa1a35c18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988229709 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.1988229709
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1802542063
Short name T410
Test name
Test status
Simulation time 103156787642 ps
CPU time 156.64 seconds
Started May 28 01:12:56 PM PDT 24
Finished May 28 01:15:34 PM PDT 24
Peak memory 182580 kb
Host smart-bed322a0-3c56-4721-8e8a-daa2aab484ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802542063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1802542063
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1409982747
Short name T129
Test name
Test status
Simulation time 409474209821 ps
CPU time 187.44 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:16:13 PM PDT 24
Peak memory 190836 kb
Host smart-8ecf1279-98b2-4316-b7f8-ca756d79019f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409982747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1409982747
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3207238347
Short name T371
Test name
Test status
Simulation time 54326380 ps
CPU time 1 seconds
Started May 28 01:12:56 PM PDT 24
Finished May 28 01:12:58 PM PDT 24
Peak memory 182516 kb
Host smart-ff3816d3-82d5-4789-b854-ee8a18dae7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207238347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3207238347
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1165477142
Short name T4
Test name
Test status
Simulation time 76277474068 ps
CPU time 119.3 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:15:22 PM PDT 24
Peak memory 182568 kb
Host smart-89b93015-0bca-4ab4-8e44-f38f3626387f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165477142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1165477142
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.1214484690
Short name T39
Test name
Test status
Simulation time 61996481541 ps
CPU time 173.81 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:16:07 PM PDT 24
Peak memory 205460 kb
Host smart-d844ebb2-5113-4dec-95e6-fa9542761ddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214484690 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.1214484690
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3008868362
Short name T434
Test name
Test status
Simulation time 73637649789 ps
CPU time 118.33 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:15:11 PM PDT 24
Peak memory 182576 kb
Host smart-e309892c-f09d-444a-a385-04f627f502e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008868362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3008868362
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3720525303
Short name T21
Test name
Test status
Simulation time 985875829294 ps
CPU time 278.02 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:17:50 PM PDT 24
Peak memory 190760 kb
Host smart-cab8960f-9a93-41ae-b445-d877294f2bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720525303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3720525303
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3707991404
Short name T135
Test name
Test status
Simulation time 72193658853 ps
CPU time 138.27 seconds
Started May 28 01:12:57 PM PDT 24
Finished May 28 01:15:16 PM PDT 24
Peak memory 190828 kb
Host smart-1b45583a-04cd-4272-bdfb-fadde057d610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707991404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3707991404
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1421300950
Short name T301
Test name
Test status
Simulation time 409701806728 ps
CPU time 665.54 seconds
Started May 28 01:12:54 PM PDT 24
Finished May 28 01:24:01 PM PDT 24
Peak memory 182648 kb
Host smart-13624b21-6140-42ad-9e63-29e0b20b081c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421300950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1421300950
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1340239560
Short name T356
Test name
Test status
Simulation time 46087062411 ps
CPU time 72.82 seconds
Started May 28 01:13:05 PM PDT 24
Finished May 28 01:14:21 PM PDT 24
Peak memory 182572 kb
Host smart-a0506159-790f-4adb-9eeb-000773c2a072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340239560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1340239560
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.4140729277
Short name T395
Test name
Test status
Simulation time 37212270341 ps
CPU time 59.88 seconds
Started May 28 01:13:04 PM PDT 24
Finished May 28 01:14:07 PM PDT 24
Peak memory 182628 kb
Host smart-8c01a9f9-82ff-4d95-bbdf-3519097f2a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140729277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.4140729277
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2213610678
Short name T354
Test name
Test status
Simulation time 727697664 ps
CPU time 0.81 seconds
Started May 28 01:12:54 PM PDT 24
Finished May 28 01:12:56 PM PDT 24
Peak memory 182440 kb
Host smart-f4d57a83-e736-4461-9366-1dacc68178b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213610678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2213610678
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2080769317
Short name T398
Test name
Test status
Simulation time 21686135892 ps
CPU time 90.93 seconds
Started May 28 01:12:55 PM PDT 24
Finished May 28 01:14:28 PM PDT 24
Peak memory 197272 kb
Host smart-9049f9d9-7bc3-4e5e-9a54-9cb1261eb413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080769317 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2080769317
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.938169024
Short name T199
Test name
Test status
Simulation time 575785722605 ps
CPU time 306.01 seconds
Started May 28 01:13:04 PM PDT 24
Finished May 28 01:18:13 PM PDT 24
Peak memory 182576 kb
Host smart-83bdfd71-9b0e-4575-99a5-26671dee68f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938169024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.938169024
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1964621566
Short name T448
Test name
Test status
Simulation time 148247179966 ps
CPU time 199.77 seconds
Started May 28 01:13:00 PM PDT 24
Finished May 28 01:16:22 PM PDT 24
Peak memory 182644 kb
Host smart-ad402e8e-c517-47e2-bbec-e643f9f0184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964621566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1964621566
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3626068556
Short name T193
Test name
Test status
Simulation time 123467144690 ps
CPU time 288.16 seconds
Started May 28 01:13:04 PM PDT 24
Finished May 28 01:17:56 PM PDT 24
Peak memory 190828 kb
Host smart-6615fb24-477e-46fa-b08b-d4f814f08ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626068556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3626068556
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2626366981
Short name T59
Test name
Test status
Simulation time 73564559207 ps
CPU time 350.6 seconds
Started May 28 01:12:53 PM PDT 24
Finished May 28 01:18:44 PM PDT 24
Peak memory 194572 kb
Host smart-6c37a5f0-ecf1-48eb-8e2e-22d1aace5562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626366981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2626366981
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1053024064
Short name T33
Test name
Test status
Simulation time 181219884011 ps
CPU time 208.74 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:16:48 PM PDT 24
Peak memory 195420 kb
Host smart-e587ca76-a0a7-45b1-bc57-9d5496177c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053024064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1053024064
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3562933685
Short name T230
Test name
Test status
Simulation time 568947749466 ps
CPU time 303.57 seconds
Started May 28 01:12:56 PM PDT 24
Finished May 28 01:18:01 PM PDT 24
Peak memory 182600 kb
Host smart-4602d364-f2a9-4a06-8f55-38348f88e424
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562933685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3562933685
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2394610764
Short name T446
Test name
Test status
Simulation time 85675509256 ps
CPU time 32.11 seconds
Started May 28 01:13:05 PM PDT 24
Finished May 28 01:13:41 PM PDT 24
Peak memory 182600 kb
Host smart-c1c0723d-147b-449c-8bac-9550438b9541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394610764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2394610764
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3279919948
Short name T7
Test name
Test status
Simulation time 9899351690 ps
CPU time 22.83 seconds
Started May 28 01:12:58 PM PDT 24
Finished May 28 01:13:22 PM PDT 24
Peak memory 182572 kb
Host smart-9474e81c-9e09-4c44-8fcb-9805617e24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279919948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3279919948
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_random.1932151508
Short name T117
Test name
Test status
Simulation time 75498489231 ps
CPU time 118.38 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:15:04 PM PDT 24
Peak memory 193048 kb
Host smart-dc842ae2-8fde-463c-8692-3f05a1703a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932151508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1932151508
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2435811948
Short name T385
Test name
Test status
Simulation time 64059469097 ps
CPU time 55.92 seconds
Started May 28 01:13:03 PM PDT 24
Finished May 28 01:14:02 PM PDT 24
Peak memory 190848 kb
Host smart-0f9daf07-d3fa-45c1-9cae-a0684573ce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435811948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2435811948
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3793388478
Short name T53
Test name
Test status
Simulation time 73894339 ps
CPU time 0.62 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:13:04 PM PDT 24
Peak memory 182328 kb
Host smart-7795a6ae-f1b2-45ed-8e05-280f431af42e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793388478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3793388478
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.196856354
Short name T238
Test name
Test status
Simulation time 204354212063 ps
CPU time 108.58 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:14:54 PM PDT 24
Peak memory 182640 kb
Host smart-da24e6a7-eb5d-4bd3-8f6d-b255df09148d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196856354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.196856354
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3447055565
Short name T380
Test name
Test status
Simulation time 149187250053 ps
CPU time 243.82 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:17:17 PM PDT 24
Peak memory 182608 kb
Host smart-1d331e44-8293-4eef-865b-e418f5116959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447055565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3447055565
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1298973924
Short name T206
Test name
Test status
Simulation time 508325095042 ps
CPU time 904.31 seconds
Started May 28 01:12:59 PM PDT 24
Finished May 28 01:28:04 PM PDT 24
Peak memory 190836 kb
Host smart-5970d8d1-8bca-4837-8f74-50af841e656c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298973924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1298973924
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1914705363
Short name T57
Test name
Test status
Simulation time 286438871871 ps
CPU time 1093.32 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:31:18 PM PDT 24
Peak memory 194060 kb
Host smart-0fa3e742-2fa5-4daa-b6bc-f236e2a4f038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914705363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1914705363
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1488471495
Short name T337
Test name
Test status
Simulation time 687226676741 ps
CPU time 673.07 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:24:19 PM PDT 24
Peak memory 182648 kb
Host smart-e6a979cb-fd1a-4b66-b31b-8be018b2dc72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488471495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1488471495
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3796928780
Short name T437
Test name
Test status
Simulation time 113165382130 ps
CPU time 169.19 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:15:53 PM PDT 24
Peak memory 182584 kb
Host smart-5e217926-32d5-421d-b724-9a91cb5d3dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796928780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3796928780
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1298841577
Short name T222
Test name
Test status
Simulation time 135530053787 ps
CPU time 132.36 seconds
Started May 28 01:13:00 PM PDT 24
Finished May 28 01:15:15 PM PDT 24
Peak memory 193544 kb
Host smart-fdbac4cb-53cc-4291-9471-85ff0307737b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298841577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1298841577
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.4142147524
Short name T265
Test name
Test status
Simulation time 124835864317 ps
CPU time 204.02 seconds
Started May 28 01:13:00 PM PDT 24
Finished May 28 01:16:26 PM PDT 24
Peak memory 190812 kb
Host smart-3a89c206-bba1-440b-a3ba-214f560112c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142147524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.4142147524
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3121516453
Short name T355
Test name
Test status
Simulation time 152769942679 ps
CPU time 253.63 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:16:38 PM PDT 24
Peak memory 182652 kb
Host smart-b30101c8-6b86-4f82-b62b-dfe91c1601c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121516453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3121516453
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2035829731
Short name T140
Test name
Test status
Simulation time 5358845378 ps
CPU time 8.56 seconds
Started May 28 01:12:07 PM PDT 24
Finished May 28 01:12:21 PM PDT 24
Peak memory 182524 kb
Host smart-09ce436f-e884-4107-bd14-9d808eb548c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035829731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2035829731
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3747876739
Short name T431
Test name
Test status
Simulation time 314353866 ps
CPU time 0.78 seconds
Started May 28 01:12:07 PM PDT 24
Finished May 28 01:12:13 PM PDT 24
Peak memory 182428 kb
Host smart-57ba90f2-ad50-49bf-941e-300e26de6c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747876739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3747876739
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1195341283
Short name T13
Test name
Test status
Simulation time 167004402 ps
CPU time 0.93 seconds
Started May 28 01:12:11 PM PDT 24
Finished May 28 01:12:16 PM PDT 24
Peak memory 213152 kb
Host smart-74b8f0e8-4d74-4163-8cac-d094652ba2d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195341283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1195341283
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3130997410
Short name T284
Test name
Test status
Simulation time 552249141782 ps
CPU time 554.53 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:22:19 PM PDT 24
Peak memory 182592 kb
Host smart-1eb65947-ed32-4340-b211-ec00fb5ee283
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130997410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3130997410
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3553882438
Short name T376
Test name
Test status
Simulation time 770318715206 ps
CPU time 295.39 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:18:00 PM PDT 24
Peak memory 182596 kb
Host smart-886046c9-ee29-4fef-8404-ff023d87245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553882438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3553882438
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1047386396
Short name T151
Test name
Test status
Simulation time 67016784328 ps
CPU time 95.03 seconds
Started May 28 01:13:00 PM PDT 24
Finished May 28 01:14:38 PM PDT 24
Peak memory 190644 kb
Host smart-5207fe84-11da-4196-af71-d73bd3bb3de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047386396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1047386396
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3621090487
Short name T444
Test name
Test status
Simulation time 137769230062 ps
CPU time 67.31 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:14:13 PM PDT 24
Peak memory 182928 kb
Host smart-1fc4b876-8cce-4eb0-b82e-d75a40ef0222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621090487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3621090487
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1529034784
Short name T447
Test name
Test status
Simulation time 352172934137 ps
CPU time 147.9 seconds
Started May 28 01:13:00 PM PDT 24
Finished May 28 01:15:30 PM PDT 24
Peak memory 194248 kb
Host smart-d6b1c816-aea5-4c3f-a289-223826651424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529034784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1529034784
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3341105036
Short name T119
Test name
Test status
Simulation time 919651224919 ps
CPU time 835.31 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:27:07 PM PDT 24
Peak memory 182592 kb
Host smart-cc1b73fd-50c6-454a-8088-fad8dc183c74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341105036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3341105036
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3897794093
Short name T361
Test name
Test status
Simulation time 113768050899 ps
CPU time 147.42 seconds
Started May 28 01:13:06 PM PDT 24
Finished May 28 01:15:36 PM PDT 24
Peak memory 182532 kb
Host smart-eef7a2a3-ebb3-405b-8362-ddd9087d3900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897794093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3897794093
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2657334477
Short name T305
Test name
Test status
Simulation time 377923735606 ps
CPU time 173.76 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:16:08 PM PDT 24
Peak memory 190712 kb
Host smart-899cecff-315c-4004-bb4f-411a5b4fdecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657334477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2657334477
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1455630108
Short name T348
Test name
Test status
Simulation time 45635407640 ps
CPU time 113.13 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:15:06 PM PDT 24
Peak memory 194956 kb
Host smart-98bb67de-cbc6-4572-af76-98b85a038804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455630108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1455630108
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1763692892
Short name T316
Test name
Test status
Simulation time 156003651109 ps
CPU time 42.95 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:13:55 PM PDT 24
Peak memory 182640 kb
Host smart-c2a4d6ba-0913-414a-bfb7-df2553808f37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763692892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1763692892
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2159651385
Short name T450
Test name
Test status
Simulation time 159496288201 ps
CPU time 228.16 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:16:51 PM PDT 24
Peak memory 182640 kb
Host smart-09af0706-62a9-4337-8398-926d264ecf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159651385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2159651385
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1990294418
Short name T286
Test name
Test status
Simulation time 14568549635 ps
CPU time 25.88 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:13:48 PM PDT 24
Peak memory 182600 kb
Host smart-914bd16a-ab68-4389-bfd7-677876e5e4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990294418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1990294418
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1740164829
Short name T342
Test name
Test status
Simulation time 83685337309 ps
CPU time 134.1 seconds
Started May 28 01:13:12 PM PDT 24
Finished May 28 01:15:30 PM PDT 24
Peak memory 190732 kb
Host smart-0d775559-7a49-42fb-8776-fb17b8172bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740164829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1740164829
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1349633831
Short name T344
Test name
Test status
Simulation time 3223247068631 ps
CPU time 796.78 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:26:29 PM PDT 24
Peak memory 182584 kb
Host smart-cf159a35-b861-4964-85e4-00b8eb9f9d45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349633831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1349633831
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1295460359
Short name T360
Test name
Test status
Simulation time 84480595546 ps
CPU time 116.76 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:15:10 PM PDT 24
Peak memory 182648 kb
Host smart-c49f24db-a254-459a-b906-ad431da95e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295460359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1295460359
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3348299094
Short name T183
Test name
Test status
Simulation time 95252452933 ps
CPU time 153.45 seconds
Started May 28 01:13:19 PM PDT 24
Finished May 28 01:15:57 PM PDT 24
Peak memory 190828 kb
Host smart-c21ab7b3-8d22-4140-9880-a91fd36c1dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348299094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3348299094
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3555172862
Short name T42
Test name
Test status
Simulation time 112478908 ps
CPU time 0.73 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:13:06 PM PDT 24
Peak memory 182384 kb
Host smart-230309e8-02e4-41a2-8e8e-fd2ab845a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555172862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3555172862
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3863467883
Short name T161
Test name
Test status
Simulation time 908972617634 ps
CPU time 703.55 seconds
Started May 28 01:13:12 PM PDT 24
Finished May 28 01:25:00 PM PDT 24
Peak memory 195568 kb
Host smart-b9dd94d7-df49-4454-84b9-bcbdd67609e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863467883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3863467883
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.4128384362
Short name T38
Test name
Test status
Simulation time 54827152618 ps
CPU time 389.81 seconds
Started May 28 01:13:12 PM PDT 24
Finished May 28 01:19:47 PM PDT 24
Peak memory 205488 kb
Host smart-36d7f819-2eff-4557-a9cd-5ce88d3bb1d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128384362 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.4128384362
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3016604878
Short name T95
Test name
Test status
Simulation time 640637862397 ps
CPU time 1076.16 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:31:19 PM PDT 24
Peak memory 182624 kb
Host smart-ca039c63-3fe8-4cdc-8531-70d2bbaaf437
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016604878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3016604878
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2581893859
Short name T418
Test name
Test status
Simulation time 168259090496 ps
CPU time 254.09 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:17:28 PM PDT 24
Peak memory 182640 kb
Host smart-8a2c26df-0cad-4476-82a0-a36f08126a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581893859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2581893859
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2132029984
Short name T336
Test name
Test status
Simulation time 47388787597 ps
CPU time 32.74 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:13:47 PM PDT 24
Peak memory 182608 kb
Host smart-4080f952-d563-439e-88a6-0ffba1d32407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132029984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2132029984
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1014634747
Short name T334
Test name
Test status
Simulation time 109931340058 ps
CPU time 57.83 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:14:10 PM PDT 24
Peak memory 190840 kb
Host smart-a86e971c-563c-4433-a4e5-578164986e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014634747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1014634747
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.453908286
Short name T40
Test name
Test status
Simulation time 105089396598 ps
CPU time 1150.35 seconds
Started May 28 01:13:12 PM PDT 24
Finished May 28 01:32:28 PM PDT 24
Peak memory 213464 kb
Host smart-f0c03475-5f0f-4909-87d1-15623475c8e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453908286 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.453908286
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3972182397
Short name T421
Test name
Test status
Simulation time 178596794568 ps
CPU time 141.53 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:15:42 PM PDT 24
Peak memory 182620 kb
Host smart-3720a7dd-34f7-4a71-a383-2f23631805bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972182397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3972182397
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.748512307
Short name T1
Test name
Test status
Simulation time 26457288566 ps
CPU time 37.21 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:13:58 PM PDT 24
Peak memory 182608 kb
Host smart-8de2c9cb-cdaa-424d-8889-963096056a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748512307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.748512307
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.2685359993
Short name T34
Test name
Test status
Simulation time 52244940438 ps
CPU time 186.48 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:16:18 PM PDT 24
Peak memory 196936 kb
Host smart-c0b50556-c007-4eb0-88f2-4aa206516691
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685359993 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.2685359993
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3571972194
Short name T137
Test name
Test status
Simulation time 1064179712 ps
CPU time 2.27 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:13:23 PM PDT 24
Peak memory 182368 kb
Host smart-f0f974da-de72-42a5-a09b-7bee0852cdb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571972194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3571972194
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3454849557
Short name T353
Test name
Test status
Simulation time 40346033105 ps
CPU time 31.23 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:13:53 PM PDT 24
Peak memory 182612 kb
Host smart-2e2134b1-0144-4c0c-bacf-257591b7c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454849557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3454849557
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4156256148
Short name T362
Test name
Test status
Simulation time 145631530 ps
CPU time 0.64 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:13:21 PM PDT 24
Peak memory 182408 kb
Host smart-043d88b4-6caf-4823-8d29-137b7ec22551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156256148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4156256148
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2039545337
Short name T241
Test name
Test status
Simulation time 339272817445 ps
CPU time 462.72 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:21:03 PM PDT 24
Peak memory 190764 kb
Host smart-772add97-3674-4cc8-89f4-08af55168c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039545337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2039545337
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2141991709
Short name T219
Test name
Test status
Simulation time 236345573510 ps
CPU time 426.98 seconds
Started May 28 01:13:07 PM PDT 24
Finished May 28 01:20:17 PM PDT 24
Peak memory 182584 kb
Host smart-88bd0d40-1dff-43bf-a284-2e92255b1074
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141991709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2141991709
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.235919184
Short name T432
Test name
Test status
Simulation time 361201935110 ps
CPU time 140.6 seconds
Started May 28 01:13:07 PM PDT 24
Finished May 28 01:15:31 PM PDT 24
Peak memory 182572 kb
Host smart-c03e4198-7de8-4152-9e54-83aa5f1ed5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235919184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.235919184
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1382041887
Short name T323
Test name
Test status
Simulation time 51112327452 ps
CPU time 44.78 seconds
Started May 28 01:13:07 PM PDT 24
Finished May 28 01:13:55 PM PDT 24
Peak memory 182580 kb
Host smart-3d80fc84-6f87-4966-8614-034644d4ca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382041887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1382041887
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1311522106
Short name T369
Test name
Test status
Simulation time 616095066723 ps
CPU time 150.08 seconds
Started May 28 01:13:07 PM PDT 24
Finished May 28 01:15:41 PM PDT 24
Peak memory 182516 kb
Host smart-55021fde-6147-4860-937c-f115ac07b04c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311522106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1311522106
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3388001651
Short name T8
Test name
Test status
Simulation time 5258699901137 ps
CPU time 1474.01 seconds
Started May 28 01:13:07 PM PDT 24
Finished May 28 01:37:44 PM PDT 24
Peak memory 182584 kb
Host smart-5b98d70e-0da9-4831-a919-2022af5bcc35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388001651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3388001651
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4272854275
Short name T402
Test name
Test status
Simulation time 125437557453 ps
CPU time 105.06 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:14:58 PM PDT 24
Peak memory 182544 kb
Host smart-eddc690b-b7a1-4274-a5e6-26c7be243ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272854275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4272854275
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.4001621966
Short name T445
Test name
Test status
Simulation time 90912339072 ps
CPU time 500.75 seconds
Started May 28 01:12:59 PM PDT 24
Finished May 28 01:21:21 PM PDT 24
Peak memory 190816 kb
Host smart-e420fea7-d45c-4a8a-b5ba-6e9de83110ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001621966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.4001621966
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3970012357
Short name T244
Test name
Test status
Simulation time 6685978531 ps
CPU time 36.86 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:13:42 PM PDT 24
Peak memory 191128 kb
Host smart-c8f62a81-aef4-40d8-bbb5-dc8ca047fddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970012357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3970012357
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1655273087
Short name T407
Test name
Test status
Simulation time 525923351885 ps
CPU time 419.38 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:20:13 PM PDT 24
Peak memory 190732 kb
Host smart-02f042cf-f0ba-47e7-a543-686cd86d7cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655273087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1655273087
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2271682092
Short name T411
Test name
Test status
Simulation time 170307414729 ps
CPU time 86.28 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:14:39 PM PDT 24
Peak memory 182652 kb
Host smart-c73b3727-80f9-4e4a-908f-8dbb0238312a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271682092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2271682092
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1390440237
Short name T382
Test name
Test status
Simulation time 431895599989 ps
CPU time 187.94 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:16:12 PM PDT 24
Peak memory 182908 kb
Host smart-b73968b7-1eb6-444a-9cf3-2cb50720db97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390440237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1390440237
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1480063600
Short name T116
Test name
Test status
Simulation time 41732438046 ps
CPU time 78.34 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:14:32 PM PDT 24
Peak memory 190724 kb
Host smart-fc00b142-8c1c-421d-8da3-3b54c810a891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480063600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1480063600
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.170261850
Short name T389
Test name
Test status
Simulation time 675732908 ps
CPU time 1.36 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:13:17 PM PDT 24
Peak memory 182588 kb
Host smart-50ebb4ca-4f54-45a2-b180-8898b82c8c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170261850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.170261850
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3964075690
Short name T339
Test name
Test status
Simulation time 59810428769 ps
CPU time 90.58 seconds
Started May 28 01:13:06 PM PDT 24
Finished May 28 01:14:40 PM PDT 24
Peak memory 194516 kb
Host smart-72c2172b-f67e-4261-b9ed-79ecf0688a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964075690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3964075690
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3368209992
Short name T44
Test name
Test status
Simulation time 980047398971 ps
CPU time 504.93 seconds
Started May 28 01:12:27 PM PDT 24
Finished May 28 01:20:55 PM PDT 24
Peak memory 182676 kb
Host smart-b81a5401-b0eb-473d-9ef3-05c9f316998d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368209992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3368209992
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random.2579596408
Short name T131
Test name
Test status
Simulation time 202096778168 ps
CPU time 912.21 seconds
Started May 28 01:12:07 PM PDT 24
Finished May 28 01:27:24 PM PDT 24
Peak memory 190764 kb
Host smart-59e6993e-da80-4554-9d93-03f373fc74f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579596408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2579596408
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.4122090483
Short name T422
Test name
Test status
Simulation time 116978713809 ps
CPU time 492.99 seconds
Started May 28 01:12:24 PM PDT 24
Finished May 28 01:20:39 PM PDT 24
Peak memory 194212 kb
Host smart-54740016-2f98-49b5-960e-a51a640eb82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122090483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4122090483
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2438355318
Short name T259
Test name
Test status
Simulation time 922181242230 ps
CPU time 353.38 seconds
Started May 28 01:12:26 PM PDT 24
Finished May 28 01:18:23 PM PDT 24
Peak memory 190764 kb
Host smart-9a422eea-df68-45c5-96fc-a641e9b9ccb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438355318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2438355318
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3863596221
Short name T379
Test name
Test status
Simulation time 33440548138 ps
CPU time 35.91 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:13:40 PM PDT 24
Peak memory 182912 kb
Host smart-9b31a389-aa7e-4785-8e7a-828880f0686e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863596221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3863596221
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1117242950
Short name T114
Test name
Test status
Simulation time 129264928767 ps
CPU time 160.68 seconds
Started May 28 01:13:06 PM PDT 24
Finished May 28 01:15:55 PM PDT 24
Peak memory 190828 kb
Host smart-096e7fad-9e4e-466b-9cf9-297d195ccc8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117242950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1117242950
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4259607504
Short name T43
Test name
Test status
Simulation time 113483845278 ps
CPU time 258.9 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:17:25 PM PDT 24
Peak memory 190784 kb
Host smart-6aab6022-62cc-48a3-9e4a-7517dde46aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259607504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4259607504
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3103290401
Short name T341
Test name
Test status
Simulation time 380181193610 ps
CPU time 213.98 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:16:39 PM PDT 24
Peak memory 191112 kb
Host smart-b77d14bb-57eb-4709-903d-de3624d5cc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103290401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3103290401
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.914728728
Short name T243
Test name
Test status
Simulation time 229156869213 ps
CPU time 272.15 seconds
Started May 28 01:13:01 PM PDT 24
Finished May 28 01:17:37 PM PDT 24
Peak memory 191108 kb
Host smart-6022ae6e-6494-4ce9-8d1d-8587b3651d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914728728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.914728728
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.628478743
Short name T235
Test name
Test status
Simulation time 70262232085 ps
CPU time 192.44 seconds
Started May 28 01:13:22 PM PDT 24
Finished May 28 01:16:39 PM PDT 24
Peak memory 190788 kb
Host smart-b3434e90-87e8-4cf8-a395-35f62ca4097f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628478743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.628478743
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2890353903
Short name T134
Test name
Test status
Simulation time 368178844055 ps
CPU time 351.9 seconds
Started May 28 01:13:02 PM PDT 24
Finished May 28 01:18:57 PM PDT 24
Peak memory 190808 kb
Host smart-5130916a-2417-42b2-a4d3-68629dac0a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890353903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2890353903
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1914891457
Short name T203
Test name
Test status
Simulation time 251398472721 ps
CPU time 247.45 seconds
Started May 28 01:13:29 PM PDT 24
Finished May 28 01:17:39 PM PDT 24
Peak memory 190812 kb
Host smart-82ba50b5-f32f-4b68-930b-42ffb9170917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914891457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1914891457
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4277810487
Short name T207
Test name
Test status
Simulation time 136936988561 ps
CPU time 109.1 seconds
Started May 28 01:13:33 PM PDT 24
Finished May 28 01:15:23 PM PDT 24
Peak memory 190836 kb
Host smart-c1525891-8075-482b-b4a6-524ffb717fb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277810487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4277810487
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3810551530
Short name T279
Test name
Test status
Simulation time 500298676006 ps
CPU time 825.67 seconds
Started May 28 01:12:28 PM PDT 24
Finished May 28 01:26:16 PM PDT 24
Peak memory 182576 kb
Host smart-e373cc59-2e6d-438f-8415-b180ae91a416
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810551530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3810551530
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3971917136
Short name T427
Test name
Test status
Simulation time 14321782115 ps
CPU time 22.34 seconds
Started May 28 01:12:25 PM PDT 24
Finished May 28 01:12:50 PM PDT 24
Peak memory 182572 kb
Host smart-4e3bf112-5524-42c3-8fdf-aabc6870533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971917136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3971917136
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.885616082
Short name T111
Test name
Test status
Simulation time 156391507830 ps
CPU time 260.09 seconds
Started May 28 01:12:26 PM PDT 24
Finished May 28 01:16:49 PM PDT 24
Peak memory 190820 kb
Host smart-2e8936f9-fbab-4ecb-9aa1-e60cb619280d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885616082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.885616082
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4037961025
Short name T383
Test name
Test status
Simulation time 208535022 ps
CPU time 0.55 seconds
Started May 28 01:12:26 PM PDT 24
Finished May 28 01:12:29 PM PDT 24
Peak memory 182208 kb
Host smart-3cc51d80-3b68-4225-ae54-e24178d6803d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037961025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4037961025
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3439735109
Short name T178
Test name
Test status
Simulation time 414307109892 ps
CPU time 218.15 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:16:52 PM PDT 24
Peak memory 190724 kb
Host smart-c4f54ea9-3dd7-4ab1-a015-69ac65313441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439735109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3439735109
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3743468808
Short name T276
Test name
Test status
Simulation time 204215840005 ps
CPU time 574.1 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:22:56 PM PDT 24
Peak memory 190704 kb
Host smart-ada4cfc4-d82f-426e-bf13-208aa98087e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743468808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3743468808
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.130804782
Short name T319
Test name
Test status
Simulation time 61542885526 ps
CPU time 132.24 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:15:28 PM PDT 24
Peak memory 190832 kb
Host smart-f5a92403-a286-4659-a619-d85f8fb9d468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130804782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.130804782
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3619310398
Short name T9
Test name
Test status
Simulation time 326187841466 ps
CPU time 205.41 seconds
Started May 28 01:13:03 PM PDT 24
Finished May 28 01:16:32 PM PDT 24
Peak memory 190860 kb
Host smart-f75e1e8e-e719-471f-87ea-acad62b4682d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619310398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3619310398
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.771574131
Short name T157
Test name
Test status
Simulation time 47836472834 ps
CPU time 141.05 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:15:35 PM PDT 24
Peak memory 182528 kb
Host smart-f7ec9397-d4cf-4064-87f7-16db29d91db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771574131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.771574131
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1742293287
Short name T257
Test name
Test status
Simulation time 87892845283 ps
CPU time 1125.51 seconds
Started May 28 01:13:31 PM PDT 24
Finished May 28 01:32:19 PM PDT 24
Peak memory 190768 kb
Host smart-9d05bce5-e9b9-4390-8014-45b0b7cb3c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742293287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1742293287
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1288822574
Short name T105
Test name
Test status
Simulation time 125974368901 ps
CPU time 463.27 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:21:09 PM PDT 24
Peak memory 193256 kb
Host smart-4d6ff2bf-15a6-47a1-80dd-47abbd3236bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288822574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1288822574
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.750613176
Short name T113
Test name
Test status
Simulation time 151351795371 ps
CPU time 185.49 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:16:26 PM PDT 24
Peak memory 190764 kb
Host smart-7191a116-ccf1-4097-935a-ed722c3590b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750613176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.750613176
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1745432751
Short name T233
Test name
Test status
Simulation time 333679600396 ps
CPU time 448.8 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:20:45 PM PDT 24
Peak memory 190828 kb
Host smart-200dd4cd-800f-4bfc-a40c-2c004471ef4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745432751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1745432751
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.839605207
Short name T196
Test name
Test status
Simulation time 510289180091 ps
CPU time 286.89 seconds
Started May 28 01:12:27 PM PDT 24
Finished May 28 01:17:17 PM PDT 24
Peak memory 182632 kb
Host smart-18732ea6-bb14-4ced-b27c-fb45faa04a7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839605207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.839605207
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2837410162
Short name T393
Test name
Test status
Simulation time 535405165993 ps
CPU time 164.64 seconds
Started May 28 01:12:26 PM PDT 24
Finished May 28 01:15:13 PM PDT 24
Peak memory 182672 kb
Host smart-328d3860-56e2-41a8-924b-b3adf47d63e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837410162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2837410162
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.568283731
Short name T440
Test name
Test status
Simulation time 472978825390 ps
CPU time 252.51 seconds
Started May 28 01:12:26 PM PDT 24
Finished May 28 01:16:42 PM PDT 24
Peak memory 191784 kb
Host smart-f32d2ccc-a930-4c7b-b70c-5977073e0ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568283731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.568283731
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1168712282
Short name T274
Test name
Test status
Simulation time 97406090764 ps
CPU time 157.68 seconds
Started May 28 01:12:25 PM PDT 24
Finished May 28 01:15:05 PM PDT 24
Peak memory 194428 kb
Host smart-48138320-d22f-4f84-b5c5-5d3d3a003394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168712282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1168712282
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2782590682
Short name T285
Test name
Test status
Simulation time 83818348908 ps
CPU time 49.65 seconds
Started May 28 01:13:08 PM PDT 24
Finished May 28 01:14:01 PM PDT 24
Peak memory 182532 kb
Host smart-5a75a76b-d0e5-42c4-b7da-f79c4b250849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782590682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2782590682
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3661123333
Short name T108
Test name
Test status
Simulation time 64917489520 ps
CPU time 313.46 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:18:29 PM PDT 24
Peak memory 190768 kb
Host smart-e0d982c4-535d-47fd-930d-78a0673f6686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661123333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3661123333
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2742946483
Short name T127
Test name
Test status
Simulation time 134730181742 ps
CPU time 303.31 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:18:27 PM PDT 24
Peak memory 190800 kb
Host smart-c5b29d1d-6c78-40d5-9f93-4c79f149551f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742946483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2742946483
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1157532178
Short name T158
Test name
Test status
Simulation time 228230651961 ps
CPU time 550.19 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:22:24 PM PDT 24
Peak memory 190724 kb
Host smart-e0d6b9f9-3b83-4761-b5c3-b8415fc14985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157532178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1157532178
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.4133726595
Short name T308
Test name
Test status
Simulation time 360257057660 ps
CPU time 102.93 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:15:04 PM PDT 24
Peak memory 190828 kb
Host smart-fa7f9993-3d35-4256-a984-2d24c67ecafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133726595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.4133726595
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1560564465
Short name T343
Test name
Test status
Simulation time 93282914455 ps
CPU time 682.27 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:24:38 PM PDT 24
Peak memory 194368 kb
Host smart-3c250b53-7692-41a3-aa1a-cb5ecfd91b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560564465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1560564465
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1701260832
Short name T120
Test name
Test status
Simulation time 4567102015 ps
CPU time 7.9 seconds
Started May 28 01:13:09 PM PDT 24
Finished May 28 01:13:21 PM PDT 24
Peak memory 182380 kb
Host smart-d20238d7-e154-4517-a251-d27e4b022700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701260832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1701260832
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3804937334
Short name T231
Test name
Test status
Simulation time 179209489033 ps
CPU time 180.79 seconds
Started May 28 01:13:21 PM PDT 24
Finished May 28 01:16:29 PM PDT 24
Peak memory 193132 kb
Host smart-3d06aae3-94f9-469c-aa63-8974dac9634f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804937334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3804937334
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2461933227
Short name T294
Test name
Test status
Simulation time 94354541324 ps
CPU time 75.97 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:14:32 PM PDT 24
Peak memory 182632 kb
Host smart-b9299a5a-1769-49dc-999b-f7e04deee683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461933227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2461933227
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.768966894
Short name T165
Test name
Test status
Simulation time 33444305313 ps
CPU time 51.98 seconds
Started May 28 01:12:21 PM PDT 24
Finished May 28 01:13:15 PM PDT 24
Peak memory 182596 kb
Host smart-a6f50b16-b50e-43da-a789-2234b84f45d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768966894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.768966894
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.389318235
Short name T20
Test name
Test status
Simulation time 98391305733 ps
CPU time 84.61 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:13:49 PM PDT 24
Peak memory 182584 kb
Host smart-a40a91ed-4721-47a3-b2dd-1307ac7f752e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389318235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.389318235
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2544076728
Short name T255
Test name
Test status
Simulation time 64630198777 ps
CPU time 198.59 seconds
Started May 28 01:12:26 PM PDT 24
Finished May 28 01:15:47 PM PDT 24
Peak memory 190760 kb
Host smart-22fa809d-44b9-4afd-b5aa-736906ca2940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544076728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2544076728
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2328317268
Short name T416
Test name
Test status
Simulation time 27891297610 ps
CPU time 54.57 seconds
Started May 28 01:12:23 PM PDT 24
Finished May 28 01:13:25 PM PDT 24
Peak memory 190828 kb
Host smart-52bbf075-71ad-49f6-8951-4127db85e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328317268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2328317268
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1683377688
Short name T91
Test name
Test status
Simulation time 1306219683967 ps
CPU time 597.14 seconds
Started May 28 01:12:28 PM PDT 24
Finished May 28 01:22:28 PM PDT 24
Peak memory 190768 kb
Host smart-e81a0f84-8d15-4d82-83a8-f53cb2f19a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683377688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1683377688
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2786425681
Short name T150
Test name
Test status
Simulation time 587344391531 ps
CPU time 842.65 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:27:24 PM PDT 24
Peak memory 190676 kb
Host smart-baac1133-0c10-4392-bcad-4c149ebe6551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786425681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2786425681
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1075093620
Short name T253
Test name
Test status
Simulation time 60322446068 ps
CPU time 43.8 seconds
Started May 28 01:13:16 PM PDT 24
Finished May 28 01:14:06 PM PDT 24
Peak memory 182636 kb
Host smart-9e1bff15-2717-479f-be84-69afa84a3842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075093620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1075093620
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.223672186
Short name T144
Test name
Test status
Simulation time 92479148791 ps
CPU time 147.16 seconds
Started May 28 01:13:14 PM PDT 24
Finished May 28 01:15:47 PM PDT 24
Peak memory 190764 kb
Host smart-909cdf05-3900-44f2-b1ad-8ec9aab4b004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223672186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.223672186
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2720461123
Short name T327
Test name
Test status
Simulation time 41105108689 ps
CPU time 813.3 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:26:48 PM PDT 24
Peak memory 190828 kb
Host smart-4e10486e-c067-4042-a048-ee457c55cbcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720461123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2720461123
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2778765525
Short name T192
Test name
Test status
Simulation time 55034325618 ps
CPU time 53.15 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:14:16 PM PDT 24
Peak memory 190800 kb
Host smart-44770298-85fa-443f-bf6c-177d7638cea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778765525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2778765525
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3930720680
Short name T347
Test name
Test status
Simulation time 84770224466 ps
CPU time 39.36 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:13:54 PM PDT 24
Peak memory 182636 kb
Host smart-1dbed5ff-3042-4c69-8565-63f24e9a5aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930720680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3930720680
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.4216204615
Short name T174
Test name
Test status
Simulation time 274113219525 ps
CPU time 342.95 seconds
Started May 28 01:13:24 PM PDT 24
Finished May 28 01:19:10 PM PDT 24
Peak memory 190836 kb
Host smart-b4a74233-def5-402f-87de-25ee72b8504e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216204615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.4216204615
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3342756066
Short name T245
Test name
Test status
Simulation time 29444411698 ps
CPU time 14.86 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:13:31 PM PDT 24
Peak memory 182620 kb
Host smart-722606ab-9850-4c71-a925-797aa8c716d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342756066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3342756066
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3724481966
Short name T297
Test name
Test status
Simulation time 242803008572 ps
CPU time 1847.97 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:44:04 PM PDT 24
Peak memory 190768 kb
Host smart-9df32a08-6296-4805-85d0-d71d930983b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724481966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3724481966
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1777027198
Short name T330
Test name
Test status
Simulation time 3730851811495 ps
CPU time 1432.03 seconds
Started May 28 01:12:25 PM PDT 24
Finished May 28 01:36:19 PM PDT 24
Peak memory 182636 kb
Host smart-f9fb52fa-828f-4ef0-a2f2-6037d43f7a37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777027198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1777027198
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1788038671
Short name T357
Test name
Test status
Simulation time 121461687148 ps
CPU time 168.41 seconds
Started May 28 01:12:24 PM PDT 24
Finished May 28 01:15:15 PM PDT 24
Peak memory 182580 kb
Host smart-b5d20171-5bf1-4e09-b8cf-c3a2bf0f671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788038671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1788038671
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2256661167
Short name T390
Test name
Test status
Simulation time 69003719 ps
CPU time 0.55 seconds
Started May 28 01:12:33 PM PDT 24
Finished May 28 01:12:34 PM PDT 24
Peak memory 182364 kb
Host smart-83562ea1-54f8-43cb-8cbc-2ad7dede9612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256661167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2256661167
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1749513717
Short name T194
Test name
Test status
Simulation time 397525746547 ps
CPU time 471.45 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:21:12 PM PDT 24
Peak memory 190712 kb
Host smart-34e5917f-820c-431c-a2ab-0b6ffcfb329d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749513717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1749513717
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.763907239
Short name T160
Test name
Test status
Simulation time 125235500761 ps
CPU time 753.17 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:25:54 PM PDT 24
Peak memory 190804 kb
Host smart-5f78c7ff-e474-4af0-bd40-28f02d745694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763907239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.763907239
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1325493285
Short name T58
Test name
Test status
Simulation time 223719895042 ps
CPU time 128.1 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:15:31 PM PDT 24
Peak memory 190808 kb
Host smart-a711778f-94ba-473b-a4f8-d83a363d6f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325493285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1325493285
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4254373123
Short name T211
Test name
Test status
Simulation time 367197426323 ps
CPU time 519.31 seconds
Started May 28 01:13:15 PM PDT 24
Finished May 28 01:22:00 PM PDT 24
Peak memory 190808 kb
Host smart-b11ae4c1-86b1-4cff-86ef-6984f1819fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254373123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4254373123
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2261463165
Short name T92
Test name
Test status
Simulation time 167680037885 ps
CPU time 599.24 seconds
Started May 28 01:13:10 PM PDT 24
Finished May 28 01:23:14 PM PDT 24
Peak memory 190768 kb
Host smart-2b72003b-81bc-4f07-81c8-09e2766a00b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261463165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2261463165
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.449250687
Short name T155
Test name
Test status
Simulation time 143693806588 ps
CPU time 399.71 seconds
Started May 28 01:13:11 PM PDT 24
Finished May 28 01:19:56 PM PDT 24
Peak memory 190756 kb
Host smart-ac079586-a297-4cce-bb62-d4e42ada7063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449250687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.449250687
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1934208804
Short name T128
Test name
Test status
Simulation time 189581673963 ps
CPU time 503.42 seconds
Started May 28 01:13:17 PM PDT 24
Finished May 28 01:21:46 PM PDT 24
Peak memory 190828 kb
Host smart-d2c74647-e930-44bb-9ca1-eb8f24fd2850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934208804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1934208804
Directory /workspace/99.rv_timer_random/latest
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