Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
114160797 |
1 |
|
T1 |
878284 |
|
T2 |
41175 |
|
T3 |
1819 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53749785 |
1 |
|
T1 |
9114 |
|
T2 |
16792 |
|
T3 |
1819 |
auto[1] |
60411012 |
1 |
|
T1 |
869170 |
|
T2 |
24383 |
|
T4 |
181835 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
114155362 |
1 |
|
T1 |
878265 |
|
T2 |
41171 |
|
T3 |
1815 |
auto[1] |
5435 |
1 |
|
T1 |
19 |
|
T2 |
4 |
|
T3 |
4 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
53747008 |
1 |
|
T1 |
9107 |
|
T2 |
16790 |
|
T3 |
1815 |
all_values[0] |
auto[0] |
auto[1] |
2777 |
1 |
|
T1 |
7 |
|
T2 |
2 |
|
T3 |
4 |
all_values[0] |
auto[1] |
auto[0] |
60408354 |
1 |
|
T1 |
869158 |
|
T2 |
24381 |
|
T4 |
181831 |
all_values[0] |
auto[1] |
auto[1] |
2658 |
1 |
|
T1 |
12 |
|
T2 |
2 |
|
T4 |
4 |