| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.55 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.21 |
| T510 | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1080935613 | May 30 12:36:42 PM PDT 24 | May 30 12:36:44 PM PDT 24 | 35547937 ps | ||
| T511 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3484986107 | May 30 12:36:15 PM PDT 24 | May 30 12:36:18 PM PDT 24 | 321242715 ps | ||
| T78 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3623189198 | May 30 12:36:16 PM PDT 24 | May 30 12:36:20 PM PDT 24 | 91357450 ps | ||
| T512 | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4018272190 | May 30 12:36:40 PM PDT 24 | May 30 12:36:42 PM PDT 24 | 60028085 ps | ||
| T513 | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2798351584 | May 30 12:36:33 PM PDT 24 | May 30 12:36:35 PM PDT 24 | 337583504 ps | ||
| T514 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2919607196 | May 30 12:36:21 PM PDT 24 | May 30 12:36:22 PM PDT 24 | 29349648 ps | ||
| T79 | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3609871610 | May 30 12:36:40 PM PDT 24 | May 30 12:36:42 PM PDT 24 | 21081203 ps | ||
| T515 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.973824025 | May 30 12:36:25 PM PDT 24 | May 30 12:36:27 PM PDT 24 | 14698078 ps | ||
| T516 | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2107129217 | May 30 12:36:47 PM PDT 24 | May 30 12:36:48 PM PDT 24 | 49044562 ps | ||
| T517 | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1198306822 | May 30 12:36:17 PM PDT 24 | May 30 12:36:21 PM PDT 24 | 209521054 ps | ||
| T518 | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1514956900 | May 30 12:36:26 PM PDT 24 | May 30 12:36:28 PM PDT 24 | 32063097 ps | ||
| T519 | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1929705015 | May 30 12:36:43 PM PDT 24 | May 30 12:36:44 PM PDT 24 | 16556802 ps | ||
| T520 | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1326048024 | May 30 12:36:38 PM PDT 24 | May 30 12:36:41 PM PDT 24 | 108748820 ps | ||
| T521 | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.67670756 | May 30 12:37:00 PM PDT 24 | May 30 12:37:02 PM PDT 24 | 54490980 ps | ||
| T522 | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3634825741 | May 30 12:36:15 PM PDT 24 | May 30 12:36:18 PM PDT 24 | 68802443 ps | ||
| T80 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1163456720 | May 30 12:36:25 PM PDT 24 | May 30 12:36:26 PM PDT 24 | 39850080 ps | ||
| T523 | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2760488116 | May 30 12:36:34 PM PDT 24 | May 30 12:36:36 PM PDT 24 | 25089725 ps | ||
| T524 | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.360647874 | May 30 12:36:34 PM PDT 24 | May 30 12:36:36 PM PDT 24 | 11060269 ps | ||
| T525 | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.837027098 | May 30 12:36:29 PM PDT 24 | May 30 12:36:31 PM PDT 24 | 18470867 ps | ||
| T526 | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1213812834 | May 30 12:36:40 PM PDT 24 | May 30 12:36:42 PM PDT 24 | 41088595 ps | ||
| T527 | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1381763565 | May 30 12:36:37 PM PDT 24 | May 30 12:36:38 PM PDT 24 | 50349525 ps | ||
| T528 | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3338247243 | May 30 12:36:37 PM PDT 24 | May 30 12:36:39 PM PDT 24 | 16897044 ps | ||
| T81 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.935379244 | May 30 12:36:27 PM PDT 24 | May 30 12:36:28 PM PDT 24 | 24131335 ps | ||
| T529 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1493428976 | May 30 12:36:17 PM PDT 24 | May 30 12:36:19 PM PDT 24 | 37935295 ps | ||
| T530 | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3848151439 | May 30 12:36:44 PM PDT 24 | May 30 12:36:46 PM PDT 24 | 14891744 ps | ||
| T531 | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.681028233 | May 30 12:36:41 PM PDT 24 | May 30 12:36:44 PM PDT 24 | 41510851 ps | ||
| T532 | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2545257337 | May 30 12:36:39 PM PDT 24 | May 30 12:36:41 PM PDT 24 | 370915549 ps | ||
| T533 | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1105680509 | May 30 12:36:37 PM PDT 24 | May 30 12:36:39 PM PDT 24 | 24570537 ps | ||
| T534 | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1674005379 | May 30 12:36:39 PM PDT 24 | May 30 12:36:41 PM PDT 24 | 17707109 ps | ||
| T535 | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2823782075 | May 30 12:36:35 PM PDT 24 | May 30 12:36:38 PM PDT 24 | 117665671 ps | ||
| T536 | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.202991921 | May 30 12:36:38 PM PDT 24 | May 30 12:36:40 PM PDT 24 | 42468241 ps | ||
| T537 | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2497209675 | May 30 12:36:34 PM PDT 24 | May 30 12:36:36 PM PDT 24 | 48864818 ps | ||
| T538 | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3717471313 | May 30 12:36:33 PM PDT 24 | May 30 12:36:35 PM PDT 24 | 107828010 ps | ||
| T539 | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1406882404 | May 30 12:36:29 PM PDT 24 | May 30 12:36:31 PM PDT 24 | 51925155 ps | ||
| T540 | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1237486594 | May 30 12:36:40 PM PDT 24 | May 30 12:36:42 PM PDT 24 | 12186033 ps | ||
| T541 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1986750459 | May 30 12:36:15 PM PDT 24 | May 30 12:36:17 PM PDT 24 | 47912478 ps | ||
| T542 | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3241653449 | May 30 12:36:17 PM PDT 24 | May 30 12:36:20 PM PDT 24 | 201434936 ps | ||
| T82 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2092788780 | May 30 12:36:23 PM PDT 24 | May 30 12:36:25 PM PDT 24 | 15830403 ps | ||
| T543 | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2633841394 | May 30 12:36:35 PM PDT 24 | May 30 12:36:37 PM PDT 24 | 36202829 ps | ||
| T544 | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4108472248 | May 30 12:36:36 PM PDT 24 | May 30 12:36:37 PM PDT 24 | 11887698 ps | ||
| T545 | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3855484014 | May 30 12:36:25 PM PDT 24 | May 30 12:36:27 PM PDT 24 | 403600385 ps | ||
| T546 | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.963237250 | May 30 12:36:20 PM PDT 24 | May 30 12:36:22 PM PDT 24 | 100242045 ps | ||
| T547 | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3514974899 | May 30 12:36:27 PM PDT 24 | May 30 12:36:30 PM PDT 24 | 59501525 ps | ||
| T548 | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1010994831 | May 30 12:36:41 PM PDT 24 | May 30 12:36:43 PM PDT 24 | 78832055 ps | ||
| T549 | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3250220323 | May 30 12:36:34 PM PDT 24 | May 30 12:36:37 PM PDT 24 | 200278716 ps | ||
| T550 | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4249445011 | May 30 12:36:37 PM PDT 24 | May 30 12:36:38 PM PDT 24 | 42641163 ps | ||
| T551 | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1961714641 | May 30 12:36:40 PM PDT 24 | May 30 12:36:42 PM PDT 24 | 371937338 ps | ||
| T552 | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2912088388 | May 30 12:36:40 PM PDT 24 | May 30 12:36:42 PM PDT 24 | 54167123 ps | ||
| T553 | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4085774287 | May 30 12:36:32 PM PDT 24 | May 30 12:36:34 PM PDT 24 | 81387453 ps | ||
| T554 | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3870931548 | May 30 12:36:17 PM PDT 24 | May 30 12:36:19 PM PDT 24 | 18222946 ps | ||
| T83 | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2201976186 | May 30 12:36:33 PM PDT 24 | May 30 12:36:35 PM PDT 24 | 16834747 ps | ||
| T85 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4183683647 | May 30 12:36:34 PM PDT 24 | May 30 12:36:38 PM PDT 24 | 814524446 ps | ||
| T555 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3984421174 | May 30 12:36:18 PM PDT 24 | May 30 12:36:20 PM PDT 24 | 48863267 ps | ||
| T556 | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3510295776 | May 30 12:36:43 PM PDT 24 | May 30 12:36:45 PM PDT 24 | 228167669 ps | ||
| T557 | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1368647375 | May 30 12:36:14 PM PDT 24 | May 30 12:36:16 PM PDT 24 | 106294055 ps | ||
| T558 | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.469205073 | May 30 12:36:18 PM PDT 24 | May 30 12:36:20 PM PDT 24 | 49675181 ps | ||
| T86 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3997855623 | May 30 12:36:32 PM PDT 24 | May 30 12:36:34 PM PDT 24 | 19353563 ps | ||
| T559 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1400917837 | May 30 12:36:22 PM PDT 24 | May 30 12:36:25 PM PDT 24 | 17299689 ps | ||
| T560 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1505272458 | May 30 12:36:19 PM PDT 24 | May 30 12:36:21 PM PDT 24 | 170549572 ps | ||
| T94 | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2095536049 | May 30 12:36:28 PM PDT 24 | May 30 12:36:31 PM PDT 24 | 118107823 ps | ||
| T561 | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4198093382 | May 30 12:36:28 PM PDT 24 | May 30 12:36:30 PM PDT 24 | 251030754 ps | ||
| T562 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3776034845 | May 30 12:36:27 PM PDT 24 | May 30 12:36:28 PM PDT 24 | 21556070 ps | ||
| T563 | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1381573699 | May 30 12:36:38 PM PDT 24 | May 30 12:36:40 PM PDT 24 | 10994309 ps | ||
| T564 | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2145079703 | May 30 12:36:26 PM PDT 24 | May 30 12:36:28 PM PDT 24 | 120482757 ps | ||
| T565 | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1570881069 | May 30 12:36:43 PM PDT 24 | May 30 12:36:45 PM PDT 24 | 39801982 ps | ||
| T566 | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.41081715 | May 30 12:36:47 PM PDT 24 | May 30 12:36:48 PM PDT 24 | 41529014 ps | ||
| T567 | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3196532922 | May 30 12:36:26 PM PDT 24 | May 30 12:36:28 PM PDT 24 | 37774103 ps | ||
| T568 | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2708580683 | May 30 12:36:25 PM PDT 24 | May 30 12:36:27 PM PDT 24 | 20341337 ps | ||
| T569 | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.640866067 | May 30 12:36:31 PM PDT 24 | May 30 12:36:33 PM PDT 24 | 39020744 ps | ||
| T570 | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1715946154 | May 30 12:36:24 PM PDT 24 | May 30 12:36:26 PM PDT 24 | 14696785 ps | ||
| T571 | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3027976251 | May 30 12:36:17 PM PDT 24 | May 30 12:36:19 PM PDT 24 | 39789897 ps | ||
| T572 | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2889681195 | May 30 12:36:34 PM PDT 24 | May 30 12:36:36 PM PDT 24 | 19715448 ps | ||
| T573 | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3961495602 | May 30 12:36:29 PM PDT 24 | May 30 12:36:31 PM PDT 24 | 157612824 ps | ||
| T574 | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3294958268 | May 30 12:36:21 PM PDT 24 | May 30 12:36:23 PM PDT 24 | 18057883 ps | ||
| T575 | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1775824466 | May 30 12:36:34 PM PDT 24 | May 30 12:36:36 PM PDT 24 | 11104329 ps | ||
| T576 | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2432638744 | May 30 12:36:28 PM PDT 24 | May 30 12:36:30 PM PDT 24 | 43527802 ps |
| Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2317418440 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1298943496482 ps |
| CPU time | 1204.26 seconds |
| Started | May 30 12:37:04 PM PDT 24 |
| Finished | May 30 12:57:10 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-81675882-f43d-4247-a119-ffc8cdc81566 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317418440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.2317418440 |
| Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3236707775 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 147273928180 ps |
| CPU time | 1044.18 seconds |
| Started | May 30 12:36:57 PM PDT 24 |
| Finished | May 30 12:54:23 PM PDT 24 |
| Peak memory | 208920 kb |
| Host | smart-577ba476-3b20-4b16-984b-fa4f72b78b5d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236707775 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3236707775 |
| Directory | /workspace/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.rv_timer_stress_all.3984478157 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 491133729542 ps |
| CPU time | 1202.32 seconds |
| Started | May 30 12:37:04 PM PDT 24 |
| Finished | May 30 12:57:08 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-a59e8761-0692-46e0-8c8d-9bf32bf01683 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984478157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 3984478157 |
| Directory | /workspace/9.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1747427173 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 44717740 ps |
| CPU time | 0.8 seconds |
| Started | May 30 12:36:32 PM PDT 24 |
| Finished | May 30 12:36:34 PM PDT 24 |
| Peak memory | 182860 kb |
| Host | smart-0c7e0dc2-3f96-480f-ba06-6c1f24a880e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747427173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i ntg_err.1747427173 |
| Directory | /workspace/10.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/3.rv_timer_stress_all.1009536947 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3311555924381 ps |
| CPU time | 1862.45 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 01:07:49 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-1c6ce57b-cd28-4636-8d82-d7976d2a42ff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009536947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 1009536947 |
| Directory | /workspace/3.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/7.rv_timer_stress_all.3560147071 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2180260532389 ps |
| CPU time | 1016.69 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:53:43 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-61415027-cf2a-42ac-b39f-1c0a060ac70b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560147071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all. 3560147071 |
| Directory | /workspace/7.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/14.rv_timer_stress_all.3809448216 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2787790496150 ps |
| CPU time | 2446.18 seconds |
| Started | May 30 12:36:58 PM PDT 24 |
| Finished | May 30 01:17:46 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-2cb3548c-a79f-41a4-b839-a81045288c4c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809448216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all .3809448216 |
| Directory | /workspace/14.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/29.rv_timer_stress_all.2698557447 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 1086122513460 ps |
| CPU time | 2814.8 seconds |
| Started | May 30 12:37:15 PM PDT 24 |
| Finished | May 30 01:24:10 PM PDT 24 |
| Peak memory | 191048 kb |
| Host | smart-52945be0-cd4e-4732-aad3-ef7700a4357d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698557447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .2698557447 |
| Directory | /workspace/29.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/48.rv_timer_stress_all.1956822130 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4728365233594 ps |
| CPU time | 1097.38 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:55:45 PM PDT 24 |
| Peak memory | 191056 kb |
| Host | smart-6af60104-1839-41cc-bb17-de0280020443 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956822130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all .1956822130 |
| Directory | /workspace/48.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.rv_timer_stress_all.4008861235 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1676850719483 ps |
| CPU time | 1700.19 seconds |
| Started | May 30 12:37:23 PM PDT 24 |
| Finished | May 30 01:05:44 PM PDT 24 |
| Peak memory | 196340 kb |
| Host | smart-ecb9f170-13a0-4747-8a13-3f4e4dd4917e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008861235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all .4008861235 |
| Directory | /workspace/32.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/20.rv_timer_stress_all.649679511 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 2404718877607 ps |
| CPU time | 1617.61 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 01:04:18 PM PDT 24 |
| Peak memory | 191056 kb |
| Host | smart-9bb09d6c-5362-4cff-893b-5dcf4841b73e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649679511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all. 649679511 |
| Directory | /workspace/20.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/6.rv_timer_stress_all.2938302572 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3042561769719 ps |
| CPU time | 2075.41 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 01:11:23 PM PDT 24 |
| Peak memory | 195736 kb |
| Host | smart-8b671722-f458-4956-89dc-7c30809eb61e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938302572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all. 2938302572 |
| Directory | /workspace/6.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/16.rv_timer_stress_all.931536567 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1325858414931 ps |
| CPU time | 3006.07 seconds |
| Started | May 30 12:37:15 PM PDT 24 |
| Finished | May 30 01:27:22 PM PDT 24 |
| Peak memory | 191048 kb |
| Host | smart-ce0bebc0-1c31-4db1-a455-9ae380bba95f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931536567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all. 931536567 |
| Directory | /workspace/16.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.8343107 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 93777019 ps |
| CPU time | 0.52 seconds |
| Started | May 30 12:36:22 PM PDT 24 |
| Finished | May 30 12:36:24 PM PDT 24 |
| Peak memory | 182328 kb |
| Host | smart-28ec76a5-e2f3-403b-a90d-1070fb72ab28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8343107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.8343107 |
| Directory | /workspace/0.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/default/49.rv_timer_stress_all.421979822 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 390704633499 ps |
| CPU time | 1275.73 seconds |
| Started | May 30 12:37:31 PM PDT 24 |
| Finished | May 30 12:58:48 PM PDT 24 |
| Peak memory | 191192 kb |
| Host | smart-e599c2ea-d48a-4155-895f-fba0b88f1eb4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421979822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all. 421979822 |
| Directory | /workspace/49.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/0.rv_timer_sec_cm.4101466246 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 321530049 ps |
| CPU time | 0.96 seconds |
| Started | May 30 12:36:49 PM PDT 24 |
| Finished | May 30 12:36:51 PM PDT 24 |
| Peak memory | 213324 kb |
| Host | smart-a92d5b84-3e70-4a98-b095-6bbf272b2c80 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101466246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.4101466246 |
| Directory | /workspace/0.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/23.rv_timer_stress_all.1705300548 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 1108100020250 ps |
| CPU time | 932.98 seconds |
| Started | May 30 12:37:11 PM PDT 24 |
| Finished | May 30 12:52:45 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-8f18d902-8af1-4ebc-bf25-3e6261fa5fab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705300548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .1705300548 |
| Directory | /workspace/23.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all.1050431602 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 1326784238856 ps |
| CPU time | 1072.65 seconds |
| Started | May 30 12:37:18 PM PDT 24 |
| Finished | May 30 12:55:12 PM PDT 24 |
| Peak memory | 195516 kb |
| Host | smart-c9a67a98-fc19-41f8-b4cf-71c7b04d0932 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050431602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .1050431602 |
| Directory | /workspace/37.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/12.rv_timer_stress_all.1916834653 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 266622750172 ps |
| CPU time | 953.54 seconds |
| Started | May 30 12:37:09 PM PDT 24 |
| Finished | May 30 12:53:03 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-732fba73-ab04-4034-81a6-ad8a495468c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916834653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .1916834653 |
| Directory | /workspace/12.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/28.rv_timer_stress_all.2598386697 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1304000775414 ps |
| CPU time | 1475.47 seconds |
| Started | May 30 12:37:09 PM PDT 24 |
| Finished | May 30 01:01:45 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-85aa9f05-4851-4f3f-b684-e154b2542f0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598386697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all .2598386697 |
| Directory | /workspace/28.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/92.rv_timer_random.348111617 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 146337627935 ps |
| CPU time | 1653.67 seconds |
| Started | May 30 12:37:38 PM PDT 24 |
| Finished | May 30 01:05:17 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-792d3b16-1cd5-40f9-a5e1-02e20b875b44 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348111617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.348111617 |
| Directory | /workspace/92.rv_timer_random/latest |
| Test location | /workspace/coverage/default/176.rv_timer_random.3059463697 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2832646314256 ps |
| CPU time | 547.51 seconds |
| Started | May 30 12:37:42 PM PDT 24 |
| Finished | May 30 12:46:50 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-4f5d2acd-9de2-4e45-8745-c1d1c97b3208 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059463697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3059463697 |
| Directory | /workspace/176.rv_timer_random/latest |
| Test location | /workspace/coverage/default/177.rv_timer_random.1910499974 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 472890382209 ps |
| CPU time | 626.18 seconds |
| Started | May 30 12:37:42 PM PDT 24 |
| Finished | May 30 12:48:09 PM PDT 24 |
| Peak memory | 191048 kb |
| Host | smart-bf03bdae-9cce-4c55-a14c-0c7edeb5d6a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910499974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1910499974 |
| Directory | /workspace/177.rv_timer_random/latest |
| Test location | /workspace/coverage/default/85.rv_timer_random.1427941848 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 147721944976 ps |
| CPU time | 490.74 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:45:39 PM PDT 24 |
| Peak memory | 194364 kb |
| Host | smart-042d1987-98eb-4d27-9895-de6e5fd4f494 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427941848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1427941848 |
| Directory | /workspace/85.rv_timer_random/latest |
| Test location | /workspace/coverage/default/103.rv_timer_random.2001032685 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 68871482311 ps |
| CPU time | 114.54 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:39:29 PM PDT 24 |
| Peak memory | 190280 kb |
| Host | smart-9d1cf7dc-4805-47ed-a8dd-2d0daee0fefa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001032685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2001032685 |
| Directory | /workspace/103.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_stress_all.414370750 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 791777460030 ps |
| CPU time | 1467.98 seconds |
| Started | May 30 12:36:56 PM PDT 24 |
| Finished | May 30 01:01:26 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-f4415550-60d4-42b4-ba77-8cba45e50263 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414370750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all. 414370750 |
| Directory | /workspace/13.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/143.rv_timer_random.1697549171 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 122394810598 ps |
| CPU time | 188.4 seconds |
| Started | May 30 12:37:38 PM PDT 24 |
| Finished | May 30 12:40:48 PM PDT 24 |
| Peak memory | 193972 kb |
| Host | smart-b1fe6dba-205d-41eb-adc5-62feed738f96 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697549171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1697549171 |
| Directory | /workspace/143.rv_timer_random/latest |
| Test location | /workspace/coverage/default/189.rv_timer_random.4004657404 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 141880999010 ps |
| CPU time | 287.4 seconds |
| Started | May 30 12:37:43 PM PDT 24 |
| Finished | May 30 12:42:32 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-e120fd01-8270-43ca-8294-f77274674f11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004657404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4004657404 |
| Directory | /workspace/189.rv_timer_random/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random.336913544 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 240303424266 ps |
| CPU time | 724.39 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:49:33 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-0dbc29ea-071d-4e11-a98c-ca84b7685b8d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336913544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.336913544 |
| Directory | /workspace/41.rv_timer_random/latest |
| Test location | /workspace/coverage/default/46.rv_timer_stress_all.2553323082 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 493616217944 ps |
| CPU time | 1389 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 01:00:40 PM PDT 24 |
| Peak memory | 191076 kb |
| Host | smart-d449f661-a1dd-49a7-accb-6420e8beb582 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553323082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all .2553323082 |
| Directory | /workspace/46.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/47.rv_timer_stress_all.698276031 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 6430645711518 ps |
| CPU time | 1321.97 seconds |
| Started | May 30 12:37:41 PM PDT 24 |
| Finished | May 30 12:59:44 PM PDT 24 |
| Peak memory | 195784 kb |
| Host | smart-9025e610-138c-4580-94a9-960dc6f0670a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698276031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all. 698276031 |
| Directory | /workspace/47.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/109.rv_timer_random.1813428145 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 161368265578 ps |
| CPU time | 439.52 seconds |
| Started | May 30 12:37:38 PM PDT 24 |
| Finished | May 30 12:44:59 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-2f5e5061-78a3-4f1f-8b30-4e40cfa02dd8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813428145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1813428145 |
| Directory | /workspace/109.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random.3236995403 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1252310754586 ps |
| CPU time | 324.34 seconds |
| Started | May 30 12:36:53 PM PDT 24 |
| Finished | May 30 12:42:19 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-b16559ca-9207-465c-8fdb-72a062560376 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236995403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3236995403 |
| Directory | /workspace/11.rv_timer_random/latest |
| Test location | /workspace/coverage/default/139.rv_timer_random.87687975 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 145152580620 ps |
| CPU time | 195.95 seconds |
| Started | May 30 12:37:28 PM PDT 24 |
| Finished | May 30 12:40:45 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-4528e091-4950-41d1-b4ae-7be1bd3161bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87687975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.87687975 |
| Directory | /workspace/139.rv_timer_random/latest |
| Test location | /workspace/coverage/default/163.rv_timer_random.102929067 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 142599973755 ps |
| CPU time | 417.14 seconds |
| Started | May 30 12:37:45 PM PDT 24 |
| Finished | May 30 12:44:43 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-16b819d7-05b3-4a05-8ac3-f32eeb3ea962 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102929067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.102929067 |
| Directory | /workspace/163.rv_timer_random/latest |
| Test location | /workspace/coverage/default/172.rv_timer_random.2109906112 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 293252528863 ps |
| CPU time | 548.81 seconds |
| Started | May 30 12:37:42 PM PDT 24 |
| Finished | May 30 12:46:52 PM PDT 24 |
| Peak memory | 191044 kb |
| Host | smart-3098ddcf-e9b0-443f-a7ab-a0772f13c36e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109906112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2109906112 |
| Directory | /workspace/172.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_stress_all.1377307424 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 437188216128 ps |
| CPU time | 1133.55 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:56:29 PM PDT 24 |
| Peak memory | 191024 kb |
| Host | smart-88e7384c-7f1d-4b93-a78c-2c7c12e2b0fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377307424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .1377307424 |
| Directory | /workspace/39.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/118.rv_timer_random.720175012 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1103959784198 ps |
| CPU time | 605.9 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:47:39 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-0883a4b9-cefe-474b-aa50-4d7cfe348f50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720175012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.720175012 |
| Directory | /workspace/118.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random.4018090350 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 309474102185 ps |
| CPU time | 602.34 seconds |
| Started | May 30 12:37:09 PM PDT 24 |
| Finished | May 30 12:47:12 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-9ba29e2d-432d-4f6b-9496-8c1693726288 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018090350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4018090350 |
| Directory | /workspace/16.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_stress_all.2727926550 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 316525317339 ps |
| CPU time | 737.86 seconds |
| Started | May 30 12:36:55 PM PDT 24 |
| Finished | May 30 12:49:15 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-51a03438-0907-4f0e-b268-a15a5b275de9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727926550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 2727926550 |
| Directory | /workspace/2.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random.3107674425 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 174163647432 ps |
| CPU time | 510.51 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:45:53 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-e3d5c3d0-1c9e-4099-b81b-f3da0342dd8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107674425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3107674425 |
| Directory | /workspace/32.rv_timer_random/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random.1511836099 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 316856694312 ps |
| CPU time | 454.41 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:45:09 PM PDT 24 |
| Peak memory | 190992 kb |
| Host | smart-f5b65d50-1ee9-4f2f-8e18-3f4bb5882035 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511836099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1511836099 |
| Directory | /workspace/34.rv_timer_random/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random.2381646134 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 226453300757 ps |
| CPU time | 584.86 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:47:12 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-1b045091-6da1-4158-8058-507309642b64 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381646134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2381646134 |
| Directory | /workspace/39.rv_timer_random/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random.498174081 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 205925884034 ps |
| CPU time | 421.26 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:43:47 PM PDT 24 |
| Peak memory | 191112 kb |
| Host | smart-8fb8abb5-46d6-47bb-9ead-afecd4ddc304 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498174081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.498174081 |
| Directory | /workspace/1.rv_timer_random/latest |
| Test location | /workspace/coverage/default/129.rv_timer_random.196065837 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 167878512838 ps |
| CPU time | 175.55 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:40:27 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-46a44a18-a989-408e-b565-1d69902c5c85 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196065837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.196065837 |
| Directory | /workspace/129.rv_timer_random/latest |
| Test location | /workspace/coverage/default/138.rv_timer_random.3075234024 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 91848012332 ps |
| CPU time | 190.91 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 12:40:51 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-56c85072-2a91-4d26-a828-6869c830a1a3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075234024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3075234024 |
| Directory | /workspace/138.rv_timer_random/latest |
| Test location | /workspace/coverage/default/141.rv_timer_random.1374571336 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 125091932303 ps |
| CPU time | 213.83 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:41:08 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-54a4e581-2504-4a70-8c91-4a8eb2a0a80b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374571336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1374571336 |
| Directory | /workspace/141.rv_timer_random/latest |
| Test location | /workspace/coverage/default/148.rv_timer_random.1691310639 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1139109464678 ps |
| CPU time | 338.79 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:43:16 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-a691ad41-62bf-4544-8ce3-f1c29a5d6609 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691310639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1691310639 |
| Directory | /workspace/148.rv_timer_random/latest |
| Test location | /workspace/coverage/default/188.rv_timer_random.3543773350 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 740700092492 ps |
| CPU time | 617.14 seconds |
| Started | May 30 12:37:51 PM PDT 24 |
| Finished | May 30 12:48:09 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-63f69506-cb2f-4fbb-97b4-3bcf19bc6f59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543773350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3543773350 |
| Directory | /workspace/188.rv_timer_random/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random.3622414859 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 941686725523 ps |
| CPU time | 500.31 seconds |
| Started | May 30 12:37:07 PM PDT 24 |
| Finished | May 30 12:45:29 PM PDT 24 |
| Peak memory | 191040 kb |
| Host | smart-598ac681-90b6-4720-9f4f-df017a1056d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622414859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3622414859 |
| Directory | /workspace/22.rv_timer_random/latest |
| Test location | /workspace/coverage/default/52.rv_timer_random.3215700742 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 95566938409 ps |
| CPU time | 385 seconds |
| Started | May 30 12:37:37 PM PDT 24 |
| Finished | May 30 12:44:03 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-32fa26b2-5561-4f7c-be2e-c489fc7fa9ff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215700742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3215700742 |
| Directory | /workspace/52.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1668830948 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 100766771 ps |
| CPU time | 0.7 seconds |
| Started | May 30 12:36:20 PM PDT 24 |
| Finished | May 30 12:36:22 PM PDT 24 |
| Peak memory | 192996 kb |
| Host | smart-8877e170-28f9-4f9b-8ccd-d8879a8630f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668830948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti mer_same_csr_outstanding.1668830948 |
| Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.935379244 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 24131335 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:36:27 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 182644 kb |
| Host | smart-b40b90d2-ffd4-4290-9e63-85b44024ae68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935379244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.935379244 |
| Directory | /workspace/1.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/default/1.rv_timer_random_reset.1277906779 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 42047359147 ps |
| CPU time | 68.12 seconds |
| Started | May 30 12:36:44 PM PDT 24 |
| Finished | May 30 12:37:54 PM PDT 24 |
| Peak memory | 182724 kb |
| Host | smart-32fdadbb-653d-410c-8643-3824ac2965b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1277906779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1277906779 |
| Directory | /workspace/1.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/100.rv_timer_random.1918200253 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 700081042718 ps |
| CPU time | 916.95 seconds |
| Started | May 30 12:37:43 PM PDT 24 |
| Finished | May 30 12:53:01 PM PDT 24 |
| Peak memory | 194564 kb |
| Host | smart-c24d34d6-ec38-48f7-b74d-2ccac6b9b10b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918200253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1918200253 |
| Directory | /workspace/100.rv_timer_random/latest |
| Test location | /workspace/coverage/default/112.rv_timer_random.1014093609 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 298455914582 ps |
| CPU time | 412.76 seconds |
| Started | May 30 12:37:35 PM PDT 24 |
| Finished | May 30 12:44:29 PM PDT 24 |
| Peak memory | 191040 kb |
| Host | smart-8cade3b6-8aa9-4368-ac1d-e7a05bb6fcd6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014093609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1014093609 |
| Directory | /workspace/112.rv_timer_random/latest |
| Test location | /workspace/coverage/default/113.rv_timer_random.1510652896 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 96621379724 ps |
| CPU time | 64.02 seconds |
| Started | May 30 12:37:41 PM PDT 24 |
| Finished | May 30 12:38:47 PM PDT 24 |
| Peak memory | 191048 kb |
| Host | smart-67269d3b-39f7-4b45-bc94-74fe89ab2efe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510652896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1510652896 |
| Directory | /workspace/113.rv_timer_random/latest |
| Test location | /workspace/coverage/default/128.rv_timer_random.3809708815 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 115930281749 ps |
| CPU time | 1298.66 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 12:59:19 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-b4c72e3a-05e3-498b-bd1a-33f754a7dfdc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809708815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3809708815 |
| Directory | /workspace/128.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random_reset.168811433 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 133755605010 ps |
| CPU time | 263.46 seconds |
| Started | May 30 12:37:14 PM PDT 24 |
| Finished | May 30 12:41:38 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-2c15a9ea-4531-409c-b911-003ca04e1c7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168811433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.168811433 |
| Directory | /workspace/13.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/132.rv_timer_random.368372905 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 427335635297 ps |
| CPU time | 383.87 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:43:59 PM PDT 24 |
| Peak memory | 193592 kb |
| Host | smart-66692a6f-d4bf-4b1b-8137-204ed4e714f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368372905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.368372905 |
| Directory | /workspace/132.rv_timer_random/latest |
| Test location | /workspace/coverage/default/149.rv_timer_random.2321078250 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 101820132690 ps |
| CPU time | 402.39 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:44:17 PM PDT 24 |
| Peak memory | 191012 kb |
| Host | smart-1975f015-8498-43d4-8971-ba48285bbef9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321078250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2321078250 |
| Directory | /workspace/149.rv_timer_random/latest |
| Test location | /workspace/coverage/default/154.rv_timer_random.2527044789 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 1011550194109 ps |
| CPU time | 732.19 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 12:49:52 PM PDT 24 |
| Peak memory | 191048 kb |
| Host | smart-6d9a496b-8e86-4ee5-859b-8b335e2a5cd5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527044789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2527044789 |
| Directory | /workspace/154.rv_timer_random/latest |
| Test location | /workspace/coverage/default/165.rv_timer_random.1491269355 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 492523288587 ps |
| CPU time | 248.31 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 12:41:48 PM PDT 24 |
| Peak memory | 190744 kb |
| Host | smart-8c7d2b98-e23d-44b6-a815-ca5cfc7f47be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491269355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1491269355 |
| Directory | /workspace/165.rv_timer_random/latest |
| Test location | /workspace/coverage/default/190.rv_timer_random.21337882 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 68984047557 ps |
| CPU time | 231.44 seconds |
| Started | May 30 12:37:44 PM PDT 24 |
| Finished | May 30 12:41:36 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-e910d50f-fcb2-4589-a806-6c6986c686bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21337882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.21337882 |
| Directory | /workspace/190.rv_timer_random/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random.605338734 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 106850119757 ps |
| CPU time | 417.08 seconds |
| Started | May 30 12:37:10 PM PDT 24 |
| Finished | May 30 12:44:08 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-291addbf-1d91-40a0-80e5-19927a082291 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605338734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.605338734 |
| Directory | /workspace/24.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random_reset.1376824314 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 378134983521 ps |
| CPU time | 250.79 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:41:36 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-7d4dddae-bd95-456b-a254-426bff5bdac0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376824314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1376824314 |
| Directory | /workspace/25.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/27.rv_timer_stress_all.3002579585 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 216888234613 ps |
| CPU time | 343.6 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:43:01 PM PDT 24 |
| Peak memory | 182824 kb |
| Host | smart-7a6416d5-b971-4abf-97d9-dc165aacdc56 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002579585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .3002579585 |
| Directory | /workspace/27.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random_reset.347370620 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 60095296296 ps |
| CPU time | 116.33 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:39:21 PM PDT 24 |
| Peak memory | 191024 kb |
| Host | smart-6c6ca671-1c41-4f69-8444-250d8310167f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347370620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.347370620 |
| Directory | /workspace/37.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all.2824100460 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 345319732374 ps |
| CPU time | 1565.37 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 01:03:38 PM PDT 24 |
| Peak memory | 191112 kb |
| Host | smart-b2ddef19-6b0e-441d-8e96-68a3d9b95fef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824100460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all .2824100460 |
| Directory | /workspace/41.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random.618275801 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 389552647366 ps |
| CPU time | 322.12 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:42:54 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-5e3f754f-426c-4003-b448-53dfad2ee9ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618275801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.618275801 |
| Directory | /workspace/45.rv_timer_random/latest |
| Test location | /workspace/coverage/default/51.rv_timer_random.1826062031 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 164079019721 ps |
| CPU time | 2045.12 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 01:11:40 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-bda3ff7b-0990-41a2-884f-194392e78a95 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826062031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1826062031 |
| Directory | /workspace/51.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random_reset.1267823259 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 93564628901 ps |
| CPU time | 136.97 seconds |
| Started | May 30 12:36:49 PM PDT 24 |
| Finished | May 30 12:39:06 PM PDT 24 |
| Peak memory | 191084 kb |
| Host | smart-0af653bf-13e5-4d85-bb0d-6f08e876422d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1267823259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1267823259 |
| Directory | /workspace/9.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3241653449 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 201434936 ps |
| CPU time | 1.15 seconds |
| Started | May 30 12:36:17 PM PDT 24 |
| Finished | May 30 12:36:20 PM PDT 24 |
| Peak memory | 183436 kb |
| Host | smart-d4aff86a-741d-4797-bec1-62100559c1b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241653449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in tg_err.3241653449 |
| Directory | /workspace/0.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2095536049 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 118107823 ps |
| CPU time | 1.35 seconds |
| Started | May 30 12:36:28 PM PDT 24 |
| Finished | May 30 12:36:31 PM PDT 24 |
| Peak memory | 195500 kb |
| Host | smart-c40699c6-d9c0-478c-b5a3-858b042fb462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095536049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.2095536049 |
| Directory | /workspace/14.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random.4036841729 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 160719926004 ps |
| CPU time | 240.74 seconds |
| Started | May 30 12:36:57 PM PDT 24 |
| Finished | May 30 12:40:59 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-6bcb4c7f-30e8-45a6-92bb-9724df7b2661 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036841729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.4036841729 |
| Directory | /workspace/0.rv_timer_random/latest |
| Test location | /workspace/coverage/default/102.rv_timer_random.3676904763 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 240188119729 ps |
| CPU time | 130.33 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:39:45 PM PDT 24 |
| Peak memory | 191004 kb |
| Host | smart-c42512e4-64ec-437a-9f5a-fc13a2c17438 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676904763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3676904763 |
| Directory | /workspace/102.rv_timer_random/latest |
| Test location | /workspace/coverage/default/106.rv_timer_random.1548731157 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 54830368247 ps |
| CPU time | 62.88 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:38:38 PM PDT 24 |
| Peak memory | 193392 kb |
| Host | smart-f0c2288a-a8b8-4a9a-8686-b336898f60cd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548731157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1548731157 |
| Directory | /workspace/106.rv_timer_random/latest |
| Test location | /workspace/coverage/default/107.rv_timer_random.324847822 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 687619047979 ps |
| CPU time | 360.75 seconds |
| Started | May 30 12:37:46 PM PDT 24 |
| Finished | May 30 12:43:48 PM PDT 24 |
| Peak memory | 191116 kb |
| Host | smart-16c676d1-60c4-4c65-a71f-6a8fc86d88f5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324847822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.324847822 |
| Directory | /workspace/107.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all.2455850694 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 320300361118 ps |
| CPU time | 96.46 seconds |
| Started | May 30 12:37:04 PM PDT 24 |
| Finished | May 30 12:38:43 PM PDT 24 |
| Peak memory | 182928 kb |
| Host | smart-787a7c0a-4743-4070-ac6f-2b4b291bc3b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455850694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all .2455850694 |
| Directory | /workspace/11.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/116.rv_timer_random.3623624819 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 90100198212 ps |
| CPU time | 173 seconds |
| Started | May 30 12:37:43 PM PDT 24 |
| Finished | May 30 12:40:37 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-68a401f0-1e96-4f85-89e0-4015c30cc819 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623624819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3623624819 |
| Directory | /workspace/116.rv_timer_random/latest |
| Test location | /workspace/coverage/default/137.rv_timer_random.876882117 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 231046219255 ps |
| CPU time | 395.35 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:44:06 PM PDT 24 |
| Peak memory | 190996 kb |
| Host | smart-ca17ea0b-1ad1-475a-a2c6-79cd4f1dd9ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876882117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.876882117 |
| Directory | /workspace/137.rv_timer_random/latest |
| Test location | /workspace/coverage/default/153.rv_timer_random.2718386900 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 32164787845 ps |
| CPU time | 33.08 seconds |
| Started | May 30 12:37:46 PM PDT 24 |
| Finished | May 30 12:38:19 PM PDT 24 |
| Peak memory | 182904 kb |
| Host | smart-b638554b-2fc3-4d6d-86e8-9e5e5d19899a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718386900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2718386900 |
| Directory | /workspace/153.rv_timer_random/latest |
| Test location | /workspace/coverage/default/155.rv_timer_random.2396595252 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 258051073042 ps |
| CPU time | 556.91 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:46:52 PM PDT 24 |
| Peak memory | 191012 kb |
| Host | smart-f79f89e1-e054-4e55-856b-696f488b0af6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396595252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2396595252 |
| Directory | /workspace/155.rv_timer_random/latest |
| Test location | /workspace/coverage/default/157.rv_timer_random.1579299983 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3405227789 ps |
| CPU time | 4.45 seconds |
| Started | May 30 12:37:42 PM PDT 24 |
| Finished | May 30 12:37:47 PM PDT 24 |
| Peak memory | 182848 kb |
| Host | smart-6f6983ea-6461-4ba8-ac0b-998a20167ee5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579299983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1579299983 |
| Directory | /workspace/157.rv_timer_random/latest |
| Test location | /workspace/coverage/default/158.rv_timer_random.997827477 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 76651618618 ps |
| CPU time | 332.19 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:43:10 PM PDT 24 |
| Peak memory | 191052 kb |
| Host | smart-24bf910b-bbc3-4c4e-9aab-0e3df724cc4c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997827477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.997827477 |
| Directory | /workspace/158.rv_timer_random/latest |
| Test location | /workspace/coverage/default/162.rv_timer_random.578029303 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1004381717918 ps |
| CPU time | 3382.86 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 01:34:04 PM PDT 24 |
| Peak memory | 191052 kb |
| Host | smart-bb693fa1-d747-4d44-ae1b-baefce58ec54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578029303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.578029303 |
| Directory | /workspace/162.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all.1292057758 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 183988126137 ps |
| CPU time | 387.84 seconds |
| Started | May 30 12:37:12 PM PDT 24 |
| Finished | May 30 12:43:41 PM PDT 24 |
| Peak memory | 191052 kb |
| Host | smart-7a3e7c21-3722-4589-90b5-f71edc6dac39 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292057758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all .1292057758 |
| Directory | /workspace/17.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/181.rv_timer_random.3860000269 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 135053263469 ps |
| CPU time | 260.61 seconds |
| Started | May 30 12:37:46 PM PDT 24 |
| Finished | May 30 12:42:08 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-906b755d-eca2-4c7a-83f8-61f317684dac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860000269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3860000269 |
| Directory | /workspace/181.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.874937276 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 32709295747 ps |
| CPU time | 51.39 seconds |
| Started | May 30 12:37:06 PM PDT 24 |
| Finished | May 30 12:38:00 PM PDT 24 |
| Peak memory | 182852 kb |
| Host | smart-a89636f2-0dab-4b25-906d-ca79c381d9e5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874937276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.rv_timer_cfg_update_on_fly.874937276 |
| Directory | /workspace/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_random_reset.4090043999 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 105752085474 ps |
| CPU time | 83.57 seconds |
| Started | May 30 12:36:58 PM PDT 24 |
| Finished | May 30 12:38:23 PM PDT 24 |
| Peak memory | 194632 kb |
| Host | smart-89776588-2a0a-4ad5-bc1e-19417a18182b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090043999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4090043999 |
| Directory | /workspace/24.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random.1960371890 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 293624065769 ps |
| CPU time | 141.57 seconds |
| Started | May 30 12:37:11 PM PDT 24 |
| Finished | May 30 12:39:34 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-af07c948-355a-43c4-b8cf-d58c99de2ed6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960371890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1960371890 |
| Directory | /workspace/26.rv_timer_random/latest |
| Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2520824130 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 354326757725 ps |
| CPU time | 585.44 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:47:10 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-cea5d9eb-f20e-4921-a346-313f35bcafe9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520824130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.2520824130 |
| Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random.2185652485 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 10254866216 ps |
| CPU time | 4.72 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:37:22 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-ace19b33-c51c-4e0d-a8d1-ea934c64b85f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185652485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2185652485 |
| Directory | /workspace/27.rv_timer_random/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random.2137805413 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 502637941161 ps |
| CPU time | 398.93 seconds |
| Started | May 30 12:37:12 PM PDT 24 |
| Finished | May 30 12:43:52 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-a30768ae-c87f-4fc3-be0e-7fc455893f52 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137805413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2137805413 |
| Directory | /workspace/30.rv_timer_random/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random.786328680 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 133330380710 ps |
| CPU time | 60.87 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:38:34 PM PDT 24 |
| Peak memory | 191076 kb |
| Host | smart-c6afdbc6-0eab-4a10-af68-f952087d521b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786328680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.786328680 |
| Directory | /workspace/35.rv_timer_random/latest |
| Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2425755568 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 651507320549 ps |
| CPU time | 306.6 seconds |
| Started | May 30 12:37:20 PM PDT 24 |
| Finished | May 30 12:42:28 PM PDT 24 |
| Peak memory | 182976 kb |
| Host | smart-0ae56e6b-0a10-421b-bf91-732b3e1bdc00 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425755568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.2425755568 |
| Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/61.rv_timer_random.138931791 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 93117645551 ps |
| CPU time | 79.19 seconds |
| Started | May 30 12:37:23 PM PDT 24 |
| Finished | May 30 12:38:43 PM PDT 24 |
| Peak memory | 191128 kb |
| Host | smart-423eb79a-a884-481d-b9b8-bfb4e1f70f46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138931791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.138931791 |
| Directory | /workspace/61.rv_timer_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1986750459 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 47912478 ps |
| CPU time | 0.73 seconds |
| Started | May 30 12:36:15 PM PDT 24 |
| Finished | May 30 12:36:17 PM PDT 24 |
| Peak memory | 192556 kb |
| Host | smart-a6765c60-3b24-4a9f-946b-4a68abe68562 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986750459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia sing.1986750459 |
| Directory | /workspace/0.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1981028307 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 632352231 ps |
| CPU time | 3.18 seconds |
| Started | May 30 12:36:16 PM PDT 24 |
| Finished | May 30 12:36:20 PM PDT 24 |
| Peak memory | 193908 kb |
| Host | smart-396ff19c-561f-429a-926d-8d2b5824d487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981028307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ bash.1981028307 |
| Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2092788780 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 15830403 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:23 PM PDT 24 |
| Finished | May 30 12:36:25 PM PDT 24 |
| Peak memory | 182584 kb |
| Host | smart-a997d441-9538-46d3-b4a8-b303abddf742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092788780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r eset.2092788780 |
| Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2644139684 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 27374357 ps |
| CPU time | 0.87 seconds |
| Started | May 30 12:36:16 PM PDT 24 |
| Finished | May 30 12:36:18 PM PDT 24 |
| Peak memory | 197012 kb |
| Host | smart-61e898f4-79d8-4651-b18c-c43a509093fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644139684 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2644139684 |
| Directory | /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1517757944 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 31443516 ps |
| CPU time | 0.55 seconds |
| Started | May 30 12:36:25 PM PDT 24 |
| Finished | May 30 12:36:27 PM PDT 24 |
| Peak memory | 182484 kb |
| Host | smart-a5db3a1d-3df4-4c47-ad4f-07f8218c3776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517757944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1517757944 |
| Directory | /workspace/0.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1292208722 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 66184557 ps |
| CPU time | 1.45 seconds |
| Started | May 30 12:36:22 PM PDT 24 |
| Finished | May 30 12:36:25 PM PDT 24 |
| Peak memory | 197564 kb |
| Host | smart-f8be6e9b-ed45-41fa-b7ca-c4c4cca392a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292208722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1292208722 |
| Directory | /workspace/0.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1493428976 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 37935295 ps |
| CPU time | 0.59 seconds |
| Started | May 30 12:36:17 PM PDT 24 |
| Finished | May 30 12:36:19 PM PDT 24 |
| Peak memory | 182672 kb |
| Host | smart-c3ad0547-0539-41e5-b6fc-a9e20e4a1b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493428976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia sing.1493428976 |
| Directory | /workspace/1.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2123701250 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 829902523 ps |
| CPU time | 3.32 seconds |
| Started | May 30 12:36:17 PM PDT 24 |
| Finished | May 30 12:36:22 PM PDT 24 |
| Peak memory | 193908 kb |
| Host | smart-6097b58d-8c1b-4199-b100-52bf2d8f3fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123701250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ bash.2123701250 |
| Directory | /workspace/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2881225678 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 32770951 ps |
| CPU time | 0.56 seconds |
| Started | May 30 12:36:14 PM PDT 24 |
| Finished | May 30 12:36:16 PM PDT 24 |
| Peak memory | 182712 kb |
| Host | smart-6ea66aa6-f74c-4822-a9e1-384d36c1fe5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881225678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r eset.2881225678 |
| Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.512626707 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 12557107 ps |
| CPU time | 0.61 seconds |
| Started | May 30 12:36:26 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 193612 kb |
| Host | smart-f979be84-b365-4d27-8220-f8e28b110dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512626707 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.512626707 |
| Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3294958268 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 18057883 ps |
| CPU time | 0.55 seconds |
| Started | May 30 12:36:21 PM PDT 24 |
| Finished | May 30 12:36:23 PM PDT 24 |
| Peak memory | 182676 kb |
| Host | smart-e5ae0a19-a61b-4298-ba2c-bdfb2b79333f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294958268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3294958268 |
| Directory | /workspace/1.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1125916170 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 60975298 ps |
| CPU time | 0.82 seconds |
| Started | May 30 12:36:20 PM PDT 24 |
| Finished | May 30 12:36:22 PM PDT 24 |
| Peak memory | 191544 kb |
| Host | smart-18285905-423c-4189-9225-8e795c240ade |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125916170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.1125916170 |
| Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3882004501 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 638961947 ps |
| CPU time | 1.4 seconds |
| Started | May 30 12:36:27 PM PDT 24 |
| Finished | May 30 12:36:30 PM PDT 24 |
| Peak memory | 197544 kb |
| Host | smart-9df9d55e-bed8-4a06-9833-d639ad4dca88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882004501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3882004501 |
| Directory | /workspace/1.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3634825741 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 68802443 ps |
| CPU time | 0.8 seconds |
| Started | May 30 12:36:15 PM PDT 24 |
| Finished | May 30 12:36:18 PM PDT 24 |
| Peak memory | 193728 kb |
| Host | smart-38a52fe0-3f70-4a00-8945-1cdf4b506553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634825741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in tg_err.3634825741 |
| Directory | /workspace/1.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1833447795 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 25775917 ps |
| CPU time | 0.71 seconds |
| Started | May 30 12:36:26 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 195064 kb |
| Host | smart-07f413bc-1331-4501-b990-8d76533d4d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833447795 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1833447795 |
| Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2580403741 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 15147856 ps |
| CPU time | 0.6 seconds |
| Started | May 30 12:36:33 PM PDT 24 |
| Finished | May 30 12:36:35 PM PDT 24 |
| Peak memory | 182288 kb |
| Host | smart-c09dc966-8859-4be3-a786-82d20a186306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580403741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2580403741 |
| Directory | /workspace/10.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1674005379 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 17707109 ps |
| CPU time | 0.56 seconds |
| Started | May 30 12:36:39 PM PDT 24 |
| Finished | May 30 12:36:41 PM PDT 24 |
| Peak memory | 182560 kb |
| Host | smart-bee2aebe-7730-44e0-a8ea-73c7da641c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674005379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1674005379 |
| Directory | /workspace/10.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.825245866 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 33313972 ps |
| CPU time | 0.72 seconds |
| Started | May 30 12:36:43 PM PDT 24 |
| Finished | May 30 12:36:45 PM PDT 24 |
| Peak memory | 193272 kb |
| Host | smart-ad016c9b-f3e0-4eb2-8458-36fd5a8856d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825245866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti mer_same_csr_outstanding.825245866 |
| Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1726431980 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 35921614 ps |
| CPU time | 1.39 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:37 PM PDT 24 |
| Peak memory | 197084 kb |
| Host | smart-5c8a73e4-b858-4175-aaab-c536e2ba33c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726431980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1726431980 |
| Directory | /workspace/10.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2145079703 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 120482757 ps |
| CPU time | 0.88 seconds |
| Started | May 30 12:36:26 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 196848 kb |
| Host | smart-22f1f3fe-ddb5-4435-82de-3a115be6d49b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145079703 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2145079703 |
| Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2422521798 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 25032679 ps |
| CPU time | 0.53 seconds |
| Started | May 30 12:36:38 PM PDT 24 |
| Finished | May 30 12:36:40 PM PDT 24 |
| Peak memory | 182748 kb |
| Host | smart-6ac7de93-6993-47c9-8124-3ce7ce8129b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422521798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2422521798 |
| Directory | /workspace/11.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3116597470 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 28854951 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:35 PM PDT 24 |
| Finished | May 30 12:36:37 PM PDT 24 |
| Peak memory | 181920 kb |
| Host | smart-38ef4a2b-c5e8-4bdb-bf85-b3470d638450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116597470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3116597470 |
| Directory | /workspace/11.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2159068403 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 104756051 ps |
| CPU time | 0.69 seconds |
| Started | May 30 12:36:30 PM PDT 24 |
| Finished | May 30 12:36:32 PM PDT 24 |
| Peak memory | 191452 kb |
| Host | smart-05152cc5-2a0e-4e34-b460-656cbfc953f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159068403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.2159068403 |
| Directory | /workspace/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1406882404 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 51925155 ps |
| CPU time | 1.01 seconds |
| Started | May 30 12:36:29 PM PDT 24 |
| Finished | May 30 12:36:31 PM PDT 24 |
| Peak memory | 195896 kb |
| Host | smart-70d39686-2838-4ff9-87bd-aa4186b68b28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406882404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1406882404 |
| Directory | /workspace/11.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3961495602 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 157612824 ps |
| CPU time | 1.08 seconds |
| Started | May 30 12:36:29 PM PDT 24 |
| Finished | May 30 12:36:31 PM PDT 24 |
| Peak memory | 183408 kb |
| Host | smart-950b9e57-3bde-4622-8b83-08721d0ac57e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961495602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i ntg_err.3961495602 |
| Directory | /workspace/11.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.469205073 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 49675181 ps |
| CPU time | 0.92 seconds |
| Started | May 30 12:36:18 PM PDT 24 |
| Finished | May 30 12:36:20 PM PDT 24 |
| Peak memory | 196976 kb |
| Host | smart-8f74c52c-cafa-49ec-a9ea-13483c48ca62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469205073 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.469205073 |
| Directory | /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2201976186 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 16834747 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:33 PM PDT 24 |
| Finished | May 30 12:36:35 PM PDT 24 |
| Peak memory | 182628 kb |
| Host | smart-1b6791c3-d904-43ae-91a7-d650f53748f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201976186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2201976186 |
| Directory | /workspace/12.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2639061810 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 15843873 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:38 PM PDT 24 |
| Finished | May 30 12:36:40 PM PDT 24 |
| Peak memory | 182616 kb |
| Host | smart-c6abccc7-46f1-4fbb-bb91-5e75b9f99ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639061810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2639061810 |
| Directory | /workspace/12.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.203881174 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 38471902 ps |
| CPU time | 0.79 seconds |
| Started | May 30 12:36:37 PM PDT 24 |
| Finished | May 30 12:36:39 PM PDT 24 |
| Peak memory | 191668 kb |
| Host | smart-f480dd96-ab57-4266-a55a-a486c2f483b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203881174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti mer_same_csr_outstanding.203881174 |
| Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.369864266 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 211866920 ps |
| CPU time | 2.75 seconds |
| Started | May 30 12:36:29 PM PDT 24 |
| Finished | May 30 12:36:33 PM PDT 24 |
| Peak memory | 197536 kb |
| Host | smart-0823af05-8f99-4cab-bc77-670cfd1f15b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369864266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.369864266 |
| Directory | /workspace/12.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3855484014 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 403600385 ps |
| CPU time | 1.12 seconds |
| Started | May 30 12:36:25 PM PDT 24 |
| Finished | May 30 12:36:27 PM PDT 24 |
| Peak memory | 195044 kb |
| Host | smart-2ac94835-1318-4254-98fc-96d6f0295eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855484014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.3855484014 |
| Directory | /workspace/12.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3360540427 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 98968594 ps |
| CPU time | 1.14 seconds |
| Started | May 30 12:36:37 PM PDT 24 |
| Finished | May 30 12:36:39 PM PDT 24 |
| Peak memory | 197676 kb |
| Host | smart-18123c8c-e292-4800-8c40-fc33de65ef6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360540427 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3360540427 |
| Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.837027098 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 18470867 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:29 PM PDT 24 |
| Finished | May 30 12:36:31 PM PDT 24 |
| Peak memory | 182584 kb |
| Host | smart-24453da7-3d8e-469e-89f7-d568c27d2f19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837027098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.837027098 |
| Directory | /workspace/13.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1976594875 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 14442068 ps |
| CPU time | 0.53 seconds |
| Started | May 30 12:36:26 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 182568 kb |
| Host | smart-5b4c1b49-7393-4803-887e-6642e6f65577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976594875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1976594875 |
| Directory | /workspace/13.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.853832396 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 15424709 ps |
| CPU time | 0.61 seconds |
| Started | May 30 12:36:33 PM PDT 24 |
| Finished | May 30 12:36:34 PM PDT 24 |
| Peak memory | 191392 kb |
| Host | smart-43c062a4-3c24-48bd-b8d1-69ec273636a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853832396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti mer_same_csr_outstanding.853832396 |
| Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1713235086 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 772298588 ps |
| CPU time | 2.91 seconds |
| Started | May 30 12:36:31 PM PDT 24 |
| Finished | May 30 12:36:35 PM PDT 24 |
| Peak memory | 197496 kb |
| Host | smart-cd1242ab-0841-4392-bf82-f31e2a46aed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713235086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1713235086 |
| Directory | /workspace/13.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2249874995 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 178002430 ps |
| CPU time | 0.77 seconds |
| Started | May 30 12:36:39 PM PDT 24 |
| Finished | May 30 12:36:41 PM PDT 24 |
| Peak memory | 193652 kb |
| Host | smart-98ae72bb-0eed-4eed-914c-cd808f7be559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249874995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.2249874995 |
| Directory | /workspace/13.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2359568777 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 39076355 ps |
| CPU time | 0.95 seconds |
| Started | May 30 12:36:32 PM PDT 24 |
| Finished | May 30 12:36:34 PM PDT 24 |
| Peak memory | 197244 kb |
| Host | smart-ffb512eb-75d1-48d0-a36f-df63247a5792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359568777 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2359568777 |
| Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3196532922 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 37774103 ps |
| CPU time | 0.53 seconds |
| Started | May 30 12:36:26 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 182308 kb |
| Host | smart-076a94a6-40c2-4989-ad5d-e2b8741a0b92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196532922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3196532922 |
| Directory | /workspace/14.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1381573699 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 10994309 ps |
| CPU time | 0.53 seconds |
| Started | May 30 12:36:38 PM PDT 24 |
| Finished | May 30 12:36:40 PM PDT 24 |
| Peak memory | 182564 kb |
| Host | smart-3e012a55-fe15-4332-9125-d648987476bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381573699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1381573699 |
| Directory | /workspace/14.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.550222023 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 38637958 ps |
| CPU time | 0.59 seconds |
| Started | May 30 12:36:33 PM PDT 24 |
| Finished | May 30 12:36:35 PM PDT 24 |
| Peak memory | 192100 kb |
| Host | smart-8c0fe23a-1b6d-48c9-8dd6-00a64ca5c926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550222023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti mer_same_csr_outstanding.550222023 |
| Directory | /workspace/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2545257337 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 370915549 ps |
| CPU time | 1.23 seconds |
| Started | May 30 12:36:39 PM PDT 24 |
| Finished | May 30 12:36:41 PM PDT 24 |
| Peak memory | 197292 kb |
| Host | smart-46725edf-a4a6-44dd-b3cd-5f0c850d0a4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545257337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2545257337 |
| Directory | /workspace/14.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1326048024 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 108748820 ps |
| CPU time | 1.39 seconds |
| Started | May 30 12:36:38 PM PDT 24 |
| Finished | May 30 12:36:41 PM PDT 24 |
| Peak memory | 197568 kb |
| Host | smart-280e7b48-1d7f-45ff-9ff3-18b2e7f580a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326048024 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1326048024 |
| Directory | /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1105680509 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 24570537 ps |
| CPU time | 0.55 seconds |
| Started | May 30 12:36:37 PM PDT 24 |
| Finished | May 30 12:36:39 PM PDT 24 |
| Peak memory | 182596 kb |
| Host | smart-44d71b35-3e2a-4cf9-bc23-4f856e7b0b94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105680509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1105680509 |
| Directory | /workspace/15.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3338247243 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 16897044 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:37 PM PDT 24 |
| Finished | May 30 12:36:39 PM PDT 24 |
| Peak memory | 182180 kb |
| Host | smart-edb7d7c9-1426-4077-a6f8-bf793f232e64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338247243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3338247243 |
| Directory | /workspace/15.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2380967791 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 30216986 ps |
| CPU time | 0.78 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 191620 kb |
| Host | smart-24e8687c-1081-4c39-8cd0-5b04c11b29cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380967791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t imer_same_csr_outstanding.2380967791 |
| Directory | /workspace/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.197806759 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 75154262 ps |
| CPU time | 1.03 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 197280 kb |
| Host | smart-f5756267-435f-46ef-98ac-d0f1a96ee025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197806759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.197806759 |
| Directory | /workspace/15.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1961714641 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 371937338 ps |
| CPU time | 1.34 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 195560 kb |
| Host | smart-b97528ea-7312-49b2-98b9-6e9f7bc6c500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961714641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i ntg_err.1961714641 |
| Directory | /workspace/15.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.681028233 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 41510851 ps |
| CPU time | 1.57 seconds |
| Started | May 30 12:36:41 PM PDT 24 |
| Finished | May 30 12:36:44 PM PDT 24 |
| Peak memory | 197644 kb |
| Host | smart-193ecab8-c972-4604-a79d-f4453bda3734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681028233 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.681028233 |
| Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3609871610 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 21081203 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 182608 kb |
| Host | smart-17f4ae75-22af-4a5d-9bdc-9e3b508950b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609871610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3609871610 |
| Directory | /workspace/16.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3426516335 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 21486893 ps |
| CPU time | 0.63 seconds |
| Started | May 30 12:36:42 PM PDT 24 |
| Finished | May 30 12:36:44 PM PDT 24 |
| Peak memory | 182672 kb |
| Host | smart-2c4d842f-60c2-4627-a770-13d9b149ccbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426516335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3426516335 |
| Directory | /workspace/16.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3996922819 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 18553730 ps |
| CPU time | 0.61 seconds |
| Started | May 30 12:36:35 PM PDT 24 |
| Finished | May 30 12:36:37 PM PDT 24 |
| Peak memory | 191856 kb |
| Host | smart-fee4337e-5cfe-4278-a04f-24a5f5962b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996922819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t imer_same_csr_outstanding.3996922819 |
| Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.765900184 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 46480093 ps |
| CPU time | 1.19 seconds |
| Started | May 30 12:36:39 PM PDT 24 |
| Finished | May 30 12:36:41 PM PDT 24 |
| Peak memory | 197324 kb |
| Host | smart-8edbc72b-e55c-4487-9fcf-4efe66c1589f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765900184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.765900184 |
| Directory | /workspace/16.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1279809182 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 99207809 ps |
| CPU time | 1.33 seconds |
| Started | May 30 12:36:43 PM PDT 24 |
| Finished | May 30 12:36:45 PM PDT 24 |
| Peak memory | 183116 kb |
| Host | smart-e88e6878-9683-44a2-ac6f-cd3de22cb2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279809182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i ntg_err.1279809182 |
| Directory | /workspace/16.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2512683535 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 167054951 ps |
| CPU time | 0.88 seconds |
| Started | May 30 12:36:42 PM PDT 24 |
| Finished | May 30 12:36:44 PM PDT 24 |
| Peak memory | 197300 kb |
| Host | smart-5a81ab27-d19b-45fa-9e40-5d995e4cae35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512683535 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2512683535 |
| Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1010994831 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 78832055 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:36:41 PM PDT 24 |
| Finished | May 30 12:36:43 PM PDT 24 |
| Peak memory | 182732 kb |
| Host | smart-cd7cb9c6-8070-4b1a-835e-caf3833844c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010994831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1010994831 |
| Directory | /workspace/17.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3258653618 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 55170935 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 182496 kb |
| Host | smart-eb444938-1d8b-452b-9101-fbd0bf6ca325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258653618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3258653618 |
| Directory | /workspace/17.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4018272190 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 60028085 ps |
| CPU time | 0.67 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 192184 kb |
| Host | smart-682ec472-4a54-48fa-aa1d-e038643054b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018272190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t imer_same_csr_outstanding.4018272190 |
| Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4011257851 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 39675408 ps |
| CPU time | 1.96 seconds |
| Started | May 30 12:36:29 PM PDT 24 |
| Finished | May 30 12:36:32 PM PDT 24 |
| Peak memory | 197624 kb |
| Host | smart-4370b2ff-0967-476c-baf4-960576b37dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011257851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4011257851 |
| Directory | /workspace/17.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3614821270 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 512036262 ps |
| CPU time | 1.41 seconds |
| Started | May 30 12:36:38 PM PDT 24 |
| Finished | May 30 12:36:41 PM PDT 24 |
| Peak memory | 195464 kb |
| Host | smart-770d0a6b-1fa4-4c01-a7e4-9c3564e6231f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614821270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i ntg_err.3614821270 |
| Directory | /workspace/17.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2497209675 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 48864818 ps |
| CPU time | 0.67 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:36 PM PDT 24 |
| Peak memory | 194820 kb |
| Host | smart-3fa144ba-ea8a-4984-a3af-9cb10a0495dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497209675 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2497209675 |
| Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4249445011 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 42641163 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:37 PM PDT 24 |
| Finished | May 30 12:36:38 PM PDT 24 |
| Peak memory | 182616 kb |
| Host | smart-f1113442-ec0e-4f2d-b435-9df2f1100694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249445011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.4249445011 |
| Directory | /workspace/18.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2912088388 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 54167123 ps |
| CPU time | 0.56 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 182612 kb |
| Host | smart-62ee453b-8bc7-402d-8e09-1237517109fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912088388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2912088388 |
| Directory | /workspace/18.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2544841204 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 20333597 ps |
| CPU time | 0.81 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 194456 kb |
| Host | smart-0fd7c3b8-a290-4412-8f6a-0ce450780d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544841204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.2544841204 |
| Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3250220323 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 200278716 ps |
| CPU time | 1.99 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:37 PM PDT 24 |
| Peak memory | 197560 kb |
| Host | smart-4769e717-ffaa-460b-a36b-1399b5c8e6b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250220323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3250220323 |
| Directory | /workspace/18.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2013443355 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 441458454 ps |
| CPU time | 1.29 seconds |
| Started | May 30 12:36:41 PM PDT 24 |
| Finished | May 30 12:36:43 PM PDT 24 |
| Peak memory | 183412 kb |
| Host | smart-6e9c0728-6010-4f99-9e27-e05330a5fafb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013443355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i ntg_err.2013443355 |
| Directory | /workspace/18.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1213812834 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 41088595 ps |
| CPU time | 1.41 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 197612 kb |
| Host | smart-ad3288e2-f426-4da7-9f7e-239d2891d713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213812834 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1213812834 |
| Directory | /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.287972837 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 11658813 ps |
| CPU time | 0.53 seconds |
| Started | May 30 12:36:35 PM PDT 24 |
| Finished | May 30 12:36:37 PM PDT 24 |
| Peak memory | 182540 kb |
| Host | smart-69d64bd0-0c6b-42c4-9324-cfd169a9e03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287972837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.287972837 |
| Directory | /workspace/19.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2344466124 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 30346474 ps |
| CPU time | 0.52 seconds |
| Started | May 30 12:36:30 PM PDT 24 |
| Finished | May 30 12:36:31 PM PDT 24 |
| Peak memory | 181968 kb |
| Host | smart-94903f85-5024-43de-b0d0-882792adefdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344466124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2344466124 |
| Directory | /workspace/19.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1565517397 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 17850864 ps |
| CPU time | 0.73 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:36 PM PDT 24 |
| Peak memory | 193092 kb |
| Host | smart-d19ab56e-10d4-4b46-9841-e5e2790a1e75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565517397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t imer_same_csr_outstanding.1565517397 |
| Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1756220160 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 130420339 ps |
| CPU time | 2.01 seconds |
| Started | May 30 12:36:41 PM PDT 24 |
| Finished | May 30 12:36:45 PM PDT 24 |
| Peak memory | 197448 kb |
| Host | smart-6a0e8bb3-6e99-4d13-b756-84526d4a0500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756220160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1756220160 |
| Directory | /workspace/19.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.860564895 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 369979793 ps |
| CPU time | 1.14 seconds |
| Started | May 30 12:36:44 PM PDT 24 |
| Finished | May 30 12:36:46 PM PDT 24 |
| Peak memory | 195220 kb |
| Host | smart-d895f4d4-9f46-46fe-b2b2-cbe06bf4c365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860564895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in tg_err.860564895 |
| Directory | /workspace/19.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.973824025 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 14698078 ps |
| CPU time | 0.59 seconds |
| Started | May 30 12:36:25 PM PDT 24 |
| Finished | May 30 12:36:27 PM PDT 24 |
| Peak memory | 182720 kb |
| Host | smart-7ea681c2-6d22-4f1a-9c6c-e329dba7e729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973824025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias ing.973824025 |
| Directory | /workspace/2.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2141179636 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 69827852 ps |
| CPU time | 1.35 seconds |
| Started | May 30 12:36:25 PM PDT 24 |
| Finished | May 30 12:36:27 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-be5bd214-0e40-4d32-9976-2c5856dbf9ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141179636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ bash.2141179636 |
| Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3997855623 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 19353563 ps |
| CPU time | 0.61 seconds |
| Started | May 30 12:36:32 PM PDT 24 |
| Finished | May 30 12:36:34 PM PDT 24 |
| Peak memory | 182640 kb |
| Host | smart-3b1f8964-47c7-4e4e-a4b0-40fd2941a8d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997855623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r eset.3997855623 |
| Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2481954121 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 87412433 ps |
| CPU time | 0.7 seconds |
| Started | May 30 12:36:21 PM PDT 24 |
| Finished | May 30 12:36:23 PM PDT 24 |
| Peak memory | 194728 kb |
| Host | smart-9070f9b7-f435-4a00-b426-5ab210c0c63a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481954121 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2481954121 |
| Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3776034845 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 21556070 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:36:27 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 182636 kb |
| Host | smart-b867fa4f-18f7-4cda-8fb8-52f636e3d5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776034845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3776034845 |
| Directory | /workspace/2.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3027976251 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 39789897 ps |
| CPU time | 0.56 seconds |
| Started | May 30 12:36:17 PM PDT 24 |
| Finished | May 30 12:36:19 PM PDT 24 |
| Peak memory | 182540 kb |
| Host | smart-812069e3-1b8b-4473-8c24-75f3ed009520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027976251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3027976251 |
| Directory | /workspace/2.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3368796735 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 23035721 ps |
| CPU time | 0.76 seconds |
| Started | May 30 12:36:15 PM PDT 24 |
| Finished | May 30 12:36:18 PM PDT 24 |
| Peak memory | 193300 kb |
| Host | smart-5b1e6cc7-37da-4133-8962-87739e998938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368796735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti mer_same_csr_outstanding.3368796735 |
| Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4198093382 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 251030754 ps |
| CPU time | 1.48 seconds |
| Started | May 30 12:36:28 PM PDT 24 |
| Finished | May 30 12:36:30 PM PDT 24 |
| Peak memory | 197492 kb |
| Host | smart-8279c690-7e8d-4e91-978e-42910ed03b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198093382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4198093382 |
| Directory | /workspace/2.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1368647375 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 106294055 ps |
| CPU time | 1.05 seconds |
| Started | May 30 12:36:14 PM PDT 24 |
| Finished | May 30 12:36:16 PM PDT 24 |
| Peak memory | 183120 kb |
| Host | smart-a4545860-44d0-4e4a-a841-9ae4959a2063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368647375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in tg_err.1368647375 |
| Directory | /workspace/2.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.360647874 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 11060269 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:36 PM PDT 24 |
| Peak memory | 182456 kb |
| Host | smart-d939a3d2-916a-4b16-9452-5615b9937bed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360647874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.360647874 |
| Directory | /workspace/20.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3717471313 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 107828010 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:33 PM PDT 24 |
| Finished | May 30 12:36:35 PM PDT 24 |
| Peak memory | 182460 kb |
| Host | smart-a3266484-2351-4a4c-ba10-db1e1a04803d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717471313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3717471313 |
| Directory | /workspace/21.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2459606135 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 11197246 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:37 PM PDT 24 |
| Finished | May 30 12:36:39 PM PDT 24 |
| Peak memory | 182572 kb |
| Host | smart-1d1099a1-51fc-45d2-ae83-b6cf38f22c76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459606135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2459606135 |
| Directory | /workspace/22.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2633841394 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 36202829 ps |
| CPU time | 0.51 seconds |
| Started | May 30 12:36:35 PM PDT 24 |
| Finished | May 30 12:36:37 PM PDT 24 |
| Peak memory | 181976 kb |
| Host | smart-c3e4c11b-035e-4974-9cca-092fc04372e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633841394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2633841394 |
| Directory | /workspace/23.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1599637568 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 38158864 ps |
| CPU time | 0.53 seconds |
| Started | May 30 12:36:39 PM PDT 24 |
| Finished | May 30 12:36:41 PM PDT 24 |
| Peak memory | 182148 kb |
| Host | smart-4ca80bfe-1cf3-41f2-81b0-8659e4a8d403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599637568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1599637568 |
| Directory | /workspace/24.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1570881069 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 39801982 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:43 PM PDT 24 |
| Finished | May 30 12:36:45 PM PDT 24 |
| Peak memory | 182528 kb |
| Host | smart-4b33b18e-ff92-4211-9170-c2c0374fa36d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570881069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1570881069 |
| Directory | /workspace/25.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2760488116 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 25089725 ps |
| CPU time | 0.59 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:36 PM PDT 24 |
| Peak memory | 182480 kb |
| Host | smart-873dc45f-cdfb-4451-92ab-a45bff5261c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760488116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2760488116 |
| Directory | /workspace/26.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2889681195 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 19715448 ps |
| CPU time | 0.55 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:36 PM PDT 24 |
| Peak memory | 182464 kb |
| Host | smart-f497d8d5-ce1e-480c-a6fd-935ef4de57b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889681195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2889681195 |
| Directory | /workspace/27.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3604936081 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 16337011 ps |
| CPU time | 0.56 seconds |
| Started | May 30 12:36:44 PM PDT 24 |
| Finished | May 30 12:36:46 PM PDT 24 |
| Peak memory | 181968 kb |
| Host | smart-625e06b4-1db7-4c24-9a74-801827b425d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604936081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3604936081 |
| Directory | /workspace/28.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3848151439 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 14891744 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:44 PM PDT 24 |
| Finished | May 30 12:36:46 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-8bd159bc-9e63-4628-a785-dcc7ae2d0e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848151439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3848151439 |
| Directory | /workspace/29.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3484986107 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 321242715 ps |
| CPU time | 0.73 seconds |
| Started | May 30 12:36:15 PM PDT 24 |
| Finished | May 30 12:36:18 PM PDT 24 |
| Peak memory | 192388 kb |
| Host | smart-381ac74d-d6c0-4db0-b0fe-a55dc4153a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484986107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia sing.3484986107 |
| Directory | /workspace/3.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3623189198 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 91357450 ps |
| CPU time | 3.09 seconds |
| Started | May 30 12:36:16 PM PDT 24 |
| Finished | May 30 12:36:20 PM PDT 24 |
| Peak memory | 193448 kb |
| Host | smart-2f4494aa-8d4d-4a9c-a070-a16230de9af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623189198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.3623189198 |
| Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3530563632 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 30680901 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:13 PM PDT 24 |
| Finished | May 30 12:36:15 PM PDT 24 |
| Peak memory | 182636 kb |
| Host | smart-4066b23c-eaba-4d42-b1ae-6982e1a0f4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530563632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.3530563632 |
| Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1400917837 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 17299689 ps |
| CPU time | 0.83 seconds |
| Started | May 30 12:36:22 PM PDT 24 |
| Finished | May 30 12:36:25 PM PDT 24 |
| Peak memory | 197248 kb |
| Host | smart-35ab2d52-cf60-431f-9e03-8a905f88d014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400917837 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1400917837 |
| Directory | /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1505272458 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 170549572 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:19 PM PDT 24 |
| Finished | May 30 12:36:21 PM PDT 24 |
| Peak memory | 182724 kb |
| Host | smart-0038d762-3430-4ba0-ac08-6efe7abd994f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505272458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1505272458 |
| Directory | /workspace/3.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2158852563 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 38366024 ps |
| CPU time | 0.51 seconds |
| Started | May 30 12:36:15 PM PDT 24 |
| Finished | May 30 12:36:17 PM PDT 24 |
| Peak memory | 182012 kb |
| Host | smart-f29cac0a-66b9-43a9-a1ef-5e8ea63e214b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158852563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2158852563 |
| Directory | /workspace/3.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3279408887 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 142068950 ps |
| CPU time | 0.82 seconds |
| Started | May 30 12:36:22 PM PDT 24 |
| Finished | May 30 12:36:24 PM PDT 24 |
| Peak memory | 193292 kb |
| Host | smart-305c256e-c8d1-470f-b430-e870a8e9d370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279408887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti mer_same_csr_outstanding.3279408887 |
| Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3650419739 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 527902925 ps |
| CPU time | 2.34 seconds |
| Started | May 30 12:36:15 PM PDT 24 |
| Finished | May 30 12:36:19 PM PDT 24 |
| Peak memory | 197640 kb |
| Host | smart-7dfc147b-1e6b-4ae7-aaf6-9140a3881bf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650419739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3650419739 |
| Directory | /workspace/3.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2432638744 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 43527802 ps |
| CPU time | 0.79 seconds |
| Started | May 30 12:36:28 PM PDT 24 |
| Finished | May 30 12:36:30 PM PDT 24 |
| Peak memory | 193352 kb |
| Host | smart-500c9e0f-d0db-4710-a8f2-e58af4571099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432638744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.2432638744 |
| Directory | /workspace/3.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1055327266 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 11660024 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:42 PM PDT 24 |
| Finished | May 30 12:36:44 PM PDT 24 |
| Peak memory | 182488 kb |
| Host | smart-7b951fd2-9e42-49e7-bc99-c11bfc52f021 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055327266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1055327266 |
| Directory | /workspace/30.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1080935613 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 35547937 ps |
| CPU time | 0.55 seconds |
| Started | May 30 12:36:42 PM PDT 24 |
| Finished | May 30 12:36:44 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-b0bbb673-0006-4581-b523-1f409b006ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080935613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1080935613 |
| Directory | /workspace/31.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1381763565 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 50349525 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:37 PM PDT 24 |
| Finished | May 30 12:36:38 PM PDT 24 |
| Peak memory | 182516 kb |
| Host | smart-1a092fe8-3541-44b9-abf5-61654825edeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381763565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1381763565 |
| Directory | /workspace/32.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.941008836 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 113784742 ps |
| CPU time | 0.51 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:36:48 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-309aab46-e5c5-4d54-b890-448cd5b6b6c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941008836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.941008836 |
| Directory | /workspace/33.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1237486594 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 12186033 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 182504 kb |
| Host | smart-3dd8dd3c-8666-4836-8e29-887ec264ecc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237486594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1237486594 |
| Directory | /workspace/34.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1125509746 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 23993011 ps |
| CPU time | 0.55 seconds |
| Started | May 30 12:36:42 PM PDT 24 |
| Finished | May 30 12:36:44 PM PDT 24 |
| Peak memory | 182516 kb |
| Host | smart-7b0830f3-a21d-4efd-9939-7e1f8a603924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125509746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1125509746 |
| Directory | /workspace/35.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.202991921 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 42468241 ps |
| CPU time | 0.56 seconds |
| Started | May 30 12:36:38 PM PDT 24 |
| Finished | May 30 12:36:40 PM PDT 24 |
| Peak memory | 182052 kb |
| Host | smart-44c80e0f-bbbd-4ca0-9861-a20cd76002fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202991921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.202991921 |
| Directory | /workspace/36.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1929705015 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 16556802 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:36:43 PM PDT 24 |
| Finished | May 30 12:36:44 PM PDT 24 |
| Peak memory | 182516 kb |
| Host | smart-ca8012ce-28d6-4264-9eb7-a72e1d57292a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929705015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1929705015 |
| Directory | /workspace/37.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2107129217 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 49044562 ps |
| CPU time | 0.55 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:36:48 PM PDT 24 |
| Peak memory | 182452 kb |
| Host | smart-5274cfbf-cefb-4fbc-9728-1e4ad03d015c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107129217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2107129217 |
| Directory | /workspace/38.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.283347249 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 15104190 ps |
| CPU time | 0.51 seconds |
| Started | May 30 12:36:55 PM PDT 24 |
| Finished | May 30 12:36:57 PM PDT 24 |
| Peak memory | 182584 kb |
| Host | smart-f3777e69-963e-487d-80b8-6cb64af929c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283347249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.283347249 |
| Directory | /workspace/39.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1163456720 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 39850080 ps |
| CPU time | 0.62 seconds |
| Started | May 30 12:36:25 PM PDT 24 |
| Finished | May 30 12:36:26 PM PDT 24 |
| Peak memory | 182592 kb |
| Host | smart-ee54ac1a-4fc1-4b3d-9a4a-8b4654d88707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163456720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.1163456720 |
| Directory | /workspace/4.rv_timer_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4183683647 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 814524446 ps |
| CPU time | 2.29 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:38 PM PDT 24 |
| Peak memory | 193416 kb |
| Host | smart-9b308982-7658-451e-b79b-2eb6c0ab3f44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183683647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.4183683647 |
| Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2919607196 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 29349648 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:21 PM PDT 24 |
| Finished | May 30 12:36:22 PM PDT 24 |
| Peak memory | 182588 kb |
| Host | smart-74ec73f4-05da-475b-83a7-6ed23516fede |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919607196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.2919607196 |
| Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3984421174 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 48863267 ps |
| CPU time | 0.72 seconds |
| Started | May 30 12:36:18 PM PDT 24 |
| Finished | May 30 12:36:20 PM PDT 24 |
| Peak memory | 195556 kb |
| Host | smart-0c6e84ca-f0a3-457e-b451-6c5942c64fb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984421174 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3984421174 |
| Directory | /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.313632777 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 58259112 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:36:25 PM PDT 24 |
| Finished | May 30 12:36:26 PM PDT 24 |
| Peak memory | 182592 kb |
| Host | smart-49bfe443-5a55-434f-8812-a7db7de79852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313632777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.313632777 |
| Directory | /workspace/4.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3870931548 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 18222946 ps |
| CPU time | 0.51 seconds |
| Started | May 30 12:36:17 PM PDT 24 |
| Finished | May 30 12:36:19 PM PDT 24 |
| Peak memory | 182296 kb |
| Host | smart-ae7072ff-3a59-468f-bf53-11f2382ccf94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870931548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3870931548 |
| Directory | /workspace/4.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2430851698 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 34317870 ps |
| CPU time | 0.8 seconds |
| Started | May 30 12:36:16 PM PDT 24 |
| Finished | May 30 12:36:18 PM PDT 24 |
| Peak memory | 193432 kb |
| Host | smart-f2792597-4314-4762-8979-9e71850f9f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430851698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.2430851698 |
| Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1072525181 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 39297799 ps |
| CPU time | 1.8 seconds |
| Started | May 30 12:36:28 PM PDT 24 |
| Finished | May 30 12:36:31 PM PDT 24 |
| Peak memory | 197472 kb |
| Host | smart-d4915cc0-57ed-4cc0-a170-8cd63f532cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072525181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1072525181 |
| Directory | /workspace/4.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4183779185 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 430033962 ps |
| CPU time | 1.28 seconds |
| Started | May 30 12:36:14 PM PDT 24 |
| Finished | May 30 12:36:17 PM PDT 24 |
| Peak memory | 195372 kb |
| Host | smart-d276f09a-e4ec-48a6-a08d-d478db844a02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183779185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in tg_err.4183779185 |
| Directory | /workspace/4.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1261443844 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 13783904 ps |
| CPU time | 0.59 seconds |
| Started | May 30 12:36:58 PM PDT 24 |
| Finished | May 30 12:37:00 PM PDT 24 |
| Peak memory | 182584 kb |
| Host | smart-cb5b9b8d-2493-493c-845b-db942897af18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261443844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1261443844 |
| Directory | /workspace/40.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.41081715 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 41529014 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:36:48 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-cb03e95a-e13c-4330-be08-ff69318d1a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41081715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.41081715 |
| Directory | /workspace/41.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2313450334 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 38039622 ps |
| CPU time | 0.53 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:36:47 PM PDT 24 |
| Peak memory | 182572 kb |
| Host | smart-ac64c5c8-973f-48b8-a81d-214a89a5c758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313450334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2313450334 |
| Directory | /workspace/42.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2450259561 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 15902097 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:53 PM PDT 24 |
| Finished | May 30 12:36:54 PM PDT 24 |
| Peak memory | 182640 kb |
| Host | smart-a6658628-47f5-4e04-876f-9ca8d1e91f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450259561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2450259561 |
| Directory | /workspace/43.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1434976310 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 44809827 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:37:11 PM PDT 24 |
| Finished | May 30 12:37:12 PM PDT 24 |
| Peak memory | 182512 kb |
| Host | smart-eaedb2d7-3a1d-4e58-8f2e-e1a2e48007fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434976310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1434976310 |
| Directory | /workspace/44.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.67670756 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 54490980 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:37:00 PM PDT 24 |
| Finished | May 30 12:37:02 PM PDT 24 |
| Peak memory | 181960 kb |
| Host | smart-3b67c44e-aba7-43a0-9b09-1597dfd7743a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67670756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.67670756 |
| Directory | /workspace/45.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4188565228 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 73019568 ps |
| CPU time | 0.6 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:36:47 PM PDT 24 |
| Peak memory | 181968 kb |
| Host | smart-770f7913-896e-4e27-97a0-69b44e087574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188565228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4188565228 |
| Directory | /workspace/46.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3698713007 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 11429396 ps |
| CPU time | 0.59 seconds |
| Started | May 30 12:36:57 PM PDT 24 |
| Finished | May 30 12:36:59 PM PDT 24 |
| Peak memory | 182552 kb |
| Host | smart-db790dde-3b04-46f9-a642-a26e15d5163c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698713007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3698713007 |
| Directory | /workspace/47.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3702436290 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 37121672 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:36:47 PM PDT 24 |
| Peak memory | 182492 kb |
| Host | smart-aaa73504-2456-4c1e-b4a9-0c8c02c68151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702436290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3702436290 |
| Directory | /workspace/48.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.668601609 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 11623286 ps |
| CPU time | 0.56 seconds |
| Started | May 30 12:37:01 PM PDT 24 |
| Finished | May 30 12:37:04 PM PDT 24 |
| Peak memory | 182508 kb |
| Host | smart-e286d92b-d3d2-47a4-907e-306794bbce90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668601609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.668601609 |
| Directory | /workspace/49.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.640866067 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 39020744 ps |
| CPU time | 1.09 seconds |
| Started | May 30 12:36:31 PM PDT 24 |
| Finished | May 30 12:36:33 PM PDT 24 |
| Peak memory | 197332 kb |
| Host | smart-14ebefea-a3b9-42d4-bda2-50bc54bb1cab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640866067 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.640866067 |
| Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3496335641 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 28952677 ps |
| CPU time | 0.6 seconds |
| Started | May 30 12:36:42 PM PDT 24 |
| Finished | May 30 12:36:44 PM PDT 24 |
| Peak memory | 182596 kb |
| Host | smart-5005e8dd-8079-4e6a-a21d-77a3c97ecfae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496335641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3496335641 |
| Directory | /workspace/5.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1775824466 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 11104329 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:36 PM PDT 24 |
| Peak memory | 182596 kb |
| Host | smart-31c9868c-6df9-4f23-99d5-beca0ca430c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775824466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1775824466 |
| Directory | /workspace/5.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2740281813 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 23174841 ps |
| CPU time | 0.64 seconds |
| Started | May 30 12:36:34 PM PDT 24 |
| Finished | May 30 12:36:36 PM PDT 24 |
| Peak memory | 191504 kb |
| Host | smart-1e8c1c35-bb37-4a86-b728-68da2b6e584a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740281813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti mer_same_csr_outstanding.2740281813 |
| Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1514956900 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 32063097 ps |
| CPU time | 0.91 seconds |
| Started | May 30 12:36:26 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 197040 kb |
| Host | smart-7d10fe10-a527-4339-9ea1-fde286c42c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514956900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1514956900 |
| Directory | /workspace/5.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3161444722 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 327080926 ps |
| CPU time | 1.3 seconds |
| Started | May 30 12:36:40 PM PDT 24 |
| Finished | May 30 12:36:48 PM PDT 24 |
| Peak memory | 195156 kb |
| Host | smart-22b24fd1-fae0-40d4-850a-f19a6f9af3f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161444722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in tg_err.3161444722 |
| Directory | /workspace/5.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.963237250 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 100242045 ps |
| CPU time | 0.81 seconds |
| Started | May 30 12:36:20 PM PDT 24 |
| Finished | May 30 12:36:22 PM PDT 24 |
| Peak memory | 196408 kb |
| Host | smart-24dfa5e7-b2f1-4d85-9b61-f94aded4e024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963237250 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.963237250 |
| Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2639071186 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 22477720 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:29 PM PDT 24 |
| Finished | May 30 12:36:30 PM PDT 24 |
| Peak memory | 182592 kb |
| Host | smart-824a7e58-9c1b-4efc-af00-06d2f6a25c33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639071186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2639071186 |
| Directory | /workspace/6.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4108472248 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 11887698 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:36 PM PDT 24 |
| Finished | May 30 12:36:37 PM PDT 24 |
| Peak memory | 182176 kb |
| Host | smart-779e2752-4a58-4543-b988-ceff14ce5989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108472248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4108472248 |
| Directory | /workspace/6.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2966151348 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 95447637 ps |
| CPU time | 0.76 seconds |
| Started | May 30 12:36:28 PM PDT 24 |
| Finished | May 30 12:36:30 PM PDT 24 |
| Peak memory | 193320 kb |
| Host | smart-1f219d5a-399a-42bf-b977-cfce4a1156fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966151348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.2966151348 |
| Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1198306822 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 209521054 ps |
| CPU time | 2.06 seconds |
| Started | May 30 12:36:17 PM PDT 24 |
| Finished | May 30 12:36:21 PM PDT 24 |
| Peak memory | 197532 kb |
| Host | smart-3647f125-079b-4327-81cd-e08da8deb424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198306822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1198306822 |
| Directory | /workspace/6.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2345770531 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 95673404 ps |
| CPU time | 1.31 seconds |
| Started | May 30 12:36:32 PM PDT 24 |
| Finished | May 30 12:36:34 PM PDT 24 |
| Peak memory | 195556 kb |
| Host | smart-f45ce15a-3b9f-4c09-933e-520998b789b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345770531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in tg_err.2345770531 |
| Directory | /workspace/6.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2798351584 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 337583504 ps |
| CPU time | 0.85 seconds |
| Started | May 30 12:36:33 PM PDT 24 |
| Finished | May 30 12:36:35 PM PDT 24 |
| Peak memory | 195980 kb |
| Host | smart-b30e37b8-0d34-4339-b000-7c42807cda63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798351584 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2798351584 |
| Directory | /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4264318185 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 32179604 ps |
| CPU time | 0.58 seconds |
| Started | May 30 12:36:30 PM PDT 24 |
| Finished | May 30 12:36:32 PM PDT 24 |
| Peak memory | 182588 kb |
| Host | smart-be00aa28-9978-4c1e-99a0-03f912640af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264318185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.4264318185 |
| Directory | /workspace/7.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2233067326 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 16303314 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:36:32 PM PDT 24 |
| Finished | May 30 12:36:34 PM PDT 24 |
| Peak memory | 182468 kb |
| Host | smart-9180c3f0-f6fa-4520-bdcb-4ec6b70512d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233067326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2233067326 |
| Directory | /workspace/7.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1586172621 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 54549992 ps |
| CPU time | 0.77 seconds |
| Started | May 30 12:36:27 PM PDT 24 |
| Finished | May 30 12:36:29 PM PDT 24 |
| Peak memory | 191616 kb |
| Host | smart-08673dfe-fa58-47d3-8c5e-efa815091060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586172621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti mer_same_csr_outstanding.1586172621 |
| Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.920940420 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 229850207 ps |
| CPU time | 3.09 seconds |
| Started | May 30 12:36:18 PM PDT 24 |
| Finished | May 30 12:36:23 PM PDT 24 |
| Peak memory | 197516 kb |
| Host | smart-bdf241bf-2f2f-4c26-b802-bfc276e1cbe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920940420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.920940420 |
| Directory | /workspace/7.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.851197662 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 48116416 ps |
| CPU time | 0.88 seconds |
| Started | May 30 12:36:32 PM PDT 24 |
| Finished | May 30 12:36:34 PM PDT 24 |
| Peak memory | 183144 kb |
| Host | smart-2055ab35-c7e4-45a9-ad91-2bf973e6d1c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851197662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int g_err.851197662 |
| Directory | /workspace/7.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.908435771 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 91619887 ps |
| CPU time | 0.64 seconds |
| Started | May 30 12:36:26 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 194172 kb |
| Host | smart-6eb1f677-6125-4177-8fe3-a9c81e297794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908435771 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.908435771 |
| Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2695196444 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 10577894 ps |
| CPU time | 0.57 seconds |
| Started | May 30 12:36:35 PM PDT 24 |
| Finished | May 30 12:36:37 PM PDT 24 |
| Peak memory | 182728 kb |
| Host | smart-3e8b520a-4801-4de3-809b-53529c68b999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695196444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2695196444 |
| Directory | /workspace/8.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1715946154 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 14696785 ps |
| CPU time | 0.55 seconds |
| Started | May 30 12:36:24 PM PDT 24 |
| Finished | May 30 12:36:26 PM PDT 24 |
| Peak memory | 182512 kb |
| Host | smart-247b6c0f-6a07-46a5-97ec-d752f721aadc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715946154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1715946154 |
| Directory | /workspace/8.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2428011921 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 48519817 ps |
| CPU time | 0.75 seconds |
| Started | May 30 12:36:29 PM PDT 24 |
| Finished | May 30 12:36:31 PM PDT 24 |
| Peak memory | 192648 kb |
| Host | smart-fafc6b53-70cc-47ec-be2a-5409f63a9af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428011921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti mer_same_csr_outstanding.2428011921 |
| Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.4248920181 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 226776779 ps |
| CPU time | 1.27 seconds |
| Started | May 30 12:36:39 PM PDT 24 |
| Finished | May 30 12:36:42 PM PDT 24 |
| Peak memory | 197504 kb |
| Host | smart-3c7308b9-ae28-4f55-88e7-755ad8f3c36e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248920181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.4248920181 |
| Directory | /workspace/8.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4085774287 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 81387453 ps |
| CPU time | 0.8 seconds |
| Started | May 30 12:36:32 PM PDT 24 |
| Finished | May 30 12:36:34 PM PDT 24 |
| Peak memory | 193172 kb |
| Host | smart-6de248d5-f3ff-4fbf-82d4-01703ed4d5d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085774287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in tg_err.4085774287 |
| Directory | /workspace/8.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3510295776 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 228167669 ps |
| CPU time | 0.76 seconds |
| Started | May 30 12:36:43 PM PDT 24 |
| Finished | May 30 12:36:45 PM PDT 24 |
| Peak memory | 194860 kb |
| Host | smart-21ee4962-1025-44e7-bae8-766f38d98c7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510295776 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3510295776 |
| Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2708580683 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 20341337 ps |
| CPU time | 0.62 seconds |
| Started | May 30 12:36:25 PM PDT 24 |
| Finished | May 30 12:36:27 PM PDT 24 |
| Peak memory | 182588 kb |
| Host | smart-82bc09fe-0765-4224-884c-dc834aba918d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708580683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2708580683 |
| Directory | /workspace/9.rv_timer_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2389921996 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 42307550 ps |
| CPU time | 0.52 seconds |
| Started | May 30 12:36:23 PM PDT 24 |
| Finished | May 30 12:36:24 PM PDT 24 |
| Peak memory | 182212 kb |
| Host | smart-0d0eeeed-2d60-4d06-805b-2138f6a7a3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389921996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2389921996 |
| Directory | /workspace/9.rv_timer_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3564476818 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 41976751 ps |
| CPU time | 0.85 seconds |
| Started | May 30 12:36:26 PM PDT 24 |
| Finished | May 30 12:36:28 PM PDT 24 |
| Peak memory | 191712 kb |
| Host | smart-2612887b-8bcc-4bf0-b5a9-6683ef3c2782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564476818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.3564476818 |
| Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3514974899 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 59501525 ps |
| CPU time | 1.39 seconds |
| Started | May 30 12:36:27 PM PDT 24 |
| Finished | May 30 12:36:30 PM PDT 24 |
| Peak memory | 197580 kb |
| Host | smart-329ec723-7a57-4bc7-8835-ab2bbc78c603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514974899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3514974899 |
| Directory | /workspace/9.rv_timer_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2823782075 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 117665671 ps |
| CPU time | 1.25 seconds |
| Started | May 30 12:36:35 PM PDT 24 |
| Finished | May 30 12:36:38 PM PDT 24 |
| Peak memory | 183420 kb |
| Host | smart-584953e1-36ae-43ad-895e-f379ad414a63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823782075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.2823782075 |
| Directory | /workspace/9.rv_timer_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1390357891 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 251480716097 ps |
| CPU time | 427.29 seconds |
| Started | May 30 12:36:52 PM PDT 24 |
| Finished | May 30 12:44:01 PM PDT 24 |
| Peak memory | 182856 kb |
| Host | smart-53e44f4f-2eb8-4ef6-9d25-db5b4ab30a41 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390357891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.1390357891 |
| Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/0.rv_timer_disabled.2234656411 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 100060922936 ps |
| CPU time | 166.92 seconds |
| Started | May 30 12:36:51 PM PDT 24 |
| Finished | May 30 12:39:39 PM PDT 24 |
| Peak memory | 182916 kb |
| Host | smart-ab02eebd-7166-4785-b18b-33049ccb94d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234656411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2234656411 |
| Directory | /workspace/0.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/0.rv_timer_random_reset.3720842056 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 149696854994 ps |
| CPU time | 74.99 seconds |
| Started | May 30 12:36:43 PM PDT 24 |
| Finished | May 30 12:37:59 PM PDT 24 |
| Peak memory | 182816 kb |
| Host | smart-07230a12-905a-4fdb-9129-d40a9616dc36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3720842056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3720842056 |
| Directory | /workspace/0.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/0.rv_timer_stress_all.3276837093 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 179290160195 ps |
| CPU time | 344.19 seconds |
| Started | May 30 12:36:57 PM PDT 24 |
| Finished | May 30 12:42:42 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-aa9dcb29-59ab-46e7-bab9-61e4e9954096 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276837093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 3276837093 |
| Directory | /workspace/0.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.256747184 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3204890941148 ps |
| CPU time | 1445.9 seconds |
| Started | May 30 12:36:48 PM PDT 24 |
| Finished | May 30 01:00:54 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-425ccf9f-7eca-49bb-9201-db6104792edc |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256747184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rv_timer_cfg_update_on_fly.256747184 |
| Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/1.rv_timer_disabled.2606908626 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 459427298089 ps |
| CPU time | 181.02 seconds |
| Started | May 30 12:36:56 PM PDT 24 |
| Finished | May 30 12:39:58 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-c7ee0daf-bf5c-4dff-8353-9bfbd484c877 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606908626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2606908626 |
| Directory | /workspace/1.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/1.rv_timer_sec_cm.272533373 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 136213598 ps |
| CPU time | 0.8 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:36:49 PM PDT 24 |
| Peak memory | 213340 kb |
| Host | smart-214601e9-d566-4333-9f76-45f0393db61a |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272533373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.272533373 |
| Directory | /workspace/1.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/1.rv_timer_stress_all.1511356296 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 195609801728 ps |
| CPU time | 112.38 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:38:39 PM PDT 24 |
| Peak memory | 182824 kb |
| Host | smart-75ead052-e3fe-4a01-b903-4f7ff1277d95 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511356296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 1511356296 |
| Directory | /workspace/1.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2729761815 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 134111947854 ps |
| CPU time | 222.66 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:40:31 PM PDT 24 |
| Peak memory | 182880 kb |
| Host | smart-e799345b-1b87-42a8-8188-de257e64cb74 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729761815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.2729761815 |
| Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/10.rv_timer_disabled.845835805 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 295150000233 ps |
| CPU time | 113.9 seconds |
| Started | May 30 12:36:51 PM PDT 24 |
| Finished | May 30 12:38:46 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-9f80ea08-ffcb-4b60-bab8-aeb0691d291b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845835805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.845835805 |
| Directory | /workspace/10.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random.793997348 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 45792920619 ps |
| CPU time | 70.94 seconds |
| Started | May 30 12:36:56 PM PDT 24 |
| Finished | May 30 12:38:08 PM PDT 24 |
| Peak memory | 182972 kb |
| Host | smart-673e4dcc-68aa-4184-b19b-e34a770151bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793997348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.793997348 |
| Directory | /workspace/10.rv_timer_random/latest |
| Test location | /workspace/coverage/default/10.rv_timer_random_reset.1029127350 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 29990938671 ps |
| CPU time | 34.94 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:37:23 PM PDT 24 |
| Peak memory | 182876 kb |
| Host | smart-c6aed61c-d6bb-4719-b1ef-225eb4a6bce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1029127350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1029127350 |
| Directory | /workspace/10.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/10.rv_timer_stress_all.2212015231 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 474529053861 ps |
| CPU time | 709.39 seconds |
| Started | May 30 12:36:53 PM PDT 24 |
| Finished | May 30 12:48:44 PM PDT 24 |
| Peak memory | 191044 kb |
| Host | smart-5a1ceb58-605d-4159-8bec-e90e45a1359f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212015231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all .2212015231 |
| Directory | /workspace/10.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/101.rv_timer_random.2573537136 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 195062526578 ps |
| CPU time | 194.85 seconds |
| Started | May 30 12:37:37 PM PDT 24 |
| Finished | May 30 12:40:53 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-fa4b94eb-d74a-4be9-907f-00b6b9f6fb15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573537136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2573537136 |
| Directory | /workspace/101.rv_timer_random/latest |
| Test location | /workspace/coverage/default/104.rv_timer_random.2951589735 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 155837008373 ps |
| CPU time | 133.48 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:39:50 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-0c196762-9093-45ca-a366-f265425a06d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951589735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2951589735 |
| Directory | /workspace/104.rv_timer_random/latest |
| Test location | /workspace/coverage/default/105.rv_timer_random.1732693002 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 277644387105 ps |
| CPU time | 158.05 seconds |
| Started | May 30 12:37:40 PM PDT 24 |
| Finished | May 30 12:40:19 PM PDT 24 |
| Peak memory | 191112 kb |
| Host | smart-0c9465ae-2dfc-425d-90e0-d1381b73f95d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732693002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1732693002 |
| Directory | /workspace/105.rv_timer_random/latest |
| Test location | /workspace/coverage/default/108.rv_timer_random.1203496906 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 89601605283 ps |
| CPU time | 34.16 seconds |
| Started | May 30 12:37:40 PM PDT 24 |
| Finished | May 30 12:38:15 PM PDT 24 |
| Peak memory | 182916 kb |
| Host | smart-7ae2831a-bf64-4330-9f49-b6b53c2609d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203496906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1203496906 |
| Directory | /workspace/108.rv_timer_random/latest |
| Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1021622690 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 904271626967 ps |
| CPU time | 833.99 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 12:50:41 PM PDT 24 |
| Peak memory | 182856 kb |
| Host | smart-616c9447-f311-46a9-a0b9-a3804fdde476 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021622690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.1021622690 |
| Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/11.rv_timer_disabled.2448664621 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 142961240102 ps |
| CPU time | 236.47 seconds |
| Started | May 30 12:36:48 PM PDT 24 |
| Finished | May 30 12:40:45 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-c4e0ae17-52ea-4ab1-a76c-897452a9e87d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448664621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2448664621 |
| Directory | /workspace/11.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/11.rv_timer_random_reset.3577641419 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 18674068 ps |
| CPU time | 0.54 seconds |
| Started | May 30 12:37:02 PM PDT 24 |
| Finished | May 30 12:37:05 PM PDT 24 |
| Peak memory | 182728 kb |
| Host | smart-9b71dbe6-2afb-4e91-80f2-30fd27cff268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577641419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3577641419 |
| Directory | /workspace/11.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.1559556539 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 62741945865 ps |
| CPU time | 641.04 seconds |
| Started | May 30 12:37:05 PM PDT 24 |
| Finished | May 30 12:47:48 PM PDT 24 |
| Peak memory | 206100 kb |
| Host | smart-4145b932-ad47-4957-8906-f72b9c18f54a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559556539 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.1559556539 |
| Directory | /workspace/11.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/110.rv_timer_random.892787542 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 9729823900 ps |
| CPU time | 17.75 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:37:54 PM PDT 24 |
| Peak memory | 182852 kb |
| Host | smart-e4cf7264-a7da-4aa1-b49f-df480c3a5c28 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892787542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.892787542 |
| Directory | /workspace/110.rv_timer_random/latest |
| Test location | /workspace/coverage/default/111.rv_timer_random.84127554 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 21176737873 ps |
| CPU time | 14.13 seconds |
| Started | May 30 12:37:38 PM PDT 24 |
| Finished | May 30 12:37:54 PM PDT 24 |
| Peak memory | 182848 kb |
| Host | smart-03682277-829a-4cb0-8438-23bbd8c9c39a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84127554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.84127554 |
| Directory | /workspace/111.rv_timer_random/latest |
| Test location | /workspace/coverage/default/114.rv_timer_random.1370802099 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 213242465652 ps |
| CPU time | 110.74 seconds |
| Started | May 30 12:37:41 PM PDT 24 |
| Finished | May 30 12:39:32 PM PDT 24 |
| Peak memory | 191116 kb |
| Host | smart-9d294cf0-f994-4304-a273-78a5e1b42a54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370802099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1370802099 |
| Directory | /workspace/114.rv_timer_random/latest |
| Test location | /workspace/coverage/default/115.rv_timer_random.4259014802 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 273510422727 ps |
| CPU time | 336.57 seconds |
| Started | May 30 12:37:40 PM PDT 24 |
| Finished | May 30 12:43:17 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-fe5f6fc8-1e4c-4327-a9ea-64880f0ab70d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259014802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4259014802 |
| Directory | /workspace/115.rv_timer_random/latest |
| Test location | /workspace/coverage/default/117.rv_timer_random.1088858816 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 33710489224 ps |
| CPU time | 33.82 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:38:11 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-2b9adf01-c52d-4fa0-a8da-0a24ccba5f15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088858816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1088858816 |
| Directory | /workspace/117.rv_timer_random/latest |
| Test location | /workspace/coverage/default/119.rv_timer_random.4217994027 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 391333651171 ps |
| CPU time | 224.99 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:41:17 PM PDT 24 |
| Peak memory | 191120 kb |
| Host | smart-bb5ba312-1b08-4f28-87fd-0e39cd54e1d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217994027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4217994027 |
| Directory | /workspace/119.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_disabled.974195108 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 281969517617 ps |
| CPU time | 211.2 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:40:49 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-4f9e1aec-c3b2-45e5-8143-dc3451aa595a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974195108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.974195108 |
| Directory | /workspace/12.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random.3600564078 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 36123474656 ps |
| CPU time | 55.16 seconds |
| Started | May 30 12:37:00 PM PDT 24 |
| Finished | May 30 12:37:57 PM PDT 24 |
| Peak memory | 190992 kb |
| Host | smart-02fd8702-ee91-4a17-b4d0-30451f42199f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600564078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3600564078 |
| Directory | /workspace/12.rv_timer_random/latest |
| Test location | /workspace/coverage/default/12.rv_timer_random_reset.437892124 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 244455276976 ps |
| CPU time | 552.17 seconds |
| Started | May 30 12:36:57 PM PDT 24 |
| Finished | May 30 12:46:10 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-8dfc3abd-e5f4-4ccd-ba2f-649095859e07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437892124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.437892124 |
| Directory | /workspace/12.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/120.rv_timer_random.2642507440 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 47816953479 ps |
| CPU time | 82.93 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 12:39:02 PM PDT 24 |
| Peak memory | 190800 kb |
| Host | smart-68123987-aaa0-4be3-8fe0-86610ea94d03 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642507440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2642507440 |
| Directory | /workspace/120.rv_timer_random/latest |
| Test location | /workspace/coverage/default/121.rv_timer_random.2232322410 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 70442556119 ps |
| CPU time | 165.79 seconds |
| Started | May 30 12:37:43 PM PDT 24 |
| Finished | May 30 12:40:30 PM PDT 24 |
| Peak memory | 191040 kb |
| Host | smart-2635ec99-c051-4b68-a40e-06d280c2fbdb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232322410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2232322410 |
| Directory | /workspace/121.rv_timer_random/latest |
| Test location | /workspace/coverage/default/122.rv_timer_random.1385011401 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 156890750049 ps |
| CPU time | 1613.49 seconds |
| Started | May 30 12:37:41 PM PDT 24 |
| Finished | May 30 01:04:36 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-5df43cc2-223c-47ba-aa37-b9edbe426eaf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385011401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1385011401 |
| Directory | /workspace/122.rv_timer_random/latest |
| Test location | /workspace/coverage/default/123.rv_timer_random.1197444135 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 49302643077 ps |
| CPU time | 107.46 seconds |
| Started | May 30 12:37:31 PM PDT 24 |
| Finished | May 30 12:39:20 PM PDT 24 |
| Peak memory | 191044 kb |
| Host | smart-4d89dc64-fae4-4408-88ae-5adda10e0f12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197444135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1197444135 |
| Directory | /workspace/123.rv_timer_random/latest |
| Test location | /workspace/coverage/default/124.rv_timer_random.4052627579 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 28817899637 ps |
| CPU time | 14.03 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:37:46 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-1a8bbdd3-9460-4429-8181-9ece973cf9f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052627579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.4052627579 |
| Directory | /workspace/124.rv_timer_random/latest |
| Test location | /workspace/coverage/default/125.rv_timer_random.3789332866 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 66704370246 ps |
| CPU time | 23.81 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:37:57 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-0e5e7184-9227-4790-909b-c097f0e26a7c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789332866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3789332866 |
| Directory | /workspace/125.rv_timer_random/latest |
| Test location | /workspace/coverage/default/126.rv_timer_random.2992008104 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 88613567797 ps |
| CPU time | 158.44 seconds |
| Started | May 30 12:37:31 PM PDT 24 |
| Finished | May 30 12:40:11 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-66bf0165-82ea-4e51-a30c-986640a02122 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992008104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2992008104 |
| Directory | /workspace/126.rv_timer_random/latest |
| Test location | /workspace/coverage/default/127.rv_timer_random.2310077417 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 216848097954 ps |
| CPU time | 130.49 seconds |
| Started | May 30 12:37:47 PM PDT 24 |
| Finished | May 30 12:39:59 PM PDT 24 |
| Peak memory | 191040 kb |
| Host | smart-fb624421-51b8-4817-b614-41568d0841d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310077417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2310077417 |
| Directory | /workspace/127.rv_timer_random/latest |
| Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3956220936 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 7202437770 ps |
| CPU time | 6.86 seconds |
| Started | May 30 12:37:07 PM PDT 24 |
| Finished | May 30 12:37:16 PM PDT 24 |
| Peak memory | 182940 kb |
| Host | smart-c09021b4-8146-4344-98dc-03220f73f2af |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956220936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.3956220936 |
| Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/13.rv_timer_disabled.306155597 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 565129393376 ps |
| CPU time | 219.26 seconds |
| Started | May 30 12:37:03 PM PDT 24 |
| Finished | May 30 12:40:44 PM PDT 24 |
| Peak memory | 182872 kb |
| Host | smart-97ba2535-372c-4bc8-a7b6-9950d8b17b00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306155597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.306155597 |
| Directory | /workspace/13.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/13.rv_timer_random.3644240764 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 156027589842 ps |
| CPU time | 99.16 seconds |
| Started | May 30 12:37:07 PM PDT 24 |
| Finished | May 30 12:38:48 PM PDT 24 |
| Peak memory | 191184 kb |
| Host | smart-4c6695f9-c629-485b-85f4-c8e7ca4654a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644240764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3644240764 |
| Directory | /workspace/13.rv_timer_random/latest |
| Test location | /workspace/coverage/default/130.rv_timer_random.1665051912 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 182204186688 ps |
| CPU time | 304.53 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:42:41 PM PDT 24 |
| Peak memory | 191052 kb |
| Host | smart-c23338fd-8737-486e-abe8-955774f983ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665051912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1665051912 |
| Directory | /workspace/130.rv_timer_random/latest |
| Test location | /workspace/coverage/default/131.rv_timer_random.2717500402 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 38897012853 ps |
| CPU time | 330.55 seconds |
| Started | May 30 12:37:42 PM PDT 24 |
| Finished | May 30 12:43:13 PM PDT 24 |
| Peak memory | 191052 kb |
| Host | smart-cca35593-6e40-4e56-a474-6fa4dc955862 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717500402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2717500402 |
| Directory | /workspace/131.rv_timer_random/latest |
| Test location | /workspace/coverage/default/133.rv_timer_random.2941785015 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 983465295460 ps |
| CPU time | 445.9 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:44:57 PM PDT 24 |
| Peak memory | 191052 kb |
| Host | smart-117ac0c0-3910-4e14-a5e6-976053dd2f3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941785015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2941785015 |
| Directory | /workspace/133.rv_timer_random/latest |
| Test location | /workspace/coverage/default/134.rv_timer_random.362082122 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 711601585762 ps |
| CPU time | 998.38 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:54:10 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-127b094a-c517-444c-9d84-2952ef7a22b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362082122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.362082122 |
| Directory | /workspace/134.rv_timer_random/latest |
| Test location | /workspace/coverage/default/135.rv_timer_random.3672988866 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 186646111624 ps |
| CPU time | 94.04 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:39:05 PM PDT 24 |
| Peak memory | 182852 kb |
| Host | smart-b21ab437-9343-466d-9cf0-72647d47e185 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672988866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3672988866 |
| Directory | /workspace/135.rv_timer_random/latest |
| Test location | /workspace/coverage/default/136.rv_timer_random.438567545 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2346365345404 ps |
| CPU time | 953.34 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:53:27 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-1775aedf-2c91-402e-bb0a-ead37dd6761a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438567545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.438567545 |
| Directory | /workspace/136.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.4184284675 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 512596500278 ps |
| CPU time | 935.59 seconds |
| Started | May 30 12:37:00 PM PDT 24 |
| Finished | May 30 12:52:37 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-37986f90-7647-4ee7-af97-5ff9997de832 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184284675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.4184284675 |
| Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/14.rv_timer_disabled.2491321506 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 79981495294 ps |
| CPU time | 121.58 seconds |
| Started | May 30 12:37:03 PM PDT 24 |
| Finished | May 30 12:39:06 PM PDT 24 |
| Peak memory | 182972 kb |
| Host | smart-778cf49a-d380-4506-9084-30eace156f06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491321506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2491321506 |
| Directory | /workspace/14.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random.2852127220 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 179558488566 ps |
| CPU time | 715.54 seconds |
| Started | May 30 12:37:04 PM PDT 24 |
| Finished | May 30 12:49:02 PM PDT 24 |
| Peak memory | 191080 kb |
| Host | smart-4bacc2af-ed68-4fa1-84ea-8012327b7e30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852127220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2852127220 |
| Directory | /workspace/14.rv_timer_random/latest |
| Test location | /workspace/coverage/default/14.rv_timer_random_reset.4126478578 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 117245693137 ps |
| CPU time | 103.18 seconds |
| Started | May 30 12:37:14 PM PDT 24 |
| Finished | May 30 12:38:58 PM PDT 24 |
| Peak memory | 191056 kb |
| Host | smart-e7459da9-4b19-4b04-bd9a-576f9b1aa7d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4126478578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4126478578 |
| Directory | /workspace/14.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/140.rv_timer_random.3511466276 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 255612865113 ps |
| CPU time | 336.45 seconds |
| Started | May 30 12:37:35 PM PDT 24 |
| Finished | May 30 12:43:13 PM PDT 24 |
| Peak memory | 191044 kb |
| Host | smart-d34cc223-8489-4466-b527-4051b7761287 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511466276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3511466276 |
| Directory | /workspace/140.rv_timer_random/latest |
| Test location | /workspace/coverage/default/142.rv_timer_random.3672860162 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 271028179510 ps |
| CPU time | 272.57 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 12:42:12 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-4cb6d9e2-5b01-4fcd-b13f-19413ec85237 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672860162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3672860162 |
| Directory | /workspace/142.rv_timer_random/latest |
| Test location | /workspace/coverage/default/144.rv_timer_random.3276364751 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 139465508979 ps |
| CPU time | 608.32 seconds |
| Started | May 30 12:37:41 PM PDT 24 |
| Finished | May 30 12:47:50 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-7eb9d042-0612-4ad6-bcc6-30d9d3f55aec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276364751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3276364751 |
| Directory | /workspace/144.rv_timer_random/latest |
| Test location | /workspace/coverage/default/145.rv_timer_random.3895202231 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 11635269809 ps |
| CPU time | 16.92 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:37:51 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-31160f92-0c2d-44e3-b3cb-1d1de9a9697d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895202231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3895202231 |
| Directory | /workspace/145.rv_timer_random/latest |
| Test location | /workspace/coverage/default/146.rv_timer_random.3846489312 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 214872400619 ps |
| CPU time | 65.77 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:38:41 PM PDT 24 |
| Peak memory | 182812 kb |
| Host | smart-d073e4b9-e401-4eb2-acfe-38ffa9902343 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846489312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3846489312 |
| Directory | /workspace/146.rv_timer_random/latest |
| Test location | /workspace/coverage/default/147.rv_timer_random.904437569 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 107935089895 ps |
| CPU time | 201.46 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 12:41:06 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-76dbdc3c-20d7-4d55-ad58-a382d9251121 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904437569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.904437569 |
| Directory | /workspace/147.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1444114336 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 438439818023 ps |
| CPU time | 209.13 seconds |
| Started | May 30 12:37:11 PM PDT 24 |
| Finished | May 30 12:40:41 PM PDT 24 |
| Peak memory | 182860 kb |
| Host | smart-18679057-14d4-47b9-91f4-6d976a0978e8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444114336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1444114336 |
| Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/15.rv_timer_disabled.3274013556 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 48983694045 ps |
| CPU time | 22.69 seconds |
| Started | May 30 12:37:10 PM PDT 24 |
| Finished | May 30 12:37:34 PM PDT 24 |
| Peak memory | 182828 kb |
| Host | smart-ca652f37-489c-4a5f-9499-11e95df6b219 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3274013556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3274013556 |
| Directory | /workspace/15.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random.719630822 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 150141346242 ps |
| CPU time | 297.49 seconds |
| Started | May 30 12:37:09 PM PDT 24 |
| Finished | May 30 12:42:07 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-e5190639-208b-4bc4-8976-27f816ce0b05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719630822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.719630822 |
| Directory | /workspace/15.rv_timer_random/latest |
| Test location | /workspace/coverage/default/15.rv_timer_random_reset.3257089028 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 73290946516 ps |
| CPU time | 74.5 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:38:37 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-fc9968cf-e07d-427f-a583-c8a778241d79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257089028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3257089028 |
| Directory | /workspace/15.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/15.rv_timer_stress_all.3279055144 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 184937514617 ps |
| CPU time | 918.8 seconds |
| Started | May 30 12:37:01 PM PDT 24 |
| Finished | May 30 12:52:22 PM PDT 24 |
| Peak memory | 191048 kb |
| Host | smart-561d6e4d-25e3-4b33-ac55-2747c081f492 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279055144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .3279055144 |
| Directory | /workspace/15.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/150.rv_timer_random.913870554 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 41403973057 ps |
| CPU time | 69.13 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:38:44 PM PDT 24 |
| Peak memory | 182816 kb |
| Host | smart-a701a713-5187-4c36-9437-ca73762578b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913870554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.913870554 |
| Directory | /workspace/150.rv_timer_random/latest |
| Test location | /workspace/coverage/default/151.rv_timer_random.3205841033 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 53429534998 ps |
| CPU time | 94.35 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:39:09 PM PDT 24 |
| Peak memory | 190336 kb |
| Host | smart-3015c5f2-e8c0-4af5-80cc-417453a955a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205841033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3205841033 |
| Directory | /workspace/151.rv_timer_random/latest |
| Test location | /workspace/coverage/default/152.rv_timer_random.3019684583 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 49631373290 ps |
| CPU time | 40.1 seconds |
| Started | May 30 12:37:44 PM PDT 24 |
| Finished | May 30 12:38:25 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-36911ce1-f321-47b3-b880-631c40c64d11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019684583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3019684583 |
| Directory | /workspace/152.rv_timer_random/latest |
| Test location | /workspace/coverage/default/156.rv_timer_random.975196711 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 147058522828 ps |
| CPU time | 350.27 seconds |
| Started | May 30 12:37:50 PM PDT 24 |
| Finished | May 30 12:43:41 PM PDT 24 |
| Peak memory | 194552 kb |
| Host | smart-8c5ca5ce-1da8-4689-8946-4591b0bf0793 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975196711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.975196711 |
| Directory | /workspace/156.rv_timer_random/latest |
| Test location | /workspace/coverage/default/159.rv_timer_random.720724853 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5519244395 ps |
| CPU time | 44.54 seconds |
| Started | May 30 12:37:50 PM PDT 24 |
| Finished | May 30 12:38:35 PM PDT 24 |
| Peak memory | 194736 kb |
| Host | smart-ebdc99d1-5c7d-40e7-9e8c-020653c4d2ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720724853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.720724853 |
| Directory | /workspace/159.rv_timer_random/latest |
| Test location | /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2547775316 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 121016490589 ps |
| CPU time | 196.55 seconds |
| Started | May 30 12:37:03 PM PDT 24 |
| Finished | May 30 12:40:21 PM PDT 24 |
| Peak memory | 182816 kb |
| Host | smart-2d56a2e3-4cd4-4626-81c4-d36cd1f8ea81 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547775316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.2547775316 |
| Directory | /workspace/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/16.rv_timer_disabled.421666329 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 100438039817 ps |
| CPU time | 35.67 seconds |
| Started | May 30 12:37:05 PM PDT 24 |
| Finished | May 30 12:37:42 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-5b4a9159-57b5-47eb-ac46-1fc2857dde89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421666329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.421666329 |
| Directory | /workspace/16.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/16.rv_timer_random_reset.1350138546 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 879822987 ps |
| CPU time | 1.81 seconds |
| Started | May 30 12:37:07 PM PDT 24 |
| Finished | May 30 12:37:11 PM PDT 24 |
| Peak memory | 182632 kb |
| Host | smart-193b6041-e7d4-4c0e-b3a7-81634bcc8aa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350138546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1350138546 |
| Directory | /workspace/16.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/160.rv_timer_random.4079819082 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 607955939477 ps |
| CPU time | 1029.86 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:54:46 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-82d03f58-639c-4617-b3be-dda61cf36051 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079819082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4079819082 |
| Directory | /workspace/160.rv_timer_random/latest |
| Test location | /workspace/coverage/default/161.rv_timer_random.4253208433 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 225193962341 ps |
| CPU time | 80.45 seconds |
| Started | May 30 12:37:45 PM PDT 24 |
| Finished | May 30 12:39:06 PM PDT 24 |
| Peak memory | 182848 kb |
| Host | smart-bff13c06-18a4-42d8-a665-ab4167bbd39e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253208433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4253208433 |
| Directory | /workspace/161.rv_timer_random/latest |
| Test location | /workspace/coverage/default/164.rv_timer_random.2686697632 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 120358439401 ps |
| CPU time | 222.75 seconds |
| Started | May 30 12:37:43 PM PDT 24 |
| Finished | May 30 12:41:27 PM PDT 24 |
| Peak memory | 194556 kb |
| Host | smart-bd8cdfcb-39cc-46f9-85c5-558b8904c021 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686697632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2686697632 |
| Directory | /workspace/164.rv_timer_random/latest |
| Test location | /workspace/coverage/default/166.rv_timer_random.3173059133 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 98101230454 ps |
| CPU time | 45.47 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:38:17 PM PDT 24 |
| Peak memory | 194576 kb |
| Host | smart-4ec10c84-e2a8-4cb4-948f-7da520e80c19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173059133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3173059133 |
| Directory | /workspace/166.rv_timer_random/latest |
| Test location | /workspace/coverage/default/167.rv_timer_random.3080170275 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 17176516747 ps |
| CPU time | 29.51 seconds |
| Started | May 30 12:37:49 PM PDT 24 |
| Finished | May 30 12:38:19 PM PDT 24 |
| Peak memory | 182848 kb |
| Host | smart-54bebda0-856d-4547-b808-c0e7adb27c7d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080170275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3080170275 |
| Directory | /workspace/167.rv_timer_random/latest |
| Test location | /workspace/coverage/default/168.rv_timer_random.1250818315 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 70858103574 ps |
| CPU time | 273.13 seconds |
| Started | May 30 12:37:47 PM PDT 24 |
| Finished | May 30 12:42:21 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-38f57aeb-a3a2-4def-b782-af34c877d12f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250818315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1250818315 |
| Directory | /workspace/168.rv_timer_random/latest |
| Test location | /workspace/coverage/default/169.rv_timer_random.3575892108 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 58374094915 ps |
| CPU time | 95.35 seconds |
| Started | May 30 12:37:42 PM PDT 24 |
| Finished | May 30 12:39:18 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-16c02a02-1c11-4c39-a1e8-c671ae4b1c9c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575892108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3575892108 |
| Directory | /workspace/169.rv_timer_random/latest |
| Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1867068402 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 904428200 ps |
| CPU time | 2.23 seconds |
| Started | May 30 12:37:03 PM PDT 24 |
| Finished | May 30 12:37:07 PM PDT 24 |
| Peak memory | 182664 kb |
| Host | smart-12dcfbeb-fc78-4650-b5e5-64134745bc63 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867068402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.1867068402 |
| Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/17.rv_timer_disabled.1945049562 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 24142357447 ps |
| CPU time | 36.67 seconds |
| Started | May 30 12:37:09 PM PDT 24 |
| Finished | May 30 12:37:46 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-920b41c3-7c43-4254-882b-e506a64e4e77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945049562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1945049562 |
| Directory | /workspace/17.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/17.rv_timer_random_reset.76296055 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 169958800834 ps |
| CPU time | 242.97 seconds |
| Started | May 30 12:37:13 PM PDT 24 |
| Finished | May 30 12:41:17 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-12b80e6d-37b9-4b57-8721-ccd2cecc7961 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=76296055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.76296055 |
| Directory | /workspace/17.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1066739516 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 145428118846 ps |
| CPU time | 328.88 seconds |
| Started | May 30 12:37:10 PM PDT 24 |
| Finished | May 30 12:42:40 PM PDT 24 |
| Peak memory | 197504 kb |
| Host | smart-d71aaa0e-a330-403f-8260-490395bac308 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066739516 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1066739516 |
| Directory | /workspace/17.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/170.rv_timer_random.3643101250 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 122902957165 ps |
| CPU time | 388.62 seconds |
| Started | May 30 12:37:48 PM PDT 24 |
| Finished | May 30 12:44:18 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-df17d868-061a-489b-b94b-f50be9e18013 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643101250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3643101250 |
| Directory | /workspace/170.rv_timer_random/latest |
| Test location | /workspace/coverage/default/171.rv_timer_random.2117227083 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 38064768335 ps |
| CPU time | 23.51 seconds |
| Started | May 30 12:37:41 PM PDT 24 |
| Finished | May 30 12:38:06 PM PDT 24 |
| Peak memory | 182860 kb |
| Host | smart-9265a5fc-3dbb-4555-9d6c-58a056039e28 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117227083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2117227083 |
| Directory | /workspace/171.rv_timer_random/latest |
| Test location | /workspace/coverage/default/173.rv_timer_random.1087368835 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 173708028716 ps |
| CPU time | 87.18 seconds |
| Started | May 30 12:37:48 PM PDT 24 |
| Finished | May 30 12:39:17 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-de34740e-9fc3-45d8-801c-4c1c2a6e44bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087368835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1087368835 |
| Directory | /workspace/173.rv_timer_random/latest |
| Test location | /workspace/coverage/default/174.rv_timer_random.63117119 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 216300608703 ps |
| CPU time | 523.47 seconds |
| Started | May 30 12:37:56 PM PDT 24 |
| Finished | May 30 12:46:40 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-e6051f92-c76f-4624-92ef-eae8497e5f3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63117119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.63117119 |
| Directory | /workspace/174.rv_timer_random/latest |
| Test location | /workspace/coverage/default/175.rv_timer_random.238575704 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 153537522210 ps |
| CPU time | 561.8 seconds |
| Started | May 30 12:37:43 PM PDT 24 |
| Finished | May 30 12:47:06 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-d8672978-d370-4288-9696-b4299c5f664e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238575704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.238575704 |
| Directory | /workspace/175.rv_timer_random/latest |
| Test location | /workspace/coverage/default/178.rv_timer_random.62653367 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 316653478279 ps |
| CPU time | 217.85 seconds |
| Started | May 30 12:38:05 PM PDT 24 |
| Finished | May 30 12:41:43 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-18808812-c396-4555-b3cc-0910247a4d48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62653367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.62653367 |
| Directory | /workspace/178.rv_timer_random/latest |
| Test location | /workspace/coverage/default/179.rv_timer_random.2664887444 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 310363064670 ps |
| CPU time | 2313.94 seconds |
| Started | May 30 12:37:52 PM PDT 24 |
| Finished | May 30 01:16:27 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-ef4656ae-7d30-4c52-a6fa-d2a86046cefb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664887444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2664887444 |
| Directory | /workspace/179.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.734683298 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1117437360695 ps |
| CPU time | 410.38 seconds |
| Started | May 30 12:37:06 PM PDT 24 |
| Finished | May 30 12:43:58 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-d2efe355-ddac-4d24-926c-20f380243fac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734683298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.rv_timer_cfg_update_on_fly.734683298 |
| Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/18.rv_timer_disabled.2005789387 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 31881486027 ps |
| CPU time | 33.62 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:37:51 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-8a038df6-fcb0-4562-82a8-7d03f3e5f8be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005789387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2005789387 |
| Directory | /workspace/18.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random.2732263870 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 234186040514 ps |
| CPU time | 1308.45 seconds |
| Started | May 30 12:37:02 PM PDT 24 |
| Finished | May 30 12:58:53 PM PDT 24 |
| Peak memory | 191048 kb |
| Host | smart-0799ef4a-e987-44c6-888a-871765474c55 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732263870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2732263870 |
| Directory | /workspace/18.rv_timer_random/latest |
| Test location | /workspace/coverage/default/18.rv_timer_random_reset.3029376845 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3049118718 ps |
| CPU time | 6.07 seconds |
| Started | May 30 12:37:03 PM PDT 24 |
| Finished | May 30 12:37:11 PM PDT 24 |
| Peak memory | 182996 kb |
| Host | smart-4129612a-1060-4483-9e4e-23ebffa56cad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3029376845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3029376845 |
| Directory | /workspace/18.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/18.rv_timer_stress_all.377835624 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 118248663574 ps |
| CPU time | 136.62 seconds |
| Started | May 30 12:37:10 PM PDT 24 |
| Finished | May 30 12:39:28 PM PDT 24 |
| Peak memory | 182848 kb |
| Host | smart-0a721801-8296-4e0a-b33c-ba1b4b37784a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377835624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all. 377835624 |
| Directory | /workspace/18.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/180.rv_timer_random.3893920453 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 72514505844 ps |
| CPU time | 131.88 seconds |
| Started | May 30 12:37:45 PM PDT 24 |
| Finished | May 30 12:39:58 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-31636ef1-f658-4b95-b7d8-f03e8ecbfccd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893920453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3893920453 |
| Directory | /workspace/180.rv_timer_random/latest |
| Test location | /workspace/coverage/default/182.rv_timer_random.2417146409 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 38758265319 ps |
| CPU time | 94.98 seconds |
| Started | May 30 12:37:44 PM PDT 24 |
| Finished | May 30 12:39:20 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-f1cfc5ad-7efd-4ef9-a884-493bae09077f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417146409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2417146409 |
| Directory | /workspace/182.rv_timer_random/latest |
| Test location | /workspace/coverage/default/183.rv_timer_random.2258576861 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 377123100340 ps |
| CPU time | 658.99 seconds |
| Started | May 30 12:37:44 PM PDT 24 |
| Finished | May 30 12:48:44 PM PDT 24 |
| Peak memory | 191108 kb |
| Host | smart-c517ffe1-8cc7-4a7a-8d9d-d535427eb7e3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258576861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2258576861 |
| Directory | /workspace/183.rv_timer_random/latest |
| Test location | /workspace/coverage/default/184.rv_timer_random.2767780505 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 150097173409 ps |
| CPU time | 442.03 seconds |
| Started | May 30 12:37:44 PM PDT 24 |
| Finished | May 30 12:45:07 PM PDT 24 |
| Peak memory | 191140 kb |
| Host | smart-e9a8d149-5ef7-441a-ba8d-e1cbff0bfaec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767780505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2767780505 |
| Directory | /workspace/184.rv_timer_random/latest |
| Test location | /workspace/coverage/default/185.rv_timer_random.624374108 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 119223441198 ps |
| CPU time | 95.97 seconds |
| Started | May 30 12:38:03 PM PDT 24 |
| Finished | May 30 12:39:40 PM PDT 24 |
| Peak memory | 191032 kb |
| Host | smart-6e82cb94-2c9e-42cf-a50e-520114548519 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624374108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.624374108 |
| Directory | /workspace/185.rv_timer_random/latest |
| Test location | /workspace/coverage/default/186.rv_timer_random.1755039702 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 250525453449 ps |
| CPU time | 166.04 seconds |
| Started | May 30 12:37:46 PM PDT 24 |
| Finished | May 30 12:40:33 PM PDT 24 |
| Peak memory | 191044 kb |
| Host | smart-26633aef-1901-415f-88c3-5b5b959daf54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755039702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1755039702 |
| Directory | /workspace/186.rv_timer_random/latest |
| Test location | /workspace/coverage/default/187.rv_timer_random.2167927563 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 70087560422 ps |
| CPU time | 292.15 seconds |
| Started | May 30 12:37:39 PM PDT 24 |
| Finished | May 30 12:42:33 PM PDT 24 |
| Peak memory | 191048 kb |
| Host | smart-4f4ad329-4787-4cd0-9c94-a087a745441d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167927563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2167927563 |
| Directory | /workspace/187.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.259314271 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 262390918576 ps |
| CPU time | 121.94 seconds |
| Started | May 30 12:37:00 PM PDT 24 |
| Finished | May 30 12:39:04 PM PDT 24 |
| Peak memory | 182856 kb |
| Host | smart-0a942435-0206-4182-8cfc-4633a4f00f41 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259314271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.rv_timer_cfg_update_on_fly.259314271 |
| Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/19.rv_timer_disabled.2860937742 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 17574137202 ps |
| CPU time | 23.06 seconds |
| Started | May 30 12:37:07 PM PDT 24 |
| Finished | May 30 12:37:31 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-ce245327-68a3-4b6d-9f3e-5698c4db7cc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2860937742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2860937742 |
| Directory | /workspace/19.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random.929731806 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 61070577987 ps |
| CPU time | 50.06 seconds |
| Started | May 30 12:36:54 PM PDT 24 |
| Finished | May 30 12:37:45 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-77149d9b-61e8-44b6-a7a6-b62212c6fc8d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929731806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.929731806 |
| Directory | /workspace/19.rv_timer_random/latest |
| Test location | /workspace/coverage/default/19.rv_timer_random_reset.511829103 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1557558599 ps |
| CPU time | 3.08 seconds |
| Started | May 30 12:37:10 PM PDT 24 |
| Finished | May 30 12:37:14 PM PDT 24 |
| Peak memory | 191436 kb |
| Host | smart-a621947e-1125-4846-ae73-9feab9940764 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511829103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.511829103 |
| Directory | /workspace/19.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/19.rv_timer_stress_all.2121724644 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 717388056730 ps |
| CPU time | 573.3 seconds |
| Started | May 30 12:37:13 PM PDT 24 |
| Finished | May 30 12:46:47 PM PDT 24 |
| Peak memory | 191052 kb |
| Host | smart-44be1cc5-fd3d-419c-abab-7c720b2041c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121724644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all .2121724644 |
| Directory | /workspace/19.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/191.rv_timer_random.405395177 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 86565497509 ps |
| CPU time | 46.83 seconds |
| Started | May 30 12:37:48 PM PDT 24 |
| Finished | May 30 12:38:35 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-6f695f45-3bc8-4ec4-baca-c926f2690d95 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405395177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.405395177 |
| Directory | /workspace/191.rv_timer_random/latest |
| Test location | /workspace/coverage/default/192.rv_timer_random.3656772858 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 105717002951 ps |
| CPU time | 92.09 seconds |
| Started | May 30 12:37:48 PM PDT 24 |
| Finished | May 30 12:39:21 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-052709d2-6bf1-48d5-b399-b1b483cabd54 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656772858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3656772858 |
| Directory | /workspace/192.rv_timer_random/latest |
| Test location | /workspace/coverage/default/193.rv_timer_random.2218564359 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 203928056770 ps |
| CPU time | 163.27 seconds |
| Started | May 30 12:37:48 PM PDT 24 |
| Finished | May 30 12:40:32 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-cad0f235-864c-453a-96e3-8019fe06ee5d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218564359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2218564359 |
| Directory | /workspace/193.rv_timer_random/latest |
| Test location | /workspace/coverage/default/194.rv_timer_random.568146896 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 21607810264 ps |
| CPU time | 97.55 seconds |
| Started | May 30 12:37:48 PM PDT 24 |
| Finished | May 30 12:39:26 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-a3c18ce3-1538-4940-ab92-f4ff748363dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568146896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.568146896 |
| Directory | /workspace/194.rv_timer_random/latest |
| Test location | /workspace/coverage/default/195.rv_timer_random.1078486085 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 429760448393 ps |
| CPU time | 592.74 seconds |
| Started | May 30 12:37:44 PM PDT 24 |
| Finished | May 30 12:47:38 PM PDT 24 |
| Peak memory | 191128 kb |
| Host | smart-4a12bd6f-9671-4426-9c83-cbe56143c87f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078486085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1078486085 |
| Directory | /workspace/195.rv_timer_random/latest |
| Test location | /workspace/coverage/default/196.rv_timer_random.4261108198 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 48875155062 ps |
| CPU time | 81.45 seconds |
| Started | May 30 12:37:48 PM PDT 24 |
| Finished | May 30 12:39:11 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-c9d530c8-fd7b-4695-ba1d-54b40559275b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261108198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.4261108198 |
| Directory | /workspace/196.rv_timer_random/latest |
| Test location | /workspace/coverage/default/197.rv_timer_random.2353623468 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1195665597829 ps |
| CPU time | 450.93 seconds |
| Started | May 30 12:37:44 PM PDT 24 |
| Finished | May 30 12:45:15 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-7e4dada7-aded-482c-9f19-104fb14d9f2d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353623468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2353623468 |
| Directory | /workspace/197.rv_timer_random/latest |
| Test location | /workspace/coverage/default/198.rv_timer_random.3454056384 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 46323063437 ps |
| CPU time | 74.84 seconds |
| Started | May 30 12:37:56 PM PDT 24 |
| Finished | May 30 12:39:12 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-f076ea7e-3238-4569-8e29-5e38e69ac25f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454056384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3454056384 |
| Directory | /workspace/198.rv_timer_random/latest |
| Test location | /workspace/coverage/default/199.rv_timer_random.2368145537 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 53652755700 ps |
| CPU time | 181.91 seconds |
| Started | May 30 12:37:51 PM PDT 24 |
| Finished | May 30 12:40:54 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-789e298a-cae1-4798-8164-f29bbf88da7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368145537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2368145537 |
| Directory | /workspace/199.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.448258664 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 12667866645 ps |
| CPU time | 20.86 seconds |
| Started | May 30 12:36:54 PM PDT 24 |
| Finished | May 30 12:37:16 PM PDT 24 |
| Peak memory | 182840 kb |
| Host | smart-f0375532-4ebb-4cb0-839d-83d7d162c7d5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448258664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rv_timer_cfg_update_on_fly.448258664 |
| Directory | /workspace/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/2.rv_timer_disabled.455465650 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 79951321459 ps |
| CPU time | 90.98 seconds |
| Started | May 30 12:36:44 PM PDT 24 |
| Finished | May 30 12:38:16 PM PDT 24 |
| Peak memory | 182888 kb |
| Host | smart-fd60c7ea-735a-4c5b-a95a-3cb0a35bfbb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455465650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.455465650 |
| Directory | /workspace/2.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random.1305032979 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 202996424545 ps |
| CPU time | 177.49 seconds |
| Started | May 30 12:36:54 PM PDT 24 |
| Finished | May 30 12:39:52 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-7fb9f876-f2b0-4693-be2b-c5b4ab74f387 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305032979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1305032979 |
| Directory | /workspace/2.rv_timer_random/latest |
| Test location | /workspace/coverage/default/2.rv_timer_random_reset.38771798 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 99483217695 ps |
| CPU time | 50.38 seconds |
| Started | May 30 12:36:51 PM PDT 24 |
| Finished | May 30 12:37:42 PM PDT 24 |
| Peak memory | 191104 kb |
| Host | smart-dcc21b39-df4c-48f2-ab6e-994a5875677c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38771798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.38771798 |
| Directory | /workspace/2.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/2.rv_timer_sec_cm.461319417 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 70358846 ps |
| CPU time | 0.78 seconds |
| Started | May 30 12:36:53 PM PDT 24 |
| Finished | May 30 12:36:56 PM PDT 24 |
| Peak memory | 213388 kb |
| Host | smart-fb64f2c5-f3ae-42e3-aad8-54b58f5ce769 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461319417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.461319417 |
| Directory | /workspace/2.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2905415709 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2941835433209 ps |
| CPU time | 854.34 seconds |
| Started | May 30 12:37:08 PM PDT 24 |
| Finished | May 30 12:51:24 PM PDT 24 |
| Peak memory | 182992 kb |
| Host | smart-dfbb4473-806a-49c4-96d1-c2094a7d7fc1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905415709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2905415709 |
| Directory | /workspace/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/20.rv_timer_disabled.1169637819 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 229477398450 ps |
| CPU time | 182.3 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:40:21 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-6995ac3d-b227-4edc-a985-2f19384ae2be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1169637819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1169637819 |
| Directory | /workspace/20.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random.1688632478 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 157819296139 ps |
| CPU time | 178.48 seconds |
| Started | May 30 12:36:57 PM PDT 24 |
| Finished | May 30 12:39:57 PM PDT 24 |
| Peak memory | 194324 kb |
| Host | smart-a589fcd0-832e-4210-8e97-0c0f7c037464 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688632478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1688632478 |
| Directory | /workspace/20.rv_timer_random/latest |
| Test location | /workspace/coverage/default/20.rv_timer_random_reset.3263065 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 91282607605 ps |
| CPU time | 564.79 seconds |
| Started | May 30 12:37:04 PM PDT 24 |
| Finished | May 30 12:46:31 PM PDT 24 |
| Peak memory | 191012 kb |
| Host | smart-74aee416-f9f8-4004-888c-e6f086788dda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3263065 |
| Directory | /workspace/20.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_disabled.1162697068 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 357188114457 ps |
| CPU time | 147.1 seconds |
| Started | May 30 12:37:15 PM PDT 24 |
| Finished | May 30 12:39:43 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-b0710639-c48e-4166-8e09-b7adf9358f08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162697068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1162697068 |
| Directory | /workspace/21.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random.205153512 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 73917068040 ps |
| CPU time | 122.46 seconds |
| Started | May 30 12:37:07 PM PDT 24 |
| Finished | May 30 12:39:11 PM PDT 24 |
| Peak memory | 191024 kb |
| Host | smart-c3eba1d5-73be-4961-b0f1-d020fe4d33e7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205153512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.205153512 |
| Directory | /workspace/21.rv_timer_random/latest |
| Test location | /workspace/coverage/default/21.rv_timer_random_reset.308318829 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 6349443981 ps |
| CPU time | 12.38 seconds |
| Started | May 30 12:37:03 PM PDT 24 |
| Finished | May 30 12:37:18 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-59e0278a-f062-4339-ae55-a81ce7a4fcb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308318829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.308318829 |
| Directory | /workspace/21.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/21.rv_timer_stress_all.2796456079 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 5221024478794 ps |
| CPU time | 2968.22 seconds |
| Started | May 30 12:37:08 PM PDT 24 |
| Finished | May 30 01:26:38 PM PDT 24 |
| Peak memory | 191044 kb |
| Host | smart-7ea9c4ce-5ca0-4bb9-914a-d16d3f9db009 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796456079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all .2796456079 |
| Directory | /workspace/21.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2919773224 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 64558334698 ps |
| CPU time | 63.07 seconds |
| Started | May 30 12:37:12 PM PDT 24 |
| Finished | May 30 12:38:16 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-09eceaa2-e887-421c-991b-a4c591fbc3db |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919773224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.2919773224 |
| Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/22.rv_timer_random_reset.3300852537 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 52174751091 ps |
| CPU time | 85.42 seconds |
| Started | May 30 12:37:06 PM PDT 24 |
| Finished | May 30 12:38:33 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-1f0e3941-608e-4fa9-a4bb-b24c44ad401c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300852537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3300852537 |
| Directory | /workspace/22.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/22.rv_timer_stress_all.2610679552 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1911601210798 ps |
| CPU time | 1437.26 seconds |
| Started | May 30 12:37:13 PM PDT 24 |
| Finished | May 30 01:01:11 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-dd9678b9-f2d8-4c8e-89bf-ca7ab4802118 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610679552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all .2610679552 |
| Directory | /workspace/22.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3979987623 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 269627476967 ps |
| CPU time | 183.99 seconds |
| Started | May 30 12:37:09 PM PDT 24 |
| Finished | May 30 12:40:14 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-9564fdde-1dc5-4a52-8ad0-d202105874ca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979987623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.3979987623 |
| Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/23.rv_timer_disabled.42085904 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 273593404199 ps |
| CPU time | 184.35 seconds |
| Started | May 30 12:36:57 PM PDT 24 |
| Finished | May 30 12:40:02 PM PDT 24 |
| Peak memory | 182840 kb |
| Host | smart-af1d9fe8-4ca1-4bec-b1e9-ccee1ec56da8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=42085904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.42085904 |
| Directory | /workspace/23.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random.76221816 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 71503401994 ps |
| CPU time | 65.48 seconds |
| Started | May 30 12:37:03 PM PDT 24 |
| Finished | May 30 12:38:10 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-69f67780-e0ed-4692-9841-640a419411db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76221816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.76221816 |
| Directory | /workspace/23.rv_timer_random/latest |
| Test location | /workspace/coverage/default/23.rv_timer_random_reset.2243348513 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 271688865 ps |
| CPU time | 2.23 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:37:22 PM PDT 24 |
| Peak memory | 182812 kb |
| Host | smart-da028596-50fb-4fa8-92ae-ce434b8a173c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2243348513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2243348513 |
| Directory | /workspace/23.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3620706200 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 508779879112 ps |
| CPU time | 781.92 seconds |
| Started | May 30 12:37:18 PM PDT 24 |
| Finished | May 30 12:50:22 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-09194531-7f65-47e9-879b-9488438874da |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620706200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.3620706200 |
| Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/24.rv_timer_disabled.2189885082 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 64579938248 ps |
| CPU time | 52.31 seconds |
| Started | May 30 12:37:06 PM PDT 24 |
| Finished | May 30 12:38:00 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-a15f7e9c-2bc3-466c-9b72-37c4988f8a28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189885082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2189885082 |
| Directory | /workspace/24.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/24.rv_timer_stress_all.497747807 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 328322794616 ps |
| CPU time | 533.72 seconds |
| Started | May 30 12:37:11 PM PDT 24 |
| Finished | May 30 12:46:10 PM PDT 24 |
| Peak memory | 191056 kb |
| Host | smart-bb47a833-cd2b-448d-9576-73605d4917b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497747807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all. 497747807 |
| Directory | /workspace/24.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2691493893 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 388896580006 ps |
| CPU time | 392.01 seconds |
| Started | May 30 12:37:15 PM PDT 24 |
| Finished | May 30 12:43:47 PM PDT 24 |
| Peak memory | 182864 kb |
| Host | smart-c1ae2f2f-1185-4af4-936a-2266968a2d9f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691493893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2691493893 |
| Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/25.rv_timer_disabled.1420981684 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 58047228686 ps |
| CPU time | 77.12 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:38:36 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-96f765b5-c0f6-4625-90a5-32bb82fadd89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420981684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1420981684 |
| Directory | /workspace/25.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/25.rv_timer_random.2699882514 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 273086410558 ps |
| CPU time | 378.36 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:43:39 PM PDT 24 |
| Peak memory | 191040 kb |
| Host | smart-59d52a71-1681-4aa2-8a9e-a74828513fba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699882514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2699882514 |
| Directory | /workspace/25.rv_timer_random/latest |
| Test location | /workspace/coverage/default/25.rv_timer_stress_all.2444190153 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 267737606014 ps |
| CPU time | 972.84 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:53:33 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-f97114c6-602d-4b02-9ac7-12e70ee726d6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444190153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all .2444190153 |
| Directory | /workspace/25.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3673014136 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 17051161374 ps |
| CPU time | 9.41 seconds |
| Started | May 30 12:37:12 PM PDT 24 |
| Finished | May 30 12:37:23 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-dbff26b3-4a28-4e42-b768-d8046a5b06a7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673014136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3673014136 |
| Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/26.rv_timer_disabled.1311957255 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 866100211861 ps |
| CPU time | 175 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:40:16 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-9f473550-311f-4c7b-9846-59285430bf68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1311957255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1311957255 |
| Directory | /workspace/26.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/26.rv_timer_random_reset.699998273 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 79503853938 ps |
| CPU time | 1221.8 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:57:44 PM PDT 24 |
| Peak memory | 191080 kb |
| Host | smart-f8f7ac07-391f-4b72-960c-d242b8ebd6b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699998273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.699998273 |
| Directory | /workspace/26.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/26.rv_timer_stress_all.222202535 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 641714572507 ps |
| CPU time | 2694.37 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 01:22:22 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-b6ba11cd-aaa5-41e7-b839-c57f965633a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222202535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all. 222202535 |
| Directory | /workspace/26.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/27.rv_timer_disabled.815729488 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 470604606062 ps |
| CPU time | 191.18 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:40:32 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-2e38f0db-de37-4098-ab20-90655a6067a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815729488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.815729488 |
| Directory | /workspace/27.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/27.rv_timer_random_reset.4066383873 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 140188392617 ps |
| CPU time | 69.2 seconds |
| Started | May 30 12:37:16 PM PDT 24 |
| Finished | May 30 12:38:26 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-60f34660-194c-493f-8b78-f353cfe95d3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066383873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4066383873 |
| Directory | /workspace/27.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.4144577371 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1787801911307 ps |
| CPU time | 705.14 seconds |
| Started | May 30 12:37:11 PM PDT 24 |
| Finished | May 30 12:48:57 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-2562d98d-963e-47ca-9661-a5a7103beb25 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144577371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.4144577371 |
| Directory | /workspace/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/28.rv_timer_disabled.575667259 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 84774000077 ps |
| CPU time | 144.16 seconds |
| Started | May 30 12:37:12 PM PDT 24 |
| Finished | May 30 12:39:37 PM PDT 24 |
| Peak memory | 182912 kb |
| Host | smart-ffb5086a-5cf2-431b-b434-9336ea3fd0af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=575667259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.575667259 |
| Directory | /workspace/28.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random.2164789364 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 41938703582 ps |
| CPU time | 60.8 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:38:19 PM PDT 24 |
| Peak memory | 182808 kb |
| Host | smart-bf1572cb-c94c-43ac-8ddc-df796b4b25da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164789364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2164789364 |
| Directory | /workspace/28.rv_timer_random/latest |
| Test location | /workspace/coverage/default/28.rv_timer_random_reset.4086752224 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 300728161179 ps |
| CPU time | 186.66 seconds |
| Started | May 30 12:37:22 PM PDT 24 |
| Finished | May 30 12:40:29 PM PDT 24 |
| Peak memory | 182852 kb |
| Host | smart-fea9fab6-1d94-4b9c-b366-1334795b5ff3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086752224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4086752224 |
| Directory | /workspace/28.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1436369063 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 173099998537 ps |
| CPU time | 240.57 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:41:21 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-543c0c16-b602-41fe-88c2-7e97f2d7dfee |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436369063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.1436369063 |
| Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/29.rv_timer_disabled.692019171 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 249196628412 ps |
| CPU time | 209.07 seconds |
| Started | May 30 12:37:35 PM PDT 24 |
| Finished | May 30 12:41:06 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-c9831482-4744-4c06-9d21-4c2a9218266c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692019171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.692019171 |
| Directory | /workspace/29.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random.276359079 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4605145662 ps |
| CPU time | 152.33 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:39:50 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-c03dbcd5-8b65-45b6-be97-74f335ffaf98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276359079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.276359079 |
| Directory | /workspace/29.rv_timer_random/latest |
| Test location | /workspace/coverage/default/29.rv_timer_random_reset.3766092047 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 172285410987 ps |
| CPU time | 105.95 seconds |
| Started | May 30 12:37:15 PM PDT 24 |
| Finished | May 30 12:39:01 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-f342fc7c-1b24-4944-811f-45ed294530b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766092047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3766092047 |
| Directory | /workspace/29.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3748287769 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1015258085708 ps |
| CPU time | 562.69 seconds |
| Started | May 30 12:37:03 PM PDT 24 |
| Finished | May 30 12:46:28 PM PDT 24 |
| Peak memory | 182852 kb |
| Host | smart-e119974e-bc0f-4ff4-ad49-c47a20bc6dbf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748287769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.3748287769 |
| Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/3.rv_timer_disabled.2042538155 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 374529744294 ps |
| CPU time | 116.39 seconds |
| Started | May 30 12:36:53 PM PDT 24 |
| Finished | May 30 12:38:51 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-b185444e-1035-48a9-941e-66b2372bf1ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042538155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2042538155 |
| Directory | /workspace/3.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random.3758513410 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 106801535529 ps |
| CPU time | 1150.41 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:55:56 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-31e41988-59e1-4b95-a127-faaf8eea4e4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758513410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3758513410 |
| Directory | /workspace/3.rv_timer_random/latest |
| Test location | /workspace/coverage/default/3.rv_timer_random_reset.2711028145 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 54303770908 ps |
| CPU time | 25.96 seconds |
| Started | May 30 12:36:54 PM PDT 24 |
| Finished | May 30 12:37:22 PM PDT 24 |
| Peak memory | 194460 kb |
| Host | smart-3083d613-0952-4212-93ba-cbab7c9292b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711028145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2711028145 |
| Directory | /workspace/3.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/3.rv_timer_sec_cm.3180789410 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 264261291 ps |
| CPU time | 0.87 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 12:36:48 PM PDT 24 |
| Peak memory | 213872 kb |
| Host | smart-2c03817e-cde8-4f69-ad86-f35ff2985dd8 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180789410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3180789410 |
| Directory | /workspace/3.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4112630519 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 157942268885 ps |
| CPU time | 261.5 seconds |
| Started | May 30 12:37:18 PM PDT 24 |
| Finished | May 30 12:41:41 PM PDT 24 |
| Peak memory | 182892 kb |
| Host | smart-9d69c46a-83a6-4c7d-b6d7-e4e187a76c7f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112630519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.4112630519 |
| Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/30.rv_timer_disabled.2894378594 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 15061628675 ps |
| CPU time | 22.7 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:37:43 PM PDT 24 |
| Peak memory | 182952 kb |
| Host | smart-872b0989-c90c-4168-83e1-ae018de4267b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894378594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2894378594 |
| Directory | /workspace/30.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/30.rv_timer_random_reset.2474599943 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 112619357060 ps |
| CPU time | 166.52 seconds |
| Started | May 30 12:37:31 PM PDT 24 |
| Finished | May 30 12:40:19 PM PDT 24 |
| Peak memory | 182836 kb |
| Host | smart-79b2fa86-8e14-4263-b6d4-8ce8097c6a65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2474599943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2474599943 |
| Directory | /workspace/30.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all.1171490078 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 229822715132 ps |
| CPU time | 302.56 seconds |
| Started | May 30 12:37:13 PM PDT 24 |
| Finished | May 30 12:42:16 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-80766a34-a31a-451d-bb97-143db42f9bed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171490078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all .1171490078 |
| Directory | /workspace/30.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2133394012 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 21433897475 ps |
| CPU time | 161.99 seconds |
| Started | May 30 12:37:14 PM PDT 24 |
| Finished | May 30 12:39:56 PM PDT 24 |
| Peak memory | 197152 kb |
| Host | smart-3bec4e4d-5127-44b4-98e7-ebdc4fef4836 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133394012 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2133394012 |
| Directory | /workspace/30.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.16320255 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 289524840489 ps |
| CPU time | 262.22 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:41:43 PM PDT 24 |
| Peak memory | 182840 kb |
| Host | smart-5fd6198e-7a76-4bfc-94af-90ac8eb88c6f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31 .rv_timer_cfg_update_on_fly.16320255 |
| Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/31.rv_timer_disabled.2048118748 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 218501347229 ps |
| CPU time | 63.94 seconds |
| Started | May 30 12:37:10 PM PDT 24 |
| Finished | May 30 12:38:14 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-98155278-4018-41d6-8793-41dfcf9ce0be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048118748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2048118748 |
| Directory | /workspace/31.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random.3633751994 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 153744863525 ps |
| CPU time | 57.86 seconds |
| Started | May 30 12:37:18 PM PDT 24 |
| Finished | May 30 12:38:17 PM PDT 24 |
| Peak memory | 194108 kb |
| Host | smart-dd746d0c-a8eb-497d-b4e5-291f93a5b93e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633751994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3633751994 |
| Directory | /workspace/31.rv_timer_random/latest |
| Test location | /workspace/coverage/default/31.rv_timer_random_reset.1396726948 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 238831889764 ps |
| CPU time | 89.44 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:38:52 PM PDT 24 |
| Peak memory | 194136 kb |
| Host | smart-262b690b-132a-48ae-98d0-4491f55f78ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396726948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1396726948 |
| Directory | /workspace/31.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/31.rv_timer_stress_all.3391641344 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2201463685063 ps |
| CPU time | 923.5 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:52:50 PM PDT 24 |
| Peak memory | 195732 kb |
| Host | smart-04958424-083d-4f20-b529-3b0aa40f2dbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391641344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all .3391641344 |
| Directory | /workspace/31.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.4097625412 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 333492106469 ps |
| CPU time | 644.88 seconds |
| Started | May 30 12:37:16 PM PDT 24 |
| Finished | May 30 12:48:01 PM PDT 24 |
| Peak memory | 182956 kb |
| Host | smart-840eae01-6d8f-4418-a8e2-b392c120b69a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097625412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.4097625412 |
| Directory | /workspace/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/32.rv_timer_disabled.2144864829 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 104485801055 ps |
| CPU time | 113.64 seconds |
| Started | May 30 12:37:10 PM PDT 24 |
| Finished | May 30 12:39:04 PM PDT 24 |
| Peak memory | 182860 kb |
| Host | smart-ea297251-7273-478f-9f6b-8422aa4afe7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144864829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2144864829 |
| Directory | /workspace/32.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/32.rv_timer_random_reset.2002839925 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 22550413972 ps |
| CPU time | 45.92 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:38:14 PM PDT 24 |
| Peak memory | 194516 kb |
| Host | smart-15a27bd5-f55a-4a33-af80-0ae0a84b8302 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2002839925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2002839925 |
| Directory | /workspace/32.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.587810364 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 144530809922 ps |
| CPU time | 217.47 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:41:07 PM PDT 24 |
| Peak memory | 182916 kb |
| Host | smart-e88af7d7-9227-4afd-b7d4-6787d27da5a8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587810364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.rv_timer_cfg_update_on_fly.587810364 |
| Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/33.rv_timer_disabled.1872944425 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 472866592185 ps |
| CPU time | 212.79 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:41:00 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-2519ad1b-ae92-466e-a2ca-57e17c3a9469 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1872944425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1872944425 |
| Directory | /workspace/33.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random.1983061130 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 43069292669 ps |
| CPU time | 23.74 seconds |
| Started | May 30 12:37:13 PM PDT 24 |
| Finished | May 30 12:37:37 PM PDT 24 |
| Peak memory | 182952 kb |
| Host | smart-3f78410b-ad4a-4c97-9894-702c6ae175dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983061130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1983061130 |
| Directory | /workspace/33.rv_timer_random/latest |
| Test location | /workspace/coverage/default/33.rv_timer_random_reset.1085884119 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 63056862609 ps |
| CPU time | 59.92 seconds |
| Started | May 30 12:37:28 PM PDT 24 |
| Finished | May 30 12:38:29 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-564ef947-92c9-4096-9634-a953b7b93576 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085884119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1085884119 |
| Directory | /workspace/33.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all.723402261 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 241602855418 ps |
| CPU time | 332.86 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:42:51 PM PDT 24 |
| Peak memory | 191112 kb |
| Host | smart-0eaf6359-6ecf-474e-881c-a5055898e0d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723402261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all. 723402261 |
| Directory | /workspace/33.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1434472439 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 49809391056 ps |
| CPU time | 178.83 seconds |
| Started | May 30 12:37:28 PM PDT 24 |
| Finished | May 30 12:40:28 PM PDT 24 |
| Peak memory | 197560 kb |
| Host | smart-cc14166c-fd9b-4756-9615-f8cbab1896eb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434472439 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1434472439 |
| Directory | /workspace/33.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2512834236 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 455180086120 ps |
| CPU time | 802.77 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:50:50 PM PDT 24 |
| Peak memory | 182892 kb |
| Host | smart-bf6fcfa6-f3da-4c90-8879-ef420ae6a7e6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512834236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.2512834236 |
| Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/34.rv_timer_disabled.128944777 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 172899706294 ps |
| CPU time | 251.53 seconds |
| Started | May 30 12:37:17 PM PDT 24 |
| Finished | May 30 12:41:30 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-1c889a1f-e820-4efd-98b2-4efbc585d133 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=128944777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.128944777 |
| Directory | /workspace/34.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/34.rv_timer_random_reset.875663040 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 118789943549 ps |
| CPU time | 64.52 seconds |
| Started | May 30 12:37:22 PM PDT 24 |
| Finished | May 30 12:38:27 PM PDT 24 |
| Peak memory | 191120 kb |
| Host | smart-0f578b17-6512-47f9-87bd-71ec4bb69a2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875663040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.875663040 |
| Directory | /workspace/34.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/34.rv_timer_stress_all.387208759 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 261584960842 ps |
| CPU time | 213.58 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:41:08 PM PDT 24 |
| Peak memory | 182860 kb |
| Host | smart-104f21a1-4cbf-4d6b-a6a5-8f20ed2d50db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387208759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all. 387208759 |
| Directory | /workspace/34.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2663565588 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 114965643845 ps |
| CPU time | 67.82 seconds |
| Started | May 30 12:37:22 PM PDT 24 |
| Finished | May 30 12:38:31 PM PDT 24 |
| Peak memory | 182868 kb |
| Host | smart-dc492df5-1ad8-4f0c-816d-52fea488d7f6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663565588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.2663565588 |
| Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/35.rv_timer_disabled.3598515391 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 295062330389 ps |
| CPU time | 220.17 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:41:03 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-d61b4565-3345-431d-b2aa-79d918692900 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598515391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3598515391 |
| Directory | /workspace/35.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/35.rv_timer_random_reset.465716598 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 138330967303 ps |
| CPU time | 406.38 seconds |
| Started | May 30 12:37:09 PM PDT 24 |
| Finished | May 30 12:43:56 PM PDT 24 |
| Peak memory | 192188 kb |
| Host | smart-9efb868d-01bd-4ae4-b57a-2280a4b3870d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465716598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.465716598 |
| Directory | /workspace/35.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/35.rv_timer_stress_all.4099322326 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 2526805170366 ps |
| CPU time | 1659.81 seconds |
| Started | May 30 12:37:22 PM PDT 24 |
| Finished | May 30 01:05:03 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-e5d18ce8-afb1-4436-8d98-983741c87cbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099322326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all .4099322326 |
| Directory | /workspace/35.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_disabled.3211998503 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 229237093585 ps |
| CPU time | 184.72 seconds |
| Started | May 30 12:37:16 PM PDT 24 |
| Finished | May 30 12:40:21 PM PDT 24 |
| Peak memory | 182956 kb |
| Host | smart-f6e1fade-577f-4d74-b733-29414107fb43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211998503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3211998503 |
| Directory | /workspace/36.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random.140721626 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 72995310990 ps |
| CPU time | 199.57 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:40:46 PM PDT 24 |
| Peak memory | 191140 kb |
| Host | smart-7a6f084e-ca3c-4add-a046-facc68fc3494 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140721626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.140721626 |
| Directory | /workspace/36.rv_timer_random/latest |
| Test location | /workspace/coverage/default/36.rv_timer_random_reset.2274944219 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 95331973 ps |
| CPU time | 0.66 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:37:21 PM PDT 24 |
| Peak memory | 182748 kb |
| Host | smart-11fd20d3-9f87-43ad-8da4-ff1a6801afaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2274944219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2274944219 |
| Directory | /workspace/36.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all.3125164824 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 360279101593 ps |
| CPU time | 674.1 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:48:42 PM PDT 24 |
| Peak memory | 191176 kb |
| Host | smart-6033d545-4c4e-4bc4-9b66-11daf011f882 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125164824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .3125164824 |
| Directory | /workspace/36.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.257136238 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 42830680330 ps |
| CPU time | 155.14 seconds |
| Started | May 30 12:37:38 PM PDT 24 |
| Finished | May 30 12:40:14 PM PDT 24 |
| Peak memory | 197580 kb |
| Host | smart-ee335434-4642-44cd-82cf-d91818fa94f7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257136238 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.257136238 |
| Directory | /workspace/36.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1255764633 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 396816992664 ps |
| CPU time | 207.33 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:40:54 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-fa893266-bfec-4ba8-8a23-94e5a293d9b5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255764633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.1255764633 |
| Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/37.rv_timer_disabled.1253958893 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 111669580849 ps |
| CPU time | 178.47 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:40:23 PM PDT 24 |
| Peak memory | 182956 kb |
| Host | smart-70d0a189-6067-4ab5-a2ad-313710f64bd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1253958893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1253958893 |
| Directory | /workspace/37.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/37.rv_timer_random.3667055787 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 28468151214 ps |
| CPU time | 608.17 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:47:35 PM PDT 24 |
| Peak memory | 191052 kb |
| Host | smart-fe061aae-0166-4f67-b86b-242d351c3265 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667055787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3667055787 |
| Directory | /workspace/37.rv_timer_random/latest |
| Test location | /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.3353336900 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 22109516686 ps |
| CPU time | 235.77 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:41:16 PM PDT 24 |
| Peak memory | 205764 kb |
| Host | smart-5ef6b351-90aa-43f6-91d1-fb607b65ce63 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353336900 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.3353336900 |
| Directory | /workspace/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.182808942 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 16553599225 ps |
| CPU time | 30.77 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:37:58 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-4f53b235-39f3-4cd3-bb47-fc829d7f70eb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182808942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.rv_timer_cfg_update_on_fly.182808942 |
| Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/38.rv_timer_disabled.3672338038 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 61662629991 ps |
| CPU time | 99.84 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:39:10 PM PDT 24 |
| Peak memory | 182892 kb |
| Host | smart-c4b546fb-346b-4d67-aa48-32a82fdfe538 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672338038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3672338038 |
| Directory | /workspace/38.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random.3632160452 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 524126172291 ps |
| CPU time | 412.29 seconds |
| Started | May 30 12:37:23 PM PDT 24 |
| Finished | May 30 12:44:16 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-06d5fb59-a5c1-44f9-880e-d07eb7687ec4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632160452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3632160452 |
| Directory | /workspace/38.rv_timer_random/latest |
| Test location | /workspace/coverage/default/38.rv_timer_random_reset.1647633019 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 263379346486 ps |
| CPU time | 299.16 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:42:21 PM PDT 24 |
| Peak memory | 191076 kb |
| Host | smart-833c8edd-ab02-493c-964d-4daaecc74fa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647633019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1647633019 |
| Directory | /workspace/38.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/38.rv_timer_stress_all.3562113967 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1091634806483 ps |
| CPU time | 672.67 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:48:46 PM PDT 24 |
| Peak memory | 191156 kb |
| Host | smart-acd60bb7-0586-4bec-b41d-7edd7be63647 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562113967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .3562113967 |
| Directory | /workspace/38.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2604674400 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9228372794 ps |
| CPU time | 8.25 seconds |
| Started | May 30 12:37:38 PM PDT 24 |
| Finished | May 30 12:37:48 PM PDT 24 |
| Peak memory | 183000 kb |
| Host | smart-d1c240b3-8c81-4036-af5e-04634d1c73c3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604674400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.2604674400 |
| Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/39.rv_timer_disabled.3457681006 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 15326063385 ps |
| CPU time | 23.52 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:37:48 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-36ec931f-232c-4a44-8e42-200bde41c794 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457681006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3457681006 |
| Directory | /workspace/39.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/39.rv_timer_random_reset.2440615606 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 173175348647 ps |
| CPU time | 185.8 seconds |
| Started | May 30 12:37:22 PM PDT 24 |
| Finished | May 30 12:40:29 PM PDT 24 |
| Peak memory | 194716 kb |
| Host | smart-5bdf12f5-a768-4554-829c-32d0bd5394ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440615606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2440615606 |
| Directory | /workspace/39.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3377981270 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 193358930222 ps |
| CPU time | 321.25 seconds |
| Started | May 30 12:36:44 PM PDT 24 |
| Finished | May 30 12:42:06 PM PDT 24 |
| Peak memory | 182812 kb |
| Host | smart-431427aa-5fe4-4c5a-9b65-194eb026b8c2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377981270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.3377981270 |
| Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/4.rv_timer_disabled.1672671553 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 140212580449 ps |
| CPU time | 221.94 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:40:30 PM PDT 24 |
| Peak memory | 182876 kb |
| Host | smart-91538fd3-f1a5-4051-a61f-e0d0dbe1d314 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672671553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1672671553 |
| Directory | /workspace/4.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random.642817145 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 422263703343 ps |
| CPU time | 662.03 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:47:50 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-892c0dd0-6a2e-4ff7-9c54-49e64a86b622 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642817145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.642817145 |
| Directory | /workspace/4.rv_timer_random/latest |
| Test location | /workspace/coverage/default/4.rv_timer_random_reset.2693266446 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 109131102089 ps |
| CPU time | 52.63 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 12:37:40 PM PDT 24 |
| Peak memory | 182872 kb |
| Host | smart-c0dca4ce-db9b-4f3b-b1fb-aba6294735d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2693266446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2693266446 |
| Directory | /workspace/4.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/4.rv_timer_sec_cm.625373735 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 282362895 ps |
| CPU time | 0.77 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 12:36:48 PM PDT 24 |
| Peak memory | 213272 kb |
| Host | smart-a20947bd-9d26-4055-9ede-d98ea6e370dd |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625373735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.625373735 |
| Directory | /workspace/4.rv_timer_sec_cm/latest |
| Test location | /workspace/coverage/default/4.rv_timer_stress_all.1084376527 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 400198343471 ps |
| CPU time | 161.73 seconds |
| Started | May 30 12:36:55 PM PDT 24 |
| Finished | May 30 12:39:38 PM PDT 24 |
| Peak memory | 182816 kb |
| Host | smart-55c6fe83-8da3-43b4-bd32-bb87f7e715f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084376527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all. 1084376527 |
| Directory | /workspace/4.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1136437876 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 378268712163 ps |
| CPU time | 185.52 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:40:34 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-c8a46d30-0d5a-4166-9de7-bba5110bc366 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136437876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.1136437876 |
| Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/40.rv_timer_disabled.87931859 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 129292684928 ps |
| CPU time | 56.93 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:38:22 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-908d2101-37b1-4f6f-beab-936db5fd9825 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=87931859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.87931859 |
| Directory | /workspace/40.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random.1062358848 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 436888829212 ps |
| CPU time | 287.36 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:42:16 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-f54b7197-069e-43c7-8bc3-55846cb7866c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062358848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1062358848 |
| Directory | /workspace/40.rv_timer_random/latest |
| Test location | /workspace/coverage/default/40.rv_timer_random_reset.4142302364 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 45918823469 ps |
| CPU time | 382.66 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:43:57 PM PDT 24 |
| Peak memory | 182940 kb |
| Host | smart-11dcbca4-287e-4a98-8dee-cd10f35adec4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142302364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4142302364 |
| Directory | /workspace/40.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/40.rv_timer_stress_all.464144142 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 240272052901 ps |
| CPU time | 877.45 seconds |
| Started | May 30 12:37:20 PM PDT 24 |
| Finished | May 30 12:51:59 PM PDT 24 |
| Peak memory | 193748 kb |
| Host | smart-8f7e11a1-5196-4dce-aef0-65b19ac4e408 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464144142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all. 464144142 |
| Directory | /workspace/40.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.345668351 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 669748411969 ps |
| CPU time | 345.48 seconds |
| Started | May 30 12:37:35 PM PDT 24 |
| Finished | May 30 12:43:21 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-cf3d06d7-f495-4ab6-84de-a183d9cd0643 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345668351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.rv_timer_cfg_update_on_fly.345668351 |
| Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/41.rv_timer_disabled.1271489625 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 88881470754 ps |
| CPU time | 138.11 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:39:45 PM PDT 24 |
| Peak memory | 182988 kb |
| Host | smart-ba5263bd-ec3a-49a0-a2df-8dd12e498744 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271489625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1271489625 |
| Directory | /workspace/41.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/41.rv_timer_random_reset.2468778436 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 1296935064 ps |
| CPU time | 1.06 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:37:26 PM PDT 24 |
| Peak memory | 192140 kb |
| Host | smart-cd3f50c8-d87b-43ed-bd5c-9ae9d2bbc5a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2468778436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2468778436 |
| Directory | /workspace/41.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.4203609132 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 90188202972 ps |
| CPU time | 182.44 seconds |
| Started | May 30 12:37:18 PM PDT 24 |
| Finished | May 30 12:40:21 PM PDT 24 |
| Peak memory | 197632 kb |
| Host | smart-318afbdd-4c62-41cb-b040-991ff7c4dc97 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203609132 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.4203609132 |
| Directory | /workspace/41.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2461013788 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 17774834693 ps |
| CPU time | 27.75 seconds |
| Started | May 30 12:37:16 PM PDT 24 |
| Finished | May 30 12:37:45 PM PDT 24 |
| Peak memory | 182812 kb |
| Host | smart-d0f19834-c0bf-427d-8a89-63f002659a82 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461013788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.2461013788 |
| Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/42.rv_timer_disabled.606926936 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 150809154866 ps |
| CPU time | 62.31 seconds |
| Started | May 30 12:37:20 PM PDT 24 |
| Finished | May 30 12:38:24 PM PDT 24 |
| Peak memory | 182972 kb |
| Host | smart-ad1af85c-7780-4dee-b398-f5bec992b972 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606926936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.606926936 |
| Directory | /workspace/42.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random.1249660417 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 724455873733 ps |
| CPU time | 2701.8 seconds |
| Started | May 30 12:37:28 PM PDT 24 |
| Finished | May 30 01:22:31 PM PDT 24 |
| Peak memory | 191168 kb |
| Host | smart-f56c469c-216d-45e9-968b-65d1a35495fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249660417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1249660417 |
| Directory | /workspace/42.rv_timer_random/latest |
| Test location | /workspace/coverage/default/42.rv_timer_random_reset.2072893589 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 85246973514 ps |
| CPU time | 86.16 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:38:58 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-b08cdd9b-5320-40ed-a226-f3075ec500bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2072893589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2072893589 |
| Directory | /workspace/42.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/42.rv_timer_stress_all.314472782 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 72804868247 ps |
| CPU time | 110.43 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:39:16 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-d033b280-d419-47ef-872f-fc19ceba0c86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314472782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all. 314472782 |
| Directory | /workspace/42.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.137297500 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 190643745351 ps |
| CPU time | 343.33 seconds |
| Started | May 30 12:37:18 PM PDT 24 |
| Finished | May 30 12:43:03 PM PDT 24 |
| Peak memory | 182952 kb |
| Host | smart-5b38890b-5703-41a0-b071-a15227952ec8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137297500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.rv_timer_cfg_update_on_fly.137297500 |
| Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/43.rv_timer_disabled.1156270552 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 445876984365 ps |
| CPU time | 178.29 seconds |
| Started | May 30 12:37:20 PM PDT 24 |
| Finished | May 30 12:40:19 PM PDT 24 |
| Peak memory | 182812 kb |
| Host | smart-f6c27b04-7839-4d2f-886b-727935bb4628 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156270552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1156270552 |
| Directory | /workspace/43.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random.2187524614 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3194996524395 ps |
| CPU time | 421.55 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:44:24 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-a4239896-19d9-4ead-84e4-aec3ab49bbfd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187524614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2187524614 |
| Directory | /workspace/43.rv_timer_random/latest |
| Test location | /workspace/coverage/default/43.rv_timer_random_reset.2121187132 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 173790574539 ps |
| CPU time | 171.82 seconds |
| Started | May 30 12:37:40 PM PDT 24 |
| Finished | May 30 12:40:33 PM PDT 24 |
| Peak memory | 191696 kb |
| Host | smart-75f8a99e-b9fc-4b5b-abc1-94567dae178a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2121187132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2121187132 |
| Directory | /workspace/43.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all.3007530685 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 19951429 ps |
| CPU time | 0.53 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:37:29 PM PDT 24 |
| Peak memory | 182668 kb |
| Host | smart-4f929c71-22a3-445b-9860-0be6f9c337fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007530685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all .3007530685 |
| Directory | /workspace/43.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1399175718 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 44872520498 ps |
| CPU time | 183.89 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:40:26 PM PDT 24 |
| Peak memory | 197604 kb |
| Host | smart-5878d66b-7ef8-4700-927f-d415ca50c4cd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399175718 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1399175718 |
| Directory | /workspace/43.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.944798147 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 17628530078 ps |
| CPU time | 7.71 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:37:33 PM PDT 24 |
| Peak memory | 182956 kb |
| Host | smart-a46aef1f-b01f-490d-bfdb-b3d2d8767917 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944798147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.rv_timer_cfg_update_on_fly.944798147 |
| Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/44.rv_timer_disabled.3583703281 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 113874297492 ps |
| CPU time | 81.73 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:38:50 PM PDT 24 |
| Peak memory | 182912 kb |
| Host | smart-849e7819-1013-4c43-b56c-6725381796bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583703281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3583703281 |
| Directory | /workspace/44.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random.2954042691 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 961892377177 ps |
| CPU time | 2162.21 seconds |
| Started | May 30 12:37:20 PM PDT 24 |
| Finished | May 30 01:13:24 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-e68c2394-5a8d-40da-9ddf-df96d5566182 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954042691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2954042691 |
| Directory | /workspace/44.rv_timer_random/latest |
| Test location | /workspace/coverage/default/44.rv_timer_random_reset.3022426868 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 38153704251 ps |
| CPU time | 46.04 seconds |
| Started | May 30 12:37:37 PM PDT 24 |
| Finished | May 30 12:38:24 PM PDT 24 |
| Peak memory | 182812 kb |
| Host | smart-72b35090-cda3-496b-ab24-f9d875a0bb2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022426868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3022426868 |
| Directory | /workspace/44.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/44.rv_timer_stress_all.2824109409 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 376216100727 ps |
| CPU time | 160.1 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:40:05 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-b6cf3539-1b62-4339-b6c8-b41517fc546d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824109409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all .2824109409 |
| Directory | /workspace/44.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1480072511 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 177166802286 ps |
| CPU time | 320.25 seconds |
| Started | May 30 12:37:20 PM PDT 24 |
| Finished | May 30 12:42:42 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-97c624c5-a071-4b6a-8bcf-c4a284d3847a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480072511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.1480072511 |
| Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/45.rv_timer_disabled.1967581624 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 505380194426 ps |
| CPU time | 182.9 seconds |
| Started | May 30 12:37:19 PM PDT 24 |
| Finished | May 30 12:40:23 PM PDT 24 |
| Peak memory | 182960 kb |
| Host | smart-cdcdffab-944a-4c2a-9999-14817da42867 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967581624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1967581624 |
| Directory | /workspace/45.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/45.rv_timer_random_reset.2523554077 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 129637415931 ps |
| CPU time | 63.28 seconds |
| Started | May 30 12:37:16 PM PDT 24 |
| Finished | May 30 12:38:20 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-cc09901a-fd8a-4514-a968-782ee46d88d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523554077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2523554077 |
| Directory | /workspace/45.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/45.rv_timer_stress_all.633723127 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 958203025918 ps |
| CPU time | 1019.74 seconds |
| Started | May 30 12:37:21 PM PDT 24 |
| Finished | May 30 12:54:22 PM PDT 24 |
| Peak memory | 194480 kb |
| Host | smart-45f1bd70-0586-4f5e-884d-dfa251cdab89 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633723127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all. 633723127 |
| Directory | /workspace/45.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.484646607 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 122101285956 ps |
| CPU time | 200.47 seconds |
| Started | May 30 12:37:18 PM PDT 24 |
| Finished | May 30 12:40:40 PM PDT 24 |
| Peak memory | 182944 kb |
| Host | smart-f0f13932-90e3-492d-8b13-b31f8958c392 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484646607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.rv_timer_cfg_update_on_fly.484646607 |
| Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/46.rv_timer_disabled.459777853 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 641618640866 ps |
| CPU time | 291.35 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:42:18 PM PDT 24 |
| Peak memory | 182892 kb |
| Host | smart-a8c8c9ea-4969-4549-803f-d52ea23ecf17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459777853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.459777853 |
| Directory | /workspace/46.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random.783405308 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 540993849975 ps |
| CPU time | 247.95 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:41:38 PM PDT 24 |
| Peak memory | 193628 kb |
| Host | smart-0733d3f2-718c-43b0-a6bc-87be93039100 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783405308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.783405308 |
| Directory | /workspace/46.rv_timer_random/latest |
| Test location | /workspace/coverage/default/46.rv_timer_random_reset.307124657 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 38320332630 ps |
| CPU time | 82.21 seconds |
| Started | May 30 12:37:18 PM PDT 24 |
| Finished | May 30 12:38:42 PM PDT 24 |
| Peak memory | 191032 kb |
| Host | smart-3491e4e2-ca3c-4618-903e-97c6e15990d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307124657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.307124657 |
| Directory | /workspace/46.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.310676140 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 377893589499 ps |
| CPU time | 359.46 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:43:26 PM PDT 24 |
| Peak memory | 182816 kb |
| Host | smart-caf9090e-2182-41f7-a4d3-43ed3971a52c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310676140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.rv_timer_cfg_update_on_fly.310676140 |
| Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/47.rv_timer_disabled.2451470299 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 168192358377 ps |
| CPU time | 114.82 seconds |
| Started | May 30 12:37:23 PM PDT 24 |
| Finished | May 30 12:39:19 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-c778dd46-081c-48d6-a80e-bf103c9b09d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451470299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2451470299 |
| Directory | /workspace/47.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random.2096192935 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 51925688711 ps |
| CPU time | 145.17 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:39:52 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-9f78a8dc-440d-4bd2-b647-330e72312f79 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096192935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2096192935 |
| Directory | /workspace/47.rv_timer_random/latest |
| Test location | /workspace/coverage/default/47.rv_timer_random_reset.4187058701 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 53639553 ps |
| CPU time | 0.65 seconds |
| Started | May 30 12:37:30 PM PDT 24 |
| Finished | May 30 12:37:32 PM PDT 24 |
| Peak memory | 182740 kb |
| Host | smart-c69e45cd-eddd-400f-97cc-30aaeec5910a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4187058701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.4187058701 |
| Directory | /workspace/47.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1479972072 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 266871747071 ps |
| CPU time | 467.22 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:45:15 PM PDT 24 |
| Peak memory | 182860 kb |
| Host | smart-1c965031-a8c3-4f9a-93e6-39b01c24a869 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479972072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1479972072 |
| Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/48.rv_timer_disabled.1550955189 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 125048741231 ps |
| CPU time | 165.05 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:40:15 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-a2c2d799-d4b0-41ec-a4d0-b3c1879d3ef5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550955189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1550955189 |
| Directory | /workspace/48.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random.539835562 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 127798545570 ps |
| CPU time | 227.01 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:41:15 PM PDT 24 |
| Peak memory | 191148 kb |
| Host | smart-b6c3580f-9be6-4133-b9ba-383db989cf09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539835562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.539835562 |
| Directory | /workspace/48.rv_timer_random/latest |
| Test location | /workspace/coverage/default/48.rv_timer_random_reset.1483338816 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 40060657125 ps |
| CPU time | 69.36 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:38:35 PM PDT 24 |
| Peak memory | 182876 kb |
| Host | smart-795a7884-c306-42fc-9b2e-6cf48d04ce1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483338816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1483338816 |
| Directory | /workspace/48.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3588524569 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 150976317465 ps |
| CPU time | 126.7 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:39:33 PM PDT 24 |
| Peak memory | 182828 kb |
| Host | smart-d0e5b580-edc3-41d3-93f1-5e94650daf40 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588524569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3588524569 |
| Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/49.rv_timer_disabled.1871944241 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 470035518516 ps |
| CPU time | 199.75 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:40:49 PM PDT 24 |
| Peak memory | 182820 kb |
| Host | smart-16ede3cf-0455-4dae-b0b9-84bb70470655 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871944241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1871944241 |
| Directory | /workspace/49.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random.568205338 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 66088504878 ps |
| CPU time | 106.97 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:39:21 PM PDT 24 |
| Peak memory | 191020 kb |
| Host | smart-8c4aada3-d8ee-4c5b-b6da-44528a34d14b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568205338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.568205338 |
| Directory | /workspace/49.rv_timer_random/latest |
| Test location | /workspace/coverage/default/49.rv_timer_random_reset.2722416226 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 64198130 ps |
| CPU time | 0.7 seconds |
| Started | May 30 12:37:42 PM PDT 24 |
| Finished | May 30 12:37:44 PM PDT 24 |
| Peak memory | 191356 kb |
| Host | smart-c225baf3-9aa7-4803-8cf8-6fe980eeff22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2722416226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2722416226 |
| Directory | /workspace/49.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1516845709 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 730108484192 ps |
| CPU time | 375.34 seconds |
| Started | May 30 12:36:43 PM PDT 24 |
| Finished | May 30 12:43:00 PM PDT 24 |
| Peak memory | 182844 kb |
| Host | smart-5fb4d8ec-c103-496f-b5a8-7c836f24ab43 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516845709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.1516845709 |
| Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/5.rv_timer_disabled.999789214 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 89562130761 ps |
| CPU time | 146.76 seconds |
| Started | May 30 12:36:55 PM PDT 24 |
| Finished | May 30 12:39:23 PM PDT 24 |
| Peak memory | 182984 kb |
| Host | smart-4e351cb9-2026-47b5-a2a6-c32e11e8a27a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=999789214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.999789214 |
| Directory | /workspace/5.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random.446515478 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 174428866618 ps |
| CPU time | 74.4 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:38:00 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-c905b0a0-7751-416b-91d9-69c23f917738 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446515478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.446515478 |
| Directory | /workspace/5.rv_timer_random/latest |
| Test location | /workspace/coverage/default/5.rv_timer_random_reset.889346612 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 51162773748 ps |
| CPU time | 72.26 seconds |
| Started | May 30 12:36:47 PM PDT 24 |
| Finished | May 30 12:38:00 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-b06e8813-9ef2-4ad7-8c89-09076eb46cab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889346612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.889346612 |
| Directory | /workspace/5.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/5.rv_timer_stress_all.1097115266 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1573738100151 ps |
| CPU time | 1309.26 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:58:35 PM PDT 24 |
| Peak memory | 191036 kb |
| Host | smart-34e35d1c-bd2f-4f73-9024-c54cf6b0f251 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097115266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 1097115266 |
| Directory | /workspace/5.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/50.rv_timer_random.971373579 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 103433863621 ps |
| CPU time | 41.91 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:38:12 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-2ed66c41-3867-4639-8b7e-4f9274f15699 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971373579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.971373579 |
| Directory | /workspace/50.rv_timer_random/latest |
| Test location | /workspace/coverage/default/53.rv_timer_random.3789000824 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 152531188889 ps |
| CPU time | 556.3 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:46:53 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-5d7a3bbc-9800-406c-b781-a507e65c82d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789000824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3789000824 |
| Directory | /workspace/53.rv_timer_random/latest |
| Test location | /workspace/coverage/default/54.rv_timer_random.4088539710 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 93639783418 ps |
| CPU time | 101.3 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:39:06 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-d64554a0-4ea7-4858-9a8f-160e29b8ab30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088539710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4088539710 |
| Directory | /workspace/54.rv_timer_random/latest |
| Test location | /workspace/coverage/default/55.rv_timer_random.1347119414 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 144381081724 ps |
| CPU time | 1397.21 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 01:00:52 PM PDT 24 |
| Peak memory | 191128 kb |
| Host | smart-784a3205-9bb3-4345-bd46-27e453a55347 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347119414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1347119414 |
| Directory | /workspace/55.rv_timer_random/latest |
| Test location | /workspace/coverage/default/56.rv_timer_random.3760679015 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 557053138210 ps |
| CPU time | 356.83 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:43:27 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-88e4a19c-2411-4de0-87b2-d71280bdfe6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760679015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3760679015 |
| Directory | /workspace/56.rv_timer_random/latest |
| Test location | /workspace/coverage/default/57.rv_timer_random.1590086581 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 123263612767 ps |
| CPU time | 50.13 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:38:17 PM PDT 24 |
| Peak memory | 182876 kb |
| Host | smart-ee860a40-510b-4dec-8035-34b0b37bfa24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590086581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1590086581 |
| Directory | /workspace/57.rv_timer_random/latest |
| Test location | /workspace/coverage/default/58.rv_timer_random.989480994 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 126443260770 ps |
| CPU time | 356.06 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:43:31 PM PDT 24 |
| Peak memory | 191012 kb |
| Host | smart-c621c073-7006-4089-8df6-efed4c2f2ed8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989480994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.989480994 |
| Directory | /workspace/58.rv_timer_random/latest |
| Test location | /workspace/coverage/default/59.rv_timer_random.2452843599 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 161182595371 ps |
| CPU time | 75.51 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:38:52 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-612e4f8e-9998-4db1-a76f-78c14b28d928 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452843599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2452843599 |
| Directory | /workspace/59.rv_timer_random/latest |
| Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3117268005 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 253596598998 ps |
| CPU time | 137.13 seconds |
| Started | May 30 12:36:54 PM PDT 24 |
| Finished | May 30 12:39:12 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-b56f988d-3949-4cb7-83a3-f19b65a1ed0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117268005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.3117268005 |
| Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/6.rv_timer_disabled.3923409629 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 70162332894 ps |
| CPU time | 107.04 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 12:38:35 PM PDT 24 |
| Peak memory | 182980 kb |
| Host | smart-7065b2ce-fca2-40fe-93fe-ac32f75a0fdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3923409629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3923409629 |
| Directory | /workspace/6.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/6.rv_timer_random_reset.593669177 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 60437153102 ps |
| CPU time | 293.98 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:41:40 PM PDT 24 |
| Peak memory | 195312 kb |
| Host | smart-3cb45638-b053-43e2-b3ab-7b0cd066efe1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593669177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.593669177 |
| Directory | /workspace/6.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/60.rv_timer_random.2957427142 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 272850008310 ps |
| CPU time | 1111.86 seconds |
| Started | May 30 12:37:31 PM PDT 24 |
| Finished | May 30 12:56:04 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-7443cd8b-ed87-4bb2-869a-268568f25062 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957427142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2957427142 |
| Directory | /workspace/60.rv_timer_random/latest |
| Test location | /workspace/coverage/default/62.rv_timer_random.1251259185 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 142518081064 ps |
| CPU time | 200.63 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:40:49 PM PDT 24 |
| Peak memory | 191144 kb |
| Host | smart-68e70205-ccbb-44fa-b15c-dd4e69e934f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251259185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1251259185 |
| Directory | /workspace/62.rv_timer_random/latest |
| Test location | /workspace/coverage/default/63.rv_timer_random.1968153546 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 553124387627 ps |
| CPU time | 744.75 seconds |
| Started | May 30 12:37:26 PM PDT 24 |
| Finished | May 30 12:49:57 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-57f49c89-a612-4abc-8d45-422b9420c1d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968153546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1968153546 |
| Directory | /workspace/63.rv_timer_random/latest |
| Test location | /workspace/coverage/default/64.rv_timer_random.2756888403 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 73649805775 ps |
| CPU time | 69.86 seconds |
| Started | May 30 12:37:40 PM PDT 24 |
| Finished | May 30 12:38:51 PM PDT 24 |
| Peak memory | 182852 kb |
| Host | smart-5f5e542e-ffb0-4bc7-a613-a1ea08e66e45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756888403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2756888403 |
| Directory | /workspace/64.rv_timer_random/latest |
| Test location | /workspace/coverage/default/65.rv_timer_random.3676509588 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 315298348749 ps |
| CPU time | 167.85 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:40:23 PM PDT 24 |
| Peak memory | 182860 kb |
| Host | smart-8bdab16e-1f7e-4a59-a868-54fe934266a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676509588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3676509588 |
| Directory | /workspace/65.rv_timer_random/latest |
| Test location | /workspace/coverage/default/66.rv_timer_random.2753827812 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 20607434149 ps |
| CPU time | 37.39 seconds |
| Started | May 30 12:37:35 PM PDT 24 |
| Finished | May 30 12:38:13 PM PDT 24 |
| Peak memory | 182916 kb |
| Host | smart-eb186b2b-c33c-492b-bf74-6df413685fd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753827812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2753827812 |
| Directory | /workspace/66.rv_timer_random/latest |
| Test location | /workspace/coverage/default/67.rv_timer_random.4144067516 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 34789689091 ps |
| CPU time | 45.59 seconds |
| Started | May 30 12:37:35 PM PDT 24 |
| Finished | May 30 12:38:22 PM PDT 24 |
| Peak memory | 182924 kb |
| Host | smart-745bf345-2738-4728-85be-bb08bfeb2b19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144067516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4144067516 |
| Directory | /workspace/67.rv_timer_random/latest |
| Test location | /workspace/coverage/default/68.rv_timer_random.1818453342 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 65284366884 ps |
| CPU time | 408.51 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:44:22 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-a6167f27-56db-4d78-b802-282cd903636f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818453342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1818453342 |
| Directory | /workspace/68.rv_timer_random/latest |
| Test location | /workspace/coverage/default/69.rv_timer_random.2366223501 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 88749190769 ps |
| CPU time | 405.56 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:44:23 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-805db5d7-bb21-42ef-b779-0112b64fc8c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366223501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2366223501 |
| Directory | /workspace/69.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.750417394 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 81031870159 ps |
| CPU time | 131.98 seconds |
| Started | May 30 12:36:56 PM PDT 24 |
| Finished | May 30 12:39:09 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-b8970951-7ae0-4469-bbc6-2584befe1b8c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750417394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .rv_timer_cfg_update_on_fly.750417394 |
| Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/7.rv_timer_disabled.2053815258 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 153931340490 ps |
| CPU time | 29.12 seconds |
| Started | May 30 12:36:54 PM PDT 24 |
| Finished | May 30 12:37:24 PM PDT 24 |
| Peak memory | 182860 kb |
| Host | smart-a20ecb92-b6fe-417c-a048-39cfac9d6d93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053815258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2053815258 |
| Directory | /workspace/7.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random.1681464252 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 180384212350 ps |
| CPU time | 114.98 seconds |
| Started | May 30 12:36:58 PM PDT 24 |
| Finished | May 30 12:38:54 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-4fb8823c-e7b5-40ec-ab8f-2b08652dd91a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681464252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1681464252 |
| Directory | /workspace/7.rv_timer_random/latest |
| Test location | /workspace/coverage/default/7.rv_timer_random_reset.4007142854 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 25228937910 ps |
| CPU time | 42.67 seconds |
| Started | May 30 12:37:11 PM PDT 24 |
| Finished | May 30 12:37:54 PM PDT 24 |
| Peak memory | 182872 kb |
| Host | smart-2da9d886-45ec-4945-b551-b8e93255665d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007142854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4007142854 |
| Directory | /workspace/7.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/70.rv_timer_random.3761031 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 416237739337 ps |
| CPU time | 159.31 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:40:09 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-28c79283-03e6-4d36-adb2-39e1e02544b2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3761031 |
| Directory | /workspace/70.rv_timer_random/latest |
| Test location | /workspace/coverage/default/71.rv_timer_random.1786157101 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 93228601059 ps |
| CPU time | 444.12 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:44:53 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-34ccb253-40cd-4dde-9f0b-a6420b87195d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786157101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1786157101 |
| Directory | /workspace/71.rv_timer_random/latest |
| Test location | /workspace/coverage/default/72.rv_timer_random.2920492016 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 93189579014 ps |
| CPU time | 179.61 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:40:28 PM PDT 24 |
| Peak memory | 191152 kb |
| Host | smart-76894d26-cd24-4392-aa3f-6f8509c6d3b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920492016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2920492016 |
| Directory | /workspace/72.rv_timer_random/latest |
| Test location | /workspace/coverage/default/73.rv_timer_random.3781474054 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 469753243644 ps |
| CPU time | 223.99 seconds |
| Started | May 30 12:37:28 PM PDT 24 |
| Finished | May 30 12:41:13 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-8611eca5-719b-4d5d-9b37-32219ac23c7e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781474054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3781474054 |
| Directory | /workspace/73.rv_timer_random/latest |
| Test location | /workspace/coverage/default/74.rv_timer_random.220155801 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 35211283295 ps |
| CPU time | 25.6 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:37:52 PM PDT 24 |
| Peak memory | 182708 kb |
| Host | smart-d9602005-0c4d-4bbb-b149-64f0a8b5927b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220155801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.220155801 |
| Directory | /workspace/74.rv_timer_random/latest |
| Test location | /workspace/coverage/default/75.rv_timer_random.3712714000 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 19403935668 ps |
| CPU time | 32.26 seconds |
| Started | May 30 12:37:29 PM PDT 24 |
| Finished | May 30 12:38:02 PM PDT 24 |
| Peak memory | 182872 kb |
| Host | smart-a39aad99-e672-4925-bd6c-4e87b43a9e7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712714000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3712714000 |
| Directory | /workspace/75.rv_timer_random/latest |
| Test location | /workspace/coverage/default/76.rv_timer_random.714137044 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 34240362681 ps |
| CPU time | 62.6 seconds |
| Started | May 30 12:37:24 PM PDT 24 |
| Finished | May 30 12:38:28 PM PDT 24 |
| Peak memory | 182968 kb |
| Host | smart-a1630eb8-4cf9-436c-8474-c82657441222 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714137044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.714137044 |
| Directory | /workspace/76.rv_timer_random/latest |
| Test location | /workspace/coverage/default/77.rv_timer_random.1651311895 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 102179335214 ps |
| CPU time | 174.51 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:40:30 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-7fff8ab5-c22d-406b-b768-74b11190c5df |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651311895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1651311895 |
| Directory | /workspace/77.rv_timer_random/latest |
| Test location | /workspace/coverage/default/78.rv_timer_random.1615587685 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 118795325176 ps |
| CPU time | 489.72 seconds |
| Started | May 30 12:37:37 PM PDT 24 |
| Finished | May 30 12:45:48 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-4d048c5e-3631-4a6e-b2d2-151eb970e1d0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615587685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1615587685 |
| Directory | /workspace/78.rv_timer_random/latest |
| Test location | /workspace/coverage/default/79.rv_timer_random.2278691071 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 117177676095 ps |
| CPU time | 171.15 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:40:18 PM PDT 24 |
| Peak memory | 191016 kb |
| Host | smart-cb8aeef4-4d58-4a21-8229-fe49d6bdfb59 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278691071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2278691071 |
| Directory | /workspace/79.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3374715826 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1011220437147 ps |
| CPU time | 242.16 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 12:40:55 PM PDT 24 |
| Peak memory | 182964 kb |
| Host | smart-41b787a8-f3e9-48d3-b0f0-543c5d1d78d0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374715826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3374715826 |
| Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/8.rv_timer_disabled.2185380017 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 27426154319 ps |
| CPU time | 43.66 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:37:30 PM PDT 24 |
| Peak memory | 182848 kb |
| Host | smart-8788caa4-6817-4569-a911-6c8b44578dcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2185380017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2185380017 |
| Directory | /workspace/8.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random.3121351253 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 1446106360365 ps |
| CPU time | 352.7 seconds |
| Started | May 30 12:36:46 PM PDT 24 |
| Finished | May 30 12:42:40 PM PDT 24 |
| Peak memory | 191016 kb |
| Host | smart-ec8f5ef3-8101-49be-9c23-408baf7bbfa6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121351253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3121351253 |
| Directory | /workspace/8.rv_timer_random/latest |
| Test location | /workspace/coverage/default/8.rv_timer_random_reset.1082648534 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 100707637 ps |
| CPU time | 0.68 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:36:47 PM PDT 24 |
| Peak memory | 182740 kb |
| Host | smart-a8e32410-9133-478d-b286-9d10b05fdb5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082648534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1082648534 |
| Directory | /workspace/8.rv_timer_random_reset/latest |
| Test location | /workspace/coverage/default/8.rv_timer_stress_all.479545566 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 185208814329 ps |
| CPU time | 277.17 seconds |
| Started | May 30 12:36:45 PM PDT 24 |
| Finished | May 30 12:41:23 PM PDT 24 |
| Peak memory | 191180 kb |
| Host | smart-30040db7-d7f5-4af6-b7b1-dc95f99c1a5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479545566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.479545566 |
| Directory | /workspace/8.rv_timer_stress_all/latest |
| Test location | /workspace/coverage/default/80.rv_timer_random.4163981685 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 185295307633 ps |
| CPU time | 325.8 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:43:01 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-ba0458d1-2adf-49f5-a529-ab8c3e2092f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163981685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4163981685 |
| Directory | /workspace/80.rv_timer_random/latest |
| Test location | /workspace/coverage/default/81.rv_timer_random.923639640 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 69406235337 ps |
| CPU time | 111.09 seconds |
| Started | May 30 12:37:37 PM PDT 24 |
| Finished | May 30 12:39:29 PM PDT 24 |
| Peak memory | 191060 kb |
| Host | smart-d9cd12c8-78fd-471c-a5eb-5081ed11f28a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923639640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.923639640 |
| Directory | /workspace/81.rv_timer_random/latest |
| Test location | /workspace/coverage/default/82.rv_timer_random.2090232549 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 198286194246 ps |
| CPU time | 1019.82 seconds |
| Started | May 30 12:37:38 PM PDT 24 |
| Finished | May 30 12:54:39 PM PDT 24 |
| Peak memory | 191160 kb |
| Host | smart-25843844-c3f2-4dca-a212-e270024fcef8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090232549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2090232549 |
| Directory | /workspace/82.rv_timer_random/latest |
| Test location | /workspace/coverage/default/83.rv_timer_random.2951075659 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 742201523076 ps |
| CPU time | 528.55 seconds |
| Started | May 30 12:37:28 PM PDT 24 |
| Finished | May 30 12:46:17 PM PDT 24 |
| Peak memory | 191008 kb |
| Host | smart-ddc9f4a7-706c-4f95-9376-fa23624e8e23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951075659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2951075659 |
| Directory | /workspace/83.rv_timer_random/latest |
| Test location | /workspace/coverage/default/84.rv_timer_random.2175537553 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 45438891920 ps |
| CPU time | 75.68 seconds |
| Started | May 30 12:37:46 PM PDT 24 |
| Finished | May 30 12:39:02 PM PDT 24 |
| Peak memory | 182872 kb |
| Host | smart-2f41d481-b058-4f57-8743-a592b4dd8485 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175537553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2175537553 |
| Directory | /workspace/84.rv_timer_random/latest |
| Test location | /workspace/coverage/default/86.rv_timer_random.163242344 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 650373823085 ps |
| CPU time | 1514.14 seconds |
| Started | May 30 12:37:42 PM PDT 24 |
| Finished | May 30 01:02:57 PM PDT 24 |
| Peak memory | 191012 kb |
| Host | smart-5cc89a0f-2b3b-485e-a769-535e5659a6c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163242344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.163242344 |
| Directory | /workspace/86.rv_timer_random/latest |
| Test location | /workspace/coverage/default/87.rv_timer_random.936482060 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 122453206611 ps |
| CPU time | 224.22 seconds |
| Started | May 30 12:37:28 PM PDT 24 |
| Finished | May 30 12:41:19 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-704f9e6a-c391-4ba9-bbcb-9af8af6c993b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936482060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.936482060 |
| Directory | /workspace/87.rv_timer_random/latest |
| Test location | /workspace/coverage/default/88.rv_timer_random.4058970723 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 203066294336 ps |
| CPU time | 116.59 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:39:31 PM PDT 24 |
| Peak memory | 191016 kb |
| Host | smart-702316e3-60f4-4965-94b6-4c4a4b3aeeb6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058970723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4058970723 |
| Directory | /workspace/88.rv_timer_random/latest |
| Test location | /workspace/coverage/default/89.rv_timer_random.2148461961 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 302610000657 ps |
| CPU time | 254.7 seconds |
| Started | May 30 12:37:27 PM PDT 24 |
| Finished | May 30 12:41:43 PM PDT 24 |
| Peak memory | 191008 kb |
| Host | smart-f93240c3-6d48-42f7-8018-1abb23e67dfd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148461961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2148461961 |
| Directory | /workspace/89.rv_timer_random/latest |
| Test location | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2619577589 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 59139803020 ps |
| CPU time | 111.06 seconds |
| Started | May 30 12:36:52 PM PDT 24 |
| Finished | May 30 12:38:44 PM PDT 24 |
| Peak memory | 182624 kb |
| Host | smart-4959e503-dcc6-40e6-a76e-b9dd64fd8ffb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619577589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.2619577589 |
| Directory | /workspace/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspace/coverage/default/9.rv_timer_disabled.1416684701 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 408604509319 ps |
| CPU time | 175.02 seconds |
| Started | May 30 12:37:11 PM PDT 24 |
| Finished | May 30 12:40:06 PM PDT 24 |
| Peak memory | 182884 kb |
| Host | smart-594def02-91e6-4dec-b04b-18f4fc2f6477 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1416684701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1416684701 |
| Directory | /workspace/9.rv_timer_disabled/latest |
| Test location | /workspace/coverage/default/9.rv_timer_random.1369170540 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 368537705722 ps |
| CPU time | 362.03 seconds |
| Started | May 30 12:36:58 PM PDT 24 |
| Finished | May 30 12:43:01 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-4c5731dc-e1d0-4a2a-afe3-c52b2d2317ea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369170540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1369170540 |
| Directory | /workspace/9.rv_timer_random/latest |
| Test location | /workspace/coverage/default/90.rv_timer_random.1676604140 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 222623296022 ps |
| CPU time | 234.12 seconds |
| Started | May 30 12:37:34 PM PDT 24 |
| Finished | May 30 12:41:34 PM PDT 24 |
| Peak memory | 193528 kb |
| Host | smart-7a44676e-1555-4a9d-9676-33d560473369 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676604140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1676604140 |
| Directory | /workspace/90.rv_timer_random/latest |
| Test location | /workspace/coverage/default/91.rv_timer_random.2445647254 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 612712586393 ps |
| CPU time | 327.74 seconds |
| Started | May 30 12:37:25 PM PDT 24 |
| Finished | May 30 12:42:53 PM PDT 24 |
| Peak memory | 193228 kb |
| Host | smart-7adc8c2e-7241-405a-85dd-41af1de1f847 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445647254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2445647254 |
| Directory | /workspace/91.rv_timer_random/latest |
| Test location | /workspace/coverage/default/93.rv_timer_random.2698787058 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 287431924670 ps |
| CPU time | 287.45 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:42:20 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-76fffc27-7683-44f7-a30e-be478ebda4f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698787058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2698787058 |
| Directory | /workspace/93.rv_timer_random/latest |
| Test location | /workspace/coverage/default/94.rv_timer_random.2493415988 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 969119376272 ps |
| CPU time | 419.38 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:44:33 PM PDT 24 |
| Peak memory | 191172 kb |
| Host | smart-36be0b6a-74dd-4aae-95f8-83fd50dc859a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493415988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2493415988 |
| Directory | /workspace/94.rv_timer_random/latest |
| Test location | /workspace/coverage/default/95.rv_timer_random.538683435 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 168041077617 ps |
| CPU time | 126.72 seconds |
| Started | May 30 12:37:36 PM PDT 24 |
| Finished | May 30 12:39:44 PM PDT 24 |
| Peak memory | 191068 kb |
| Host | smart-1f37be65-8102-46bd-af68-47e0d5c6a96b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538683435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.538683435 |
| Directory | /workspace/95.rv_timer_random/latest |
| Test location | /workspace/coverage/default/96.rv_timer_random.1619027870 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 48579874367 ps |
| CPU time | 64.65 seconds |
| Started | May 30 12:37:32 PM PDT 24 |
| Finished | May 30 12:38:38 PM PDT 24 |
| Peak memory | 191164 kb |
| Host | smart-8bfe74ca-5382-4226-a9bf-53eeea0ad15d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619027870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1619027870 |
| Directory | /workspace/96.rv_timer_random/latest |
| Test location | /workspace/coverage/default/97.rv_timer_random.4232405116 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 569805370286 ps |
| CPU time | 1323.06 seconds |
| Started | May 30 12:37:38 PM PDT 24 |
| Finished | May 30 12:59:46 PM PDT 24 |
| Peak memory | 191072 kb |
| Host | smart-7ec45780-08d5-45a9-983c-e1efa2e99952 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232405116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4232405116 |
| Directory | /workspace/97.rv_timer_random/latest |
| Test location | /workspace/coverage/default/98.rv_timer_random.2649154798 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 79041255699 ps |
| CPU time | 132.13 seconds |
| Started | May 30 12:37:28 PM PDT 24 |
| Finished | May 30 12:39:42 PM PDT 24 |
| Peak memory | 193856 kb |
| Host | smart-d44dfacb-99ac-4070-a7ae-872fd562f104 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649154798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2649154798 |
| Directory | /workspace/98.rv_timer_random/latest |
| Test location | /workspace/coverage/default/99.rv_timer_random.4095511857 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 95318010234 ps |
| CPU time | 186.84 seconds |
| Started | May 30 12:37:33 PM PDT 24 |
| Finished | May 30 12:40:41 PM PDT 24 |
| Peak memory | 191064 kb |
| Host | smart-3370ff4a-84ca-4f39-9596-5a89837d3e11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095511857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4095511857 |
| Directory | /workspace/99.rv_timer_random/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |