Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4202372552 Jun 02 02:03:09 PM PDT 24 Jun 02 02:03:11 PM PDT 24 204705184 ps
T512 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1200098123 Jun 02 02:03:28 PM PDT 24 Jun 02 02:03:29 PM PDT 24 31284296 ps
T513 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3393498691 Jun 02 02:03:26 PM PDT 24 Jun 02 02:03:27 PM PDT 24 64137999 ps
T514 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2644721422 Jun 02 02:03:38 PM PDT 24 Jun 02 02:03:39 PM PDT 24 87956254 ps
T81 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1061389809 Jun 02 02:03:09 PM PDT 24 Jun 02 02:03:10 PM PDT 24 45166943 ps
T515 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1178587853 Jun 02 02:03:34 PM PDT 24 Jun 02 02:03:35 PM PDT 24 39437472 ps
T516 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.305583072 Jun 02 02:03:19 PM PDT 24 Jun 02 02:03:22 PM PDT 24 140273023 ps
T517 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2964258549 Jun 02 02:03:08 PM PDT 24 Jun 02 02:03:09 PM PDT 24 25356268 ps
T518 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4138583474 Jun 02 02:03:07 PM PDT 24 Jun 02 02:03:09 PM PDT 24 321002971 ps
T91 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3915690871 Jun 02 02:03:26 PM PDT 24 Jun 02 02:03:27 PM PDT 24 16238646 ps
T519 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4113338836 Jun 02 02:03:18 PM PDT 24 Jun 02 02:03:19 PM PDT 24 22486008 ps
T520 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4059767420 Jun 02 02:03:35 PM PDT 24 Jun 02 02:03:37 PM PDT 24 64220701 ps
T521 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.5536345 Jun 02 02:03:10 PM PDT 24 Jun 02 02:03:11 PM PDT 24 20726772 ps
T522 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.194050713 Jun 02 02:03:15 PM PDT 24 Jun 02 02:03:17 PM PDT 24 342080468 ps
T523 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1603372355 Jun 02 02:03:03 PM PDT 24 Jun 02 02:03:05 PM PDT 24 131698970 ps
T524 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.630458021 Jun 02 02:03:21 PM PDT 24 Jun 02 02:03:22 PM PDT 24 23367624 ps
T525 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3904443040 Jun 02 02:03:18 PM PDT 24 Jun 02 02:03:19 PM PDT 24 13196718 ps
T526 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2152526106 Jun 02 02:03:06 PM PDT 24 Jun 02 02:03:07 PM PDT 24 40174124 ps
T92 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3866693489 Jun 02 02:03:19 PM PDT 24 Jun 02 02:03:20 PM PDT 24 55183957 ps
T527 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1061397144 Jun 02 02:03:28 PM PDT 24 Jun 02 02:03:29 PM PDT 24 40219505 ps
T528 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2330334553 Jun 02 02:03:05 PM PDT 24 Jun 02 02:03:07 PM PDT 24 327606428 ps
T529 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2069644882 Jun 02 02:03:41 PM PDT 24 Jun 02 02:03:42 PM PDT 24 13636480 ps
T530 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3569570587 Jun 02 02:03:15 PM PDT 24 Jun 02 02:03:17 PM PDT 24 54418977 ps
T531 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2135226887 Jun 02 02:03:13 PM PDT 24 Jun 02 02:03:15 PM PDT 24 21116335 ps
T532 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.866597644 Jun 02 02:03:06 PM PDT 24 Jun 02 02:03:07 PM PDT 24 39077752 ps
T533 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1265063772 Jun 02 02:03:07 PM PDT 24 Jun 02 02:03:08 PM PDT 24 45024551 ps
T534 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3218592306 Jun 02 02:03:36 PM PDT 24 Jun 02 02:03:36 PM PDT 24 12960377 ps
T535 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3732051725 Jun 02 02:03:25 PM PDT 24 Jun 02 02:03:28 PM PDT 24 376750001 ps
T536 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.524912299 Jun 02 02:03:29 PM PDT 24 Jun 02 02:03:30 PM PDT 24 135716107 ps
T93 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3011215439 Jun 02 02:03:29 PM PDT 24 Jun 02 02:03:30 PM PDT 24 40676783 ps
T537 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2309592162 Jun 02 02:03:43 PM PDT 24 Jun 02 02:03:44 PM PDT 24 13832982 ps
T538 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3085596305 Jun 02 02:03:26 PM PDT 24 Jun 02 02:03:27 PM PDT 24 67117269 ps
T539 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1167226240 Jun 02 02:03:35 PM PDT 24 Jun 02 02:03:36 PM PDT 24 20646004 ps
T540 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1962139458 Jun 02 02:03:33 PM PDT 24 Jun 02 02:03:34 PM PDT 24 16412579 ps
T541 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1561968313 Jun 02 02:03:27 PM PDT 24 Jun 02 02:03:29 PM PDT 24 62999409 ps
T542 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2472865532 Jun 02 02:03:13 PM PDT 24 Jun 02 02:03:14 PM PDT 24 13760840 ps
T543 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3916439092 Jun 02 02:03:37 PM PDT 24 Jun 02 02:03:38 PM PDT 24 37157361 ps
T108 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4194610660 Jun 02 02:03:15 PM PDT 24 Jun 02 02:03:17 PM PDT 24 621300213 ps
T544 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4293819663 Jun 02 02:03:29 PM PDT 24 Jun 02 02:03:30 PM PDT 24 20344501 ps
T545 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1131251308 Jun 02 02:03:35 PM PDT 24 Jun 02 02:03:36 PM PDT 24 12656384 ps
T546 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1523445699 Jun 02 02:03:18 PM PDT 24 Jun 02 02:03:19 PM PDT 24 36858036 ps
T547 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3732635042 Jun 02 02:03:31 PM PDT 24 Jun 02 02:03:32 PM PDT 24 74670607 ps
T548 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2083196144 Jun 02 02:03:15 PM PDT 24 Jun 02 02:03:17 PM PDT 24 65681465 ps
T549 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.645964796 Jun 02 02:03:12 PM PDT 24 Jun 02 02:03:14 PM PDT 24 121901914 ps
T550 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4005372541 Jun 02 02:03:37 PM PDT 24 Jun 02 02:03:38 PM PDT 24 25910080 ps
T551 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1509633323 Jun 02 02:03:20 PM PDT 24 Jun 02 02:03:23 PM PDT 24 86946767 ps
T552 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.84617866 Jun 02 02:03:13 PM PDT 24 Jun 02 02:03:15 PM PDT 24 39667348 ps
T553 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1920555147 Jun 02 02:03:28 PM PDT 24 Jun 02 02:03:32 PM PDT 24 871792104 ps
T554 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1737632506 Jun 02 02:03:42 PM PDT 24 Jun 02 02:03:43 PM PDT 24 26896101 ps
T555 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.379302891 Jun 02 02:03:29 PM PDT 24 Jun 02 02:03:31 PM PDT 24 133823805 ps
T556 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1322186412 Jun 02 02:03:36 PM PDT 24 Jun 02 02:03:37 PM PDT 24 45215659 ps
T557 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2989646423 Jun 02 02:03:41 PM PDT 24 Jun 02 02:03:42 PM PDT 24 47028349 ps
T558 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1152952577 Jun 02 02:03:39 PM PDT 24 Jun 02 02:03:40 PM PDT 24 117358845 ps
T559 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3563202792 Jun 02 02:03:05 PM PDT 24 Jun 02 02:03:06 PM PDT 24 76948553 ps
T560 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.899287941 Jun 02 02:03:35 PM PDT 24 Jun 02 02:03:36 PM PDT 24 17415900 ps
T561 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.582927975 Jun 02 02:03:15 PM PDT 24 Jun 02 02:03:17 PM PDT 24 90599756 ps
T562 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.613365605 Jun 02 02:03:34 PM PDT 24 Jun 02 02:03:35 PM PDT 24 61745169 ps
T563 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.165059926 Jun 02 02:03:14 PM PDT 24 Jun 02 02:03:15 PM PDT 24 19221558 ps
T564 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3552040461 Jun 02 02:03:16 PM PDT 24 Jun 02 02:03:17 PM PDT 24 30535809 ps
T565 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2280981914 Jun 02 02:03:30 PM PDT 24 Jun 02 02:03:31 PM PDT 24 68138187 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4002699121 Jun 02 02:03:23 PM PDT 24 Jun 02 02:03:24 PM PDT 24 72936735 ps
T567 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1836752476 Jun 02 02:03:24 PM PDT 24 Jun 02 02:03:25 PM PDT 24 185772758 ps
T568 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.302690667 Jun 02 02:03:29 PM PDT 24 Jun 02 02:03:30 PM PDT 24 29744422 ps
T569 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2226724870 Jun 02 02:03:39 PM PDT 24 Jun 02 02:03:40 PM PDT 24 17924547 ps
T570 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1347479800 Jun 02 02:03:02 PM PDT 24 Jun 02 02:03:04 PM PDT 24 28376554 ps
T571 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3230973361 Jun 02 02:03:16 PM PDT 24 Jun 02 02:03:17 PM PDT 24 17711610 ps
T572 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1614998265 Jun 02 02:03:36 PM PDT 24 Jun 02 02:03:40 PM PDT 24 701246445 ps
T97 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.856167983 Jun 02 02:03:01 PM PDT 24 Jun 02 02:03:02 PM PDT 24 36993366 ps
T573 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.658962200 Jun 02 02:03:15 PM PDT 24 Jun 02 02:03:16 PM PDT 24 123156034 ps
T574 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2838591646 Jun 02 02:03:24 PM PDT 24 Jun 02 02:03:25 PM PDT 24 50671732 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.410657065 Jun 02 02:03:08 PM PDT 24 Jun 02 02:03:09 PM PDT 24 104612845 ps
T98 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2608879542 Jun 02 02:03:25 PM PDT 24 Jun 02 02:03:26 PM PDT 24 34735895 ps
T94 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.948995322 Jun 02 02:03:29 PM PDT 24 Jun 02 02:03:30 PM PDT 24 15334363 ps
T576 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2151634287 Jun 02 02:03:36 PM PDT 24 Jun 02 02:03:37 PM PDT 24 14085550 ps
T95 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1032496296 Jun 02 02:03:08 PM PDT 24 Jun 02 02:03:12 PM PDT 24 1678608416 ps
T577 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1438700266 Jun 02 02:03:23 PM PDT 24 Jun 02 02:03:25 PM PDT 24 31929722 ps
T578 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2138208399 Jun 02 02:03:21 PM PDT 24 Jun 02 02:03:23 PM PDT 24 145317048 ps
T579 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1938213768 Jun 02 02:03:40 PM PDT 24 Jun 02 02:03:41 PM PDT 24 34734649 ps
T96 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.727550383 Jun 02 02:03:22 PM PDT 24 Jun 02 02:03:23 PM PDT 24 17795399 ps
T580 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3507810011 Jun 02 02:03:12 PM PDT 24 Jun 02 02:03:14 PM PDT 24 33975763 ps

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2529502509
Short name T1
Test name
Test status
Simulation time 318973703070 ps
CPU time 308.71 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:23:33 PM PDT 24
Peak memory 182952 kb
Host smart-ee5dd95f-1346-4398-8fae-0ae3583a5a30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529502509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2529502509
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2011110095
Short name T15
Test name
Test status
Simulation time 58043385339 ps
CPU time 429.57 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:25:48 PM PDT 24
Peak memory 205776 kb
Host smart-395eb328-da4c-4b17-af0b-e44cc5b76ed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011110095 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2011110095
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_random.2027372903
Short name T62
Test name
Test status
Simulation time 195815904050 ps
CPU time 494.18 seconds
Started Jun 02 02:18:32 PM PDT 24
Finished Jun 02 02:26:47 PM PDT 24
Peak memory 191188 kb
Host smart-4267dbee-d946-4fcc-8153-08bd766c5954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027372903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2027372903
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1122479527
Short name T11
Test name
Test status
Simulation time 894804485008 ps
CPU time 2091.52 seconds
Started Jun 02 02:18:41 PM PDT 24
Finished Jun 02 02:53:33 PM PDT 24
Peak memory 195496 kb
Host smart-daef3804-c1b9-4814-afed-df7c7915228e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122479527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1122479527
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2153143797
Short name T32
Test name
Test status
Simulation time 186689644 ps
CPU time 1.32 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 195384 kb
Host smart-abb19260-2906-4d40-8855-9c7205bad7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153143797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2153143797
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.480831168
Short name T88
Test name
Test status
Simulation time 4624005782334 ps
CPU time 3577.52 seconds
Started Jun 02 02:19:02 PM PDT 24
Finished Jun 02 03:18:41 PM PDT 24
Peak memory 191116 kb
Host smart-6369c5da-4139-4bb1-a2e6-b2817405ccde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480831168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
480831168
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2467644203
Short name T137
Test name
Test status
Simulation time 1834517904578 ps
CPU time 7095.06 seconds
Started Jun 02 02:18:37 PM PDT 24
Finished Jun 02 04:16:53 PM PDT 24
Peak memory 191192 kb
Host smart-077066e3-982b-4e43-abc3-eab5b2d70c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467644203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2467644203
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2653557711
Short name T58
Test name
Test status
Simulation time 224910523350 ps
CPU time 698.33 seconds
Started Jun 02 02:18:17 PM PDT 24
Finished Jun 02 02:29:56 PM PDT 24
Peak memory 191140 kb
Host smart-93955d5c-670b-491f-9046-9fd5fb4deefe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653557711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2653557711
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.199323901
Short name T150
Test name
Test status
Simulation time 436672290763 ps
CPU time 636.6 seconds
Started Jun 02 02:19:01 PM PDT 24
Finished Jun 02 02:29:38 PM PDT 24
Peak memory 191196 kb
Host smart-34c1b286-59d1-4ab8-9479-9dfebb6f3d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199323901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
199323901
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.384943916
Short name T36
Test name
Test status
Simulation time 18754981 ps
CPU time 0.57 seconds
Started Jun 02 02:03:23 PM PDT 24
Finished Jun 02 02:03:24 PM PDT 24
Peak memory 182744 kb
Host smart-cf75c2cc-221e-4cfe-9625-8575ba258ee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384943916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.384943916
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.216872112
Short name T152
Test name
Test status
Simulation time 1415481780492 ps
CPU time 2357.62 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:58:02 PM PDT 24
Peak memory 196108 kb
Host smart-9700de83-6842-444b-a05a-fa1056fad4ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216872112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
216872112
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1559496662
Short name T156
Test name
Test status
Simulation time 627791985185 ps
CPU time 1946.7 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:50:52 PM PDT 24
Peak memory 191196 kb
Host smart-ab7f6e4e-7219-4a0a-a1c0-611f46ce4ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559496662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1559496662
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2936998284
Short name T161
Test name
Test status
Simulation time 1684091189909 ps
CPU time 3639.03 seconds
Started Jun 02 02:18:22 PM PDT 24
Finished Jun 02 03:19:02 PM PDT 24
Peak memory 191184 kb
Host smart-e33f9425-0f86-48ca-a9fd-1f66d0ec1525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936998284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2936998284
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1317003962
Short name T12
Test name
Test status
Simulation time 156394867132 ps
CPU time 219.36 seconds
Started Jun 02 02:18:22 PM PDT 24
Finished Jun 02 02:22:02 PM PDT 24
Peak memory 191188 kb
Host smart-c8e86e0b-f35e-4ba8-bdc8-d136d657233b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317003962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1317003962
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1039256996
Short name T187
Test name
Test status
Simulation time 7892862553397 ps
CPU time 2046.32 seconds
Started Jun 02 02:18:50 PM PDT 24
Finished Jun 02 02:52:57 PM PDT 24
Peak memory 191136 kb
Host smart-ae9d6ae6-4b0f-46e7-bdc1-f9a197018c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039256996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1039256996
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2276476577
Short name T22
Test name
Test status
Simulation time 167472779 ps
CPU time 0.94 seconds
Started Jun 02 02:18:13 PM PDT 24
Finished Jun 02 02:18:14 PM PDT 24
Peak memory 214460 kb
Host smart-d624cdb4-32cd-4cb0-b59c-4fb7ad03ab35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276476577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2276476577
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3753849295
Short name T312
Test name
Test status
Simulation time 639537824494 ps
CPU time 2513.77 seconds
Started Jun 02 02:18:27 PM PDT 24
Finished Jun 02 03:00:21 PM PDT 24
Peak memory 191196 kb
Host smart-c19c3117-49c4-4e90-b38b-714a5697fc14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753849295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3753849295
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1095945509
Short name T242
Test name
Test status
Simulation time 1323857374627 ps
CPU time 975.22 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:35:14 PM PDT 24
Peak memory 191200 kb
Host smart-836b0d69-b17f-49c2-a654-05ae65d7acd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095945509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1095945509
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3854997088
Short name T87
Test name
Test status
Simulation time 976940587906 ps
CPU time 1384.87 seconds
Started Jun 02 02:19:18 PM PDT 24
Finished Jun 02 02:42:24 PM PDT 24
Peak memory 191104 kb
Host smart-6b2572e4-e034-4fa7-a98d-275c0ead83a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854997088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3854997088
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_random.363528483
Short name T63
Test name
Test status
Simulation time 411168157067 ps
CPU time 379.19 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:24:59 PM PDT 24
Peak memory 191184 kb
Host smart-fd7d3d70-976a-4887-9f04-b7d616641efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363528483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.363528483
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1422050690
Short name T171
Test name
Test status
Simulation time 1132956883427 ps
CPU time 3138.42 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 03:10:43 PM PDT 24
Peak memory 195456 kb
Host smart-35bc0dc0-cbcb-467e-ac39-68da5ffed4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422050690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1422050690
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3723136062
Short name T218
Test name
Test status
Simulation time 1091618012439 ps
CPU time 541.08 seconds
Started Jun 02 02:18:17 PM PDT 24
Finished Jun 02 02:27:19 PM PDT 24
Peak memory 182980 kb
Host smart-0dfdd92c-8172-4b3b-afc3-335bb1b14fac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723136062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3723136062
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/159.rv_timer_random.2118633255
Short name T274
Test name
Test status
Simulation time 391862164926 ps
CPU time 1204.39 seconds
Started Jun 02 02:20:39 PM PDT 24
Finished Jun 02 02:40:44 PM PDT 24
Peak memory 191184 kb
Host smart-e17e2d16-4cbc-4afb-99b4-d5eac7e27025
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118633255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2118633255
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.493017833
Short name T283
Test name
Test status
Simulation time 391073701788 ps
CPU time 707.14 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:30:26 PM PDT 24
Peak memory 191176 kb
Host smart-32c82bea-ce4c-43cc-aa87-f4e270397b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493017833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
493017833
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/88.rv_timer_random.472757849
Short name T25
Test name
Test status
Simulation time 410234709752 ps
CPU time 329.37 seconds
Started Jun 02 02:19:41 PM PDT 24
Finished Jun 02 02:25:11 PM PDT 24
Peak memory 191168 kb
Host smart-32e244c9-0e33-4e5e-bb74-24dfbd5176fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472757849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.472757849
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2226467599
Short name T284
Test name
Test status
Simulation time 1187802628465 ps
CPU time 1803.01 seconds
Started Jun 02 02:20:41 PM PDT 24
Finished Jun 02 02:50:45 PM PDT 24
Peak memory 191096 kb
Host smart-8ea97036-e6b0-43dc-b344-d45625e5355c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226467599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2226467599
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3483470617
Short name T129
Test name
Test status
Simulation time 352455360970 ps
CPU time 677.91 seconds
Started Jun 02 02:18:51 PM PDT 24
Finished Jun 02 02:30:09 PM PDT 24
Peak memory 191192 kb
Host smart-79830948-88cf-4993-ba3c-3fd9b614b90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483470617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3483470617
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/83.rv_timer_random.1277456810
Short name T201
Test name
Test status
Simulation time 160594345591 ps
CPU time 1940.92 seconds
Started Jun 02 02:19:42 PM PDT 24
Finished Jun 02 02:52:03 PM PDT 24
Peak memory 194720 kb
Host smart-005ac691-ae8f-46a1-936e-4aa527c897ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277456810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1277456810
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.2791667035
Short name T183
Test name
Test status
Simulation time 172274881312 ps
CPU time 771.62 seconds
Started Jun 02 02:20:42 PM PDT 24
Finished Jun 02 02:33:34 PM PDT 24
Peak memory 191104 kb
Host smart-f696f434-fe27-4a91-a7c6-8f423a5cda1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791667035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2791667035
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3373411988
Short name T313
Test name
Test status
Simulation time 3154972420831 ps
CPU time 1808.49 seconds
Started Jun 02 02:18:31 PM PDT 24
Finished Jun 02 02:48:41 PM PDT 24
Peak memory 191196 kb
Host smart-977b9cf9-bd85-4a7e-a708-879c5de5188c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373411988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3373411988
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/57.rv_timer_random.3322035506
Short name T135
Test name
Test status
Simulation time 722953195170 ps
CPU time 415.97 seconds
Started Jun 02 02:19:24 PM PDT 24
Finished Jun 02 02:26:20 PM PDT 24
Peak memory 191192 kb
Host smart-3e2aab40-483e-4ac0-94be-6761666c60f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322035506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3322035506
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3941990946
Short name T160
Test name
Test status
Simulation time 2069667784077 ps
CPU time 1083.09 seconds
Started Jun 02 02:18:18 PM PDT 24
Finished Jun 02 02:36:22 PM PDT 24
Peak memory 191148 kb
Host smart-e6417de0-5ff3-49ca-9633-a4b6edf8368f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941990946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3941990946
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/162.rv_timer_random.1072587993
Short name T287
Test name
Test status
Simulation time 522693459154 ps
CPU time 1415.36 seconds
Started Jun 02 02:20:41 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 191104 kb
Host smart-ed00de53-c695-4bf3-9636-b9c899422a39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072587993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1072587993
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2819601235
Short name T149
Test name
Test status
Simulation time 143162076037 ps
CPU time 535.78 seconds
Started Jun 02 02:19:29 PM PDT 24
Finished Jun 02 02:28:25 PM PDT 24
Peak memory 191140 kb
Host smart-264e54cd-b158-406b-a51f-2ff5c93fbabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819601235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2819601235
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.4068630205
Short name T357
Test name
Test status
Simulation time 556349303477 ps
CPU time 271.32 seconds
Started Jun 02 02:20:28 PM PDT 24
Finished Jun 02 02:25:00 PM PDT 24
Peak memory 191096 kb
Host smart-2fd5d23e-df82-45fe-9cda-f10ebfb04277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068630205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.4068630205
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.938062722
Short name T165
Test name
Test status
Simulation time 163745174106 ps
CPU time 360.36 seconds
Started Jun 02 02:21:05 PM PDT 24
Finished Jun 02 02:27:06 PM PDT 24
Peak memory 191172 kb
Host smart-9e0a4a52-4798-468c-b0e4-56be225db346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938062722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.938062722
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.2742800979
Short name T305
Test name
Test status
Simulation time 282986379444 ps
CPU time 630.89 seconds
Started Jun 02 02:18:33 PM PDT 24
Finished Jun 02 02:29:04 PM PDT 24
Peak memory 191164 kb
Host smart-49caa9c6-f592-4b9d-9dcf-a9e2a442037f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742800979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2742800979
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.558275515
Short name T29
Test name
Test status
Simulation time 607367046077 ps
CPU time 1064.17 seconds
Started Jun 02 02:18:51 PM PDT 24
Finished Jun 02 02:36:36 PM PDT 24
Peak memory 191132 kb
Host smart-7bf48dbe-4a91-42d5-82a6-f7d0623d4837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558275515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.558275515
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3757141973
Short name T180
Test name
Test status
Simulation time 856922736924 ps
CPU time 543.17 seconds
Started Jun 02 02:19:36 PM PDT 24
Finished Jun 02 02:28:39 PM PDT 24
Peak memory 191136 kb
Host smart-5889fd38-2b3b-47f9-ba7c-9958ed4e3f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757141973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3757141973
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.408942178
Short name T157
Test name
Test status
Simulation time 156720859595 ps
CPU time 218.71 seconds
Started Jun 02 02:20:07 PM PDT 24
Finished Jun 02 02:23:46 PM PDT 24
Peak memory 191136 kb
Host smart-0c78c525-6383-4886-906c-9ddc81eae6ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408942178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.408942178
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3864673668
Short name T256
Test name
Test status
Simulation time 996003454892 ps
CPU time 863.49 seconds
Started Jun 02 02:20:06 PM PDT 24
Finished Jun 02 02:34:30 PM PDT 24
Peak memory 191136 kb
Host smart-77fe367a-9a97-49d5-ba3e-d0e0f7eb27d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864673668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3864673668
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1459877885
Short name T198
Test name
Test status
Simulation time 531116460646 ps
CPU time 1119.21 seconds
Started Jun 02 02:18:27 PM PDT 24
Finished Jun 02 02:37:06 PM PDT 24
Peak memory 191164 kb
Host smart-9eab5f09-99dc-45af-89f0-3c7c553bf503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459877885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1459877885
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/146.rv_timer_random.2754844227
Short name T253
Test name
Test status
Simulation time 634786079179 ps
CPU time 1304.02 seconds
Started Jun 02 02:20:33 PM PDT 24
Finished Jun 02 02:42:17 PM PDT 24
Peak memory 191188 kb
Host smart-ce6490a6-23e6-4516-b4cd-35f2920ed395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754844227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2754844227
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2402386905
Short name T186
Test name
Test status
Simulation time 382783142465 ps
CPU time 996.12 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:35:16 PM PDT 24
Peak memory 191192 kb
Host smart-6b9b9fdc-b960-48df-9a35-3e7bb743231e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402386905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2402386905
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2030175100
Short name T216
Test name
Test status
Simulation time 482556011137 ps
CPU time 1658.24 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:46:23 PM PDT 24
Peak memory 191196 kb
Host smart-4cfdb41d-d607-4725-b345-c2bb514fa4c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030175100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2030175100
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_random.1227318119
Short name T309
Test name
Test status
Simulation time 765357925655 ps
CPU time 389.73 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:25:22 PM PDT 24
Peak memory 191144 kb
Host smart-38c8e0a2-0408-43c6-86c9-56d27bf7e9e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227318119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1227318119
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2596542106
Short name T48
Test name
Test status
Simulation time 302759487363 ps
CPU time 292.09 seconds
Started Jun 02 02:20:15 PM PDT 24
Finished Jun 02 02:25:07 PM PDT 24
Peak memory 191188 kb
Host smart-d4425e66-2e7c-4abd-ac80-e9c9c1100247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596542106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2596542106
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2250714004
Short name T119
Test name
Test status
Simulation time 220209147717 ps
CPU time 1540.02 seconds
Started Jun 02 02:20:33 PM PDT 24
Finished Jun 02 02:46:14 PM PDT 24
Peak memory 191120 kb
Host smart-98122e4d-ccab-456a-8d9d-97d85668f2db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250714004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2250714004
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.714170210
Short name T4
Test name
Test status
Simulation time 173697809550 ps
CPU time 305.33 seconds
Started Jun 02 02:20:33 PM PDT 24
Finished Jun 02 02:25:39 PM PDT 24
Peak memory 191180 kb
Host smart-45b292df-c5d3-425a-95d5-71ed0a8b956c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714170210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.714170210
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2249965659
Short name T190
Test name
Test status
Simulation time 812820207264 ps
CPU time 608.58 seconds
Started Jun 02 02:18:31 PM PDT 24
Finished Jun 02 02:28:41 PM PDT 24
Peak memory 191164 kb
Host smart-eab6ed66-ccd5-469d-8fbc-09fc317308b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249965659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2249965659
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.188648061
Short name T249
Test name
Test status
Simulation time 823385048281 ps
CPU time 483.84 seconds
Started Jun 02 02:21:04 PM PDT 24
Finished Jun 02 02:29:08 PM PDT 24
Peak memory 191176 kb
Host smart-1ee45aab-aa86-4c83-ba17-63a5ddbb3316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188648061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.188648061
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1041546953
Short name T189
Test name
Test status
Simulation time 421209188230 ps
CPU time 215.74 seconds
Started Jun 02 02:18:15 PM PDT 24
Finished Jun 02 02:21:51 PM PDT 24
Peak memory 182996 kb
Host smart-14b50683-a72b-4b8a-aed2-05dae10c8822
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041546953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1041546953
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1564603613
Short name T174
Test name
Test status
Simulation time 231507080450 ps
CPU time 117.9 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:20:38 PM PDT 24
Peak memory 191152 kb
Host smart-97975bc7-2603-4219-ae35-740cca1cc062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564603613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1564603613
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.841142762
Short name T199
Test name
Test status
Simulation time 110712186379 ps
CPU time 199.1 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:21:57 PM PDT 24
Peak memory 195040 kb
Host smart-522dbfde-b226-4ac5-be84-6cd41f5aa46c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841142762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
841142762
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3261893605
Short name T103
Test name
Test status
Simulation time 75711745 ps
CPU time 0.8 seconds
Started Jun 02 02:03:10 PM PDT 24
Finished Jun 02 02:03:12 PM PDT 24
Peak memory 193256 kb
Host smart-732cb568-8940-496b-880e-7ca1fa1338b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261893605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3261893605
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/112.rv_timer_random.1898842876
Short name T132
Test name
Test status
Simulation time 273619044770 ps
CPU time 550.45 seconds
Started Jun 02 02:20:00 PM PDT 24
Finished Jun 02 02:29:10 PM PDT 24
Peak memory 191196 kb
Host smart-54125f77-79be-4a6e-b431-7d278afd1bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898842876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1898842876
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1405926391
Short name T116
Test name
Test status
Simulation time 1515512879352 ps
CPU time 658.4 seconds
Started Jun 02 02:20:05 PM PDT 24
Finished Jun 02 02:31:04 PM PDT 24
Peak memory 191148 kb
Host smart-02ec7c7d-461e-4a21-bd25-ef94aa4ff9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405926391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1405926391
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1696081119
Short name T69
Test name
Test status
Simulation time 688255458196 ps
CPU time 576.49 seconds
Started Jun 02 02:20:07 PM PDT 24
Finished Jun 02 02:29:44 PM PDT 24
Peak memory 194344 kb
Host smart-faafdecc-2dd7-4bed-b6d3-f25817d31231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696081119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1696081119
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.1809828680
Short name T235
Test name
Test status
Simulation time 117734987564 ps
CPU time 307.93 seconds
Started Jun 02 02:18:22 PM PDT 24
Finished Jun 02 02:23:30 PM PDT 24
Peak memory 191128 kb
Host smart-2afc9807-dd30-4c3e-bad5-225e67571080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809828680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1809828680
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3261362073
Short name T226
Test name
Test status
Simulation time 62970446132 ps
CPU time 119.57 seconds
Started Jun 02 02:18:23 PM PDT 24
Finished Jun 02 02:20:23 PM PDT 24
Peak memory 191192 kb
Host smart-dbee450c-ee41-41d1-84f5-b7c61c6d5af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261362073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3261362073
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4204481040
Short name T276
Test name
Test status
Simulation time 186788772814 ps
CPU time 320.98 seconds
Started Jun 02 02:20:47 PM PDT 24
Finished Jun 02 02:26:09 PM PDT 24
Peak memory 191136 kb
Host smart-f56dbd7c-7341-43ec-85fb-34a3c8fe9427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204481040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4204481040
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4235729997
Short name T131
Test name
Test status
Simulation time 97673024236 ps
CPU time 351.93 seconds
Started Jun 02 02:20:47 PM PDT 24
Finished Jun 02 02:26:40 PM PDT 24
Peak memory 194772 kb
Host smart-b5f5c12c-37b3-4718-a4ff-3ac3c9706026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235729997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4235729997
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.700971392
Short name T50
Test name
Test status
Simulation time 193196629399 ps
CPU time 331.35 seconds
Started Jun 02 02:20:58 PM PDT 24
Finished Jun 02 02:26:30 PM PDT 24
Peak memory 191168 kb
Host smart-bf81ecbe-066e-43ab-b7af-e25b2e9377bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700971392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.700971392
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2560458315
Short name T164
Test name
Test status
Simulation time 89398800844 ps
CPU time 430.36 seconds
Started Jun 02 02:20:57 PM PDT 24
Finished Jun 02 02:28:08 PM PDT 24
Peak memory 191196 kb
Host smart-ee8a9c95-be7c-4ee0-b4b9-9c438267d3ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560458315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2560458315
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3596084119
Short name T336
Test name
Test status
Simulation time 543469883505 ps
CPU time 141.73 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:21:06 PM PDT 24
Peak memory 182948 kb
Host smart-f537f455-a588-4a6a-a2f1-8827be08d034
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596084119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3596084119
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.1506354948
Short name T308
Test name
Test status
Simulation time 354126535468 ps
CPU time 240.79 seconds
Started Jun 02 02:18:51 PM PDT 24
Finished Jun 02 02:22:52 PM PDT 24
Peak memory 191192 kb
Host smart-9559f850-be7b-49e1-bb29-c4df09585f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506354948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1506354948
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.2262158107
Short name T114
Test name
Test status
Simulation time 158237367161 ps
CPU time 252.4 seconds
Started Jun 02 02:18:51 PM PDT 24
Finished Jun 02 02:23:04 PM PDT 24
Peak memory 191108 kb
Host smart-4dd4d2bd-ecf2-467d-9cf0-dadd71f5031b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262158107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2262158107
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2858410450
Short name T163
Test name
Test status
Simulation time 66047618324 ps
CPU time 102.94 seconds
Started Jun 02 02:19:22 PM PDT 24
Finished Jun 02 02:21:05 PM PDT 24
Peak memory 191188 kb
Host smart-8c04a669-db4d-4347-8ba1-777d5664ffe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858410450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2858410450
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.3030185882
Short name T279
Test name
Test status
Simulation time 300632603140 ps
CPU time 681.93 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:29:44 PM PDT 24
Peak memory 191124 kb
Host smart-7ac880a6-7798-44b3-bb14-20e887e9707f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030185882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3030185882
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2479256920
Short name T106
Test name
Test status
Simulation time 162951841 ps
CPU time 1.15 seconds
Started Jun 02 02:03:02 PM PDT 24
Finished Jun 02 02:03:04 PM PDT 24
Peak memory 195000 kb
Host smart-60e4ef10-8d7f-4160-a878-1d3477c2d783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479256920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2479256920
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.566857350
Short name T143
Test name
Test status
Simulation time 83294679898 ps
CPU time 253.3 seconds
Started Jun 02 02:18:13 PM PDT 24
Finished Jun 02 02:22:27 PM PDT 24
Peak memory 191184 kb
Host smart-fdafa552-aad2-46fd-9363-d47c72973ee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566857350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.566857350
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1647127255
Short name T299
Test name
Test status
Simulation time 292255695909 ps
CPU time 341.38 seconds
Started Jun 02 02:18:18 PM PDT 24
Finished Jun 02 02:24:00 PM PDT 24
Peak memory 191104 kb
Host smart-13c0d439-63b5-4151-bb2e-3825dbe760ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647127255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1647127255
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.975808220
Short name T288
Test name
Test status
Simulation time 64293675860 ps
CPU time 111.25 seconds
Started Jun 02 02:18:13 PM PDT 24
Finished Jun 02 02:20:05 PM PDT 24
Peak memory 182980 kb
Host smart-ee2331a3-c409-4547-b88a-4123c3134b94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975808220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.975808220
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/102.rv_timer_random.3563229792
Short name T233
Test name
Test status
Simulation time 203265936883 ps
CPU time 1246.17 seconds
Started Jun 02 02:19:53 PM PDT 24
Finished Jun 02 02:40:40 PM PDT 24
Peak memory 191196 kb
Host smart-edbd4c70-5a92-49b5-8433-42d36ada15b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563229792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3563229792
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3641367835
Short name T231
Test name
Test status
Simulation time 792600602625 ps
CPU time 357.13 seconds
Started Jun 02 02:20:01 PM PDT 24
Finished Jun 02 02:25:58 PM PDT 24
Peak memory 191196 kb
Host smart-707e19e0-546f-4b29-be77-defd32789d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641367835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3641367835
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.578578729
Short name T227
Test name
Test status
Simulation time 125537789703 ps
CPU time 195.16 seconds
Started Jun 02 02:18:22 PM PDT 24
Finished Jun 02 02:21:38 PM PDT 24
Peak memory 194728 kb
Host smart-63fd3239-d91f-4943-8732-99d3c9e84ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578578729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.578578729
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.1469700751
Short name T212
Test name
Test status
Simulation time 122042826170 ps
CPU time 218.5 seconds
Started Jun 02 02:20:08 PM PDT 24
Finished Jun 02 02:23:46 PM PDT 24
Peak memory 191140 kb
Host smart-9decbe7a-d2f8-436f-9fb8-8fcc50d521c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469700751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1469700751
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3450075494
Short name T273
Test name
Test status
Simulation time 225514475184 ps
CPU time 430.53 seconds
Started Jun 02 02:20:22 PM PDT 24
Finished Jun 02 02:27:33 PM PDT 24
Peak memory 191156 kb
Host smart-18a7e1ee-6a58-40a5-97d1-dd549e1746f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450075494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3450075494
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1627961928
Short name T246
Test name
Test status
Simulation time 167550382782 ps
CPU time 617.21 seconds
Started Jun 02 02:20:23 PM PDT 24
Finished Jun 02 02:30:40 PM PDT 24
Peak memory 192176 kb
Host smart-e0fb8e3d-67a4-4938-a005-44de75177505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627961928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1627961928
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3117594378
Short name T206
Test name
Test status
Simulation time 261069466337 ps
CPU time 378.25 seconds
Started Jun 02 02:20:25 PM PDT 24
Finished Jun 02 02:26:44 PM PDT 24
Peak memory 191128 kb
Host smart-33a2908d-5886-44b3-bfdd-c8d761ff6cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117594378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3117594378
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3574368534
Short name T341
Test name
Test status
Simulation time 73639055647 ps
CPU time 28.31 seconds
Started Jun 02 02:18:23 PM PDT 24
Finished Jun 02 02:18:52 PM PDT 24
Peak memory 182868 kb
Host smart-0646dcc0-73d8-4757-84ad-3a753b010a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574368534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3574368534
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3440643682
Short name T193
Test name
Test status
Simulation time 27771463520 ps
CPU time 21.14 seconds
Started Jun 02 02:20:33 PM PDT 24
Finished Jun 02 02:20:54 PM PDT 24
Peak memory 191116 kb
Host smart-6a66d4da-da67-4efe-9e9b-b9fe0027bb13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440643682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3440643682
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.571864490
Short name T41
Test name
Test status
Simulation time 70270357292 ps
CPU time 437.71 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:25:56 PM PDT 24
Peak memory 205864 kb
Host smart-895c96da-3696-402c-8698-82d46a3d110b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571864490 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.571864490
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.961628429
Short name T49
Test name
Test status
Simulation time 154691746884 ps
CPU time 649.64 seconds
Started Jun 02 02:20:39 PM PDT 24
Finished Jun 02 02:31:29 PM PDT 24
Peak memory 193968 kb
Host smart-a1bb96fb-77be-41c6-8988-ff7ecb046e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961628429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.961628429
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2176199607
Short name T46
Test name
Test status
Simulation time 618652623181 ps
CPU time 2057.59 seconds
Started Jun 02 02:20:47 PM PDT 24
Finished Jun 02 02:55:06 PM PDT 24
Peak memory 191180 kb
Host smart-de3d1cef-16eb-419f-a573-eee8e101b385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176199607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2176199607
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.229212571
Short name T258
Test name
Test status
Simulation time 70415507212 ps
CPU time 239.95 seconds
Started Jun 02 02:20:46 PM PDT 24
Finished Jun 02 02:24:46 PM PDT 24
Peak memory 191180 kb
Host smart-19e5e95f-bac6-4176-8456-8fecd5d81ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229212571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.229212571
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.1983739597
Short name T159
Test name
Test status
Simulation time 347728212130 ps
CPU time 639.95 seconds
Started Jun 02 02:18:23 PM PDT 24
Finished Jun 02 02:29:04 PM PDT 24
Peak memory 191192 kb
Host smart-de9d7ea2-2e81-4141-a661-de2dfa00d277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983739597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1983739597
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3124420946
Short name T196
Test name
Test status
Simulation time 75937958752 ps
CPU time 375.62 seconds
Started Jun 02 02:20:59 PM PDT 24
Finished Jun 02 02:27:14 PM PDT 24
Peak memory 191188 kb
Host smart-5e561345-dfe4-4abc-9682-1d9cc59b9eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124420946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3124420946
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.4080010264
Short name T166
Test name
Test status
Simulation time 71509135864 ps
CPU time 181.72 seconds
Started Jun 02 02:20:58 PM PDT 24
Finished Jun 02 02:24:00 PM PDT 24
Peak memory 191172 kb
Host smart-5fe455ad-bfc0-41c1-830f-4317b09a27bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080010264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4080010264
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4043064354
Short name T356
Test name
Test status
Simulation time 655893842309 ps
CPU time 651.93 seconds
Started Jun 02 02:21:09 PM PDT 24
Finished Jun 02 02:32:01 PM PDT 24
Peak memory 191188 kb
Host smart-2524ce6c-420b-4bff-978a-9514b58b2dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043064354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4043064354
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3781741528
Short name T243
Test name
Test status
Simulation time 266777662773 ps
CPU time 299.03 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:23:40 PM PDT 24
Peak memory 196604 kb
Host smart-dbd4e0ef-053e-4854-a695-bf0167c0a2a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781741528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3781741528
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.704458146
Short name T136
Test name
Test status
Simulation time 393561379624 ps
CPU time 566.96 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:28:21 PM PDT 24
Peak memory 191132 kb
Host smart-2b11233a-8090-4547-b2f1-ff2e0c46fc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704458146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
704458146
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.3529228901
Short name T321
Test name
Test status
Simulation time 243038333965 ps
CPU time 241.05 seconds
Started Jun 02 02:19:18 PM PDT 24
Finished Jun 02 02:23:20 PM PDT 24
Peak memory 191104 kb
Host smart-ef89f972-6bb1-48ce-899a-96fcead4b00a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529228901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3529228901
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.856167983
Short name T97
Test name
Test status
Simulation time 36993366 ps
CPU time 0.63 seconds
Started Jun 02 02:03:01 PM PDT 24
Finished Jun 02 02:03:02 PM PDT 24
Peak memory 182676 kb
Host smart-ca732955-38ce-434a-bab7-14448ff48584
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856167983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.856167983
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3304634290
Short name T467
Test name
Test status
Simulation time 75371036 ps
CPU time 1.5 seconds
Started Jun 02 02:03:01 PM PDT 24
Finished Jun 02 02:03:03 PM PDT 24
Peak memory 191080 kb
Host smart-490c285d-4b6a-4038-8a9e-a8f18db13a71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304634290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3304634290
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.5536345
Short name T521
Test name
Test status
Simulation time 20726772 ps
CPU time 0.59 seconds
Started Jun 02 02:03:10 PM PDT 24
Finished Jun 02 02:03:11 PM PDT 24
Peak memory 182680 kb
Host smart-30972193-48d0-41a2-a722-aa2ff3fb2ce9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5536345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_rese
t.5536345
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1347479800
Short name T570
Test name
Test status
Simulation time 28376554 ps
CPU time 0.87 seconds
Started Jun 02 02:03:02 PM PDT 24
Finished Jun 02 02:03:04 PM PDT 24
Peak memory 196220 kb
Host smart-6ae26f56-785c-43c2-82cb-059a79592183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347479800 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1347479800
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3702993452
Short name T56
Test name
Test status
Simulation time 38278673 ps
CPU time 0.55 seconds
Started Jun 02 02:03:06 PM PDT 24
Finished Jun 02 02:03:07 PM PDT 24
Peak memory 182396 kb
Host smart-d59c59c4-a92a-450f-a6a4-386bb1c66bb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702993452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3702993452
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2152526106
Short name T526
Test name
Test status
Simulation time 40174124 ps
CPU time 0.54 seconds
Started Jun 02 02:03:06 PM PDT 24
Finished Jun 02 02:03:07 PM PDT 24
Peak memory 182568 kb
Host smart-4253c567-db34-480f-b5fd-fea49a3ea1c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152526106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2152526106
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1950176885
Short name T483
Test name
Test status
Simulation time 56313094 ps
CPU time 0.66 seconds
Started Jun 02 02:03:03 PM PDT 24
Finished Jun 02 02:03:04 PM PDT 24
Peak memory 192148 kb
Host smart-08604ef3-6e01-4ba2-9bf7-715bbe48c80d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950176885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1950176885
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1603372355
Short name T523
Test name
Test status
Simulation time 131698970 ps
CPU time 2.21 seconds
Started Jun 02 02:03:03 PM PDT 24
Finished Jun 02 02:03:05 PM PDT 24
Peak memory 197628 kb
Host smart-3df446e8-0213-4994-a615-9a9b749149e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603372355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1603372355
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3563202792
Short name T559
Test name
Test status
Simulation time 76948553 ps
CPU time 0.79 seconds
Started Jun 02 02:03:05 PM PDT 24
Finished Jun 02 02:03:06 PM PDT 24
Peak memory 193592 kb
Host smart-36a1d5e5-7295-4656-ab90-a5d782dcd45a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563202792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3563202792
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.866597644
Short name T532
Test name
Test status
Simulation time 39077752 ps
CPU time 0.65 seconds
Started Jun 02 02:03:06 PM PDT 24
Finished Jun 02 02:03:07 PM PDT 24
Peak memory 191908 kb
Host smart-b4d58044-61a7-4337-adb2-b33ce9e19f8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866597644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.866597644
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2654084356
Short name T503
Test name
Test status
Simulation time 169988371 ps
CPU time 2.35 seconds
Started Jun 02 02:03:05 PM PDT 24
Finished Jun 02 02:03:07 PM PDT 24
Peak memory 193880 kb
Host smart-8b2dc9f5-130a-4075-80ce-5d26e8f6185e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654084356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2654084356
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.831961320
Short name T499
Test name
Test status
Simulation time 82491300 ps
CPU time 0.58 seconds
Started Jun 02 02:03:02 PM PDT 24
Finished Jun 02 02:03:03 PM PDT 24
Peak memory 182288 kb
Host smart-15891a25-68f8-45a4-ab52-dab51681bd99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831961320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.831961320
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.410657065
Short name T575
Test name
Test status
Simulation time 104612845 ps
CPU time 0.7 seconds
Started Jun 02 02:03:08 PM PDT 24
Finished Jun 02 02:03:09 PM PDT 24
Peak memory 194680 kb
Host smart-79c08b8e-3d15-4263-8e76-76185c3ad139
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410657065 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.410657065
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2787633477
Short name T80
Test name
Test status
Simulation time 51898789 ps
CPU time 0.62 seconds
Started Jun 02 02:03:04 PM PDT 24
Finished Jun 02 02:03:05 PM PDT 24
Peak memory 182680 kb
Host smart-f82d3df3-54bc-4788-94e3-89e4fd617e07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787633477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2787633477
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3900893379
Short name T471
Test name
Test status
Simulation time 12078650 ps
CPU time 0.54 seconds
Started Jun 02 02:03:02 PM PDT 24
Finished Jun 02 02:03:02 PM PDT 24
Peak memory 182616 kb
Host smart-c3c65bd6-cc20-4c86-804a-1ab15ddeb1da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900893379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3900893379
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2330334553
Short name T528
Test name
Test status
Simulation time 327606428 ps
CPU time 1.91 seconds
Started Jun 02 02:03:05 PM PDT 24
Finished Jun 02 02:03:07 PM PDT 24
Peak memory 197676 kb
Host smart-7945bcdc-cbbc-413e-bc0a-030ce088048b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330334553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2330334553
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2499349882
Short name T476
Test name
Test status
Simulation time 23194444 ps
CPU time 1.02 seconds
Started Jun 02 02:03:18 PM PDT 24
Finished Jun 02 02:03:20 PM PDT 24
Peak memory 197364 kb
Host smart-797acc04-a421-439a-9ed0-51e3ef58aa95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499349882 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2499349882
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3915690871
Short name T91
Test name
Test status
Simulation time 16238646 ps
CPU time 0.54 seconds
Started Jun 02 02:03:26 PM PDT 24
Finished Jun 02 02:03:27 PM PDT 24
Peak memory 182744 kb
Host smart-548c735f-2399-4aa8-bf52-b4ed0c5c9c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915690871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3915690871
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3904443040
Short name T525
Test name
Test status
Simulation time 13196718 ps
CPU time 0.55 seconds
Started Jun 02 02:03:18 PM PDT 24
Finished Jun 02 02:03:19 PM PDT 24
Peak memory 182080 kb
Host smart-4e719c35-7d9a-49ec-b8de-457602463658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904443040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3904443040
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2612993922
Short name T101
Test name
Test status
Simulation time 37842349 ps
CPU time 0.87 seconds
Started Jun 02 02:03:22 PM PDT 24
Finished Jun 02 02:03:23 PM PDT 24
Peak memory 193312 kb
Host smart-c48e0378-f5ab-4ea2-9db0-d7ed51361664
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612993922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2612993922
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2556272424
Short name T509
Test name
Test status
Simulation time 262161484 ps
CPU time 1.04 seconds
Started Jun 02 02:03:19 PM PDT 24
Finished Jun 02 02:03:20 PM PDT 24
Peak memory 197068 kb
Host smart-0bd0dad2-3f00-40d7-a864-8cdabe636841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556272424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2556272424
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2358000712
Short name T469
Test name
Test status
Simulation time 113102793 ps
CPU time 1.28 seconds
Started Jun 02 02:03:19 PM PDT 24
Finished Jun 02 02:03:21 PM PDT 24
Peak memory 194548 kb
Host smart-a2cce7f3-202d-4d8f-911d-351a8080cc0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358000712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2358000712
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.630458021
Short name T524
Test name
Test status
Simulation time 23367624 ps
CPU time 0.89 seconds
Started Jun 02 02:03:21 PM PDT 24
Finished Jun 02 02:03:22 PM PDT 24
Peak memory 197116 kb
Host smart-4ee62c9f-74a1-4112-9eca-b6a0f98834c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630458021 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.630458021
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.727550383
Short name T96
Test name
Test status
Simulation time 17795399 ps
CPU time 0.59 seconds
Started Jun 02 02:03:22 PM PDT 24
Finished Jun 02 02:03:23 PM PDT 24
Peak memory 182696 kb
Host smart-c82b9763-111f-4924-81b5-7076e1e6a17e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727550383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.727550383
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1679049596
Short name T455
Test name
Test status
Simulation time 21500421 ps
CPU time 0.52 seconds
Started Jun 02 02:03:21 PM PDT 24
Finished Jun 02 02:03:22 PM PDT 24
Peak memory 182112 kb
Host smart-86244b5a-1bfe-4601-bd76-79adc7b59210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679049596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1679049596
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1714245279
Short name T35
Test name
Test status
Simulation time 47806566 ps
CPU time 0.69 seconds
Started Jun 02 02:03:18 PM PDT 24
Finished Jun 02 02:03:19 PM PDT 24
Peak memory 192284 kb
Host smart-ab31a633-ab4f-4e21-874f-5caa3828baaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714245279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1714245279
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1509633323
Short name T551
Test name
Test status
Simulation time 86946767 ps
CPU time 1.9 seconds
Started Jun 02 02:03:20 PM PDT 24
Finished Jun 02 02:03:23 PM PDT 24
Peak memory 197572 kb
Host smart-64602f84-4d5f-47ad-8038-398432acac33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509633323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1509633323
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.408411170
Short name T33
Test name
Test status
Simulation time 166488416 ps
CPU time 0.83 seconds
Started Jun 02 02:03:21 PM PDT 24
Finished Jun 02 02:03:22 PM PDT 24
Peak memory 193716 kb
Host smart-ed386a78-4da8-4b9c-a83d-3ab634549ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408411170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.408411170
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.379302891
Short name T555
Test name
Test status
Simulation time 133823805 ps
CPU time 1.47 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:31 PM PDT 24
Peak memory 197684 kb
Host smart-35531ef7-d574-4a02-bfea-d5f5bf9b278a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379302891 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.379302891
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2608879542
Short name T98
Test name
Test status
Simulation time 34735895 ps
CPU time 0.57 seconds
Started Jun 02 02:03:25 PM PDT 24
Finished Jun 02 02:03:26 PM PDT 24
Peak memory 182704 kb
Host smart-af845a3c-63c1-4756-81d0-fe246145fedf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608879542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2608879542
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1523445699
Short name T546
Test name
Test status
Simulation time 36858036 ps
CPU time 0.53 seconds
Started Jun 02 02:03:18 PM PDT 24
Finished Jun 02 02:03:19 PM PDT 24
Peak memory 182696 kb
Host smart-378734d3-2004-4a02-8245-c40f9c4ca52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523445699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1523445699
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3085596305
Short name T538
Test name
Test status
Simulation time 67117269 ps
CPU time 0.8 seconds
Started Jun 02 02:03:26 PM PDT 24
Finished Jun 02 02:03:27 PM PDT 24
Peak memory 191656 kb
Host smart-de920551-7443-4e37-a3ac-5a382c9cbcb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085596305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3085596305
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.305583072
Short name T516
Test name
Test status
Simulation time 140273023 ps
CPU time 2.51 seconds
Started Jun 02 02:03:19 PM PDT 24
Finished Jun 02 02:03:22 PM PDT 24
Peak memory 197652 kb
Host smart-5802ac3f-2dfe-484d-8db7-4d5f308c50a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305583072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.305583072
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3160190575
Short name T474
Test name
Test status
Simulation time 148848555 ps
CPU time 1.14 seconds
Started Jun 02 02:03:20 PM PDT 24
Finished Jun 02 02:03:21 PM PDT 24
Peak memory 195456 kb
Host smart-0314782c-3e95-4cbe-8e9f-48a451e9a631
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160190575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3160190575
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2838591646
Short name T574
Test name
Test status
Simulation time 50671732 ps
CPU time 0.64 seconds
Started Jun 02 02:03:24 PM PDT 24
Finished Jun 02 02:03:25 PM PDT 24
Peak memory 193400 kb
Host smart-4b0efd42-54e7-44d6-abcb-698803f1ae48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838591646 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2838591646
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.893376236
Short name T482
Test name
Test status
Simulation time 14078861 ps
CPU time 0.54 seconds
Started Jun 02 02:03:26 PM PDT 24
Finished Jun 02 02:03:27 PM PDT 24
Peak memory 182444 kb
Host smart-e02b838d-d6ba-4c2e-a774-3441c70fa283
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893376236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.893376236
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4002699121
Short name T566
Test name
Test status
Simulation time 72936735 ps
CPU time 0.58 seconds
Started Jun 02 02:03:23 PM PDT 24
Finished Jun 02 02:03:24 PM PDT 24
Peak memory 182692 kb
Host smart-5b2ab63d-23a6-4cb8-ba9c-dac4c41077f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002699121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.4002699121
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3000260049
Short name T75
Test name
Test status
Simulation time 121448619 ps
CPU time 0.71 seconds
Started Jun 02 02:03:23 PM PDT 24
Finished Jun 02 02:03:24 PM PDT 24
Peak memory 191720 kb
Host smart-3bcbe58a-83ba-4198-a174-ab7ce247485d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000260049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3000260049
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1561968313
Short name T541
Test name
Test status
Simulation time 62999409 ps
CPU time 1.25 seconds
Started Jun 02 02:03:27 PM PDT 24
Finished Jun 02 02:03:29 PM PDT 24
Peak memory 197612 kb
Host smart-bee15005-b9c3-482d-9455-375768d97537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561968313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1561968313
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1836752476
Short name T567
Test name
Test status
Simulation time 185772758 ps
CPU time 0.83 seconds
Started Jun 02 02:03:24 PM PDT 24
Finished Jun 02 02:03:25 PM PDT 24
Peak memory 183252 kb
Host smart-c0d151ef-2dd4-4c50-9519-26afbe507a49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836752476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1836752476
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.524912299
Short name T536
Test name
Test status
Simulation time 135716107 ps
CPU time 0.87 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:30 PM PDT 24
Peak memory 197348 kb
Host smart-b8c9e383-0623-4578-9987-06ae155108c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524912299 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.524912299
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3448906475
Short name T468
Test name
Test status
Simulation time 17445624 ps
CPU time 0.58 seconds
Started Jun 02 02:03:24 PM PDT 24
Finished Jun 02 02:03:25 PM PDT 24
Peak memory 182704 kb
Host smart-79e828ac-02d6-47e2-bc71-33a72f418f08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448906475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3448906475
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3173921465
Short name T488
Test name
Test status
Simulation time 166461701 ps
CPU time 0.52 seconds
Started Jun 02 02:03:25 PM PDT 24
Finished Jun 02 02:03:25 PM PDT 24
Peak memory 182048 kb
Host smart-2b5953ac-5ba1-44cd-ae8b-0286f40f6736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173921465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3173921465
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4293819663
Short name T544
Test name
Test status
Simulation time 20344501 ps
CPU time 0.64 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:30 PM PDT 24
Peak memory 192124 kb
Host smart-870697a7-2ff1-4d0e-a844-5e3bacfe26ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293819663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.4293819663
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3732051725
Short name T535
Test name
Test status
Simulation time 376750001 ps
CPU time 3.07 seconds
Started Jun 02 02:03:25 PM PDT 24
Finished Jun 02 02:03:28 PM PDT 24
Peak memory 197632 kb
Host smart-6ff6cc02-23b6-4422-a96d-d2099a56a054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732051725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3732051725
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1310126559
Short name T459
Test name
Test status
Simulation time 63563113 ps
CPU time 0.85 seconds
Started Jun 02 02:03:24 PM PDT 24
Finished Jun 02 02:03:25 PM PDT 24
Peak memory 193604 kb
Host smart-7cc0aa1b-2dec-45d2-b715-f489382a00ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310126559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1310126559
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1962139458
Short name T540
Test name
Test status
Simulation time 16412579 ps
CPU time 0.63 seconds
Started Jun 02 02:03:33 PM PDT 24
Finished Jun 02 02:03:34 PM PDT 24
Peak memory 193092 kb
Host smart-182e9c8a-a018-4706-a425-16d3be29ceea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962139458 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1962139458
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3011215439
Short name T93
Test name
Test status
Simulation time 40676783 ps
CPU time 0.59 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:30 PM PDT 24
Peak memory 191892 kb
Host smart-300ee552-fb35-41d3-9f5b-f8d45663a5b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011215439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3011215439
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.363115278
Short name T477
Test name
Test status
Simulation time 28504050 ps
CPU time 0.61 seconds
Started Jun 02 02:03:28 PM PDT 24
Finished Jun 02 02:03:29 PM PDT 24
Peak memory 182588 kb
Host smart-e245fd76-fcc8-4a2e-a3e0-cb7b054d0733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363115278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.363115278
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.302690667
Short name T568
Test name
Test status
Simulation time 29744422 ps
CPU time 0.67 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:30 PM PDT 24
Peak memory 191592 kb
Host smart-7e37354b-82ca-4c7b-9a1d-9a7330094bf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302690667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.302690667
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.329769901
Short name T451
Test name
Test status
Simulation time 21724899 ps
CPU time 1.1 seconds
Started Jun 02 02:03:26 PM PDT 24
Finished Jun 02 02:03:27 PM PDT 24
Peak memory 197124 kb
Host smart-e89c94ce-43a4-4a79-a028-798e26083cd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329769901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.329769901
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1061397144
Short name T527
Test name
Test status
Simulation time 40219505 ps
CPU time 0.83 seconds
Started Jun 02 02:03:28 PM PDT 24
Finished Jun 02 02:03:29 PM PDT 24
Peak memory 193624 kb
Host smart-ec1e00d5-39a0-4029-9e31-481fd4cddf9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061397144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1061397144
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.678906086
Short name T490
Test name
Test status
Simulation time 32321845 ps
CPU time 1.34 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:31 PM PDT 24
Peak memory 197608 kb
Host smart-6a54a176-282d-42ba-afdc-db46e89924e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678906086 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.678906086
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.948995322
Short name T94
Test name
Test status
Simulation time 15334363 ps
CPU time 0.61 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:30 PM PDT 24
Peak memory 182736 kb
Host smart-e749a1ca-f5ae-44bd-9a73-6f0109d71e9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948995322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.948995322
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2280981914
Short name T565
Test name
Test status
Simulation time 68138187 ps
CPU time 0.59 seconds
Started Jun 02 02:03:30 PM PDT 24
Finished Jun 02 02:03:31 PM PDT 24
Peak memory 182720 kb
Host smart-c80413d3-d993-4cb4-a397-85e5ef2e4165
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280981914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2280981914
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3732635042
Short name T547
Test name
Test status
Simulation time 74670607 ps
CPU time 0.64 seconds
Started Jun 02 02:03:31 PM PDT 24
Finished Jun 02 02:03:32 PM PDT 24
Peak memory 192192 kb
Host smart-cf7f1f3a-a67c-4cea-80e1-0c4d6b5424be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732635042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3732635042
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1920555147
Short name T553
Test name
Test status
Simulation time 871792104 ps
CPU time 2.84 seconds
Started Jun 02 02:03:28 PM PDT 24
Finished Jun 02 02:03:32 PM PDT 24
Peak memory 197652 kb
Host smart-9818294c-49e4-40da-ac8b-eb0cbab1f675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920555147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1920555147
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.832965063
Short name T502
Test name
Test status
Simulation time 139562632 ps
CPU time 0.83 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:31 PM PDT 24
Peak memory 193236 kb
Host smart-ed3262d4-c5ad-42b7-b875-93718b0ed0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832965063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.832965063
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2199533996
Short name T501
Test name
Test status
Simulation time 30534182 ps
CPU time 0.79 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:31 PM PDT 24
Peak memory 195648 kb
Host smart-5078296a-b850-48ad-b75e-8021673145f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199533996 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2199533996
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1200098123
Short name T512
Test name
Test status
Simulation time 31284296 ps
CPU time 0.53 seconds
Started Jun 02 02:03:28 PM PDT 24
Finished Jun 02 02:03:29 PM PDT 24
Peak memory 182384 kb
Host smart-8858a3da-8422-497c-8632-aec6dbf4a88d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200098123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1200098123
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3037409208
Short name T465
Test name
Test status
Simulation time 53243197 ps
CPU time 0.59 seconds
Started Jun 02 02:03:29 PM PDT 24
Finished Jun 02 02:03:30 PM PDT 24
Peak memory 182548 kb
Host smart-ec2e3bce-9dfa-4f3f-baa8-7dd80c3f05cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037409208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3037409208
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2794101669
Short name T492
Test name
Test status
Simulation time 22588531 ps
CPU time 0.78 seconds
Started Jun 02 02:03:30 PM PDT 24
Finished Jun 02 02:03:31 PM PDT 24
Peak memory 191724 kb
Host smart-ca6a0b1b-a5be-4ea1-92ab-5553b416c1b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794101669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2794101669
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4017550560
Short name T505
Test name
Test status
Simulation time 22596104 ps
CPU time 1.18 seconds
Started Jun 02 02:03:31 PM PDT 24
Finished Jun 02 02:03:33 PM PDT 24
Peak memory 197644 kb
Host smart-aa62f877-2cc6-40b8-8e97-0ad82b71cd7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017550560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4017550560
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.586036682
Short name T107
Test name
Test status
Simulation time 71214521 ps
CPU time 1.13 seconds
Started Jun 02 02:03:26 PM PDT 24
Finished Jun 02 02:03:28 PM PDT 24
Peak memory 195228 kb
Host smart-40e3fe01-3a01-48ed-b6bb-bf6ba176a92a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586036682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.586036682
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4059767420
Short name T520
Test name
Test status
Simulation time 64220701 ps
CPU time 0.93 seconds
Started Jun 02 02:03:35 PM PDT 24
Finished Jun 02 02:03:37 PM PDT 24
Peak memory 197152 kb
Host smart-d9e298e4-b533-4d8b-ab56-35fc5e6e7492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059767420 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4059767420
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4005372541
Short name T550
Test name
Test status
Simulation time 25910080 ps
CPU time 0.57 seconds
Started Jun 02 02:03:37 PM PDT 24
Finished Jun 02 02:03:38 PM PDT 24
Peak memory 182756 kb
Host smart-5ac114e0-78e2-42a0-824a-e19f20490878
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005372541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.4005372541
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1803568397
Short name T475
Test name
Test status
Simulation time 24453121 ps
CPU time 0.54 seconds
Started Jun 02 02:03:33 PM PDT 24
Finished Jun 02 02:03:34 PM PDT 24
Peak memory 182096 kb
Host smart-a2c4755b-532f-420f-b755-f031b08652f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803568397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1803568397
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.613365605
Short name T562
Test name
Test status
Simulation time 61745169 ps
CPU time 0.7 seconds
Started Jun 02 02:03:34 PM PDT 24
Finished Jun 02 02:03:35 PM PDT 24
Peak memory 191844 kb
Host smart-d061396f-b0d1-427d-b341-5be5cf9b307f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613365605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.613365605
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1167226240
Short name T539
Test name
Test status
Simulation time 20646004 ps
CPU time 1.01 seconds
Started Jun 02 02:03:35 PM PDT 24
Finished Jun 02 02:03:36 PM PDT 24
Peak memory 196612 kb
Host smart-0153cc4e-b32f-4b40-9471-afc85120ddf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167226240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1167226240
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2475938472
Short name T484
Test name
Test status
Simulation time 264773014 ps
CPU time 0.89 seconds
Started Jun 02 02:03:35 PM PDT 24
Finished Jun 02 02:03:36 PM PDT 24
Peak memory 192564 kb
Host smart-d8cdb70e-cbb6-422c-ace6-d6ee95711da7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475938472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2475938472
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3538783071
Short name T479
Test name
Test status
Simulation time 104417402 ps
CPU time 0.73 seconds
Started Jun 02 02:03:35 PM PDT 24
Finished Jun 02 02:03:37 PM PDT 24
Peak memory 195656 kb
Host smart-d1cfcbd8-bd13-420b-9e32-d101bc2d88b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538783071 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3538783071
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1743642973
Short name T76
Test name
Test status
Simulation time 38761657 ps
CPU time 0.57 seconds
Started Jun 02 02:03:36 PM PDT 24
Finished Jun 02 02:03:37 PM PDT 24
Peak memory 182556 kb
Host smart-26365012-71da-4674-abbc-2e663ecc0f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743642973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1743642973
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2644721422
Short name T514
Test name
Test status
Simulation time 87956254 ps
CPU time 0.57 seconds
Started Jun 02 02:03:38 PM PDT 24
Finished Jun 02 02:03:39 PM PDT 24
Peak memory 182128 kb
Host smart-4094f7f6-2486-429f-a6e6-ec08e7bfe48b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644721422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2644721422
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3916439092
Short name T543
Test name
Test status
Simulation time 37157361 ps
CPU time 0.8 seconds
Started Jun 02 02:03:37 PM PDT 24
Finished Jun 02 02:03:38 PM PDT 24
Peak memory 193356 kb
Host smart-482e15fb-0621-4b13-8b81-de3baf80835b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916439092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3916439092
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1614998265
Short name T572
Test name
Test status
Simulation time 701246445 ps
CPU time 3.25 seconds
Started Jun 02 02:03:36 PM PDT 24
Finished Jun 02 02:03:40 PM PDT 24
Peak memory 197652 kb
Host smart-c6e77beb-e8c4-4e85-9da5-63202166ac32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614998265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1614998265
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3829413624
Short name T460
Test name
Test status
Simulation time 205242244 ps
CPU time 0.79 seconds
Started Jun 02 02:03:35 PM PDT 24
Finished Jun 02 02:03:36 PM PDT 24
Peak memory 193612 kb
Host smart-dfa3c2a6-224f-4859-b55a-b5ae732378c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829413624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3829413624
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4058209220
Short name T466
Test name
Test status
Simulation time 25985942 ps
CPU time 0.74 seconds
Started Jun 02 02:03:08 PM PDT 24
Finished Jun 02 02:03:09 PM PDT 24
Peak memory 182700 kb
Host smart-a8dd046d-4094-4099-8c0f-cbd83f288fe1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058209220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4058209220
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4202372552
Short name T511
Test name
Test status
Simulation time 204705184 ps
CPU time 1.7 seconds
Started Jun 02 02:03:09 PM PDT 24
Finished Jun 02 02:03:11 PM PDT 24
Peak memory 191172 kb
Host smart-7dc71eac-e1ef-4506-a59e-e06a654822ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202372552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4202372552
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2964258549
Short name T517
Test name
Test status
Simulation time 25356268 ps
CPU time 0.57 seconds
Started Jun 02 02:03:08 PM PDT 24
Finished Jun 02 02:03:09 PM PDT 24
Peak memory 182892 kb
Host smart-fd6a6754-595c-4497-8dab-ae4523ff0302
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964258549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2964258549
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2135226887
Short name T531
Test name
Test status
Simulation time 21116335 ps
CPU time 0.81 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 195608 kb
Host smart-5db0d767-e698-4ad3-b7ac-bb3f758eb347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135226887 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2135226887
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2472865532
Short name T542
Test name
Test status
Simulation time 13760840 ps
CPU time 0.63 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:14 PM PDT 24
Peak memory 182772 kb
Host smart-32d19735-41b3-4002-b439-166487b14154
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472865532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2472865532
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1265063772
Short name T533
Test name
Test status
Simulation time 45024551 ps
CPU time 0.56 seconds
Started Jun 02 02:03:07 PM PDT 24
Finished Jun 02 02:03:08 PM PDT 24
Peak memory 182628 kb
Host smart-a75dcb9b-a2fa-4625-a9a6-4a9609dde7b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265063772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1265063772
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2304059241
Short name T57
Test name
Test status
Simulation time 151664869 ps
CPU time 0.83 seconds
Started Jun 02 02:03:07 PM PDT 24
Finished Jun 02 02:03:08 PM PDT 24
Peak memory 193388 kb
Host smart-8542dfbe-f16e-469d-982a-dcc67b304c20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304059241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2304059241
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3569570587
Short name T530
Test name
Test status
Simulation time 54418977 ps
CPU time 1.28 seconds
Started Jun 02 02:03:15 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 197624 kb
Host smart-81522524-ff78-4e07-a9db-c5604111b566
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569570587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3569570587
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1608350285
Short name T34
Test name
Test status
Simulation time 223515426 ps
CPU time 0.84 seconds
Started Jun 02 02:03:09 PM PDT 24
Finished Jun 02 02:03:10 PM PDT 24
Peak memory 183228 kb
Host smart-074f5b91-2d8f-4907-8819-72687c7e6098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608350285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1608350285
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2151634287
Short name T576
Test name
Test status
Simulation time 14085550 ps
CPU time 0.58 seconds
Started Jun 02 02:03:36 PM PDT 24
Finished Jun 02 02:03:37 PM PDT 24
Peak memory 182580 kb
Host smart-87e9a684-e162-4a92-bd4d-35489ab94aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151634287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2151634287
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4175158903
Short name T489
Test name
Test status
Simulation time 14071632 ps
CPU time 0.6 seconds
Started Jun 02 02:03:34 PM PDT 24
Finished Jun 02 02:03:35 PM PDT 24
Peak memory 182092 kb
Host smart-a91acea7-8b9e-4287-89da-6bb10f508ccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175158903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.4175158903
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.899287941
Short name T560
Test name
Test status
Simulation time 17415900 ps
CPU time 0.59 seconds
Started Jun 02 02:03:35 PM PDT 24
Finished Jun 02 02:03:36 PM PDT 24
Peak memory 182648 kb
Host smart-a138f724-9d4d-4c03-a58b-2cb34eb88a5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899287941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.899287941
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1131251308
Short name T545
Test name
Test status
Simulation time 12656384 ps
CPU time 0.57 seconds
Started Jun 02 02:03:35 PM PDT 24
Finished Jun 02 02:03:36 PM PDT 24
Peak memory 182700 kb
Host smart-bbca50ab-3bb4-4e99-8b28-76aa58fc44c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131251308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1131251308
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2386789336
Short name T507
Test name
Test status
Simulation time 14312412 ps
CPU time 0.55 seconds
Started Jun 02 02:03:35 PM PDT 24
Finished Jun 02 02:03:36 PM PDT 24
Peak memory 182628 kb
Host smart-0fd6c4f4-90c6-4659-abbb-784a68ab4bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386789336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2386789336
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4042636814
Short name T494
Test name
Test status
Simulation time 48987708 ps
CPU time 0.55 seconds
Started Jun 02 02:03:34 PM PDT 24
Finished Jun 02 02:03:35 PM PDT 24
Peak memory 182048 kb
Host smart-52dfc302-a754-4e70-9d42-0fe4316b5343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042636814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4042636814
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2168182150
Short name T487
Test name
Test status
Simulation time 25405024 ps
CPU time 0.61 seconds
Started Jun 02 02:03:36 PM PDT 24
Finished Jun 02 02:03:37 PM PDT 24
Peak memory 182604 kb
Host smart-8c28ee94-0f6d-45de-98e6-4200276010d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168182150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2168182150
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3218592306
Short name T534
Test name
Test status
Simulation time 12960377 ps
CPU time 0.57 seconds
Started Jun 02 02:03:36 PM PDT 24
Finished Jun 02 02:03:36 PM PDT 24
Peak memory 182128 kb
Host smart-cc8a0c2b-a21f-4ca3-88c3-ea8d4a22a03b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218592306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3218592306
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1178587853
Short name T515
Test name
Test status
Simulation time 39437472 ps
CPU time 0.55 seconds
Started Jun 02 02:03:34 PM PDT 24
Finished Jun 02 02:03:35 PM PDT 24
Peak memory 182296 kb
Host smart-f203f1a0-af05-431d-bce4-3bd8c57f9a07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178587853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1178587853
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1322186412
Short name T556
Test name
Test status
Simulation time 45215659 ps
CPU time 0.61 seconds
Started Jun 02 02:03:36 PM PDT 24
Finished Jun 02 02:03:37 PM PDT 24
Peak memory 182672 kb
Host smart-0cd05253-0bfb-42cb-afe5-433ab195649c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322186412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1322186412
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1061389809
Short name T81
Test name
Test status
Simulation time 45166943 ps
CPU time 0.73 seconds
Started Jun 02 02:03:09 PM PDT 24
Finished Jun 02 02:03:10 PM PDT 24
Peak memory 182752 kb
Host smart-9dac1336-354e-48ad-84f4-c58678439fbe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061389809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1061389809
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1032496296
Short name T95
Test name
Test status
Simulation time 1678608416 ps
CPU time 3.75 seconds
Started Jun 02 02:03:08 PM PDT 24
Finished Jun 02 02:03:12 PM PDT 24
Peak memory 192544 kb
Host smart-46a61cda-c1da-473a-a681-defc6f722c9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032496296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1032496296
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4276481875
Short name T79
Test name
Test status
Simulation time 20696784 ps
CPU time 0.64 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 182772 kb
Host smart-a0133abd-078b-44a1-b628-e3e3c61d389d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276481875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4276481875
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4283300549
Short name T493
Test name
Test status
Simulation time 20695432 ps
CPU time 0.69 seconds
Started Jun 02 02:03:07 PM PDT 24
Finished Jun 02 02:03:09 PM PDT 24
Peak memory 194380 kb
Host smart-b5aedb36-f335-40c2-b4be-485c6022080f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283300549 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4283300549
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.658962200
Short name T573
Test name
Test status
Simulation time 123156034 ps
CPU time 0.56 seconds
Started Jun 02 02:03:15 PM PDT 24
Finished Jun 02 02:03:16 PM PDT 24
Peak memory 182744 kb
Host smart-951ac8c3-a5c8-4316-8fb6-6d405caec5e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658962200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.658962200
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3261947719
Short name T456
Test name
Test status
Simulation time 14427672 ps
CPU time 0.57 seconds
Started Jun 02 02:03:09 PM PDT 24
Finished Jun 02 02:03:10 PM PDT 24
Peak memory 182708 kb
Host smart-ccfb044b-1d57-4926-9927-e177903e1085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261947719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3261947719
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3111512720
Short name T100
Test name
Test status
Simulation time 23810858 ps
CPU time 0.66 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 192196 kb
Host smart-742b81ed-6b2c-442a-be92-d400d08d1216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111512720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3111512720
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2727662933
Short name T472
Test name
Test status
Simulation time 72617586 ps
CPU time 1.18 seconds
Started Jun 02 02:03:07 PM PDT 24
Finished Jun 02 02:03:09 PM PDT 24
Peak memory 197640 kb
Host smart-113ab6cc-a248-4196-b0fa-9dddebd590fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727662933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2727662933
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.442189793
Short name T105
Test name
Test status
Simulation time 89849291 ps
CPU time 1.09 seconds
Started Jun 02 02:03:06 PM PDT 24
Finished Jun 02 02:03:08 PM PDT 24
Peak memory 195060 kb
Host smart-e12b1e7b-6dd7-47c7-9db9-4169a1e3648f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442189793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.442189793
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2989646423
Short name T557
Test name
Test status
Simulation time 47028349 ps
CPU time 0.6 seconds
Started Jun 02 02:03:41 PM PDT 24
Finished Jun 02 02:03:42 PM PDT 24
Peak memory 182696 kb
Host smart-60ecf9d7-131b-40c7-bdda-ce617635278a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989646423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2989646423
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3173965909
Short name T454
Test name
Test status
Simulation time 33025327 ps
CPU time 0.56 seconds
Started Jun 02 02:03:38 PM PDT 24
Finished Jun 02 02:03:39 PM PDT 24
Peak memory 182544 kb
Host smart-56d7253a-2fc3-4f6b-91f0-4014bf1506b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173965909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3173965909
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1938213768
Short name T579
Test name
Test status
Simulation time 34734649 ps
CPU time 0.57 seconds
Started Jun 02 02:03:40 PM PDT 24
Finished Jun 02 02:03:41 PM PDT 24
Peak memory 182644 kb
Host smart-b8ed333b-73b5-4731-aedf-15074c25a467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938213768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1938213768
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2813086107
Short name T458
Test name
Test status
Simulation time 27079872 ps
CPU time 0.55 seconds
Started Jun 02 02:03:39 PM PDT 24
Finished Jun 02 02:03:40 PM PDT 24
Peak memory 182724 kb
Host smart-b6ed7e78-736b-49ed-bce1-7c5a79bba43d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813086107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2813086107
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2907643061
Short name T486
Test name
Test status
Simulation time 25486584 ps
CPU time 0.54 seconds
Started Jun 02 02:03:42 PM PDT 24
Finished Jun 02 02:03:43 PM PDT 24
Peak memory 182716 kb
Host smart-cf7ed3f5-57f9-4784-a516-b61bd6ddbcd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907643061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2907643061
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2569890315
Short name T452
Test name
Test status
Simulation time 13872633 ps
CPU time 0.59 seconds
Started Jun 02 02:03:41 PM PDT 24
Finished Jun 02 02:03:42 PM PDT 24
Peak memory 182632 kb
Host smart-73099351-aeb6-461f-ad43-dc2ce2b705e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569890315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2569890315
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2769943172
Short name T496
Test name
Test status
Simulation time 24659052 ps
CPU time 0.52 seconds
Started Jun 02 02:03:40 PM PDT 24
Finished Jun 02 02:03:41 PM PDT 24
Peak memory 182064 kb
Host smart-ed06f4b1-0291-4a2b-a738-d919cf56403d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769943172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2769943172
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4098881147
Short name T457
Test name
Test status
Simulation time 12790556 ps
CPU time 0.54 seconds
Started Jun 02 02:03:39 PM PDT 24
Finished Jun 02 02:03:41 PM PDT 24
Peak memory 182068 kb
Host smart-19d45b61-e260-42d9-8487-4c58ce96fae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098881147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4098881147
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2309592162
Short name T537
Test name
Test status
Simulation time 13832982 ps
CPU time 0.56 seconds
Started Jun 02 02:03:43 PM PDT 24
Finished Jun 02 02:03:44 PM PDT 24
Peak memory 182716 kb
Host smart-cdf306e4-66e8-47c3-9fe1-25a71b515b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309592162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2309592162
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.845996402
Short name T510
Test name
Test status
Simulation time 15601270 ps
CPU time 0.58 seconds
Started Jun 02 02:03:40 PM PDT 24
Finished Jun 02 02:03:41 PM PDT 24
Peak memory 182664 kb
Host smart-76df8df8-33c9-4f74-ab40-76fff77091d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845996402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.845996402
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3078319824
Short name T77
Test name
Test status
Simulation time 97931090 ps
CPU time 0.73 seconds
Started Jun 02 02:03:14 PM PDT 24
Finished Jun 02 02:03:16 PM PDT 24
Peak memory 192592 kb
Host smart-1765c818-f277-4110-a9ba-664eba70380d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078319824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3078319824
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2032426129
Short name T78
Test name
Test status
Simulation time 429659413 ps
CPU time 3.66 seconds
Started Jun 02 02:03:07 PM PDT 24
Finished Jun 02 02:03:11 PM PDT 24
Peak memory 192464 kb
Host smart-3caa6716-7af4-41e1-ba64-ff5904e2207f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032426129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2032426129
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2083196144
Short name T548
Test name
Test status
Simulation time 65681465 ps
CPU time 0.53 seconds
Started Jun 02 02:03:15 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 182216 kb
Host smart-b64ad175-7a1c-4201-9d1a-f49f52b454e5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083196144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2083196144
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3852635292
Short name T453
Test name
Test status
Simulation time 79801630 ps
CPU time 0.88 seconds
Started Jun 02 02:03:11 PM PDT 24
Finished Jun 02 02:03:12 PM PDT 24
Peak memory 197456 kb
Host smart-913339ac-e2ff-46c5-805a-93bb64c3e315
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852635292 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3852635292
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2795138090
Short name T102
Test name
Test status
Simulation time 11366157 ps
CPU time 0.58 seconds
Started Jun 02 02:03:07 PM PDT 24
Finished Jun 02 02:03:09 PM PDT 24
Peak memory 182756 kb
Host smart-c329652c-774d-4447-9af9-021667d2b3c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795138090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2795138090
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2854576817
Short name T461
Test name
Test status
Simulation time 11693974 ps
CPU time 0.55 seconds
Started Jun 02 02:03:09 PM PDT 24
Finished Jun 02 02:03:10 PM PDT 24
Peak memory 182072 kb
Host smart-f67a14da-5fd1-4523-b162-3d41d57cdaa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854576817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2854576817
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3507810011
Short name T580
Test name
Test status
Simulation time 33975763 ps
CPU time 0.79 seconds
Started Jun 02 02:03:12 PM PDT 24
Finished Jun 02 02:03:14 PM PDT 24
Peak memory 194512 kb
Host smart-088cad89-ead1-46b9-8c8d-11da3726a828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507810011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3507810011
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4138583474
Short name T518
Test name
Test status
Simulation time 321002971 ps
CPU time 1.49 seconds
Started Jun 02 02:03:07 PM PDT 24
Finished Jun 02 02:03:09 PM PDT 24
Peak memory 191408 kb
Host smart-f4b038d5-328f-46e1-9adb-1106bbe74f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138583474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.4138583474
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2912769377
Short name T104
Test name
Test status
Simulation time 69617814 ps
CPU time 1.14 seconds
Started Jun 02 02:03:09 PM PDT 24
Finished Jun 02 02:03:11 PM PDT 24
Peak memory 195208 kb
Host smart-87f53a35-81e5-46a8-a1da-13ffa64afe92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912769377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2912769377
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.229690684
Short name T450
Test name
Test status
Simulation time 39213577 ps
CPU time 0.57 seconds
Started Jun 02 02:03:41 PM PDT 24
Finished Jun 02 02:03:42 PM PDT 24
Peak memory 182556 kb
Host smart-af4ec303-69c5-4edf-8b6a-f22a8e280d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229690684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.229690684
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3339139848
Short name T485
Test name
Test status
Simulation time 27878873 ps
CPU time 0.54 seconds
Started Jun 02 02:03:40 PM PDT 24
Finished Jun 02 02:03:41 PM PDT 24
Peak memory 182584 kb
Host smart-e49e2dce-f587-499a-a0fa-0f868494babc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339139848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3339139848
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1224030486
Short name T500
Test name
Test status
Simulation time 45916011 ps
CPU time 0.55 seconds
Started Jun 02 02:03:43 PM PDT 24
Finished Jun 02 02:03:44 PM PDT 24
Peak memory 182524 kb
Host smart-b81c6041-0071-45c4-a368-c74671674c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224030486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1224030486
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2280650797
Short name T480
Test name
Test status
Simulation time 41960958 ps
CPU time 0.59 seconds
Started Jun 02 02:03:40 PM PDT 24
Finished Jun 02 02:03:41 PM PDT 24
Peak memory 182640 kb
Host smart-160a93f2-38aa-4774-a6da-c515d06d71d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280650797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2280650797
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2226724870
Short name T569
Test name
Test status
Simulation time 17924547 ps
CPU time 0.6 seconds
Started Jun 02 02:03:39 PM PDT 24
Finished Jun 02 02:03:40 PM PDT 24
Peak memory 182640 kb
Host smart-5331999f-402d-4b35-a503-65a7316e5f8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226724870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2226724870
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1152952577
Short name T558
Test name
Test status
Simulation time 117358845 ps
CPU time 0.57 seconds
Started Jun 02 02:03:39 PM PDT 24
Finished Jun 02 02:03:40 PM PDT 24
Peak memory 182600 kb
Host smart-0ea68838-9745-4746-9a7c-26ce56993937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152952577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1152952577
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4225694442
Short name T497
Test name
Test status
Simulation time 33625843 ps
CPU time 0.54 seconds
Started Jun 02 02:03:40 PM PDT 24
Finished Jun 02 02:03:41 PM PDT 24
Peak memory 182516 kb
Host smart-bf71a09c-db3f-4bbe-acac-7eeeaf37de86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225694442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4225694442
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2880359102
Short name T463
Test name
Test status
Simulation time 13624542 ps
CPU time 0.55 seconds
Started Jun 02 02:03:38 PM PDT 24
Finished Jun 02 02:03:39 PM PDT 24
Peak memory 182296 kb
Host smart-88deca8a-558e-4607-8f6c-bae9c10debb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880359102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2880359102
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1737632506
Short name T554
Test name
Test status
Simulation time 26896101 ps
CPU time 0.56 seconds
Started Jun 02 02:03:42 PM PDT 24
Finished Jun 02 02:03:43 PM PDT 24
Peak memory 182560 kb
Host smart-f0011de7-c3fd-40fc-84bc-e5f571c40f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737632506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1737632506
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2069644882
Short name T529
Test name
Test status
Simulation time 13636480 ps
CPU time 0.53 seconds
Started Jun 02 02:03:41 PM PDT 24
Finished Jun 02 02:03:42 PM PDT 24
Peak memory 182096 kb
Host smart-f5236ab9-f280-49a5-8f89-ec61629799f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069644882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2069644882
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2749255217
Short name T473
Test name
Test status
Simulation time 114635762 ps
CPU time 1.43 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 197640 kb
Host smart-d86284e9-fc3e-46fe-a438-e898e38a54d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749255217 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2749255217
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2172377126
Short name T498
Test name
Test status
Simulation time 55422870 ps
CPU time 0.57 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:14 PM PDT 24
Peak memory 182728 kb
Host smart-d0bf6748-cdc3-4042-9cd3-4d05a34d9304
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172377126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2172377126
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1689657065
Short name T478
Test name
Test status
Simulation time 13674348 ps
CPU time 0.58 seconds
Started Jun 02 02:03:14 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 182604 kb
Host smart-4461decb-d208-4fc3-84d6-e2039b74e452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689657065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1689657065
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3230973361
Short name T571
Test name
Test status
Simulation time 17711610 ps
CPU time 0.66 seconds
Started Jun 02 02:03:16 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 192020 kb
Host smart-9fb029e3-7a79-40fa-8202-ae5413820af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230973361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3230973361
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.194050713
Short name T522
Test name
Test status
Simulation time 342080468 ps
CPU time 1.05 seconds
Started Jun 02 02:03:15 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 197392 kb
Host smart-01756839-6e86-4d66-9afd-1a1850a9c2b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194050713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.194050713
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.634121051
Short name T481
Test name
Test status
Simulation time 39724297 ps
CPU time 0.7 seconds
Started Jun 02 02:03:12 PM PDT 24
Finished Jun 02 02:03:14 PM PDT 24
Peak memory 194256 kb
Host smart-513dac61-88c9-4657-bb47-4440726f8ffe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634121051 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.634121051
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3552040461
Short name T564
Test name
Test status
Simulation time 30535809 ps
CPU time 0.6 seconds
Started Jun 02 02:03:16 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 182548 kb
Host smart-0e7ecb21-fbdd-43fe-bb33-19d7f8bb215a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552040461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3552040461
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1416171583
Short name T470
Test name
Test status
Simulation time 16721152 ps
CPU time 0.55 seconds
Started Jun 02 02:03:14 PM PDT 24
Finished Jun 02 02:03:16 PM PDT 24
Peak memory 182552 kb
Host smart-c61b5f11-7db1-4cb5-b392-62a56b0adb57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416171583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1416171583
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3664013784
Short name T55
Test name
Test status
Simulation time 69394099 ps
CPU time 0.68 seconds
Started Jun 02 02:03:15 PM PDT 24
Finished Jun 02 02:03:16 PM PDT 24
Peak memory 191588 kb
Host smart-c3d8bb85-dff4-4ce0-82e1-b0ae83d39f81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664013784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3664013784
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1324003310
Short name T508
Test name
Test status
Simulation time 111233635 ps
CPU time 1.41 seconds
Started Jun 02 02:03:12 PM PDT 24
Finished Jun 02 02:03:14 PM PDT 24
Peak memory 197500 kb
Host smart-0f5d5c01-39a4-48a4-a11c-dac4ffdfe33a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324003310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1324003310
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2138208399
Short name T578
Test name
Test status
Simulation time 145317048 ps
CPU time 1.29 seconds
Started Jun 02 02:03:21 PM PDT 24
Finished Jun 02 02:03:23 PM PDT 24
Peak memory 183232 kb
Host smart-3715ce7f-ede0-4de2-aebb-2460435f2a67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138208399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2138208399
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.84617866
Short name T552
Test name
Test status
Simulation time 39667348 ps
CPU time 0.96 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 197192 kb
Host smart-3c7fe244-f165-4242-8a93-afef753aabce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84617866 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.84617866
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.165059926
Short name T563
Test name
Test status
Simulation time 19221558 ps
CPU time 0.58 seconds
Started Jun 02 02:03:14 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 182624 kb
Host smart-bb111d97-2deb-4093-b1d8-7a564568e3a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165059926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.165059926
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2533048892
Short name T491
Test name
Test status
Simulation time 24043172 ps
CPU time 0.7 seconds
Started Jun 02 02:03:14 PM PDT 24
Finished Jun 02 02:03:16 PM PDT 24
Peak memory 191676 kb
Host smart-f4085463-07eb-47a1-82bc-af57c04c01bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533048892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2533048892
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.645964796
Short name T549
Test name
Test status
Simulation time 121901914 ps
CPU time 1.61 seconds
Started Jun 02 02:03:12 PM PDT 24
Finished Jun 02 02:03:14 PM PDT 24
Peak memory 197600 kb
Host smart-34670e10-b476-4f3e-b85a-2436e6b95235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645964796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.645964796
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3154353194
Short name T506
Test name
Test status
Simulation time 796035131 ps
CPU time 1.32 seconds
Started Jun 02 02:03:12 PM PDT 24
Finished Jun 02 02:03:14 PM PDT 24
Peak memory 183416 kb
Host smart-b2b98da2-823b-4653-a917-9a7acb189385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154353194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3154353194
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1496371032
Short name T462
Test name
Test status
Simulation time 68221176 ps
CPU time 0.81 seconds
Started Jun 02 02:03:16 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 195540 kb
Host smart-9ad7ab95-5fe2-46e6-af32-811e820b94ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496371032 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1496371032
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3709687132
Short name T495
Test name
Test status
Simulation time 28692090 ps
CPU time 0.6 seconds
Started Jun 02 02:03:13 PM PDT 24
Finished Jun 02 02:03:15 PM PDT 24
Peak memory 191984 kb
Host smart-1dd99b0b-f730-4e74-829b-231e9a719c9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709687132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3709687132
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.11818495
Short name T464
Test name
Test status
Simulation time 60162869 ps
CPU time 0.57 seconds
Started Jun 02 02:03:12 PM PDT 24
Finished Jun 02 02:03:13 PM PDT 24
Peak memory 182672 kb
Host smart-ee4fcb07-7e6b-4303-8369-6d485ba033f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11818495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.11818495
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1102288496
Short name T99
Test name
Test status
Simulation time 28923204 ps
CPU time 0.6 seconds
Started Jun 02 02:03:16 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 191352 kb
Host smart-ef881808-7c32-492a-ba2c-5302482efbff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102288496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1102288496
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.582927975
Short name T561
Test name
Test status
Simulation time 90599756 ps
CPU time 1.27 seconds
Started Jun 02 02:03:15 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 197624 kb
Host smart-a9e1270e-e465-43de-aa30-ae51fba67204
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582927975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.582927975
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1137712952
Short name T504
Test name
Test status
Simulation time 399298555 ps
CPU time 1.37 seconds
Started Jun 02 02:03:12 PM PDT 24
Finished Jun 02 02:03:14 PM PDT 24
Peak memory 183220 kb
Host smart-240e79e6-3541-4169-9404-63f4969990a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137712952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1137712952
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3393498691
Short name T513
Test name
Test status
Simulation time 64137999 ps
CPU time 0.68 seconds
Started Jun 02 02:03:26 PM PDT 24
Finished Jun 02 02:03:27 PM PDT 24
Peak memory 194844 kb
Host smart-2871cd63-d057-4f87-9614-1fcc9c57de73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393498691 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3393498691
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3866693489
Short name T92
Test name
Test status
Simulation time 55183957 ps
CPU time 0.59 seconds
Started Jun 02 02:03:19 PM PDT 24
Finished Jun 02 02:03:20 PM PDT 24
Peak memory 182748 kb
Host smart-cda0c1a8-b014-4abf-913d-ff17f366025f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866693489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3866693489
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4113338836
Short name T519
Test name
Test status
Simulation time 22486008 ps
CPU time 0.55 seconds
Started Jun 02 02:03:18 PM PDT 24
Finished Jun 02 02:03:19 PM PDT 24
Peak memory 182676 kb
Host smart-f3f59faf-c704-402b-8e4b-b301b5edffab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113338836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4113338836
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2731045406
Short name T54
Test name
Test status
Simulation time 159468913 ps
CPU time 0.82 seconds
Started Jun 02 02:03:19 PM PDT 24
Finished Jun 02 02:03:21 PM PDT 24
Peak memory 193252 kb
Host smart-740e8295-17d8-4197-b71c-6d4d29f20afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731045406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2731045406
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1438700266
Short name T577
Test name
Test status
Simulation time 31929722 ps
CPU time 1.47 seconds
Started Jun 02 02:03:23 PM PDT 24
Finished Jun 02 02:03:25 PM PDT 24
Peak memory 197624 kb
Host smart-c32145c2-a095-49b8-b7fe-a3d7ad963d27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438700266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1438700266
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4194610660
Short name T108
Test name
Test status
Simulation time 621300213 ps
CPU time 1.37 seconds
Started Jun 02 02:03:15 PM PDT 24
Finished Jun 02 02:03:17 PM PDT 24
Peak memory 194744 kb
Host smart-fb27ea0d-cf8c-4139-8636-ef4c9045fbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194610660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4194610660
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3080632482
Short name T392
Test name
Test status
Simulation time 304630970720 ps
CPU time 221.03 seconds
Started Jun 02 02:18:12 PM PDT 24
Finished Jun 02 02:21:53 PM PDT 24
Peak memory 182992 kb
Host smart-088cd201-d750-464e-9dc0-1c6ab677486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080632482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3080632482
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2425072113
Short name T127
Test name
Test status
Simulation time 136898954962 ps
CPU time 399.82 seconds
Started Jun 02 02:18:14 PM PDT 24
Finished Jun 02 02:24:54 PM PDT 24
Peak memory 194596 kb
Host smart-dc8f793d-1c35-46f2-99d5-1c214c0880a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425072113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2425072113
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2741355274
Short name T376
Test name
Test status
Simulation time 443062218841 ps
CPU time 343.6 seconds
Started Jun 02 02:18:12 PM PDT 24
Finished Jun 02 02:23:56 PM PDT 24
Peak memory 183004 kb
Host smart-9cee94e9-cfdd-4e0f-b8e2-285656c32d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741355274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2741355274
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.838631421
Short name T331
Test name
Test status
Simulation time 128534965559 ps
CPU time 850.25 seconds
Started Jun 02 02:18:12 PM PDT 24
Finished Jun 02 02:32:23 PM PDT 24
Peak memory 191184 kb
Host smart-2e06e69a-52ee-4931-acc2-1317c5b5857a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838631421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.838631421
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3824208236
Short name T448
Test name
Test status
Simulation time 4822861903 ps
CPU time 6.03 seconds
Started Jun 02 02:18:10 PM PDT 24
Finished Jun 02 02:18:16 PM PDT 24
Peak memory 191112 kb
Host smart-f470573b-84cc-489e-b0fe-d702de5d99a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824208236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3824208236
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3837461775
Short name T18
Test name
Test status
Simulation time 35328592 ps
CPU time 0.74 seconds
Started Jun 02 02:18:13 PM PDT 24
Finished Jun 02 02:18:14 PM PDT 24
Peak memory 213404 kb
Host smart-1e0a70d8-55b8-4157-a663-25e105c3047b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837461775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3837461775
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3522825440
Short name T173
Test name
Test status
Simulation time 193142392144 ps
CPU time 325.13 seconds
Started Jun 02 02:18:10 PM PDT 24
Finished Jun 02 02:23:36 PM PDT 24
Peak memory 191180 kb
Host smart-eb540285-5cc8-42f9-a73b-fd4b06079086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522825440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3522825440
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.765892406
Short name T267
Test name
Test status
Simulation time 2511993844219 ps
CPU time 846.32 seconds
Started Jun 02 02:18:19 PM PDT 24
Finished Jun 02 02:32:26 PM PDT 24
Peak memory 182944 kb
Host smart-55309dd3-70d9-43d6-9799-74f7b14de649
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765892406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.765892406
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2028032236
Short name T28
Test name
Test status
Simulation time 107952250837 ps
CPU time 48.39 seconds
Started Jun 02 02:18:23 PM PDT 24
Finished Jun 02 02:19:12 PM PDT 24
Peak memory 183000 kb
Host smart-8d7ee20c-f8c4-46bc-8a45-a07d27a399c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028032236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2028032236
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.404933909
Short name T178
Test name
Test status
Simulation time 383150155464 ps
CPU time 615.48 seconds
Started Jun 02 02:18:18 PM PDT 24
Finished Jun 02 02:28:34 PM PDT 24
Peak memory 191156 kb
Host smart-375d5546-4e03-4211-8b6f-6d95ed5a58e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404933909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.404933909
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2453506165
Short name T439
Test name
Test status
Simulation time 198769075 ps
CPU time 0.66 seconds
Started Jun 02 02:18:16 PM PDT 24
Finished Jun 02 02:18:17 PM PDT 24
Peak memory 182812 kb
Host smart-500cbec3-ade2-4527-a0f8-c24c4e3b07d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453506165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2453506165
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.680529806
Short name T348
Test name
Test status
Simulation time 204525847952 ps
CPU time 200.9 seconds
Started Jun 02 02:18:22 PM PDT 24
Finished Jun 02 02:21:44 PM PDT 24
Peak memory 191188 kb
Host smart-ea29bdb2-a89e-46f5-8da1-70a1216279c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680529806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
680529806
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.239449365
Short name T422
Test name
Test status
Simulation time 550705782898 ps
CPU time 323.41 seconds
Started Jun 02 02:19:48 PM PDT 24
Finished Jun 02 02:25:12 PM PDT 24
Peak memory 191200 kb
Host smart-afe39c6d-a26f-4f72-adab-d22c180bc6d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239449365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.239449365
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1248289389
Short name T432
Test name
Test status
Simulation time 129066709868 ps
CPU time 462.5 seconds
Started Jun 02 02:19:48 PM PDT 24
Finished Jun 02 02:27:31 PM PDT 24
Peak memory 191140 kb
Host smart-3b83e7e8-d0de-4552-8667-ba59dede1313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248289389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1248289389
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2130384370
Short name T27
Test name
Test status
Simulation time 224670731013 ps
CPU time 186.6 seconds
Started Jun 02 02:19:54 PM PDT 24
Finished Jun 02 02:23:01 PM PDT 24
Peak memory 191204 kb
Host smart-7b428091-c921-4138-bb7d-78b7e0e9be35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130384370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2130384370
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.332665725
Short name T252
Test name
Test status
Simulation time 23199608633 ps
CPU time 33.1 seconds
Started Jun 02 02:19:54 PM PDT 24
Finished Jun 02 02:20:28 PM PDT 24
Peak memory 182800 kb
Host smart-9a197ade-4551-4646-998d-c9450534907a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332665725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.332665725
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.254202014
Short name T24
Test name
Test status
Simulation time 277766030371 ps
CPU time 467.54 seconds
Started Jun 02 02:19:54 PM PDT 24
Finished Jun 02 02:27:42 PM PDT 24
Peak memory 191172 kb
Host smart-08fb196c-d107-4766-bd96-c9d398519290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254202014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.254202014
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3970681271
Short name T139
Test name
Test status
Simulation time 247680126019 ps
CPU time 217.08 seconds
Started Jun 02 02:19:55 PM PDT 24
Finished Jun 02 02:23:33 PM PDT 24
Peak memory 191196 kb
Host smart-3b62458d-1457-4697-b306-060cc50aea8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970681271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3970681271
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1753195048
Short name T426
Test name
Test status
Simulation time 25633303453 ps
CPU time 46.82 seconds
Started Jun 02 02:19:54 PM PDT 24
Finished Jun 02 02:20:42 PM PDT 24
Peak memory 182976 kb
Host smart-41089a11-f760-497b-9516-f29ff2b503a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753195048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1753195048
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2728050668
Short name T349
Test name
Test status
Simulation time 21753922687 ps
CPU time 34.98 seconds
Started Jun 02 02:19:54 PM PDT 24
Finished Jun 02 02:20:29 PM PDT 24
Peak memory 182984 kb
Host smart-7fb36c62-cd08-42d4-8dc9-778f102d076b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728050668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2728050668
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3924956177
Short name T311
Test name
Test status
Simulation time 600200288467 ps
CPU time 135.61 seconds
Started Jun 02 02:20:00 PM PDT 24
Finished Jun 02 02:22:16 PM PDT 24
Peak memory 191192 kb
Host smart-ed82dc31-b8ce-46ee-80e3-9e6698ba3897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924956177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3924956177
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1175594794
Short name T290
Test name
Test status
Simulation time 869145701926 ps
CPU time 274.33 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:22:56 PM PDT 24
Peak memory 183004 kb
Host smart-1c65eaad-8d55-4f23-8bf6-82f1458ad171
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175594794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1175594794
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1770234588
Short name T386
Test name
Test status
Simulation time 15148392592 ps
CPU time 25.52 seconds
Started Jun 02 02:18:17 PM PDT 24
Finished Jun 02 02:18:43 PM PDT 24
Peak memory 182984 kb
Host smart-c8b1db86-a0cf-4a1a-b68c-0b142efb5460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770234588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1770234588
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.385521158
Short name T158
Test name
Test status
Simulation time 142573903256 ps
CPU time 367.64 seconds
Started Jun 02 02:18:26 PM PDT 24
Finished Jun 02 02:24:34 PM PDT 24
Peak memory 191100 kb
Host smart-d2970206-6811-4e4f-b619-0424ec7b8bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385521158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.385521158
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4190619780
Short name T315
Test name
Test status
Simulation time 51017321359 ps
CPU time 101.78 seconds
Started Jun 02 02:18:18 PM PDT 24
Finished Jun 02 02:20:01 PM PDT 24
Peak memory 182956 kb
Host smart-b456b48b-3c83-46b3-aa5c-01ba58717414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190619780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4190619780
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2073641692
Short name T292
Test name
Test status
Simulation time 92939075876 ps
CPU time 189.64 seconds
Started Jun 02 02:20:00 PM PDT 24
Finished Jun 02 02:23:10 PM PDT 24
Peak memory 191164 kb
Host smart-ae8e8e03-8567-4bcd-adef-282c26886b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073641692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2073641692
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2386545636
Short name T202
Test name
Test status
Simulation time 260167905770 ps
CPU time 518.34 seconds
Started Jun 02 02:20:00 PM PDT 24
Finished Jun 02 02:28:39 PM PDT 24
Peak memory 191184 kb
Host smart-3a506965-8b46-4f3a-bce5-2f5bf3c236c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386545636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2386545636
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2195493018
Short name T262
Test name
Test status
Simulation time 105979951390 ps
CPU time 188.38 seconds
Started Jun 02 02:19:59 PM PDT 24
Finished Jun 02 02:23:08 PM PDT 24
Peak memory 191100 kb
Host smart-bd9c118e-74cc-41ae-b9da-a85977d640cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195493018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2195493018
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.300340074
Short name T354
Test name
Test status
Simulation time 114794308210 ps
CPU time 17.84 seconds
Started Jun 02 02:20:00 PM PDT 24
Finished Jun 02 02:20:18 PM PDT 24
Peak memory 182820 kb
Host smart-a15d077d-7400-4807-b9e5-501aa43605aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300340074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.300340074
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1842804027
Short name T234
Test name
Test status
Simulation time 66607602137 ps
CPU time 119.1 seconds
Started Jun 02 02:20:05 PM PDT 24
Finished Jun 02 02:22:04 PM PDT 24
Peak memory 191148 kb
Host smart-197ba609-d497-43d1-b669-b876a6f03371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842804027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1842804027
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4011995993
Short name T295
Test name
Test status
Simulation time 215933738377 ps
CPU time 189.89 seconds
Started Jun 02 02:20:00 PM PDT 24
Finished Jun 02 02:23:11 PM PDT 24
Peak memory 193460 kb
Host smart-7958a1f7-86b0-4de3-98c6-832325bbfc50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011995993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4011995993
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.401520268
Short name T175
Test name
Test status
Simulation time 85404357092 ps
CPU time 613.4 seconds
Started Jun 02 02:20:09 PM PDT 24
Finished Jun 02 02:30:22 PM PDT 24
Peak memory 191144 kb
Host smart-bd53f0b9-e8fb-461d-a0ce-b1023596e788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401520268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.401520268
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1013155264
Short name T2
Test name
Test status
Simulation time 192089001818 ps
CPU time 55.13 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:19:17 PM PDT 24
Peak memory 183000 kb
Host smart-00b4401f-0158-4dd9-bba6-495dfd511294
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013155264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1013155264
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3487320055
Short name T428
Test name
Test status
Simulation time 951072824022 ps
CPU time 216.23 seconds
Started Jun 02 02:18:25 PM PDT 24
Finished Jun 02 02:22:02 PM PDT 24
Peak memory 182576 kb
Host smart-7ba71574-7fa7-4f6b-9cdc-3af0f7875265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487320055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3487320055
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.712011360
Short name T138
Test name
Test status
Simulation time 787444396892 ps
CPU time 642.46 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:29:07 PM PDT 24
Peak memory 193204 kb
Host smart-26ccc08c-953f-460a-a62d-273b70572e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712011360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.712011360
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.380514594
Short name T431
Test name
Test status
Simulation time 7298138731 ps
CPU time 3.92 seconds
Started Jun 02 02:18:23 PM PDT 24
Finished Jun 02 02:18:28 PM PDT 24
Peak memory 182996 kb
Host smart-175877c7-ec37-4ed8-9104-8d6e00106b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380514594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
380514594
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.3282765924
Short name T335
Test name
Test status
Simulation time 54668859337 ps
CPU time 15.62 seconds
Started Jun 02 02:20:06 PM PDT 24
Finished Jun 02 02:20:22 PM PDT 24
Peak memory 182988 kb
Host smart-2a9ef9c2-d0a3-44a5-a6ef-df8c59d3e759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282765924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3282765924
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.339144782
Short name T410
Test name
Test status
Simulation time 177438350517 ps
CPU time 84.55 seconds
Started Jun 02 02:20:07 PM PDT 24
Finished Jun 02 02:21:31 PM PDT 24
Peak memory 191208 kb
Host smart-87020c4b-a9e3-4ebc-aee4-d53500f5a78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339144782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.339144782
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.641627700
Short name T133
Test name
Test status
Simulation time 95486056170 ps
CPU time 474.89 seconds
Started Jun 02 02:20:06 PM PDT 24
Finished Jun 02 02:28:01 PM PDT 24
Peak memory 191176 kb
Host smart-94db80dc-c129-4279-932c-548e2823c5c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641627700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.641627700
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1324378235
Short name T228
Test name
Test status
Simulation time 207235572780 ps
CPU time 425.78 seconds
Started Jun 02 02:20:08 PM PDT 24
Finished Jun 02 02:27:14 PM PDT 24
Peak memory 194532 kb
Host smart-8bc45852-1723-4c76-b69a-cb00acd5b4c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324378235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1324378235
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4206871243
Short name T417
Test name
Test status
Simulation time 14838944610 ps
CPU time 26.89 seconds
Started Jun 02 02:20:12 PM PDT 24
Finished Jun 02 02:20:39 PM PDT 24
Peak memory 182920 kb
Host smart-42324503-9280-4984-89b8-ca2af45e35f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206871243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4206871243
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3227477232
Short name T182
Test name
Test status
Simulation time 140188496556 ps
CPU time 217.14 seconds
Started Jun 02 02:20:12 PM PDT 24
Finished Jun 02 02:23:50 PM PDT 24
Peak memory 193908 kb
Host smart-387f870e-846b-4eb6-a681-c2240d783a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227477232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3227477232
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.962919746
Short name T328
Test name
Test status
Simulation time 1173277574870 ps
CPU time 629.79 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:28:54 PM PDT 24
Peak memory 182944 kb
Host smart-f747af0e-abbe-4533-9ea3-9de3bbee6b27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962919746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.962919746
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3591295715
Short name T423
Test name
Test status
Simulation time 205430631271 ps
CPU time 161.75 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:21:06 PM PDT 24
Peak memory 183020 kb
Host smart-2e0b7f87-79d6-4f7d-8763-8e716e703e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591295715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3591295715
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1495239665
Short name T181
Test name
Test status
Simulation time 80301814782 ps
CPU time 551.7 seconds
Started Jun 02 02:18:27 PM PDT 24
Finished Jun 02 02:27:40 PM PDT 24
Peak memory 191112 kb
Host smart-20d1fab8-2080-484c-a4ce-60f6ce427db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495239665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1495239665
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1651417310
Short name T43
Test name
Test status
Simulation time 99386145251 ps
CPU time 206.71 seconds
Started Jun 02 02:18:25 PM PDT 24
Finished Jun 02 02:21:52 PM PDT 24
Peak memory 197892 kb
Host smart-613e288f-2e9e-4a6f-bf32-0579ccf4f3d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651417310 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1651417310
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1656245281
Short name T240
Test name
Test status
Simulation time 341103340122 ps
CPU time 257.77 seconds
Started Jun 02 02:20:12 PM PDT 24
Finished Jun 02 02:24:30 PM PDT 24
Peak memory 191172 kb
Host smart-f610c94d-598e-41e3-b534-39f57233771d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656245281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1656245281
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2485171289
Short name T250
Test name
Test status
Simulation time 37472583211 ps
CPU time 58.49 seconds
Started Jun 02 02:20:13 PM PDT 24
Finished Jun 02 02:21:12 PM PDT 24
Peak memory 191192 kb
Host smart-06db405a-a67b-453e-bde3-f3ab8d8097d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485171289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2485171289
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2505751027
Short name T325
Test name
Test status
Simulation time 922182634261 ps
CPU time 280.81 seconds
Started Jun 02 02:20:18 PM PDT 24
Finished Jun 02 02:24:59 PM PDT 24
Peak memory 191188 kb
Host smart-64624139-f5c2-4358-8d5a-8674c476de40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505751027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2505751027
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1475713268
Short name T213
Test name
Test status
Simulation time 107870672769 ps
CPU time 124.44 seconds
Started Jun 02 02:20:19 PM PDT 24
Finished Jun 02 02:22:23 PM PDT 24
Peak memory 191176 kb
Host smart-9da77537-cd7c-4a9f-9908-2fd44aee3503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475713268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1475713268
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2953477600
Short name T404
Test name
Test status
Simulation time 87139390107 ps
CPU time 129.4 seconds
Started Jun 02 02:20:22 PM PDT 24
Finished Jun 02 02:22:32 PM PDT 24
Peak memory 182956 kb
Host smart-06c894c4-9837-4de0-8a49-e12c2195e9c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953477600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2953477600
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.532220003
Short name T418
Test name
Test status
Simulation time 33571290792 ps
CPU time 48.27 seconds
Started Jun 02 02:20:25 PM PDT 24
Finished Jun 02 02:21:14 PM PDT 24
Peak memory 182980 kb
Host smart-bd04a90f-df0f-4673-a9e0-919f79956a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532220003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.532220003
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3602700588
Short name T162
Test name
Test status
Simulation time 187033630984 ps
CPU time 381.35 seconds
Started Jun 02 02:20:25 PM PDT 24
Finished Jun 02 02:26:46 PM PDT 24
Peak memory 191180 kb
Host smart-c5da9d22-21a9-4fdf-ae32-44c17e543686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602700588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3602700588
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1142550188
Short name T442
Test name
Test status
Simulation time 84549974980 ps
CPU time 49.72 seconds
Started Jun 02 02:18:22 PM PDT 24
Finished Jun 02 02:19:12 PM PDT 24
Peak memory 183000 kb
Host smart-91515711-63e4-4135-94bd-e6f090874208
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142550188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1142550188
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3757136004
Short name T408
Test name
Test status
Simulation time 133861844794 ps
CPU time 212.57 seconds
Started Jun 02 02:18:27 PM PDT 24
Finished Jun 02 02:22:01 PM PDT 24
Peak memory 183000 kb
Host smart-34f3fbee-28b4-4c02-8e14-787f4c749432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757136004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3757136004
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.183980321
Short name T251
Test name
Test status
Simulation time 670787686131 ps
CPU time 604.59 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:28:29 PM PDT 24
Peak memory 191128 kb
Host smart-8e43b9f5-de6c-47a8-b7d2-ef7a110e25b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183980321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.183980321
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3864208438
Short name T407
Test name
Test status
Simulation time 509282798 ps
CPU time 1.4 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:18:26 PM PDT 24
Peak memory 182796 kb
Host smart-272206ef-68e9-4228-a935-0734c31ef74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864208438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3864208438
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.3182690703
Short name T266
Test name
Test status
Simulation time 206311659291 ps
CPU time 383.01 seconds
Started Jun 02 02:20:27 PM PDT 24
Finished Jun 02 02:26:50 PM PDT 24
Peak memory 191148 kb
Host smart-811e0754-ba28-4cf7-b597-5fafba0f562f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182690703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3182690703
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1462656678
Short name T326
Test name
Test status
Simulation time 93132787820 ps
CPU time 80.63 seconds
Started Jun 02 02:20:26 PM PDT 24
Finished Jun 02 02:21:47 PM PDT 24
Peak memory 191160 kb
Host smart-015b6388-afad-442b-a552-ed0998d110cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462656678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1462656678
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1277706302
Short name T83
Test name
Test status
Simulation time 541601968868 ps
CPU time 576.08 seconds
Started Jun 02 02:20:25 PM PDT 24
Finished Jun 02 02:30:02 PM PDT 24
Peak memory 191180 kb
Host smart-2ba89dd7-675f-4f9a-8f98-fb4f9121fbd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277706302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1277706302
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2145293608
Short name T118
Test name
Test status
Simulation time 92409805878 ps
CPU time 242.87 seconds
Started Jun 02 02:20:34 PM PDT 24
Finished Jun 02 02:24:38 PM PDT 24
Peak memory 191188 kb
Host smart-fce69d71-790d-4407-ba1f-da059606d8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145293608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2145293608
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3935250549
Short name T7
Test name
Test status
Simulation time 97691271037 ps
CPU time 101.27 seconds
Started Jun 02 02:20:34 PM PDT 24
Finished Jun 02 02:22:16 PM PDT 24
Peak memory 182956 kb
Host smart-811d65fb-fc23-4719-bcc3-8fea351e1879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935250549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3935250549
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1332947723
Short name T302
Test name
Test status
Simulation time 174160220356 ps
CPU time 83.52 seconds
Started Jun 02 02:20:34 PM PDT 24
Finished Jun 02 02:21:57 PM PDT 24
Peak memory 182936 kb
Host smart-d89c8a31-9125-43fe-b19b-7f1ae8a27b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332947723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1332947723
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3243025191
Short name T209
Test name
Test status
Simulation time 40781884199 ps
CPU time 210.41 seconds
Started Jun 02 02:20:34 PM PDT 24
Finished Jun 02 02:24:04 PM PDT 24
Peak memory 182984 kb
Host smart-999e2488-c1b8-406b-af49-791ac97ac902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243025191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3243025191
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3757031929
Short name T371
Test name
Test status
Simulation time 841249656 ps
CPU time 0.79 seconds
Started Jun 02 02:18:23 PM PDT 24
Finished Jun 02 02:18:24 PM PDT 24
Peak memory 182804 kb
Host smart-1354e0e2-6c52-49ae-b063-8a45af6835e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757031929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3757031929
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.1423329635
Short name T74
Test name
Test status
Simulation time 93762754556 ps
CPU time 443.59 seconds
Started Jun 02 02:18:28 PM PDT 24
Finished Jun 02 02:25:52 PM PDT 24
Peak memory 205788 kb
Host smart-d3d25114-ffbb-489d-86f4-fc5529104f6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423329635 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.1423329635
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.257498974
Short name T272
Test name
Test status
Simulation time 18037508734 ps
CPU time 141.55 seconds
Started Jun 02 02:20:34 PM PDT 24
Finished Jun 02 02:22:56 PM PDT 24
Peak memory 182940 kb
Host smart-5232d697-ff08-4304-8831-53be85854bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257498974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.257498974
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.997830488
Short name T109
Test name
Test status
Simulation time 603925332968 ps
CPU time 968.21 seconds
Started Jun 02 02:20:33 PM PDT 24
Finished Jun 02 02:36:42 PM PDT 24
Peak memory 191176 kb
Host smart-d55a23b5-b7c7-453f-81dc-0950739d5482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997830488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.997830488
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2551012686
Short name T320
Test name
Test status
Simulation time 63850448172 ps
CPU time 531.7 seconds
Started Jun 02 02:20:40 PM PDT 24
Finished Jun 02 02:29:32 PM PDT 24
Peak memory 182996 kb
Host smart-47699133-66e4-4677-a899-54435f302da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551012686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2551012686
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.957640097
Short name T260
Test name
Test status
Simulation time 32703360578 ps
CPU time 81.48 seconds
Started Jun 02 02:20:40 PM PDT 24
Finished Jun 02 02:22:02 PM PDT 24
Peak memory 191204 kb
Host smart-c1f8091e-14d5-4f8f-9156-d932abd906b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957640097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.957640097
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.4009629403
Short name T10
Test name
Test status
Simulation time 82924895800 ps
CPU time 69.43 seconds
Started Jun 02 02:20:41 PM PDT 24
Finished Jun 02 02:21:50 PM PDT 24
Peak memory 191204 kb
Host smart-156d8f74-15df-4647-864c-09b0bb08c646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009629403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4009629403
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2725162690
Short name T195
Test name
Test status
Simulation time 107279840491 ps
CPU time 246.88 seconds
Started Jun 02 02:20:39 PM PDT 24
Finished Jun 02 02:24:47 PM PDT 24
Peak memory 191200 kb
Host smart-76c530ab-3cb0-4068-8965-6fa395a62291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725162690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2725162690
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.509760091
Short name T207
Test name
Test status
Simulation time 1381902570543 ps
CPU time 556.42 seconds
Started Jun 02 02:18:25 PM PDT 24
Finished Jun 02 02:27:42 PM PDT 24
Peak memory 183008 kb
Host smart-336e75e2-b5a4-43de-857a-ca7bda077fcd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509760091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.509760091
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.165704259
Short name T372
Test name
Test status
Simulation time 98752336258 ps
CPU time 85.22 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:19:50 PM PDT 24
Peak memory 182984 kb
Host smart-5ac971c3-5f81-4a85-a493-a7bdba1370e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165704259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.165704259
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2071776789
Short name T296
Test name
Test status
Simulation time 179681709436 ps
CPU time 115.82 seconds
Started Jun 02 02:18:26 PM PDT 24
Finished Jun 02 02:20:22 PM PDT 24
Peak memory 191176 kb
Host smart-da5f33f4-6b70-494f-bfc7-d1ad51c29b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071776789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2071776789
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1782145837
Short name T301
Test name
Test status
Simulation time 281184471407 ps
CPU time 549.18 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:27:34 PM PDT 24
Peak memory 191184 kb
Host smart-d632e92a-9eea-4766-ae50-4cfab8b8ed38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782145837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1782145837
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/165.rv_timer_random.2065740922
Short name T271
Test name
Test status
Simulation time 117433933691 ps
CPU time 315.28 seconds
Started Jun 02 02:20:47 PM PDT 24
Finished Jun 02 02:26:03 PM PDT 24
Peak memory 191196 kb
Host smart-8ceb29be-4a92-47b3-be59-9ef57928afc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065740922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2065740922
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1409748671
Short name T360
Test name
Test status
Simulation time 148386918273 ps
CPU time 116.78 seconds
Started Jun 02 02:20:46 PM PDT 24
Finished Jun 02 02:22:43 PM PDT 24
Peak memory 191180 kb
Host smart-db6901d6-c70e-4379-8d20-af2b6b061123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409748671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1409748671
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.909273104
Short name T247
Test name
Test status
Simulation time 16764491452 ps
CPU time 10.15 seconds
Started Jun 02 02:18:32 PM PDT 24
Finished Jun 02 02:18:42 PM PDT 24
Peak memory 182984 kb
Host smart-7905a034-0b48-454c-8dbc-80f715fdfbb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909273104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.909273104
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2808843955
Short name T436
Test name
Test status
Simulation time 60381763158 ps
CPU time 90.12 seconds
Started Jun 02 02:18:25 PM PDT 24
Finished Jun 02 02:19:55 PM PDT 24
Peak memory 183016 kb
Host smart-f72a4a0f-af9f-4531-b76d-5773463a4aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808843955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2808843955
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3436313357
Short name T362
Test name
Test status
Simulation time 540351050 ps
CPU time 1.63 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:18:43 PM PDT 24
Peak memory 193140 kb
Host smart-e7e5730c-731c-4df0-92e0-42c69b441809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436313357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3436313357
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4215746186
Short name T151
Test name
Test status
Simulation time 47242133617 ps
CPU time 120.49 seconds
Started Jun 02 02:20:45 PM PDT 24
Finished Jun 02 02:22:46 PM PDT 24
Peak memory 191112 kb
Host smart-01e3c27e-cad5-42ff-adb3-6e1eb47e5bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215746186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4215746186
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2738860803
Short name T191
Test name
Test status
Simulation time 85706266854 ps
CPU time 57.36 seconds
Started Jun 02 02:20:46 PM PDT 24
Finished Jun 02 02:21:44 PM PDT 24
Peak memory 191096 kb
Host smart-5c3781ed-2ebf-403e-a130-35946af0b13a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738860803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2738860803
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.832976164
Short name T400
Test name
Test status
Simulation time 228678620470 ps
CPU time 203.89 seconds
Started Jun 02 02:20:53 PM PDT 24
Finished Jun 02 02:24:17 PM PDT 24
Peak memory 182976 kb
Host smart-376350b7-9418-415a-876e-e3ca403ea969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832976164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.832976164
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3556787257
Short name T238
Test name
Test status
Simulation time 388584307648 ps
CPU time 367.47 seconds
Started Jun 02 02:20:53 PM PDT 24
Finished Jun 02 02:27:00 PM PDT 24
Peak memory 191180 kb
Host smart-f4b91a84-ffd4-45e2-bca8-28efc07a0d31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556787257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3556787257
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3556071203
Short name T203
Test name
Test status
Simulation time 230082010025 ps
CPU time 635.72 seconds
Started Jun 02 02:20:52 PM PDT 24
Finished Jun 02 02:31:28 PM PDT 24
Peak memory 191140 kb
Host smart-138717f2-090b-4bee-9afb-a98e7b5d8685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556071203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3556071203
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2520482883
Short name T294
Test name
Test status
Simulation time 261986877597 ps
CPU time 1110.6 seconds
Started Jun 02 02:20:58 PM PDT 24
Finished Jun 02 02:39:29 PM PDT 24
Peak memory 191176 kb
Host smart-952c7a55-aa19-4f7e-9c42-3d312a1ae172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520482883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2520482883
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1061125482
Short name T350
Test name
Test status
Simulation time 120454842968 ps
CPU time 774.44 seconds
Started Jun 02 02:20:58 PM PDT 24
Finished Jun 02 02:33:53 PM PDT 24
Peak memory 182936 kb
Host smart-f8427ae3-47d8-48ad-aa00-df52cf304823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061125482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1061125482
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.944041038
Short name T113
Test name
Test status
Simulation time 324082118355 ps
CPU time 557.35 seconds
Started Jun 02 02:20:59 PM PDT 24
Finished Jun 02 02:30:17 PM PDT 24
Peak memory 191124 kb
Host smart-590b92cc-9474-4653-bd88-3b9383bfe317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944041038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.944041038
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1290508451
Short name T192
Test name
Test status
Simulation time 45043520906 ps
CPU time 81.75 seconds
Started Jun 02 02:18:31 PM PDT 24
Finished Jun 02 02:19:53 PM PDT 24
Peak memory 182932 kb
Host smart-c8304d97-12a0-49aa-8921-35f0e8917b76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290508451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1290508451
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_random.1497211657
Short name T358
Test name
Test status
Simulation time 60642380569 ps
CPU time 419.68 seconds
Started Jun 02 02:18:30 PM PDT 24
Finished Jun 02 02:25:30 PM PDT 24
Peak memory 191144 kb
Host smart-b9dbecf5-d2ed-4866-a511-a25e407780e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497211657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1497211657
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2858440685
Short name T339
Test name
Test status
Simulation time 68428753019 ps
CPU time 71.76 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:19:50 PM PDT 24
Peak memory 191184 kb
Host smart-7d1355a6-7e0b-4b2d-ad24-485a4378858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858440685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2858440685
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2821066433
Short name T17
Test name
Test status
Simulation time 68300455408 ps
CPU time 638 seconds
Started Jun 02 02:18:30 PM PDT 24
Finished Jun 02 02:29:09 PM PDT 24
Peak memory 206852 kb
Host smart-093fdf17-35df-41da-95d6-50b92a69edb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821066433 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2821066433
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.4060589353
Short name T261
Test name
Test status
Simulation time 1391302168252 ps
CPU time 624.16 seconds
Started Jun 02 02:20:56 PM PDT 24
Finished Jun 02 02:31:21 PM PDT 24
Peak memory 191204 kb
Host smart-2c788cae-883a-42b8-8924-a5650f3e2cb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060589353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4060589353
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.637747133
Short name T177
Test name
Test status
Simulation time 303086626847 ps
CPU time 226.55 seconds
Started Jun 02 02:20:59 PM PDT 24
Finished Jun 02 02:24:46 PM PDT 24
Peak memory 182924 kb
Host smart-e1c7bebd-3e20-4f5d-af8c-df7a45eccf46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637747133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.637747133
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2091109176
Short name T265
Test name
Test status
Simulation time 52767033583 ps
CPU time 1359.74 seconds
Started Jun 02 02:20:59 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 191132 kb
Host smart-cf107270-6a16-4d2a-90bf-a72751399875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091109176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2091109176
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2211006367
Short name T121
Test name
Test status
Simulation time 208441890615 ps
CPU time 397.47 seconds
Started Jun 02 02:21:04 PM PDT 24
Finished Jun 02 02:27:42 PM PDT 24
Peak memory 191116 kb
Host smart-51b6e13a-03c9-411a-87c5-d0833ef6d8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211006367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2211006367
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1882612810
Short name T128
Test name
Test status
Simulation time 32469791655 ps
CPU time 54.42 seconds
Started Jun 02 02:21:05 PM PDT 24
Finished Jun 02 02:22:00 PM PDT 24
Peak memory 194532 kb
Host smart-996a0cde-fd12-47e0-bb83-0900c422fe4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882612810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1882612810
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1746874188
Short name T330
Test name
Test status
Simulation time 36109409382 ps
CPU time 34.34 seconds
Started Jun 02 02:21:05 PM PDT 24
Finished Jun 02 02:21:40 PM PDT 24
Peak memory 182956 kb
Host smart-2e92e228-da1c-4b3e-8b4e-f58fb186d61f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746874188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1746874188
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3882023618
Short name T146
Test name
Test status
Simulation time 598221407643 ps
CPU time 519.47 seconds
Started Jun 02 02:21:06 PM PDT 24
Finished Jun 02 02:29:45 PM PDT 24
Peak memory 191316 kb
Host smart-821ce406-f3b2-4584-91a6-811182a7cf27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882023618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3882023618
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.213322273
Short name T359
Test name
Test status
Simulation time 178060334533 ps
CPU time 164.88 seconds
Started Jun 02 02:18:30 PM PDT 24
Finished Jun 02 02:21:15 PM PDT 24
Peak memory 182944 kb
Host smart-9c0f60ea-c645-4885-bcd4-19e40ed750a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213322273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.213322273
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3036602098
Short name T396
Test name
Test status
Simulation time 89152857355 ps
CPU time 128.77 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:20:49 PM PDT 24
Peak memory 182952 kb
Host smart-9a4d2be6-d96f-4a36-b420-af3d2b63b152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036602098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3036602098
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.754483021
Short name T377
Test name
Test status
Simulation time 646602576 ps
CPU time 0.71 seconds
Started Jun 02 02:18:30 PM PDT 24
Finished Jun 02 02:18:31 PM PDT 24
Peak memory 182804 kb
Host smart-a06d5eaf-cb6c-4f90-9e66-8b69270b0c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754483021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.754483021
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2421339371
Short name T217
Test name
Test status
Simulation time 553315516602 ps
CPU time 717.83 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:30:39 PM PDT 24
Peak memory 194932 kb
Host smart-70ef2d7c-327f-4980-a59f-8a3f13285488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421339371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2421339371
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2895279728
Short name T38
Test name
Test status
Simulation time 137724629602 ps
CPU time 278.31 seconds
Started Jun 02 02:18:31 PM PDT 24
Finished Jun 02 02:23:09 PM PDT 24
Peak memory 205760 kb
Host smart-d3f37fc9-6ecb-47df-a655-4f63d9f2cf6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895279728 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.2895279728
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.rv_timer_random.591185867
Short name T241
Test name
Test status
Simulation time 24131233175 ps
CPU time 38.13 seconds
Started Jun 02 02:21:04 PM PDT 24
Finished Jun 02 02:21:42 PM PDT 24
Peak memory 191192 kb
Host smart-938fea27-a00f-4517-b7fe-cf986d9c0ce3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591185867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.591185867
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1073208397
Short name T142
Test name
Test status
Simulation time 166204983485 ps
CPU time 400.87 seconds
Started Jun 02 02:21:03 PM PDT 24
Finished Jun 02 02:27:45 PM PDT 24
Peak memory 191152 kb
Host smart-a2a189c7-a373-4ace-8cd5-bc454df36110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073208397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1073208397
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3520278512
Short name T122
Test name
Test status
Simulation time 416216454803 ps
CPU time 450.55 seconds
Started Jun 02 02:21:09 PM PDT 24
Finished Jun 02 02:28:40 PM PDT 24
Peak memory 191160 kb
Host smart-3943270e-848e-4f84-a9db-78c4b498d271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520278512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3520278512
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.476067671
Short name T155
Test name
Test status
Simulation time 152076638284 ps
CPU time 607.94 seconds
Started Jun 02 02:21:09 PM PDT 24
Finished Jun 02 02:31:18 PM PDT 24
Peak memory 191192 kb
Host smart-0ff8eb6d-2bdd-42de-b42a-3889f554fbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476067671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.476067671
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3204481200
Short name T6
Test name
Test status
Simulation time 60998607476 ps
CPU time 29.01 seconds
Started Jun 02 02:21:10 PM PDT 24
Finished Jun 02 02:21:40 PM PDT 24
Peak memory 193224 kb
Host smart-92acd2d8-1658-4ca9-8eff-90c2d2bf0dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204481200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3204481200
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2752298850
Short name T214
Test name
Test status
Simulation time 168432398095 ps
CPU time 270.2 seconds
Started Jun 02 02:21:10 PM PDT 24
Finished Jun 02 02:25:40 PM PDT 24
Peak memory 194624 kb
Host smart-0abe0b73-abcf-4a92-bad4-a04f5778cf61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752298850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2752298850
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1988085562
Short name T123
Test name
Test status
Simulation time 7678690456 ps
CPU time 13.95 seconds
Started Jun 02 02:21:10 PM PDT 24
Finished Jun 02 02:21:25 PM PDT 24
Peak memory 182920 kb
Host smart-d8845491-0040-4281-9362-9e2e9e1926b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988085562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1988085562
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2757643098
Short name T205
Test name
Test status
Simulation time 388535286352 ps
CPU time 219.01 seconds
Started Jun 02 02:21:10 PM PDT 24
Finished Jun 02 02:24:49 PM PDT 24
Peak memory 191180 kb
Host smart-dedae678-6a5d-4fa3-9cc5-60504b2b4d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757643098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2757643098
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.4194574158
Short name T402
Test name
Test status
Simulation time 101718934285 ps
CPU time 145.22 seconds
Started Jun 02 02:18:14 PM PDT 24
Finished Jun 02 02:20:39 PM PDT 24
Peak memory 182992 kb
Host smart-67e03cbd-544b-4c2f-8408-e74dc501cffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194574158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4194574158
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3575481488
Short name T229
Test name
Test status
Simulation time 653997403791 ps
CPU time 945.16 seconds
Started Jun 02 02:18:12 PM PDT 24
Finished Jun 02 02:33:58 PM PDT 24
Peak memory 193660 kb
Host smart-2efc61f6-bee1-411e-b820-eda446d853ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575481488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3575481488
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.287076758
Short name T298
Test name
Test status
Simulation time 181306878847 ps
CPU time 116.9 seconds
Started Jun 02 02:18:13 PM PDT 24
Finished Jun 02 02:20:11 PM PDT 24
Peak memory 191200 kb
Host smart-b7040e76-9f01-4c1d-8b10-737be00d4c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287076758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.287076758
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.545305296
Short name T19
Test name
Test status
Simulation time 204819876 ps
CPU time 0.87 seconds
Started Jun 02 02:18:11 PM PDT 24
Finished Jun 02 02:18:12 PM PDT 24
Peak memory 213444 kb
Host smart-821c129c-b8ad-4925-9118-bdea41eb27f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545305296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.545305296
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1426762187
Short name T215
Test name
Test status
Simulation time 1069420579041 ps
CPU time 734.64 seconds
Started Jun 02 02:18:14 PM PDT 24
Finished Jun 02 02:30:29 PM PDT 24
Peak memory 191188 kb
Host smart-55b6505b-21ef-498d-8ee5-117bb05b683e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426762187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1426762187
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3241370413
Short name T73
Test name
Test status
Simulation time 26849588159 ps
CPU time 224.7 seconds
Started Jun 02 02:18:17 PM PDT 24
Finished Jun 02 02:22:03 PM PDT 24
Peak memory 197544 kb
Host smart-f5daf113-474c-4663-a9a2-7b6a65670e41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241370413 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3241370413
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.974392080
Short name T445
Test name
Test status
Simulation time 200335869620 ps
CPU time 359.36 seconds
Started Jun 02 02:18:32 PM PDT 24
Finished Jun 02 02:24:32 PM PDT 24
Peak memory 182980 kb
Host smart-8e911c53-63a1-45e6-b8a1-209213ddbb77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974392080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.974392080
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2843091215
Short name T373
Test name
Test status
Simulation time 360557744081 ps
CPU time 156.61 seconds
Started Jun 02 02:18:32 PM PDT 24
Finished Jun 02 02:21:09 PM PDT 24
Peak memory 183008 kb
Host smart-ef813276-92f7-4f41-b15e-71244d08cfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843091215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2843091215
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2230583196
Short name T90
Test name
Test status
Simulation time 195974159 ps
CPU time 0.65 seconds
Started Jun 02 02:18:31 PM PDT 24
Finished Jun 02 02:18:32 PM PDT 24
Peak memory 182808 kb
Host smart-a04b6acf-6f1d-44f2-b07a-706584f7576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230583196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2230583196
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1371182461
Short name T126
Test name
Test status
Simulation time 1387421819181 ps
CPU time 868.66 seconds
Started Jun 02 02:18:32 PM PDT 24
Finished Jun 02 02:33:01 PM PDT 24
Peak memory 191192 kb
Host smart-56630e1b-c4b5-455f-b920-b7f6a446c6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371182461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1371182461
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.4209422281
Short name T40
Test name
Test status
Simulation time 142937223270 ps
CPU time 1196.93 seconds
Started Jun 02 02:18:35 PM PDT 24
Finished Jun 02 02:38:32 PM PDT 24
Peak memory 212748 kb
Host smart-ad96f58a-7d18-44a4-b7bf-18155c764797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209422281 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.4209422281
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2145606919
Short name T204
Test name
Test status
Simulation time 109988854664 ps
CPU time 181.12 seconds
Started Jun 02 02:18:37 PM PDT 24
Finished Jun 02 02:21:39 PM PDT 24
Peak memory 183004 kb
Host smart-05ce9688-14d5-41fb-814a-e30b972ca4a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145606919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2145606919
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.548085488
Short name T435
Test name
Test status
Simulation time 44687890688 ps
CPU time 65.21 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:19:46 PM PDT 24
Peak memory 182960 kb
Host smart-4119f5f9-7947-4c40-ae21-81ca7cd5bcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548085488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.548085488
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2946719008
Short name T324
Test name
Test status
Simulation time 49907951830 ps
CPU time 323.96 seconds
Started Jun 02 02:18:31 PM PDT 24
Finished Jun 02 02:23:56 PM PDT 24
Peak memory 182948 kb
Host smart-4ec16686-9464-43cc-9158-733eab250d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946719008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2946719008
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4125110089
Short name T37
Test name
Test status
Simulation time 216762274028 ps
CPU time 1306.67 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:40:28 PM PDT 24
Peak memory 195492 kb
Host smart-63524717-83f8-484f-b117-dfb8682b415e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125110089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4125110089
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4291340809
Short name T327
Test name
Test status
Simulation time 16423559294 ps
CPU time 14.84 seconds
Started Jun 02 02:18:32 PM PDT 24
Finished Jun 02 02:18:47 PM PDT 24
Peak memory 182996 kb
Host smart-fb77e711-acb8-4dff-b6ab-a90fbfe8b484
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291340809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4291340809
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1885740058
Short name T379
Test name
Test status
Simulation time 298202633705 ps
CPU time 116.67 seconds
Started Jun 02 02:18:32 PM PDT 24
Finished Jun 02 02:20:29 PM PDT 24
Peak memory 182928 kb
Host smart-a084b4ab-e4d9-48ab-9d50-bd75632c64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885740058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1885740058
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2713203297
Short name T172
Test name
Test status
Simulation time 75305215817 ps
CPU time 285.04 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:23:26 PM PDT 24
Peak memory 192168 kb
Host smart-e353dd28-a7f2-43ed-a559-cbb72f529b5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713203297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2713203297
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1398442789
Short name T306
Test name
Test status
Simulation time 94774757985 ps
CPU time 188.82 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:21:50 PM PDT 24
Peak memory 191372 kb
Host smart-8f663858-dbc1-4a68-99d8-71c867c6abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398442789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1398442789
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.889208938
Short name T211
Test name
Test status
Simulation time 736829860113 ps
CPU time 696.05 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:30:14 PM PDT 24
Peak memory 182960 kb
Host smart-ee36bbcc-e130-40e1-9670-22a52322c38a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889208938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.889208938
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.341334093
Short name T413
Test name
Test status
Simulation time 113927129501 ps
CPU time 47 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:19:27 PM PDT 24
Peak memory 182952 kb
Host smart-f2260e01-6857-4cdb-bd6b-2154a3c7b0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341334093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.341334093
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1719973508
Short name T239
Test name
Test status
Simulation time 94402424637 ps
CPU time 410.65 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:25:30 PM PDT 24
Peak memory 182980 kb
Host smart-7b990329-b7c3-49e7-9ab5-4077f72f2715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719973508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1719973508
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1599231872
Short name T245
Test name
Test status
Simulation time 44690177955 ps
CPU time 1073.94 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:36:34 PM PDT 24
Peak memory 182980 kb
Host smart-07704906-30de-4325-88ba-eec6e1eddb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599231872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1599231872
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2793990831
Short name T210
Test name
Test status
Simulation time 1375693471155 ps
CPU time 1054.07 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:36:15 PM PDT 24
Peak memory 183172 kb
Host smart-4f8b52e9-40e2-4c5c-bc6b-709534d6edef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793990831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2793990831
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1887530270
Short name T42
Test name
Test status
Simulation time 127620321996 ps
CPU time 419 seconds
Started Jun 02 02:18:41 PM PDT 24
Finished Jun 02 02:25:41 PM PDT 24
Peak memory 205852 kb
Host smart-128f721f-8538-4cce-8caf-e1e090a21667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887530270 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.1887530270
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2277006673
Short name T316
Test name
Test status
Simulation time 22182627710 ps
CPU time 12.96 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:18:53 PM PDT 24
Peak memory 183204 kb
Host smart-418d8e1a-682a-49f7-aec5-6d6f6c282e5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277006673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2277006673
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3732617315
Short name T421
Test name
Test status
Simulation time 61778653271 ps
CPU time 81.3 seconds
Started Jun 02 02:18:37 PM PDT 24
Finished Jun 02 02:19:59 PM PDT 24
Peak memory 182992 kb
Host smart-a60ebaf9-8194-4831-9dbc-38f6145f91b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732617315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3732617315
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3951811198
Short name T275
Test name
Test status
Simulation time 404453045563 ps
CPU time 495.38 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:26:55 PM PDT 24
Peak memory 191140 kb
Host smart-eb95d75f-a5cf-4a0e-b344-67102f6c8c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951811198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3951811198
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.133267441
Short name T89
Test name
Test status
Simulation time 8690004970 ps
CPU time 16.52 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:18:56 PM PDT 24
Peak memory 182920 kb
Host smart-226ae80c-4da6-49ee-9e38-2d1199b05ad5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133267441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.133267441
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.4193682521
Short name T399
Test name
Test status
Simulation time 126521228045 ps
CPU time 59.26 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:19:39 PM PDT 24
Peak memory 182964 kb
Host smart-fc69f28b-9f4b-4f2e-9aec-410f72072637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193682521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.4193682521
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3513096464
Short name T224
Test name
Test status
Simulation time 196529413611 ps
CPU time 943.46 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:34:23 PM PDT 24
Peak memory 183124 kb
Host smart-30fa84be-65ae-4877-b1b0-2302adc2ee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513096464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3513096464
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.683419121
Short name T318
Test name
Test status
Simulation time 5815532683 ps
CPU time 5.81 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:18:46 PM PDT 24
Peak memory 182992 kb
Host smart-cfa6a7f0-3907-484a-b25a-fe7cbe0ffc41
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683419121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.683419121
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2025386199
Short name T387
Test name
Test status
Simulation time 120166651268 ps
CPU time 42.53 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:19:21 PM PDT 24
Peak memory 182988 kb
Host smart-d496a28d-f39c-4852-bed0-22cafb3750d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025386199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2025386199
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3300415408
Short name T437
Test name
Test status
Simulation time 202399273545 ps
CPU time 85.25 seconds
Started Jun 02 02:18:41 PM PDT 24
Finished Jun 02 02:20:07 PM PDT 24
Peak memory 182900 kb
Host smart-5e133b79-89d4-4428-942f-5126116acefa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300415408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3300415408
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1900899801
Short name T343
Test name
Test status
Simulation time 27021930863 ps
CPU time 27.43 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:19:06 PM PDT 24
Peak memory 194024 kb
Host smart-bd637bbf-3760-4d72-aa67-5a32606bf9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900899801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1900899801
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2738704765
Short name T310
Test name
Test status
Simulation time 337369709778 ps
CPU time 516.29 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:27:15 PM PDT 24
Peak memory 183000 kb
Host smart-9514851c-c7d6-4b98-b1e2-8f836ad8c4fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738704765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2738704765
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.4070106154
Short name T382
Test name
Test status
Simulation time 640703854160 ps
CPU time 243.38 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:22:43 PM PDT 24
Peak memory 183008 kb
Host smart-8a4e86f1-3f45-4ef6-a2cd-d30e27afbfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070106154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.4070106154
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3537511496
Short name T167
Test name
Test status
Simulation time 45856988315 ps
CPU time 239.83 seconds
Started Jun 02 02:18:37 PM PDT 24
Finished Jun 02 02:22:38 PM PDT 24
Peak memory 191200 kb
Host smart-45d101c0-ad1e-4309-8954-0c329a2d1954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537511496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3537511496
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.4035647103
Short name T449
Test name
Test status
Simulation time 60476299359 ps
CPU time 102.04 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:20:22 PM PDT 24
Peak memory 191180 kb
Host smart-8ac56886-c0c7-498c-aa45-741861003a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035647103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4035647103
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1502544425
Short name T194
Test name
Test status
Simulation time 87942708024 ps
CPU time 204.35 seconds
Started Jun 02 02:18:38 PM PDT 24
Finished Jun 02 02:22:03 PM PDT 24
Peak memory 191196 kb
Host smart-fc8d2b24-1430-4310-82d8-be0aa51042ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502544425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1502544425
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1770343806
Short name T338
Test name
Test status
Simulation time 527217081257 ps
CPU time 324.89 seconds
Started Jun 02 02:18:41 PM PDT 24
Finished Jun 02 02:24:06 PM PDT 24
Peak memory 183016 kb
Host smart-a3cb4345-087b-4495-b77f-8057b9fee4eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770343806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1770343806
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2422796566
Short name T398
Test name
Test status
Simulation time 111850668705 ps
CPU time 144.07 seconds
Started Jun 02 02:18:39 PM PDT 24
Finished Jun 02 02:21:03 PM PDT 24
Peak memory 183000 kb
Host smart-2fb7775a-b20e-413c-b8f8-d6b76301e564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422796566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2422796566
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3749479783
Short name T355
Test name
Test status
Simulation time 82603884140 ps
CPU time 147.14 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:21:08 PM PDT 24
Peak memory 194388 kb
Host smart-a62990c0-11e5-4190-a27b-3f91a6629d0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749479783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3749479783
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.439535707
Short name T254
Test name
Test status
Simulation time 18393876381 ps
CPU time 34.9 seconds
Started Jun 02 02:18:40 PM PDT 24
Finished Jun 02 02:19:16 PM PDT 24
Peak memory 191200 kb
Host smart-80eba978-3d2d-4138-bc45-5673934e4cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439535707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.439535707
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2704491346
Short name T52
Test name
Test status
Simulation time 393071108564 ps
CPU time 170.58 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:21:35 PM PDT 24
Peak memory 182976 kb
Host smart-9004ab42-64f6-4c4f-bc91-e661b7a4a007
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704491346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2704491346
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2236531867
Short name T434
Test name
Test status
Simulation time 46867876524 ps
CPU time 32.16 seconds
Started Jun 02 02:18:46 PM PDT 24
Finished Jun 02 02:19:18 PM PDT 24
Peak memory 183012 kb
Host smart-1114c294-bd25-41be-821f-80ea123cf923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236531867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2236531867
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3301724928
Short name T68
Test name
Test status
Simulation time 101549219818 ps
CPU time 164.69 seconds
Started Jun 02 02:18:43 PM PDT 24
Finished Jun 02 02:21:28 PM PDT 24
Peak memory 182916 kb
Host smart-6a56878e-1d84-4804-a299-6188ff6f3506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301724928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3301724928
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1547420416
Short name T225
Test name
Test status
Simulation time 562115474087 ps
CPU time 596.32 seconds
Started Jun 02 02:18:45 PM PDT 24
Finished Jun 02 02:28:42 PM PDT 24
Peak memory 194660 kb
Host smart-ddbf4879-6bbf-4005-bdca-dcf1bf71dab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547420416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1547420416
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1288460520
Short name T403
Test name
Test status
Simulation time 30866114157 ps
CPU time 44.84 seconds
Started Jun 02 02:18:47 PM PDT 24
Finished Jun 02 02:19:33 PM PDT 24
Peak memory 182984 kb
Host smart-cf5368eb-d0f1-4917-9834-808233bf5e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288460520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1288460520
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1576548419
Short name T30
Test name
Test status
Simulation time 35966369785 ps
CPU time 18.86 seconds
Started Jun 02 02:18:18 PM PDT 24
Finished Jun 02 02:18:37 PM PDT 24
Peak memory 182900 kb
Host smart-38a4ce97-9cdb-4877-a38b-0c76285acf68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576548419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1576548419
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3404527371
Short name T429
Test name
Test status
Simulation time 5989481641 ps
CPU time 9.23 seconds
Started Jun 02 02:18:12 PM PDT 24
Finished Jun 02 02:18:21 PM PDT 24
Peak memory 182852 kb
Host smart-61abb2dc-d5f2-4c31-8310-2e4af89a42d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404527371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3404527371
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.495440017
Short name T148
Test name
Test status
Simulation time 7277403837 ps
CPU time 13.98 seconds
Started Jun 02 02:18:18 PM PDT 24
Finished Jun 02 02:18:33 PM PDT 24
Peak memory 182988 kb
Host smart-8fa576de-04f4-440d-bbac-b6adc9d0e7d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495440017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.495440017
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.477757368
Short name T447
Test name
Test status
Simulation time 145654422757 ps
CPU time 290.07 seconds
Started Jun 02 02:18:13 PM PDT 24
Finished Jun 02 02:23:04 PM PDT 24
Peak memory 194260 kb
Host smart-9d12dcfe-6892-43cb-bfdf-93ba5e4c2d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477757368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.477757368
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.4007146015
Short name T20
Test name
Test status
Simulation time 135961921 ps
CPU time 1 seconds
Started Jun 02 02:18:11 PM PDT 24
Finished Jun 02 02:18:12 PM PDT 24
Peak memory 214404 kb
Host smart-5ac10cdc-3754-404e-9a1c-27bba652bfa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007146015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4007146015
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2216189989
Short name T61
Test name
Test status
Simulation time 856375452382 ps
CPU time 408.73 seconds
Started Jun 02 02:18:12 PM PDT 24
Finished Jun 02 02:25:01 PM PDT 24
Peak memory 191172 kb
Host smart-dc961c33-86b5-49e8-862e-ed43306fad86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216189989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2216189989
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.92408606
Short name T184
Test name
Test status
Simulation time 746486037601 ps
CPU time 727.72 seconds
Started Jun 02 02:18:43 PM PDT 24
Finished Jun 02 02:30:51 PM PDT 24
Peak memory 182936 kb
Host smart-793d9e67-839b-4edc-a7dc-3c49c516c0ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92408606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.rv_timer_cfg_update_on_fly.92408606
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1740258457
Short name T393
Test name
Test status
Simulation time 48880652826 ps
CPU time 42.83 seconds
Started Jun 02 02:18:45 PM PDT 24
Finished Jun 02 02:19:29 PM PDT 24
Peak memory 183012 kb
Host smart-2f792748-088d-4d21-b77f-6c5b34ab3c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740258457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1740258457
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2173864203
Short name T168
Test name
Test status
Simulation time 596191479472 ps
CPU time 342.32 seconds
Started Jun 02 02:18:46 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 191208 kb
Host smart-f791b4b8-fae3-4f9b-aadf-73a7c8b7cdb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173864203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2173864203
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.336380216
Short name T409
Test name
Test status
Simulation time 160016800359 ps
CPU time 81.45 seconds
Started Jun 02 02:18:47 PM PDT 24
Finished Jun 02 02:20:09 PM PDT 24
Peak memory 191172 kb
Host smart-df5e3de4-07fb-4da4-9c4f-b39afc28c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336380216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.336380216
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.246340915
Short name T317
Test name
Test status
Simulation time 1884314301860 ps
CPU time 1079.32 seconds
Started Jun 02 02:18:43 PM PDT 24
Finished Jun 02 02:36:43 PM PDT 24
Peak memory 182924 kb
Host smart-d8a52df3-4901-4273-978a-23a55124bede
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246340915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.246340915
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3580530494
Short name T370
Test name
Test status
Simulation time 242248523549 ps
CPU time 73.58 seconds
Started Jun 02 02:18:45 PM PDT 24
Finished Jun 02 02:19:59 PM PDT 24
Peak memory 182936 kb
Host smart-5f249598-6f9f-4ff1-aab3-e5827d65dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580530494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3580530494
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2046482195
Short name T361
Test name
Test status
Simulation time 139388024922 ps
CPU time 218.4 seconds
Started Jun 02 02:18:45 PM PDT 24
Finished Jun 02 02:22:24 PM PDT 24
Peak memory 191136 kb
Host smart-ae700978-8272-41fa-b198-e8f38ceab5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046482195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2046482195
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1697562135
Short name T120
Test name
Test status
Simulation time 126035563221 ps
CPU time 129.07 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:20:54 PM PDT 24
Peak memory 191132 kb
Host smart-c1cbec8c-3978-420b-952b-567f4c9e2cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697562135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1697562135
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3075506770
Short name T346
Test name
Test status
Simulation time 6427573386 ps
CPU time 11.88 seconds
Started Jun 02 02:18:47 PM PDT 24
Finished Jun 02 02:19:00 PM PDT 24
Peak memory 183004 kb
Host smart-6bcb9ff4-68f4-46aa-b789-978171b6d791
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075506770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3075506770
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1894957534
Short name T381
Test name
Test status
Simulation time 316296615619 ps
CPU time 220.65 seconds
Started Jun 02 02:18:43 PM PDT 24
Finished Jun 02 02:22:24 PM PDT 24
Peak memory 183000 kb
Host smart-19a97597-744d-48b6-be8b-321eb01a0ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894957534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1894957534
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1272157772
Short name T112
Test name
Test status
Simulation time 327405813039 ps
CPU time 627.84 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:29:12 PM PDT 24
Peak memory 191192 kb
Host smart-77028ac9-90c7-4f1a-9dfe-c776472987e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272157772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1272157772
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.835868806
Short name T363
Test name
Test status
Simulation time 766152792 ps
CPU time 1.63 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:18:46 PM PDT 24
Peak memory 183184 kb
Host smart-9c0dc5cb-0b42-4992-a570-004c367d9389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835868806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.835868806
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3506167347
Short name T53
Test name
Test status
Simulation time 62251162034 ps
CPU time 100.02 seconds
Started Jun 02 02:18:43 PM PDT 24
Finished Jun 02 02:20:23 PM PDT 24
Peak memory 182996 kb
Host smart-d5976f66-ddd6-4a5f-9b4e-d7ae0cda175d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506167347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3506167347
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1804666583
Short name T219
Test name
Test status
Simulation time 51705460122 ps
CPU time 86.07 seconds
Started Jun 02 02:18:45 PM PDT 24
Finished Jun 02 02:20:12 PM PDT 24
Peak memory 191144 kb
Host smart-4191b7cb-d094-48fa-8931-f6962a1d38a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804666583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1804666583
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2166508893
Short name T391
Test name
Test status
Simulation time 150363390 ps
CPU time 0.88 seconds
Started Jun 02 02:18:43 PM PDT 24
Finished Jun 02 02:18:45 PM PDT 24
Peak memory 191352 kb
Host smart-231838bc-de97-4505-a478-5042f60884bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166508893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2166508893
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.875688055
Short name T179
Test name
Test status
Simulation time 1355479527521 ps
CPU time 630.38 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:29:15 PM PDT 24
Peak memory 191456 kb
Host smart-ff686170-8d33-494d-97d1-e486c5995875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875688055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
875688055
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.304122386
Short name T286
Test name
Test status
Simulation time 2903451696057 ps
CPU time 782.5 seconds
Started Jun 02 02:18:43 PM PDT 24
Finished Jun 02 02:31:46 PM PDT 24
Peak memory 182936 kb
Host smart-b6ebe117-059f-488a-95e7-5f5d9088c52a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304122386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.304122386
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.388146749
Short name T369
Test name
Test status
Simulation time 299438046824 ps
CPU time 100.54 seconds
Started Jun 02 02:18:50 PM PDT 24
Finished Jun 02 02:20:31 PM PDT 24
Peak memory 182996 kb
Host smart-69793f6e-371e-4e13-a2a4-b14fcb57bcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388146749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.388146749
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2899738823
Short name T351
Test name
Test status
Simulation time 85522853186 ps
CPU time 125.93 seconds
Started Jun 02 02:18:45 PM PDT 24
Finished Jun 02 02:20:51 PM PDT 24
Peak memory 183000 kb
Host smart-6ced8249-f867-4565-8083-f6f5a86894b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899738823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2899738823
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2296309557
Short name T323
Test name
Test status
Simulation time 1985490936995 ps
CPU time 1677.4 seconds
Started Jun 02 02:18:43 PM PDT 24
Finished Jun 02 02:46:41 PM PDT 24
Peak memory 195868 kb
Host smart-018c81f2-7e13-42c3-858c-d4a97b94941c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296309557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2296309557
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.526095249
Short name T222
Test name
Test status
Simulation time 171945572786 ps
CPU time 263.3 seconds
Started Jun 02 02:18:50 PM PDT 24
Finished Jun 02 02:23:14 PM PDT 24
Peak memory 183000 kb
Host smart-7422c48b-4c55-4eb9-a4cb-97236b02d36e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526095249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.526095249
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.957409695
Short name T419
Test name
Test status
Simulation time 263889035722 ps
CPU time 199.82 seconds
Started Jun 02 02:18:45 PM PDT 24
Finished Jun 02 02:22:05 PM PDT 24
Peak memory 182956 kb
Host smart-d3095672-ca7e-4d2c-81cf-462d327dbef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957409695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.957409695
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3250606881
Short name T145
Test name
Test status
Simulation time 404070240297 ps
CPU time 499.15 seconds
Started Jun 02 02:18:44 PM PDT 24
Finished Jun 02 02:27:04 PM PDT 24
Peak memory 191200 kb
Host smart-4248576d-bc2d-4600-b6ca-5b378c7263d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250606881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3250606881
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1426831615
Short name T268
Test name
Test status
Simulation time 106639007497 ps
CPU time 414.11 seconds
Started Jun 02 02:18:51 PM PDT 24
Finished Jun 02 02:25:46 PM PDT 24
Peak memory 194324 kb
Host smart-47c88910-53da-4986-bca6-bf71be8af741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426831615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1426831615
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3589164372
Short name T130
Test name
Test status
Simulation time 326803346728 ps
CPU time 294.25 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:23:47 PM PDT 24
Peak memory 182956 kb
Host smart-5a2684b7-4173-4020-bb46-2c2a6d725ac0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589164372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3589164372
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1227053385
Short name T412
Test name
Test status
Simulation time 50137796095 ps
CPU time 76.57 seconds
Started Jun 02 02:18:54 PM PDT 24
Finished Jun 02 02:20:11 PM PDT 24
Peak memory 182964 kb
Host smart-343e9d2b-d406-4050-9a19-4270024f42c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227053385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1227053385
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1455522974
Short name T319
Test name
Test status
Simulation time 364551066759 ps
CPU time 254.36 seconds
Started Jun 02 02:18:54 PM PDT 24
Finished Jun 02 02:23:09 PM PDT 24
Peak memory 191204 kb
Host smart-a85b7ac1-63cf-4693-8afd-659b9167b5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455522974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1455522974
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3658497495
Short name T197
Test name
Test status
Simulation time 448453722163 ps
CPU time 527.45 seconds
Started Jun 02 02:18:51 PM PDT 24
Finished Jun 02 02:27:39 PM PDT 24
Peak memory 193528 kb
Host smart-1e4d3212-38af-471f-b452-fa9acac79719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658497495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3658497495
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1494321092
Short name T334
Test name
Test status
Simulation time 350351625654 ps
CPU time 324.88 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:24:18 PM PDT 24
Peak memory 182956 kb
Host smart-42b4eaaa-2d8f-47fa-ba66-f5dfe8db5e28
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494321092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1494321092
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3921985755
Short name T378
Test name
Test status
Simulation time 47357544580 ps
CPU time 60.7 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:19:55 PM PDT 24
Peak memory 182996 kb
Host smart-a263c555-23c0-4678-9026-31393db6e320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921985755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3921985755
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3407225385
Short name T72
Test name
Test status
Simulation time 428998341049 ps
CPU time 92.12 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:20:25 PM PDT 24
Peak memory 191132 kb
Host smart-9048dd00-bc7c-4c0b-a599-0a2fde25c34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407225385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3407225385
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1805641401
Short name T9
Test name
Test status
Simulation time 462535323126 ps
CPU time 600.36 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:28:53 PM PDT 24
Peak memory 191188 kb
Host smart-740624f8-d8a1-4482-a35f-c30203ed80c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805641401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1805641401
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1169308459
Short name T200
Test name
Test status
Simulation time 388433692393 ps
CPU time 187.76 seconds
Started Jun 02 02:18:50 PM PDT 24
Finished Jun 02 02:21:58 PM PDT 24
Peak memory 182916 kb
Host smart-0c700d1d-5580-4235-b33e-116e1a2e4165
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169308459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1169308459
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3059347945
Short name T364
Test name
Test status
Simulation time 128479783743 ps
CPU time 180.22 seconds
Started Jun 02 02:19:04 PM PDT 24
Finished Jun 02 02:22:04 PM PDT 24
Peak memory 182992 kb
Host smart-9266c8ae-2bc6-4a47-a62a-9850ee744a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059347945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3059347945
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4091282332
Short name T430
Test name
Test status
Simulation time 4079015795 ps
CPU time 9.33 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:19:03 PM PDT 24
Peak memory 191212 kb
Host smart-70ccf43e-07ff-4eec-be4a-3fc4e01287f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091282332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4091282332
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1161544955
Short name T277
Test name
Test status
Simulation time 1781294006814 ps
CPU time 708.23 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:30:41 PM PDT 24
Peak memory 191188 kb
Host smart-3dae9208-b111-46b8-b50c-ef94e180f6a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161544955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1161544955
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2645898199
Short name T352
Test name
Test status
Simulation time 3045920244 ps
CPU time 5.73 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:18:59 PM PDT 24
Peak memory 183120 kb
Host smart-131f4318-2424-4490-a560-b87a7df39791
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645898199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2645898199
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1915718690
Short name T367
Test name
Test status
Simulation time 77240840943 ps
CPU time 119.58 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:20:53 PM PDT 24
Peak memory 182992 kb
Host smart-c6cb0fba-164e-4fe1-bbc9-7ed830fc8086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915718690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1915718690
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3986703786
Short name T230
Test name
Test status
Simulation time 694410870418 ps
CPU time 442.39 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:26:15 PM PDT 24
Peak memory 191128 kb
Host smart-c71cadc6-46e6-450b-a1a8-36d3e42e8b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986703786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3986703786
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3413366862
Short name T280
Test name
Test status
Simulation time 216284027623 ps
CPU time 1246.06 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:39:40 PM PDT 24
Peak memory 191200 kb
Host smart-d6bf09b5-43d6-4c07-b4ae-995e9f35d581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413366862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3413366862
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.54426383
Short name T236
Test name
Test status
Simulation time 589409447952 ps
CPU time 597.46 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:28:52 PM PDT 24
Peak memory 195680 kb
Host smart-85e4d8f6-e3b9-4608-864e-354ce468c48b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54426383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.54426383
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.285087136
Short name T237
Test name
Test status
Simulation time 431594859015 ps
CPU time 771.74 seconds
Started Jun 02 02:18:22 PM PDT 24
Finished Jun 02 02:31:14 PM PDT 24
Peak memory 182928 kb
Host smart-a750d8c3-817e-460d-a8aa-e50d517181b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285087136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.285087136
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3349871873
Short name T397
Test name
Test status
Simulation time 46841081594 ps
CPU time 72.3 seconds
Started Jun 02 02:18:14 PM PDT 24
Finished Jun 02 02:19:27 PM PDT 24
Peak memory 182916 kb
Host smart-f7e161eb-65fa-4014-b247-e5921a546662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349871873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3349871873
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2687262333
Short name T169
Test name
Test status
Simulation time 160898103878 ps
CPU time 500.29 seconds
Started Jun 02 02:18:15 PM PDT 24
Finished Jun 02 02:26:36 PM PDT 24
Peak memory 191168 kb
Host smart-030e0d27-701f-44f2-bf9c-aa84c8ac4689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687262333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2687262333
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.539798601
Short name T446
Test name
Test status
Simulation time 82687569499 ps
CPU time 369.66 seconds
Started Jun 02 02:18:19 PM PDT 24
Finished Jun 02 02:24:29 PM PDT 24
Peak memory 183136 kb
Host smart-ec118b65-cec7-40e1-9b23-136bb73738a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539798601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.539798601
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.562414710
Short name T21
Test name
Test status
Simulation time 155329589 ps
CPU time 0.83 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:18:22 PM PDT 24
Peak memory 213396 kb
Host smart-2be9693d-b00d-4118-95d5-452e0f357257
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562414710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.562414710
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2060349793
Short name T141
Test name
Test status
Simulation time 148442785793 ps
CPU time 93.16 seconds
Started Jun 02 02:18:55 PM PDT 24
Finished Jun 02 02:20:28 PM PDT 24
Peak memory 182988 kb
Host smart-e42ffdc8-8254-4e62-aa31-8ea406009fb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060349793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2060349793
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2088719973
Short name T365
Test name
Test status
Simulation time 342258809794 ps
CPU time 53.11 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:19:47 PM PDT 24
Peak memory 182972 kb
Host smart-03e935c9-fb66-4e78-b0c0-b450b03a02bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088719973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2088719973
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3365155447
Short name T3
Test name
Test status
Simulation time 100274506423 ps
CPU time 830.01 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:32:44 PM PDT 24
Peak memory 182972 kb
Host smart-e82eb2f1-179d-45fb-8f42-3e2b530cc9ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365155447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3365155447
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.677305876
Short name T438
Test name
Test status
Simulation time 256694778424 ps
CPU time 281.13 seconds
Started Jun 02 02:19:00 PM PDT 24
Finished Jun 02 02:23:41 PM PDT 24
Peak memory 194240 kb
Host smart-a5ce5191-fc28-4d7b-b22e-ba437a010b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677305876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.677305876
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1170189666
Short name T441
Test name
Test status
Simulation time 369195495851 ps
CPU time 692.74 seconds
Started Jun 02 02:18:54 PM PDT 24
Finished Jun 02 02:30:27 PM PDT 24
Peak memory 182972 kb
Host smart-243dd723-8d5b-4f5b-87ae-5e05d756bdd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170189666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1170189666
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1459006631
Short name T416
Test name
Test status
Simulation time 6776369345 ps
CPU time 4.25 seconds
Started Jun 02 02:19:03 PM PDT 24
Finished Jun 02 02:19:08 PM PDT 24
Peak memory 182852 kb
Host smart-d461fa78-3088-4c75-89fd-b6070ad8cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459006631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1459006631
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2441602762
Short name T337
Test name
Test status
Simulation time 172448802186 ps
CPU time 249.15 seconds
Started Jun 02 02:19:03 PM PDT 24
Finished Jun 02 02:23:12 PM PDT 24
Peak memory 194696 kb
Host smart-41b307a9-5923-4751-bc1e-2e1a277e98e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441602762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2441602762
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3605935340
Short name T385
Test name
Test status
Simulation time 60464622713 ps
CPU time 57.5 seconds
Started Jun 02 02:18:54 PM PDT 24
Finished Jun 02 02:19:52 PM PDT 24
Peak memory 191172 kb
Host smart-a9431454-5245-486c-83a3-84aa69342928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605935340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3605935340
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2335679618
Short name T269
Test name
Test status
Simulation time 674336604511 ps
CPU time 352.34 seconds
Started Jun 02 02:18:54 PM PDT 24
Finished Jun 02 02:24:47 PM PDT 24
Peak memory 191460 kb
Host smart-2e2e5dc8-1347-41ac-902a-22af27f03756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335679618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2335679618
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3862559079
Short name T291
Test name
Test status
Simulation time 136857690701 ps
CPU time 238.04 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:22:51 PM PDT 24
Peak memory 183008 kb
Host smart-b0b867f6-d64f-4d90-9d73-910879c1b08a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862559079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3862559079
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.759357116
Short name T405
Test name
Test status
Simulation time 16940691194 ps
CPU time 28.56 seconds
Started Jun 02 02:18:55 PM PDT 24
Finished Jun 02 02:19:24 PM PDT 24
Peak memory 182936 kb
Host smart-a8e5a3f1-dd4a-41c1-b739-7e5d622149c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759357116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.759357116
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1444401846
Short name T170
Test name
Test status
Simulation time 117635270189 ps
CPU time 216.83 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:22:36 PM PDT 24
Peak memory 191328 kb
Host smart-cc70ba62-af18-4ba9-9980-59eb833da513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444401846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1444401846
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3824737384
Short name T147
Test name
Test status
Simulation time 119516013254 ps
CPU time 39.51 seconds
Started Jun 02 02:18:51 PM PDT 24
Finished Jun 02 02:19:31 PM PDT 24
Peak memory 191112 kb
Host smart-bd714884-906d-4163-981f-199a75b0ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824737384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3824737384
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3425085047
Short name T297
Test name
Test status
Simulation time 427513285262 ps
CPU time 1041.72 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:36:14 PM PDT 24
Peak memory 191136 kb
Host smart-dfad5bdd-9270-4b38-92e2-a0b3a88c9927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425085047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3425085047
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2701267807
Short name T282
Test name
Test status
Simulation time 95708715607 ps
CPU time 150.45 seconds
Started Jun 02 02:18:53 PM PDT 24
Finished Jun 02 02:21:25 PM PDT 24
Peak memory 183004 kb
Host smart-e03956a2-1d2c-4c76-849a-d94109fb5e4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701267807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2701267807
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.501861617
Short name T375
Test name
Test status
Simulation time 25081119533 ps
CPU time 42.74 seconds
Started Jun 02 02:18:52 PM PDT 24
Finished Jun 02 02:19:35 PM PDT 24
Peak memory 182988 kb
Host smart-4ac6c6b1-0cc9-4b87-94cd-c11c496c6be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501861617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.501861617
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.642052971
Short name T153
Test name
Test status
Simulation time 395568248538 ps
CPU time 171.15 seconds
Started Jun 02 02:18:54 PM PDT 24
Finished Jun 02 02:21:46 PM PDT 24
Peak memory 191120 kb
Host smart-95befc7a-0d56-4194-9469-9e490aa73120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642052971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.642052971
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1263937535
Short name T244
Test name
Test status
Simulation time 341755935030 ps
CPU time 187.14 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:22:05 PM PDT 24
Peak memory 182948 kb
Host smart-e16dc344-ee12-4463-b08b-cc50a9c39581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263937535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1263937535
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.7516702
Short name T415
Test name
Test status
Simulation time 548465828816 ps
CPU time 226.52 seconds
Started Jun 02 02:18:59 PM PDT 24
Finished Jun 02 02:22:46 PM PDT 24
Peak memory 183012 kb
Host smart-c324b583-aeec-461d-8245-47f713413b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7516702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.7516702
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1260027839
Short name T84
Test name
Test status
Simulation time 7114053235 ps
CPU time 6.88 seconds
Started Jun 02 02:18:56 PM PDT 24
Finished Jun 02 02:19:03 PM PDT 24
Peak memory 183260 kb
Host smart-a998b841-60bc-4be5-97c7-f9398ded36e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260027839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1260027839
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3793210871
Short name T395
Test name
Test status
Simulation time 286581041222 ps
CPU time 117.7 seconds
Started Jun 02 02:19:04 PM PDT 24
Finished Jun 02 02:21:02 PM PDT 24
Peak memory 182992 kb
Host smart-68695640-ff2e-4e3d-9d61-1cd50e06d370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793210871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3793210871
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2355166958
Short name T425
Test name
Test status
Simulation time 53108427030 ps
CPU time 204.42 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:22:23 PM PDT 24
Peak memory 191180 kb
Host smart-695f75f6-87aa-4786-b5f8-48fb6d66489c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355166958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2355166958
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.102686505
Short name T401
Test name
Test status
Simulation time 123971391996 ps
CPU time 107.98 seconds
Started Jun 02 02:18:59 PM PDT 24
Finished Jun 02 02:20:48 PM PDT 24
Peak memory 183008 kb
Host smart-9be2be20-8069-4b00-b551-caae09692f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102686505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.102686505
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2432805876
Short name T427
Test name
Test status
Simulation time 12563202127 ps
CPU time 99.24 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:20:38 PM PDT 24
Peak memory 197640 kb
Host smart-c3a2f783-063a-4a1b-aafe-e40d176b7e6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432805876 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2432805876
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3039067789
Short name T424
Test name
Test status
Simulation time 12821972581 ps
CPU time 23.21 seconds
Started Jun 02 02:18:57 PM PDT 24
Finished Jun 02 02:19:21 PM PDT 24
Peak memory 183008 kb
Host smart-072dd39a-5b65-4604-a3a5-231ef5e5066c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039067789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3039067789
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2767071435
Short name T383
Test name
Test status
Simulation time 160466850367 ps
CPU time 63.02 seconds
Started Jun 02 02:19:03 PM PDT 24
Finished Jun 02 02:20:06 PM PDT 24
Peak memory 182992 kb
Host smart-e15fc847-f192-437b-af1b-9f2f6ae486a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767071435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2767071435
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.4274926113
Short name T285
Test name
Test status
Simulation time 175799619188 ps
CPU time 151.37 seconds
Started Jun 02 02:19:00 PM PDT 24
Finished Jun 02 02:21:32 PM PDT 24
Peak memory 191100 kb
Host smart-b5ecfa19-382b-4d74-9063-63a4dce8f340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274926113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.4274926113
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1333556669
Short name T440
Test name
Test status
Simulation time 11758939291 ps
CPU time 10.63 seconds
Started Jun 02 02:18:59 PM PDT 24
Finished Jun 02 02:19:10 PM PDT 24
Peak memory 182956 kb
Host smart-9ad9383a-6692-4218-a8ee-4625fb754f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333556669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1333556669
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3431910184
Short name T59
Test name
Test status
Simulation time 3099647196227 ps
CPU time 1085.29 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:37:04 PM PDT 24
Peak memory 191124 kb
Host smart-07e9277b-cf70-4956-ae94-b9f4955c7e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431910184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3431910184
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2555935070
Short name T264
Test name
Test status
Simulation time 221520599173 ps
CPU time 188.52 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:22:07 PM PDT 24
Peak memory 182916 kb
Host smart-f47f1cdb-eb81-4c86-95b9-2f2f93610933
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555935070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2555935070
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3237807228
Short name T384
Test name
Test status
Simulation time 302956654316 ps
CPU time 111.33 seconds
Started Jun 02 02:19:04 PM PDT 24
Finished Jun 02 02:20:55 PM PDT 24
Peak memory 182992 kb
Host smart-ad307c13-4219-4f40-9217-b03c6ed88025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237807228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3237807228
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.4217388067
Short name T314
Test name
Test status
Simulation time 37508950793 ps
CPU time 58.47 seconds
Started Jun 02 02:18:59 PM PDT 24
Finished Jun 02 02:19:58 PM PDT 24
Peak memory 182852 kb
Host smart-6c9e6641-ab47-4629-83da-04d4e5d93674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217388067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4217388067
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3062893652
Short name T115
Test name
Test status
Simulation time 103459892519 ps
CPU time 51.88 seconds
Started Jun 02 02:19:04 PM PDT 24
Finished Jun 02 02:19:56 PM PDT 24
Peak memory 191192 kb
Host smart-cdb17527-36e0-43ef-942b-952160ddc959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062893652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3062893652
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2361467214
Short name T8
Test name
Test status
Simulation time 465564592984 ps
CPU time 253.3 seconds
Started Jun 02 02:19:00 PM PDT 24
Finished Jun 02 02:23:14 PM PDT 24
Peak memory 183008 kb
Host smart-bd3b99e8-0150-4eff-bcfa-ee7764dd2405
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361467214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2361467214
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2555902514
Short name T366
Test name
Test status
Simulation time 89579620015 ps
CPU time 39.68 seconds
Started Jun 02 02:19:00 PM PDT 24
Finished Jun 02 02:19:40 PM PDT 24
Peak memory 182992 kb
Host smart-74d6020f-caa8-493c-9f55-0d185b9f9266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555902514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2555902514
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.109360879
Short name T223
Test name
Test status
Simulation time 416097517144 ps
CPU time 626.47 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:29:25 PM PDT 24
Peak memory 191180 kb
Host smart-21401199-8020-4d0a-817d-674194d453af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109360879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.109360879
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1861633214
Short name T259
Test name
Test status
Simulation time 18798738743 ps
CPU time 28.52 seconds
Started Jun 02 02:18:58 PM PDT 24
Finished Jun 02 02:19:27 PM PDT 24
Peak memory 182844 kb
Host smart-9df512cc-724e-45fa-a55b-14be3ba45021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861633214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1861633214
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4090651587
Short name T67
Test name
Test status
Simulation time 82112878505 ps
CPU time 73.48 seconds
Started Jun 02 02:19:10 PM PDT 24
Finished Jun 02 02:20:24 PM PDT 24
Peak memory 183012 kb
Host smart-e13c6bf9-1fc2-4237-886b-6f105946709f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090651587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.4090651587
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3229652250
Short name T374
Test name
Test status
Simulation time 209843115107 ps
CPU time 86.36 seconds
Started Jun 02 02:19:11 PM PDT 24
Finished Jun 02 02:20:37 PM PDT 24
Peak memory 182988 kb
Host smart-0c2f29be-02cc-4ec4-b9fd-e9cd2da8546a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229652250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3229652250
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.829100077
Short name T188
Test name
Test status
Simulation time 891534896017 ps
CPU time 1331.88 seconds
Started Jun 02 02:19:07 PM PDT 24
Finished Jun 02 02:41:19 PM PDT 24
Peak memory 191376 kb
Host smart-b2950f3a-051d-4357-a56d-7836cce8ca4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829100077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.829100077
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2291229626
Short name T304
Test name
Test status
Simulation time 50449174097 ps
CPU time 1808.24 seconds
Started Jun 02 02:19:10 PM PDT 24
Finished Jun 02 02:49:19 PM PDT 24
Peak memory 191188 kb
Host smart-b3980f1a-6c8a-431f-b7fc-2046bc9552bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291229626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2291229626
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.656395939
Short name T270
Test name
Test status
Simulation time 5257210054453 ps
CPU time 3143.21 seconds
Started Jun 02 02:19:12 PM PDT 24
Finished Jun 02 03:11:36 PM PDT 24
Peak memory 191188 kb
Host smart-5dfd1d0d-b44e-4cc8-8c3e-822153795550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656395939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
656395939
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3814974228
Short name T307
Test name
Test status
Simulation time 304028384287 ps
CPU time 261.07 seconds
Started Jun 02 02:19:11 PM PDT 24
Finished Jun 02 02:23:32 PM PDT 24
Peak memory 182932 kb
Host smart-4697131d-0309-4ead-ac7f-11b3fcf9c226
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814974228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3814974228
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.340707508
Short name T380
Test name
Test status
Simulation time 21785641935 ps
CPU time 34.52 seconds
Started Jun 02 02:19:13 PM PDT 24
Finished Jun 02 02:19:47 PM PDT 24
Peak memory 182996 kb
Host smart-108d0b0c-f158-4367-a166-f393dd47cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340707508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.340707508
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3892449293
Short name T185
Test name
Test status
Simulation time 437275068636 ps
CPU time 313.08 seconds
Started Jun 02 02:19:13 PM PDT 24
Finished Jun 02 02:24:26 PM PDT 24
Peak memory 191192 kb
Host smart-c2e6b0a0-3351-4b96-982d-83ab378985d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892449293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3892449293
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1010724265
Short name T414
Test name
Test status
Simulation time 344527871 ps
CPU time 1.35 seconds
Started Jun 02 02:19:11 PM PDT 24
Finished Jun 02 02:19:13 PM PDT 24
Peak memory 182892 kb
Host smart-b25e581f-b094-497b-a27d-baeadfeecf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010724265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1010724265
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.1728306952
Short name T39
Test name
Test status
Simulation time 26263521476 ps
CPU time 306.36 seconds
Started Jun 02 02:19:10 PM PDT 24
Finished Jun 02 02:24:17 PM PDT 24
Peak memory 197644 kb
Host smart-1998829f-e377-4010-924d-16ba2299d422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728306952 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.1728306952
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1922322842
Short name T353
Test name
Test status
Simulation time 1721627414723 ps
CPU time 1032.44 seconds
Started Jun 02 02:18:17 PM PDT 24
Finished Jun 02 02:35:30 PM PDT 24
Peak memory 182936 kb
Host smart-a1215b8c-47f5-44ea-a418-e02fc5db8eb6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922322842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1922322842
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random.3932394926
Short name T333
Test name
Test status
Simulation time 86481609355 ps
CPU time 50.2 seconds
Started Jun 02 02:18:19 PM PDT 24
Finished Jun 02 02:19:10 PM PDT 24
Peak memory 191192 kb
Host smart-db61cd08-7686-4622-a0bb-eeff5c799783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932394926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3932394926
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2372369232
Short name T390
Test name
Test status
Simulation time 36613532109 ps
CPU time 23.12 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:18:45 PM PDT 24
Peak memory 182932 kb
Host smart-c26511c4-f668-44f2-82b8-9456567d69ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372369232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2372369232
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1366325130
Short name T60
Test name
Test status
Simulation time 706573922946 ps
CPU time 275.07 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:23:00 PM PDT 24
Peak memory 191172 kb
Host smart-667edd0a-6ea1-49f9-89d5-fe087c200c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366325130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1366325130
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3311154620
Short name T255
Test name
Test status
Simulation time 46810892665 ps
CPU time 183.42 seconds
Started Jun 02 02:19:17 PM PDT 24
Finished Jun 02 02:22:20 PM PDT 24
Peak memory 194456 kb
Host smart-15dccfb0-db82-4f1b-b860-3c8ee18127c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311154620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3311154620
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.30901750
Short name T257
Test name
Test status
Simulation time 114087352615 ps
CPU time 197.46 seconds
Started Jun 02 02:19:17 PM PDT 24
Finished Jun 02 02:22:35 PM PDT 24
Peak memory 191188 kb
Host smart-c5726b78-e1c9-4134-ad15-9101b11e06f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30901750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.30901750
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1582826525
Short name T220
Test name
Test status
Simulation time 437979168211 ps
CPU time 161.06 seconds
Started Jun 02 02:19:15 PM PDT 24
Finished Jun 02 02:21:57 PM PDT 24
Peak memory 191192 kb
Host smart-a2db847c-fee5-4e1a-bceb-aec24f91aacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582826525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1582826525
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2325187201
Short name T140
Test name
Test status
Simulation time 157678811985 ps
CPU time 236.13 seconds
Started Jun 02 02:19:18 PM PDT 24
Finished Jun 02 02:23:15 PM PDT 24
Peak memory 191104 kb
Host smart-433a921b-6852-4797-b833-cfb8a7b22e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325187201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2325187201
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.545383841
Short name T411
Test name
Test status
Simulation time 68231009671 ps
CPU time 85.27 seconds
Started Jun 02 02:19:18 PM PDT 24
Finished Jun 02 02:20:44 PM PDT 24
Peak memory 182948 kb
Host smart-4c120a21-bfd7-46fc-808b-4a09831991d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545383841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.545383841
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3810081096
Short name T124
Test name
Test status
Simulation time 431461805418 ps
CPU time 295.74 seconds
Started Jun 02 02:19:21 PM PDT 24
Finished Jun 02 02:24:17 PM PDT 24
Peak memory 191200 kb
Host smart-b75d1b63-3823-440e-af80-372290766c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810081096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3810081096
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.220199321
Short name T420
Test name
Test status
Simulation time 548663669133 ps
CPU time 83.6 seconds
Started Jun 02 02:19:22 PM PDT 24
Finished Jun 02 02:20:46 PM PDT 24
Peak memory 182984 kb
Host smart-49a3fded-bb8a-4334-9afc-8481833f658b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220199321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.220199321
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.115729045
Short name T71
Test name
Test status
Simulation time 444272224627 ps
CPU time 233.42 seconds
Started Jun 02 02:18:23 PM PDT 24
Finished Jun 02 02:22:17 PM PDT 24
Peak memory 182980 kb
Host smart-d490d3a0-70a5-49fe-b32e-f0cf986f3e9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115729045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.115729045
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.377389712
Short name T406
Test name
Test status
Simulation time 62889323764 ps
CPU time 99.35 seconds
Started Jun 02 02:18:22 PM PDT 24
Finished Jun 02 02:20:02 PM PDT 24
Peak memory 183012 kb
Host smart-46135148-cff3-4fc6-92cd-888626474740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377389712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.377389712
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.795970158
Short name T66
Test name
Test status
Simulation time 744778536 ps
CPU time 0.96 seconds
Started Jun 02 02:18:16 PM PDT 24
Finished Jun 02 02:18:18 PM PDT 24
Peak memory 191420 kb
Host smart-1f23f9ca-6b8a-4c28-968b-03f0ca6ecf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795970158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.795970158
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1050908068
Short name T444
Test name
Test status
Simulation time 32903240884 ps
CPU time 118.36 seconds
Started Jun 02 02:19:22 PM PDT 24
Finished Jun 02 02:21:21 PM PDT 24
Peak memory 183256 kb
Host smart-94e254a3-108c-42f4-a2b2-cbc30f475569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050908068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1050908068
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2597838701
Short name T134
Test name
Test status
Simulation time 392841320869 ps
CPU time 153.25 seconds
Started Jun 02 02:19:23 PM PDT 24
Finished Jun 02 02:21:57 PM PDT 24
Peak memory 191100 kb
Host smart-e3213355-2fd8-4c7c-93b7-a2d2c302697b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597838701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2597838701
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2856499232
Short name T65
Test name
Test status
Simulation time 85784522518 ps
CPU time 125.75 seconds
Started Jun 02 02:19:22 PM PDT 24
Finished Jun 02 02:21:28 PM PDT 24
Peak memory 191180 kb
Host smart-7ac1353b-852b-49dc-8b06-22556e650b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856499232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2856499232
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1996684938
Short name T82
Test name
Test status
Simulation time 26398127895 ps
CPU time 42.73 seconds
Started Jun 02 02:19:22 PM PDT 24
Finished Jun 02 02:20:05 PM PDT 24
Peak memory 182924 kb
Host smart-7dd5e10b-3f88-473e-9baa-282c4480badf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996684938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1996684938
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2470051561
Short name T248
Test name
Test status
Simulation time 549339665305 ps
CPU time 370.89 seconds
Started Jun 02 02:19:21 PM PDT 24
Finished Jun 02 02:25:32 PM PDT 24
Peak memory 191140 kb
Host smart-b695df19-5457-403d-b512-53054a82eea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470051561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2470051561
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3516023741
Short name T14
Test name
Test status
Simulation time 35524723948 ps
CPU time 73.33 seconds
Started Jun 02 02:19:22 PM PDT 24
Finished Jun 02 02:20:36 PM PDT 24
Peak memory 191140 kb
Host smart-d6019167-0567-4123-979f-285334f49a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516023741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3516023741
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.330856262
Short name T13
Test name
Test status
Simulation time 197057421267 ps
CPU time 201.45 seconds
Started Jun 02 02:19:30 PM PDT 24
Finished Jun 02 02:22:52 PM PDT 24
Peak memory 191188 kb
Host smart-530e08aa-642e-4efe-8694-49bcd8cd0551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330856262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.330856262
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2154086144
Short name T340
Test name
Test status
Simulation time 105572386401 ps
CPU time 87.68 seconds
Started Jun 02 02:19:31 PM PDT 24
Finished Jun 02 02:20:59 PM PDT 24
Peak memory 193384 kb
Host smart-599f0aa0-f9e3-4a24-a830-aabb698c1960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154086144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2154086144
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1189670604
Short name T443
Test name
Test status
Simulation time 723720569132 ps
CPU time 498.96 seconds
Started Jun 02 02:19:30 PM PDT 24
Finished Jun 02 02:27:50 PM PDT 24
Peak memory 190840 kb
Host smart-72a09068-7884-4337-94bf-57217e52b4fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189670604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1189670604
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.282683248
Short name T111
Test name
Test status
Simulation time 175539367934 ps
CPU time 519.15 seconds
Started Jun 02 02:19:28 PM PDT 24
Finished Jun 02 02:28:08 PM PDT 24
Peak memory 191140 kb
Host smart-1b915ee7-e5f2-4a62-8a91-e4c61af88da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282683248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.282683248
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3627492547
Short name T47
Test name
Test status
Simulation time 29856528413 ps
CPU time 15.63 seconds
Started Jun 02 02:18:17 PM PDT 24
Finished Jun 02 02:18:33 PM PDT 24
Peak memory 182968 kb
Host smart-e2879404-d719-4810-bc7a-50568b9dcc83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627492547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3627492547
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2156140652
Short name T368
Test name
Test status
Simulation time 235357002025 ps
CPU time 158.75 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:21:03 PM PDT 24
Peak memory 182928 kb
Host smart-06ab4301-c02a-4b3e-9fd8-2347b3075959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156140652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2156140652
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1025585753
Short name T221
Test name
Test status
Simulation time 161601968952 ps
CPU time 638.35 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:29:00 PM PDT 24
Peak memory 182992 kb
Host smart-d9af6e24-8e80-4aad-ae11-964e1b666c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025585753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1025585753
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1661550131
Short name T23
Test name
Test status
Simulation time 139016870940 ps
CPU time 60.24 seconds
Started Jun 02 02:18:16 PM PDT 24
Finished Jun 02 02:19:17 PM PDT 24
Peak memory 183012 kb
Host smart-9d8ad485-ec33-4268-ba38-8c227d8d7aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661550131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1661550131
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.977810521
Short name T232
Test name
Test status
Simulation time 276239730285 ps
CPU time 1750.75 seconds
Started Jun 02 02:19:30 PM PDT 24
Finished Jun 02 02:48:42 PM PDT 24
Peak memory 190644 kb
Host smart-b661a48d-e8d8-4011-8717-7468b1a555d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977810521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.977810521
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.4278294764
Short name T144
Test name
Test status
Simulation time 39201362874 ps
CPU time 1225.91 seconds
Started Jun 02 02:19:29 PM PDT 24
Finished Jun 02 02:39:55 PM PDT 24
Peak memory 194456 kb
Host smart-caf4cfef-7074-4a6e-b41e-a0dd86782eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278294764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.4278294764
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.569528367
Short name T85
Test name
Test status
Simulation time 487951939187 ps
CPU time 132.72 seconds
Started Jun 02 02:19:29 PM PDT 24
Finished Jun 02 02:21:42 PM PDT 24
Peak memory 191168 kb
Host smart-c267aec5-df4e-4f8f-9fec-e86684a6260d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569528367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.569528367
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3827758328
Short name T51
Test name
Test status
Simulation time 185062263509 ps
CPU time 111.5 seconds
Started Jun 02 02:19:28 PM PDT 24
Finished Jun 02 02:21:20 PM PDT 24
Peak memory 182960 kb
Host smart-a776be50-b8a4-4f72-8384-ffe6f3557a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827758328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3827758328
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3131527962
Short name T433
Test name
Test status
Simulation time 185020579097 ps
CPU time 88.64 seconds
Started Jun 02 02:19:35 PM PDT 24
Finished Jun 02 02:21:04 PM PDT 24
Peak memory 191328 kb
Host smart-2f8b4c7c-734d-4de9-8f66-93d6751dbe28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131527962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3131527962
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3199677714
Short name T70
Test name
Test status
Simulation time 244016153364 ps
CPU time 124.57 seconds
Started Jun 02 02:19:35 PM PDT 24
Finished Jun 02 02:21:40 PM PDT 24
Peak memory 191208 kb
Host smart-5522dbba-a4d5-478e-a89b-dafe71197bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199677714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3199677714
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2437955229
Short name T154
Test name
Test status
Simulation time 179745086117 ps
CPU time 351.71 seconds
Started Jun 02 02:19:35 PM PDT 24
Finished Jun 02 02:25:27 PM PDT 24
Peak memory 191192 kb
Host smart-f8700989-c3af-4669-858d-f0839a102421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437955229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2437955229
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1448724165
Short name T332
Test name
Test status
Simulation time 70474353788 ps
CPU time 211.51 seconds
Started Jun 02 02:19:34 PM PDT 24
Finished Jun 02 02:23:06 PM PDT 24
Peak memory 182924 kb
Host smart-ecd54c47-cb13-4142-ab1a-85e02291e90a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448724165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1448724165
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.328279979
Short name T322
Test name
Test status
Simulation time 607995051543 ps
CPU time 292.22 seconds
Started Jun 02 02:18:16 PM PDT 24
Finished Jun 02 02:23:09 PM PDT 24
Peak memory 182996 kb
Host smart-26c11889-5cf3-4113-9ee1-b7535c2d1898
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328279979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.328279979
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3935973008
Short name T394
Test name
Test status
Simulation time 563473577298 ps
CPU time 128.28 seconds
Started Jun 02 02:18:19 PM PDT 24
Finished Jun 02 02:20:28 PM PDT 24
Peak memory 183124 kb
Host smart-ca18b85e-1326-40b9-a171-c23d3bf3f28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935973008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3935973008
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3346453621
Short name T281
Test name
Test status
Simulation time 139739321094 ps
CPU time 1057.89 seconds
Started Jun 02 02:18:25 PM PDT 24
Finished Jun 02 02:36:03 PM PDT 24
Peak memory 190852 kb
Host smart-588b242b-d6db-445d-92f0-ae034b4c2f62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346453621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3346453621
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1581751530
Short name T388
Test name
Test status
Simulation time 8903946718 ps
CPU time 14.56 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:18:36 PM PDT 24
Peak memory 182944 kb
Host smart-b531daed-23de-4fd4-a868-96d1c17f3f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581751530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1581751530
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3913898062
Short name T44
Test name
Test status
Simulation time 236274616749 ps
CPU time 463.07 seconds
Started Jun 02 02:18:17 PM PDT 24
Finished Jun 02 02:26:01 PM PDT 24
Peak memory 205864 kb
Host smart-87e70387-4cfe-47bd-96bc-6a2d2f6d8091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913898062 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.3913898062
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1435431617
Short name T5
Test name
Test status
Simulation time 1963729540296 ps
CPU time 453.94 seconds
Started Jun 02 02:19:35 PM PDT 24
Finished Jun 02 02:27:10 PM PDT 24
Peak memory 191140 kb
Host smart-d42c5261-9a58-4e8a-8b65-17f23a46d520
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435431617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1435431617
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.4038526619
Short name T176
Test name
Test status
Simulation time 596860068275 ps
CPU time 484.63 seconds
Started Jun 02 02:19:34 PM PDT 24
Finished Jun 02 02:27:39 PM PDT 24
Peak memory 191128 kb
Host smart-43b3b94a-9c42-42e5-886a-2112be603b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038526619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4038526619
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1927990904
Short name T303
Test name
Test status
Simulation time 20129321156 ps
CPU time 19.78 seconds
Started Jun 02 02:19:43 PM PDT 24
Finished Jun 02 02:20:03 PM PDT 24
Peak memory 191148 kb
Host smart-97c99fae-adf3-4dff-b3c1-c3ada7955501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927990904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1927990904
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2611033196
Short name T347
Test name
Test status
Simulation time 44290848750 ps
CPU time 64.03 seconds
Started Jun 02 02:19:41 PM PDT 24
Finished Jun 02 02:20:45 PM PDT 24
Peak memory 182936 kb
Host smart-e4ffd2db-e182-4e5d-8bd6-0e69603ca7c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611033196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2611033196
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.683594447
Short name T278
Test name
Test status
Simulation time 279996455187 ps
CPU time 234.68 seconds
Started Jun 02 02:19:41 PM PDT 24
Finished Jun 02 02:23:36 PM PDT 24
Peak memory 191444 kb
Host smart-0240c026-49ef-40a3-b9e2-68ef358d71a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683594447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.683594447
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.299615746
Short name T117
Test name
Test status
Simulation time 135009644185 ps
CPU time 471.5 seconds
Started Jun 02 02:19:41 PM PDT 24
Finished Jun 02 02:27:33 PM PDT 24
Peak memory 191196 kb
Host smart-d7fad717-d0ac-4d64-ade2-6c1669834412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299615746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.299615746
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2454486664
Short name T344
Test name
Test status
Simulation time 94513566182 ps
CPU time 557.57 seconds
Started Jun 02 02:19:41 PM PDT 24
Finished Jun 02 02:28:58 PM PDT 24
Peak memory 191124 kb
Host smart-1adc25bc-774c-48a3-936a-21d4b2d0fa1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454486664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2454486664
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1679610725
Short name T300
Test name
Test status
Simulation time 38348442465 ps
CPU time 62.74 seconds
Started Jun 02 02:19:42 PM PDT 24
Finished Jun 02 02:20:45 PM PDT 24
Peak memory 194760 kb
Host smart-37d7cb19-eef2-4ad2-a3f6-b4608e5dcf7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679610725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1679610725
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.122414936
Short name T110
Test name
Test status
Simulation time 326983115867 ps
CPU time 169.43 seconds
Started Jun 02 02:18:23 PM PDT 24
Finished Jun 02 02:21:13 PM PDT 24
Peak memory 182968 kb
Host smart-7ad24e24-95b8-4bf9-8852-62920b3f1150
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122414936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.122414936
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2798994184
Short name T389
Test name
Test status
Simulation time 260612807925 ps
CPU time 56.5 seconds
Started Jun 02 02:18:24 PM PDT 24
Finished Jun 02 02:19:21 PM PDT 24
Peak memory 182912 kb
Host smart-54563b25-fe2e-4bc0-823b-5caef2a806b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798994184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2798994184
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2362074744
Short name T263
Test name
Test status
Simulation time 178854377275 ps
CPU time 110.5 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:20:11 PM PDT 24
Peak memory 191192 kb
Host smart-9860084b-420f-438d-9bb0-d79b1e4f5e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362074744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2362074744
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1800265811
Short name T86
Test name
Test status
Simulation time 2338362397 ps
CPU time 1.71 seconds
Started Jun 02 02:18:15 PM PDT 24
Finished Jun 02 02:18:17 PM PDT 24
Peak memory 182952 kb
Host smart-19e5b6d0-0a6a-47ac-ac29-acf184a80c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800265811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1800265811
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3589809323
Short name T31
Test name
Test status
Simulation time 44568297422 ps
CPU time 66.9 seconds
Started Jun 02 02:18:21 PM PDT 24
Finished Jun 02 02:19:28 PM PDT 24
Peak memory 182988 kb
Host smart-5743457d-3740-42ee-ba29-13566e20e70d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589809323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3589809323
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2147463932
Short name T16
Test name
Test status
Simulation time 20611413398 ps
CPU time 166.02 seconds
Started Jun 02 02:18:18 PM PDT 24
Finished Jun 02 02:21:05 PM PDT 24
Peak memory 197636 kb
Host smart-f4f4b0e3-483f-45d4-b306-26030103a03a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147463932 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2147463932
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2460388313
Short name T64
Test name
Test status
Simulation time 71881553686 ps
CPU time 212.54 seconds
Started Jun 02 02:19:41 PM PDT 24
Finished Jun 02 02:23:14 PM PDT 24
Peak memory 191160 kb
Host smart-fd79896d-e831-455b-8f79-a7dd14b08b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460388313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2460388313
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2689861311
Short name T125
Test name
Test status
Simulation time 919305561859 ps
CPU time 1228.34 seconds
Started Jun 02 02:19:41 PM PDT 24
Finished Jun 02 02:40:10 PM PDT 24
Peak memory 191140 kb
Host smart-a2239c9b-4173-4da4-8d00-4faa953d33a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689861311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2689861311
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3733468933
Short name T45
Test name
Test status
Simulation time 497059202812 ps
CPU time 224.46 seconds
Started Jun 02 02:19:52 PM PDT 24
Finished Jun 02 02:23:36 PM PDT 24
Peak memory 191200 kb
Host smart-ea5da202-ec24-4f8f-8645-44861baaaa1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733468933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3733468933
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3947885145
Short name T342
Test name
Test status
Simulation time 50025601952 ps
CPU time 24.9 seconds
Started Jun 02 02:19:47 PM PDT 24
Finished Jun 02 02:20:13 PM PDT 24
Peak memory 182984 kb
Host smart-a78808e7-7afd-4c93-b9f5-30b3390c2bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947885145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3947885145
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3879573928
Short name T26
Test name
Test status
Simulation time 167361668743 ps
CPU time 207.11 seconds
Started Jun 02 02:19:48 PM PDT 24
Finished Jun 02 02:23:16 PM PDT 24
Peak memory 192184 kb
Host smart-fa123647-948d-4d26-93c7-46e87657ddf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879573928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3879573928
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3539107610
Short name T293
Test name
Test status
Simulation time 16531403690 ps
CPU time 22.51 seconds
Started Jun 02 02:19:51 PM PDT 24
Finished Jun 02 02:20:14 PM PDT 24
Peak memory 191200 kb
Host smart-8bc625bb-f39e-4cc4-a886-cead1e6393fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539107610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3539107610
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.40401926
Short name T208
Test name
Test status
Simulation time 91089207017 ps
CPU time 152.59 seconds
Started Jun 02 02:19:52 PM PDT 24
Finished Jun 02 02:22:25 PM PDT 24
Peak memory 191204 kb
Host smart-04802c88-8b2e-46d5-a879-5f60892266cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40401926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.40401926
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3573296698
Short name T289
Test name
Test status
Simulation time 681250987284 ps
CPU time 1460.88 seconds
Started Jun 02 02:19:48 PM PDT 24
Finished Jun 02 02:44:10 PM PDT 24
Peak memory 191376 kb
Host smart-ce5a3eb8-a6af-490f-8872-a5d254783c5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573296698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3573296698
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2017638438
Short name T345
Test name
Test status
Simulation time 30745757228 ps
CPU time 43.69 seconds
Started Jun 02 02:19:49 PM PDT 24
Finished Jun 02 02:20:33 PM PDT 24
Peak memory 182796 kb
Host smart-fab7eab6-8386-4c96-88c8-1ac64479b6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017638438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2017638438
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3034714599
Short name T329
Test name
Test status
Simulation time 283443255005 ps
CPU time 148.86 seconds
Started Jun 02 02:19:48 PM PDT 24
Finished Jun 02 02:22:17 PM PDT 24
Peak memory 191176 kb
Host smart-34b4b8f2-74ea-4ca2-920a-b8d85385666c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034714599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3034714599
Directory /workspace/99.rv_timer_random/latest
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