Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T510 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2343795265 Jun 04 12:23:32 PM PDT 24 Jun 04 12:23:35 PM PDT 24 36374742 ps
T511 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2877973459 Jun 04 12:23:45 PM PDT 24 Jun 04 12:23:47 PM PDT 24 39318482 ps
T512 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1171414750 Jun 04 12:23:40 PM PDT 24 Jun 04 12:23:41 PM PDT 24 14236952 ps
T79 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1043257487 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:32 PM PDT 24 70771039 ps
T513 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2282301938 Jun 04 12:21:52 PM PDT 24 Jun 04 12:21:54 PM PDT 24 146480931 ps
T514 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.524251806 Jun 04 12:19:43 PM PDT 24 Jun 04 12:19:46 PM PDT 24 399582306 ps
T515 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1113781573 Jun 04 12:18:47 PM PDT 24 Jun 04 12:18:48 PM PDT 24 278352087 ps
T80 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2502997194 Jun 04 12:24:01 PM PDT 24 Jun 04 12:24:04 PM PDT 24 128396116 ps
T516 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.852821612 Jun 04 12:18:40 PM PDT 24 Jun 04 12:18:41 PM PDT 24 43716622 ps
T517 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.727649873 Jun 04 12:24:01 PM PDT 24 Jun 04 12:24:03 PM PDT 24 30078929 ps
T518 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2684429890 Jun 04 12:23:39 PM PDT 24 Jun 04 12:23:41 PM PDT 24 30590378 ps
T519 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.387763184 Jun 04 12:23:28 PM PDT 24 Jun 04 12:23:32 PM PDT 24 53093321 ps
T520 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3894003844 Jun 04 12:23:17 PM PDT 24 Jun 04 12:23:19 PM PDT 24 40142069 ps
T521 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3427563106 Jun 04 12:18:47 PM PDT 24 Jun 04 12:18:48 PM PDT 24 38869651 ps
T522 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2168393623 Jun 04 12:23:38 PM PDT 24 Jun 04 12:23:42 PM PDT 24 250896232 ps
T523 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1934912208 Jun 04 12:22:33 PM PDT 24 Jun 04 12:22:34 PM PDT 24 89305444 ps
T524 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3213538268 Jun 04 12:18:36 PM PDT 24 Jun 04 12:18:38 PM PDT 24 188608529 ps
T525 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.492628699 Jun 04 12:18:35 PM PDT 24 Jun 04 12:18:36 PM PDT 24 45776867 ps
T526 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2389100792 Jun 04 12:19:39 PM PDT 24 Jun 04 12:19:40 PM PDT 24 40783810 ps
T527 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.11822148 Jun 04 12:23:32 PM PDT 24 Jun 04 12:23:36 PM PDT 24 236178475 ps
T528 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1260995633 Jun 04 12:22:24 PM PDT 24 Jun 04 12:22:28 PM PDT 24 433020999 ps
T529 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.281343174 Jun 04 12:20:18 PM PDT 24 Jun 04 12:20:20 PM PDT 24 517210205 ps
T530 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1758481647 Jun 04 12:18:25 PM PDT 24 Jun 04 12:18:26 PM PDT 24 15462766 ps
T531 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2648064471 Jun 04 12:23:14 PM PDT 24 Jun 04 12:23:16 PM PDT 24 13044843 ps
T532 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3237335088 Jun 04 12:23:44 PM PDT 24 Jun 04 12:23:46 PM PDT 24 120263182 ps
T533 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2540081296 Jun 04 12:23:04 PM PDT 24 Jun 04 12:23:06 PM PDT 24 36985934 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.96964671 Jun 04 12:23:32 PM PDT 24 Jun 04 12:23:37 PM PDT 24 98900387 ps
T81 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2045532906 Jun 04 12:18:46 PM PDT 24 Jun 04 12:18:47 PM PDT 24 25716687 ps
T535 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4211386253 Jun 04 12:21:45 PM PDT 24 Jun 04 12:21:47 PM PDT 24 330065316 ps
T83 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1657430553 Jun 04 12:23:33 PM PDT 24 Jun 04 12:23:36 PM PDT 24 52358036 ps
T536 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3923112077 Jun 04 12:23:32 PM PDT 24 Jun 04 12:23:36 PM PDT 24 121515012 ps
T82 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.323149441 Jun 04 12:23:20 PM PDT 24 Jun 04 12:23:23 PM PDT 24 23183802 ps
T537 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1957561833 Jun 04 12:24:00 PM PDT 24 Jun 04 12:24:02 PM PDT 24 152057841 ps
T538 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.267496769 Jun 04 12:23:59 PM PDT 24 Jun 04 12:24:01 PM PDT 24 64573944 ps
T539 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.54692396 Jun 04 12:24:03 PM PDT 24 Jun 04 12:24:06 PM PDT 24 276124337 ps
T540 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2764489307 Jun 04 12:18:47 PM PDT 24 Jun 04 12:18:49 PM PDT 24 70589505 ps
T541 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.202409927 Jun 04 12:22:34 PM PDT 24 Jun 04 12:22:36 PM PDT 24 10657631 ps
T542 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1531008802 Jun 04 12:22:15 PM PDT 24 Jun 04 12:22:17 PM PDT 24 32805980 ps
T543 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.713702068 Jun 04 12:23:43 PM PDT 24 Jun 04 12:23:44 PM PDT 24 44785354 ps
T544 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3368044851 Jun 04 12:23:20 PM PDT 24 Jun 04 12:23:22 PM PDT 24 20897319 ps
T545 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1704899284 Jun 04 12:23:38 PM PDT 24 Jun 04 12:23:40 PM PDT 24 10704028 ps
T84 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.369592932 Jun 04 12:23:56 PM PDT 24 Jun 04 12:23:58 PM PDT 24 28687907 ps
T546 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3755875906 Jun 04 12:24:17 PM PDT 24 Jun 04 12:24:21 PM PDT 24 108434288 ps
T547 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.91139399 Jun 04 12:23:11 PM PDT 24 Jun 04 12:23:12 PM PDT 24 57871414 ps
T548 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4146943034 Jun 04 12:23:05 PM PDT 24 Jun 04 12:23:06 PM PDT 24 26964944 ps
T85 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2675504844 Jun 04 12:24:01 PM PDT 24 Jun 04 12:24:07 PM PDT 24 973216572 ps
T86 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2162346176 Jun 04 12:23:41 PM PDT 24 Jun 04 12:23:42 PM PDT 24 14922497 ps
T549 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1700989266 Jun 04 12:21:39 PM PDT 24 Jun 04 12:21:40 PM PDT 24 13528418 ps
T550 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.493259599 Jun 04 12:24:01 PM PDT 24 Jun 04 12:24:03 PM PDT 24 17653324 ps
T551 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2677722428 Jun 04 12:23:59 PM PDT 24 Jun 04 12:24:00 PM PDT 24 52634184 ps
T552 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2266456446 Jun 04 12:23:54 PM PDT 24 Jun 04 12:23:56 PM PDT 24 34655550 ps
T553 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3963301426 Jun 04 12:19:43 PM PDT 24 Jun 04 12:19:45 PM PDT 24 55972374 ps
T554 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3673053110 Jun 04 12:18:50 PM PDT 24 Jun 04 12:18:51 PM PDT 24 13031666 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1597198423 Jun 04 12:23:04 PM PDT 24 Jun 04 12:23:07 PM PDT 24 18341434 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.550567652 Jun 04 12:19:40 PM PDT 24 Jun 04 12:19:42 PM PDT 24 409515503 ps
T557 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1248932736 Jun 04 12:24:01 PM PDT 24 Jun 04 12:24:03 PM PDT 24 22881005 ps
T87 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1802242696 Jun 04 12:24:00 PM PDT 24 Jun 04 12:24:02 PM PDT 24 87316508 ps
T558 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3846314268 Jun 04 12:23:39 PM PDT 24 Jun 04 12:23:42 PM PDT 24 75924283 ps
T559 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3015580177 Jun 04 12:23:17 PM PDT 24 Jun 04 12:23:19 PM PDT 24 49596241 ps
T560 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.30364546 Jun 04 12:23:29 PM PDT 24 Jun 04 12:23:32 PM PDT 24 94375649 ps
T561 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1005179997 Jun 04 12:21:38 PM PDT 24 Jun 04 12:21:39 PM PDT 24 54546180 ps
T562 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4109800921 Jun 04 12:18:41 PM PDT 24 Jun 04 12:18:42 PM PDT 24 12581734 ps
T563 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3400133498 Jun 04 12:23:14 PM PDT 24 Jun 04 12:23:16 PM PDT 24 45316008 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1553452520 Jun 04 12:23:44 PM PDT 24 Jun 04 12:23:46 PM PDT 24 16382135 ps
T565 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3447523493 Jun 04 12:20:14 PM PDT 24 Jun 04 12:20:16 PM PDT 24 101832112 ps
T566 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1076849002 Jun 04 12:21:43 PM PDT 24 Jun 04 12:21:44 PM PDT 24 38130773 ps
T567 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.31032310 Jun 04 12:23:07 PM PDT 24 Jun 04 12:23:10 PM PDT 24 27565799 ps
T568 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1604072721 Jun 04 12:23:44 PM PDT 24 Jun 04 12:23:46 PM PDT 24 37997907 ps
T569 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1942676863 Jun 04 12:23:06 PM PDT 24 Jun 04 12:23:10 PM PDT 24 59137262 ps
T570 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3163250202 Jun 04 12:23:17 PM PDT 24 Jun 04 12:23:19 PM PDT 24 18003971 ps
T571 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4181968571 Jun 04 12:23:44 PM PDT 24 Jun 04 12:23:46 PM PDT 24 45884390 ps
T572 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1228747890 Jun 04 12:23:13 PM PDT 24 Jun 04 12:23:15 PM PDT 24 15197664 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3859745366 Jun 04 12:23:05 PM PDT 24 Jun 04 12:23:08 PM PDT 24 72582551 ps
T574 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1544640186 Jun 04 12:24:02 PM PDT 24 Jun 04 12:24:05 PM PDT 24 16408001 ps
T575 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2028923488 Jun 04 12:20:22 PM PDT 24 Jun 04 12:20:23 PM PDT 24 132990563 ps
T576 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.305619464 Jun 04 12:23:32 PM PDT 24 Jun 04 12:23:35 PM PDT 24 48621264 ps
T577 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2730193349 Jun 04 12:22:32 PM PDT 24 Jun 04 12:22:34 PM PDT 24 24277247 ps
T578 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3684058987 Jun 04 12:24:00 PM PDT 24 Jun 04 12:24:02 PM PDT 24 62954264 ps
T579 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3403479015 Jun 04 12:23:20 PM PDT 24 Jun 04 12:23:22 PM PDT 24 18328630 ps
T580 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3555909524 Jun 04 12:23:07 PM PDT 24 Jun 04 12:23:09 PM PDT 24 12483606 ps

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1811150807
Short name T5
Test name
Test status
Simulation time 20129740292 ps
CPU time 153.82 seconds
Started Jun 04 12:23:35 PM PDT 24
Finished Jun 04 12:26:11 PM PDT 24
Peak memory 197420 kb
Host smart-e42eeace-787e-477c-b1a8-7f7ead4d34c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811150807 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.1811150807
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.rv_timer_random.4194347429
Short name T4
Test name
Test status
Simulation time 444135182121 ps
CPU time 323.37 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:30:04 PM PDT 24
Peak memory 193488 kb
Host smart-8f33574f-a00f-451c-9d3e-f8ec7c51d6b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194347429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.4194347429
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3545041204
Short name T217
Test name
Test status
Simulation time 3584824853436 ps
CPU time 1575.28 seconds
Started Jun 04 12:24:18 PM PDT 24
Finished Jun 04 12:50:35 PM PDT 24
Peak memory 190960 kb
Host smart-aa804f37-1a22-4e8a-8f49-399d3caa9937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545041204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3545041204
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2702314599
Short name T47
Test name
Test status
Simulation time 242904967 ps
CPU time 1.34 seconds
Started Jun 04 12:24:02 PM PDT 24
Finished Jun 04 12:24:06 PM PDT 24
Peak memory 195304 kb
Host smart-b9708ca9-6da3-4f56-b35c-85bed3c345f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702314599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2702314599
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3286075655
Short name T32
Test name
Test status
Simulation time 43359050 ps
CPU time 0.55 seconds
Started Jun 04 12:23:12 PM PDT 24
Finished Jun 04 12:23:13 PM PDT 24
Peak memory 181800 kb
Host smart-5f71dd80-36e2-4864-a3ae-eba844cf748e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286075655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3286075655
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2195599375
Short name T135
Test name
Test status
Simulation time 594842221619 ps
CPU time 1110.45 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:42:42 PM PDT 24
Peak memory 190948 kb
Host smart-3661be47-b25b-4b0d-ba5f-2ef22a3d3295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195599375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2195599375
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3649848586
Short name T58
Test name
Test status
Simulation time 2793585556124 ps
CPU time 1035.75 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:41:35 PM PDT 24
Peak memory 191092 kb
Host smart-87c949d0-56ef-47c8-8c1a-2d7f396d6c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649848586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3649848586
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2796608043
Short name T153
Test name
Test status
Simulation time 478567270501 ps
CPU time 1991.3 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:57:22 PM PDT 24
Peak memory 191000 kb
Host smart-136fa3b1-63b0-42a8-9bfc-632b69e98022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796608043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2796608043
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3412664763
Short name T162
Test name
Test status
Simulation time 2412820941466 ps
CPU time 2811.74 seconds
Started Jun 04 12:24:05 PM PDT 24
Finished Jun 04 01:10:59 PM PDT 24
Peak memory 190436 kb
Host smart-2451b756-e5b1-4599-ac83-5ec86ee03524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412664763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3412664763
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3330580879
Short name T61
Test name
Test status
Simulation time 711471197606 ps
CPU time 975.5 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:39:36 PM PDT 24
Peak memory 190984 kb
Host smart-2ff3daf2-af27-457e-bccc-4e0b1516479c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330580879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3330580879
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.668470776
Short name T224
Test name
Test status
Simulation time 1112493514952 ps
CPU time 1541.82 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:50:00 PM PDT 24
Peak memory 196080 kb
Host smart-d083ef3c-5d62-4ddb-9621-89c51c67be5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668470776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
668470776
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1537848160
Short name T183
Test name
Test status
Simulation time 2346225505633 ps
CPU time 1510.69 seconds
Started Jun 04 12:22:51 PM PDT 24
Finished Jun 04 12:48:03 PM PDT 24
Peak memory 191048 kb
Host smart-d1dab577-d01e-48d3-a38c-3194d916b0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537848160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1537848160
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2512854916
Short name T159
Test name
Test status
Simulation time 342790159386 ps
CPU time 1536.83 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:49:53 PM PDT 24
Peak memory 195528 kb
Host smart-1fbd790b-8e9c-4cef-82fd-5d2cdcf2d494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512854916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2512854916
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.3995989542
Short name T245
Test name
Test status
Simulation time 162763241815 ps
CPU time 268.45 seconds
Started Jun 04 12:24:45 PM PDT 24
Finished Jun 04 12:29:15 PM PDT 24
Peak memory 190932 kb
Host smart-afb3d263-ee96-48a2-97d2-5e7c6531de13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995989542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3995989542
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2313364019
Short name T149
Test name
Test status
Simulation time 4130935829278 ps
CPU time 2608.85 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 01:07:43 PM PDT 24
Peak memory 194756 kb
Host smart-3fd546ab-daef-4297-813b-fc02f3b05e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313364019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2313364019
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.464046084
Short name T11
Test name
Test status
Simulation time 164575911 ps
CPU time 0.91 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:17 PM PDT 24
Peak memory 213852 kb
Host smart-6a944c5b-cf17-4e3b-8868-3374e3ed9917
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464046084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.464046084
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/135.rv_timer_random.155516942
Short name T242
Test name
Test status
Simulation time 79722115193 ps
CPU time 143.22 seconds
Started Jun 04 12:24:30 PM PDT 24
Finished Jun 04 12:26:54 PM PDT 24
Peak memory 190988 kb
Host smart-e3d9c8e4-7e75-4114-b0e1-f35a84f3af94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155516942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.155516942
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.2410356707
Short name T24
Test name
Test status
Simulation time 130681935610 ps
CPU time 200.32 seconds
Started Jun 04 12:24:29 PM PDT 24
Finished Jun 04 12:27:50 PM PDT 24
Peak memory 190996 kb
Host smart-0886708a-47da-46c1-b5bb-2441791bcd1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410356707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2410356707
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2644642440
Short name T204
Test name
Test status
Simulation time 265007319212 ps
CPU time 2676 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 01:08:52 PM PDT 24
Peak memory 190660 kb
Host smart-fcdaa1eb-2b49-4f04-abf8-de9dbf47d06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644642440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2644642440
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/173.rv_timer_random.3129644745
Short name T53
Test name
Test status
Simulation time 183964778989 ps
CPU time 451.66 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:32:14 PM PDT 24
Peak memory 190992 kb
Host smart-32fb2d7d-1197-4073-a476-3db94e479552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129644745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3129644745
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.859711005
Short name T225
Test name
Test status
Simulation time 3441093387981 ps
CPU time 1895.11 seconds
Started Jun 04 12:22:40 PM PDT 24
Finished Jun 04 12:54:16 PM PDT 24
Peak memory 195448 kb
Host smart-9821959a-0630-41f0-93cb-24bde1e91c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859711005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.859711005
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.135699323
Short name T68
Test name
Test status
Simulation time 1007508132103 ps
CPU time 1399.07 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:47:55 PM PDT 24
Peak memory 191112 kb
Host smart-4ddaca81-553d-42e5-bdc8-083ede743672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135699323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.135699323
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2516367511
Short name T96
Test name
Test status
Simulation time 630035072020 ps
CPU time 620.44 seconds
Started Jun 04 12:24:30 PM PDT 24
Finished Jun 04 12:34:51 PM PDT 24
Peak memory 190948 kb
Host smart-c2c4b85f-0907-4d71-8a9b-dfa12f5feb4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516367511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2516367511
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.4041899527
Short name T267
Test name
Test status
Simulation time 95478280697 ps
CPU time 168.06 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:27:26 PM PDT 24
Peak memory 190944 kb
Host smart-a71892df-ad07-49bb-ab6b-3b15dd7b4765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041899527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4041899527
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.118452824
Short name T69
Test name
Test status
Simulation time 610324093962 ps
CPU time 287.82 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:29:30 PM PDT 24
Peak memory 190980 kb
Host smart-243d8e28-3284-4bba-bbd3-fdb977b50b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118452824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.118452824
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1841385105
Short name T338
Test name
Test status
Simulation time 260553608512 ps
CPU time 236.08 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 12:28:10 PM PDT 24
Peak memory 195592 kb
Host smart-4ff58f89-64a4-434c-988a-902f5d9c0c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841385105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1841385105
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.1987564939
Short name T238
Test name
Test status
Simulation time 127598205033 ps
CPU time 224.64 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:28:32 PM PDT 24
Peak memory 190940 kb
Host smart-cae04252-de83-45e2-90b5-73f5e2421a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987564939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1987564939
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.971412947
Short name T117
Test name
Test status
Simulation time 397186368856 ps
CPU time 266.94 seconds
Started Jun 04 12:22:13 PM PDT 24
Finished Jun 04 12:26:40 PM PDT 24
Peak memory 190980 kb
Host smart-b0622fd5-8b8b-44a3-93e7-b2fc33e84c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971412947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.971412947
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.882138067
Short name T55
Test name
Test status
Simulation time 415403221996 ps
CPU time 757.66 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:36:41 PM PDT 24
Peak memory 182772 kb
Host smart-0633c946-0f5b-46d0-9d08-9e5c72a4e921
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882138067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.882138067
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random.3613283904
Short name T118
Test name
Test status
Simulation time 458979979427 ps
CPU time 275.62 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:28:51 PM PDT 24
Peak memory 190968 kb
Host smart-42e693a1-a589-4528-b994-9fcc56833d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613283904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3613283904
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2790132539
Short name T213
Test name
Test status
Simulation time 278398267701 ps
CPU time 143.47 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:27:06 PM PDT 24
Peak memory 190972 kb
Host smart-b36fda87-62ef-4d4a-a495-23d82c0f7443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790132539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2790132539
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3474875500
Short name T342
Test name
Test status
Simulation time 5478234881588 ps
CPU time 2009.67 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:56:50 PM PDT 24
Peak memory 190972 kb
Host smart-cf84274e-f907-430b-b153-b9e1c014c338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474875500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3474875500
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/66.rv_timer_random.2941567979
Short name T281
Test name
Test status
Simulation time 345559381988 ps
CPU time 303.9 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:29:41 PM PDT 24
Peak memory 190992 kb
Host smart-764c61d5-1482-44d5-899c-bb3a5fa1f3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941567979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2941567979
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.885450616
Short name T226
Test name
Test status
Simulation time 684513296424 ps
CPU time 967.18 seconds
Started Jun 04 12:24:08 PM PDT 24
Finished Jun 04 12:40:16 PM PDT 24
Peak memory 190932 kb
Host smart-348be9a1-ddeb-4e84-8243-ee5f81bab8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885450616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.885450616
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1086628506
Short name T294
Test name
Test status
Simulation time 427624500594 ps
CPU time 278.83 seconds
Started Jun 04 12:24:26 PM PDT 24
Finished Jun 04 12:29:08 PM PDT 24
Peak memory 190924 kb
Host smart-419bec68-acd9-449d-8db3-3da2acf046ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086628506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1086628506
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3685191340
Short name T311
Test name
Test status
Simulation time 514838210097 ps
CPU time 240.15 seconds
Started Jun 04 12:23:25 PM PDT 24
Finished Jun 04 12:27:25 PM PDT 24
Peak memory 191004 kb
Host smart-4a012572-afdd-409a-be6e-c17f30992ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685191340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3685191340
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1767638075
Short name T59
Test name
Test status
Simulation time 220621776050 ps
CPU time 471.74 seconds
Started Jun 04 12:24:47 PM PDT 24
Finished Jun 04 12:32:41 PM PDT 24
Peak memory 190996 kb
Host smart-a7f21ae9-4fa7-4202-92f7-eb2932ba7935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767638075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1767638075
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/82.rv_timer_random.201306826
Short name T248
Test name
Test status
Simulation time 156639791307 ps
CPU time 333.78 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:30:15 PM PDT 24
Peak memory 194376 kb
Host smart-c64ae195-b574-4416-95cd-4b2d4a12cf05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201306826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.201306826
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.135597933
Short name T157
Test name
Test status
Simulation time 211630613504 ps
CPU time 1613.88 seconds
Started Jun 04 12:24:28 PM PDT 24
Finished Jun 04 12:51:23 PM PDT 24
Peak memory 190996 kb
Host smart-da39c236-415e-4be5-979f-893f2a6bc70c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135597933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.135597933
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.455522581
Short name T178
Test name
Test status
Simulation time 11847089340 ps
CPU time 21.1 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:23:41 PM PDT 24
Peak memory 182780 kb
Host smart-0d066916-62c2-479b-9d7a-5008827f1d5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455522581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.455522581
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/160.rv_timer_random.3043167955
Short name T332
Test name
Test status
Simulation time 727298666894 ps
CPU time 445.75 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:32:09 PM PDT 24
Peak memory 190868 kb
Host smart-934bab63-e301-45a2-9c48-29da4b2684fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043167955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3043167955
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.54649394
Short name T270
Test name
Test status
Simulation time 472446102189 ps
CPU time 922.61 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:40:00 PM PDT 24
Peak memory 194408 kb
Host smart-54d6f00f-d4da-48ea-b49a-c3c1960794b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54649394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.54649394
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2257066830
Short name T256
Test name
Test status
Simulation time 125980021689 ps
CPU time 888.21 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:39:27 PM PDT 24
Peak memory 191000 kb
Host smart-3d1265b7-93cf-4be3-9478-a6b356ac43dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257066830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2257066830
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1018714030
Short name T291
Test name
Test status
Simulation time 143422616502 ps
CPU time 1336.09 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:46:58 PM PDT 24
Peak memory 193500 kb
Host smart-a723ec8e-4f08-4245-bac2-2a562e16c274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018714030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1018714030
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.500207058
Short name T190
Test name
Test status
Simulation time 230616149964 ps
CPU time 122.54 seconds
Started Jun 04 12:23:08 PM PDT 24
Finished Jun 04 12:25:13 PM PDT 24
Peak memory 190776 kb
Host smart-29d12148-3e45-44cc-8a45-076c219a7ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500207058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.500207058
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.232107043
Short name T306
Test name
Test status
Simulation time 451927319859 ps
CPU time 399.69 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:30:50 PM PDT 24
Peak memory 182772 kb
Host smart-96acca97-0bba-47a0-9336-6a936eb9a287
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232107043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.232107043
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random.3891881461
Short name T192
Test name
Test status
Simulation time 718390314324 ps
CPU time 511.56 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:32:47 PM PDT 24
Peak memory 193376 kb
Host smart-ea48a911-b3eb-404c-ace2-a2d4b7f78b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891881461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3891881461
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1723299902
Short name T286
Test name
Test status
Simulation time 766247223927 ps
CPU time 1751.27 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:53:24 PM PDT 24
Peak memory 195764 kb
Host smart-1444f73a-2113-4be4-b3fc-2c974cc33723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723299902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1723299902
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/75.rv_timer_random.1473413929
Short name T236
Test name
Test status
Simulation time 195635335717 ps
CPU time 230.42 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:28:33 PM PDT 24
Peak memory 190996 kb
Host smart-edad72e9-aec8-4332-ae72-809be9ab84f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473413929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1473413929
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2046333526
Short name T288
Test name
Test status
Simulation time 184116541103 ps
CPU time 292.4 seconds
Started Jun 04 12:24:28 PM PDT 24
Finished Jun 04 12:29:22 PM PDT 24
Peak memory 190996 kb
Host smart-44053bca-3ebc-46d7-91ad-6d05f49e1040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046333526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2046333526
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2576056912
Short name T1
Test name
Test status
Simulation time 474035067614 ps
CPU time 1350.52 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:47:07 PM PDT 24
Peak memory 191000 kb
Host smart-7ac4af1c-9a8f-4571-9526-84ed16c4d4fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576056912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2576056912
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1566103363
Short name T170
Test name
Test status
Simulation time 98797339312 ps
CPU time 595.89 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:34:35 PM PDT 24
Peak memory 182796 kb
Host smart-83059f9f-0554-486a-91b2-289c93a84752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566103363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1566103363
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.325126843
Short name T54
Test name
Test status
Simulation time 125203236554 ps
CPU time 351.58 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:30:39 PM PDT 24
Peak memory 190940 kb
Host smart-b4affb56-ac30-45e8-b62a-a1326c86ba28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325126843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.325126843
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1062014173
Short name T244
Test name
Test status
Simulation time 138410866155 ps
CPU time 226.63 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:28:29 PM PDT 24
Peak memory 194564 kb
Host smart-6e08f9ea-40e9-4fec-938c-63f7a61cb924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062014173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1062014173
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3840911247
Short name T202
Test name
Test status
Simulation time 1480199872348 ps
CPU time 878.65 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:38:13 PM PDT 24
Peak memory 182772 kb
Host smart-e6f626e8-59c7-441c-83e4-7c13369fad3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840911247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3840911247
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3554488771
Short name T169
Test name
Test status
Simulation time 3048157345169 ps
CPU time 1000.14 seconds
Started Jun 04 12:24:16 PM PDT 24
Finished Jun 04 12:40:57 PM PDT 24
Peak memory 182776 kb
Host smart-f9d14e85-006c-4994-9b4d-09b9dacaeb92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554488771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3554488771
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.319472215
Short name T64
Test name
Test status
Simulation time 1059476269662 ps
CPU time 838.18 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:38:12 PM PDT 24
Peak memory 195660 kb
Host smart-1f5aca0a-1f59-4d93-8fab-7dfa6d7fdd10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319472215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
319472215
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3679531564
Short name T76
Test name
Test status
Simulation time 14417456 ps
CPU time 0.59 seconds
Started Jun 04 12:19:29 PM PDT 24
Finished Jun 04 12:19:30 PM PDT 24
Peak memory 182548 kb
Host smart-45cebe2f-6211-4ff1-9166-512ba441c316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679531564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3679531564
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/1.rv_timer_random.3007632092
Short name T287
Test name
Test status
Simulation time 4882881075 ps
CPU time 2.63 seconds
Started Jun 04 12:23:16 PM PDT 24
Finished Jun 04 12:23:21 PM PDT 24
Peak memory 182752 kb
Host smart-1b0a0631-694d-495b-bd43-09215d3aa546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007632092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3007632092
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.2530686510
Short name T221
Test name
Test status
Simulation time 422039442724 ps
CPU time 737.12 seconds
Started Jun 04 12:24:30 PM PDT 24
Finished Jun 04 12:36:48 PM PDT 24
Peak memory 190928 kb
Host smart-daf81898-ce6f-45d9-9107-e6b54a7b02b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530686510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2530686510
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4032679890
Short name T110
Test name
Test status
Simulation time 98528065438 ps
CPU time 167.97 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:27:28 PM PDT 24
Peak memory 182792 kb
Host smart-66599b72-03fe-4feb-841c-80a31a402866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032679890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4032679890
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.527952984
Short name T113
Test name
Test status
Simulation time 75009329909 ps
CPU time 67.21 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:25:49 PM PDT 24
Peak memory 193428 kb
Host smart-185dda8b-17a4-41f6-b1f9-135cca4161e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527952984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.527952984
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1137891439
Short name T164
Test name
Test status
Simulation time 366281630252 ps
CPU time 281.36 seconds
Started Jun 04 12:24:45 PM PDT 24
Finished Jun 04 12:29:27 PM PDT 24
Peak memory 190932 kb
Host smart-49983175-3535-480b-8359-442928e08ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137891439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1137891439
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3615333562
Short name T251
Test name
Test status
Simulation time 108261208810 ps
CPU time 203.33 seconds
Started Jun 04 12:23:24 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 191000 kb
Host smart-0fe32acd-5404-4826-8ced-a7ab4e43c227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615333562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3615333562
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/154.rv_timer_random.2237814726
Short name T290
Test name
Test status
Simulation time 123123479414 ps
CPU time 196.35 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:27:53 PM PDT 24
Peak memory 190816 kb
Host smart-f94a6f73-386e-4e0d-8195-7d4f9b52fcfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237814726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2237814726
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.192016985
Short name T165
Test name
Test status
Simulation time 1016596995324 ps
CPU time 431.48 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:31:55 PM PDT 24
Peak memory 191004 kb
Host smart-0b5b8ec0-493f-4780-92ec-b2825a1f73d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192016985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.192016985
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.826027445
Short name T160
Test name
Test status
Simulation time 816933576420 ps
CPU time 573.25 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:34:15 PM PDT 24
Peak memory 190992 kb
Host smart-43c20597-1399-4a83-926a-313ffa9dbfb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826027445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.826027445
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1371302039
Short name T9
Test name
Test status
Simulation time 466923942938 ps
CPU time 314.91 seconds
Started Jun 04 12:24:43 PM PDT 24
Finished Jun 04 12:30:00 PM PDT 24
Peak memory 190980 kb
Host smart-9a8f02ef-f203-4f12-9fe9-f98b8f4e965e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371302039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1371302039
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3052083576
Short name T50
Test name
Test status
Simulation time 696845946040 ps
CPU time 1157.52 seconds
Started Jun 04 12:24:05 PM PDT 24
Finished Jun 04 12:43:24 PM PDT 24
Peak memory 182916 kb
Host smart-445b612d-db37-4142-a4de-63e2c501cedb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052083576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3052083576
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.229606986
Short name T346
Test name
Test status
Simulation time 56560231763 ps
CPU time 82.97 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:26:06 PM PDT 24
Peak memory 190968 kb
Host smart-cb497550-680b-404f-bfc2-df96b7d9b6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229606986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.229606986
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1844814178
Short name T208
Test name
Test status
Simulation time 115467885655 ps
CPU time 191.65 seconds
Started Jun 04 12:24:07 PM PDT 24
Finished Jun 04 12:27:20 PM PDT 24
Peak memory 182824 kb
Host smart-a5677b7c-a86d-4092-a95d-15a847043f2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844814178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1844814178
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3975345961
Short name T264
Test name
Test status
Simulation time 455761308180 ps
CPU time 245.57 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:28:16 PM PDT 24
Peak memory 182820 kb
Host smart-2d55139a-e6f8-4298-b5e5-41306b18054f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975345961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3975345961
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.980843973
Short name T211
Test name
Test status
Simulation time 675924861516 ps
CPU time 327.34 seconds
Started Jun 04 12:24:07 PM PDT 24
Finished Jun 04 12:29:36 PM PDT 24
Peak memory 191000 kb
Host smart-d19913c4-794d-415a-b26c-f054d85bb970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980843973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.980843973
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1284603553
Short name T308
Test name
Test status
Simulation time 169236917618 ps
CPU time 177.79 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:27:34 PM PDT 24
Peak memory 190992 kb
Host smart-e460aa8c-9ec8-4b21-81db-2a06245f98e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284603553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1284603553
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1063339696
Short name T234
Test name
Test status
Simulation time 514633881375 ps
CPU time 240.95 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:28:19 PM PDT 24
Peak memory 193324 kb
Host smart-03aa689e-efb0-4684-9aa5-79e507b8646d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063339696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1063339696
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3208395900
Short name T10
Test name
Test status
Simulation time 2857626220 ps
CPU time 5.11 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:24:41 PM PDT 24
Peak memory 182640 kb
Host smart-afa8dc87-e4f2-45a2-a99a-22924a4e8b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208395900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3208395900
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.1778800955
Short name T126
Test name
Test status
Simulation time 153957135408 ps
CPU time 1281.68 seconds
Started Jun 04 12:21:50 PM PDT 24
Finished Jun 04 12:43:12 PM PDT 24
Peak memory 182944 kb
Host smart-8dfb5ce2-ba87-429a-bce7-ec08ee313c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778800955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1778800955
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.4170640876
Short name T197
Test name
Test status
Simulation time 1563447947831 ps
CPU time 757.8 seconds
Started Jun 04 12:22:51 PM PDT 24
Finished Jun 04 12:35:30 PM PDT 24
Peak memory 191016 kb
Host smart-c324346f-f25c-4527-ab71-e57acc426ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170640876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.4170640876
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/113.rv_timer_random.3682265234
Short name T266
Test name
Test status
Simulation time 86374701351 ps
CPU time 116.57 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:26:34 PM PDT 24
Peak memory 182748 kb
Host smart-af73c593-e651-4e45-8b6a-c88d8b945d1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682265234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3682265234
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.696667081
Short name T67
Test name
Test status
Simulation time 307428206019 ps
CPU time 112.97 seconds
Started Jun 04 12:24:26 PM PDT 24
Finished Jun 04 12:26:21 PM PDT 24
Peak memory 190928 kb
Host smart-cce209d2-187f-4cfd-ba30-64dfcd4ac54f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696667081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.696667081
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3871553187
Short name T179
Test name
Test status
Simulation time 155668125941 ps
CPU time 265.24 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:29:01 PM PDT 24
Peak memory 191112 kb
Host smart-52f5da87-58bc-439a-90e4-885b43cfa5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871553187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3871553187
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1810333381
Short name T148
Test name
Test status
Simulation time 349162215883 ps
CPU time 483.15 seconds
Started Jun 04 12:24:21 PM PDT 24
Finished Jun 04 12:32:26 PM PDT 24
Peak memory 190988 kb
Host smart-c58b63b9-e583-4f1f-a547-76d8c1d1c87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810333381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1810333381
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3753961933
Short name T365
Test name
Test status
Simulation time 37712440356 ps
CPU time 75.89 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:25:54 PM PDT 24
Peak memory 190988 kb
Host smart-a1490234-bf95-4548-bd0a-05368cacf11c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753961933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3753961933
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.794016203
Short name T253
Test name
Test status
Simulation time 8182736276 ps
CPU time 46.09 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:24:06 PM PDT 24
Peak memory 190744 kb
Host smart-8e6db434-c9e3-4f27-bb83-3727b5b3fd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794016203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.794016203
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/143.rv_timer_random.2794933987
Short name T150
Test name
Test status
Simulation time 54150036975 ps
CPU time 85.87 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:26:02 PM PDT 24
Peak memory 191120 kb
Host smart-92c6e0b9-3889-45c8-ad38-13b6eab632ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794933987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2794933987
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3673133011
Short name T356
Test name
Test status
Simulation time 156677218752 ps
CPU time 805.25 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:38:06 PM PDT 24
Peak memory 190996 kb
Host smart-86f1a783-ca4e-4d73-81aa-caaf008ca0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673133011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3673133011
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.688731910
Short name T151
Test name
Test status
Simulation time 419139646961 ps
CPU time 190.89 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:26:43 PM PDT 24
Peak memory 190968 kb
Host smart-3b0b86a4-e0ed-439f-bb32-e8f7d58fa81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688731910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
688731910
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/162.rv_timer_random.518739324
Short name T299
Test name
Test status
Simulation time 522373619166 ps
CPU time 765.33 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:37:29 PM PDT 24
Peak memory 190856 kb
Host smart-21cd84a0-75cd-463f-a18c-97db03653ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518739324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.518739324
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2700941665
Short name T293
Test name
Test status
Simulation time 38457419140 ps
CPU time 21.22 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:53 PM PDT 24
Peak memory 182784 kb
Host smart-9a633763-f50f-4e06-ae42-5832ee319afc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700941665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2700941665
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2223869733
Short name T357
Test name
Test status
Simulation time 1635947499174 ps
CPU time 724.39 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:35:33 PM PDT 24
Peak memory 190636 kb
Host smart-b6a61740-3cc2-4514-bae0-19a4476f9084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223869733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2223869733
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4159164880
Short name T98
Test name
Test status
Simulation time 154676558093 ps
CPU time 408.82 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:30:51 PM PDT 24
Peak memory 190956 kb
Host smart-2d9805d5-8ec3-432a-ac91-e77a89e0dacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159164880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4159164880
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.945051428
Short name T177
Test name
Test status
Simulation time 859040635882 ps
CPU time 602.46 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:34:16 PM PDT 24
Peak memory 190940 kb
Host smart-ca10eabf-5758-4271-9c61-6f0d221ec611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945051428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
945051428
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3310902655
Short name T339
Test name
Test status
Simulation time 116791064859 ps
CPU time 108.5 seconds
Started Jun 04 12:24:08 PM PDT 24
Finished Jun 04 12:25:58 PM PDT 24
Peak memory 182820 kb
Host smart-a11f85e6-a8b8-4f7b-ab7c-925d4392cf45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310902655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3310902655
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random.1407370679
Short name T203
Test name
Test status
Simulation time 251440172839 ps
CPU time 271.31 seconds
Started Jun 04 12:24:05 PM PDT 24
Finished Jun 04 12:28:38 PM PDT 24
Peak memory 191104 kb
Host smart-04ace6f9-fa85-4547-8f44-8f9b53109512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407370679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1407370679
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1937754065
Short name T141
Test name
Test status
Simulation time 116350202768 ps
CPU time 90.91 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:25:44 PM PDT 24
Peak memory 190992 kb
Host smart-b73d6110-4d81-4807-bc4f-17392b3bb3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937754065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1937754065
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_random.1039949897
Short name T127
Test name
Test status
Simulation time 110551517611 ps
CPU time 169.29 seconds
Started Jun 04 12:24:02 PM PDT 24
Finished Jun 04 12:26:54 PM PDT 24
Peak memory 190968 kb
Host smart-e1c76831-507f-4cb8-939c-47ff076014e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039949897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1039949897
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2789524330
Short name T313
Test name
Test status
Simulation time 121135859123 ps
CPU time 214.6 seconds
Started Jun 04 12:24:19 PM PDT 24
Finished Jun 04 12:27:56 PM PDT 24
Peak memory 182800 kb
Host smart-1d4b96ba-4cb9-4040-92a1-035de12f41a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789524330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2789524330
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random.1810684425
Short name T12
Test name
Test status
Simulation time 37630979062 ps
CPU time 53.87 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:25:13 PM PDT 24
Peak memory 190972 kb
Host smart-a3b37a60-0c77-47d5-b228-52f7df4ca11c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810684425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1810684425
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.1359097816
Short name T344
Test name
Test status
Simulation time 407855175965 ps
CPU time 1938.66 seconds
Started Jun 04 12:24:15 PM PDT 24
Finished Jun 04 12:56:35 PM PDT 24
Peak memory 190792 kb
Host smart-de2eaac3-3183-4d32-ba57-a9c90a7a9eef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359097816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1359097816
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random.2027349512
Short name T166
Test name
Test status
Simulation time 193764230771 ps
CPU time 1811.35 seconds
Started Jun 04 12:24:18 PM PDT 24
Finished Jun 04 12:54:32 PM PDT 24
Peak memory 194196 kb
Host smart-2a9391d3-64e0-433f-8a4c-165c12c40daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027349512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2027349512
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2691624136
Short name T199
Test name
Test status
Simulation time 136127610834 ps
CPU time 158.82 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:27:14 PM PDT 24
Peak memory 190888 kb
Host smart-a2234f72-6baa-4475-aec8-f1c1db13a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691624136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2691624136
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3977875738
Short name T185
Test name
Test status
Simulation time 543247487315 ps
CPU time 873.01 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:39:14 PM PDT 24
Peak memory 182808 kb
Host smart-746d3e4b-2595-413d-8937-5b96bc9b3bbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977875738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3977875738
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/53.rv_timer_random.1616713061
Short name T262
Test name
Test status
Simulation time 169736537677 ps
CPU time 163.62 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:26:56 PM PDT 24
Peak memory 190928 kb
Host smart-1f4c3d58-9bf3-428a-9274-5c0c6b5f8154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616713061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1616713061
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1043257487
Short name T79
Test name
Test status
Simulation time 70771039 ps
CPU time 0.6 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 191348 kb
Host smart-163bb451-d5cb-454a-8109-d361fb07b3a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043257487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1043257487
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1809641071
Short name T498
Test name
Test status
Simulation time 196593160 ps
CPU time 2.5 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:23:11 PM PDT 24
Peak memory 190572 kb
Host smart-de72a609-4589-4526-990a-47dcb91fa9ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809641071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1809641071
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.506159547
Short name T103
Test name
Test status
Simulation time 161070732 ps
CPU time 0.54 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 182144 kb
Host smart-1f21d655-1d81-483c-ad63-5d254f13819b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506159547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.506159547
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1090540554
Short name T470
Test name
Test status
Simulation time 125891987 ps
CPU time 0.91 seconds
Started Jun 04 12:23:35 PM PDT 24
Finished Jun 04 12:23:38 PM PDT 24
Peak memory 195896 kb
Host smart-24148357-444a-4b35-a740-95bdad7bdb92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090540554 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1090540554
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.140191983
Short name T496
Test name
Test status
Simulation time 32314537 ps
CPU time 0.54 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:30 PM PDT 24
Peak memory 182520 kb
Host smart-24ec0301-48f2-4386-b626-e827a1d4303e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140191983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.140191983
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1288461631
Short name T490
Test name
Test status
Simulation time 16323937 ps
CPU time 0.58 seconds
Started Jun 04 12:23:06 PM PDT 24
Finished Jun 04 12:23:09 PM PDT 24
Peak memory 181200 kb
Host smart-a5036d99-1541-419a-89ee-f42ddfe27421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288461631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1288461631
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2028923488
Short name T575
Test name
Test status
Simulation time 132990563 ps
CPU time 0.71 seconds
Started Jun 04 12:20:22 PM PDT 24
Finished Jun 04 12:20:23 PM PDT 24
Peak memory 193100 kb
Host smart-96fde280-82a0-4e62-b984-7e2507c9db55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028923488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2028923488
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3846314268
Short name T558
Test name
Test status
Simulation time 75924283 ps
CPU time 1.91 seconds
Started Jun 04 12:23:39 PM PDT 24
Finished Jun 04 12:23:42 PM PDT 24
Peak memory 197084 kb
Host smart-50ed1c0b-71bf-4ba9-9c4d-3b4571a997a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846314268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3846314268
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.305619464
Short name T576
Test name
Test status
Simulation time 48621264 ps
CPU time 0.78 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 192088 kb
Host smart-6e593c3f-8509-456f-889f-9e8324315a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305619464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.305619464
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1644256973
Short name T461
Test name
Test status
Simulation time 50773359 ps
CPU time 0.59 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 182136 kb
Host smart-086cab5a-a393-48ba-84fc-1d50b4a1301e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644256973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1644256973
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4211386253
Short name T535
Test name
Test status
Simulation time 330065316 ps
CPU time 1.52 seconds
Started Jun 04 12:21:45 PM PDT 24
Finished Jun 04 12:21:47 PM PDT 24
Peak memory 182860 kb
Host smart-6b224244-c26f-426b-8fdb-fb5e5a5c5986
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211386253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4211386253
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.91139399
Short name T547
Test name
Test status
Simulation time 57871414 ps
CPU time 0.53 seconds
Started Jun 04 12:23:11 PM PDT 24
Finished Jun 04 12:23:12 PM PDT 24
Peak memory 182104 kb
Host smart-ce75b3a2-2fce-48ef-96c0-26721def9519
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91139399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_res
et.91139399
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.798865850
Short name T502
Test name
Test status
Simulation time 77981193 ps
CPU time 0.99 seconds
Started Jun 04 12:21:35 PM PDT 24
Finished Jun 04 12:21:37 PM PDT 24
Peak memory 197408 kb
Host smart-b7a3fc2c-87bc-4c94-8c37-0c6a885a247e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798865850 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.798865850
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3015580177
Short name T559
Test name
Test status
Simulation time 49596241 ps
CPU time 0.62 seconds
Started Jun 04 12:23:17 PM PDT 24
Finished Jun 04 12:23:19 PM PDT 24
Peak memory 180244 kb
Host smart-02ebf195-398d-497b-88d3-3fbd39839567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015580177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3015580177
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4042208450
Short name T90
Test name
Test status
Simulation time 94929507 ps
CPU time 0.68 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 191160 kb
Host smart-c81dec29-ff66-472c-b327-af7157eb6de3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042208450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4042208450
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3859745366
Short name T573
Test name
Test status
Simulation time 72582551 ps
CPU time 1.16 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:08 PM PDT 24
Peak memory 197080 kb
Host smart-c13a10ab-2215-40ac-931a-f00753d91b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859745366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3859745366
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.550567652
Short name T556
Test name
Test status
Simulation time 409515503 ps
CPU time 1.3 seconds
Started Jun 04 12:19:40 PM PDT 24
Finished Jun 04 12:19:42 PM PDT 24
Peak memory 183152 kb
Host smart-5bd9fcd2-cad2-4263-b0d5-82f46d3c11ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550567652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.550567652
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1852725299
Short name T508
Test name
Test status
Simulation time 84119231 ps
CPU time 0.79 seconds
Started Jun 04 12:23:04 PM PDT 24
Finished Jun 04 12:23:06 PM PDT 24
Peak memory 193396 kb
Host smart-fbc88b56-ff6b-4771-951b-0c14b5a6d92a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852725299 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1852725299
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.252471501
Short name T57
Test name
Test status
Simulation time 27552876 ps
CPU time 0.56 seconds
Started Jun 04 12:17:52 PM PDT 24
Finished Jun 04 12:17:54 PM PDT 24
Peak memory 182276 kb
Host smart-8716a157-631c-44a7-9f06-634fc629c20d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252471501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.252471501
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3555909524
Short name T580
Test name
Test status
Simulation time 12483606 ps
CPU time 0.55 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:23:09 PM PDT 24
Peak memory 182040 kb
Host smart-f3c991a3-e9ee-44b7-a0f8-8b85beb33e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555909524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3555909524
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.719797048
Short name T91
Test name
Test status
Simulation time 39587034 ps
CPU time 0.79 seconds
Started Jun 04 12:19:39 PM PDT 24
Finished Jun 04 12:19:41 PM PDT 24
Peak memory 193184 kb
Host smart-0c077403-d4fc-4405-a353-0a23e864e55e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719797048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.719797048
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3755875906
Short name T546
Test name
Test status
Simulation time 108434288 ps
CPU time 2.2 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:24:21 PM PDT 24
Peak memory 197396 kb
Host smart-f33f2bff-408b-4cc8-bb64-0d0157be25a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755875906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3755875906
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.54692396
Short name T539
Test name
Test status
Simulation time 276124337 ps
CPU time 1 seconds
Started Jun 04 12:24:03 PM PDT 24
Finished Jun 04 12:24:06 PM PDT 24
Peak memory 195048 kb
Host smart-453625b2-01a6-4bd9-8b32-1a3e0c06af30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54692396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_int
g_err.54692396
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2730193349
Short name T577
Test name
Test status
Simulation time 24277247 ps
CPU time 1.15 seconds
Started Jun 04 12:22:32 PM PDT 24
Finished Jun 04 12:22:34 PM PDT 24
Peak memory 196192 kb
Host smart-551a5778-9965-42a1-a7d2-e5b77006a46c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730193349 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2730193349
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2162346176
Short name T86
Test name
Test status
Simulation time 14922497 ps
CPU time 0.57 seconds
Started Jun 04 12:23:41 PM PDT 24
Finished Jun 04 12:23:42 PM PDT 24
Peak memory 182548 kb
Host smart-5ad4252e-8da8-49a4-a611-500ab94bdafd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162346176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2162346176
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1089339223
Short name T484
Test name
Test status
Simulation time 15897855 ps
CPU time 0.56 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:07 PM PDT 24
Peak memory 180012 kb
Host smart-32ffcd87-03b9-4d7a-a6fc-12cd60fa4921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089339223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1089339223
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1934912208
Short name T523
Test name
Test status
Simulation time 89305444 ps
CPU time 0.7 seconds
Started Jun 04 12:22:33 PM PDT 24
Finished Jun 04 12:22:34 PM PDT 24
Peak memory 191260 kb
Host smart-9626edd8-944f-450a-a1f2-7d0f55713567
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934912208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1934912208
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.96964671
Short name T534
Test name
Test status
Simulation time 98900387 ps
CPU time 1.87 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:37 PM PDT 24
Peak memory 196964 kb
Host smart-e19c55b8-6fdc-41c9-9bae-d0456b02c840
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96964671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.96964671
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3923112077
Short name T536
Test name
Test status
Simulation time 121515012 ps
CPU time 1.35 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:36 PM PDT 24
Peak memory 194476 kb
Host smart-e7f417cb-515e-4d07-a726-7785f337edfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923112077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3923112077
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1112756165
Short name T489
Test name
Test status
Simulation time 93602923 ps
CPU time 1.1 seconds
Started Jun 04 12:18:45 PM PDT 24
Finished Jun 04 12:18:47 PM PDT 24
Peak memory 197436 kb
Host smart-54971114-dae3-41d7-8004-33214a98e5e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112756165 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1112756165
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1006025688
Short name T78
Test name
Test status
Simulation time 54349478 ps
CPU time 0.56 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:16 PM PDT 24
Peak memory 182152 kb
Host smart-6a59ec2f-6bd6-419a-a7fc-ff0ff453059b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006025688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1006025688
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1076849002
Short name T566
Test name
Test status
Simulation time 38130773 ps
CPU time 0.55 seconds
Started Jun 04 12:21:43 PM PDT 24
Finished Jun 04 12:21:44 PM PDT 24
Peak memory 182416 kb
Host smart-6b84b08d-12aa-4267-9dc6-a52202e30053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076849002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1076849002
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.713702068
Short name T543
Test name
Test status
Simulation time 44785354 ps
CPU time 0.69 seconds
Started Jun 04 12:23:43 PM PDT 24
Finished Jun 04 12:23:44 PM PDT 24
Peak memory 191440 kb
Host smart-0c609c71-b83a-402a-90af-f800609b7c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713702068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.713702068
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2322040570
Short name T463
Test name
Test status
Simulation time 89564081 ps
CPU time 1.13 seconds
Started Jun 04 12:18:54 PM PDT 24
Finished Jun 04 12:18:56 PM PDT 24
Peak memory 197772 kb
Host smart-b4e6faa2-f40a-4237-be04-bd6e78c8b0d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322040570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2322040570
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.539832579
Short name T472
Test name
Test status
Simulation time 62486589 ps
CPU time 0.87 seconds
Started Jun 04 12:23:31 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 192520 kb
Host smart-ce71dd99-6406-4955-9dbf-14ce44de0462
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539832579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.539832579
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2198052398
Short name T45
Test name
Test status
Simulation time 56474574 ps
CPU time 0.74 seconds
Started Jun 04 12:19:33 PM PDT 24
Finished Jun 04 12:19:34 PM PDT 24
Peak memory 195152 kb
Host smart-21941fe1-427e-490d-a165-c654c4dc5eff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198052398 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2198052398
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1399905598
Short name T486
Test name
Test status
Simulation time 44266783 ps
CPU time 0.57 seconds
Started Jun 04 12:20:20 PM PDT 24
Finished Jun 04 12:20:22 PM PDT 24
Peak memory 182580 kb
Host smart-244a35ee-d923-4e37-9250-582fcb64f24a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399905598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1399905598
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1516156355
Short name T457
Test name
Test status
Simulation time 31475601 ps
CPU time 0.55 seconds
Started Jun 04 12:22:48 PM PDT 24
Finished Jun 04 12:22:50 PM PDT 24
Peak memory 182136 kb
Host smart-fa758615-ff88-42f4-b172-84a07f51a6ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516156355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1516156355
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2677722428
Short name T551
Test name
Test status
Simulation time 52634184 ps
CPU time 0.77 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:00 PM PDT 24
Peak memory 192868 kb
Host smart-430a102a-8327-4a78-af30-d182efd24438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677722428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2677722428
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.267496769
Short name T538
Test name
Test status
Simulation time 64573944 ps
CPU time 1.19 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:01 PM PDT 24
Peak memory 197176 kb
Host smart-bd976293-a40a-4a52-b1df-92b0c8f01152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267496769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.267496769
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1855573417
Short name T477
Test name
Test status
Simulation time 121175068 ps
CPU time 0.8 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 192768 kb
Host smart-bf225935-3f1e-4d5c-a104-e123daf7ace3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855573417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1855573417
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.493259599
Short name T550
Test name
Test status
Simulation time 17653324 ps
CPU time 0.77 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:24:03 PM PDT 24
Peak memory 195268 kb
Host smart-7cc967c0-f42f-4e2e-b5dc-7aaee9c383c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493259599 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.493259599
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2132497251
Short name T44
Test name
Test status
Simulation time 40040566 ps
CPU time 0.58 seconds
Started Jun 04 12:23:12 PM PDT 24
Finished Jun 04 12:23:13 PM PDT 24
Peak memory 181548 kb
Host smart-8a5893b6-e863-44cc-8919-c3f1018ff78d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132497251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2132497251
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3894003844
Short name T520
Test name
Test status
Simulation time 40142069 ps
CPU time 0.66 seconds
Started Jun 04 12:23:17 PM PDT 24
Finished Jun 04 12:23:19 PM PDT 24
Peak memory 180744 kb
Host smart-50f82f6c-2c73-4a05-864e-3572a4b28eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894003844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3894003844
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2282301938
Short name T513
Test name
Test status
Simulation time 146480931 ps
CPU time 0.82 seconds
Started Jun 04 12:21:52 PM PDT 24
Finished Jun 04 12:21:54 PM PDT 24
Peak memory 193440 kb
Host smart-10c6d3f1-166c-465b-954f-02489fb0f6d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282301938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2282301938
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.649188846
Short name T467
Test name
Test status
Simulation time 67759188 ps
CPU time 2.48 seconds
Started Jun 04 12:23:17 PM PDT 24
Finished Jun 04 12:23:21 PM PDT 24
Peak memory 196408 kb
Host smart-52abc40f-3390-4342-9f64-ae8cec2d86ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649188846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.649188846
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1100648563
Short name T499
Test name
Test status
Simulation time 85320951 ps
CPU time 0.79 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:23:29 PM PDT 24
Peak memory 183048 kb
Host smart-8336bea0-4df2-4328-b7a2-4a43b9423a58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100648563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1100648563
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2524518678
Short name T506
Test name
Test status
Simulation time 24069002 ps
CPU time 0.77 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:24:04 PM PDT 24
Peak memory 194588 kb
Host smart-ea49ca76-5a6e-4246-b12c-41e354de5893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524518678 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2524518678
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.369592932
Short name T84
Test name
Test status
Simulation time 28687907 ps
CPU time 0.56 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:23:58 PM PDT 24
Peak memory 182484 kb
Host smart-802fe3ec-a038-4abe-9597-49d164ad486e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369592932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.369592932
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2877973459
Short name T511
Test name
Test status
Simulation time 39318482 ps
CPU time 0.53 seconds
Started Jun 04 12:23:45 PM PDT 24
Finished Jun 04 12:23:47 PM PDT 24
Peak memory 181632 kb
Host smart-7f07eef4-ef5d-425b-a2dc-2ae70b3a03ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877973459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2877973459
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2684429890
Short name T518
Test name
Test status
Simulation time 30590378 ps
CPU time 0.73 seconds
Started Jun 04 12:23:39 PM PDT 24
Finished Jun 04 12:23:41 PM PDT 24
Peak memory 191036 kb
Host smart-9ed0da9c-f075-4432-9049-9c9554d9e775
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684429890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2684429890
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3582296352
Short name T475
Test name
Test status
Simulation time 270126174 ps
CPU time 2.16 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:23:34 PM PDT 24
Peak memory 197112 kb
Host smart-f1740c3d-537a-4dbe-af20-36b34c8a460d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582296352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3582296352
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.281343174
Short name T529
Test name
Test status
Simulation time 517210205 ps
CPU time 1.34 seconds
Started Jun 04 12:20:18 PM PDT 24
Finished Jun 04 12:20:20 PM PDT 24
Peak memory 183208 kb
Host smart-667de4bd-3268-4b61-87e8-ba89831ec70a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281343174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.281343174
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3400133498
Short name T563
Test name
Test status
Simulation time 45316008 ps
CPU time 0.73 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:16 PM PDT 24
Peak memory 194780 kb
Host smart-79bb80c8-4e0d-474a-82a5-f2334623f46d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400133498 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3400133498
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3427563106
Short name T521
Test name
Test status
Simulation time 38869651 ps
CPU time 0.57 seconds
Started Jun 04 12:18:47 PM PDT 24
Finished Jun 04 12:18:48 PM PDT 24
Peak memory 182428 kb
Host smart-03c3193f-6fd1-4d50-a217-69bb330037ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427563106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3427563106
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1604072721
Short name T568
Test name
Test status
Simulation time 37997907 ps
CPU time 0.57 seconds
Started Jun 04 12:23:44 PM PDT 24
Finished Jun 04 12:23:46 PM PDT 24
Peak memory 180412 kb
Host smart-ce8cfef3-1b4f-4649-a34d-33156a0adc98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604072721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1604072721
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1531008802
Short name T542
Test name
Test status
Simulation time 32805980 ps
CPU time 0.76 seconds
Started Jun 04 12:22:15 PM PDT 24
Finished Jun 04 12:22:17 PM PDT 24
Peak memory 191924 kb
Host smart-8c68a8ae-de86-4e61-b37a-418582aa61e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531008802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1531008802
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.524251806
Short name T514
Test name
Test status
Simulation time 399582306 ps
CPU time 1.79 seconds
Started Jun 04 12:19:43 PM PDT 24
Finished Jun 04 12:19:46 PM PDT 24
Peak memory 196188 kb
Host smart-4eb367b6-0498-4d76-a0fe-c354cd4e44a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524251806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.524251806
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3213102808
Short name T495
Test name
Test status
Simulation time 44856937 ps
CPU time 0.79 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:23:10 PM PDT 24
Peak memory 193224 kb
Host smart-eaeafd3a-b4a8-4983-a383-36b5fa23b310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213102808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3213102808
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1942676863
Short name T569
Test name
Test status
Simulation time 59137262 ps
CPU time 1.24 seconds
Started Jun 04 12:23:06 PM PDT 24
Finished Jun 04 12:23:10 PM PDT 24
Peak memory 196308 kb
Host smart-e9d34e7b-3333-422c-9fb2-9b98c864a464
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942676863 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1942676863
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2764726885
Short name T507
Test name
Test status
Simulation time 25310022 ps
CPU time 0.54 seconds
Started Jun 04 12:19:25 PM PDT 24
Finished Jun 04 12:19:26 PM PDT 24
Peak memory 182268 kb
Host smart-fdc28118-c281-466f-96a2-b46a4e10a26b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764726885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2764726885
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4201646689
Short name T500
Test name
Test status
Simulation time 44368886 ps
CPU time 0.53 seconds
Started Jun 04 12:20:38 PM PDT 24
Finished Jun 04 12:20:39 PM PDT 24
Peak memory 182384 kb
Host smart-ca4a995d-ddf3-461f-9fd0-ef06bfe72e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201646689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4201646689
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3163250202
Short name T570
Test name
Test status
Simulation time 18003971 ps
CPU time 0.64 seconds
Started Jun 04 12:23:17 PM PDT 24
Finished Jun 04 12:23:19 PM PDT 24
Peak memory 191000 kb
Host smart-0da38ad1-d013-4af1-9f48-4f1e311b4d8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163250202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3163250202
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4062360032
Short name T491
Test name
Test status
Simulation time 259576274 ps
CPU time 2.45 seconds
Started Jun 04 12:21:01 PM PDT 24
Finished Jun 04 12:21:04 PM PDT 24
Peak memory 197440 kb
Host smart-55687193-c266-4d12-8219-541b778c0d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062360032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4062360032
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3213538268
Short name T524
Test name
Test status
Simulation time 188608529 ps
CPU time 1.35 seconds
Started Jun 04 12:18:36 PM PDT 24
Finished Jun 04 12:18:38 PM PDT 24
Peak memory 195456 kb
Host smart-f9bc3816-b660-4702-be2d-f5b4443f1001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213538268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3213538268
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1557128748
Short name T455
Test name
Test status
Simulation time 72122307 ps
CPU time 1.04 seconds
Started Jun 04 12:23:43 PM PDT 24
Finished Jun 04 12:23:45 PM PDT 24
Peak memory 196352 kb
Host smart-b48adfb6-5ffd-4d42-bd34-1a643d9ae5e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557128748 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1557128748
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3609213682
Short name T456
Test name
Test status
Simulation time 13979855 ps
CPU time 0.52 seconds
Started Jun 04 12:23:21 PM PDT 24
Finished Jun 04 12:23:23 PM PDT 24
Peak memory 182232 kb
Host smart-75c4ec30-2c8f-4060-8cf1-ddea40159727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609213682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3609213682
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1978595062
Short name T494
Test name
Test status
Simulation time 49475708 ps
CPU time 0.57 seconds
Started Jun 04 12:22:03 PM PDT 24
Finished Jun 04 12:22:03 PM PDT 24
Peak memory 181888 kb
Host smart-dbf0c028-cce2-48d8-879f-4234a807fea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978595062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1978595062
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3878388
Short name T505
Test name
Test status
Simulation time 67902415 ps
CPU time 0.82 seconds
Started Jun 04 12:21:38 PM PDT 24
Finished Jun 04 12:21:40 PM PDT 24
Peak memory 193236 kb
Host smart-abafe54d-be66-4c50-af38-ef997857074c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_time
r_same_csr_outstanding.3878388
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4210588757
Short name T481
Test name
Test status
Simulation time 60521380 ps
CPU time 2.89 seconds
Started Jun 04 12:23:13 PM PDT 24
Finished Jun 04 12:23:17 PM PDT 24
Peak memory 196560 kb
Host smart-229a4958-8bca-4da5-9306-b08fb419f871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210588757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4210588757
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.457575647
Short name T105
Test name
Test status
Simulation time 213191623 ps
CPU time 0.9 seconds
Started Jun 04 12:23:06 PM PDT 24
Finished Jun 04 12:23:09 PM PDT 24
Peak memory 192072 kb
Host smart-eed4385e-f9d0-4825-b1dc-7deeb1556798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457575647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.457575647
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3384614016
Short name T464
Test name
Test status
Simulation time 29803643 ps
CPU time 0.85 seconds
Started Jun 04 12:23:31 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 196532 kb
Host smart-f629ba68-8318-4a6e-82e4-b04973b01760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384614016 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3384614016
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3622624773
Short name T77
Test name
Test status
Simulation time 20591236 ps
CPU time 0.55 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:07 PM PDT 24
Peak memory 180924 kb
Host smart-f8642bb2-a808-4097-b456-f071cbefd599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622624773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3622624773
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2905458505
Short name T466
Test name
Test status
Simulation time 16302726 ps
CPU time 0.57 seconds
Started Jun 04 12:23:24 PM PDT 24
Finished Jun 04 12:23:26 PM PDT 24
Peak memory 181564 kb
Host smart-8bdb6ff7-9f3e-4749-a189-e77e52b1ec60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905458505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2905458505
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1961622622
Short name T46
Test name
Test status
Simulation time 32171699 ps
CPU time 0.79 seconds
Started Jun 04 12:21:41 PM PDT 24
Finished Jun 04 12:21:43 PM PDT 24
Peak memory 191888 kb
Host smart-0a0c96b4-571e-4559-8e05-2187bd4e844a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961622622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1961622622
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.359055361
Short name T43
Test name
Test status
Simulation time 717976820 ps
CPU time 2.46 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:09 PM PDT 24
Peak memory 195388 kb
Host smart-b0028280-bcc8-4717-963d-5e542aeebdba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359055361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.359055361
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.313223047
Short name T29
Test name
Test status
Simulation time 45710701 ps
CPU time 0.89 seconds
Started Jun 04 12:23:31 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 181584 kb
Host smart-a66230b5-6dd4-4f90-988f-0a3812bb6ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313223047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.313223047
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2169933366
Short name T72
Test name
Test status
Simulation time 46457118 ps
CPU time 0.68 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:23:22 PM PDT 24
Peak memory 191704 kb
Host smart-10e178ff-108f-4eb4-be05-3292f3ae1359
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169933366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2169933366
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1260995633
Short name T528
Test name
Test status
Simulation time 433020999 ps
CPU time 2.64 seconds
Started Jun 04 12:22:24 PM PDT 24
Finished Jun 04 12:22:28 PM PDT 24
Peak memory 190000 kb
Host smart-2ea08a0f-5da7-4f20-86cc-d0475f993eb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260995633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1260995633
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1657430553
Short name T83
Test name
Test status
Simulation time 52358036 ps
CPU time 0.52 seconds
Started Jun 04 12:23:33 PM PDT 24
Finished Jun 04 12:23:36 PM PDT 24
Peak memory 181852 kb
Host smart-60674247-9c93-43d5-bed3-4520450beeef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657430553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1657430553
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2087664477
Short name T504
Test name
Test status
Simulation time 23877734 ps
CPU time 1.06 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:23:22 PM PDT 24
Peak memory 196068 kb
Host smart-0c319326-fe34-4133-99c1-e5cde6effa8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087664477 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2087664477
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1224144541
Short name T488
Test name
Test status
Simulation time 43429205 ps
CPU time 0.52 seconds
Started Jun 04 12:23:41 PM PDT 24
Finished Jun 04 12:23:42 PM PDT 24
Peak memory 182276 kb
Host smart-9eaf01c5-8db4-41d7-801d-36c63d3c14c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224144541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1224144541
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.494423987
Short name T476
Test name
Test status
Simulation time 36827673 ps
CPU time 0.53 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:23:22 PM PDT 24
Peak memory 180672 kb
Host smart-b792d14f-021c-4607-bc92-cdebdae30850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494423987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.494423987
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3996843491
Short name T509
Test name
Test status
Simulation time 40879206 ps
CPU time 0.81 seconds
Started Jun 04 12:23:42 PM PDT 24
Finished Jun 04 12:23:43 PM PDT 24
Peak memory 193336 kb
Host smart-ea506425-a17c-49c5-b186-d2fe23324acd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996843491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3996843491
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.387763184
Short name T519
Test name
Test status
Simulation time 53093321 ps
CPU time 2.46 seconds
Started Jun 04 12:23:28 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 197456 kb
Host smart-10d7b07a-fc88-4f26-9373-a575535752a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387763184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.387763184
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2694967649
Short name T28
Test name
Test status
Simulation time 154703833 ps
CPU time 0.79 seconds
Started Jun 04 12:22:48 PM PDT 24
Finished Jun 04 12:22:50 PM PDT 24
Peak memory 182464 kb
Host smart-5952df54-ebd0-4304-a880-d5786409ff47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694967649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2694967649
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3759031108
Short name T478
Test name
Test status
Simulation time 12816459 ps
CPU time 0.57 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:07 PM PDT 24
Peak memory 180000 kb
Host smart-1385f3ca-2a48-408e-85cf-3a12dfe7ed0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759031108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3759031108
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.852821612
Short name T516
Test name
Test status
Simulation time 43716622 ps
CPU time 0.56 seconds
Started Jun 04 12:18:40 PM PDT 24
Finished Jun 04 12:18:41 PM PDT 24
Peak memory 182436 kb
Host smart-0306e0e0-f739-4301-bfa9-b9a20590ab9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852821612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.852821612
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1614021996
Short name T471
Test name
Test status
Simulation time 28916783 ps
CPU time 0.6 seconds
Started Jun 04 12:22:24 PM PDT 24
Finished Jun 04 12:22:26 PM PDT 24
Peak memory 180892 kb
Host smart-79ecff95-f59f-4020-8c81-96b5c23ad404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614021996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1614021996
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3593611391
Short name T485
Test name
Test status
Simulation time 31474181 ps
CPU time 0.54 seconds
Started Jun 04 12:22:25 PM PDT 24
Finished Jun 04 12:22:27 PM PDT 24
Peak memory 182092 kb
Host smart-99e8b552-6980-4a10-ae93-dcdff6aa78bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593611391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3593611391
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2540081296
Short name T533
Test name
Test status
Simulation time 36985934 ps
CPU time 0.6 seconds
Started Jun 04 12:23:04 PM PDT 24
Finished Jun 04 12:23:06 PM PDT 24
Peak memory 179872 kb
Host smart-e8f9923e-7ee3-4ab4-ab77-91658d93fbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540081296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2540081296
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3302069090
Short name T458
Test name
Test status
Simulation time 27639135 ps
CPU time 0.66 seconds
Started Jun 04 12:23:04 PM PDT 24
Finished Jun 04 12:23:06 PM PDT 24
Peak memory 180244 kb
Host smart-ad481f93-ca3c-4860-bdc5-80cc4617674b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302069090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3302069090
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1171414750
Short name T512
Test name
Test status
Simulation time 14236952 ps
CPU time 0.54 seconds
Started Jun 04 12:23:40 PM PDT 24
Finished Jun 04 12:23:41 PM PDT 24
Peak memory 182264 kb
Host smart-9ef1ddbb-93d8-4152-bed3-1e257adfebdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171414750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1171414750
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1704899284
Short name T545
Test name
Test status
Simulation time 10704028 ps
CPU time 0.56 seconds
Started Jun 04 12:23:38 PM PDT 24
Finished Jun 04 12:23:40 PM PDT 24
Peak memory 181472 kb
Host smart-29a89659-d0d8-44f9-b2f4-0d7105a706e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704899284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1704899284
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1700989266
Short name T549
Test name
Test status
Simulation time 13528418 ps
CPU time 0.56 seconds
Started Jun 04 12:21:39 PM PDT 24
Finished Jun 04 12:21:40 PM PDT 24
Peak memory 181876 kb
Host smart-ad2d1b3b-e97e-4cb4-bbe1-c3db79a56077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700989266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1700989266
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4146943034
Short name T548
Test name
Test status
Simulation time 26964944 ps
CPU time 0.56 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:06 PM PDT 24
Peak memory 180472 kb
Host smart-f86e27a9-2581-45e4-916d-ee0563129823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146943034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4146943034
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2502997194
Short name T80
Test name
Test status
Simulation time 128396116 ps
CPU time 0.83 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:24:04 PM PDT 24
Peak memory 182540 kb
Host smart-8348b9db-9229-40a5-9977-01ff80a3cd77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502997194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2502997194
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2168393623
Short name T522
Test name
Test status
Simulation time 250896232 ps
CPU time 2.53 seconds
Started Jun 04 12:23:38 PM PDT 24
Finished Jun 04 12:23:42 PM PDT 24
Peak memory 190012 kb
Host smart-bf096f44-eaf7-43bb-a751-ed819ffd7c34
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168393623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2168393623
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3004565289
Short name T73
Test name
Test status
Simulation time 24873974 ps
CPU time 0.61 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 181996 kb
Host smart-b1b2ffe2-bc6c-4e2b-af7d-2e130a908bf1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004565289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3004565289
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1957561833
Short name T537
Test name
Test status
Simulation time 152057841 ps
CPU time 1.58 seconds
Started Jun 04 12:24:00 PM PDT 24
Finished Jun 04 12:24:02 PM PDT 24
Peak memory 197468 kb
Host smart-1697180f-1386-410b-8849-5c72c7439e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957561833 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1957561833
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2389100792
Short name T526
Test name
Test status
Simulation time 40783810 ps
CPU time 0.59 seconds
Started Jun 04 12:19:39 PM PDT 24
Finished Jun 04 12:19:40 PM PDT 24
Peak memory 182420 kb
Host smart-5be7088e-cde2-418f-a343-d5c80da0f0f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389100792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2389100792
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1597198423
Short name T555
Test name
Test status
Simulation time 18341434 ps
CPU time 0.77 seconds
Started Jun 04 12:23:04 PM PDT 24
Finished Jun 04 12:23:07 PM PDT 24
Peak memory 188868 kb
Host smart-3f89f16c-b4b9-48d7-80ed-79227d0e3e7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597198423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1597198423
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2743366236
Short name T487
Test name
Test status
Simulation time 224510646 ps
CPU time 1.87 seconds
Started Jun 04 12:19:32 PM PDT 24
Finished Jun 04 12:19:35 PM PDT 24
Peak memory 191052 kb
Host smart-f7efa474-0be6-4b88-993a-97c83d74433e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743366236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2743366236
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.11822148
Short name T527
Test name
Test status
Simulation time 236178475 ps
CPU time 1.32 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:36 PM PDT 24
Peak memory 194776 kb
Host smart-ed8f4470-83b5-4b45-950d-ffc4318faf32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11822148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg
_err.11822148
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3972900841
Short name T503
Test name
Test status
Simulation time 12823290 ps
CPU time 0.57 seconds
Started Jun 04 12:23:04 PM PDT 24
Finished Jun 04 12:23:06 PM PDT 24
Peak memory 179708 kb
Host smart-03c26cd2-b70b-453a-9847-f67383bc46d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972900841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3972900841
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2569784948
Short name T459
Test name
Test status
Simulation time 40982020 ps
CPU time 0.56 seconds
Started Jun 04 12:23:58 PM PDT 24
Finished Jun 04 12:24:00 PM PDT 24
Peak memory 181016 kb
Host smart-4418427c-ab77-4e34-8e97-da55b4ad1c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569784948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2569784948
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3368044851
Short name T544
Test name
Test status
Simulation time 20897319 ps
CPU time 0.51 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:23:22 PM PDT 24
Peak memory 181776 kb
Host smart-6ebe5614-c58a-49ad-ad66-e7dffff81d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368044851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3368044851
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3180698362
Short name T465
Test name
Test status
Simulation time 52271751 ps
CPU time 0.53 seconds
Started Jun 04 12:22:49 PM PDT 24
Finished Jun 04 12:22:50 PM PDT 24
Peak memory 182068 kb
Host smart-2bdb42a9-b7a9-444b-b86c-0861eacede1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180698362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3180698362
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3295369754
Short name T482
Test name
Test status
Simulation time 19601288 ps
CPU time 0.55 seconds
Started Jun 04 12:18:54 PM PDT 24
Finished Jun 04 12:18:55 PM PDT 24
Peak memory 182756 kb
Host smart-90a1ff67-8fba-43c4-8390-3b6150e1cf78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295369754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3295369754
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2343795265
Short name T510
Test name
Test status
Simulation time 36374742 ps
CPU time 0.54 seconds
Started Jun 04 12:23:32 PM PDT 24
Finished Jun 04 12:23:35 PM PDT 24
Peak memory 182360 kb
Host smart-e1541089-5585-457a-a9f1-061abb7be707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343795265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2343795265
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1005179997
Short name T561
Test name
Test status
Simulation time 54546180 ps
CPU time 0.59 seconds
Started Jun 04 12:21:38 PM PDT 24
Finished Jun 04 12:21:39 PM PDT 24
Peak memory 182444 kb
Host smart-efefefa5-2608-468f-b6e4-9fcac4ac1cbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005179997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1005179997
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.564513963
Short name T492
Test name
Test status
Simulation time 13541889 ps
CPU time 0.55 seconds
Started Jun 04 12:23:39 PM PDT 24
Finished Jun 04 12:23:41 PM PDT 24
Peak memory 180120 kb
Host smart-5fe7cde5-ecaf-4d6b-877a-3060ed1eb7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564513963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.564513963
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3487813516
Short name T501
Test name
Test status
Simulation time 18878365 ps
CPU time 0.6 seconds
Started Jun 04 12:23:46 PM PDT 24
Finished Jun 04 12:23:47 PM PDT 24
Peak memory 181476 kb
Host smart-330803bb-63f3-4a5a-ba2e-f37e37c9c17b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487813516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3487813516
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3160532513
Short name T497
Test name
Test status
Simulation time 16204876 ps
CPU time 0.55 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:23:28 PM PDT 24
Peak memory 182480 kb
Host smart-75fef42d-a7af-4d02-8edc-46499dea0b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160532513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3160532513
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1802242696
Short name T87
Test name
Test status
Simulation time 87316508 ps
CPU time 0.78 seconds
Started Jun 04 12:24:00 PM PDT 24
Finished Jun 04 12:24:02 PM PDT 24
Peak memory 182516 kb
Host smart-69b9f25a-5dc6-4dbb-b32e-ee8acedcbd21
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802242696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1802242696
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2675504844
Short name T85
Test name
Test status
Simulation time 973216572 ps
CPU time 3.65 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:24:07 PM PDT 24
Peak memory 193516 kb
Host smart-ef359eff-5825-4dfb-943e-1002d2c9e27b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675504844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2675504844
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3108727316
Short name T469
Test name
Test status
Simulation time 31974665 ps
CPU time 0.61 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:23:37 PM PDT 24
Peak memory 181724 kb
Host smart-d3cdd598-548c-4063-b765-26f43815a5d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108727316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3108727316
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3403479015
Short name T579
Test name
Test status
Simulation time 18328630 ps
CPU time 0.7 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:23:22 PM PDT 24
Peak memory 194440 kb
Host smart-9142b3a7-87ad-4d01-a3aa-29167fa46efe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403479015 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3403479015
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.323149441
Short name T82
Test name
Test status
Simulation time 23183802 ps
CPU time 0.56 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:23:23 PM PDT 24
Peak memory 182240 kb
Host smart-d26d8cca-5c61-44d4-9e5a-992364dabe2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323149441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.323149441
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1553452520
Short name T564
Test name
Test status
Simulation time 16382135 ps
CPU time 0.56 seconds
Started Jun 04 12:23:44 PM PDT 24
Finished Jun 04 12:23:46 PM PDT 24
Peak memory 180984 kb
Host smart-9910eb53-7b5a-4698-bb8b-e11331afdda3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553452520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1553452520
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1574254814
Short name T33
Test name
Test status
Simulation time 20276025 ps
CPU time 0.76 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:23:37 PM PDT 24
Peak memory 192748 kb
Host smart-3c8525e7-416e-4ade-829d-482191aef8ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574254814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1574254814
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.571855392
Short name T479
Test name
Test status
Simulation time 151763165 ps
CPU time 2.58 seconds
Started Jun 04 12:23:59 PM PDT 24
Finished Jun 04 12:24:03 PM PDT 24
Peak memory 197180 kb
Host smart-2bc89b65-3443-4cb9-bb59-0c192cf16389
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571855392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.571855392
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1015983647
Short name T493
Test name
Test status
Simulation time 13353099 ps
CPU time 0.56 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:23:58 PM PDT 24
Peak memory 182404 kb
Host smart-cabbc13c-67f3-4e0d-8337-112d047be871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015983647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1015983647
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3237335088
Short name T532
Test name
Test status
Simulation time 120263182 ps
CPU time 0.54 seconds
Started Jun 04 12:23:44 PM PDT 24
Finished Jun 04 12:23:46 PM PDT 24
Peak memory 181392 kb
Host smart-47bc6d6c-ae1c-4b7f-b541-c946bae9c648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237335088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3237335088
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2502382824
Short name T462
Test name
Test status
Simulation time 14526712 ps
CPU time 0.54 seconds
Started Jun 04 12:23:39 PM PDT 24
Finished Jun 04 12:23:41 PM PDT 24
Peak memory 180380 kb
Host smart-7731f340-bcbc-4c94-a547-99ac993bdb89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502382824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2502382824
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1544640186
Short name T574
Test name
Test status
Simulation time 16408001 ps
CPU time 0.56 seconds
Started Jun 04 12:24:02 PM PDT 24
Finished Jun 04 12:24:05 PM PDT 24
Peak memory 182444 kb
Host smart-a6df7893-5633-410a-82fb-2e25a34c41c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544640186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1544640186
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1248932736
Short name T557
Test name
Test status
Simulation time 22881005 ps
CPU time 0.53 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:24:03 PM PDT 24
Peak memory 181888 kb
Host smart-5607e9c8-0c1d-41ed-a2fb-7348f9553e51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248932736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1248932736
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3447523493
Short name T565
Test name
Test status
Simulation time 101832112 ps
CPU time 0.6 seconds
Started Jun 04 12:20:14 PM PDT 24
Finished Jun 04 12:20:16 PM PDT 24
Peak memory 182432 kb
Host smart-6d1c0d2d-d508-41b5-8f38-a2b94ebc78ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447523493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3447523493
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.727649873
Short name T517
Test name
Test status
Simulation time 30078929 ps
CPU time 0.55 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:24:03 PM PDT 24
Peak memory 182404 kb
Host smart-a2d7066b-686e-447b-9d34-125a11a14050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727649873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.727649873
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3673053110
Short name T554
Test name
Test status
Simulation time 13031666 ps
CPU time 0.54 seconds
Started Jun 04 12:18:50 PM PDT 24
Finished Jun 04 12:18:51 PM PDT 24
Peak memory 181880 kb
Host smart-ab151039-83b9-4a35-a27d-81cb6b800f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673053110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3673053110
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2648064471
Short name T531
Test name
Test status
Simulation time 13044843 ps
CPU time 0.55 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:16 PM PDT 24
Peak memory 182168 kb
Host smart-6bbe4ca3-4f9c-449f-af19-d02be0882c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648064471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2648064471
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1758481647
Short name T530
Test name
Test status
Simulation time 15462766 ps
CPU time 0.61 seconds
Started Jun 04 12:18:25 PM PDT 24
Finished Jun 04 12:18:26 PM PDT 24
Peak memory 182440 kb
Host smart-3b746ace-0e21-4913-bfdc-ea4b31d4c71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758481647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1758481647
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2764489307
Short name T540
Test name
Test status
Simulation time 70589505 ps
CPU time 0.72 seconds
Started Jun 04 12:18:47 PM PDT 24
Finished Jun 04 12:18:49 PM PDT 24
Peak memory 194656 kb
Host smart-b6195130-9fb7-43f6-af8b-131614c91e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764489307 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2764489307
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3963301426
Short name T553
Test name
Test status
Simulation time 55972374 ps
CPU time 0.61 seconds
Started Jun 04 12:19:43 PM PDT 24
Finished Jun 04 12:19:45 PM PDT 24
Peak memory 180916 kb
Host smart-1279e4b4-28de-4eff-983b-d48b13527c75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963301426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3963301426
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2277475097
Short name T460
Test name
Test status
Simulation time 13640582 ps
CPU time 0.53 seconds
Started Jun 04 12:23:21 PM PDT 24
Finished Jun 04 12:23:23 PM PDT 24
Peak memory 182112 kb
Host smart-07a68cca-3525-4804-a439-8e5aca376b3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277475097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2277475097
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3684058987
Short name T578
Test name
Test status
Simulation time 62954264 ps
CPU time 0.77 seconds
Started Jun 04 12:24:00 PM PDT 24
Finished Jun 04 12:24:02 PM PDT 24
Peak memory 193144 kb
Host smart-d1cb59ce-214f-4447-8963-fa197187acda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684058987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3684058987
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.300114606
Short name T483
Test name
Test status
Simulation time 183261120 ps
CPU time 1.78 seconds
Started Jun 04 12:23:17 PM PDT 24
Finished Jun 04 12:23:20 PM PDT 24
Peak memory 195652 kb
Host smart-660be428-f100-4d45-b03e-38fed64f06c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300114606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.300114606
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.736036563
Short name T107
Test name
Test status
Simulation time 305038103 ps
CPU time 1.05 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:23:29 PM PDT 24
Peak memory 195008 kb
Host smart-257f8da8-bcd1-4b72-8e82-6aa3b3489497
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736036563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.736036563
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1113781573
Short name T515
Test name
Test status
Simulation time 278352087 ps
CPU time 0.87 seconds
Started Jun 04 12:18:47 PM PDT 24
Finished Jun 04 12:18:48 PM PDT 24
Peak memory 196976 kb
Host smart-538f130c-ab0a-4786-a90b-b7042367c83c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113781573 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1113781573
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1398450214
Short name T104
Test name
Test status
Simulation time 71074877 ps
CPU time 0.57 seconds
Started Jun 04 12:23:12 PM PDT 24
Finished Jun 04 12:23:14 PM PDT 24
Peak memory 182256 kb
Host smart-ad3c401d-4745-44ea-8ad3-59e523dcfb49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398450214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1398450214
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4109800921
Short name T562
Test name
Test status
Simulation time 12581734 ps
CPU time 0.54 seconds
Started Jun 04 12:18:41 PM PDT 24
Finished Jun 04 12:18:42 PM PDT 24
Peak memory 181844 kb
Host smart-5de20553-e330-4bd8-9ca0-35137c78c097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109800921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4109800921
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3142929277
Short name T74
Test name
Test status
Simulation time 19652498 ps
CPU time 0.82 seconds
Started Jun 04 12:24:00 PM PDT 24
Finished Jun 04 12:24:03 PM PDT 24
Peak memory 193332 kb
Host smart-691039b5-637c-4171-9e1d-2250cfa1a42b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142929277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3142929277
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.30364546
Short name T560
Test name
Test status
Simulation time 94375649 ps
CPU time 1.34 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:23:32 PM PDT 24
Peak memory 196604 kb
Host smart-2192743c-27b3-411f-873b-9426f0730024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30364546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.30364546
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4061634556
Short name T108
Test name
Test status
Simulation time 123673203 ps
CPU time 1.27 seconds
Started Jun 04 12:24:02 PM PDT 24
Finished Jun 04 12:24:05 PM PDT 24
Peak memory 194976 kb
Host smart-863ed8f3-116b-4e4e-978e-e690a2e729bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061634556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.4061634556
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.492628699
Short name T525
Test name
Test status
Simulation time 45776867 ps
CPU time 1.17 seconds
Started Jun 04 12:18:35 PM PDT 24
Finished Jun 04 12:18:36 PM PDT 24
Peak memory 197516 kb
Host smart-9228cdc1-8c6c-475e-a7d5-ad0987749c4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492628699 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.492628699
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.883859774
Short name T75
Test name
Test status
Simulation time 38520160 ps
CPU time 0.54 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:23:56 PM PDT 24
Peak memory 181524 kb
Host smart-f09cc739-bffd-496a-8bb8-dc7e5ba8e95c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883859774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.883859774
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.546767363
Short name T474
Test name
Test status
Simulation time 27611059 ps
CPU time 0.55 seconds
Started Jun 04 12:24:00 PM PDT 24
Finished Jun 04 12:24:02 PM PDT 24
Peak memory 182392 kb
Host smart-c0203495-709c-44ba-adf5-b84fa40ae99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546767363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.546767363
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2221643771
Short name T88
Test name
Test status
Simulation time 39939526 ps
CPU time 0.62 seconds
Started Jun 04 12:19:32 PM PDT 24
Finished Jun 04 12:19:33 PM PDT 24
Peak memory 191780 kb
Host smart-203e7a47-875b-4175-83aa-491948174edd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221643771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2221643771
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4181968571
Short name T571
Test name
Test status
Simulation time 45884390 ps
CPU time 1.04 seconds
Started Jun 04 12:23:44 PM PDT 24
Finished Jun 04 12:23:46 PM PDT 24
Peak memory 196428 kb
Host smart-8eee9d11-72c9-4fd1-a7d8-90353ecf7589
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181968571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4181968571
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4064723487
Short name T468
Test name
Test status
Simulation time 440930520 ps
CPU time 1.42 seconds
Started Jun 04 12:19:21 PM PDT 24
Finished Jun 04 12:19:23 PM PDT 24
Peak memory 195144 kb
Host smart-64e16555-dade-4ca2-a48f-e6935de7ca9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064723487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.4064723487
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2266456446
Short name T552
Test name
Test status
Simulation time 34655550 ps
CPU time 0.68 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:23:56 PM PDT 24
Peak memory 192588 kb
Host smart-151ccda8-30f4-4339-a788-bc4c5dc7ed51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266456446 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2266456446
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2045532906
Short name T81
Test name
Test status
Simulation time 25716687 ps
CPU time 0.57 seconds
Started Jun 04 12:18:46 PM PDT 24
Finished Jun 04 12:18:47 PM PDT 24
Peak memory 182672 kb
Host smart-f120a9d9-0257-4c3f-83cd-d4e5406d1646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045532906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2045532906
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1228747890
Short name T572
Test name
Test status
Simulation time 15197664 ps
CPU time 0.62 seconds
Started Jun 04 12:23:13 PM PDT 24
Finished Jun 04 12:23:15 PM PDT 24
Peak memory 181156 kb
Host smart-491f2d47-8444-4bfc-95ac-1c5edf8670cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228747890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1228747890
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3008387650
Short name T89
Test name
Test status
Simulation time 68759981 ps
CPU time 0.79 seconds
Started Jun 04 12:18:46 PM PDT 24
Finished Jun 04 12:18:47 PM PDT 24
Peak memory 193312 kb
Host smart-b676bf98-5241-4508-aef9-e72d3abb625f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008387650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3008387650
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.933134661
Short name T480
Test name
Test status
Simulation time 46548901 ps
CPU time 2.27 seconds
Started Jun 04 12:19:44 PM PDT 24
Finished Jun 04 12:19:46 PM PDT 24
Peak memory 196932 kb
Host smart-95181286-e7c7-444a-a6b3-e84b06f6013d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933134661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.933134661
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1529136089
Short name T106
Test name
Test status
Simulation time 229500785 ps
CPU time 1.1 seconds
Started Jun 04 12:23:56 PM PDT 24
Finished Jun 04 12:23:59 PM PDT 24
Peak memory 194784 kb
Host smart-3f018f06-4fec-47e2-b152-1647926a5c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529136089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1529136089
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3586328457
Short name T31
Test name
Test status
Simulation time 16973322 ps
CPU time 0.61 seconds
Started Jun 04 12:23:05 PM PDT 24
Finished Jun 04 12:23:07 PM PDT 24
Peak memory 193052 kb
Host smart-8517e580-7d3f-4664-9b50-a4d24eacca8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586328457 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3586328457
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.31032310
Short name T567
Test name
Test status
Simulation time 27565799 ps
CPU time 0.59 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:23:10 PM PDT 24
Peak memory 182256 kb
Host smart-1a5298f8-5ef3-496d-a6e1-42f79d0c6830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31032310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.31032310
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.202409927
Short name T541
Test name
Test status
Simulation time 10657631 ps
CPU time 0.54 seconds
Started Jun 04 12:22:34 PM PDT 24
Finished Jun 04 12:22:36 PM PDT 24
Peak memory 181084 kb
Host smart-5bc2241d-6c46-4475-af31-8301bbdb07ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202409927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.202409927
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1710562401
Short name T56
Test name
Test status
Simulation time 147089526 ps
CPU time 0.84 seconds
Started Jun 04 12:23:04 PM PDT 24
Finished Jun 04 12:23:06 PM PDT 24
Peak memory 191996 kb
Host smart-bdf163cd-7360-4520-b689-c33d888b34f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710562401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1710562401
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.72443016
Short name T473
Test name
Test status
Simulation time 50588198 ps
CPU time 1.23 seconds
Started Jun 04 12:23:13 PM PDT 24
Finished Jun 04 12:23:16 PM PDT 24
Peak memory 195800 kb
Host smart-1fed8ccd-6795-4931-a852-f3019ec806ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72443016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.72443016
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2928997376
Short name T30
Test name
Test status
Simulation time 703690965 ps
CPU time 0.99 seconds
Started Jun 04 12:18:12 PM PDT 24
Finished Jun 04 12:18:14 PM PDT 24
Peak memory 192596 kb
Host smart-c98da384-b093-469b-a427-8f7f04baeb9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928997376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2928997376
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2797061415
Short name T444
Test name
Test status
Simulation time 349493730214 ps
CPU time 350.18 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:29:00 PM PDT 24
Peak memory 180340 kb
Host smart-dd92954b-cabe-4413-916f-d27ebdd1ef8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797061415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2797061415
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2502191775
Short name T6
Test name
Test status
Simulation time 81551208105 ps
CPU time 138.68 seconds
Started Jun 04 12:21:47 PM PDT 24
Finished Jun 04 12:24:06 PM PDT 24
Peak memory 182804 kb
Host smart-ed086f4c-3fde-42e4-b6dc-aa93cd467dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502191775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2502191775
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.790093981
Short name T195
Test name
Test status
Simulation time 42609368409 ps
CPU time 71.72 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:24:48 PM PDT 24
Peak memory 182824 kb
Host smart-9743c155-c594-4743-b594-5e088f594c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790093981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.790093981
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3053199766
Short name T307
Test name
Test status
Simulation time 5614165223276 ps
CPU time 1072.64 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:41:08 PM PDT 24
Peak memory 195128 kb
Host smart-c74bbe1a-6c50-47f7-8b13-88aa03aff9d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053199766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3053199766
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.770845530
Short name T296
Test name
Test status
Simulation time 173606061661 ps
CPU time 281.06 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:28:17 PM PDT 24
Peak memory 182812 kb
Host smart-252cb7b5-7aa6-4199-b4c5-f4deb4fcb79d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770845530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.770845530
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.959037065
Short name T426
Test name
Test status
Simulation time 406120404300 ps
CPU time 171.07 seconds
Started Jun 04 12:23:08 PM PDT 24
Finished Jun 04 12:26:01 PM PDT 24
Peak memory 182468 kb
Host smart-6211645d-6270-4057-a533-9bd0124f32dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959037065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.959037065
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.9880322
Short name T210
Test name
Test status
Simulation time 338284932568 ps
CPU time 141.62 seconds
Started Jun 04 12:23:08 PM PDT 24
Finished Jun 04 12:25:31 PM PDT 24
Peak memory 189356 kb
Host smart-e66b0627-22fc-45f2-83fd-88b7eddc75d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9880322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.9880322
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.923818449
Short name T15
Test name
Test status
Simulation time 45150908 ps
CPU time 0.77 seconds
Started Jun 04 12:23:16 PM PDT 24
Finished Jun 04 12:23:19 PM PDT 24
Peak memory 213144 kb
Host smart-86e8d9a1-1ec8-43e3-8f74-7c1ef71b5498
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923818449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.923818449
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.4139411610
Short name T441
Test name
Test status
Simulation time 21834235 ps
CPU time 0.56 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:23:10 PM PDT 24
Peak memory 180160 kb
Host smart-ad08c1d0-8694-45c5-8bff-1845c9f58bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139411610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
4139411610
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2444949810
Short name T38
Test name
Test status
Simulation time 22501671727 ps
CPU time 242.14 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:27:39 PM PDT 24
Peak memory 197524 kb
Host smart-619c3326-9666-4943-9d4d-c9cea11112a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444949810 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2444949810
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1083419241
Short name T324
Test name
Test status
Simulation time 215921996920 ps
CPU time 200.94 seconds
Started Jun 04 12:22:49 PM PDT 24
Finished Jun 04 12:26:11 PM PDT 24
Peak memory 182940 kb
Host smart-140e167e-cb1b-4c6d-8884-4222129f3d82
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083419241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1083419241
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.266282192
Short name T376
Test name
Test status
Simulation time 38749732883 ps
CPU time 17.62 seconds
Started Jun 04 12:22:40 PM PDT 24
Finished Jun 04 12:22:59 PM PDT 24
Peak memory 182816 kb
Host smart-b7dbe44c-9c17-430e-83f1-8b804dec474a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266282192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.266282192
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1593311629
Short name T289
Test name
Test status
Simulation time 172801330963 ps
CPU time 159.32 seconds
Started Jun 04 12:22:48 PM PDT 24
Finished Jun 04 12:25:28 PM PDT 24
Peak memory 191380 kb
Host smart-b34edfca-32ec-4e8d-8029-9009df3e70b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593311629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1593311629
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3213017731
Short name T233
Test name
Test status
Simulation time 245433609951 ps
CPU time 78.85 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 12:25:34 PM PDT 24
Peak memory 193004 kb
Host smart-fa704ab9-1042-4487-b00b-a3edc2646c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213017731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3213017731
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.1639321156
Short name T175
Test name
Test status
Simulation time 19430175947 ps
CPU time 9.06 seconds
Started Jun 04 12:24:30 PM PDT 24
Finished Jun 04 12:24:40 PM PDT 24
Peak memory 182720 kb
Host smart-3dec4e6d-138a-49ee-8a90-f813cf7d2637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639321156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1639321156
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1417135271
Short name T277
Test name
Test status
Simulation time 451259331540 ps
CPU time 357.06 seconds
Started Jun 04 12:24:32 PM PDT 24
Finished Jun 04 12:30:30 PM PDT 24
Peak memory 191004 kb
Host smart-f9be0af2-7102-4374-b959-04f1e82e0bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417135271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1417135271
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.137126945
Short name T129
Test name
Test status
Simulation time 1225642805987 ps
CPU time 717.18 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:36:32 PM PDT 24
Peak memory 191004 kb
Host smart-da8da264-2d25-4d8d-9565-79c184b840fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137126945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.137126945
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1826034589
Short name T205
Test name
Test status
Simulation time 164190384624 ps
CPU time 438.08 seconds
Started Jun 04 12:24:32 PM PDT 24
Finished Jun 04 12:31:52 PM PDT 24
Peak memory 193176 kb
Host smart-368140fd-01b9-4851-bb57-9acb56d9cc6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826034589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1826034589
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3121796545
Short name T438
Test name
Test status
Simulation time 37706158987 ps
CPU time 62.27 seconds
Started Jun 04 12:24:29 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 193348 kb
Host smart-4dc80ea1-2ef5-42aa-bfc4-9872cfb7ef74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121796545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3121796545
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3222916174
Short name T70
Test name
Test status
Simulation time 141734305730 ps
CPU time 240.02 seconds
Started Jun 04 12:24:18 PM PDT 24
Finished Jun 04 12:28:20 PM PDT 24
Peak memory 191124 kb
Host smart-c3aadd81-4494-43ad-b63c-0607309408b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222916174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3222916174
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.588269026
Short name T99
Test name
Test status
Simulation time 217603081338 ps
CPU time 72.97 seconds
Started Jun 04 12:24:26 PM PDT 24
Finished Jun 04 12:25:41 PM PDT 24
Peak memory 182728 kb
Host smart-b150729f-25bd-4025-8f97-0d322b3f8245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588269026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.588269026
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2707824897
Short name T334
Test name
Test status
Simulation time 119766562635 ps
CPU time 170.73 seconds
Started Jun 04 12:22:48 PM PDT 24
Finished Jun 04 12:25:40 PM PDT 24
Peak memory 182820 kb
Host smart-bd623734-0d37-4487-be9f-6abda9ec5756
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707824897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2707824897
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1029556884
Short name T384
Test name
Test status
Simulation time 527979390235 ps
CPU time 156.36 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 12:26:51 PM PDT 24
Peak memory 181396 kb
Host smart-9ceb3d0d-e83f-4806-95d8-563823ffa095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029556884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1029556884
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2718100414
Short name T167
Test name
Test status
Simulation time 546471000029 ps
CPU time 585.08 seconds
Started Jun 04 12:22:49 PM PDT 24
Finished Jun 04 12:32:35 PM PDT 24
Peak memory 191000 kb
Host smart-ca651fb0-198d-41be-8657-44f30c19d4bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718100414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2718100414
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1125362608
Short name T399
Test name
Test status
Simulation time 19484667239 ps
CPU time 116.06 seconds
Started Jun 04 12:22:58 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 191004 kb
Host smart-0b16c4e3-0ba0-4112-b8b3-9bb9285b4de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125362608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1125362608
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.2588395878
Short name T101
Test name
Test status
Simulation time 138698446579 ps
CPU time 507.13 seconds
Started Jun 04 12:24:15 PM PDT 24
Finished Jun 04 12:32:44 PM PDT 24
Peak memory 211108 kb
Host smart-3fe75e5a-3fcd-4e18-a47b-185304da7822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588395878 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.2588395878
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2842926581
Short name T215
Test name
Test status
Simulation time 175650583385 ps
CPU time 557.4 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:33:58 PM PDT 24
Peak memory 190948 kb
Host smart-ae5d13e2-3f0f-4840-bc41-65a33ccaa8e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842926581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2842926581
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.936339248
Short name T8
Test name
Test status
Simulation time 278886538416 ps
CPU time 154.66 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:27:15 PM PDT 24
Peak memory 182804 kb
Host smart-a4553712-5b8c-4b6f-82f9-fefa56181eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936339248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.936339248
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1058154071
Short name T284
Test name
Test status
Simulation time 402109259838 ps
CPU time 310.06 seconds
Started Jun 04 12:24:29 PM PDT 24
Finished Jun 04 12:29:40 PM PDT 24
Peak memory 190992 kb
Host smart-e5fe2423-e909-48fe-b894-9216f8d8f91d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058154071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1058154071
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3457164483
Short name T171
Test name
Test status
Simulation time 238091053816 ps
CPU time 206.92 seconds
Started Jun 04 12:24:20 PM PDT 24
Finished Jun 04 12:27:49 PM PDT 24
Peak memory 190964 kb
Host smart-c07cd956-2c49-45c2-afb5-aee5ca1c9a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457164483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3457164483
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3927470116
Short name T279
Test name
Test status
Simulation time 442324273600 ps
CPU time 736.72 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:37:00 PM PDT 24
Peak memory 190880 kb
Host smart-1c7fb932-735f-49f0-84f4-a8aa99391341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927470116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3927470116
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1813284455
Short name T187
Test name
Test status
Simulation time 92260070128 ps
CPU time 148.84 seconds
Started Jun 04 12:22:58 PM PDT 24
Finished Jun 04 12:25:28 PM PDT 24
Peak memory 182820 kb
Host smart-bbdf8af1-5db4-4fd2-b24d-054085e36e5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813284455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1813284455
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3494441937
Short name T414
Test name
Test status
Simulation time 694976061552 ps
CPU time 236.64 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 12:28:11 PM PDT 24
Peak memory 181636 kb
Host smart-06f6aab4-f51a-442b-a7f5-bdc42c02e373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494441937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3494441937
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.595293714
Short name T186
Test name
Test status
Simulation time 194809984752 ps
CPU time 99.01 seconds
Started Jun 04 12:22:58 PM PDT 24
Finished Jun 04 12:24:38 PM PDT 24
Peak memory 191008 kb
Host smart-947fb7a1-c720-4895-bb29-beb1fde33596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595293714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.595293714
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1088389518
Short name T359
Test name
Test status
Simulation time 224275171624 ps
CPU time 256.81 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:27:37 PM PDT 24
Peak memory 193076 kb
Host smart-7076b349-d617-4140-a064-e724efe9770e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088389518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1088389518
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.895339641
Short name T433
Test name
Test status
Simulation time 838736843366 ps
CPU time 349.52 seconds
Started Jun 04 12:23:18 PM PDT 24
Finished Jun 04 12:29:09 PM PDT 24
Peak memory 190968 kb
Host smart-cf7120ad-2098-4cb5-993d-fd52b428560e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895339641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
895339641
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.407873588
Short name T137
Test name
Test status
Simulation time 257178088874 ps
CPU time 223.99 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:28:21 PM PDT 24
Peak memory 191004 kb
Host smart-c03b9d9f-9822-4c75-ba56-42533e2e4d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407873588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.407873588
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2975670128
Short name T314
Test name
Test status
Simulation time 98676214630 ps
CPU time 2613.83 seconds
Started Jun 04 12:24:27 PM PDT 24
Finished Jun 04 01:08:03 PM PDT 24
Peak memory 191000 kb
Host smart-a98d9948-9421-4b35-98d0-ae2e541fde11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975670128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2975670128
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2904134113
Short name T318
Test name
Test status
Simulation time 208071275902 ps
CPU time 165.79 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:27:27 PM PDT 24
Peak memory 190980 kb
Host smart-ee5081fc-30be-48e3-b529-53628a5a58b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904134113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2904134113
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2701360770
Short name T412
Test name
Test status
Simulation time 41830909878 ps
CPU time 65.87 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:25:47 PM PDT 24
Peak memory 182772 kb
Host smart-68823c29-381d-41fd-a000-a304918cc230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701360770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2701360770
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.827045467
Short name T25
Test name
Test status
Simulation time 161906951921 ps
CPU time 2299.68 seconds
Started Jun 04 12:24:21 PM PDT 24
Finished Jun 04 01:02:43 PM PDT 24
Peak memory 190936 kb
Host smart-2bff05a7-e7a6-4d28-8a98-083183552d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827045467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.827045467
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.931775849
Short name T451
Test name
Test status
Simulation time 40175853540 ps
CPU time 67.62 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:25:48 PM PDT 24
Peak memory 182784 kb
Host smart-3bf89c0b-de2c-4150-a9ca-4eac97b5eb14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931775849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.931775849
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2520025244
Short name T180
Test name
Test status
Simulation time 128672319810 ps
CPU time 186.1 seconds
Started Jun 04 12:24:33 PM PDT 24
Finished Jun 04 12:27:41 PM PDT 24
Peak memory 191120 kb
Host smart-48dcc091-4200-469e-85a4-04dfbb74cc88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520025244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2520025244
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3514991906
Short name T52
Test name
Test status
Simulation time 831337398748 ps
CPU time 420.14 seconds
Started Jun 04 12:23:08 PM PDT 24
Finished Jun 04 12:30:10 PM PDT 24
Peak memory 182820 kb
Host smart-cc2dc5cb-d418-4c84-a534-68a824146c58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514991906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3514991906
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_random.1745735325
Short name T154
Test name
Test status
Simulation time 807038635650 ps
CPU time 248.44 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:27:29 PM PDT 24
Peak memory 190940 kb
Host smart-02936e07-0caf-4097-84e9-2fd90bfc42e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745735325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1745735325
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1949728217
Short name T409
Test name
Test status
Simulation time 104151790 ps
CPU time 0.71 seconds
Started Jun 04 12:23:26 PM PDT 24
Finished Jun 04 12:23:27 PM PDT 24
Peak memory 182612 kb
Host smart-241e9ccb-3090-452e-a270-bac91305074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949728217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1949728217
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.4274917321
Short name T298
Test name
Test status
Simulation time 404607371481 ps
CPU time 407.57 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:31:27 PM PDT 24
Peak memory 190996 kb
Host smart-e30efcf7-90c3-463c-a964-9624e2bfd634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274917321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.4274917321
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.629112737
Short name T340
Test name
Test status
Simulation time 49810714679 ps
CPU time 22.61 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:24:58 PM PDT 24
Peak memory 182776 kb
Host smart-58991b36-25f9-43eb-87d0-daa5178432ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629112737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.629112737
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2568342494
Short name T303
Test name
Test status
Simulation time 338373842194 ps
CPU time 163.24 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:27:19 PM PDT 24
Peak memory 190732 kb
Host smart-a6136923-36d6-4318-8a0d-81dd067f32da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568342494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2568342494
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1290801274
Short name T302
Test name
Test status
Simulation time 38681191834 ps
CPU time 102.66 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:26:20 PM PDT 24
Peak memory 182720 kb
Host smart-a55b1ba1-6e20-49bc-9c99-895960070682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290801274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1290801274
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2962013062
Short name T249
Test name
Test status
Simulation time 427023802614 ps
CPU time 1899.01 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:56:18 PM PDT 24
Peak memory 190988 kb
Host smart-a4d16780-67eb-4670-9126-28c8c5867ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962013062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2962013062
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3474521995
Short name T188
Test name
Test status
Simulation time 107860972315 ps
CPU time 157.4 seconds
Started Jun 04 12:24:45 PM PDT 24
Finished Jun 04 12:27:23 PM PDT 24
Peak memory 195072 kb
Host smart-d8c8b93f-bf4b-4abd-b0f1-fb12fdcf0c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474521995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3474521995
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2422496485
Short name T448
Test name
Test status
Simulation time 30205137498 ps
CPU time 31.81 seconds
Started Jun 04 12:23:18 PM PDT 24
Finished Jun 04 12:23:50 PM PDT 24
Peak memory 182788 kb
Host smart-93ce35b8-2e27-4fbb-9249-3a0afdfe02d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422496485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2422496485
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3003525693
Short name T385
Test name
Test status
Simulation time 12149102563 ps
CPU time 20.43 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:23:40 PM PDT 24
Peak memory 182724 kb
Host smart-82662733-7685-4a4e-8ada-917cb8129aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003525693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3003525693
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.329839151
Short name T227
Test name
Test status
Simulation time 16194960212 ps
CPU time 51.13 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:24:12 PM PDT 24
Peak memory 182772 kb
Host smart-479988a0-f56b-4980-b866-9a43a30b065a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329839151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.329839151
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4184422666
Short name T434
Test name
Test status
Simulation time 344195744811 ps
CPU time 519.28 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:32:12 PM PDT 24
Peak memory 190968 kb
Host smart-756fcf26-2dc5-4a27-9af8-519e64ad3dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184422666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4184422666
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.4116712952
Short name T269
Test name
Test status
Simulation time 18239021459 ps
CPU time 38.6 seconds
Started Jun 04 12:24:30 PM PDT 24
Finished Jun 04 12:25:10 PM PDT 24
Peak memory 182720 kb
Host smart-fead5808-7097-4719-9f7d-11f19c434174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116712952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4116712952
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.687155504
Short name T122
Test name
Test status
Simulation time 16691877160 ps
CPU time 31.23 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:25:06 PM PDT 24
Peak memory 191116 kb
Host smart-5b369a1f-1bb0-4988-9711-40e66e1d0392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687155504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.687155504
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.445791107
Short name T121
Test name
Test status
Simulation time 134743181036 ps
CPU time 567.45 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:34:06 PM PDT 24
Peak memory 190948 kb
Host smart-4d30f333-3062-4fb5-b76e-c9739f4225b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445791107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.445791107
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3242376494
Short name T310
Test name
Test status
Simulation time 56459550014 ps
CPU time 90.67 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:26:05 PM PDT 24
Peak memory 191112 kb
Host smart-391f3fed-1e80-4d87-864b-5bceb451d3bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242376494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3242376494
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.527974798
Short name T358
Test name
Test status
Simulation time 1869386859055 ps
CPU time 570.18 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:32:50 PM PDT 24
Peak memory 182772 kb
Host smart-070327a1-db55-4342-ad98-0b1ec7b95e8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527974798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.527974798
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3420014681
Short name T397
Test name
Test status
Simulation time 88532927589 ps
CPU time 71.65 seconds
Started Jun 04 12:23:18 PM PDT 24
Finished Jun 04 12:24:31 PM PDT 24
Peak memory 182784 kb
Host smart-89e25653-3862-4b00-bfdf-bb5a6acc4584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420014681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3420014681
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3241989460
Short name T432
Test name
Test status
Simulation time 190358615897 ps
CPU time 59.8 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:24:20 PM PDT 24
Peak memory 182748 kb
Host smart-3eec1668-b886-4b6b-8b2f-933c841b4711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241989460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3241989460
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2988345183
Short name T322
Test name
Test status
Simulation time 11228321682 ps
CPU time 53.35 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:24:14 PM PDT 24
Peak memory 193096 kb
Host smart-3dd1eac5-9708-47ee-9a87-a2e292ee43df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988345183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2988345183
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.2130988069
Short name T350
Test name
Test status
Simulation time 10486223397 ps
CPU time 9.65 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:24:44 PM PDT 24
Peak memory 182920 kb
Host smart-0014399d-a4f1-4947-80ab-05b48f1f06d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130988069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2130988069
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.71864125
Short name T271
Test name
Test status
Simulation time 53170814026 ps
CPU time 105.59 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:26:28 PM PDT 24
Peak memory 182804 kb
Host smart-348e9506-d361-4b0f-822b-939dd687b1d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71864125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.71864125
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1085204687
Short name T176
Test name
Test status
Simulation time 44440240931 ps
CPU time 108.45 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 190996 kb
Host smart-6e33e346-476b-40fa-9de4-01b12f2adf4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085204687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1085204687
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2585319530
Short name T347
Test name
Test status
Simulation time 99595510509 ps
CPU time 66.76 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 191008 kb
Host smart-d7df1399-9feb-4be7-9e87-e63125d019ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585319530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2585319530
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.599060856
Short name T333
Test name
Test status
Simulation time 627277183308 ps
CPU time 1435.25 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:48:34 PM PDT 24
Peak memory 191000 kb
Host smart-6739b3da-966b-42c1-a557-3cd19db5dcf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599060856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.599060856
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.4108008006
Short name T128
Test name
Test status
Simulation time 3592288594 ps
CPU time 3.51 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:24:42 PM PDT 24
Peak memory 182648 kb
Host smart-512983fb-9a06-410a-a73b-f31ab4bcd1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108008006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4108008006
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.325377543
Short name T417
Test name
Test status
Simulation time 109036299261 ps
CPU time 150.36 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 182720 kb
Host smart-a9909d9a-4205-4320-a11a-ddcc5a176d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325377543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.325377543
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2582944607
Short name T239
Test name
Test status
Simulation time 327371135158 ps
CPU time 88.4 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:24:49 PM PDT 24
Peak memory 190900 kb
Host smart-e932e2b7-a2f2-4ab8-95d4-d312c6f9b8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582944607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2582944607
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.3778158035
Short name T182
Test name
Test status
Simulation time 416623668339 ps
CPU time 122.74 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:26:50 PM PDT 24
Peak memory 190940 kb
Host smart-d42b645a-846e-4d0e-9ed0-ac650eaa9a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778158035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3778158035
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3774696755
Short name T257
Test name
Test status
Simulation time 263604477467 ps
CPU time 515.88 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:33:14 PM PDT 24
Peak memory 193228 kb
Host smart-04afc22f-8162-4996-b2f8-21c6f4d9011e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774696755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3774696755
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2026104892
Short name T181
Test name
Test status
Simulation time 85676586599 ps
CPU time 382.95 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:31:04 PM PDT 24
Peak memory 190952 kb
Host smart-4d75f78e-6c4f-4a85-afbc-47e80ddbcde3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026104892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2026104892
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.447934617
Short name T300
Test name
Test status
Simulation time 68896105070 ps
CPU time 108.35 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 182756 kb
Host smart-0ff0c7e4-3ee6-4e5a-bc67-3e8e1d77db57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447934617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.447934617
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1921777584
Short name T130
Test name
Test status
Simulation time 83308810124 ps
CPU time 131.11 seconds
Started Jun 04 12:24:45 PM PDT 24
Finished Jun 04 12:26:57 PM PDT 24
Peak memory 190940 kb
Host smart-f0f0cf45-0d32-4a59-bd28-91e1d5da5379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921777584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1921777584
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2829091562
Short name T247
Test name
Test status
Simulation time 1246919151840 ps
CPU time 378.27 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:30:58 PM PDT 24
Peak memory 190952 kb
Host smart-db866019-5f6d-45bd-adda-e611e7dfd6a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829091562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2829091562
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2463120893
Short name T258
Test name
Test status
Simulation time 3200150040 ps
CPU time 5.95 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:24:47 PM PDT 24
Peak memory 182744 kb
Host smart-d60b599f-611e-428b-af1d-f69d525cadc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463120893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2463120893
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4285137113
Short name T317
Test name
Test status
Simulation time 253340227564 ps
CPU time 264.59 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:29:04 PM PDT 24
Peak memory 192988 kb
Host smart-84cac0bd-103d-4a03-9fc6-8627a85599e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285137113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4285137113
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.455505942
Short name T372
Test name
Test status
Simulation time 199917528798 ps
CPU time 337.67 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:29:05 PM PDT 24
Peak memory 182776 kb
Host smart-0e472340-7a5b-49f2-818b-29f2f5e2dfcd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455505942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.455505942
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.359970119
Short name T396
Test name
Test status
Simulation time 139878945829 ps
CPU time 195.76 seconds
Started Jun 04 12:23:28 PM PDT 24
Finished Jun 04 12:26:44 PM PDT 24
Peak memory 182532 kb
Host smart-7d756d59-aab4-4609-8385-eb6a31a9d303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359970119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.359970119
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3575893585
Short name T201
Test name
Test status
Simulation time 492799142189 ps
CPU time 517.46 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:31:58 PM PDT 24
Peak memory 193892 kb
Host smart-cac4016d-8357-41ce-9f49-7eced16cdd17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575893585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3575893585
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1584499332
Short name T411
Test name
Test status
Simulation time 91677087 ps
CPU time 0.61 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:23:28 PM PDT 24
Peak memory 182580 kb
Host smart-e1a99b4f-ee47-49e3-8209-2ea59d9e3846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584499332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1584499332
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3415241200
Short name T214
Test name
Test status
Simulation time 520777998690 ps
CPU time 779.19 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:36:27 PM PDT 24
Peak memory 190980 kb
Host smart-0372b4df-fb8b-4fa4-ba7b-13873a72a3dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415241200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3415241200
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.282601679
Short name T40
Test name
Test status
Simulation time 104695255693 ps
CPU time 265.44 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:27:46 PM PDT 24
Peak memory 197420 kb
Host smart-64bc8eb2-a6aa-4329-97e6-bf63fd263666
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282601679 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.282601679
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.2588432644
Short name T292
Test name
Test status
Simulation time 66161737823 ps
CPU time 118.87 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 190944 kb
Host smart-ce29c0cb-3b6b-4374-b293-96e1f90e37d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588432644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2588432644
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1804618792
Short name T276
Test name
Test status
Simulation time 71821947502 ps
CPU time 121.16 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:26:41 PM PDT 24
Peak memory 190952 kb
Host smart-a203e3d7-50a8-47dd-b485-78479f201bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804618792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1804618792
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2910634060
Short name T316
Test name
Test status
Simulation time 174008546521 ps
CPU time 746.68 seconds
Started Jun 04 12:24:33 PM PDT 24
Finished Jun 04 12:37:01 PM PDT 24
Peak memory 190972 kb
Host smart-d03be56b-206c-4e97-bc73-449b27e2070a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910634060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2910634060
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2825716195
Short name T327
Test name
Test status
Simulation time 38172750583 ps
CPU time 8.22 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:24:47 PM PDT 24
Peak memory 182752 kb
Host smart-c214a985-f91c-4b7a-958d-17705693c28d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825716195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2825716195
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1576377711
Short name T349
Test name
Test status
Simulation time 347804540952 ps
CPU time 673.8 seconds
Started Jun 04 12:24:43 PM PDT 24
Finished Jun 04 12:35:58 PM PDT 24
Peak memory 190948 kb
Host smart-488a9920-40ee-49c3-b0b0-9641c83dfe63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576377711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1576377711
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1787405685
Short name T325
Test name
Test status
Simulation time 6333474587 ps
CPU time 10.2 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:24:50 PM PDT 24
Peak memory 182752 kb
Host smart-06cad760-585d-44b5-b645-367aa33280e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787405685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1787405685
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.211634347
Short name T216
Test name
Test status
Simulation time 66182412150 ps
CPU time 394.43 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:31:15 PM PDT 24
Peak memory 182780 kb
Host smart-3fdeeb1e-f5be-4a2c-8499-6832ad979fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211634347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.211634347
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1722351118
Short name T65
Test name
Test status
Simulation time 631262996743 ps
CPU time 87.21 seconds
Started Jun 04 12:23:26 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 182780 kb
Host smart-ecdf485b-9def-42ae-98e7-f59a2ada0a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722351118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1722351118
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2800091699
Short name T373
Test name
Test status
Simulation time 30766768282 ps
CPU time 24.3 seconds
Started Jun 04 12:23:24 PM PDT 24
Finished Jun 04 12:23:49 PM PDT 24
Peak memory 182664 kb
Host smart-e0b71aab-db47-4325-af17-2cddef344f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800091699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2800091699
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.409295728
Short name T406
Test name
Test status
Simulation time 25669624 ps
CPU time 0.53 seconds
Started Jun 04 12:23:19 PM PDT 24
Finished Jun 04 12:23:21 PM PDT 24
Peak memory 182548 kb
Host smart-0dd52273-987e-40f1-8b74-36b04b86f4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409295728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.409295728
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3090110371
Short name T341
Test name
Test status
Simulation time 193494580732 ps
CPU time 106.05 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:26:27 PM PDT 24
Peak memory 190976 kb
Host smart-933c23eb-4eff-4cef-9aa3-7dd9e50b331d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090110371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3090110371
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.500052025
Short name T228
Test name
Test status
Simulation time 448477769837 ps
CPU time 294.83 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:29:37 PM PDT 24
Peak memory 190972 kb
Host smart-11d929e6-c5bd-415f-9bb6-ae9c878c583a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500052025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.500052025
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.459050406
Short name T331
Test name
Test status
Simulation time 134054690511 ps
CPU time 64.74 seconds
Started Jun 04 12:24:41 PM PDT 24
Finished Jun 04 12:25:49 PM PDT 24
Peak memory 182784 kb
Host smart-ac4bada6-c50e-4d1f-ba18-5a78a2028546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459050406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.459050406
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1330683095
Short name T240
Test name
Test status
Simulation time 160094086920 ps
CPU time 126.91 seconds
Started Jun 04 12:24:42 PM PDT 24
Finished Jun 04 12:26:51 PM PDT 24
Peak memory 190988 kb
Host smart-b31b9de0-6d33-461c-abb5-7c6aa5cbcd30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330683095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1330683095
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3153971260
Short name T260
Test name
Test status
Simulation time 830998195511 ps
CPU time 210.41 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:28:11 PM PDT 24
Peak memory 190968 kb
Host smart-6f79aeac-ce97-4b11-b59f-707f805e9d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153971260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3153971260
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2146126944
Short name T423
Test name
Test status
Simulation time 82462932554 ps
CPU time 68.56 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 190976 kb
Host smart-05eecb84-2410-4d0d-8b80-c37448a31aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146126944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2146126944
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1926106249
Short name T184
Test name
Test status
Simulation time 133034296672 ps
CPU time 290.63 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:29:33 PM PDT 24
Peak memory 190968 kb
Host smart-62be655c-5b79-46d6-900d-fd6bc3345afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926106249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1926106249
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4101110741
Short name T443
Test name
Test status
Simulation time 532916394984 ps
CPU time 439.44 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:30:41 PM PDT 24
Peak memory 182724 kb
Host smart-6fb28f0f-4bb1-4306-b349-a74ba239b68a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101110741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4101110741
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1527035075
Short name T402
Test name
Test status
Simulation time 176186945353 ps
CPU time 71.58 seconds
Started Jun 04 12:23:20 PM PDT 24
Finished Jun 04 12:24:33 PM PDT 24
Peak memory 182724 kb
Host smart-bcd5b303-c1d9-4cd4-acea-20d8f2ddc79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527035075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1527035075
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.27713915
Short name T2
Test name
Test status
Simulation time 241707385525 ps
CPU time 199.19 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:26:51 PM PDT 24
Peak memory 194420 kb
Host smart-809353a1-06bd-42be-bfda-6cc085144ba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27713915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.27713915
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3310494343
Short name T120
Test name
Test status
Simulation time 469449305026 ps
CPU time 56.59 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:24:25 PM PDT 24
Peak memory 182708 kb
Host smart-a7266ce8-cc09-4dbf-9b35-28194994d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310494343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3310494343
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1856780699
Short name T231
Test name
Test status
Simulation time 174196584273 ps
CPU time 92.66 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:26:15 PM PDT 24
Peak memory 190980 kb
Host smart-4361baa8-29c4-41e7-b5e8-e6e81d8eac22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856780699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1856780699
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.4167488593
Short name T174
Test name
Test status
Simulation time 40867592942 ps
CPU time 85.55 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:26:07 PM PDT 24
Peak memory 193172 kb
Host smart-9194ada3-c5b3-4a34-b5ac-7665b20e89ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167488593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.4167488593
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2817889493
Short name T374
Test name
Test status
Simulation time 85912628500 ps
CPU time 331.02 seconds
Started Jun 04 12:24:44 PM PDT 24
Finished Jun 04 12:30:17 PM PDT 24
Peak memory 191068 kb
Host smart-e45d6316-0d13-4a99-9b1a-39ed8519193f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817889493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2817889493
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.5311555
Short name T116
Test name
Test status
Simulation time 176781600360 ps
CPU time 135.26 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:26:56 PM PDT 24
Peak memory 190972 kb
Host smart-0e348d6f-9934-49ee-a2f7-f134be920f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5311555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.5311555
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3404603623
Short name T297
Test name
Test status
Simulation time 46114788783 ps
CPU time 152.79 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:27:15 PM PDT 24
Peak memory 182776 kb
Host smart-c25fd706-d214-4070-91fb-bc1da9198489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404603623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3404603623
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2998949277
Short name T95
Test name
Test status
Simulation time 349845312788 ps
CPU time 118.64 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:26:37 PM PDT 24
Peak memory 182768 kb
Host smart-7185e1b8-ca65-4b7d-818a-4c47b277ecfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998949277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2998949277
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1371511313
Short name T41
Test name
Test status
Simulation time 42676786787 ps
CPU time 76.98 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:25:56 PM PDT 24
Peak memory 190976 kb
Host smart-cad7ddb0-7c27-41fc-b715-2cff09421f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371511313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1371511313
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1580886529
Short name T229
Test name
Test status
Simulation time 186503977524 ps
CPU time 302.8 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:28:12 PM PDT 24
Peak memory 180628 kb
Host smart-f6b7c788-370e-4e09-be18-5c72c3db8e43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580886529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1580886529
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2906571119
Short name T440
Test name
Test status
Simulation time 530919720543 ps
CPU time 197.73 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:26:33 PM PDT 24
Peak memory 181224 kb
Host smart-d7b3c7a4-2b4b-4372-87df-ab6aa3f5e01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906571119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2906571119
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1785072496
Short name T361
Test name
Test status
Simulation time 57771328832 ps
CPU time 42.9 seconds
Started Jun 04 12:23:14 PM PDT 24
Finished Jun 04 12:23:58 PM PDT 24
Peak memory 181256 kb
Host smart-a5c85794-45a7-4582-b45d-d0095d3fb142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785072496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1785072496
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.78507071
Short name T18
Test name
Test status
Simulation time 65572190 ps
CPU time 0.9 seconds
Started Jun 04 12:23:35 PM PDT 24
Finished Jun 04 12:23:38 PM PDT 24
Peak memory 212612 kb
Host smart-ef035737-3c96-41b4-a116-292733209aca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78507071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.78507071
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2850848734
Short name T13
Test name
Test status
Simulation time 42534898477 ps
CPU time 257.96 seconds
Started Jun 04 12:23:07 PM PDT 24
Finished Jun 04 12:27:28 PM PDT 24
Peak memory 203196 kb
Host smart-cc045fde-a06a-4012-85a7-f9d019d04db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850848734 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2850848734
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.4262238317
Short name T280
Test name
Test status
Simulation time 490898445409 ps
CPU time 914.76 seconds
Started Jun 04 12:23:27 PM PDT 24
Finished Jun 04 12:38:43 PM PDT 24
Peak memory 182800 kb
Host smart-9e3afc92-2b5d-45ec-a2a1-a069027e60a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262238317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.4262238317
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_random.3436944801
Short name T100
Test name
Test status
Simulation time 160336439319 ps
CPU time 132.96 seconds
Started Jun 04 12:23:29 PM PDT 24
Finished Jun 04 12:25:44 PM PDT 24
Peak memory 182716 kb
Host smart-d9febfec-99ce-4f1d-a6ee-ffc76f3614d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436944801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3436944801
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.450262812
Short name T146
Test name
Test status
Simulation time 222085029407 ps
CPU time 263.53 seconds
Started Jun 04 12:23:26 PM PDT 24
Finished Jun 04 12:27:50 PM PDT 24
Peak memory 190984 kb
Host smart-336983ec-60cd-4a77-96c9-3e55ea6ddf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450262812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.450262812
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2543078126
Short name T115
Test name
Test status
Simulation time 261644074062 ps
CPU time 721.92 seconds
Started Jun 04 12:23:28 PM PDT 24
Finished Jun 04 12:35:31 PM PDT 24
Peak memory 190960 kb
Host smart-467338c4-7566-4484-8e2b-bbbc5771f468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543078126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2543078126
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3619102836
Short name T14
Test name
Test status
Simulation time 24747759183 ps
CPU time 168.62 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:26:20 PM PDT 24
Peak memory 197388 kb
Host smart-64884878-4757-4f9e-bddd-02a64f7cd002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619102836 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3619102836
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2295819926
Short name T246
Test name
Test status
Simulation time 526332323022 ps
CPU time 576.39 seconds
Started Jun 04 12:24:03 PM PDT 24
Finished Jun 04 12:33:41 PM PDT 24
Peak memory 183164 kb
Host smart-bcc652ce-867d-4c93-8ff3-17a9bbf42258
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295819926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2295819926
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3300063394
Short name T398
Test name
Test status
Simulation time 631933944798 ps
CPU time 166.58 seconds
Started Jun 04 12:24:32 PM PDT 24
Finished Jun 04 12:27:20 PM PDT 24
Peak memory 183168 kb
Host smart-891f624a-91d6-49da-8b67-fadec18f1d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300063394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3300063394
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2001508142
Short name T285
Test name
Test status
Simulation time 477715998965 ps
CPU time 940.01 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:39:53 PM PDT 24
Peak memory 194328 kb
Host smart-2f97abe7-300b-4dee-b82f-5c97cff8b8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001508142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2001508142
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1124607769
Short name T119
Test name
Test status
Simulation time 280387550600 ps
CPU time 796.55 seconds
Started Jun 04 12:23:25 PM PDT 24
Finished Jun 04 12:36:42 PM PDT 24
Peak memory 194840 kb
Host smart-5948f3bb-204b-4f06-9a1d-a21548638162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124607769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1124607769
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.710230862
Short name T102
Test name
Test status
Simulation time 101192437250 ps
CPU time 1261.93 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:45:18 PM PDT 24
Peak memory 213464 kb
Host smart-3a1ae183-c063-4747-af2c-ca97b36e8007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710230862 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.710230862
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2834231752
Short name T404
Test name
Test status
Simulation time 224440156628 ps
CPU time 85.97 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:25:37 PM PDT 24
Peak memory 182812 kb
Host smart-8675d94f-8d47-48a4-9719-5bea7483a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834231752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2834231752
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.611937750
Short name T109
Test name
Test status
Simulation time 291727345454 ps
CPU time 323.08 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:30:02 PM PDT 24
Peak memory 190992 kb
Host smart-922c3648-54fa-423a-ab49-ca95c01d9a9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611937750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.611937750
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4041604608
Short name T366
Test name
Test status
Simulation time 76873106793 ps
CPU time 64.26 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:25:45 PM PDT 24
Peak memory 191016 kb
Host smart-ce6db760-74f3-45c4-9b3e-00e6c4625ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041604608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4041604608
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1889212963
Short name T3
Test name
Test status
Simulation time 1086858145016 ps
CPU time 440.48 seconds
Started Jun 04 12:23:25 PM PDT 24
Finished Jun 04 12:30:46 PM PDT 24
Peak memory 190984 kb
Host smart-076b8f43-fc2e-4dd6-b813-6b5a7095090e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889212963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1889212963
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.812267905
Short name T435
Test name
Test status
Simulation time 364709056728 ps
CPU time 342.24 seconds
Started Jun 04 12:24:41 PM PDT 24
Finished Jun 04 12:30:26 PM PDT 24
Peak memory 182792 kb
Host smart-7b198fad-5dbf-4237-be11-b6ebfde7532d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812267905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.812267905
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3899655295
Short name T403
Test name
Test status
Simulation time 912601506605 ps
CPU time 189.45 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:27:51 PM PDT 24
Peak memory 182804 kb
Host smart-9ef0a1bf-2efb-4699-9afa-f8ab01d98e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899655295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3899655295
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3113293489
Short name T241
Test name
Test status
Simulation time 409064940220 ps
CPU time 496.28 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:32:58 PM PDT 24
Peak memory 191004 kb
Host smart-3c9f33a4-fbaf-4dc1-abcb-a65489be98ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113293489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3113293489
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3432588200
Short name T420
Test name
Test status
Simulation time 45627692975 ps
CPU time 74.92 seconds
Started Jun 04 12:23:30 PM PDT 24
Finished Jun 04 12:24:48 PM PDT 24
Peak memory 190968 kb
Host smart-3fee88b4-986d-4e8c-83a0-c8439cc9b591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432588200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3432588200
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2282461167
Short name T63
Test name
Test status
Simulation time 857280858957 ps
CPU time 608.01 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:34:49 PM PDT 24
Peak memory 195472 kb
Host smart-e00db195-a0ac-4ff7-a355-8ac6a65e8ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282461167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2282461167
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2847669326
Short name T405
Test name
Test status
Simulation time 69735860936 ps
CPU time 60.54 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:25:41 PM PDT 24
Peak memory 182804 kb
Host smart-f8ec438e-a423-4989-aa67-fd63f5c30376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847669326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2847669326
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1105621509
Short name T22
Test name
Test status
Simulation time 67616136046 ps
CPU time 196.67 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:27:52 PM PDT 24
Peak memory 191012 kb
Host smart-e8659aa2-60cb-4ed3-a57a-b0d3d91d05cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105621509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1105621509
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2475891245
Short name T364
Test name
Test status
Simulation time 1051330027404 ps
CPU time 350.84 seconds
Started Jun 04 12:23:51 PM PDT 24
Finished Jun 04 12:29:43 PM PDT 24
Peak memory 190976 kb
Host smart-d44b5dc4-4a47-410a-9029-46ba75edf542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475891245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2475891245
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3368532330
Short name T319
Test name
Test status
Simulation time 431860664385 ps
CPU time 771.39 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:37:28 PM PDT 24
Peak memory 182812 kb
Host smart-42af07d8-21d4-4bcf-9641-5e2b86371490
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368532330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3368532330
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.809132633
Short name T449
Test name
Test status
Simulation time 30007989858 ps
CPU time 42.8 seconds
Started Jun 04 12:23:51 PM PDT 24
Finished Jun 04 12:24:35 PM PDT 24
Peak memory 182776 kb
Host smart-066f080c-fc46-4b20-9949-1980e12edd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809132633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.809132633
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3745047323
Short name T209
Test name
Test status
Simulation time 428032710527 ps
CPU time 1113.27 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:43:13 PM PDT 24
Peak memory 190992 kb
Host smart-06a9be29-995a-427e-aaca-dc490996cfd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745047323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3745047323
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.695398257
Short name T48
Test name
Test status
Simulation time 63199482169 ps
CPU time 102.76 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:25:54 PM PDT 24
Peak memory 190976 kb
Host smart-99d9a4d8-8e6f-472a-930d-f0235119fdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695398257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.695398257
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2611129465
Short name T218
Test name
Test status
Simulation time 1757206055165 ps
CPU time 1346.08 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:46:40 PM PDT 24
Peak memory 190980 kb
Host smart-d1b6a2a1-6ce5-41f2-905a-b43341445929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611129465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2611129465
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2247384084
Short name T394
Test name
Test status
Simulation time 767922653177 ps
CPU time 328.65 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:29:39 PM PDT 24
Peak memory 182808 kb
Host smart-5cc6b4fc-493e-4dd6-b487-6fe6a15da9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247384084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2247384084
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1971742496
Short name T330
Test name
Test status
Simulation time 167179007006 ps
CPU time 37.24 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:24:49 PM PDT 24
Peak memory 182776 kb
Host smart-1e906c90-77ac-47a6-beb8-34607d6cf915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971742496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1971742496
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3621646414
Short name T367
Test name
Test status
Simulation time 22446690553 ps
CPU time 38.23 seconds
Started Jun 04 12:24:07 PM PDT 24
Finished Jun 04 12:24:46 PM PDT 24
Peak memory 191680 kb
Host smart-b6375bb5-014a-41da-b911-525261b044a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621646414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3621646414
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_random.2019732721
Short name T173
Test name
Test status
Simulation time 317881918410 ps
CPU time 285.93 seconds
Started Jun 04 12:24:04 PM PDT 24
Finished Jun 04 12:28:51 PM PDT 24
Peak memory 191064 kb
Host smart-58d08743-5977-4392-8e1d-de0770c43aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019732721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2019732721
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3980931538
Short name T326
Test name
Test status
Simulation time 203311919912 ps
CPU time 256.64 seconds
Started Jun 04 12:24:05 PM PDT 24
Finished Jun 04 12:28:23 PM PDT 24
Peak memory 191116 kb
Host smart-ae280062-1760-4032-a5f9-a9b21be38ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980931538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3980931538
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.703881643
Short name T348
Test name
Test status
Simulation time 1039952681294 ps
CPU time 422.71 seconds
Started Jun 04 12:24:08 PM PDT 24
Finished Jun 04 12:31:12 PM PDT 24
Peak memory 191008 kb
Host smart-64491f8b-0dce-49f1-9305-538fafefb994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703881643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
703881643
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1917139529
Short name T395
Test name
Test status
Simulation time 33002343511 ps
CPU time 43.13 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:24:57 PM PDT 24
Peak memory 183160 kb
Host smart-b8735a30-2e59-4276-97ab-c79073bc5653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917139529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1917139529
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3943655189
Short name T323
Test name
Test status
Simulation time 154688534195 ps
CPU time 62.33 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:25:13 PM PDT 24
Peak memory 190996 kb
Host smart-9cf8ec89-66a0-4056-930a-5704b1ba431a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943655189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3943655189
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1655230386
Short name T393
Test name
Test status
Simulation time 106597013 ps
CPU time 0.58 seconds
Started Jun 04 12:23:55 PM PDT 24
Finished Jun 04 12:23:57 PM PDT 24
Peak memory 182612 kb
Host smart-b78ea9e4-82bf-470e-a85b-bbc229168bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655230386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1655230386
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3916792821
Short name T447
Test name
Test status
Simulation time 394226769766 ps
CPU time 138.64 seconds
Started Jun 04 12:24:05 PM PDT 24
Finished Jun 04 12:26:25 PM PDT 24
Peak memory 182916 kb
Host smart-779e9a76-8112-4c2f-9e6c-f5430836aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916792821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3916792821
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2585725124
Short name T152
Test name
Test status
Simulation time 342370389788 ps
CPU time 301.98 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:29:13 PM PDT 24
Peak memory 190952 kb
Host smart-2a951dfe-6630-4133-9c2e-8155f93cc239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585725124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2585725124
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2380355490
Short name T125
Test name
Test status
Simulation time 128740306213 ps
CPU time 257.2 seconds
Started Jun 04 12:23:55 PM PDT 24
Finished Jun 04 12:28:14 PM PDT 24
Peak memory 182792 kb
Host smart-a29de5cd-5629-4603-97f2-890af16a1cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380355490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2380355490
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1411400489
Short name T390
Test name
Test status
Simulation time 921320615140 ps
CPU time 322 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:29:32 PM PDT 24
Peak memory 191000 kb
Host smart-bd3b63b5-ac4c-4de3-9b2a-e42716b2ea0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411400489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1411400489
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.568731608
Short name T295
Test name
Test status
Simulation time 16333216252 ps
CPU time 28.66 seconds
Started Jun 04 12:23:31 PM PDT 24
Finished Jun 04 12:24:03 PM PDT 24
Peak memory 181764 kb
Host smart-443cb6bc-7c0d-4fd2-81a2-c4df67533e8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568731608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.568731608
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.720944380
Short name T425
Test name
Test status
Simulation time 119312357504 ps
CPU time 97.76 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:25:40 PM PDT 24
Peak memory 182716 kb
Host smart-5741a701-ef7f-4461-91d4-9ec2f49830f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720944380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.720944380
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2980524075
Short name T206
Test name
Test status
Simulation time 149001565610 ps
CPU time 440.41 seconds
Started Jun 04 12:23:55 PM PDT 24
Finished Jun 04 12:31:17 PM PDT 24
Peak memory 190848 kb
Host smart-0195af27-f461-411f-93e6-a7d9758db05a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980524075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2980524075
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.4151324011
Short name T17
Test name
Test status
Simulation time 126184830 ps
CPU time 0.73 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:23:37 PM PDT 24
Peak memory 213136 kb
Host smart-5670e4f4-1a02-491f-be9c-e25a9eb993e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151324011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4151324011
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2344971363
Short name T49
Test name
Test status
Simulation time 84994069679 ps
CPU time 126.8 seconds
Started Jun 04 12:22:11 PM PDT 24
Finished Jun 04 12:24:19 PM PDT 24
Peak memory 182772 kb
Host smart-aaf710a0-4e84-486c-bfea-a276831c15c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344971363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2344971363
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1422703461
Short name T37
Test name
Test status
Simulation time 54904586160 ps
CPU time 383.9 seconds
Started Jun 04 12:23:33 PM PDT 24
Finished Jun 04 12:30:00 PM PDT 24
Peak memory 197448 kb
Host smart-59d1d8ba-c6b2-4cea-a41a-ecc1841ff314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422703461 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1422703461
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3473176412
Short name T363
Test name
Test status
Simulation time 500949584657 ps
CPU time 761.3 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:36:54 PM PDT 24
Peak memory 182796 kb
Host smart-a6e8007a-9d98-432a-ad3d-56ebb17cf0bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473176412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3473176412
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.872511180
Short name T452
Test name
Test status
Simulation time 269511877835 ps
CPU time 197.74 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:27:29 PM PDT 24
Peak memory 182436 kb
Host smart-88cc8074-3029-48ea-8df8-1549390fb6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872511180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.872511180
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2724542997
Short name T336
Test name
Test status
Simulation time 531525207728 ps
CPU time 1124.41 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:42:55 PM PDT 24
Peak memory 190996 kb
Host smart-a298e09d-87f0-4393-ba70-243697113fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724542997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2724542997
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2185534962
Short name T413
Test name
Test status
Simulation time 140404874 ps
CPU time 0.62 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:24:15 PM PDT 24
Peak memory 182588 kb
Host smart-ab0e0637-f1bf-4e4a-8c32-a18622d425ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185534962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2185534962
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1474030032
Short name T446
Test name
Test status
Simulation time 64645314 ps
CPU time 0.51 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:24:13 PM PDT 24
Peak memory 182116 kb
Host smart-3f731148-8b80-4990-90e7-5243d4fd1105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474030032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1474030032
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.633965543
Short name T391
Test name
Test status
Simulation time 83128449503 ps
CPU time 130.37 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:26:20 PM PDT 24
Peak memory 182788 kb
Host smart-a8f40117-4f3f-4e4e-b5ff-b1608ed15d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633965543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.633965543
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3582811825
Short name T20
Test name
Test status
Simulation time 19096479669 ps
CPU time 28.93 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:24:41 PM PDT 24
Peak memory 194408 kb
Host smart-d28d3649-99b4-4bbe-adbd-91409d561c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582811825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3582811825
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.40402
Short name T34
Test name
Test status
Simulation time 45804224703 ps
CPU time 135.17 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 197436 kb
Host smart-9b4f42bb-b9bb-47cb-8a68-f959c8ada6eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40402 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.40402
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2460873077
Short name T320
Test name
Test status
Simulation time 120558551691 ps
CPU time 214.28 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:27:47 PM PDT 24
Peak memory 182796 kb
Host smart-e22264c6-8f8c-4d84-993e-f4cf030642ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460873077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2460873077
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2883815244
Short name T400
Test name
Test status
Simulation time 128595185662 ps
CPU time 199.72 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:27:31 PM PDT 24
Peak memory 182812 kb
Host smart-f922c12d-d005-4510-b31f-cc44d35ef778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883815244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2883815244
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3792708494
Short name T93
Test name
Test status
Simulation time 63209294558 ps
CPU time 1499.07 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:49:11 PM PDT 24
Peak memory 182756 kb
Host smart-394817a2-0d3a-4dad-8944-77ccf74eabfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792708494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3792708494
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.89053802
Short name T112
Test name
Test status
Simulation time 261771033279 ps
CPU time 454.11 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:31:47 PM PDT 24
Peak memory 182776 kb
Host smart-fec925df-cda1-4e66-8739-b0ed58ed715d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89053802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.rv_timer_cfg_update_on_fly.89053802
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1058293951
Short name T410
Test name
Test status
Simulation time 130486369561 ps
CPU time 185.21 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:27:17 PM PDT 24
Peak memory 182792 kb
Host smart-065999f0-b5f5-4a64-9bdf-59b8bfff251a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058293951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1058293951
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2428453619
Short name T220
Test name
Test status
Simulation time 153600813350 ps
CPU time 699.39 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:35:51 PM PDT 24
Peak memory 190944 kb
Host smart-21bc667f-4734-424d-b548-3f49ff9a1cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428453619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2428453619
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1009765914
Short name T305
Test name
Test status
Simulation time 329026667537 ps
CPU time 285.86 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:28:56 PM PDT 24
Peak memory 191016 kb
Host smart-1b2d6e9f-7ef9-4c42-9b8a-46721ca29832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009765914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1009765914
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.4028048362
Short name T278
Test name
Test status
Simulation time 279232217735 ps
CPU time 529.44 seconds
Started Jun 04 12:24:07 PM PDT 24
Finished Jun 04 12:32:58 PM PDT 24
Peak memory 182824 kb
Host smart-10548d5f-8b9e-44c5-b2a1-cc3d13a3c716
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028048362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.4028048362
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3446100537
Short name T445
Test name
Test status
Simulation time 61536810484 ps
CPU time 45.33 seconds
Started Jun 04 12:24:07 PM PDT 24
Finished Jun 04 12:24:54 PM PDT 24
Peak memory 182816 kb
Host smart-4152ad43-e7dc-4fef-bacf-74c8f01c7444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446100537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3446100537
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3271151500
Short name T235
Test name
Test status
Simulation time 65239998408 ps
CPU time 311.73 seconds
Started Jun 04 12:24:04 PM PDT 24
Finished Jun 04 12:29:17 PM PDT 24
Peak memory 191048 kb
Host smart-ac9e05f0-ca5e-4450-9a9c-80b7dec90b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271151500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3271151500
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.615295011
Short name T155
Test name
Test status
Simulation time 36290391909 ps
CPU time 46.7 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:25:01 PM PDT 24
Peak memory 182772 kb
Host smart-7d45d116-6e14-4341-b195-33d1a73ca653
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615295011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.615295011
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.988958900
Short name T27
Test name
Test status
Simulation time 12438838212 ps
CPU time 9.76 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 12:24:24 PM PDT 24
Peak memory 182776 kb
Host smart-60fb532a-946c-4b53-88ec-7d87aca47ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988958900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.988958900
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.972697688
Short name T132
Test name
Test status
Simulation time 163517609135 ps
CPU time 341.73 seconds
Started Jun 04 12:24:16 PM PDT 24
Finished Jun 04 12:29:59 PM PDT 24
Peak memory 191116 kb
Host smart-73f3e04a-a190-4b5d-9b7f-83a512177f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972697688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.972697688
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4150842897
Short name T454
Test name
Test status
Simulation time 29684588729 ps
CPU time 54.87 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:25:09 PM PDT 24
Peak memory 194708 kb
Host smart-a4e6ec2f-4b38-4c14-8fdc-9e84a0a554c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150842897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4150842897
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2829347218
Short name T429
Test name
Test status
Simulation time 1040976824521 ps
CPU time 409.55 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:31:05 PM PDT 24
Peak memory 194376 kb
Host smart-99de758d-11fe-41cd-b8f2-5e03acefecd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829347218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2829347218
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.915518119
Short name T163
Test name
Test status
Simulation time 74868708975 ps
CPU time 115.39 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 12:26:10 PM PDT 24
Peak memory 182772 kb
Host smart-66a6f863-4cb5-4226-a321-ee542f823131
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915518119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.915518119
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.227166412
Short name T427
Test name
Test status
Simulation time 248075319969 ps
CPU time 100.83 seconds
Started Jun 04 12:24:10 PM PDT 24
Finished Jun 04 12:25:52 PM PDT 24
Peak memory 182812 kb
Host smart-dbad008c-1eb2-41ea-80e4-2ddfd1b5ff99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227166412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.227166412
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2256526218
Short name T156
Test name
Test status
Simulation time 225683481341 ps
CPU time 448.53 seconds
Started Jun 04 12:24:04 PM PDT 24
Finished Jun 04 12:31:34 PM PDT 24
Peak memory 182848 kb
Host smart-150d13a5-d2c3-466e-bdc3-447e4b8367c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256526218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2256526218
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2602759209
Short name T144
Test name
Test status
Simulation time 63919398427 ps
CPU time 57.97 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:25:01 PM PDT 24
Peak memory 182776 kb
Host smart-e8c509ed-cc95-4fee-a6f9-9c66f7c63440
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602759209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2602759209
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1455392859
Short name T377
Test name
Test status
Simulation time 44611182230 ps
CPU time 74.62 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:25:30 PM PDT 24
Peak memory 182776 kb
Host smart-ddbf1dfa-c76c-4dd9-8c10-4438e6066fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455392859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1455392859
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2497037685
Short name T136
Test name
Test status
Simulation time 752775918998 ps
CPU time 150.33 seconds
Started Jun 04 12:24:15 PM PDT 24
Finished Jun 04 12:26:47 PM PDT 24
Peak memory 190120 kb
Host smart-9606d7a6-3796-4ef2-99ab-63422dc9cfeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497037685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2497037685
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1649329091
Short name T321
Test name
Test status
Simulation time 200814864827 ps
CPU time 146.99 seconds
Started Jun 04 12:24:15 PM PDT 24
Finished Jun 04 12:26:43 PM PDT 24
Peak memory 195204 kb
Host smart-86a37a72-e9b0-4e6d-af6c-4d52f5669402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649329091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1649329091
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3690653449
Short name T369
Test name
Test status
Simulation time 243781890592 ps
CPU time 403.31 seconds
Started Jun 04 12:24:08 PM PDT 24
Finished Jun 04 12:30:53 PM PDT 24
Peak memory 191004 kb
Host smart-b35f5e4c-a584-49d9-898c-49ad48b2da17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690653449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3690653449
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2876256158
Short name T415
Test name
Test status
Simulation time 135500256284 ps
CPU time 234.05 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:28:09 PM PDT 24
Peak memory 182832 kb
Host smart-a492261b-9316-4d6a-ab27-5c3a19059869
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876256158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2876256158
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3406927563
Short name T26
Test name
Test status
Simulation time 163802867638 ps
CPU time 67.36 seconds
Started Jun 04 12:24:04 PM PDT 24
Finished Jun 04 12:25:13 PM PDT 24
Peak memory 182808 kb
Host smart-02c2f809-0d78-4f1c-93b5-9c38e317bd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406927563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3406927563
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2443990531
Short name T272
Test name
Test status
Simulation time 178821065527 ps
CPU time 144.11 seconds
Started Jun 04 12:24:03 PM PDT 24
Finished Jun 04 12:26:29 PM PDT 24
Peak memory 191128 kb
Host smart-eb22a296-f367-44d2-bdbe-8553b987ef61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443990531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2443990531
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2104074937
Short name T191
Test name
Test status
Simulation time 132559329792 ps
CPU time 203.27 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:27:42 PM PDT 24
Peak memory 182768 kb
Host smart-110cbd1a-bbc3-4879-b656-6c7724e9d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104074937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2104074937
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.4058675561
Short name T431
Test name
Test status
Simulation time 238504345243 ps
CPU time 122.59 seconds
Started Jun 04 12:24:03 PM PDT 24
Finished Jun 04 12:26:07 PM PDT 24
Peak memory 182940 kb
Host smart-80bc7d44-be5a-4652-8554-4b4e03f796aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058675561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.4058675561
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.262334028
Short name T407
Test name
Test status
Simulation time 133388112 ps
CPU time 0.94 seconds
Started Jun 04 12:24:18 PM PDT 24
Finished Jun 04 12:24:21 PM PDT 24
Peak memory 191236 kb
Host smart-17ab9848-61ac-46d6-b9fc-d47f8b91721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262334028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.262334028
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3592345845
Short name T381
Test name
Test status
Simulation time 418756916388 ps
CPU time 165.88 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:27:02 PM PDT 24
Peak memory 182816 kb
Host smart-650e8418-fd77-43ed-8d79-3735d4bbcb03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592345845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3592345845
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1210624095
Short name T138
Test name
Test status
Simulation time 237025179536 ps
CPU time 132.67 seconds
Started Jun 04 12:22:23 PM PDT 24
Finished Jun 04 12:24:36 PM PDT 24
Peak memory 182764 kb
Host smart-2218e868-4326-4fe3-8de8-f45ce812f093
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210624095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1210624095
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.4242074514
Short name T7
Test name
Test status
Simulation time 298569003551 ps
CPU time 46.93 seconds
Started Jun 04 12:23:34 PM PDT 24
Finished Jun 04 12:24:23 PM PDT 24
Peak memory 182900 kb
Host smart-e5229f37-ad8c-4b64-a0af-4200d014d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242074514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.4242074514
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3487690310
Short name T51
Test name
Test status
Simulation time 554735248879 ps
CPU time 732.41 seconds
Started Jun 04 12:22:14 PM PDT 24
Finished Jun 04 12:34:27 PM PDT 24
Peak memory 194584 kb
Host smart-ca6050e5-a48d-4b11-8c36-17736d5c74b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487690310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3487690310
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3371922122
Short name T351
Test name
Test status
Simulation time 298141730055 ps
CPU time 1737.17 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:52:52 PM PDT 24
Peak memory 182428 kb
Host smart-47976a46-6a03-4e01-a306-fa0754090711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371922122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3371922122
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3134708672
Short name T16
Test name
Test status
Simulation time 124208191 ps
CPU time 0.72 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:24:19 PM PDT 24
Peak memory 213816 kb
Host smart-cf5413ef-62b4-4870-ae55-b71998d9e0dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134708672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3134708672
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.511173909
Short name T223
Test name
Test status
Simulation time 201558903647 ps
CPU time 443.91 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:31:27 PM PDT 24
Peak memory 190276 kb
Host smart-184560b2-84fe-497d-8579-a64414dbb401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511173909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.511173909
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.4238063741
Short name T36
Test name
Test status
Simulation time 19976530816 ps
CPU time 205.94 seconds
Started Jun 04 12:22:23 PM PDT 24
Finished Jun 04 12:25:50 PM PDT 24
Peak memory 197388 kb
Host smart-90f63dcf-eb3e-455d-b0d0-0c62ab4f814a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238063741 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.4238063741
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.657982090
Short name T219
Test name
Test status
Simulation time 9196012947 ps
CPU time 14.79 seconds
Started Jun 04 12:24:05 PM PDT 24
Finished Jun 04 12:24:22 PM PDT 24
Peak memory 182780 kb
Host smart-c6cfd1c6-e0bc-4eec-8455-55354fff0470
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657982090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.657982090
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1379947075
Short name T392
Test name
Test status
Simulation time 58412201394 ps
CPU time 74.81 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:25:33 PM PDT 24
Peak memory 182792 kb
Host smart-6fb98cf7-8cd7-4a76-b7ea-9f80e8640dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379947075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1379947075
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.55115954
Short name T375
Test name
Test status
Simulation time 621455880 ps
CPU time 1.19 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:24:17 PM PDT 24
Peak memory 182740 kb
Host smart-88738b07-04c2-4a1e-b2d5-3002e967a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55115954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.55115954
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3815565219
Short name T97
Test name
Test status
Simulation time 363850978167 ps
CPU time 164.09 seconds
Started Jun 04 12:24:15 PM PDT 24
Finished Jun 04 12:27:00 PM PDT 24
Peak memory 191008 kb
Host smart-476602da-fde7-44e2-8f8b-3d8b46c395cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815565219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3815565219
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2798553552
Short name T370
Test name
Test status
Simulation time 147134243745 ps
CPU time 262.35 seconds
Started Jun 04 12:24:20 PM PDT 24
Finished Jun 04 12:28:45 PM PDT 24
Peak memory 182716 kb
Host smart-1eac78e8-351e-446a-b782-ed1af9a6d6aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798553552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2798553552
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3238216856
Short name T421
Test name
Test status
Simulation time 80417650179 ps
CPU time 61.71 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:25:14 PM PDT 24
Peak memory 182764 kb
Host smart-cabd0c45-d8e6-4d00-8779-18fa18a4afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238216856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3238216856
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2000154690
Short name T360
Test name
Test status
Simulation time 23323476444 ps
CPU time 37.86 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:24:55 PM PDT 24
Peak memory 182760 kb
Host smart-7934e367-ba10-414e-9cae-a1b002712f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000154690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2000154690
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.4234594516
Short name T408
Test name
Test status
Simulation time 100851066861 ps
CPU time 52.83 seconds
Started Jun 04 12:24:22 PM PDT 24
Finished Jun 04 12:25:16 PM PDT 24
Peak memory 182808 kb
Host smart-b30a6eca-625d-48f7-97e3-67c40a393006
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234594516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.4234594516
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.413972651
Short name T428
Test name
Test status
Simulation time 119904797405 ps
CPU time 166.11 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:27:01 PM PDT 24
Peak memory 182824 kb
Host smart-07fc6c4e-66dc-4c47-b689-b87b47561f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413972651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.413972651
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3109352682
Short name T193
Test name
Test status
Simulation time 223843091744 ps
CPU time 1052.26 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:41:51 PM PDT 24
Peak memory 182644 kb
Host smart-7a1d94a3-37a2-4361-92da-73dd5385130f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109352682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3109352682
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1593134999
Short name T259
Test name
Test status
Simulation time 103809482690 ps
CPU time 163.1 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:26:56 PM PDT 24
Peak memory 193020 kb
Host smart-a46015b3-f180-41cb-bc24-a594989cff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593134999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1593134999
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.786494242
Short name T39
Test name
Test status
Simulation time 24842655638 ps
CPU time 184.49 seconds
Started Jun 04 12:24:22 PM PDT 24
Finished Jun 04 12:27:28 PM PDT 24
Peak memory 197464 kb
Host smart-d201fd24-39fe-499c-a8d8-7fdc664c9e47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786494242 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.786494242
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3113414725
Short name T436
Test name
Test status
Simulation time 44974903494 ps
CPU time 15.69 seconds
Started Jun 04 12:24:16 PM PDT 24
Finished Jun 04 12:24:32 PM PDT 24
Peak memory 182772 kb
Host smart-087727fc-28bc-4e1f-911c-21b78e948215
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113414725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3113414725
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3593177269
Short name T382
Test name
Test status
Simulation time 38427219927 ps
CPU time 59.19 seconds
Started Jun 04 12:24:15 PM PDT 24
Finished Jun 04 12:25:15 PM PDT 24
Peak memory 182808 kb
Host smart-2805ea94-e588-45ac-ba6a-910adf6aa58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593177269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3593177269
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3700313576
Short name T23
Test name
Test status
Simulation time 808788461 ps
CPU time 2.88 seconds
Started Jun 04 12:24:09 PM PDT 24
Finished Jun 04 12:24:14 PM PDT 24
Peak memory 182720 kb
Host smart-deac2225-7c0d-45cf-86d9-07eb1541cf4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700313576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3700313576
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1417601364
Short name T442
Test name
Test status
Simulation time 63648352278 ps
CPU time 47.63 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:25:06 PM PDT 24
Peak memory 190864 kb
Host smart-0092734c-3c71-44b6-8316-aab0b6dfba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417601364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1417601364
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.103052745
Short name T62
Test name
Test status
Simulation time 2043871257370 ps
CPU time 1348.98 seconds
Started Jun 04 12:24:14 PM PDT 24
Finished Jun 04 12:46:44 PM PDT 24
Peak memory 190976 kb
Host smart-bf2b2eaa-e81f-4a33-a3d7-51f966f06925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103052745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
103052745
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2092316902
Short name T383
Test name
Test status
Simulation time 83975414690 ps
CPU time 130.15 seconds
Started Jun 04 12:24:18 PM PDT 24
Finished Jun 04 12:26:30 PM PDT 24
Peak memory 182792 kb
Host smart-2c218f33-0011-4440-9a17-cc62e6b4e61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092316902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2092316902
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.542861213
Short name T328
Test name
Test status
Simulation time 307645288839 ps
CPU time 1293.99 seconds
Started Jun 04 12:24:04 PM PDT 24
Finished Jun 04 12:45:40 PM PDT 24
Peak memory 191000 kb
Host smart-f86f14fa-47f6-44bd-861c-ecbcd646e147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542861213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.542861213
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.4280415920
Short name T140
Test name
Test status
Simulation time 37223916100 ps
CPU time 19.63 seconds
Started Jun 04 12:24:12 PM PDT 24
Finished Jun 04 12:24:33 PM PDT 24
Peak memory 193972 kb
Host smart-8735a53e-9842-47bd-8f91-1b0c40985a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280415920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4280415920
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.458054803
Short name T189
Test name
Test status
Simulation time 788747706416 ps
CPU time 474.79 seconds
Started Jun 04 12:24:18 PM PDT 24
Finished Jun 04 12:32:15 PM PDT 24
Peak memory 195328 kb
Host smart-573f3a2b-57c9-4dc1-a47e-b1696a27dc3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458054803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
458054803
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4185829828
Short name T198
Test name
Test status
Simulation time 45228803240 ps
CPU time 73.97 seconds
Started Jun 04 12:24:15 PM PDT 24
Finished Jun 04 12:25:30 PM PDT 24
Peak memory 182120 kb
Host smart-67967954-1f9f-474a-ba0d-8c726b7f0d95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185829828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4185829828
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2041718133
Short name T386
Test name
Test status
Simulation time 868665662871 ps
CPU time 372.02 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:30:47 PM PDT 24
Peak memory 182732 kb
Host smart-bb218991-b289-4db0-93d1-7badb6a2f44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041718133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2041718133
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.984562340
Short name T194
Test name
Test status
Simulation time 61816337236 ps
CPU time 244.13 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:28:22 PM PDT 24
Peak memory 193100 kb
Host smart-4c06596d-947a-4d99-837c-f9bdbcbc219b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984562340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.984562340
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3080919333
Short name T424
Test name
Test status
Simulation time 115484207 ps
CPU time 0.7 seconds
Started Jun 04 12:24:17 PM PDT 24
Finished Jun 04 12:24:20 PM PDT 24
Peak memory 182568 kb
Host smart-69b38789-e04c-4e9f-975f-d5f8fe5e62a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080919333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3080919333
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.204343979
Short name T368
Test name
Test status
Simulation time 387714933423 ps
CPU time 586.35 seconds
Started Jun 04 12:24:18 PM PDT 24
Finished Jun 04 12:34:07 PM PDT 24
Peak memory 190964 kb
Host smart-721850c8-455f-455f-a824-53d2688463e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204343979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
204343979
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.3440403296
Short name T352
Test name
Test status
Simulation time 76725375220 ps
CPU time 309.06 seconds
Started Jun 04 12:24:19 PM PDT 24
Finished Jun 04 12:29:30 PM PDT 24
Peak memory 197384 kb
Host smart-e8078529-7574-4bf4-a5ef-8f12c5a5119c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440403296 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.3440403296
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.998934354
Short name T237
Test name
Test status
Simulation time 237298469777 ps
CPU time 394.3 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:31:13 PM PDT 24
Peak memory 182720 kb
Host smart-c662b489-4f12-4b46-a3fc-1f7ca875f7fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998934354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.998934354
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.579044092
Short name T379
Test name
Test status
Simulation time 124294744959 ps
CPU time 34.35 seconds
Started Jun 04 12:24:46 PM PDT 24
Finished Jun 04 12:25:22 PM PDT 24
Peak memory 182732 kb
Host smart-3596badb-96fa-4fae-a4b0-56c93275097b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579044092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.579044092
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.19320244
Short name T207
Test name
Test status
Simulation time 151012783776 ps
CPU time 142.28 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:27:04 PM PDT 24
Peak memory 190852 kb
Host smart-145713bb-a7c3-43e1-a9bf-36cc19fd8eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19320244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.19320244
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.202056446
Short name T282
Test name
Test status
Simulation time 38599735042 ps
CPU time 102.87 seconds
Started Jun 04 12:24:25 PM PDT 24
Finished Jun 04 12:26:11 PM PDT 24
Peak memory 182720 kb
Host smart-462d7c33-62a2-49a1-a297-2a7296c56b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202056446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.202056446
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4118621891
Short name T315
Test name
Test status
Simulation time 212747205999 ps
CPU time 341.09 seconds
Started Jun 04 12:24:20 PM PDT 24
Finished Jun 04 12:30:03 PM PDT 24
Peak memory 190968 kb
Host smart-8305e63d-3c2d-497c-9f94-bd179f153a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118621891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4118621891
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2285857267
Short name T35
Test name
Test status
Simulation time 22005891913 ps
CPU time 160.68 seconds
Started Jun 04 12:24:21 PM PDT 24
Finished Jun 04 12:27:03 PM PDT 24
Peak memory 197372 kb
Host smart-cf846ad1-99d2-4e00-bd4a-8f11d22e7817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285857267 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2285857267
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1151356233
Short name T309
Test name
Test status
Simulation time 71241977814 ps
CPU time 111.23 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:26:26 PM PDT 24
Peak memory 182740 kb
Host smart-4a3ce429-1190-4ed0-97ae-ea01ac7e7e91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151356233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1151356233
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.510270946
Short name T439
Test name
Test status
Simulation time 1569163911 ps
CPU time 2.88 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:24:40 PM PDT 24
Peak memory 182596 kb
Host smart-c96fd62b-16e8-4124-b478-10a0223b2508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510270946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.510270946
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1862938010
Short name T19
Test name
Test status
Simulation time 248383353 ps
CPU time 0.6 seconds
Started Jun 04 12:24:20 PM PDT 24
Finished Jun 04 12:24:22 PM PDT 24
Peak memory 182548 kb
Host smart-ce5edcff-18ce-4731-9815-104b0dc0327d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862938010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1862938010
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2827588777
Short name T416
Test name
Test status
Simulation time 72849571394 ps
CPU time 128.57 seconds
Started Jun 04 12:24:40 PM PDT 24
Finished Jun 04 12:26:52 PM PDT 24
Peak memory 182820 kb
Host smart-79b23e10-ab44-474a-88e0-0ece3ba3ffd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827588777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2827588777
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2808643861
Short name T66
Test name
Test status
Simulation time 190109589388 ps
CPU time 74.72 seconds
Started Jun 04 12:24:22 PM PDT 24
Finished Jun 04 12:25:38 PM PDT 24
Peak memory 182796 kb
Host smart-2e2a0fa8-30ba-4da8-b181-3b5e737027c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808643861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2808643861
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2806246077
Short name T42
Test name
Test status
Simulation time 43533470713 ps
CPU time 61.24 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:25:38 PM PDT 24
Peak memory 182720 kb
Host smart-3b0d373a-22fa-4e17-87a5-f94dd35c4c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806246077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2806246077
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3056165450
Short name T261
Test name
Test status
Simulation time 319335479825 ps
CPU time 181.49 seconds
Started Jun 04 12:24:32 PM PDT 24
Finished Jun 04 12:27:34 PM PDT 24
Peak memory 182812 kb
Host smart-06a2370f-d223-4d43-b306-e6b39b4d58f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056165450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3056165450
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2883784727
Short name T401
Test name
Test status
Simulation time 227082855763 ps
CPU time 102.63 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:26:18 PM PDT 24
Peak memory 182804 kb
Host smart-304f26fb-7722-47f9-b051-8b7e701d4806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883784727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2883784727
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2281764706
Short name T355
Test name
Test status
Simulation time 68943052840 ps
CPU time 109.18 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:26:24 PM PDT 24
Peak memory 182792 kb
Host smart-da8ef896-ab49-4305-ad23-13ce2d864f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281764706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2281764706
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1487620515
Short name T255
Test name
Test status
Simulation time 49561347374 ps
CPU time 106.9 seconds
Started Jun 04 12:24:19 PM PDT 24
Finished Jun 04 12:26:09 PM PDT 24
Peak memory 190972 kb
Host smart-f7e9f46e-6e1d-4bd4-a706-f4005914a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487620515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1487620515
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2032447672
Short name T343
Test name
Test status
Simulation time 10510398146 ps
CPU time 5.8 seconds
Started Jun 04 12:24:01 PM PDT 24
Finished Jun 04 12:24:09 PM PDT 24
Peak memory 182224 kb
Host smart-d2ebb120-af3b-46d3-8b34-f6a53c87c5b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032447672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2032447672
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2835555495
Short name T378
Test name
Test status
Simulation time 111992062788 ps
CPU time 165.76 seconds
Started Jun 04 12:22:23 PM PDT 24
Finished Jun 04 12:25:09 PM PDT 24
Peak memory 182780 kb
Host smart-e9cd3740-c90e-4b45-82d6-164664d28d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835555495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2835555495
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2126024379
Short name T92
Test name
Test status
Simulation time 102235822914 ps
CPU time 613.16 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:34:08 PM PDT 24
Peak memory 189548 kb
Host smart-e991e9b9-be34-4813-b03d-80e07c76ae3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126024379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2126024379
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3502685616
Short name T389
Test name
Test status
Simulation time 28599999 ps
CPU time 0.54 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:23:55 PM PDT 24
Peak memory 182204 kb
Host smart-75dd2e19-4586-4aef-a65f-15baca8078ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502685616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3502685616
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2126103416
Short name T230
Test name
Test status
Simulation time 65036276951 ps
CPU time 111.2 seconds
Started Jun 04 12:24:04 PM PDT 24
Finished Jun 04 12:25:57 PM PDT 24
Peak memory 194540 kb
Host smart-877cc1ef-41cc-48ec-abd0-e8cd4655990a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126103416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2126103416
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.11635625
Short name T453
Test name
Test status
Simulation time 321620859622 ps
CPU time 1406.32 seconds
Started Jun 04 12:24:19 PM PDT 24
Finished Jun 04 12:47:47 PM PDT 24
Peak memory 190948 kb
Host smart-d9d84ad3-ab8b-4050-b6a7-c7c0b144b864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11635625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.11635625
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3782844120
Short name T337
Test name
Test status
Simulation time 442978702056 ps
CPU time 299.06 seconds
Started Jun 04 12:24:11 PM PDT 24
Finished Jun 04 12:29:12 PM PDT 24
Peak memory 190920 kb
Host smart-b26fcbfc-90ac-4015-a2dd-144564f520d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782844120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3782844120
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1389335491
Short name T124
Test name
Test status
Simulation time 100158141904 ps
CPU time 171.71 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:27:34 PM PDT 24
Peak memory 190992 kb
Host smart-1cac3731-c7e3-4b32-a57c-3b54bc6a79c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389335491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1389335491
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.246007323
Short name T196
Test name
Test status
Simulation time 18181505466 ps
CPU time 27.14 seconds
Started Jun 04 12:24:31 PM PDT 24
Finished Jun 04 12:24:59 PM PDT 24
Peak memory 182788 kb
Host smart-d9a1d391-682e-447a-9f4c-19159ede06c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246007323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.246007323
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2993358549
Short name T250
Test name
Test status
Simulation time 117622047167 ps
CPU time 63.47 seconds
Started Jun 04 12:24:43 PM PDT 24
Finished Jun 04 12:25:49 PM PDT 24
Peak memory 192872 kb
Host smart-a91fbc85-4c24-47ce-bb49-3cdbde6709e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993358549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2993358549
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3444642427
Short name T143
Test name
Test status
Simulation time 241741397328 ps
CPU time 868.74 seconds
Started Jun 04 12:24:19 PM PDT 24
Finished Jun 04 12:38:50 PM PDT 24
Peak memory 190972 kb
Host smart-8e77f1f5-e7fc-4417-9baa-da7a4573c099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444642427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3444642427
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3866902239
Short name T263
Test name
Test status
Simulation time 96220719348 ps
CPU time 458.73 seconds
Started Jun 04 12:24:42 PM PDT 24
Finished Jun 04 12:32:23 PM PDT 24
Peak memory 190952 kb
Host smart-ae40c3fc-9dde-4f95-a598-90c4466d8df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866902239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3866902239
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1013794093
Short name T268
Test name
Test status
Simulation time 4978304209597 ps
CPU time 1088.2 seconds
Started Jun 04 12:22:22 PM PDT 24
Finished Jun 04 12:40:31 PM PDT 24
Peak memory 182784 kb
Host smart-556ac168-6999-4e30-859b-df9e36157bd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013794093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1013794093
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2046421868
Short name T380
Test name
Test status
Simulation time 290301370258 ps
CPU time 83.84 seconds
Started Jun 04 12:22:25 PM PDT 24
Finished Jun 04 12:23:49 PM PDT 24
Peak memory 182816 kb
Host smart-595503c3-46b7-4dd2-b30b-0de5f58c5d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046421868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2046421868
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2899743495
Short name T145
Test name
Test status
Simulation time 634576147581 ps
CPU time 407.55 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:30:42 PM PDT 24
Peak memory 190644 kb
Host smart-78d085a7-a192-4c1a-b081-947794b414a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899743495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2899743495
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.459991715
Short name T94
Test name
Test status
Simulation time 1449704742 ps
CPU time 1.15 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:23:56 PM PDT 24
Peak memory 180960 kb
Host smart-c5f6fa2d-ccc3-4c62-b7aa-869f3c03a70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459991715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.459991715
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3014582253
Short name T60
Test name
Test status
Simulation time 833793185385 ps
CPU time 550.36 seconds
Started Jun 04 12:24:08 PM PDT 24
Finished Jun 04 12:33:19 PM PDT 24
Peak memory 190996 kb
Host smart-02a5a111-3883-4de6-8b2b-2eb8d8f604cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014582253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3014582253
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2616722480
Short name T21
Test name
Test status
Simulation time 47051370028 ps
CPU time 71.28 seconds
Started Jun 04 12:24:19 PM PDT 24
Finished Jun 04 12:25:32 PM PDT 24
Peak memory 182776 kb
Host smart-6f9d1f3f-f903-460c-8b09-988a53fb2cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616722480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2616722480
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1815358979
Short name T275
Test name
Test status
Simulation time 74272766291 ps
CPU time 1270.21 seconds
Started Jun 04 12:24:27 PM PDT 24
Finished Jun 04 12:45:39 PM PDT 24
Peak memory 190924 kb
Host smart-eb2dd467-848a-4cb9-95e6-8228d5af21f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815358979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1815358979
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.836973511
Short name T252
Test name
Test status
Simulation time 38629849983 ps
CPU time 58.4 seconds
Started Jun 04 12:24:28 PM PDT 24
Finished Jun 04 12:25:28 PM PDT 24
Peak memory 190984 kb
Host smart-8b8dd6e6-d98a-4027-bef8-b2c2e1ecf298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836973511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.836973511
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2144214548
Short name T371
Test name
Test status
Simulation time 107983126311 ps
CPU time 157.99 seconds
Started Jun 04 12:24:25 PM PDT 24
Finished Jun 04 12:27:05 PM PDT 24
Peak memory 190996 kb
Host smart-abc14862-9abf-4dcd-b0b8-932fb4fde323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144214548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2144214548
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3548542174
Short name T345
Test name
Test status
Simulation time 103306123776 ps
CPU time 194.34 seconds
Started Jun 04 12:24:37 PM PDT 24
Finished Jun 04 12:27:55 PM PDT 24
Peak memory 191000 kb
Host smart-f127cb71-b2f4-4dcd-a7f7-519066de2131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548542174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3548542174
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.823709220
Short name T254
Test name
Test status
Simulation time 542795215922 ps
CPU time 388.45 seconds
Started Jun 04 12:24:31 PM PDT 24
Finished Jun 04 12:31:01 PM PDT 24
Peak memory 194496 kb
Host smart-29f502da-3e60-43f1-91b4-ab78aad6fd9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823709220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.823709220
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.4056092728
Short name T274
Test name
Test status
Simulation time 243421719205 ps
CPU time 130.07 seconds
Started Jun 04 12:24:27 PM PDT 24
Finished Jun 04 12:26:39 PM PDT 24
Peak memory 190928 kb
Host smart-7f174ac7-e873-4c0f-9b5e-b4a8121e0049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056092728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4056092728
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.114918676
Short name T161
Test name
Test status
Simulation time 1466519003660 ps
CPU time 1079.9 seconds
Started Jun 04 12:24:32 PM PDT 24
Finished Jun 04 12:42:33 PM PDT 24
Peak memory 190980 kb
Host smart-e0623e86-bea7-4529-a4ed-d14109e4a418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114918676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.114918676
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.33373615
Short name T437
Test name
Test status
Simulation time 748130819865 ps
CPU time 419.31 seconds
Started Jun 04 12:22:33 PM PDT 24
Finished Jun 04 12:29:33 PM PDT 24
Peak memory 182936 kb
Host smart-bbc9592e-2f57-4eac-af70-4f5f1c0340b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33373615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
rv_timer_cfg_update_on_fly.33373615
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1927321935
Short name T430
Test name
Test status
Simulation time 43009181366 ps
CPU time 65.29 seconds
Started Jun 04 12:22:40 PM PDT 24
Finished Jun 04 12:23:47 PM PDT 24
Peak memory 182848 kb
Host smart-06b55e57-5556-406e-82ea-8b3ca8b14280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927321935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1927321935
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1607998863
Short name T265
Test name
Test status
Simulation time 42054011266 ps
CPU time 98.38 seconds
Started Jun 04 12:22:29 PM PDT 24
Finished Jun 04 12:24:08 PM PDT 24
Peak memory 191000 kb
Host smart-b77475b3-2b01-4ed9-80dc-a59ca9b85ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607998863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1607998863
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3841991353
Short name T450
Test name
Test status
Simulation time 23047661 ps
CPU time 0.67 seconds
Started Jun 04 12:22:41 PM PDT 24
Finished Jun 04 12:22:43 PM PDT 24
Peak memory 182632 kb
Host smart-83cecabd-f10e-4020-b9ec-0bc8d4890186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841991353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3841991353
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.4194670092
Short name T418
Test name
Test status
Simulation time 34701545227 ps
CPU time 53.54 seconds
Started Jun 04 12:22:33 PM PDT 24
Finished Jun 04 12:23:28 PM PDT 24
Peak memory 182948 kb
Host smart-1aaf3498-ed27-4604-a59f-003e4a5bfa50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194670092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
4194670092
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.705332969
Short name T329
Test name
Test status
Simulation time 237014605630 ps
CPU time 281.83 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:29:19 PM PDT 24
Peak memory 190940 kb
Host smart-d98dfa09-042d-4c56-839a-e43e233e00ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705332969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.705332969
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1492301079
Short name T168
Test name
Test status
Simulation time 280110406062 ps
CPU time 399.82 seconds
Started Jun 04 12:24:28 PM PDT 24
Finished Jun 04 12:31:09 PM PDT 24
Peak memory 190996 kb
Host smart-aae9b064-ff3f-41da-a406-4bb88442297e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492301079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1492301079
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3537803592
Short name T114
Test name
Test status
Simulation time 109823567107 ps
CPU time 214.47 seconds
Started Jun 04 12:24:26 PM PDT 24
Finished Jun 04 12:28:03 PM PDT 24
Peak memory 190920 kb
Host smart-60b6282e-f5f1-4fa6-a6f2-71c36af83ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537803592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3537803592
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2081663429
Short name T232
Test name
Test status
Simulation time 395176407979 ps
CPU time 274.14 seconds
Started Jun 04 12:24:27 PM PDT 24
Finished Jun 04 12:29:03 PM PDT 24
Peak memory 190920 kb
Host smart-5575b0c0-664e-4ef9-9b2c-6ff2986cd079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081663429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2081663429
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3062842587
Short name T354
Test name
Test status
Simulation time 233535859582 ps
CPU time 204.66 seconds
Started Jun 04 12:24:36 PM PDT 24
Finished Jun 04 12:28:04 PM PDT 24
Peak memory 190996 kb
Host smart-aa5eaa4b-ab78-4a5b-8509-b200b985c517
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062842587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3062842587
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1682215109
Short name T422
Test name
Test status
Simulation time 8613730584 ps
CPU time 99.23 seconds
Started Jun 04 12:24:24 PM PDT 24
Finished Jun 04 12:26:05 PM PDT 24
Peak memory 182804 kb
Host smart-0b8c8a53-6206-45b2-a2bc-9a5be9fc003b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682215109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1682215109
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2967643272
Short name T134
Test name
Test status
Simulation time 21897819779 ps
CPU time 7.11 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:24:48 PM PDT 24
Peak memory 182660 kb
Host smart-08456567-7262-4bbc-9ef9-7f2dd4cc6e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967643272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2967643272
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4052989855
Short name T158
Test name
Test status
Simulation time 280804478259 ps
CPU time 1076.3 seconds
Started Jun 04 12:24:19 PM PDT 24
Finished Jun 04 12:42:17 PM PDT 24
Peak memory 191124 kb
Host smart-dd673b6c-ef6a-4a0c-affe-6e8285c8c693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052989855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4052989855
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2562322531
Short name T71
Test name
Test status
Simulation time 380180008973 ps
CPU time 185.32 seconds
Started Jun 04 12:24:26 PM PDT 24
Finished Jun 04 12:27:33 PM PDT 24
Peak memory 190940 kb
Host smart-b18b8257-abd4-4313-a6e2-8619592f898a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562322531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2562322531
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3010171506
Short name T362
Test name
Test status
Simulation time 235362016768 ps
CPU time 66.48 seconds
Started Jun 04 12:23:54 PM PDT 24
Finished Jun 04 12:25:02 PM PDT 24
Peak memory 182572 kb
Host smart-7d436b75-4952-4ba0-8be9-5406de07dcca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010171506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3010171506
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1943894469
Short name T388
Test name
Test status
Simulation time 667953801771 ps
CPU time 109.47 seconds
Started Jun 04 12:22:32 PM PDT 24
Finished Jun 04 12:24:23 PM PDT 24
Peak memory 182796 kb
Host smart-36f7040f-16c2-4a74-9e05-54b3c4d1f240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943894469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1943894469
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3280023631
Short name T212
Test name
Test status
Simulation time 1884834552967 ps
CPU time 583.24 seconds
Started Jun 04 12:22:34 PM PDT 24
Finished Jun 04 12:32:18 PM PDT 24
Peak memory 191152 kb
Host smart-a2501bfc-964d-4212-9f13-8a211be21495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280023631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3280023631
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3951589092
Short name T123
Test name
Test status
Simulation time 128639533296 ps
CPU time 31.62 seconds
Started Jun 04 12:23:24 PM PDT 24
Finished Jun 04 12:23:56 PM PDT 24
Peak memory 190984 kb
Host smart-e720e465-d3b8-417f-a4b2-99ed03f3541c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951589092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3951589092
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.4269457516
Short name T243
Test name
Test status
Simulation time 1150133652688 ps
CPU time 613.87 seconds
Started Jun 04 12:24:24 PM PDT 24
Finished Jun 04 12:34:41 PM PDT 24
Peak memory 191004 kb
Host smart-350083d0-d04d-464e-9101-ecaf244e98ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269457516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4269457516
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1015438534
Short name T147
Test name
Test status
Simulation time 82143715662 ps
CPU time 311.15 seconds
Started Jun 04 12:24:28 PM PDT 24
Finished Jun 04 12:29:41 PM PDT 24
Peak memory 190984 kb
Host smart-51fdddab-6348-417e-83b9-8e719b246666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015438534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1015438534
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2438695839
Short name T419
Test name
Test status
Simulation time 21753120320 ps
CPU time 32 seconds
Started Jun 04 12:24:13 PM PDT 24
Finished Jun 04 12:24:46 PM PDT 24
Peak memory 182764 kb
Host smart-d8716c61-62da-475d-b8d8-e8dc836b33d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438695839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2438695839
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.981349157
Short name T172
Test name
Test status
Simulation time 47909051186 ps
CPU time 149.57 seconds
Started Jun 04 12:24:41 PM PDT 24
Finished Jun 04 12:27:13 PM PDT 24
Peak memory 190972 kb
Host smart-15e21120-c9b2-4cf4-a7ad-c4138e0d673e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981349157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.981349157
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2563043818
Short name T142
Test name
Test status
Simulation time 68122574668 ps
CPU time 23.36 seconds
Started Jun 04 12:24:34 PM PDT 24
Finished Jun 04 12:24:58 PM PDT 24
Peak memory 182720 kb
Host smart-292a12d5-3c1f-4e40-a113-282a8cd2dbc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563043818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2563043818
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.272933761
Short name T301
Test name
Test status
Simulation time 150176824697 ps
CPU time 376.81 seconds
Started Jun 04 12:24:39 PM PDT 24
Finished Jun 04 12:30:59 PM PDT 24
Peak memory 182728 kb
Host smart-a08a4fee-a414-4123-88f4-688e9d0794af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272933761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.272933761
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3038046315
Short name T353
Test name
Test status
Simulation time 29272773326 ps
CPU time 22.87 seconds
Started Jun 04 12:24:24 PM PDT 24
Finished Jun 04 12:24:49 PM PDT 24
Peak memory 182796 kb
Host smart-129176b0-e5d2-4ba3-8120-a9e7062442a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038046315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3038046315
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1590328600
Short name T273
Test name
Test status
Simulation time 2012853440454 ps
CPU time 419.35 seconds
Started Jun 04 12:24:38 PM PDT 24
Finished Jun 04 12:31:41 PM PDT 24
Peak memory 191008 kb
Host smart-c241a40d-b74c-4422-9f16-1cf385a3a05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590328600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1590328600
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2984071853
Short name T335
Test name
Test status
Simulation time 52872159046 ps
CPU time 1096.13 seconds
Started Jun 04 12:24:27 PM PDT 24
Finished Jun 04 12:42:45 PM PDT 24
Peak memory 190928 kb
Host smart-39b4ae99-d7ce-4ed2-8e9c-15017cd94e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984071853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2984071853
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2700874728
Short name T131
Test name
Test status
Simulation time 1232200385770 ps
CPU time 692.32 seconds
Started Jun 04 12:22:38 PM PDT 24
Finished Jun 04 12:34:11 PM PDT 24
Peak memory 182784 kb
Host smart-385905b2-ad94-4da1-b097-195d743cfdd1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700874728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2700874728
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3207979959
Short name T387
Test name
Test status
Simulation time 93919756708 ps
CPU time 110.18 seconds
Started Jun 04 12:22:41 PM PDT 24
Finished Jun 04 12:24:32 PM PDT 24
Peak memory 182816 kb
Host smart-7787d642-83ac-424f-9319-73433e16243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207979959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3207979959
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1985788841
Short name T304
Test name
Test status
Simulation time 943057939405 ps
CPU time 287.31 seconds
Started Jun 04 12:22:39 PM PDT 24
Finished Jun 04 12:27:26 PM PDT 24
Peak memory 182944 kb
Host smart-6c66b6f2-932e-42a1-ada0-bfcd6f57308e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985788841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1985788841
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.3479481225
Short name T111
Test name
Test status
Simulation time 510759143570 ps
CPU time 256.45 seconds
Started Jun 04 12:24:30 PM PDT 24
Finished Jun 04 12:28:47 PM PDT 24
Peak memory 191004 kb
Host smart-2354de86-df3b-431a-9df9-80c076eddee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479481225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3479481225
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.544828541
Short name T312
Test name
Test status
Simulation time 216503936119 ps
CPU time 105.6 seconds
Started Jun 04 12:24:25 PM PDT 24
Finished Jun 04 12:26:13 PM PDT 24
Peak memory 191000 kb
Host smart-46895fa7-d17e-48b0-aaf9-8335901449e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544828541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.544828541
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.345412482
Short name T222
Test name
Test status
Simulation time 144589827734 ps
CPU time 65.64 seconds
Started Jun 04 12:24:35 PM PDT 24
Finished Jun 04 12:25:42 PM PDT 24
Peak memory 190948 kb
Host smart-733a1544-7868-4e6b-bb7a-d87d644e041b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345412482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.345412482
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3457606118
Short name T133
Test name
Test status
Simulation time 747123364850 ps
CPU time 600.64 seconds
Started Jun 04 12:24:27 PM PDT 24
Finished Jun 04 12:34:30 PM PDT 24
Peak memory 193628 kb
Host smart-5e8dc4e2-6cb9-49ce-be44-e157595e85bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457606118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3457606118
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1889368661
Short name T283
Test name
Test status
Simulation time 67449113353 ps
CPU time 131.68 seconds
Started Jun 04 12:24:23 PM PDT 24
Finished Jun 04 12:26:37 PM PDT 24
Peak memory 191004 kb
Host smart-64a01d52-8d3c-49cb-8c66-2748cc41a840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889368661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1889368661
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2393416629
Short name T139
Test name
Test status
Simulation time 3417777392693 ps
CPU time 614.43 seconds
Started Jun 04 12:24:47 PM PDT 24
Finished Jun 04 12:35:03 PM PDT 24
Peak memory 190980 kb
Host smart-2c3f1f26-abc9-4bc9-b5f1-278a233bccf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393416629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2393416629
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2122413919
Short name T200
Test name
Test status
Simulation time 212403695384 ps
CPU time 92.05 seconds
Started Jun 04 12:24:24 PM PDT 24
Finished Jun 04 12:25:59 PM PDT 24
Peak memory 191000 kb
Host smart-e08bde1e-6987-4015-89c7-0e4673d643fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122413919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2122413919
Directory /workspace/99.rv_timer_random/latest
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