Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 584
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1860556226 Jun 05 03:51:33 PM PDT 24 Jun 05 03:51:35 PM PDT 24 15581470 ps
T512 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1099657288 Jun 05 03:51:44 PM PDT 24 Jun 05 03:51:47 PM PDT 24 16042159 ps
T513 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4290581231 Jun 05 03:51:35 PM PDT 24 Jun 05 03:51:39 PM PDT 24 199275473 ps
T514 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3808771932 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:47 PM PDT 24 54122554 ps
T515 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1752911711 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:34 PM PDT 24 12778750 ps
T516 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2601689473 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:34 PM PDT 24 81945199 ps
T75 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2370406663 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:45 PM PDT 24 13667536 ps
T517 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2541216752 Jun 05 03:51:45 PM PDT 24 Jun 05 03:51:50 PM PDT 24 727220582 ps
T518 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2619081009 Jun 05 03:51:48 PM PDT 24 Jun 05 03:51:50 PM PDT 24 41196386 ps
T519 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3025783471 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:34 PM PDT 24 46164956 ps
T520 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1918090936 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:34 PM PDT 24 74199207 ps
T521 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2515355843 Jun 05 03:51:54 PM PDT 24 Jun 05 03:51:55 PM PDT 24 17148934 ps
T522 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3984265348 Jun 05 03:51:39 PM PDT 24 Jun 05 03:51:41 PM PDT 24 16647511 ps
T523 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3526331827 Jun 05 03:51:29 PM PDT 24 Jun 05 03:51:33 PM PDT 24 412724357 ps
T524 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.4166715422 Jun 05 03:51:33 PM PDT 24 Jun 05 03:51:35 PM PDT 24 20634453 ps
T76 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1410350819 Jun 05 03:51:42 PM PDT 24 Jun 05 03:51:44 PM PDT 24 40497231 ps
T525 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1149294902 Jun 05 03:51:47 PM PDT 24 Jun 05 03:51:48 PM PDT 24 12276862 ps
T526 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4127263503 Jun 05 03:51:31 PM PDT 24 Jun 05 03:51:33 PM PDT 24 87163775 ps
T527 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1023567136 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:35 PM PDT 24 31550240 ps
T528 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2991184282 Jun 05 03:51:39 PM PDT 24 Jun 05 03:51:41 PM PDT 24 19324617 ps
T529 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3339012362 Jun 05 03:51:50 PM PDT 24 Jun 05 03:51:51 PM PDT 24 12074513 ps
T530 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2498347079 Jun 05 03:51:40 PM PDT 24 Jun 05 03:51:44 PM PDT 24 55407688 ps
T531 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2753964112 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:46 PM PDT 24 19909772 ps
T532 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2020944292 Jun 05 03:51:40 PM PDT 24 Jun 05 03:51:42 PM PDT 24 60011162 ps
T533 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.433179508 Jun 05 03:51:41 PM PDT 24 Jun 05 03:51:43 PM PDT 24 19043018 ps
T534 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4213879849 Jun 05 03:51:42 PM PDT 24 Jun 05 03:51:44 PM PDT 24 36811479 ps
T535 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3441508183 Jun 05 03:51:42 PM PDT 24 Jun 05 03:51:44 PM PDT 24 47156394 ps
T536 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3485233514 Jun 05 03:51:44 PM PDT 24 Jun 05 03:51:47 PM PDT 24 23663253 ps
T537 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2637683348 Jun 05 03:51:36 PM PDT 24 Jun 05 03:51:37 PM PDT 24 16722357 ps
T538 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2248789252 Jun 05 03:51:51 PM PDT 24 Jun 05 03:51:53 PM PDT 24 16164380 ps
T539 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2364340500 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:45 PM PDT 24 13272812 ps
T540 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1556763298 Jun 05 03:51:24 PM PDT 24 Jun 05 03:51:27 PM PDT 24 95297033 ps
T541 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1739757080 Jun 05 03:51:29 PM PDT 24 Jun 05 03:51:31 PM PDT 24 294540061 ps
T98 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2815351373 Jun 05 03:51:31 PM PDT 24 Jun 05 03:51:33 PM PDT 24 350066361 ps
T542 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1566301608 Jun 05 03:51:45 PM PDT 24 Jun 05 03:51:48 PM PDT 24 34614081 ps
T543 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1006618772 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:45 PM PDT 24 40508688 ps
T544 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1402623006 Jun 05 03:51:31 PM PDT 24 Jun 05 03:51:35 PM PDT 24 540675041 ps
T545 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3564686109 Jun 05 03:51:44 PM PDT 24 Jun 05 03:51:47 PM PDT 24 93285394 ps
T77 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1936073084 Jun 05 03:51:31 PM PDT 24 Jun 05 03:51:33 PM PDT 24 43967677 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3392076571 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:34 PM PDT 24 18481480 ps
T547 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.906355308 Jun 05 03:51:42 PM PDT 24 Jun 05 03:51:45 PM PDT 24 111310754 ps
T548 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1318368291 Jun 05 03:51:41 PM PDT 24 Jun 05 03:51:43 PM PDT 24 155856735 ps
T549 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1233704929 Jun 05 03:51:44 PM PDT 24 Jun 05 03:51:48 PM PDT 24 278826713 ps
T550 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3446352122 Jun 05 03:51:37 PM PDT 24 Jun 05 03:51:38 PM PDT 24 52581584 ps
T78 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1301016035 Jun 05 03:51:30 PM PDT 24 Jun 05 03:51:32 PM PDT 24 30781630 ps
T551 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1104792654 Jun 05 03:51:49 PM PDT 24 Jun 05 03:51:50 PM PDT 24 15503176 ps
T552 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1688890720 Jun 05 03:51:30 PM PDT 24 Jun 05 03:51:33 PM PDT 24 176507478 ps
T553 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.527445121 Jun 05 03:51:24 PM PDT 24 Jun 05 03:51:25 PM PDT 24 12239399 ps
T97 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.109892214 Jun 05 03:51:41 PM PDT 24 Jun 05 03:51:44 PM PDT 24 960534412 ps
T554 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2049759477 Jun 05 03:51:30 PM PDT 24 Jun 05 03:51:33 PM PDT 24 247900922 ps
T555 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1790329482 Jun 05 03:51:38 PM PDT 24 Jun 05 03:51:41 PM PDT 24 95404416 ps
T556 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1734558625 Jun 05 03:51:50 PM PDT 24 Jun 05 03:51:51 PM PDT 24 28658290 ps
T557 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.154085702 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:46 PM PDT 24 13189491 ps
T558 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.750695037 Jun 05 03:51:42 PM PDT 24 Jun 05 03:51:45 PM PDT 24 128160887 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.25667548 Jun 05 03:51:33 PM PDT 24 Jun 05 03:51:36 PM PDT 24 29352984 ps
T560 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3476781380 Jun 05 03:51:45 PM PDT 24 Jun 05 03:51:47 PM PDT 24 65578325 ps
T561 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3542366608 Jun 05 03:51:33 PM PDT 24 Jun 05 03:51:36 PM PDT 24 142893128 ps
T79 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4131914015 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:35 PM PDT 24 19400434 ps
T562 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1904117685 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:45 PM PDT 24 67364394 ps
T563 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.16807418 Jun 05 03:51:42 PM PDT 24 Jun 05 03:51:45 PM PDT 24 195269611 ps
T80 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2915211299 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:35 PM PDT 24 827669639 ps
T564 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3449879702 Jun 05 03:51:41 PM PDT 24 Jun 05 03:51:43 PM PDT 24 38097639 ps
T565 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3961528822 Jun 05 03:51:24 PM PDT 24 Jun 05 03:51:26 PM PDT 24 254685555 ps
T566 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1624465121 Jun 05 03:51:45 PM PDT 24 Jun 05 03:51:47 PM PDT 24 17097193 ps
T567 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3390183195 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:46 PM PDT 24 15067774 ps
T568 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3346386856 Jun 05 03:51:36 PM PDT 24 Jun 05 03:51:38 PM PDT 24 117887689 ps
T569 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1812232884 Jun 05 03:51:47 PM PDT 24 Jun 05 03:51:48 PM PDT 24 108387914 ps
T570 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.658664183 Jun 05 03:51:47 PM PDT 24 Jun 05 03:51:49 PM PDT 24 25152710 ps
T571 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2855124337 Jun 05 03:51:32 PM PDT 24 Jun 05 03:51:35 PM PDT 24 94505621 ps
T572 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1287340034 Jun 05 03:51:37 PM PDT 24 Jun 05 03:51:38 PM PDT 24 10722125 ps
T573 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1073400598 Jun 05 03:51:29 PM PDT 24 Jun 05 03:51:30 PM PDT 24 27059160 ps
T81 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3568833336 Jun 05 03:51:33 PM PDT 24 Jun 05 03:51:35 PM PDT 24 98295211 ps
T574 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.384916824 Jun 05 03:51:42 PM PDT 24 Jun 05 03:51:44 PM PDT 24 14720324 ps
T575 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2766259185 Jun 05 03:51:38 PM PDT 24 Jun 05 03:51:39 PM PDT 24 66650495 ps
T576 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1155620649 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:46 PM PDT 24 12182721 ps
T577 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4206283264 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:46 PM PDT 24 28518299 ps
T578 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3681868715 Jun 05 03:51:41 PM PDT 24 Jun 05 03:51:43 PM PDT 24 39708859 ps
T99 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4019461626 Jun 05 03:51:36 PM PDT 24 Jun 05 03:51:39 PM PDT 24 380584187 ps
T579 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.233360617 Jun 05 03:51:40 PM PDT 24 Jun 05 03:51:41 PM PDT 24 14671755 ps
T580 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2967695705 Jun 05 03:51:46 PM PDT 24 Jun 05 03:51:48 PM PDT 24 26490008 ps
T581 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1581030288 Jun 05 03:51:33 PM PDT 24 Jun 05 03:51:35 PM PDT 24 681890746 ps
T582 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1768751652 Jun 05 03:51:45 PM PDT 24 Jun 05 03:51:47 PM PDT 24 37861354 ps
T583 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2686504159 Jun 05 03:51:43 PM PDT 24 Jun 05 03:51:46 PM PDT 24 29521882 ps
T584 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1219674518 Jun 05 03:51:49 PM PDT 24 Jun 05 03:51:50 PM PDT 24 14672250 ps

Test location /workspace/coverage/default/29.rv_timer_random_reset.678766989
Short name T3
Test name
Test status
Simulation time 282195311623 ps
CPU time 375.11 seconds
Started Jun 05 03:52:21 PM PDT 24
Finished Jun 05 03:58:36 PM PDT 24
Peak memory 191188 kb
Host smart-e4b3a9d2-f112-4522-9e99-1eafcf3f2e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678766989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.678766989
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3226145006
Short name T12
Test name
Test status
Simulation time 230738765267 ps
CPU time 469.66 seconds
Started Jun 05 03:52:26 PM PDT 24
Finished Jun 05 04:00:17 PM PDT 24
Peak memory 205868 kb
Host smart-03a8be6e-e8ac-4c02-80f0-8cf6f04da8c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226145006 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3226145006
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2754018030
Short name T8
Test name
Test status
Simulation time 1755493056535 ps
CPU time 1345.8 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 04:15:00 PM PDT 24
Peak memory 191076 kb
Host smart-21667a54-3f7b-41c9-a3db-a3c6a3cb3364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754018030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2754018030
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1170698390
Short name T26
Test name
Test status
Simulation time 214838354 ps
CPU time 1.42 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 183112 kb
Host smart-abdd021a-980c-4c9e-8337-ab840ccff4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170698390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1170698390
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1557777078
Short name T53
Test name
Test status
Simulation time 3836676739385 ps
CPU time 1637.3 seconds
Started Jun 05 03:52:21 PM PDT 24
Finished Jun 05 04:19:39 PM PDT 24
Peak memory 191076 kb
Host smart-ec79a33a-2763-4c25-ae02-3c42f897e25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557777078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1557777078
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1930176838
Short name T198
Test name
Test status
Simulation time 595494913491 ps
CPU time 3044.77 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 04:43:10 PM PDT 24
Peak memory 195896 kb
Host smart-494f0f5e-a84b-450d-bfbb-2a0d388d0c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930176838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1930176838
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1810558430
Short name T107
Test name
Test status
Simulation time 884821650613 ps
CPU time 2964.73 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 04:41:49 PM PDT 24
Peak memory 191068 kb
Host smart-d6812ce9-c16b-43a5-9201-7f7d8dae521c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810558430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1810558430
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2798628991
Short name T208
Test name
Test status
Simulation time 1915885182595 ps
CPU time 1672.68 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 04:19:45 PM PDT 24
Peak memory 191416 kb
Host smart-cc47c6a1-a374-4919-bfc6-7f6bf6076cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798628991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2798628991
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3101260905
Short name T176
Test name
Test status
Simulation time 8034240595802 ps
CPU time 2763.72 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 04:38:41 PM PDT 24
Peak memory 191184 kb
Host smart-9ef498eb-8fd4-44e1-957b-6dc1d5d4afe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101260905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3101260905
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.202728393
Short name T171
Test name
Test status
Simulation time 680508483241 ps
CPU time 1243.1 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 04:13:12 PM PDT 24
Peak memory 191084 kb
Host smart-833ffb95-5ac5-4bde-9b78-5ebb55365686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202728393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
202728393
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2030819004
Short name T164
Test name
Test status
Simulation time 877216498156 ps
CPU time 3174.91 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 04:45:23 PM PDT 24
Peak memory 191452 kb
Host smart-90735974-6924-4fc2-ae3d-fbcccf8755c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030819004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2030819004
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.557519147
Short name T73
Test name
Test status
Simulation time 18898309 ps
CPU time 0.61 seconds
Started Jun 05 03:51:31 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 182612 kb
Host smart-21aede9b-635d-4817-a85b-cc7993882475
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557519147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.557519147
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/175.rv_timer_random.250418930
Short name T128
Test name
Test status
Simulation time 195545190869 ps
CPU time 287.55 seconds
Started Jun 05 03:52:52 PM PDT 24
Finished Jun 05 03:57:41 PM PDT 24
Peak memory 193784 kb
Host smart-47983d86-712a-4e81-88fb-85ef792d9181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250418930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.250418930
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.2087734176
Short name T106
Test name
Test status
Simulation time 581636840849 ps
CPU time 746.24 seconds
Started Jun 05 03:52:22 PM PDT 24
Finished Jun 05 04:04:50 PM PDT 24
Peak memory 191072 kb
Host smart-14ea5d73-03a2-49c9-bfcc-d696bcf46df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087734176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2087734176
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2062661436
Short name T15
Test name
Test status
Simulation time 478221746 ps
CPU time 0.94 seconds
Started Jun 05 03:51:57 PM PDT 24
Finished Jun 05 03:51:59 PM PDT 24
Peak memory 213360 kb
Host smart-f3345b53-ef09-46af-9e02-49b6a2ed45e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062661436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2062661436
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/182.rv_timer_random.4227772347
Short name T10
Test name
Test status
Simulation time 164638480124 ps
CPU time 1245.92 seconds
Started Jun 05 03:52:56 PM PDT 24
Finished Jun 05 04:13:43 PM PDT 24
Peak memory 191176 kb
Host smart-3431ba4a-cb6b-44a3-871d-3a5c18cc9631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227772347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.4227772347
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2872108435
Short name T329
Test name
Test status
Simulation time 1717872962982 ps
CPU time 3229.9 seconds
Started Jun 05 03:52:22 PM PDT 24
Finished Jun 05 04:46:14 PM PDT 24
Peak memory 191168 kb
Host smart-7d9323e3-a8b1-47f7-9846-3067973c90d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872108435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2872108435
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1208038669
Short name T241
Test name
Test status
Simulation time 522409889579 ps
CPU time 2011.19 seconds
Started Jun 05 03:52:03 PM PDT 24
Finished Jun 05 04:25:35 PM PDT 24
Peak memory 191068 kb
Host smart-9bedb0d6-b27d-40d4-bbde-db6c6c3efbe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208038669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1208038669
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2688856020
Short name T50
Test name
Test status
Simulation time 2537732545967 ps
CPU time 1137.83 seconds
Started Jun 05 03:52:13 PM PDT 24
Finished Jun 05 04:11:12 PM PDT 24
Peak memory 191084 kb
Host smart-a6ff247c-1f4f-4d5f-8ec9-828b15a4882f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688856020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2688856020
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_random.2618890293
Short name T104
Test name
Test status
Simulation time 607351891791 ps
CPU time 554.2 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 04:01:48 PM PDT 24
Peak memory 191184 kb
Host smart-f300f5b1-10db-4f95-8cee-bdad728097ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618890293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2618890293
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.723695821
Short name T52
Test name
Test status
Simulation time 460288218785 ps
CPU time 407.36 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 03:59:24 PM PDT 24
Peak memory 195844 kb
Host smart-0dca9ad1-2ea4-4f31-b545-b463abc45774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723695821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
723695821
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2671758125
Short name T179
Test name
Test status
Simulation time 589789264489 ps
CPU time 1245.76 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 04:13:16 PM PDT 24
Peak memory 191036 kb
Host smart-aceb4fcb-3323-45d9-8421-5a8fd947b538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671758125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2671758125
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.615122055
Short name T120
Test name
Test status
Simulation time 2560623120826 ps
CPU time 1482.66 seconds
Started Jun 05 03:52:56 PM PDT 24
Finished Jun 05 04:17:40 PM PDT 24
Peak memory 191068 kb
Host smart-d6c6b433-4a18-449b-a413-e22c7866e65e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615122055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.615122055
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2189231158
Short name T131
Test name
Test status
Simulation time 1692979646716 ps
CPU time 738.43 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 04:04:46 PM PDT 24
Peak memory 191060 kb
Host smart-b144e826-0f5e-4a4e-bf07-a77289790033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189231158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2189231158
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4025905643
Short name T242
Test name
Test status
Simulation time 4222668006883 ps
CPU time 2224.12 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 04:29:36 PM PDT 24
Peak memory 191076 kb
Host smart-4e511447-ea4a-4e18-a43f-4dc6352036d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025905643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4025905643
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_random.4190005769
Short name T197
Test name
Test status
Simulation time 164033899263 ps
CPU time 828.18 seconds
Started Jun 05 03:52:09 PM PDT 24
Finished Jun 05 04:05:58 PM PDT 24
Peak memory 191076 kb
Host smart-cb9acb0f-cc91-4577-8b3f-ff0dbddb1dde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190005769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4190005769
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3640838825
Short name T237
Test name
Test status
Simulation time 613247965132 ps
CPU time 305.59 seconds
Started Jun 05 03:52:34 PM PDT 24
Finished Jun 05 03:57:40 PM PDT 24
Peak memory 191016 kb
Host smart-6a10dfe2-1522-4f22-a980-6487b7fc899b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640838825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3640838825
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.3605486559
Short name T265
Test name
Test status
Simulation time 490793311963 ps
CPU time 261.29 seconds
Started Jun 05 03:52:15 PM PDT 24
Finished Jun 05 03:56:37 PM PDT 24
Peak memory 191184 kb
Host smart-9c4a9958-e43b-4ca9-82af-acdfc7bd1aa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605486559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3605486559
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.2765562326
Short name T111
Test name
Test status
Simulation time 249492585190 ps
CPU time 296.09 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:57:21 PM PDT 24
Peak memory 194704 kb
Host smart-db0b47a5-0406-4d15-8246-f3dc59a68230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765562326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2765562326
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1746203382
Short name T190
Test name
Test status
Simulation time 132590125234 ps
CPU time 212.55 seconds
Started Jun 05 03:52:44 PM PDT 24
Finished Jun 05 03:56:17 PM PDT 24
Peak memory 193400 kb
Host smart-05be8441-40ca-480c-9c51-bd2da916da6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746203382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1746203382
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4229057034
Short name T227
Test name
Test status
Simulation time 599669627557 ps
CPU time 2297.74 seconds
Started Jun 05 03:53:02 PM PDT 24
Finished Jun 05 04:31:21 PM PDT 24
Peak memory 191180 kb
Host smart-99506e51-a359-4221-a7af-b3063f06b6e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229057034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4229057034
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3474179080
Short name T256
Test name
Test status
Simulation time 119200771232 ps
CPU time 435.2 seconds
Started Jun 05 03:52:41 PM PDT 24
Finished Jun 05 03:59:57 PM PDT 24
Peak memory 191052 kb
Host smart-3fddddfd-d51e-45d1-9b1a-149effcf8533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474179080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3474179080
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.972944919
Short name T67
Test name
Test status
Simulation time 34977536 ps
CPU time 0.61 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 182616 kb
Host smart-bacaca5a-fcf4-4134-9fd3-88784662024b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972944919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.972944919
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/100.rv_timer_random.3320699298
Short name T286
Test name
Test status
Simulation time 568788673298 ps
CPU time 580.32 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 04:02:14 PM PDT 24
Peak memory 193508 kb
Host smart-1c8f005f-9adc-4e5d-a307-f9a413ee4b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320699298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3320699298
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2117192064
Short name T268
Test name
Test status
Simulation time 1140917529475 ps
CPU time 1470.21 seconds
Started Jun 05 03:52:57 PM PDT 24
Finished Jun 05 04:17:28 PM PDT 24
Peak memory 190784 kb
Host smart-08af8302-921e-4794-bda7-b6eb8cfbc898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117192064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2117192064
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.545807975
Short name T9
Test name
Test status
Simulation time 266031746610 ps
CPU time 275.4 seconds
Started Jun 05 03:52:59 PM PDT 24
Finished Jun 05 03:57:36 PM PDT 24
Peak memory 193308 kb
Host smart-a3b05bfb-1f02-447b-96a4-3e737127cb46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545807975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.545807975
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3080448634
Short name T225
Test name
Test status
Simulation time 731143812489 ps
CPU time 601.11 seconds
Started Jun 05 03:52:51 PM PDT 24
Finished Jun 05 04:02:53 PM PDT 24
Peak memory 193660 kb
Host smart-a62f90c1-f0d2-4b24-96f1-badf9e41c7ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080448634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3080448634
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1785779689
Short name T91
Test name
Test status
Simulation time 1155499542930 ps
CPU time 735.29 seconds
Started Jun 05 03:52:48 PM PDT 24
Finished Jun 05 04:05:04 PM PDT 24
Peak memory 191076 kb
Host smart-3966991a-1c84-4ab0-9341-d2fb6ffcfc36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785779689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1785779689
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random.3568861331
Short name T126
Test name
Test status
Simulation time 316614599782 ps
CPU time 1538.78 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 04:18:07 PM PDT 24
Peak memory 191176 kb
Host smart-e9b9fe64-1295-4c6c-8611-0609f3e9a16c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568861331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3568861331
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1644168033
Short name T324
Test name
Test status
Simulation time 555034537526 ps
CPU time 210.9 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 03:56:05 PM PDT 24
Peak memory 191180 kb
Host smart-b4fe18dd-608c-4bae-a566-73545a94852c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644168033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1644168033
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.644487263
Short name T149
Test name
Test status
Simulation time 936745860237 ps
CPU time 853.5 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 04:07:00 PM PDT 24
Peak memory 191064 kb
Host smart-67f3e6e6-ea91-4f1a-8eef-8df06a6d4ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644487263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.644487263
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1693071862
Short name T276
Test name
Test status
Simulation time 80036093655 ps
CPU time 124.29 seconds
Started Jun 05 03:52:44 PM PDT 24
Finished Jun 05 03:54:49 PM PDT 24
Peak memory 191068 kb
Host smart-66bac054-9906-4625-8645-3db6e65c97db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693071862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1693071862
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2027667495
Short name T302
Test name
Test status
Simulation time 159327522828 ps
CPU time 428.76 seconds
Started Jun 05 03:52:43 PM PDT 24
Finished Jun 05 03:59:53 PM PDT 24
Peak memory 191076 kb
Host smart-2dc2ed10-6106-4440-8bf2-050dd4abe868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027667495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2027667495
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.4156458976
Short name T217
Test name
Test status
Simulation time 416169828567 ps
CPU time 456.07 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 04:00:22 PM PDT 24
Peak memory 191180 kb
Host smart-ac048f58-ae44-4c45-aefe-824e52c12b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156458976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.4156458976
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3540278483
Short name T203
Test name
Test status
Simulation time 1788274511268 ps
CPU time 825.16 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 04:06:10 PM PDT 24
Peak memory 191188 kb
Host smart-fc9f6b3e-e9b8-4442-bfe6-0ea6fec9f10d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540278483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3540278483
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3897089065
Short name T223
Test name
Test status
Simulation time 305991932080 ps
CPU time 553.65 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 04:01:42 PM PDT 24
Peak memory 182888 kb
Host smart-a6bd8db0-7bed-43a4-9ee8-2ba18dff28ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897089065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3897089065
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.4072575165
Short name T161
Test name
Test status
Simulation time 1278755682612 ps
CPU time 697.47 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 04:04:24 PM PDT 24
Peak memory 191176 kb
Host smart-e633bb3d-5570-44b7-b451-243b7fce7de2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072575165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.4072575165
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1822087503
Short name T337
Test name
Test status
Simulation time 164076501851 ps
CPU time 101.31 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 03:54:24 PM PDT 24
Peak memory 191184 kb
Host smart-559334ff-ca6c-493e-9a95-5de2875b0af3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822087503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1822087503
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1740610094
Short name T238
Test name
Test status
Simulation time 152621101613 ps
CPU time 1342.23 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 04:15:00 PM PDT 24
Peak memory 191072 kb
Host smart-e61a4389-1d2e-4d80-9554-62168cbea544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740610094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1740610094
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2244026679
Short name T249
Test name
Test status
Simulation time 254346528512 ps
CPU time 246.04 seconds
Started Jun 05 03:52:48 PM PDT 24
Finished Jun 05 03:56:55 PM PDT 24
Peak memory 191180 kb
Host smart-70aea8a9-bdef-46b1-9e5f-c14871463dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244026679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2244026679
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1361501529
Short name T289
Test name
Test status
Simulation time 131800995920 ps
CPU time 531.24 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 04:01:28 PM PDT 24
Peak memory 191444 kb
Host smart-5e672f5e-7b7f-4568-8ea7-0e939c566793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361501529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1361501529
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3500369199
Short name T231
Test name
Test status
Simulation time 20415928429 ps
CPU time 20.34 seconds
Started Jun 05 03:52:39 PM PDT 24
Finished Jun 05 03:53:00 PM PDT 24
Peak memory 191080 kb
Host smart-fe76408d-fa5f-43c8-9411-3e90494a4beb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500369199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3500369199
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2742684413
Short name T157
Test name
Test status
Simulation time 136276644795 ps
CPU time 802.7 seconds
Started Jun 05 03:52:48 PM PDT 24
Finished Jun 05 04:06:11 PM PDT 24
Peak memory 191172 kb
Host smart-0c6cb009-91b8-4092-bbb8-f436e499a0ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742684413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2742684413
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.1739045197
Short name T46
Test name
Test status
Simulation time 192756988169 ps
CPU time 190.46 seconds
Started Jun 05 03:52:11 PM PDT 24
Finished Jun 05 03:55:23 PM PDT 24
Peak memory 197608 kb
Host smart-881e7239-4cd1-493c-86f9-7d9f4a31cdc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739045197 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.1739045197
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.1869455287
Short name T243
Test name
Test status
Simulation time 444833124561 ps
CPU time 385.53 seconds
Started Jun 05 03:52:52 PM PDT 24
Finished Jun 05 03:59:18 PM PDT 24
Peak memory 191180 kb
Host smart-3182e491-3623-4190-8361-97bff4b80e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869455287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1869455287
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.505131680
Short name T182
Test name
Test status
Simulation time 1333934293875 ps
CPU time 522.14 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 04:01:11 PM PDT 24
Peak memory 182868 kb
Host smart-8d80700b-5e0b-4b79-ab64-98e095d3dfa6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505131680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.505131680
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.467677920
Short name T267
Test name
Test status
Simulation time 303587403537 ps
CPU time 1163.45 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 04:11:48 PM PDT 24
Peak memory 191180 kb
Host smart-318487f3-c780-4199-85d7-66e663fe6ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467677920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.467677920
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.2431923087
Short name T274
Test name
Test status
Simulation time 9596381348 ps
CPU time 14.64 seconds
Started Jun 05 03:52:34 PM PDT 24
Finished Jun 05 03:52:50 PM PDT 24
Peak memory 191080 kb
Host smart-ea38f2f3-20a8-42e3-b9ba-193a43c4cc52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431923087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2431923087
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.784929991
Short name T42
Test name
Test status
Simulation time 1881454719720 ps
CPU time 770.73 seconds
Started Jun 05 03:52:06 PM PDT 24
Finished Jun 05 04:04:58 PM PDT 24
Peak memory 182956 kb
Host smart-088dcddc-b1b8-4bf0-b5d3-dd2dbc0efd8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784929991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.784929991
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3072169911
Short name T55
Test name
Test status
Simulation time 562612086258 ps
CPU time 549.84 seconds
Started Jun 05 03:51:56 PM PDT 24
Finished Jun 05 04:01:07 PM PDT 24
Peak memory 191200 kb
Host smart-e2f954f0-344e-4218-8fda-02b9f608b3ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072169911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3072169911
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.3142820509
Short name T200
Test name
Test status
Simulation time 101228897753 ps
CPU time 158.17 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 191180 kb
Host smart-34886b5f-1278-44da-8ef4-2f5a7038e6b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142820509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3142820509
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2058277061
Short name T206
Test name
Test status
Simulation time 310295379924 ps
CPU time 379.46 seconds
Started Jun 05 03:53:02 PM PDT 24
Finished Jun 05 03:59:22 PM PDT 24
Peak memory 193112 kb
Host smart-c104d275-a637-4272-aae0-f09a230ca28a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058277061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2058277061
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1167097970
Short name T262
Test name
Test status
Simulation time 161519263117 ps
CPU time 787.42 seconds
Started Jun 05 03:52:58 PM PDT 24
Finished Jun 05 04:06:07 PM PDT 24
Peak memory 191068 kb
Host smart-8932a53e-f6aa-49ea-b582-53cd31127385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167097970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1167097970
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2586559598
Short name T54
Test name
Test status
Simulation time 667222123285 ps
CPU time 1342.08 seconds
Started Jun 05 03:52:12 PM PDT 24
Finished Jun 05 04:14:35 PM PDT 24
Peak memory 191184 kb
Host smart-7115b472-f510-4a11-8a7c-43b7e41ce23e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586559598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2586559598
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/177.rv_timer_random.624747637
Short name T196
Test name
Test status
Simulation time 133312382576 ps
CPU time 1612.11 seconds
Started Jun 05 03:52:59 PM PDT 24
Finished Jun 05 04:19:53 PM PDT 24
Peak memory 191072 kb
Host smart-d1ffcce7-2d4a-44dd-9304-72a76e3c9b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624747637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.624747637
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3423867173
Short name T168
Test name
Test status
Simulation time 68327037378 ps
CPU time 116.07 seconds
Started Jun 05 03:52:47 PM PDT 24
Finished Jun 05 03:54:43 PM PDT 24
Peak memory 191456 kb
Host smart-69203a9b-e028-4d74-a5ae-39f779363f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423867173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3423867173
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.2267456247
Short name T58
Test name
Test status
Simulation time 577047565655 ps
CPU time 408.93 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 03:59:22 PM PDT 24
Peak memory 191072 kb
Host smart-ee26954e-f1f6-41fc-a806-902000660860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267456247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2267456247
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.631120824
Short name T63
Test name
Test status
Simulation time 404669746389 ps
CPU time 216.08 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 03:56:00 PM PDT 24
Peak memory 193336 kb
Host smart-ba684010-7fa1-4637-ae77-d1b01859074e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631120824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.631120824
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.376353563
Short name T307
Test name
Test status
Simulation time 2022372871661 ps
CPU time 1271.27 seconds
Started Jun 05 03:52:25 PM PDT 24
Finished Jun 05 04:13:38 PM PDT 24
Peak memory 182972 kb
Host smart-0fb1766b-3bd0-4ed1-8d76-00f7790f29ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376353563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.376353563
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random.187879361
Short name T195
Test name
Test status
Simulation time 84074781423 ps
CPU time 162.97 seconds
Started Jun 05 03:52:34 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 191064 kb
Host smart-aeaa5f59-5661-4e6f-bc74-e6236d2cf9eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187879361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.187879361
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3685844193
Short name T148
Test name
Test status
Simulation time 161164185831 ps
CPU time 318.49 seconds
Started Jun 05 03:52:40 PM PDT 24
Finished Jun 05 03:57:59 PM PDT 24
Peak memory 191172 kb
Host smart-a46247e6-c3d2-4b15-882c-3146cc93a597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685844193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3685844193
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1530888649
Short name T240
Test name
Test status
Simulation time 301530078796 ps
CPU time 166.07 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 03:55:24 PM PDT 24
Peak memory 191128 kb
Host smart-ea93d832-e13b-4f21-8cb3-67801aa15a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530888649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1530888649
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1531117355
Short name T264
Test name
Test status
Simulation time 96813018328 ps
CPU time 179.7 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:55:36 PM PDT 24
Peak memory 191180 kb
Host smart-35313bb5-f91a-43da-9642-2b82f31a78b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531117355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1531117355
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.362993726
Short name T347
Test name
Test status
Simulation time 235457909689 ps
CPU time 405.16 seconds
Started Jun 05 03:52:08 PM PDT 24
Finished Jun 05 03:58:53 PM PDT 24
Peak memory 191436 kb
Host smart-cd3a0304-8dbd-433b-bac2-e54c760cf3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362993726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.362993726
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.109892214
Short name T97
Test name
Test status
Simulation time 960534412 ps
CPU time 1.09 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 194032 kb
Host smart-4f35c8dc-1d61-4652-8c2b-efb57575cd56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109892214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.109892214
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/101.rv_timer_random.1874563212
Short name T39
Test name
Test status
Simulation time 193549298135 ps
CPU time 778.69 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 04:05:36 PM PDT 24
Peak memory 191172 kb
Host smart-bcbb616e-f7f4-401f-a499-8fbe23f542ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874563212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1874563212
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3008792582
Short name T137
Test name
Test status
Simulation time 81277601843 ps
CPU time 138.96 seconds
Started Jun 05 03:51:57 PM PDT 24
Finished Jun 05 03:54:16 PM PDT 24
Peak memory 182840 kb
Host smart-41142703-b892-432d-a211-b2a1cdebff38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008792582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3008792582
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/110.rv_timer_random.1468323985
Short name T214
Test name
Test status
Simulation time 84854768063 ps
CPU time 49.38 seconds
Started Jun 05 03:52:40 PM PDT 24
Finished Jun 05 03:53:30 PM PDT 24
Peak memory 182848 kb
Host smart-e7339849-df5e-4e9c-9d14-6e689780f3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468323985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1468323985
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2282290354
Short name T318
Test name
Test status
Simulation time 111587302768 ps
CPU time 207.84 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 03:56:13 PM PDT 24
Peak memory 191076 kb
Host smart-96cfbc39-119b-46f7-bd55-f85a579ab534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282290354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2282290354
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1969553840
Short name T253
Test name
Test status
Simulation time 261133739366 ps
CPU time 642.61 seconds
Started Jun 05 03:52:51 PM PDT 24
Finished Jun 05 04:03:34 PM PDT 24
Peak memory 191060 kb
Host smart-8b9d355c-1f12-49b0-820b-7b30cd696624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969553840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1969553840
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2528344589
Short name T222
Test name
Test status
Simulation time 458938994230 ps
CPU time 690.2 seconds
Started Jun 05 03:52:01 PM PDT 24
Finished Jun 05 04:03:32 PM PDT 24
Peak memory 191072 kb
Host smart-a00deb14-1973-49bc-a27b-2d54c5c29d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528344589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2528344589
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.3958591170
Short name T4
Test name
Test status
Simulation time 66398859780 ps
CPU time 36.78 seconds
Started Jun 05 03:52:58 PM PDT 24
Finished Jun 05 03:53:36 PM PDT 24
Peak memory 191076 kb
Host smart-5405ad99-dbcb-4c03-93b7-296b1b1fccb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958591170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3958591170
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.847943799
Short name T257
Test name
Test status
Simulation time 699630060985 ps
CPU time 1335.86 seconds
Started Jun 05 03:52:53 PM PDT 24
Finished Jun 05 04:15:10 PM PDT 24
Peak memory 191176 kb
Host smart-d8fd81b1-a963-4a1a-87da-9909a93415f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847943799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.847943799
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2539705193
Short name T247
Test name
Test status
Simulation time 80292445379 ps
CPU time 147.38 seconds
Started Jun 05 03:52:54 PM PDT 24
Finished Jun 05 03:55:23 PM PDT 24
Peak memory 191180 kb
Host smart-8d291fae-7895-443d-8816-c68d110e7f59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539705193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2539705193
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2924442867
Short name T331
Test name
Test status
Simulation time 130703969700 ps
CPU time 1573.04 seconds
Started Jun 05 03:52:49 PM PDT 24
Finished Jun 05 04:19:03 PM PDT 24
Peak memory 191172 kb
Host smart-3242f7f4-63c5-488c-9758-200c0aa7e9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924442867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2924442867
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3148677997
Short name T40
Test name
Test status
Simulation time 408031604488 ps
CPU time 712.76 seconds
Started Jun 05 03:52:12 PM PDT 24
Finished Jun 05 04:04:06 PM PDT 24
Peak memory 182900 kb
Host smart-4d829f5b-0bb0-47f9-86e8-bc3b01e8e882
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148677997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3148677997
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1052231572
Short name T103
Test name
Test status
Simulation time 369409501033 ps
CPU time 199.68 seconds
Started Jun 05 03:52:16 PM PDT 24
Finished Jun 05 03:55:37 PM PDT 24
Peak memory 183004 kb
Host smart-72cd6148-b78f-432b-bb32-8e22cd3c55c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052231572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1052231572
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/161.rv_timer_random.157260360
Short name T105
Test name
Test status
Simulation time 234651981893 ps
CPU time 2365.82 seconds
Started Jun 05 03:52:51 PM PDT 24
Finished Jun 05 04:32:18 PM PDT 24
Peak memory 191184 kb
Host smart-61563891-9c95-4ab9-ba28-340a80821289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157260360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.157260360
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.99295172
Short name T38
Test name
Test status
Simulation time 150956226684 ps
CPU time 556.66 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 04:02:00 PM PDT 24
Peak memory 189780 kb
Host smart-588bccb9-5f6f-4515-942d-7a6f57aaeeae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99295172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.99295172
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3954187730
Short name T309
Test name
Test status
Simulation time 94728588346 ps
CPU time 1285.07 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 04:14:09 PM PDT 24
Peak memory 189820 kb
Host smart-15489f73-6d4e-4d43-821f-5191d701573a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954187730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3954187730
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1964769967
Short name T133
Test name
Test status
Simulation time 417672498934 ps
CPU time 283.53 seconds
Started Jun 05 03:52:16 PM PDT 24
Finished Jun 05 03:57:00 PM PDT 24
Peak memory 194384 kb
Host smart-6aaf13a1-dc3d-4ae6-8092-d0e0b7797713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964769967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1964769967
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2370023481
Short name T155
Test name
Test status
Simulation time 129506909214 ps
CPU time 153.78 seconds
Started Jun 05 03:52:55 PM PDT 24
Finished Jun 05 03:55:30 PM PDT 24
Peak memory 191060 kb
Host smart-d589e7f7-1bed-4315-8753-91b216d9d299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370023481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2370023481
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3276481119
Short name T229
Test name
Test status
Simulation time 314157678588 ps
CPU time 1182.95 seconds
Started Jun 05 03:52:57 PM PDT 24
Finished Jun 05 04:12:41 PM PDT 24
Peak memory 191172 kb
Host smart-8e645f44-fc96-4ba7-b1e1-fef3ce1cab9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276481119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3276481119
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2259352262
Short name T250
Test name
Test status
Simulation time 65494564412 ps
CPU time 108.85 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:54:14 PM PDT 24
Peak memory 191092 kb
Host smart-2ea20a2d-104e-4106-97a7-caffd66949e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259352262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2259352262
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2425680930
Short name T282
Test name
Test status
Simulation time 180116807745 ps
CPU time 174.15 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 182880 kb
Host smart-cbbae7f5-db92-4328-b83b-aac134dee16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425680930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2425680930
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1369461140
Short name T234
Test name
Test status
Simulation time 41358245541 ps
CPU time 318.21 seconds
Started Jun 05 03:52:01 PM PDT 24
Finished Jun 05 03:57:20 PM PDT 24
Peak memory 182856 kb
Host smart-a6e2b82e-ea85-45c2-ab1e-2ced8139e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369461140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1369461140
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_random.6446366
Short name T199
Test name
Test status
Simulation time 167818346443 ps
CPU time 281.24 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:57:12 PM PDT 24
Peak memory 191080 kb
Host smart-cb08d994-d02a-417f-b996-c85478b6f8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6446366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.6446366
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.1752473342
Short name T59
Test name
Test status
Simulation time 690657316454 ps
CPU time 1131.39 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 04:11:21 PM PDT 24
Peak memory 191076 kb
Host smart-41e7b380-ceb4-4dbb-8cab-a26ef9b28e29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752473342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1752473342
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3123851029
Short name T192
Test name
Test status
Simulation time 115900534931 ps
CPU time 54.63 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:53:30 PM PDT 24
Peak memory 194332 kb
Host smart-055bf7a0-6ace-4449-8208-1e5a0dbc5734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123851029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3123851029
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1190387593
Short name T272
Test name
Test status
Simulation time 5733940517 ps
CPU time 10.5 seconds
Started Jun 05 03:52:53 PM PDT 24
Finished Jun 05 03:53:04 PM PDT 24
Peak memory 182896 kb
Host smart-6a256251-971b-4022-9650-bae298831876
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190387593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1190387593
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/62.rv_timer_random.1977118518
Short name T308
Test name
Test status
Simulation time 496405072634 ps
CPU time 515.47 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 04:01:13 PM PDT 24
Peak memory 191068 kb
Host smart-5fc9eac7-df5f-4b2b-ab08-7a77b1f48840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977118518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1977118518
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2184404773
Short name T139
Test name
Test status
Simulation time 510196159406 ps
CPU time 266.53 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 03:57:12 PM PDT 24
Peak memory 194012 kb
Host smart-bdd6a0ae-8529-4cf2-93a0-c95f04035afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184404773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2184404773
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3992936031
Short name T101
Test name
Test status
Simulation time 83782029424 ps
CPU time 139.09 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:54:54 PM PDT 24
Peak memory 191160 kb
Host smart-5eccce6e-97ee-4857-8c7f-118ddd69f8af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992936031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3992936031
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4131914015
Short name T79
Test name
Test status
Simulation time 19400434 ps
CPU time 0.84 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 182656 kb
Host smart-53250b23-ee1a-4263-a555-7bb8fd3cafaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131914015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4131914015
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3526331827
Short name T523
Test name
Test status
Simulation time 412724357 ps
CPU time 3.52 seconds
Started Jun 05 03:51:29 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 182912 kb
Host smart-82a5b815-4434-47a3-8c15-a942218cda3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526331827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3526331827
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3300250432
Short name T504
Test name
Test status
Simulation time 21696627 ps
CPU time 0.83 seconds
Started Jun 05 03:51:21 PM PDT 24
Finished Jun 05 03:51:22 PM PDT 24
Peak memory 195272 kb
Host smart-06b44284-e1dd-4908-8fa0-df5382ce434e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300250432 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3300250432
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.527445121
Short name T553
Test name
Test status
Simulation time 12239399 ps
CPU time 0.55 seconds
Started Jun 05 03:51:24 PM PDT 24
Finished Jun 05 03:51:25 PM PDT 24
Peak memory 182384 kb
Host smart-f7d5dadb-23d2-4ed3-93a2-ea6906169efc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527445121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.527445121
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1287340034
Short name T572
Test name
Test status
Simulation time 10722125 ps
CPU time 0.56 seconds
Started Jun 05 03:51:37 PM PDT 24
Finished Jun 05 03:51:38 PM PDT 24
Peak memory 182564 kb
Host smart-0fc33963-39fb-4bc8-8a99-3e1f289d5f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287340034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1287340034
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3135019883
Short name T502
Test name
Test status
Simulation time 19735760 ps
CPU time 0.59 seconds
Started Jun 05 03:51:31 PM PDT 24
Finished Jun 05 03:51:32 PM PDT 24
Peak memory 191304 kb
Host smart-70d21305-3b84-42ea-aae6-f1b4cf4da77a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135019883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3135019883
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1556763298
Short name T540
Test name
Test status
Simulation time 95297033 ps
CPU time 2.04 seconds
Started Jun 05 03:51:24 PM PDT 24
Finished Jun 05 03:51:27 PM PDT 24
Peak memory 197532 kb
Host smart-5acac3f5-a46a-4b49-9732-f0eab35553ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556763298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1556763298
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1167061858
Short name T467
Test name
Test status
Simulation time 252254787 ps
CPU time 1.06 seconds
Started Jun 05 03:51:24 PM PDT 24
Finished Jun 05 03:51:25 PM PDT 24
Peak memory 195064 kb
Host smart-056a533b-b370-4b83-9b8c-cda4da4e718f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167061858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1167061858
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3524652354
Short name T72
Test name
Test status
Simulation time 89186501 ps
CPU time 0.77 seconds
Started Jun 05 03:51:24 PM PDT 24
Finished Jun 05 03:51:26 PM PDT 24
Peak memory 192476 kb
Host smart-9b8ef3b5-4a40-4c28-86f8-d2da9102c78a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524652354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3524652354
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1694741532
Short name T472
Test name
Test status
Simulation time 231986964 ps
CPU time 1.48 seconds
Started Jun 05 03:51:30 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 191036 kb
Host smart-549e66ea-7695-4ced-81ff-1b55cc85472d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694741532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1694741532
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3129283940
Short name T485
Test name
Test status
Simulation time 14040009 ps
CPU time 0.52 seconds
Started Jun 05 03:51:24 PM PDT 24
Finished Jun 05 03:51:25 PM PDT 24
Peak memory 182204 kb
Host smart-90447c11-0c04-4cf4-805f-c9dc0bc83e94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129283940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3129283940
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2855124337
Short name T571
Test name
Test status
Simulation time 94505621 ps
CPU time 0.99 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 197152 kb
Host smart-09025a89-8418-496c-83dd-69529ac2ad8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855124337 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2855124337
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3025783471
Short name T519
Test name
Test status
Simulation time 46164956 ps
CPU time 0.58 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 182624 kb
Host smart-af184dfe-3a03-49ef-8724-87385de75561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025783471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3025783471
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3856358873
Short name T452
Test name
Test status
Simulation time 12277343 ps
CPU time 0.52 seconds
Started Jun 05 03:51:39 PM PDT 24
Finished Jun 05 03:51:41 PM PDT 24
Peak memory 182572 kb
Host smart-06060bbd-66e6-4e30-a915-270c5ae8b610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856358873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3856358873
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.321621731
Short name T83
Test name
Test status
Simulation time 36199574 ps
CPU time 0.71 seconds
Started Jun 05 03:51:28 PM PDT 24
Finished Jun 05 03:51:29 PM PDT 24
Peak memory 193104 kb
Host smart-89932fb5-8011-440a-8b51-e5d000c792a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321621731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.321621731
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1402623006
Short name T544
Test name
Test status
Simulation time 540675041 ps
CPU time 2.21 seconds
Started Jun 05 03:51:31 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 197556 kb
Host smart-dfb36cfa-9bbb-4ae0-b354-f74b8dccf87f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402623006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1402623006
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3961528822
Short name T565
Test name
Test status
Simulation time 254685555 ps
CPU time 1.32 seconds
Started Jun 05 03:51:24 PM PDT 24
Finished Jun 05 03:51:26 PM PDT 24
Peak memory 195120 kb
Host smart-1b294e9f-18e4-41fa-9c54-4210491dfcdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961528822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3961528822
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3880811898
Short name T491
Test name
Test status
Simulation time 91772901 ps
CPU time 1.24 seconds
Started Jun 05 03:51:37 PM PDT 24
Finished Jun 05 03:51:39 PM PDT 24
Peak memory 197544 kb
Host smart-2542d422-96c1-4540-8b30-4ef8b663c6f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880811898 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3880811898
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2704285719
Short name T474
Test name
Test status
Simulation time 11164855 ps
CPU time 0.55 seconds
Started Jun 05 03:51:34 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 181840 kb
Host smart-e17ecc18-72ec-4247-a64b-ea24be716559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704285719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2704285719
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3360376545
Short name T84
Test name
Test status
Simulation time 29702612 ps
CPU time 0.77 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 193292 kb
Host smart-6fe0c1f9-60b6-40f6-b12d-e319e2740bc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360376545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3360376545
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.907491270
Short name T473
Test name
Test status
Simulation time 537130171 ps
CPU time 2.3 seconds
Started Jun 05 03:51:30 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 197636 kb
Host smart-e18db65e-d782-4ea1-bb7a-817850c27835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907491270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.907491270
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2695832173
Short name T494
Test name
Test status
Simulation time 103574859 ps
CPU time 1.38 seconds
Started Jun 05 03:51:36 PM PDT 24
Finished Jun 05 03:51:38 PM PDT 24
Peak memory 197536 kb
Host smart-29a24019-a580-49fc-8c94-e89f310cf6d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695832173 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2695832173
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4231023079
Short name T68
Test name
Test status
Simulation time 18030863 ps
CPU time 0.57 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182636 kb
Host smart-c44a888e-796d-407d-b759-fab77e7c66ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231023079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4231023079
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3984265348
Short name T522
Test name
Test status
Simulation time 16647511 ps
CPU time 0.55 seconds
Started Jun 05 03:51:39 PM PDT 24
Finished Jun 05 03:51:41 PM PDT 24
Peak memory 182464 kb
Host smart-aa933537-70c5-4f58-a448-dfd68dd70627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984265348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3984265348
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3446352122
Short name T550
Test name
Test status
Simulation time 52581584 ps
CPU time 0.6 seconds
Started Jun 05 03:51:37 PM PDT 24
Finished Jun 05 03:51:38 PM PDT 24
Peak memory 191152 kb
Host smart-7ed0d261-5484-49d0-8cf6-4d4bcfac4f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446352122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3446352122
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3816698909
Short name T490
Test name
Test status
Simulation time 37218609 ps
CPU time 1.78 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 197504 kb
Host smart-27d5cfd9-23db-4eb7-ad4c-59a1b39c0fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816698909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3816698909
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2489861285
Short name T460
Test name
Test status
Simulation time 250670784 ps
CPU time 1.06 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:43 PM PDT 24
Peak memory 183700 kb
Host smart-ca28ff5a-6684-4e5d-931a-66afb161be3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489861285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2489861285
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2660614040
Short name T505
Test name
Test status
Simulation time 71209014 ps
CPU time 1.06 seconds
Started Jun 05 03:51:45 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 197644 kb
Host smart-63be392d-2ed6-42fc-830a-56240cd90851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660614040 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2660614040
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1116863008
Short name T495
Test name
Test status
Simulation time 36053595 ps
CPU time 0.54 seconds
Started Jun 05 03:51:45 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182728 kb
Host smart-cf20ef9a-e58e-4237-a599-c802fd33366a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116863008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1116863008
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1768751652
Short name T582
Test name
Test status
Simulation time 37861354 ps
CPU time 0.53 seconds
Started Jun 05 03:51:45 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 182200 kb
Host smart-ba9a5ec4-3e20-4e68-a650-e1e786798c0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768751652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1768751652
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1904117685
Short name T562
Test name
Test status
Simulation time 67364394 ps
CPU time 0.61 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 191980 kb
Host smart-2b08299e-8181-4460-a03b-060eb4e43c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904117685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1904117685
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4071455274
Short name T482
Test name
Test status
Simulation time 83694876 ps
CPU time 1.86 seconds
Started Jun 05 03:51:38 PM PDT 24
Finished Jun 05 03:51:41 PM PDT 24
Peak memory 197476 kb
Host smart-ac1db337-a537-4fc0-8d1a-e1f03ce87edc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071455274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4071455274
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.857342759
Short name T475
Test name
Test status
Simulation time 77701290 ps
CPU time 1.09 seconds
Started Jun 05 03:51:40 PM PDT 24
Finished Jun 05 03:51:42 PM PDT 24
Peak memory 195208 kb
Host smart-1558ea18-d00c-4421-ae21-b642891fc73b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857342759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.857342759
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3695590188
Short name T463
Test name
Test status
Simulation time 176294781 ps
CPU time 1.1 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 197484 kb
Host smart-f366af72-1b0f-42e3-b97e-a2f5d73645e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695590188 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3695590188
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.233360617
Short name T579
Test name
Test status
Simulation time 14671755 ps
CPU time 0.51 seconds
Started Jun 05 03:51:40 PM PDT 24
Finished Jun 05 03:51:41 PM PDT 24
Peak memory 182296 kb
Host smart-83f780d0-b0ab-41db-9198-b4735e6d7ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233360617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.233360617
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3667610195
Short name T469
Test name
Test status
Simulation time 22949137 ps
CPU time 0.55 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182092 kb
Host smart-f09868a2-633a-4b5d-8f0c-27d2bba2bb1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667610195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3667610195
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4213879849
Short name T534
Test name
Test status
Simulation time 36811479 ps
CPU time 0.63 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 191928 kb
Host smart-f7f6ff00-d051-40f9-84d4-bfc493bbc1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213879849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.4213879849
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2498347079
Short name T530
Test name
Test status
Simulation time 55407688 ps
CPU time 2.74 seconds
Started Jun 05 03:51:40 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 197464 kb
Host smart-e43fd12c-d851-46da-a111-b2574e82450a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498347079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2498347079
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.66980450
Short name T470
Test name
Test status
Simulation time 87999250 ps
CPU time 1.21 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 195220 kb
Host smart-553d6cef-f4a9-4dc7-9735-2755457dde14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66980450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_int
g_err.66980450
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4145278311
Short name T483
Test name
Test status
Simulation time 41483969 ps
CPU time 0.77 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 195796 kb
Host smart-a3411fae-05cd-4bac-8594-a026b121c832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145278311 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4145278311
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2370406663
Short name T75
Test name
Test status
Simulation time 13667536 ps
CPU time 0.52 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 182532 kb
Host smart-b230f24e-080a-440d-9a0c-d357ed451ca7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370406663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2370406663
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3441508183
Short name T535
Test name
Test status
Simulation time 47156394 ps
CPU time 0.56 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 182580 kb
Host smart-a2b9009f-4cb5-4d8d-a72c-3c170891ba4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441508183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3441508183
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1318368291
Short name T548
Test name
Test status
Simulation time 155856735 ps
CPU time 0.77 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:43 PM PDT 24
Peak memory 193268 kb
Host smart-d91f8ded-70a1-466f-9755-517a557605dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318368291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1318368291
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3920471154
Short name T484
Test name
Test status
Simulation time 161655825 ps
CPU time 1.83 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 197552 kb
Host smart-54490f25-67b1-4b00-b7fd-9596364b1f5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920471154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3920471154
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1006618772
Short name T543
Test name
Test status
Simulation time 40508688 ps
CPU time 0.71 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 194832 kb
Host smart-5da1b693-db12-42b3-97e5-ab4a2b3a0a7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006618772 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1006618772
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1410350819
Short name T76
Test name
Test status
Simulation time 40497231 ps
CPU time 0.58 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 191968 kb
Host smart-633ef5e0-a097-49c1-9b31-41530d8043e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410350819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1410350819
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2020944292
Short name T532
Test name
Test status
Simulation time 60011162 ps
CPU time 0.55 seconds
Started Jun 05 03:51:40 PM PDT 24
Finished Jun 05 03:51:42 PM PDT 24
Peak memory 182584 kb
Host smart-f0809072-ae47-4e45-8fde-921221c2dcac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020944292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2020944292
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4069265822
Short name T82
Test name
Test status
Simulation time 68783839 ps
CPU time 0.78 seconds
Started Jun 05 03:51:45 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 190900 kb
Host smart-3633e02a-7d66-48d5-bf8e-d77d0f8830ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069265822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4069265822
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.16807418
Short name T563
Test name
Test status
Simulation time 195269611 ps
CPU time 1.22 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 197332 kb
Host smart-1ea4edd9-9a58-4513-9b30-86f318af1330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.16807418
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.750695037
Short name T558
Test name
Test status
Simulation time 128160887 ps
CPU time 1.04 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 195176 kb
Host smart-f1b22a31-c9d3-44e7-81ad-f1d5bc758aad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750695037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.750695037
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2934959521
Short name T455
Test name
Test status
Simulation time 14893931 ps
CPU time 0.72 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 194632 kb
Host smart-659b08a9-8e1d-4d1a-b813-25e1bf96eafb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934959521 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2934959521
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2364340500
Short name T539
Test name
Test status
Simulation time 13272812 ps
CPU time 0.55 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 182628 kb
Host smart-545c10bb-c069-495f-a016-65efda9deea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364340500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2364340500
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.384916824
Short name T574
Test name
Test status
Simulation time 14720324 ps
CPU time 0.53 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 182548 kb
Host smart-23984198-9d93-47b5-8d2b-4e23c15137ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384916824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.384916824
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.275173133
Short name T70
Test name
Test status
Simulation time 44236846 ps
CPU time 0.82 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 191736 kb
Host smart-4d849744-1946-420f-974e-26804164415e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275173133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.275173133
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3045696847
Short name T508
Test name
Test status
Simulation time 105728882 ps
CPU time 1.16 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:51 PM PDT 24
Peak memory 197264 kb
Host smart-878fd61a-558b-4a1e-a73c-c445504a2c9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045696847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3045696847
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.854698643
Short name T96
Test name
Test status
Simulation time 533676707 ps
CPU time 1.09 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 195084 kb
Host smart-cf5b9e4c-294a-4f86-af96-3e311a3db459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854698643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.854698643
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.906355308
Short name T547
Test name
Test status
Simulation time 111310754 ps
CPU time 0.65 seconds
Started Jun 05 03:51:42 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 194492 kb
Host smart-0e66c174-39f9-48c7-a1a9-660f6ec69665
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906355308 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.906355308
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.154085702
Short name T557
Test name
Test status
Simulation time 13189491 ps
CPU time 0.54 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182448 kb
Host smart-99c86038-2d09-4c8f-abfe-45afcce28b83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154085702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.154085702
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2003213106
Short name T459
Test name
Test status
Simulation time 16054097 ps
CPU time 0.58 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182168 kb
Host smart-34bf3ba1-8be9-4217-9193-9e383b6564f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003213106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2003213106
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3564686109
Short name T545
Test name
Test status
Simulation time 93285394 ps
CPU time 0.71 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 191772 kb
Host smart-1ece99e0-4357-49ce-b840-5f47c4f323f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564686109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3564686109
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2541216752
Short name T517
Test name
Test status
Simulation time 727220582 ps
CPU time 3.02 seconds
Started Jun 05 03:51:45 PM PDT 24
Finished Jun 05 03:51:50 PM PDT 24
Peak memory 197628 kb
Host smart-095802c2-3cba-4199-9fab-4c6f0299e448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541216752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2541216752
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.938488297
Short name T456
Test name
Test status
Simulation time 167321479 ps
CPU time 0.79 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:43 PM PDT 24
Peak memory 193436 kb
Host smart-bcbd4586-fe26-4d2b-a4ec-2f6a71616f88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938488297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.938488297
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4223596412
Short name T488
Test name
Test status
Simulation time 17346688 ps
CPU time 0.6 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 192952 kb
Host smart-e3eb3c8f-7ca0-4879-9842-48eed0c4f5ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223596412 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4223596412
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1507292002
Short name T503
Test name
Test status
Simulation time 27952882 ps
CPU time 0.55 seconds
Started Jun 05 03:51:46 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182748 kb
Host smart-3ff11b0c-09ea-4a47-9e93-0459bf8cfef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507292002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1507292002
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2686504159
Short name T583
Test name
Test status
Simulation time 29521882 ps
CPU time 0.54 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182772 kb
Host smart-6fc91336-84d7-4c7b-9d32-46c26b83cc30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686504159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2686504159
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3476781380
Short name T560
Test name
Test status
Simulation time 65578325 ps
CPU time 0.78 seconds
Started Jun 05 03:51:45 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 193184 kb
Host smart-246c4e45-022a-4ef4-9c6c-8b9212c7a001
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476781380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3476781380
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2060501813
Short name T477
Test name
Test status
Simulation time 191844816 ps
CPU time 2.45 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 197520 kb
Host smart-747f3be3-119c-41f0-883d-ac5a3f01e23c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060501813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2060501813
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1407275458
Short name T27
Test name
Test status
Simulation time 114234538 ps
CPU time 1.36 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 195364 kb
Host smart-8f4615a7-f155-4de9-b305-331deb5b725c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407275458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1407275458
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3808771932
Short name T514
Test name
Test status
Simulation time 54122554 ps
CPU time 1.27 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 197624 kb
Host smart-c3976e37-970a-40d9-80d3-9dd31d3109af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808771932 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3808771932
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3311472216
Short name T506
Test name
Test status
Simulation time 68922143 ps
CPU time 0.6 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182752 kb
Host smart-68297f52-75e0-436e-95a3-9aca44cb4dee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311472216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3311472216
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3390183195
Short name T567
Test name
Test status
Simulation time 15067774 ps
CPU time 0.56 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182664 kb
Host smart-eacd896a-a476-4604-8f76-e489aba62d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390183195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3390183195
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2753964112
Short name T531
Test name
Test status
Simulation time 19909772 ps
CPU time 0.65 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 191164 kb
Host smart-129087dd-34d8-4aba-a91e-f50fde3d333b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753964112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2753964112
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1233704929
Short name T549
Test name
Test status
Simulation time 278826713 ps
CPU time 1.13 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 197408 kb
Host smart-d23be638-86b3-41e6-a6cf-bdc6adebdb57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233704929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1233704929
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.183126713
Short name T497
Test name
Test status
Simulation time 199855279 ps
CPU time 0.79 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 193820 kb
Host smart-900abd63-afb9-431e-a2cc-1c99c77ba4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183126713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.183126713
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1301016035
Short name T78
Test name
Test status
Simulation time 30781630 ps
CPU time 0.83 seconds
Started Jun 05 03:51:30 PM PDT 24
Finished Jun 05 03:51:32 PM PDT 24
Peak memory 192492 kb
Host smart-ef1e2023-2c2f-4ad1-8d1c-21d02c032ff8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301016035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1301016035
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.578195156
Short name T29
Test name
Test status
Simulation time 1326287101 ps
CPU time 3.57 seconds
Started Jun 05 03:51:36 PM PDT 24
Finished Jun 05 03:51:41 PM PDT 24
Peak memory 193764 kb
Host smart-853adb45-e844-4892-830d-e81a883f59a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578195156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.578195156
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.916743276
Short name T458
Test name
Test status
Simulation time 13598590 ps
CPU time 0.55 seconds
Started Jun 05 03:51:34 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 182628 kb
Host smart-7be8118f-87e3-4c72-b856-654d8b6155be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916743276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.916743276
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3542366608
Short name T561
Test name
Test status
Simulation time 142893128 ps
CPU time 1 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 196404 kb
Host smart-368b7e5f-d941-44d7-915a-84495bc3c3e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542366608 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3542366608
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3346386856
Short name T568
Test name
Test status
Simulation time 117887689 ps
CPU time 0.6 seconds
Started Jun 05 03:51:36 PM PDT 24
Finished Jun 05 03:51:38 PM PDT 24
Peak memory 191796 kb
Host smart-acaa365c-d289-46d9-9e5f-e89273038be8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346386856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3346386856
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1752911711
Short name T515
Test name
Test status
Simulation time 12778750 ps
CPU time 0.54 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 182480 kb
Host smart-1b0895b6-5d1d-45e8-8d0a-96d33f7186be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752911711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1752911711
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1286352741
Short name T69
Test name
Test status
Simulation time 114137447 ps
CPU time 0.77 seconds
Started Jun 05 03:51:38 PM PDT 24
Finished Jun 05 03:51:40 PM PDT 24
Peak memory 193248 kb
Host smart-e523a4f1-1645-49d2-9e66-d10b7bb9d27e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286352741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1286352741
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2049759477
Short name T554
Test name
Test status
Simulation time 247900922 ps
CPU time 2.31 seconds
Started Jun 05 03:51:30 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 197844 kb
Host smart-b81aeda3-225b-423f-ae71-af1c1866e6c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049759477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2049759477
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.832014082
Short name T464
Test name
Test status
Simulation time 148642826 ps
CPU time 1.15 seconds
Started Jun 05 03:51:34 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 183176 kb
Host smart-8ce467a5-9b0b-473a-98ec-e2a38e5f5b4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832014082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.832014082
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2609142386
Short name T462
Test name
Test status
Simulation time 43343781 ps
CPU time 0.56 seconds
Started Jun 05 03:51:46 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182476 kb
Host smart-4a332d43-27e2-4e63-b97d-ade108db706a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609142386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2609142386
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3485233514
Short name T536
Test name
Test status
Simulation time 23663253 ps
CPU time 0.56 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 181984 kb
Host smart-07f4923d-54e2-498f-83b6-1d026f4df0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485233514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3485233514
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1624465121
Short name T566
Test name
Test status
Simulation time 17097193 ps
CPU time 0.54 seconds
Started Jun 05 03:51:45 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 182500 kb
Host smart-7efdee07-4f0e-4137-8cf7-9178ebe55e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624465121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1624465121
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3596600268
Short name T451
Test name
Test status
Simulation time 43983307 ps
CPU time 0.54 seconds
Started Jun 05 03:51:47 PM PDT 24
Finished Jun 05 03:51:49 PM PDT 24
Peak memory 182648 kb
Host smart-aed275d4-271b-4ba0-818a-387edfd7c8cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596600268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3596600268
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2619081009
Short name T518
Test name
Test status
Simulation time 41196386 ps
CPU time 0.57 seconds
Started Jun 05 03:51:48 PM PDT 24
Finished Jun 05 03:51:50 PM PDT 24
Peak memory 182464 kb
Host smart-1d9ed3d3-b0d2-469a-bdc7-30dde0b16edf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619081009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2619081009
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2241540905
Short name T457
Test name
Test status
Simulation time 14606949 ps
CPU time 0.56 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:45 PM PDT 24
Peak memory 182572 kb
Host smart-84b5c65f-b020-40d6-bc48-fdbbd55a2676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241540905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2241540905
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4206283264
Short name T577
Test name
Test status
Simulation time 28518299 ps
CPU time 0.55 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182572 kb
Host smart-37c4f4bc-7992-44b7-90dc-eae98adcba44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206283264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.4206283264
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1426577288
Short name T468
Test name
Test status
Simulation time 70127081 ps
CPU time 0.56 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 182540 kb
Host smart-843ba86f-c771-48ec-bb8a-d860c0ce9b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426577288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1426577288
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.984525632
Short name T492
Test name
Test status
Simulation time 16754468 ps
CPU time 0.56 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182584 kb
Host smart-fe7decb3-1604-4a3e-ac42-fc767cb0db62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984525632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.984525632
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2008541914
Short name T487
Test name
Test status
Simulation time 15579598 ps
CPU time 0.56 seconds
Started Jun 05 03:51:48 PM PDT 24
Finished Jun 05 03:51:50 PM PDT 24
Peak memory 182684 kb
Host smart-e288d3c8-03ad-48d6-ae00-108a397a2cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008541914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2008541914
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2005642635
Short name T461
Test name
Test status
Simulation time 55421252 ps
CPU time 0.7 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 182620 kb
Host smart-f8421353-76ba-43c7-bd58-126fa7159334
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005642635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2005642635
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1165925074
Short name T65
Test name
Test status
Simulation time 128052005 ps
CPU time 2.38 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:44 PM PDT 24
Peak memory 191028 kb
Host smart-ebd694f2-9ce4-4d53-9d32-a7622b57ea79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165925074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1165925074
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1860556226
Short name T511
Test name
Test status
Simulation time 15581470 ps
CPU time 0.59 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 182620 kb
Host smart-42cd3a91-6e35-45b8-a9e7-0f5c52c4429d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860556226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1860556226
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.781446790
Short name T476
Test name
Test status
Simulation time 18762638 ps
CPU time 0.64 seconds
Started Jun 05 03:51:29 PM PDT 24
Finished Jun 05 03:51:30 PM PDT 24
Peak memory 193688 kb
Host smart-d46f1ea1-f1e2-4d19-9319-2122a631c453
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781446790 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.781446790
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3385749205
Short name T71
Test name
Test status
Simulation time 21306222 ps
CPU time 0.56 seconds
Started Jun 05 03:51:37 PM PDT 24
Finished Jun 05 03:51:38 PM PDT 24
Peak memory 182740 kb
Host smart-650edf60-01d9-42fc-8e1b-74d433348f30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385749205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3385749205
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2637683348
Short name T537
Test name
Test status
Simulation time 16722357 ps
CPU time 0.62 seconds
Started Jun 05 03:51:36 PM PDT 24
Finished Jun 05 03:51:37 PM PDT 24
Peak memory 182556 kb
Host smart-caeb92a5-fe96-4ab7-8f2e-62457d882c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637683348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2637683348
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3449879702
Short name T564
Test name
Test status
Simulation time 38097639 ps
CPU time 0.88 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:43 PM PDT 24
Peak memory 190884 kb
Host smart-3d640a86-1ca9-4e3e-831f-3eec8c35a824
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449879702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3449879702
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.25667548
Short name T559
Test name
Test status
Simulation time 29352984 ps
CPU time 1.31 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 197448 kb
Host smart-e19c03ba-9b1c-4d85-a851-8486fd226999
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25667548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.25667548
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2815351373
Short name T98
Test name
Test status
Simulation time 350066361 ps
CPU time 1.07 seconds
Started Jun 05 03:51:31 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 195004 kb
Host smart-b8150d05-02cd-4fb1-be93-692568aebaf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815351373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2815351373
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2437040589
Short name T466
Test name
Test status
Simulation time 46746956 ps
CPU time 0.52 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 182524 kb
Host smart-a5b2fe3f-1ca0-4b2a-a0e5-6d783a90d0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437040589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2437040589
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2217733687
Short name T510
Test name
Test status
Simulation time 14337877 ps
CPU time 0.54 seconds
Started Jun 05 03:51:55 PM PDT 24
Finished Jun 05 03:51:56 PM PDT 24
Peak memory 182576 kb
Host smart-0c6a88df-d27f-4170-81cb-8ed4f71461a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217733687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2217733687
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1149294902
Short name T525
Test name
Test status
Simulation time 12276862 ps
CPU time 0.54 seconds
Started Jun 05 03:51:47 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182620 kb
Host smart-6f0aae85-6829-4ff2-9099-58a90e30e043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149294902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1149294902
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.686828769
Short name T501
Test name
Test status
Simulation time 23098754 ps
CPU time 0.53 seconds
Started Jun 05 03:51:46 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182164 kb
Host smart-d7271c32-9f1e-4580-a799-bfa411507509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686828769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.686828769
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.658664183
Short name T570
Test name
Test status
Simulation time 25152710 ps
CPU time 0.54 seconds
Started Jun 05 03:51:47 PM PDT 24
Finished Jun 05 03:51:49 PM PDT 24
Peak memory 182596 kb
Host smart-ed13d8af-6ead-45d0-829e-102d2be4ee00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658664183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.658664183
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1099657288
Short name T512
Test name
Test status
Simulation time 16042159 ps
CPU time 0.56 seconds
Started Jun 05 03:51:44 PM PDT 24
Finished Jun 05 03:51:47 PM PDT 24
Peak memory 182632 kb
Host smart-df8a72a3-0ce8-485c-a167-a43885e8aeaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099657288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1099657288
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2422998237
Short name T499
Test name
Test status
Simulation time 15720734 ps
CPU time 0.56 seconds
Started Jun 05 03:51:46 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182608 kb
Host smart-08725e76-6208-40bf-ae51-a196a503c8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422998237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2422998237
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1104792654
Short name T551
Test name
Test status
Simulation time 15503176 ps
CPU time 0.55 seconds
Started Jun 05 03:51:49 PM PDT 24
Finished Jun 05 03:51:50 PM PDT 24
Peak memory 182508 kb
Host smart-b28897a9-1212-44d1-a960-70ad02397bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104792654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1104792654
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3339012362
Short name T529
Test name
Test status
Simulation time 12074513 ps
CPU time 0.53 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 03:51:51 PM PDT 24
Peak memory 182180 kb
Host smart-e40f89cd-5229-4e5d-90d6-af8f8e3dc7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339012362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3339012362
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1010803149
Short name T453
Test name
Test status
Simulation time 10711048 ps
CPU time 0.54 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:51:53 PM PDT 24
Peak memory 182088 kb
Host smart-72f7c04a-e609-4e23-953a-13bfa06687b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010803149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1010803149
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2766259185
Short name T575
Test name
Test status
Simulation time 66650495 ps
CPU time 0.64 seconds
Started Jun 05 03:51:38 PM PDT 24
Finished Jun 05 03:51:39 PM PDT 24
Peak memory 182612 kb
Host smart-3b0c766a-b5b8-4c54-9689-234de2c64fe9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766259185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2766259185
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2915211299
Short name T80
Test name
Test status
Simulation time 827669639 ps
CPU time 1.71 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 191032 kb
Host smart-a592dcc2-019c-4874-8719-3d360558742f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915211299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2915211299
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3568833336
Short name T81
Test name
Test status
Simulation time 98295211 ps
CPU time 0.59 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 182744 kb
Host smart-8bb84b99-bd50-4808-89c0-3af2d155e638
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568833336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3568833336
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1790329482
Short name T555
Test name
Test status
Simulation time 95404416 ps
CPU time 1.17 seconds
Started Jun 05 03:51:38 PM PDT 24
Finished Jun 05 03:51:41 PM PDT 24
Peak memory 197280 kb
Host smart-abf378c6-54f2-44c9-b42d-dc9f6c85942d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790329482 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1790329482
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1936073084
Short name T77
Test name
Test status
Simulation time 43967677 ps
CPU time 0.63 seconds
Started Jun 05 03:51:31 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 182628 kb
Host smart-99e8dd07-c8cb-4ab8-820c-3434a7feac1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936073084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1936073084
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3498150162
Short name T465
Test name
Test status
Simulation time 124133026 ps
CPU time 0.55 seconds
Started Jun 05 03:51:29 PM PDT 24
Finished Jun 05 03:51:30 PM PDT 24
Peak memory 182516 kb
Host smart-2fe8b989-910f-4b45-b117-727aa9304e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498150162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3498150162
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.472554414
Short name T66
Test name
Test status
Simulation time 21621041 ps
CPU time 0.6 seconds
Started Jun 05 03:51:34 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 191484 kb
Host smart-836da08c-b367-43e3-b9ad-d1319948f83f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472554414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.472554414
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4290581231
Short name T513
Test name
Test status
Simulation time 199275473 ps
CPU time 3.18 seconds
Started Jun 05 03:51:35 PM PDT 24
Finished Jun 05 03:51:39 PM PDT 24
Peak memory 197496 kb
Host smart-5d24b20c-7f70-4103-af27-c701690fb768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290581231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.4290581231
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3776020052
Short name T95
Test name
Test status
Simulation time 173232668 ps
CPU time 1.32 seconds
Started Jun 05 03:51:38 PM PDT 24
Finished Jun 05 03:51:41 PM PDT 24
Peak memory 194592 kb
Host smart-3bb0d6e5-2b07-4fd4-b268-a167af20c741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776020052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3776020052
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3468493808
Short name T496
Test name
Test status
Simulation time 52882790 ps
CPU time 0.57 seconds
Started Jun 05 03:51:47 PM PDT 24
Finished Jun 05 03:51:49 PM PDT 24
Peak memory 182548 kb
Host smart-dec434fd-30a2-4f93-8c8e-cef2b8fafca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468493808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3468493808
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1566301608
Short name T542
Test name
Test status
Simulation time 34614081 ps
CPU time 0.57 seconds
Started Jun 05 03:51:45 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182564 kb
Host smart-6e1cea64-970d-44dd-97a5-03a7b6f51905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566301608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1566301608
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2385972615
Short name T478
Test name
Test status
Simulation time 33917567 ps
CPU time 0.62 seconds
Started Jun 05 03:51:47 PM PDT 24
Finished Jun 05 03:51:49 PM PDT 24
Peak memory 182640 kb
Host smart-b7010a35-c78a-43aa-b236-1cc1bfdf469a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385972615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2385972615
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1734558625
Short name T556
Test name
Test status
Simulation time 28658290 ps
CPU time 0.57 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 03:51:51 PM PDT 24
Peak memory 182604 kb
Host smart-9942a63c-bdc4-4ef8-9068-d90decc2ff2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734558625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1734558625
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1812232884
Short name T569
Test name
Test status
Simulation time 108387914 ps
CPU time 0.58 seconds
Started Jun 05 03:51:47 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182556 kb
Host smart-a6b54ca2-57f1-45ab-b946-62227d7ed266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812232884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1812232884
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1219674518
Short name T584
Test name
Test status
Simulation time 14672250 ps
CPU time 0.55 seconds
Started Jun 05 03:51:49 PM PDT 24
Finished Jun 05 03:51:50 PM PDT 24
Peak memory 182600 kb
Host smart-5f3b0446-c848-43af-8ceb-5c990ddffda7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219674518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1219674518
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2515355843
Short name T521
Test name
Test status
Simulation time 17148934 ps
CPU time 0.52 seconds
Started Jun 05 03:51:54 PM PDT 24
Finished Jun 05 03:51:55 PM PDT 24
Peak memory 182160 kb
Host smart-584ff913-97c8-4c66-9480-b5bd5be934f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515355843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2515355843
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2967695705
Short name T580
Test name
Test status
Simulation time 26490008 ps
CPU time 0.55 seconds
Started Jun 05 03:51:46 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182648 kb
Host smart-fbc0b535-cddb-48a9-9f70-eb06c28307a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967695705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2967695705
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3550216601
Short name T479
Test name
Test status
Simulation time 16621885 ps
CPU time 0.55 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:51:53 PM PDT 24
Peak memory 182588 kb
Host smart-3cf61ca6-b764-4cbd-a294-4e693f4e498f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550216601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3550216601
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2248789252
Short name T538
Test name
Test status
Simulation time 16164380 ps
CPU time 0.55 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:51:53 PM PDT 24
Peak memory 182600 kb
Host smart-46408b25-f985-4749-95d4-3074c3dc76e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248789252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2248789252
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4127263503
Short name T526
Test name
Test status
Simulation time 87163775 ps
CPU time 0.79 seconds
Started Jun 05 03:51:31 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 196068 kb
Host smart-f8f56026-2bc5-48ca-8799-adca5e664628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127263503 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.4127263503
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2738816228
Short name T48
Test name
Test status
Simulation time 49868996 ps
CPU time 0.56 seconds
Started Jun 05 03:51:36 PM PDT 24
Finished Jun 05 03:51:38 PM PDT 24
Peak memory 182624 kb
Host smart-6c8b2f17-9c33-4b51-b1b0-644a3c6ccda8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738816228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2738816228
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1918090936
Short name T520
Test name
Test status
Simulation time 74199207 ps
CPU time 0.57 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 182524 kb
Host smart-9469b25c-71f1-4eb9-9bbe-08fd5571153f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918090936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1918090936
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.4166715422
Short name T524
Test name
Test status
Simulation time 20634453 ps
CPU time 0.64 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 191976 kb
Host smart-c3d3dd3e-9b1e-4afc-811c-86143beea11b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166715422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.4166715422
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2439544409
Short name T486
Test name
Test status
Simulation time 905495439 ps
CPU time 2.99 seconds
Started Jun 05 03:51:30 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 197548 kb
Host smart-0d60cb67-05d4-4fc0-8245-6cd1d2246d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439544409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2439544409
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1581030288
Short name T581
Test name
Test status
Simulation time 681890746 ps
CPU time 1.41 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 195484 kb
Host smart-01b5624d-639b-45d3-bf6c-1020cf2d94cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581030288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1581030288
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2991184282
Short name T528
Test name
Test status
Simulation time 19324617 ps
CPU time 0.74 seconds
Started Jun 05 03:51:39 PM PDT 24
Finished Jun 05 03:51:41 PM PDT 24
Peak memory 194300 kb
Host smart-5e1a840b-f8b5-4aa3-8507-581f3554208c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991184282 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2991184282
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1473081837
Short name T74
Test name
Test status
Simulation time 21865773 ps
CPU time 0.59 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 191840 kb
Host smart-0e9375df-bfd5-42cb-b0d2-d815a2f157d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473081837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1473081837
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1542370832
Short name T489
Test name
Test status
Simulation time 12887786 ps
CPU time 0.54 seconds
Started Jun 05 03:51:27 PM PDT 24
Finished Jun 05 03:51:28 PM PDT 24
Peak memory 182292 kb
Host smart-2a316213-cc6f-43ac-a6c6-661a76abc67b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542370832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1542370832
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.206248701
Short name T85
Test name
Test status
Simulation time 52055591 ps
CPU time 0.71 seconds
Started Jun 05 03:51:31 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 192192 kb
Host smart-9ca90ae8-affc-4ad7-8c16-8e1e5d0d911a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206248701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.206248701
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2762920830
Short name T509
Test name
Test status
Simulation time 82782008 ps
CPU time 1.45 seconds
Started Jun 05 03:51:37 PM PDT 24
Finished Jun 05 03:51:40 PM PDT 24
Peak memory 197660 kb
Host smart-0cf7c5ce-c4ca-464f-a100-5bff15cb16e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762920830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2762920830
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4019461626
Short name T99
Test name
Test status
Simulation time 380584187 ps
CPU time 1.33 seconds
Started Jun 05 03:51:36 PM PDT 24
Finished Jun 05 03:51:39 PM PDT 24
Peak memory 183136 kb
Host smart-9f705c16-eccb-417e-b730-d6104b2c319e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019461626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.4019461626
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1023567136
Short name T527
Test name
Test status
Simulation time 31550240 ps
CPU time 0.79 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 194564 kb
Host smart-e6cc40d3-5a1b-408b-810a-7ac8292c1dba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023567136 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1023567136
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.187501267
Short name T500
Test name
Test status
Simulation time 19209192 ps
CPU time 0.62 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 182628 kb
Host smart-523eafbe-4dfe-40e7-b10a-2a2e93c28f37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187501267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.187501267
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1610191948
Short name T471
Test name
Test status
Simulation time 47249275 ps
CPU time 0.54 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:35 PM PDT 24
Peak memory 182516 kb
Host smart-0cbd1d8e-3202-4173-a424-dd8102fcaa7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610191948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1610191948
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3681868715
Short name T578
Test name
Test status
Simulation time 39708859 ps
CPU time 0.74 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:43 PM PDT 24
Peak memory 194040 kb
Host smart-33612e88-f1bc-4baa-89d2-cd6c837efa50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681868715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3681868715
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1688890720
Short name T552
Test name
Test status
Simulation time 176507478 ps
CPU time 1.78 seconds
Started Jun 05 03:51:30 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 197644 kb
Host smart-db179a74-e804-40dd-9368-995337c7d547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688890720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1688890720
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1739757080
Short name T541
Test name
Test status
Simulation time 294540061 ps
CPU time 0.79 seconds
Started Jun 05 03:51:29 PM PDT 24
Finished Jun 05 03:51:31 PM PDT 24
Peak memory 182936 kb
Host smart-9c854cc9-0dc8-4288-b72a-11a6183d6f23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739757080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1739757080
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2601689473
Short name T516
Test name
Test status
Simulation time 81945199 ps
CPU time 1.21 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 197468 kb
Host smart-c2284519-c499-4c17-a303-9f320d510a39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601689473 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2601689473
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1155620649
Short name T576
Test name
Test status
Simulation time 12182721 ps
CPU time 0.58 seconds
Started Jun 05 03:51:43 PM PDT 24
Finished Jun 05 03:51:46 PM PDT 24
Peak memory 182628 kb
Host smart-f11c91f8-4161-4c83-8b31-261fe0c741cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155620649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1155620649
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3392076571
Short name T546
Test name
Test status
Simulation time 18481480 ps
CPU time 0.58 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 182488 kb
Host smart-a65ed5f6-3e7a-4944-b226-37217c7a8723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392076571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3392076571
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.433179508
Short name T533
Test name
Test status
Simulation time 19043018 ps
CPU time 0.6 seconds
Started Jun 05 03:51:41 PM PDT 24
Finished Jun 05 03:51:43 PM PDT 24
Peak memory 192204 kb
Host smart-4e28fb6a-033c-41c1-86cd-77367d6c0ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433179508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.433179508
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1899024374
Short name T498
Test name
Test status
Simulation time 230331113 ps
CPU time 2.15 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 197632 kb
Host smart-2ce1f4e1-79d3-4453-9145-73fbd20f36f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899024374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1899024374
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2480799033
Short name T28
Test name
Test status
Simulation time 459378584 ps
CPU time 1.31 seconds
Started Jun 05 03:51:30 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 183284 kb
Host smart-75198d00-161f-4261-9b2c-42a05efc7511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480799033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2480799033
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3859590304
Short name T493
Test name
Test status
Simulation time 103416372 ps
CPU time 0.87 seconds
Started Jun 05 03:51:37 PM PDT 24
Finished Jun 05 03:51:40 PM PDT 24
Peak memory 196744 kb
Host smart-a3b60a22-77f0-4b29-b4fc-30cce48e3f05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859590304 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3859590304
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.797744160
Short name T480
Test name
Test status
Simulation time 12470684 ps
CPU time 0.53 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:33 PM PDT 24
Peak memory 182252 kb
Host smart-caa963d3-c4a4-4667-a9eb-5bf87c6df0b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797744160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.797744160
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3244203113
Short name T507
Test name
Test status
Simulation time 15247492 ps
CPU time 0.56 seconds
Started Jun 05 03:51:32 PM PDT 24
Finished Jun 05 03:51:34 PM PDT 24
Peak memory 182732 kb
Host smart-f055f37c-baa0-4c03-8646-2566c42cccc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244203113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3244203113
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1073400598
Short name T573
Test name
Test status
Simulation time 27059160 ps
CPU time 0.71 seconds
Started Jun 05 03:51:29 PM PDT 24
Finished Jun 05 03:51:30 PM PDT 24
Peak memory 192216 kb
Host smart-5fc451d5-b668-47d6-b028-f2632eee81df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073400598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1073400598
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3626546887
Short name T454
Test name
Test status
Simulation time 50350882 ps
CPU time 2.17 seconds
Started Jun 05 03:51:33 PM PDT 24
Finished Jun 05 03:51:36 PM PDT 24
Peak memory 197536 kb
Host smart-42de196b-8147-4a92-abc6-f003d5347a90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626546887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3626546887
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1166704346
Short name T481
Test name
Test status
Simulation time 84054054 ps
CPU time 1.16 seconds
Started Jun 05 03:51:34 PM PDT 24
Finished Jun 05 03:51:37 PM PDT 24
Peak memory 194732 kb
Host smart-7b461462-2ba3-467c-a121-abbee8d3ff7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166704346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1166704346
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.66724657
Short name T316
Test name
Test status
Simulation time 25625534395 ps
CPU time 46.69 seconds
Started Jun 05 03:51:58 PM PDT 24
Finished Jun 05 03:52:45 PM PDT 24
Peak memory 182868 kb
Host smart-8aad4170-0695-4a6b-87a8-d34c39496414
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66724657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
rv_timer_cfg_update_on_fly.66724657
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.4218610814
Short name T414
Test name
Test status
Simulation time 20244554387 ps
CPU time 28.33 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:52:20 PM PDT 24
Peak memory 182996 kb
Host smart-8f41d04a-f022-43dd-8fce-910432539bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218610814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4218610814
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2785071558
Short name T146
Test name
Test status
Simulation time 70616896399 ps
CPU time 128.56 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:54:01 PM PDT 24
Peak memory 191172 kb
Host smart-61f75dcd-af8b-43f5-8a8a-59b18c2afab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785071558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2785071558
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1127086806
Short name T386
Test name
Test status
Simulation time 73154603244 ps
CPU time 34.54 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:52:26 PM PDT 24
Peak memory 191160 kb
Host smart-5715174c-7776-42e3-bbef-acb071f7268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127086806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1127086806
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1449041262
Short name T191
Test name
Test status
Simulation time 83405150864 ps
CPU time 83.42 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:53:15 PM PDT 24
Peak memory 182868 kb
Host smart-4c6ae8d5-be8a-47b2-95f4-e7fb532e143e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449041262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1449041262
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2483077569
Short name T90
Test name
Test status
Simulation time 356827080941 ps
CPU time 153.27 seconds
Started Jun 05 03:51:52 PM PDT 24
Finished Jun 05 03:54:26 PM PDT 24
Peak memory 182976 kb
Host smart-a382675a-6ec9-44ce-8438-1a42a5ccc61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483077569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2483077569
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.346235989
Short name T183
Test name
Test status
Simulation time 72661901510 ps
CPU time 98.71 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 195036 kb
Host smart-e4710885-f26b-42d0-ad8d-f439c6396c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346235989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.346235989
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1497137915
Short name T205
Test name
Test status
Simulation time 222601828316 ps
CPU time 117.04 seconds
Started Jun 05 03:51:55 PM PDT 24
Finished Jun 05 03:53:52 PM PDT 24
Peak memory 191084 kb
Host smart-8ea55c8f-bb95-4311-b3ef-0edecded1abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497137915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1497137915
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2637467473
Short name T17
Test name
Test status
Simulation time 311618898 ps
CPU time 0.74 seconds
Started Jun 05 03:51:49 PM PDT 24
Finished Jun 05 03:51:51 PM PDT 24
Peak memory 213884 kb
Host smart-a82dab45-efce-43dc-b990-8ced7aebbe70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637467473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2637467473
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3146071408
Short name T51
Test name
Test status
Simulation time 37085814 ps
CPU time 0.58 seconds
Started Jun 05 03:51:46 PM PDT 24
Finished Jun 05 03:51:48 PM PDT 24
Peak memory 182644 kb
Host smart-1b0e5818-4167-4091-9075-1fb12d586131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146071408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3146071408
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3665831815
Short name T13
Test name
Test status
Simulation time 52920000340 ps
CPU time 387.33 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 03:58:18 PM PDT 24
Peak memory 205836 kb
Host smart-83a3f9b9-7a0e-477a-92af-c950dc7f2bbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665831815 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3665831815
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3814240952
Short name T204
Test name
Test status
Simulation time 55058697182 ps
CPU time 95.31 seconds
Started Jun 05 03:52:09 PM PDT 24
Finished Jun 05 03:53:45 PM PDT 24
Peak memory 183012 kb
Host smart-ecc71a64-eddd-4baa-ac09-56ad1d6669df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814240952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3814240952
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2049142216
Short name T420
Test name
Test status
Simulation time 176218943829 ps
CPU time 283.56 seconds
Started Jun 05 03:52:05 PM PDT 24
Finished Jun 05 03:56:50 PM PDT 24
Peak memory 182600 kb
Host smart-58596977-1b60-4bc3-adda-1d544ba2b8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049142216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2049142216
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2280088381
Short name T321
Test name
Test status
Simulation time 8584306676 ps
CPU time 11.79 seconds
Started Jun 05 03:51:59 PM PDT 24
Finished Jun 05 03:52:11 PM PDT 24
Peak memory 182976 kb
Host smart-4b50f456-0d3e-43e7-9940-8ea741935945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280088381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2280088381
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3959848433
Short name T178
Test name
Test status
Simulation time 420226877030 ps
CPU time 242.5 seconds
Started Jun 05 03:52:13 PM PDT 24
Finished Jun 05 03:56:16 PM PDT 24
Peak memory 191092 kb
Host smart-788f5d0f-91b0-485d-9f84-ecdb14fdb3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959848433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3959848433
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3772925451
Short name T210
Test name
Test status
Simulation time 170668323236 ps
CPU time 800.94 seconds
Started Jun 05 03:52:08 PM PDT 24
Finished Jun 05 04:05:30 PM PDT 24
Peak memory 191184 kb
Host smart-93701636-3d16-4a51-a595-956cb5b45b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772925451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3772925451
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.2348530219
Short name T156
Test name
Test status
Simulation time 691320798804 ps
CPU time 744.94 seconds
Started Jun 05 03:52:41 PM PDT 24
Finished Jun 05 04:05:07 PM PDT 24
Peak memory 191068 kb
Host smart-39d7b847-5ce7-4594-a386-4b13584635b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348530219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2348530219
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.601323569
Short name T327
Test name
Test status
Simulation time 601020575134 ps
CPU time 407.79 seconds
Started Jun 05 03:52:47 PM PDT 24
Finished Jun 05 03:59:35 PM PDT 24
Peak memory 191184 kb
Host smart-91a8fc6f-0635-403c-a9ee-b864bf34194b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601323569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.601323569
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3659556542
Short name T185
Test name
Test status
Simulation time 215907845717 ps
CPU time 393.57 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:59:09 PM PDT 24
Peak memory 191072 kb
Host smart-01655dd9-913d-4e44-8fed-ae8eecda5bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659556542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3659556542
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2871068604
Short name T167
Test name
Test status
Simulation time 169035522436 ps
CPU time 508.11 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 04:01:06 PM PDT 24
Peak memory 191048 kb
Host smart-86861059-436b-4450-b4ef-a7da76a0d090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871068604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2871068604
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1557675623
Short name T112
Test name
Test status
Simulation time 510542737296 ps
CPU time 204.9 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 03:56:02 PM PDT 24
Peak memory 191072 kb
Host smart-7b2aa353-2331-4c7e-926a-d70327b38786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557675623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1557675623
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1241397162
Short name T94
Test name
Test status
Simulation time 16056179276 ps
CPU time 19.28 seconds
Started Jun 05 03:52:41 PM PDT 24
Finished Jun 05 03:53:01 PM PDT 24
Peak memory 182848 kb
Host smart-1969df5c-3967-4315-9737-7c3a5e182f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241397162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1241397162
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.701958898
Short name T426
Test name
Test status
Simulation time 300832683076 ps
CPU time 188.43 seconds
Started Jun 05 03:52:41 PM PDT 24
Finished Jun 05 03:55:50 PM PDT 24
Peak memory 193608 kb
Host smart-9054eb96-0cd9-4c6d-b830-6424f831d069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701958898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.701958898
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.381361908
Short name T379
Test name
Test status
Simulation time 568772798398 ps
CPU time 214.07 seconds
Started Jun 05 03:52:02 PM PDT 24
Finished Jun 05 03:55:37 PM PDT 24
Peak memory 182972 kb
Host smart-238c4cb0-f1b7-4f28-8a69-07f0c11fcda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381361908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.381361908
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.467891119
Short name T263
Test name
Test status
Simulation time 52119107501 ps
CPU time 402.51 seconds
Started Jun 05 03:51:59 PM PDT 24
Finished Jun 05 03:58:42 PM PDT 24
Peak memory 191084 kb
Host smart-b00dcee3-76c1-4fc3-b0e7-83d12748d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467891119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.467891119
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1998665425
Short name T281
Test name
Test status
Simulation time 1880826011757 ps
CPU time 912.86 seconds
Started Jun 05 03:52:04 PM PDT 24
Finished Jun 05 04:07:17 PM PDT 24
Peak memory 191180 kb
Host smart-1cb5e9bf-d90a-4f15-92d6-384d1dc1db44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998665425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1998665425
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.3310353123
Short name T130
Test name
Test status
Simulation time 97783879334 ps
CPU time 280.46 seconds
Started Jun 05 03:52:40 PM PDT 24
Finished Jun 05 03:57:21 PM PDT 24
Peak memory 191048 kb
Host smart-fd36d9e9-8922-4b2f-8199-92c828cdfd42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310353123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3310353123
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3641362361
Short name T315
Test name
Test status
Simulation time 58263014749 ps
CPU time 101.59 seconds
Started Jun 05 03:52:41 PM PDT 24
Finished Jun 05 03:54:23 PM PDT 24
Peak memory 191056 kb
Host smart-23e2f6b5-2698-426b-a132-667cc6679ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641362361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3641362361
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1011702884
Short name T342
Test name
Test status
Simulation time 77721001487 ps
CPU time 141.19 seconds
Started Jun 05 03:52:41 PM PDT 24
Finished Jun 05 03:55:03 PM PDT 24
Peak memory 191056 kb
Host smart-b7eafe0a-60a9-4757-bd80-fab0a5784422
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011702884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1011702884
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4196996541
Short name T258
Test name
Test status
Simulation time 346755085538 ps
CPU time 871.43 seconds
Started Jun 05 03:52:38 PM PDT 24
Finished Jun 05 04:07:10 PM PDT 24
Peak memory 191172 kb
Host smart-dbbcf91f-302a-43b3-aa55-49026c0820ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196996541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4196996541
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3216399971
Short name T298
Test name
Test status
Simulation time 759816772074 ps
CPU time 742.25 seconds
Started Jun 05 03:51:58 PM PDT 24
Finished Jun 05 04:04:21 PM PDT 24
Peak memory 183004 kb
Host smart-df0f87a5-72af-4065-ba96-d2333c25ed2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216399971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3216399971
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2300713153
Short name T436
Test name
Test status
Simulation time 206094285330 ps
CPU time 86.3 seconds
Started Jun 05 03:52:01 PM PDT 24
Finished Jun 05 03:53:29 PM PDT 24
Peak memory 182892 kb
Host smart-77f5803e-8500-463d-ac94-a2ae58db0e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300713153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2300713153
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1668023783
Short name T279
Test name
Test status
Simulation time 524722088121 ps
CPU time 247.57 seconds
Started Jun 05 03:51:58 PM PDT 24
Finished Jun 05 03:56:06 PM PDT 24
Peak memory 191080 kb
Host smart-fd4dc5a5-8017-41b0-8a89-c5e70cf0a9f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668023783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1668023783
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1446342054
Short name T440
Test name
Test status
Simulation time 146803434629 ps
CPU time 74.41 seconds
Started Jun 05 03:52:07 PM PDT 24
Finished Jun 05 03:53:22 PM PDT 24
Peak memory 182892 kb
Host smart-b5affa7f-d4c5-4c9d-b376-2fcf5a457020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446342054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1446342054
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.272713687
Short name T418
Test name
Test status
Simulation time 58979763223 ps
CPU time 250.45 seconds
Started Jun 05 03:51:59 PM PDT 24
Finished Jun 05 03:56:11 PM PDT 24
Peak memory 205856 kb
Host smart-85c00918-027c-49c9-a10b-a3ca1a7b02f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272713687 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.272713687
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.445664923
Short name T254
Test name
Test status
Simulation time 64360315156 ps
CPU time 60.86 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 03:53:47 PM PDT 24
Peak memory 182976 kb
Host smart-36894ce7-7877-441d-b261-4bda4e9df423
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445664923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.445664923
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.590838243
Short name T165
Test name
Test status
Simulation time 160503747518 ps
CPU time 281.08 seconds
Started Jun 05 03:52:46 PM PDT 24
Finished Jun 05 03:57:28 PM PDT 24
Peak memory 191184 kb
Host smart-fb332ba8-afd1-420d-8a80-bfb7e913aac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590838243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.590838243
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1251191838
Short name T230
Test name
Test status
Simulation time 60041933512 ps
CPU time 91.46 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 03:54:14 PM PDT 24
Peak memory 191048 kb
Host smart-7b98d039-c978-468e-a55d-56f7dea62638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251191838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1251191838
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1104966104
Short name T333
Test name
Test status
Simulation time 273026665630 ps
CPU time 1225.72 seconds
Started Jun 05 03:52:49 PM PDT 24
Finished Jun 05 04:13:16 PM PDT 24
Peak memory 193996 kb
Host smart-389a3476-90bc-440a-80c3-65a111d5c3aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104966104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1104966104
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1802316510
Short name T207
Test name
Test status
Simulation time 865061213885 ps
CPU time 728.89 seconds
Started Jun 05 03:51:56 PM PDT 24
Finished Jun 05 04:04:06 PM PDT 24
Peak memory 182896 kb
Host smart-5dbf3ed9-410d-4848-980f-397197644a3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802316510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1802316510
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2247487275
Short name T429
Test name
Test status
Simulation time 253423481855 ps
CPU time 215.7 seconds
Started Jun 05 03:52:01 PM PDT 24
Finished Jun 05 03:55:38 PM PDT 24
Peak memory 182896 kb
Host smart-4eff7701-8487-4cf7-9dce-6a7b532d3759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247487275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2247487275
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.4289995467
Short name T215
Test name
Test status
Simulation time 328425133336 ps
CPU time 569.31 seconds
Started Jun 05 03:52:05 PM PDT 24
Finished Jun 05 04:01:35 PM PDT 24
Peak memory 190832 kb
Host smart-f65c4f11-7a9d-44c0-b281-e1faf70c2fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289995467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.4289995467
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1698330263
Short name T218
Test name
Test status
Simulation time 63356617739 ps
CPU time 653.31 seconds
Started Jun 05 03:52:02 PM PDT 24
Finished Jun 05 04:02:56 PM PDT 24
Peak memory 191092 kb
Host smart-c7cb4113-eea0-49e2-b4d7-9c99ec576338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698330263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1698330263
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2730765262
Short name T5
Test name
Test status
Simulation time 736819783666 ps
CPU time 176.8 seconds
Started Jun 05 03:52:44 PM PDT 24
Finished Jun 05 03:55:41 PM PDT 24
Peak memory 191064 kb
Host smart-c0a3e366-be5c-4fdf-9dbb-dec5919f7870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730765262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2730765262
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.744435636
Short name T86
Test name
Test status
Simulation time 25151066542 ps
CPU time 40.89 seconds
Started Jun 05 03:52:52 PM PDT 24
Finished Jun 05 03:53:33 PM PDT 24
Peak memory 182936 kb
Host smart-8de2f384-3365-4ec9-8e6a-b49e374df2d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744435636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.744435636
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.607504965
Short name T21
Test name
Test status
Simulation time 73234123091 ps
CPU time 380.45 seconds
Started Jun 05 03:52:38 PM PDT 24
Finished Jun 05 03:58:59 PM PDT 24
Peak memory 193700 kb
Host smart-9821d13b-2d04-4cb5-94a7-31227078a283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607504965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.607504965
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3215581875
Short name T62
Test name
Test status
Simulation time 71572387633 ps
CPU time 82.27 seconds
Started Jun 05 03:52:49 PM PDT 24
Finished Jun 05 03:54:12 PM PDT 24
Peak memory 182980 kb
Host smart-473adb96-d72c-43a7-937e-5b8e3151b2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215581875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3215581875
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3201629414
Short name T425
Test name
Test status
Simulation time 29616051309 ps
CPU time 56.64 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 03:53:39 PM PDT 24
Peak memory 182840 kb
Host smart-030464ad-a4b1-47cc-ab95-abff5ac0f3f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201629414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3201629414
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1127424174
Short name T141
Test name
Test status
Simulation time 160190450623 ps
CPU time 508.19 seconds
Started Jun 05 03:52:53 PM PDT 24
Finished Jun 05 04:01:23 PM PDT 24
Peak memory 191180 kb
Host smart-f6dc3028-2e0d-4204-9564-8aed2f493ba1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127424174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1127424174
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1579236080
Short name T170
Test name
Test status
Simulation time 150911117839 ps
CPU time 168.3 seconds
Started Jun 05 03:52:51 PM PDT 24
Finished Jun 05 03:55:41 PM PDT 24
Peak memory 191060 kb
Host smart-42dc8348-daee-4eeb-9f5e-9eef6105bd98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579236080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1579236080
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2873492998
Short name T332
Test name
Test status
Simulation time 218365552787 ps
CPU time 339.38 seconds
Started Jun 05 03:51:58 PM PDT 24
Finished Jun 05 03:57:39 PM PDT 24
Peak memory 182992 kb
Host smart-03877557-8456-4b8a-9a0e-18bf92d6214a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873492998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2873492998
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3032654990
Short name T427
Test name
Test status
Simulation time 483973601593 ps
CPU time 163.13 seconds
Started Jun 05 03:52:08 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 182996 kb
Host smart-a6002823-84d4-4c6e-847c-89b70ed3c6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032654990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3032654990
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1587814216
Short name T346
Test name
Test status
Simulation time 359833518336 ps
CPU time 1015.79 seconds
Started Jun 05 03:51:58 PM PDT 24
Finished Jun 05 04:08:55 PM PDT 24
Peak memory 191176 kb
Host smart-3e7078c8-7eac-4c1d-9959-25623962d550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587814216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1587814216
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3132193000
Short name T445
Test name
Test status
Simulation time 15296197135 ps
CPU time 7.85 seconds
Started Jun 05 03:52:10 PM PDT 24
Finished Jun 05 03:52:19 PM PDT 24
Peak memory 183216 kb
Host smart-32b9cb7d-1ba0-4c17-a91a-20d34c7c22b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132193000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3132193000
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3142673876
Short name T356
Test name
Test status
Simulation time 152334246280 ps
CPU time 82.34 seconds
Started Jun 05 03:52:54 PM PDT 24
Finished Jun 05 03:54:17 PM PDT 24
Peak memory 191172 kb
Host smart-7a0f0d21-53d6-4b39-8fe1-db86046ab3c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142673876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3142673876
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.722855126
Short name T352
Test name
Test status
Simulation time 99417832967 ps
CPU time 389.36 seconds
Started Jun 05 03:52:54 PM PDT 24
Finished Jun 05 03:59:25 PM PDT 24
Peak memory 182868 kb
Host smart-656cf653-e150-4fc1-8ba4-0afd59bf8666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722855126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.722855126
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2344837638
Short name T323
Test name
Test status
Simulation time 216564342019 ps
CPU time 916.19 seconds
Started Jun 05 03:52:50 PM PDT 24
Finished Jun 05 04:08:07 PM PDT 24
Peak memory 191172 kb
Host smart-7b39c7cb-5276-4a25-bc8b-b36a970d628f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344837638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2344837638
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.850261065
Short name T19
Test name
Test status
Simulation time 272930292280 ps
CPU time 726.95 seconds
Started Jun 05 03:52:44 PM PDT 24
Finished Jun 05 04:04:52 PM PDT 24
Peak memory 191180 kb
Host smart-c36caf59-1f44-4a81-935b-597530f3464a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850261065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.850261065
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2953830818
Short name T43
Test name
Test status
Simulation time 69966159069 ps
CPU time 69.87 seconds
Started Jun 05 03:52:51 PM PDT 24
Finished Jun 05 03:54:02 PM PDT 24
Peak memory 191180 kb
Host smart-ac31e5a8-431b-416b-afb4-d0f2d6d2cf1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953830818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2953830818
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1700143883
Short name T180
Test name
Test status
Simulation time 412497169420 ps
CPU time 427.28 seconds
Started Jun 05 03:52:49 PM PDT 24
Finished Jun 05 03:59:57 PM PDT 24
Peak memory 191180 kb
Host smart-c2750e98-0dd6-4f31-a64b-49a8ed80e6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700143883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1700143883
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1798368529
Short name T392
Test name
Test status
Simulation time 334171576388 ps
CPU time 200.99 seconds
Started Jun 05 03:52:19 PM PDT 24
Finished Jun 05 03:55:41 PM PDT 24
Peak memory 182868 kb
Host smart-41fd878c-37c7-46ea-802e-014a268575f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798368529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1798368529
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1433119594
Short name T288
Test name
Test status
Simulation time 21269806493 ps
CPU time 230.92 seconds
Started Jun 05 03:52:14 PM PDT 24
Finished Jun 05 03:56:06 PM PDT 24
Peak memory 191168 kb
Host smart-a9a93fa7-5e13-463c-9ec8-2fbf8e1a5de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433119594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1433119594
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1118433595
Short name T1
Test name
Test status
Simulation time 1087101114692 ps
CPU time 332.15 seconds
Started Jun 05 03:52:11 PM PDT 24
Finished Jun 05 03:57:44 PM PDT 24
Peak memory 182960 kb
Host smart-cd4aa02f-ec76-4393-a643-bc36b0e2767f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118433595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1118433595
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.3159130688
Short name T193
Test name
Test status
Simulation time 77687143902 ps
CPU time 251.73 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 03:56:57 PM PDT 24
Peak memory 191076 kb
Host smart-31f5e6d3-bd22-40ca-ba32-d759ec77cfb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159130688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3159130688
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2667855229
Short name T340
Test name
Test status
Simulation time 54830419144 ps
CPU time 45.58 seconds
Started Jun 05 03:52:50 PM PDT 24
Finished Jun 05 03:53:36 PM PDT 24
Peak memory 182980 kb
Host smart-08e58d95-4571-40b7-89e7-5344a8956bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667855229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2667855229
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2672150585
Short name T216
Test name
Test status
Simulation time 172045937750 ps
CPU time 643.65 seconds
Started Jun 05 03:52:48 PM PDT 24
Finished Jun 05 04:03:33 PM PDT 24
Peak memory 191180 kb
Host smart-71fac028-e069-497c-be6e-0c6cbdafb2bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672150585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2672150585
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1969008640
Short name T251
Test name
Test status
Simulation time 94651903356 ps
CPU time 154.53 seconds
Started Jun 05 03:52:53 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 191072 kb
Host smart-0805f694-c0b8-49cd-996f-4cdf45a4a6d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969008640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1969008640
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2983220242
Short name T20
Test name
Test status
Simulation time 90075129512 ps
CPU time 154.59 seconds
Started Jun 05 03:52:57 PM PDT 24
Finished Jun 05 03:55:32 PM PDT 24
Peak memory 190984 kb
Host smart-cd36fa9b-6bfb-4ff6-9c72-15a54dc53fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983220242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2983220242
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2503673679
Short name T335
Test name
Test status
Simulation time 65414347127 ps
CPU time 96.44 seconds
Started Jun 05 03:52:44 PM PDT 24
Finished Jun 05 03:54:21 PM PDT 24
Peak memory 191180 kb
Host smart-1235b826-5543-46bb-b4cf-c71c5a88dd8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503673679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2503673679
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2042056028
Short name T177
Test name
Test status
Simulation time 270611174830 ps
CPU time 81.93 seconds
Started Jun 05 03:52:49 PM PDT 24
Finished Jun 05 03:54:11 PM PDT 24
Peak memory 191064 kb
Host smart-193080a5-cf49-407f-840f-e979905a63c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042056028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2042056028
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1399970021
Short name T371
Test name
Test status
Simulation time 374338314770 ps
CPU time 157.4 seconds
Started Jun 05 03:52:13 PM PDT 24
Finished Jun 05 03:54:51 PM PDT 24
Peak memory 182940 kb
Host smart-f3fcb214-6723-4110-9596-1c9609f11da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399970021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1399970021
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.219667115
Short name T244
Test name
Test status
Simulation time 85860385959 ps
CPU time 165.53 seconds
Started Jun 05 03:52:20 PM PDT 24
Finished Jun 05 03:55:06 PM PDT 24
Peak memory 182960 kb
Host smart-22dae36e-cd8e-42d2-b8c3-9a3d8f0a0b66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219667115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.219667115
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2013777076
Short name T441
Test name
Test status
Simulation time 379832396348 ps
CPU time 274.6 seconds
Started Jun 05 03:52:13 PM PDT 24
Finished Jun 05 03:56:48 PM PDT 24
Peak memory 194464 kb
Host smart-e432c106-9112-48f8-9ccf-c877533b644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013777076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2013777076
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2396751341
Short name T343
Test name
Test status
Simulation time 149288737758 ps
CPU time 122.54 seconds
Started Jun 05 03:52:14 PM PDT 24
Finished Jun 05 03:54:18 PM PDT 24
Peak memory 191160 kb
Host smart-2e4cfc06-cb59-4bac-b60b-f390a67d1cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396751341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2396751341
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1813038123
Short name T301
Test name
Test status
Simulation time 82797229970 ps
CPU time 428.43 seconds
Started Jun 05 03:52:53 PM PDT 24
Finished Jun 05 04:00:02 PM PDT 24
Peak memory 191180 kb
Host smart-40f81cc1-7ef9-4460-a078-65c0d6b5341d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813038123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1813038123
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.867568352
Short name T138
Test name
Test status
Simulation time 664245753115 ps
CPU time 119.97 seconds
Started Jun 05 03:52:57 PM PDT 24
Finished Jun 05 03:54:58 PM PDT 24
Peak memory 190972 kb
Host smart-49554877-2161-4f06-92be-b887c1236ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867568352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.867568352
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.245908797
Short name T255
Test name
Test status
Simulation time 632417544675 ps
CPU time 1773.21 seconds
Started Jun 05 03:52:51 PM PDT 24
Finished Jun 05 04:22:26 PM PDT 24
Peak memory 194212 kb
Host smart-995e2d7f-b306-4cb3-a7d4-7db78af83fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245908797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.245908797
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2923680751
Short name T359
Test name
Test status
Simulation time 5631984144 ps
CPU time 9.03 seconds
Started Jun 05 03:52:52 PM PDT 24
Finished Jun 05 03:53:01 PM PDT 24
Peak memory 182844 kb
Host smart-cc711a85-3fd4-42fa-9789-807baea57aef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923680751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2923680751
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.434155681
Short name T201
Test name
Test status
Simulation time 28151270296 ps
CPU time 54.18 seconds
Started Jun 05 03:52:57 PM PDT 24
Finished Jun 05 03:53:52 PM PDT 24
Peak memory 190984 kb
Host smart-fdac92a0-2e2c-46da-967a-c73840ebf19d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434155681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.434155681
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2582190334
Short name T213
Test name
Test status
Simulation time 118224757266 ps
CPU time 191.58 seconds
Started Jun 05 03:52:43 PM PDT 24
Finished Jun 05 03:55:56 PM PDT 24
Peak memory 190580 kb
Host smart-66680726-3bdc-4f9f-a7ad-60d413129e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582190334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2582190334
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4060689927
Short name T421
Test name
Test status
Simulation time 64731049109 ps
CPU time 86.45 seconds
Started Jun 05 03:52:51 PM PDT 24
Finished Jun 05 03:54:18 PM PDT 24
Peak memory 182980 kb
Host smart-61b742c7-9699-4f3f-ac11-c60b6660f701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060689927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4060689927
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3690833805
Short name T2
Test name
Test status
Simulation time 526618646954 ps
CPU time 839.98 seconds
Started Jun 05 03:52:13 PM PDT 24
Finished Jun 05 04:06:14 PM PDT 24
Peak memory 182948 kb
Host smart-5cc35816-bc72-4d78-bf57-c4bf9f1e0920
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690833805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3690833805
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2626913297
Short name T395
Test name
Test status
Simulation time 430208467019 ps
CPU time 152.43 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 03:54:56 PM PDT 24
Peak memory 182884 kb
Host smart-a5b19100-e105-4fb7-9f28-8d297958011b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626913297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2626913297
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1875123729
Short name T351
Test name
Test status
Simulation time 484917142266 ps
CPU time 299.44 seconds
Started Jun 05 03:52:18 PM PDT 24
Finished Jun 05 03:57:18 PM PDT 24
Peak memory 182984 kb
Host smart-d1e24f06-e856-4882-9b98-19360a26225d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875123729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1875123729
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.827437439
Short name T364
Test name
Test status
Simulation time 126185289 ps
CPU time 0.66 seconds
Started Jun 05 03:52:11 PM PDT 24
Finished Jun 05 03:52:13 PM PDT 24
Peak memory 182624 kb
Host smart-bc061172-a0f7-4605-9594-ed617886ad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827437439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.827437439
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.3550520677
Short name T33
Test name
Test status
Simulation time 136035636507 ps
CPU time 805.46 seconds
Started Jun 05 03:52:16 PM PDT 24
Finished Jun 05 04:05:42 PM PDT 24
Peak memory 213268 kb
Host smart-66d66e30-d3ca-4abd-bde3-fc029496acb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550520677 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.3550520677
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4102308296
Short name T296
Test name
Test status
Simulation time 196489042351 ps
CPU time 335.06 seconds
Started Jun 05 03:52:49 PM PDT 24
Finished Jun 05 03:58:25 PM PDT 24
Peak memory 191180 kb
Host smart-5095578f-ed24-4d3e-ad0e-e27f4fa53689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102308296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4102308296
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4016621860
Short name T64
Test name
Test status
Simulation time 38057831606 ps
CPU time 60.66 seconds
Started Jun 05 03:53:00 PM PDT 24
Finished Jun 05 03:54:02 PM PDT 24
Peak memory 182980 kb
Host smart-3854a825-ac5b-4dd2-920d-5d236cb7a774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016621860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4016621860
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3405159802
Short name T118
Test name
Test status
Simulation time 507091878536 ps
CPU time 351.55 seconds
Started Jun 05 03:53:00 PM PDT 24
Finished Jun 05 03:58:53 PM PDT 24
Peak memory 191076 kb
Host smart-95d8a2f1-81bb-4052-bbae-600211c1946a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405159802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3405159802
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3053034889
Short name T236
Test name
Test status
Simulation time 219676842283 ps
CPU time 637.04 seconds
Started Jun 05 03:52:53 PM PDT 24
Finished Jun 05 04:03:32 PM PDT 24
Peak memory 191180 kb
Host smart-dcca02ef-ec72-44b3-8320-91a7708fffc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053034889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3053034889
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.932131546
Short name T194
Test name
Test status
Simulation time 601061366002 ps
CPU time 998.16 seconds
Started Jun 05 03:52:53 PM PDT 24
Finished Jun 05 04:09:32 PM PDT 24
Peak memory 191080 kb
Host smart-fb824c6e-e964-405e-816f-3972face5154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932131546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.932131546
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.768976292
Short name T173
Test name
Test status
Simulation time 49560610953 ps
CPU time 84.57 seconds
Started Jun 05 03:52:47 PM PDT 24
Finished Jun 05 03:54:12 PM PDT 24
Peak memory 191204 kb
Host smart-a5a759c8-f816-46c0-83df-d87dc0dba652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768976292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.768976292
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1602431994
Short name T413
Test name
Test status
Simulation time 20677018109 ps
CPU time 32.79 seconds
Started Jun 05 03:52:14 PM PDT 24
Finished Jun 05 03:52:48 PM PDT 24
Peak memory 182900 kb
Host smart-5a65ae89-19c2-4efc-b329-25117c3aed37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602431994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1602431994
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1674806672
Short name T380
Test name
Test status
Simulation time 132000971748 ps
CPU time 200.05 seconds
Started Jun 05 03:52:16 PM PDT 24
Finished Jun 05 03:55:37 PM PDT 24
Peak memory 182996 kb
Host smart-717a8b7f-15d9-4a4a-aaaa-fd5bd2ee9c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674806672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1674806672
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.819187738
Short name T448
Test name
Test status
Simulation time 339739636141 ps
CPU time 587.56 seconds
Started Jun 05 03:52:12 PM PDT 24
Finished Jun 05 04:02:01 PM PDT 24
Peak memory 194604 kb
Host smart-506e51c4-775c-4eba-a035-61cda2bc75ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819187738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
819187738
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2204897416
Short name T47
Test name
Test status
Simulation time 56724495368 ps
CPU time 330.75 seconds
Started Jun 05 03:52:15 PM PDT 24
Finished Jun 05 03:57:47 PM PDT 24
Peak memory 197864 kb
Host smart-f56e7a21-a031-40a4-ad82-258897fa15d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204897416 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2204897416
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.983289760
Short name T320
Test name
Test status
Simulation time 31940013008 ps
CPU time 27.58 seconds
Started Jun 05 03:52:49 PM PDT 24
Finished Jun 05 03:53:17 PM PDT 24
Peak memory 182876 kb
Host smart-3137c3cc-5335-4d28-a1c4-8cdd2799aa73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983289760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.983289760
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1882774462
Short name T153
Test name
Test status
Simulation time 292056475190 ps
CPU time 715.87 seconds
Started Jun 05 03:52:47 PM PDT 24
Finished Jun 05 04:04:43 PM PDT 24
Peak memory 191048 kb
Host smart-b9f49ebe-d389-44c0-8d9d-4c7f145a6632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882774462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1882774462
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3069108276
Short name T424
Test name
Test status
Simulation time 57507281421 ps
CPU time 320.36 seconds
Started Jun 05 03:52:59 PM PDT 24
Finished Jun 05 03:58:21 PM PDT 24
Peak memory 191184 kb
Host smart-f20f5a3d-6ac8-4fd9-8ea3-701e447a6a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069108276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3069108276
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1924584944
Short name T270
Test name
Test status
Simulation time 387013308020 ps
CPU time 204.34 seconds
Started Jun 05 03:52:57 PM PDT 24
Finished Jun 05 03:56:22 PM PDT 24
Peak memory 191068 kb
Host smart-c54c27b7-577e-4ce8-96be-d9a9166dd480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924584944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1924584944
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.434833097
Short name T239
Test name
Test status
Simulation time 94480491635 ps
CPU time 285.52 seconds
Started Jun 05 03:52:46 PM PDT 24
Finished Jun 05 03:57:32 PM PDT 24
Peak memory 191172 kb
Host smart-72b83564-6674-4219-bae5-0aa956b7e1e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434833097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.434833097
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2767459917
Short name T116
Test name
Test status
Simulation time 485885711600 ps
CPU time 196.85 seconds
Started Jun 05 03:52:47 PM PDT 24
Finished Jun 05 03:56:04 PM PDT 24
Peak memory 191080 kb
Host smart-0a05226b-bc92-48c6-a37b-6f905a100810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767459917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2767459917
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.874084773
Short name T113
Test name
Test status
Simulation time 88839313739 ps
CPU time 146.72 seconds
Started Jun 05 03:52:52 PM PDT 24
Finished Jun 05 03:55:19 PM PDT 24
Peak memory 191176 kb
Host smart-2f6a364e-4c2c-4b38-8d11-d57210a47161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874084773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.874084773
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.887252953
Short name T311
Test name
Test status
Simulation time 3034760857 ps
CPU time 5.55 seconds
Started Jun 05 03:52:15 PM PDT 24
Finished Jun 05 03:52:22 PM PDT 24
Peak memory 183236 kb
Host smart-4da49dc6-0e0e-4018-95a8-579e635c2613
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887252953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.887252953
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1091447533
Short name T89
Test name
Test status
Simulation time 419389598999 ps
CPU time 307.72 seconds
Started Jun 05 03:52:14 PM PDT 24
Finished Jun 05 03:57:23 PM PDT 24
Peak memory 182880 kb
Host smart-3e1d41f6-89d9-4be6-bf2c-eae48c4679ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091447533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1091447533
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2146322416
Short name T122
Test name
Test status
Simulation time 415929736925 ps
CPU time 219.97 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:56:05 PM PDT 24
Peak memory 191072 kb
Host smart-cfb35c6b-2171-421f-a362-1d691d296283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146322416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2146322416
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3609917500
Short name T435
Test name
Test status
Simulation time 53433040223 ps
CPU time 88.92 seconds
Started Jun 05 03:52:14 PM PDT 24
Finished Jun 05 03:53:44 PM PDT 24
Peak memory 191172 kb
Host smart-c81f9710-ea39-4ffc-9e1b-65673e9a9d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609917500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3609917500
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1887723476
Short name T184
Test name
Test status
Simulation time 1717362819379 ps
CPU time 607.81 seconds
Started Jun 05 03:52:46 PM PDT 24
Finished Jun 05 04:02:55 PM PDT 24
Peak memory 191172 kb
Host smart-ae2f8fe6-3d0c-4d4c-9c31-c8b057f9a546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887723476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1887723476
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.92421114
Short name T151
Test name
Test status
Simulation time 119799918988 ps
CPU time 455.89 seconds
Started Jun 05 03:52:54 PM PDT 24
Finished Jun 05 04:00:31 PM PDT 24
Peak memory 182980 kb
Host smart-166f76cd-a844-44cf-a677-1e4ff5c8a32d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92421114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.92421114
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3936140007
Short name T142
Test name
Test status
Simulation time 222476275324 ps
CPU time 210.44 seconds
Started Jun 05 03:53:03 PM PDT 24
Finished Jun 05 03:56:34 PM PDT 24
Peak memory 191176 kb
Host smart-f4f064fb-6de0-41b2-9b36-37ffef4dcd37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936140007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3936140007
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3985336377
Short name T299
Test name
Test status
Simulation time 242229302350 ps
CPU time 533.74 seconds
Started Jun 05 03:53:11 PM PDT 24
Finished Jun 05 04:02:05 PM PDT 24
Peak memory 191068 kb
Host smart-309ad70a-5491-41f8-9703-b48974b17001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985336377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3985336377
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1181666923
Short name T314
Test name
Test status
Simulation time 71837060614 ps
CPU time 144 seconds
Started Jun 05 03:53:04 PM PDT 24
Finished Jun 05 03:55:29 PM PDT 24
Peak memory 191180 kb
Host smart-9cf8fc76-f34f-4ef9-817e-5f31a8db03b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181666923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1181666923
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2382544007
Short name T353
Test name
Test status
Simulation time 305864949855 ps
CPU time 253.03 seconds
Started Jun 05 03:52:56 PM PDT 24
Finished Jun 05 03:57:11 PM PDT 24
Peak memory 191068 kb
Host smart-82d08f89-2d3b-4e7d-92b7-19ee137c8902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382544007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2382544007
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2058300769
Short name T226
Test name
Test status
Simulation time 463398082093 ps
CPU time 264.67 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 03:56:15 PM PDT 24
Peak memory 182868 kb
Host smart-9504dfda-d822-4b45-a578-b23622aaf8c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058300769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2058300769
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2142004641
Short name T363
Test name
Test status
Simulation time 135147149410 ps
CPU time 206.75 seconds
Started Jun 05 03:51:46 PM PDT 24
Finished Jun 05 03:55:14 PM PDT 24
Peak memory 182880 kb
Host smart-bb7346be-d48f-4bd5-a0eb-4b1d2023ae72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142004641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2142004641
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3411888704
Short name T245
Test name
Test status
Simulation time 78708261126 ps
CPU time 80.42 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 03:53:11 PM PDT 24
Peak memory 183208 kb
Host smart-324d1718-67bf-439a-a131-b33909c33452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411888704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3411888704
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.211916341
Short name T283
Test name
Test status
Simulation time 329477058685 ps
CPU time 84.66 seconds
Started Jun 05 03:52:01 PM PDT 24
Finished Jun 05 03:53:26 PM PDT 24
Peak memory 191060 kb
Host smart-d696f1f5-a48b-4e34-809f-e976928ce781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211916341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.211916341
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3130437944
Short name T14
Test name
Test status
Simulation time 353189600 ps
CPU time 0.88 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 03:51:52 PM PDT 24
Peak memory 215724 kb
Host smart-7672f6f5-3b24-4b3c-a01e-7ca29a61fa34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130437944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3130437944
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3516533651
Short name T377
Test name
Test status
Simulation time 73161608358 ps
CPU time 97.51 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 03:53:29 PM PDT 24
Peak memory 182836 kb
Host smart-985bad09-5f09-4364-b91d-aafe2c8cccd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516533651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3516533651
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.42732690
Short name T150
Test name
Test status
Simulation time 231663933136 ps
CPU time 229.39 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:56:19 PM PDT 24
Peak memory 182876 kb
Host smart-52b7848c-cee8-4a38-8e53-105acba06693
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42732690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.rv_timer_cfg_update_on_fly.42732690
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3209718638
Short name T437
Test name
Test status
Simulation time 92271176869 ps
CPU time 42.59 seconds
Started Jun 05 03:52:15 PM PDT 24
Finished Jun 05 03:52:59 PM PDT 24
Peak memory 182880 kb
Host smart-b9057686-191f-4907-8ad6-482bbc9fc4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209718638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3209718638
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.915244259
Short name T290
Test name
Test status
Simulation time 185130927182 ps
CPU time 102.19 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:54:12 PM PDT 24
Peak memory 191060 kb
Host smart-945fcf91-2750-42e1-9cda-5a927e70d0f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915244259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.915244259
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3876586225
Short name T365
Test name
Test status
Simulation time 323752555 ps
CPU time 1.63 seconds
Started Jun 05 03:52:13 PM PDT 24
Finished Jun 05 03:52:16 PM PDT 24
Peak memory 193420 kb
Host smart-d37485e8-cbe7-41c5-a664-79fd62800c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876586225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3876586225
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3841558190
Short name T354
Test name
Test status
Simulation time 3115205562094 ps
CPU time 1130.56 seconds
Started Jun 05 03:52:13 PM PDT 24
Finished Jun 05 04:11:05 PM PDT 24
Peak memory 182904 kb
Host smart-45b51f30-4be1-4c4a-a6f7-162abd984d0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841558190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3841558190
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3220872090
Short name T370
Test name
Test status
Simulation time 91928902108 ps
CPU time 159.22 seconds
Started Jun 05 03:52:12 PM PDT 24
Finished Jun 05 03:54:52 PM PDT 24
Peak memory 183208 kb
Host smart-633102aa-338e-4266-a9c8-f69f619683c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220872090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3220872090
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3993333937
Short name T438
Test name
Test status
Simulation time 106792013335 ps
CPU time 186.92 seconds
Started Jun 05 03:52:12 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 191068 kb
Host smart-8282a036-ea9b-481e-bc51-63f44c1fa2fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993333937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3993333937
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3629915283
Short name T93
Test name
Test status
Simulation time 155842774691 ps
CPU time 56.27 seconds
Started Jun 05 03:52:15 PM PDT 24
Finished Jun 05 03:53:12 PM PDT 24
Peak memory 192780 kb
Host smart-d0b4ddeb-2dba-4712-b4e2-e6ef0ea1b709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629915283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3629915283
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2985378980
Short name T277
Test name
Test status
Simulation time 30795843235 ps
CPU time 54.8 seconds
Started Jun 05 03:52:19 PM PDT 24
Finished Jun 05 03:53:14 PM PDT 24
Peak memory 183004 kb
Host smart-130352d7-2bb7-4b52-94e9-7497891ac4a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985378980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2985378980
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2140942176
Short name T433
Test name
Test status
Simulation time 93598964951 ps
CPU time 136.41 seconds
Started Jun 05 03:52:25 PM PDT 24
Finished Jun 05 03:54:42 PM PDT 24
Peak memory 182968 kb
Host smart-19f6f3e9-1307-43a1-ad3a-afb2d7c91fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140942176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2140942176
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3541378738
Short name T129
Test name
Test status
Simulation time 87914476786 ps
CPU time 79.45 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:53:49 PM PDT 24
Peak memory 182952 kb
Host smart-f2569ef0-5fbb-4dba-8475-8b36a1f67aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541378738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3541378738
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2651078014
Short name T389
Test name
Test status
Simulation time 25278734 ps
CPU time 0.52 seconds
Started Jun 05 03:52:25 PM PDT 24
Finished Jun 05 03:52:26 PM PDT 24
Peak memory 182732 kb
Host smart-a3f1634e-deb8-45d3-be11-6a04b4412ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651078014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2651078014
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1118767188
Short name T284
Test name
Test status
Simulation time 893181345083 ps
CPU time 464.58 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 04:00:10 PM PDT 24
Peak memory 182900 kb
Host smart-cf524081-36cf-4645-baf9-32e5b87b985f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118767188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1118767188
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2620092784
Short name T385
Test name
Test status
Simulation time 77949855724 ps
CPU time 54.86 seconds
Started Jun 05 03:52:25 PM PDT 24
Finished Jun 05 03:53:21 PM PDT 24
Peak memory 182884 kb
Host smart-092fdcf3-ade7-4bf4-9906-d2d73753e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620092784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2620092784
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2937254271
Short name T430
Test name
Test status
Simulation time 17836875967 ps
CPU time 8.8 seconds
Started Jun 05 03:52:26 PM PDT 24
Finished Jun 05 03:52:36 PM PDT 24
Peak memory 182856 kb
Host smart-e731da70-7e1c-41f0-ab03-0e222fe5f38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937254271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2937254271
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3739210165
Short name T49
Test name
Test status
Simulation time 875211555880 ps
CPU time 550.07 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 04:01:40 PM PDT 24
Peak memory 191088 kb
Host smart-e961c0a3-a030-4016-afb9-b0d9c68fa90a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739210165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3739210165
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3893879804
Short name T404
Test name
Test status
Simulation time 474709274665 ps
CPU time 288.41 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:57:18 PM PDT 24
Peak memory 182948 kb
Host smart-cb563a49-5594-41ff-8d36-c573d8afe62d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893879804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3893879804
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.121022966
Short name T376
Test name
Test status
Simulation time 30773534067 ps
CPU time 42.47 seconds
Started Jun 05 03:52:22 PM PDT 24
Finished Jun 05 03:53:06 PM PDT 24
Peak memory 182996 kb
Host smart-638f19af-cba0-45b2-b008-3a23ee7b2764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121022966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.121022966
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3460713923
Short name T159
Test name
Test status
Simulation time 177152146056 ps
CPU time 440.76 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:59:50 PM PDT 24
Peak memory 194544 kb
Host smart-d2339562-8e27-485e-959d-cf0ae140adfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460713923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3460713923
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1115228452
Short name T189
Test name
Test status
Simulation time 25030490733 ps
CPU time 22.31 seconds
Started Jun 05 03:52:22 PM PDT 24
Finished Jun 05 03:52:45 PM PDT 24
Peak memory 182904 kb
Host smart-2850cb07-c8a1-4e4a-8e8b-fdd7bd06658d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115228452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1115228452
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3368748889
Short name T405
Test name
Test status
Simulation time 140722062514 ps
CPU time 185.22 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:55:33 PM PDT 24
Peak memory 182888 kb
Host smart-3c9214a8-96d3-42e5-8ef6-bed4e52c3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368748889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3368748889
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1210455701
Short name T143
Test name
Test status
Simulation time 53785212489 ps
CPU time 90.66 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 03:53:55 PM PDT 24
Peak memory 191184 kb
Host smart-543ac331-dc60-4f61-9347-cfe881154f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210455701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1210455701
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2545398404
Short name T6
Test name
Test status
Simulation time 109162414709 ps
CPU time 321.97 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:57:53 PM PDT 24
Peak memory 182900 kb
Host smart-abd7c61a-29d6-4c8f-b31f-f235f3fe344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545398404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2545398404
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3451682559
Short name T446
Test name
Test status
Simulation time 204527468222 ps
CPU time 244.5 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:56:33 PM PDT 24
Peak memory 182872 kb
Host smart-6a4a9c3b-ffe0-427d-ae3f-7cf26adc6784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451682559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3451682559
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1498503203
Short name T368
Test name
Test status
Simulation time 772144335180 ps
CPU time 258.74 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:56:49 PM PDT 24
Peak memory 182884 kb
Host smart-d1259194-ea21-4364-ae39-7ea637cf7150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498503203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1498503203
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.826458345
Short name T144
Test name
Test status
Simulation time 14779445248 ps
CPU time 24.54 seconds
Started Jun 05 03:52:21 PM PDT 24
Finished Jun 05 03:52:46 PM PDT 24
Peak memory 183000 kb
Host smart-257ba37c-1a73-421a-8097-b1f21e5aaf44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826458345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.826458345
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.297922893
Short name T209
Test name
Test status
Simulation time 242820804822 ps
CPU time 125.07 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 03:54:29 PM PDT 24
Peak memory 182972 kb
Host smart-70efa956-d3e8-4122-9578-e3e275016a0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297922893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.297922893
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.214154989
Short name T407
Test name
Test status
Simulation time 384969514801 ps
CPU time 167.31 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:55:13 PM PDT 24
Peak memory 182996 kb
Host smart-b71397d1-1ccb-4ce9-a64f-8b86f5a4f122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214154989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.214154989
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3058122365
Short name T415
Test name
Test status
Simulation time 29002547749 ps
CPU time 42.04 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:53:13 PM PDT 24
Peak memory 182876 kb
Host smart-36b34e52-38b3-4ff0-85e2-09caae038897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058122365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3058122365
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2683821028
Short name T398
Test name
Test status
Simulation time 538794616 ps
CPU time 1.38 seconds
Started Jun 05 03:52:25 PM PDT 24
Finished Jun 05 03:52:28 PM PDT 24
Peak memory 194020 kb
Host smart-e35b8ffd-c5e2-44a5-8ccc-72f507257a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683821028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2683821028
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3041781154
Short name T412
Test name
Test status
Simulation time 317884580260 ps
CPU time 434.48 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:59:40 PM PDT 24
Peak memory 194968 kb
Host smart-9fd31bc1-1d28-48a9-b79b-89e7a13f31ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041781154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3041781154
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1000290498
Short name T367
Test name
Test status
Simulation time 92577516015 ps
CPU time 130.39 seconds
Started Jun 05 03:52:22 PM PDT 24
Finished Jun 05 03:54:33 PM PDT 24
Peak memory 182952 kb
Host smart-e46d1169-281b-452b-8ef3-87240949b989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000290498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1000290498
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2281762734
Short name T419
Test name
Test status
Simulation time 24165162959 ps
CPU time 36.87 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:53:07 PM PDT 24
Peak memory 182828 kb
Host smart-58e9d561-5023-4661-8387-2dfd1d3ccfab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281762734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2281762734
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1554891382
Short name T312
Test name
Test status
Simulation time 224654677906 ps
CPU time 87.37 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:53:57 PM PDT 24
Peak memory 182884 kb
Host smart-76f0fddb-5b9b-4e8d-b301-89cd69653922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554891382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1554891382
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3145924185
Short name T175
Test name
Test status
Simulation time 2438287358060 ps
CPU time 2989.44 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 04:42:20 PM PDT 24
Peak memory 196304 kb
Host smart-90ab8cc2-7210-4862-91d6-ace09e2bf544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145924185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3145924185
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2580718582
Short name T188
Test name
Test status
Simulation time 402172422719 ps
CPU time 735.66 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 04:04:47 PM PDT 24
Peak memory 182900 kb
Host smart-1aa324fe-2bda-4845-8d14-a191856acf60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580718582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2580718582
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.73080577
Short name T362
Test name
Test status
Simulation time 49370071334 ps
CPU time 71.81 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:53:40 PM PDT 24
Peak memory 182892 kb
Host smart-e4503262-f8e6-4c41-8392-fe0c965a8499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73080577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.73080577
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1916377421
Short name T61
Test name
Test status
Simulation time 5243771017532 ps
CPU time 1659.87 seconds
Started Jun 05 03:52:26 PM PDT 24
Finished Jun 05 04:20:07 PM PDT 24
Peak memory 195596 kb
Host smart-fc515826-fccc-4d78-a1d4-f50387c3e8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916377421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1916377421
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2767788390
Short name T278
Test name
Test status
Simulation time 594376703100 ps
CPU time 312.28 seconds
Started Jun 05 03:51:59 PM PDT 24
Finished Jun 05 03:57:12 PM PDT 24
Peak memory 182872 kb
Host smart-8626d517-e1e6-4599-88c6-750e8b7e28cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767788390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2767788390
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3421698593
Short name T369
Test name
Test status
Simulation time 6078691839 ps
CPU time 11.07 seconds
Started Jun 05 03:51:57 PM PDT 24
Finished Jun 05 03:52:09 PM PDT 24
Peak memory 182740 kb
Host smart-22895d99-ebfd-4824-8870-ef23350bbc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421698593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3421698593
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2541474191
Short name T166
Test name
Test status
Simulation time 1202582626037 ps
CPU time 652.12 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 04:02:43 PM PDT 24
Peak memory 191032 kb
Host smart-a642b6d3-bb5c-48e9-a087-e8df76ca6523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541474191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2541474191
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3252585063
Short name T18
Test name
Test status
Simulation time 258350633 ps
CPU time 0.94 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 03:51:52 PM PDT 24
Peak memory 214440 kb
Host smart-11aa3266-f431-410a-8334-2315d7dbb58d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252585063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3252585063
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1202530936
Short name T30
Test name
Test status
Simulation time 381583010845 ps
CPU time 612.72 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 04:02:05 PM PDT 24
Peak memory 194776 kb
Host smart-47962b63-d86a-4da6-9d97-d9b713704868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202530936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1202530936
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3457349759
Short name T266
Test name
Test status
Simulation time 135533647672 ps
CPU time 71.29 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:53:37 PM PDT 24
Peak memory 183236 kb
Host smart-24082523-a543-4410-abf4-04c0f1e1b4ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457349759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3457349759
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.767081709
Short name T410
Test name
Test status
Simulation time 598954458325 ps
CPU time 72.36 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:53:41 PM PDT 24
Peak memory 182876 kb
Host smart-e09e40a0-3cfa-4350-b41d-f41d5583018d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767081709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.767081709
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2714768757
Short name T154
Test name
Test status
Simulation time 67286655357 ps
CPU time 146.88 seconds
Started Jun 05 03:52:22 PM PDT 24
Finished Jun 05 03:54:50 PM PDT 24
Peak memory 191156 kb
Host smart-e6f64782-ca4e-4a75-a51e-8dcd0c768c0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714768757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2714768757
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1937276551
Short name T408
Test name
Test status
Simulation time 38077723230 ps
CPU time 65.29 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:53:31 PM PDT 24
Peak memory 191088 kb
Host smart-4fb702de-e5e0-4dd6-9fd4-4dd70b55d6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937276551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1937276551
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2558189722
Short name T361
Test name
Test status
Simulation time 2624282278813 ps
CPU time 585.77 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 04:02:17 PM PDT 24
Peak memory 182876 kb
Host smart-bb315dae-ac70-455c-86ab-b5371c5100fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558189722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2558189722
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1574979573
Short name T305
Test name
Test status
Simulation time 1226178297584 ps
CPU time 646.49 seconds
Started Jun 05 03:52:21 PM PDT 24
Finished Jun 05 04:03:08 PM PDT 24
Peak memory 182896 kb
Host smart-bb867d3e-1307-4d70-807f-7cb8bceeacb5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574979573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1574979573
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1182144554
Short name T431
Test name
Test status
Simulation time 130889229873 ps
CPU time 188.5 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:55:34 PM PDT 24
Peak memory 182880 kb
Host smart-e167c681-b299-41d9-ba2f-2a5ed72262ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182144554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1182144554
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3926231610
Short name T292
Test name
Test status
Simulation time 83618497613 ps
CPU time 36.33 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:53:05 PM PDT 24
Peak memory 194536 kb
Host smart-69681d01-d1cc-4ff8-84c6-c140bad0773d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926231610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3926231610
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1722056211
Short name T388
Test name
Test status
Simulation time 135583601608 ps
CPU time 106.49 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 03:54:11 PM PDT 24
Peak memory 182884 kb
Host smart-f81302c9-ca45-451b-a8d0-2007c4794028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722056211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1722056211
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3069381715
Short name T310
Test name
Test status
Simulation time 595156550683 ps
CPU time 302.79 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:57:32 PM PDT 24
Peak memory 183004 kb
Host smart-c8da5fc4-c28a-420c-99a1-637c2669c7e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069381715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3069381715
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2172111800
Short name T381
Test name
Test status
Simulation time 157563421432 ps
CPU time 229.42 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 03:56:14 PM PDT 24
Peak memory 182996 kb
Host smart-da54e891-d094-497b-a3c1-19a4e4c97186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172111800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2172111800
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3991064731
Short name T401
Test name
Test status
Simulation time 325846076863 ps
CPU time 403.95 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:59:12 PM PDT 24
Peak memory 191412 kb
Host smart-505786a3-a8d2-4f0f-b77e-1cb312f0554c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991064731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3991064731
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.181034840
Short name T447
Test name
Test status
Simulation time 122104601379 ps
CPU time 77.54 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:53:48 PM PDT 24
Peak memory 193844 kb
Host smart-2198b1da-5d6f-4351-9a1c-7d4d1055deff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181034840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.181034840
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2289412143
Short name T212
Test name
Test status
Simulation time 255013650118 ps
CPU time 823.12 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 04:06:13 PM PDT 24
Peak memory 193144 kb
Host smart-774279a6-2a96-42c9-93ec-d1cbbfa86cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289412143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2289412143
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.122704795
Short name T261
Test name
Test status
Simulation time 1023907965177 ps
CPU time 564.87 seconds
Started Jun 05 03:52:26 PM PDT 24
Finished Jun 05 04:01:52 PM PDT 24
Peak memory 182984 kb
Host smart-24252954-941d-41ea-8317-ee0152d8fd95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122704795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.122704795
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.202569526
Short name T60
Test name
Test status
Simulation time 226060351273 ps
CPU time 158.73 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:55:10 PM PDT 24
Peak memory 182892 kb
Host smart-58ddea71-6e4d-4b69-ab3b-1d1197f0f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202569526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.202569526
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.4283270217
Short name T269
Test name
Test status
Simulation time 33721390832 ps
CPU time 243.77 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:56:33 PM PDT 24
Peak memory 194580 kb
Host smart-deb54746-704a-4f50-bb60-14c3762c22d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283270217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.4283270217
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2272720906
Short name T378
Test name
Test status
Simulation time 95495733567 ps
CPU time 135.86 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:54:46 PM PDT 24
Peak memory 183000 kb
Host smart-b1b8e571-0853-487c-ac53-9fcd8930098c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272720906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2272720906
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2879511932
Short name T382
Test name
Test status
Simulation time 353634287766 ps
CPU time 1063.36 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 04:10:12 PM PDT 24
Peak memory 191044 kb
Host smart-5121d52a-cd4b-4e6a-8c82-084a6cb71514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879511932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2879511932
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.31456507
Short name T224
Test name
Test status
Simulation time 369460256563 ps
CPU time 170.79 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 194612 kb
Host smart-4f5b756a-aa88-4324-9e8c-f53e6843d980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31456507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.31456507
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.4199962191
Short name T132
Test name
Test status
Simulation time 215285869115 ps
CPU time 359.65 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:58:25 PM PDT 24
Peak memory 182904 kb
Host smart-c0d83d76-0abe-44d2-a6f7-9c432990626f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199962191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.4199962191
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.677951263
Short name T417
Test name
Test status
Simulation time 111663551551 ps
CPU time 84.21 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:53:54 PM PDT 24
Peak memory 182876 kb
Host smart-f7ff994d-6624-4cee-bb14-0b5a8e4db8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677951263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.677951263
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1622054712
Short name T358
Test name
Test status
Simulation time 25303624810 ps
CPU time 46.91 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:53:17 PM PDT 24
Peak memory 182892 kb
Host smart-ab55ecbb-44df-4929-9c14-6f4f4e579a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622054712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1622054712
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1635383016
Short name T31
Test name
Test status
Simulation time 38941301705 ps
CPU time 376.59 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:58:47 PM PDT 24
Peak memory 197500 kb
Host smart-f19f4fee-c025-4789-95b2-74af06f14028
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635383016 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1635383016
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2363641108
Short name T293
Test name
Test status
Simulation time 3920121290 ps
CPU time 7.33 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:52:39 PM PDT 24
Peak memory 182900 kb
Host smart-54a52f11-e438-4c57-bacf-49a251a31d39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363641108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2363641108
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3437685880
Short name T366
Test name
Test status
Simulation time 911313172622 ps
CPU time 272.13 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:57:04 PM PDT 24
Peak memory 182884 kb
Host smart-514cf542-c392-4869-bee8-8c701c711619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437685880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3437685880
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2189089590
Short name T109
Test name
Test status
Simulation time 55589363481 ps
CPU time 47.08 seconds
Started Jun 05 03:52:26 PM PDT 24
Finished Jun 05 03:53:14 PM PDT 24
Peak memory 191096 kb
Host smart-b5e8c28c-2308-488c-a5d4-6f6a5ca3b459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189089590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2189089590
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1934581662
Short name T219
Test name
Test status
Simulation time 450123299023 ps
CPU time 357.31 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:58:23 PM PDT 24
Peak memory 193704 kb
Host smart-09229a2c-6a29-47ab-aeb4-6399ac4a1049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934581662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1934581662
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.1835388176
Short name T36
Test name
Test status
Simulation time 33317579860 ps
CPU time 250.08 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 03:56:44 PM PDT 24
Peak memory 205780 kb
Host smart-91739d5c-2444-476d-becc-efe2a8a40412
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835388176 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.1835388176
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3941322880
Short name T160
Test name
Test status
Simulation time 600697843138 ps
CPU time 339.19 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:58:08 PM PDT 24
Peak memory 182896 kb
Host smart-2d9514f8-3605-4162-84d3-e13bd9d91d94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941322880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3941322880
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3477430620
Short name T56
Test name
Test status
Simulation time 472164557073 ps
CPU time 166.14 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 182888 kb
Host smart-8c06b58f-fbe6-46cd-8d42-d9fba2139940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477430620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3477430620
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2427383430
Short name T443
Test name
Test status
Simulation time 178910231 ps
CPU time 0.67 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 03:52:33 PM PDT 24
Peak memory 182688 kb
Host smart-4a736112-f264-4875-9c8b-fa7b897736d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427383430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2427383430
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2802803872
Short name T252
Test name
Test status
Simulation time 809576197734 ps
CPU time 438.01 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:59:46 PM PDT 24
Peak memory 192356 kb
Host smart-1efc6967-61d4-4063-be33-9b12d09a4291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802803872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2802803872
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.475344249
Short name T35
Test name
Test status
Simulation time 107709777804 ps
CPU time 895.47 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 04:07:29 PM PDT 24
Peak memory 201740 kb
Host smart-cdfde8d4-52aa-4843-8169-f8d364c07680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475344249 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.475344249
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1605760187
Short name T162
Test name
Test status
Simulation time 327905982837 ps
CPU time 372.78 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:58:42 PM PDT 24
Peak memory 182992 kb
Host smart-d2f0e4e6-5838-4700-b42a-3f8657325a5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605760187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1605760187
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2993750312
Short name T403
Test name
Test status
Simulation time 53788958364 ps
CPU time 36.8 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:53:07 PM PDT 24
Peak memory 182972 kb
Host smart-b2b9c004-874a-43ac-9e9d-53485fec403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993750312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2993750312
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1577587915
Short name T163
Test name
Test status
Simulation time 89773496674 ps
CPU time 135.86 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:54:48 PM PDT 24
Peak memory 191072 kb
Host smart-c57d99d2-fcfd-4d16-b332-41cf4dee6a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577587915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1577587915
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3084767827
Short name T102
Test name
Test status
Simulation time 77955003669 ps
CPU time 374.69 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 03:58:47 PM PDT 24
Peak memory 194380 kb
Host smart-4c97f253-4b56-4a41-9c47-8a98d116a37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084767827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3084767827
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1022163939
Short name T45
Test name
Test status
Simulation time 162618497233 ps
CPU time 314.23 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:57:43 PM PDT 24
Peak memory 210012 kb
Host smart-05543525-fdac-4426-9e71-75f5d5f8fafa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022163939 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1022163939
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1742527838
Short name T306
Test name
Test status
Simulation time 1139017556508 ps
CPU time 460.38 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 04:00:09 PM PDT 24
Peak memory 182888 kb
Host smart-70d8ae41-4e46-4de6-8fc4-c2b0ae2fe30e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742527838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1742527838
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.4042805540
Short name T450
Test name
Test status
Simulation time 635302379529 ps
CPU time 306.05 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:57:35 PM PDT 24
Peak memory 182968 kb
Host smart-577986a6-e7b4-407e-97f2-1063af82f3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042805540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.4042805540
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1713758900
Short name T235
Test name
Test status
Simulation time 185052223763 ps
CPU time 868.44 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 04:06:57 PM PDT 24
Peak memory 191072 kb
Host smart-0096ad12-7337-4fc2-885b-b5d3f5ce9aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713758900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1713758900
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1093194041
Short name T322
Test name
Test status
Simulation time 414999826452 ps
CPU time 569.33 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 04:01:59 PM PDT 24
Peak memory 191092 kb
Host smart-9488847e-b658-4675-b7e6-c2e665036b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093194041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1093194041
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2396445304
Short name T444
Test name
Test status
Simulation time 832714607784 ps
CPU time 431.78 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:59:42 PM PDT 24
Peak memory 191192 kb
Host smart-f08777a5-6c45-4e9d-96da-d05986d6a5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396445304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2396445304
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2903504998
Short name T32
Test name
Test status
Simulation time 159077619489 ps
CPU time 221.49 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:56:07 PM PDT 24
Peak memory 206988 kb
Host smart-e0d71e36-fc83-4b0a-ac1e-9b4b3ea54f20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903504998 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2903504998
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.52735115
Short name T328
Test name
Test status
Simulation time 52106754178 ps
CPU time 97.98 seconds
Started Jun 05 03:51:58 PM PDT 24
Finished Jun 05 03:53:37 PM PDT 24
Peak memory 182848 kb
Host smart-6b176805-11de-43a3-9456-71d4eab3b894
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52735115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
rv_timer_cfg_update_on_fly.52735115
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.51330895
Short name T87
Test name
Test status
Simulation time 402032950963 ps
CPU time 155.93 seconds
Started Jun 05 03:51:49 PM PDT 24
Finished Jun 05 03:54:25 PM PDT 24
Peak memory 182996 kb
Host smart-1558dc7b-2766-4f34-a3e5-16612382bd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51330895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.51330895
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.355561449
Short name T271
Test name
Test status
Simulation time 158046858837 ps
CPU time 255.25 seconds
Started Jun 05 03:51:56 PM PDT 24
Finished Jun 05 03:56:12 PM PDT 24
Peak memory 191200 kb
Host smart-350caea7-dafe-49ad-9425-70b09716c0bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355561449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.355561449
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.837604804
Short name T434
Test name
Test status
Simulation time 196063935019 ps
CPU time 199.53 seconds
Started Jun 05 03:51:57 PM PDT 24
Finished Jun 05 03:55:17 PM PDT 24
Peak memory 191088 kb
Host smart-2724f9dd-0f8f-43d5-a8a4-2f6b5539adde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837604804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.837604804
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.813452894
Short name T16
Test name
Test status
Simulation time 38392385 ps
CPU time 0.72 seconds
Started Jun 05 03:51:56 PM PDT 24
Finished Jun 05 03:51:57 PM PDT 24
Peak memory 213260 kb
Host smart-afdc3be3-e6ca-4867-ad80-2ce695f6f31b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813452894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.813452894
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1386965454
Short name T355
Test name
Test status
Simulation time 704316867345 ps
CPU time 381.64 seconds
Started Jun 05 03:52:22 PM PDT 24
Finished Jun 05 03:58:45 PM PDT 24
Peak memory 183244 kb
Host smart-35015278-3e5e-4c26-9866-ad32bf5e97df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386965454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1386965454
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3346715894
Short name T384
Test name
Test status
Simulation time 89843698824 ps
CPU time 115.67 seconds
Started Jun 05 03:52:25 PM PDT 24
Finished Jun 05 03:54:22 PM PDT 24
Peak memory 182888 kb
Host smart-0d0c6ef4-eebf-4d42-878e-580389e2c038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346715894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3346715894
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1711137365
Short name T344
Test name
Test status
Simulation time 26535806603 ps
CPU time 44.9 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:53:20 PM PDT 24
Peak memory 182984 kb
Host smart-1516acdd-dcc3-4e13-a045-0cb6130ceede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711137365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1711137365
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3948048580
Short name T23
Test name
Test status
Simulation time 189044891211 ps
CPU time 296.53 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:57:27 PM PDT 24
Peak memory 191088 kb
Host smart-4024a3e4-0308-4049-b2b5-739e0605d143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948048580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3948048580
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.180833795
Short name T57
Test name
Test status
Simulation time 18214618929 ps
CPU time 188.55 seconds
Started Jun 05 03:52:23 PM PDT 24
Finished Jun 05 03:55:33 PM PDT 24
Peak memory 197624 kb
Host smart-216ee429-3c5a-4faf-a789-9e0e3bf2fd61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180833795 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.180833795
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2272631268
Short name T334
Test name
Test status
Simulation time 39319372877 ps
CPU time 73.3 seconds
Started Jun 05 03:52:25 PM PDT 24
Finished Jun 05 03:53:39 PM PDT 24
Peak memory 183004 kb
Host smart-7d4cf1a0-f48f-4241-9872-d1f25dfbb425
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272631268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2272631268
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1679799873
Short name T374
Test name
Test status
Simulation time 151123914778 ps
CPU time 216.56 seconds
Started Jun 05 03:52:24 PM PDT 24
Finished Jun 05 03:56:02 PM PDT 24
Peak memory 182932 kb
Host smart-f40d907d-fc28-43e5-9428-daaf204c74c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679799873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1679799873
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1021779329
Short name T432
Test name
Test status
Simulation time 43474791118 ps
CPU time 77.58 seconds
Started Jun 05 03:52:26 PM PDT 24
Finished Jun 05 03:53:44 PM PDT 24
Peak memory 182872 kb
Host smart-f56ff39d-e469-466f-b939-15bf9a41d5f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021779329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1021779329
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.230168963
Short name T297
Test name
Test status
Simulation time 14511145498 ps
CPU time 15.33 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:52:45 PM PDT 24
Peak memory 182716 kb
Host smart-4be8f53c-b940-43ec-8753-65636a4d25f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230168963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.230168963
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3625655260
Short name T393
Test name
Test status
Simulation time 55969007 ps
CPU time 0.6 seconds
Started Jun 05 03:52:25 PM PDT 24
Finished Jun 05 03:52:27 PM PDT 24
Peak memory 182772 kb
Host smart-9497626f-21bf-48be-8baa-5986704879ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625655260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3625655260
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.21400033
Short name T304
Test name
Test status
Simulation time 466559326274 ps
CPU time 240.1 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:56:29 PM PDT 24
Peak memory 182872 kb
Host smart-26215a1f-60da-436d-b2e2-c73c3f663977
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21400033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.rv_timer_cfg_update_on_fly.21400033
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2407847439
Short name T411
Test name
Test status
Simulation time 76648460762 ps
CPU time 123.32 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:54:34 PM PDT 24
Peak memory 182892 kb
Host smart-ae1fd734-ab00-4ed7-9af2-96aaddf08b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407847439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2407847439
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1490974025
Short name T25
Test name
Test status
Simulation time 125083809161 ps
CPU time 1717.94 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 04:21:08 PM PDT 24
Peak memory 190896 kb
Host smart-5b372f07-65c6-48ce-bae3-23dfe6ff5b8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490974025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1490974025
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1387494188
Short name T396
Test name
Test status
Simulation time 61842726 ps
CPU time 0.67 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:52:30 PM PDT 24
Peak memory 182652 kb
Host smart-1bb5f677-ac44-47d4-81c0-1fe351608091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387494188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1387494188
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1984066643
Short name T406
Test name
Test status
Simulation time 102566640408 ps
CPU time 150.86 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:55:02 PM PDT 24
Peak memory 193724 kb
Host smart-62505f24-b8b9-4ed1-87ad-67e7d71ce322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984066643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1984066643
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.735453863
Short name T125
Test name
Test status
Simulation time 7025274070 ps
CPU time 4.06 seconds
Started Jun 05 03:52:27 PM PDT 24
Finished Jun 05 03:52:33 PM PDT 24
Peak memory 182872 kb
Host smart-7d0d05af-b4a0-4f7c-acee-099db5c6c556
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735453863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.735453863
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.998268901
Short name T422
Test name
Test status
Simulation time 831652879517 ps
CPU time 98.23 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:54:08 PM PDT 24
Peak memory 183000 kb
Host smart-fb3c0305-b9f4-431f-b9d1-dd482a472dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998268901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.998268901
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3301712766
Short name T273
Test name
Test status
Simulation time 66747595365 ps
CPU time 211.75 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:56:02 PM PDT 24
Peak memory 191076 kb
Host smart-6c0c4e40-c25b-466d-bee2-9841d9ecc1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301712766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3301712766
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2532712089
Short name T220
Test name
Test status
Simulation time 95130931978 ps
CPU time 26.55 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:52:58 PM PDT 24
Peak memory 182892 kb
Host smart-c205ceef-d13e-4020-9026-92dab8c3b5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532712089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2532712089
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2909253508
Short name T339
Test name
Test status
Simulation time 346880565633 ps
CPU time 417.76 seconds
Started Jun 05 03:52:26 PM PDT 24
Finished Jun 05 03:59:25 PM PDT 24
Peak memory 191140 kb
Host smart-06301af9-583a-4a53-ab2a-e7b48f30384f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909253508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2909253508
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.108956734
Short name T147
Test name
Test status
Simulation time 8863423487 ps
CPU time 5.3 seconds
Started Jun 05 03:52:38 PM PDT 24
Finished Jun 05 03:52:44 PM PDT 24
Peak memory 182944 kb
Host smart-1aec1789-cb18-4d08-999a-b78ae11ecc96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108956734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.108956734
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1852771783
Short name T399
Test name
Test status
Simulation time 752897047959 ps
CPU time 250.68 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 03:56:45 PM PDT 24
Peak memory 183216 kb
Host smart-dd7f8789-0511-4ad0-a76f-6c315c01ec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852771783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1852771783
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.95182639
Short name T439
Test name
Test status
Simulation time 614441292064 ps
CPU time 304.71 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 03:57:51 PM PDT 24
Peak memory 182968 kb
Host smart-cc514e0a-7123-4131-8fbb-72b332a23835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95182639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.95182639
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1663450212
Short name T416
Test name
Test status
Simulation time 142474485110 ps
CPU time 100.12 seconds
Started Jun 05 03:52:34 PM PDT 24
Finished Jun 05 03:54:15 PM PDT 24
Peak memory 182884 kb
Host smart-d9c15422-3f49-4462-b9af-e26f94748b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663450212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1663450212
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3495210582
Short name T34
Test name
Test status
Simulation time 41990350639 ps
CPU time 364.1 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 03:58:35 PM PDT 24
Peak memory 206084 kb
Host smart-a0a12523-0333-4540-a25e-2a3b85e425ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495210582 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3495210582
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2676779535
Short name T114
Test name
Test status
Simulation time 614751963052 ps
CPU time 1131.22 seconds
Started Jun 05 03:52:43 PM PDT 24
Finished Jun 05 04:11:35 PM PDT 24
Peak memory 182888 kb
Host smart-700e8db2-4d2e-420f-a5d9-4e10f00de2b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676779535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2676779535
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2018812456
Short name T394
Test name
Test status
Simulation time 168855501949 ps
CPU time 80.92 seconds
Started Jun 05 03:52:34 PM PDT 24
Finished Jun 05 03:53:56 PM PDT 24
Peak memory 182996 kb
Host smart-a347be84-9b95-4f2a-901f-435d887958f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018812456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2018812456
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1324345310
Short name T11
Test name
Test status
Simulation time 63875975853 ps
CPU time 487.45 seconds
Started Jun 05 03:52:30 PM PDT 24
Finished Jun 05 04:00:39 PM PDT 24
Peak memory 206064 kb
Host smart-305a179a-18a6-4dec-bfd5-8e9a881175a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324345310 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1324345310
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1784136595
Short name T41
Test name
Test status
Simulation time 38193178302 ps
CPU time 19.59 seconds
Started Jun 05 03:52:28 PM PDT 24
Finished Jun 05 03:52:50 PM PDT 24
Peak memory 182888 kb
Host smart-0bd5ade0-c995-446a-9d96-d5271d49620c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784136595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1784136595
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1470069648
Short name T92
Test name
Test status
Simulation time 307078938211 ps
CPU time 128.68 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 03:54:45 PM PDT 24
Peak memory 182988 kb
Host smart-4fb57ec8-3969-4a54-96b9-78b09eb4e94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470069648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1470069648
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2096992910
Short name T145
Test name
Test status
Simulation time 227175913926 ps
CPU time 678.46 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 04:03:55 PM PDT 24
Peak memory 191064 kb
Host smart-701213f7-7eef-4940-bc15-c3157cc6c900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096992910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2096992910
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4011893294
Short name T280
Test name
Test status
Simulation time 136954956020 ps
CPU time 649.51 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 04:03:22 PM PDT 24
Peak memory 194368 kb
Host smart-f1e3db18-8ba6-4434-a256-4579d929b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011893294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4011893294
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2199549517
Short name T330
Test name
Test status
Simulation time 8375008516 ps
CPU time 8.57 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 03:52:41 PM PDT 24
Peak memory 183000 kb
Host smart-dc6cc4f8-932a-416f-a855-ee56202fb1f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199549517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2199549517
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2881271604
Short name T22
Test name
Test status
Simulation time 98652616659 ps
CPU time 158.68 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:55:09 PM PDT 24
Peak memory 182868 kb
Host smart-a5f0995f-18fb-4c9f-b60c-edbb4b78b892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881271604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2881271604
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3183440907
Short name T383
Test name
Test status
Simulation time 652516634 ps
CPU time 1.28 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 03:52:34 PM PDT 24
Peak memory 182912 kb
Host smart-ef386085-45fd-4393-8a68-5dc261e956e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183440907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3183440907
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3364827628
Short name T402
Test name
Test status
Simulation time 61945734 ps
CPU time 0.59 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 03:52:32 PM PDT 24
Peak memory 182720 kb
Host smart-884d8323-9824-431f-bf01-0cc05ad5975a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364827628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3364827628
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_random.4070794029
Short name T291
Test name
Test status
Simulation time 254787138470 ps
CPU time 1554.91 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 04:18:33 PM PDT 24
Peak memory 191156 kb
Host smart-22ef8473-1f13-4eef-a505-220273269177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070794029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.4070794029
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.98495425
Short name T313
Test name
Test status
Simulation time 553736648081 ps
CPU time 193.03 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 03:55:51 PM PDT 24
Peak memory 191148 kb
Host smart-c113e155-8c6a-432d-87ce-0b5c15061f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98495425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.98495425
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1940193779
Short name T110
Test name
Test status
Simulation time 147480271105 ps
CPU time 440.3 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:59:56 PM PDT 24
Peak memory 195552 kb
Host smart-b0ba6ce3-285b-4c14-8672-a25b13d7d066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940193779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1940193779
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1179009910
Short name T169
Test name
Test status
Simulation time 320082102542 ps
CPU time 174.69 seconds
Started Jun 05 03:52:38 PM PDT 24
Finished Jun 05 03:55:34 PM PDT 24
Peak memory 183000 kb
Host smart-0f5cf419-7232-4f21-b596-7aca25ff4625
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179009910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1179009910
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.497443608
Short name T423
Test name
Test status
Simulation time 126938014650 ps
CPU time 53.7 seconds
Started Jun 05 03:52:29 PM PDT 24
Finished Jun 05 03:53:24 PM PDT 24
Peak memory 182992 kb
Host smart-d8937d07-bdb1-4755-aea5-17fbaca1e9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497443608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.497443608
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2173488538
Short name T442
Test name
Test status
Simulation time 161439023610 ps
CPU time 85.7 seconds
Started Jun 05 03:52:34 PM PDT 24
Finished Jun 05 03:54:01 PM PDT 24
Peak memory 182984 kb
Host smart-b5cc61a6-6527-41a3-86c1-a7dfa3f74673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173488538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2173488538
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.4129831375
Short name T372
Test name
Test status
Simulation time 294875438 ps
CPU time 0.66 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:52:36 PM PDT 24
Peak memory 182676 kb
Host smart-c5f5f38e-15dc-4574-b008-316c7fee6bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129831375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4129831375
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1436909406
Short name T119
Test name
Test status
Simulation time 2627080420769 ps
CPU time 1315.66 seconds
Started Jun 05 03:51:50 PM PDT 24
Finished Jun 05 04:13:47 PM PDT 24
Peak memory 182872 kb
Host smart-559d5f7f-059e-435e-b48e-453bfc8cc0ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436909406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1436909406
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1620001495
Short name T400
Test name
Test status
Simulation time 780689583786 ps
CPU time 347.26 seconds
Started Jun 05 03:51:57 PM PDT 24
Finished Jun 05 03:57:45 PM PDT 24
Peak memory 182888 kb
Host smart-62ef4d23-7b83-4bc4-9b52-696e847c66c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620001495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1620001495
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.4152172893
Short name T319
Test name
Test status
Simulation time 609906761379 ps
CPU time 310.95 seconds
Started Jun 05 03:51:53 PM PDT 24
Finished Jun 05 03:57:05 PM PDT 24
Peak memory 191072 kb
Host smart-7db3f961-6a9c-4cba-92f9-fd4ed969e4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152172893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.4152172893
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2390784473
Short name T186
Test name
Test status
Simulation time 34612910071 ps
CPU time 139.62 seconds
Started Jun 05 03:51:51 PM PDT 24
Finished Jun 05 03:54:11 PM PDT 24
Peak memory 191152 kb
Host smart-c17d7d2c-e1ff-465d-8f4d-55cbe9c32067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390784473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2390784473
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1521953123
Short name T44
Test name
Test status
Simulation time 94712719 ps
CPU time 0.6 seconds
Started Jun 05 03:51:54 PM PDT 24
Finished Jun 05 03:51:55 PM PDT 24
Peak memory 182644 kb
Host smart-895d3aed-5976-4d05-a406-daa3d4dcc7c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521953123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1521953123
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1168657731
Short name T24
Test name
Test status
Simulation time 28331771831 ps
CPU time 316.1 seconds
Started Jun 05 03:51:57 PM PDT 24
Finished Jun 05 03:57:14 PM PDT 24
Peak memory 197500 kb
Host smart-60adcbf5-f3e5-4ee8-bd92-044b02a53d05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168657731 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1168657731
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.341487504
Short name T285
Test name
Test status
Simulation time 169778135176 ps
CPU time 1545.66 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 04:18:18 PM PDT 24
Peak memory 182968 kb
Host smart-1568307a-b618-421b-b81a-a09be7303bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341487504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.341487504
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3233571084
Short name T357
Test name
Test status
Simulation time 76773209227 ps
CPU time 122.39 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 03:54:35 PM PDT 24
Peak memory 191172 kb
Host smart-8561ab2c-cbaf-4318-822c-51ee66f0134c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233571084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3233571084
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1113355672
Short name T202
Test name
Test status
Simulation time 44144608062 ps
CPU time 20.84 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 03:53:07 PM PDT 24
Peak memory 194560 kb
Host smart-285031ab-f7de-4498-ad77-6fc7401eac1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113355672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1113355672
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3190239049
Short name T325
Test name
Test status
Simulation time 9338291940 ps
CPU time 8.39 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:52:44 PM PDT 24
Peak memory 182868 kb
Host smart-17471562-a51b-4c2c-bc56-ddcf1d182320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190239049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3190239049
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2109203485
Short name T345
Test name
Test status
Simulation time 182897711587 ps
CPU time 168.08 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:55:24 PM PDT 24
Peak memory 191068 kb
Host smart-f2fd75a3-bd6d-4dcc-a713-8129e84447ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109203485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2109203485
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3977353074
Short name T221
Test name
Test status
Simulation time 147866138810 ps
CPU time 56.99 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 03:53:43 PM PDT 24
Peak memory 191136 kb
Host smart-05e461ca-a13d-4575-91b7-d49522d13fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977353074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3977353074
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.5760196
Short name T121
Test name
Test status
Simulation time 144138087376 ps
CPU time 72.8 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:53:49 PM PDT 24
Peak memory 182876 kb
Host smart-00962c6b-70d8-4f7f-aace-cc55fb0746d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5760196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.5760196
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2548548647
Short name T295
Test name
Test status
Simulation time 198723406290 ps
CPU time 450.68 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 04:00:04 PM PDT 24
Peak memory 191184 kb
Host smart-0e61ccb4-3b67-4b55-b94b-b787a125a241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548548647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2548548647
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2103566423
Short name T360
Test name
Test status
Simulation time 6477318906 ps
CPU time 11.43 seconds
Started Jun 05 03:51:52 PM PDT 24
Finished Jun 05 03:52:04 PM PDT 24
Peak memory 182876 kb
Host smart-cd71e317-f574-4139-bef1-350d0fbd75a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103566423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2103566423
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2242474207
Short name T375
Test name
Test status
Simulation time 144981218241 ps
CPU time 204.01 seconds
Started Jun 05 03:51:56 PM PDT 24
Finished Jun 05 03:55:21 PM PDT 24
Peak memory 182996 kb
Host smart-20bf4e38-86c8-4cbe-9b32-99eda61a6fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242474207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2242474207
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.4128543946
Short name T117
Test name
Test status
Simulation time 145200850083 ps
CPU time 644.13 seconds
Started Jun 05 03:51:59 PM PDT 24
Finished Jun 05 04:02:44 PM PDT 24
Peak memory 191076 kb
Host smart-678bf9f9-63b8-41d5-b725-b4e051b588e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128543946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.4128543946
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2355708197
Short name T134
Test name
Test status
Simulation time 68317643984 ps
CPU time 34.39 seconds
Started Jun 05 03:51:57 PM PDT 24
Finished Jun 05 03:52:32 PM PDT 24
Peak memory 191076 kb
Host smart-3d3911dd-76ec-43ef-afe4-b379c3159370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355708197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2355708197
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.4267334526
Short name T259
Test name
Test status
Simulation time 425612049634 ps
CPU time 806.41 seconds
Started Jun 05 03:51:49 PM PDT 24
Finished Jun 05 04:05:17 PM PDT 24
Peak memory 191188 kb
Host smart-6ba8ea60-be88-4f9d-8d1d-bf1df3486cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267334526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
4267334526
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3147016745
Short name T127
Test name
Test status
Simulation time 46870184797 ps
CPU time 1117.08 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 04:11:15 PM PDT 24
Peak memory 191072 kb
Host smart-4579c285-4f40-45b0-adf3-83f666f3290d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147016745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3147016745
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.859080532
Short name T123
Test name
Test status
Simulation time 485828882855 ps
CPU time 723.82 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 04:04:41 PM PDT 24
Peak memory 191060 kb
Host smart-d4fc024b-9389-4835-908f-8611db97ac56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859080532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.859080532
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.349309344
Short name T317
Test name
Test status
Simulation time 43684227307 ps
CPU time 71.06 seconds
Started Jun 05 03:52:38 PM PDT 24
Finished Jun 05 03:53:49 PM PDT 24
Peak memory 182924 kb
Host smart-2a7785cb-21fe-4cd3-b2b2-4ae6eca0e5ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349309344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.349309344
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1622412671
Short name T152
Test name
Test status
Simulation time 216099718550 ps
CPU time 87.65 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 03:54:02 PM PDT 24
Peak memory 191176 kb
Host smart-7ce26c20-954b-45d0-8f97-3634484b456c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622412671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1622412671
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3986916133
Short name T409
Test name
Test status
Simulation time 174283358741 ps
CPU time 276.31 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 03:57:09 PM PDT 24
Peak memory 191184 kb
Host smart-629315d7-4c77-40cd-9530-5ded6a3db295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986916133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3986916133
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2535618277
Short name T338
Test name
Test status
Simulation time 155782794519 ps
CPU time 75.39 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 03:53:59 PM PDT 24
Peak memory 182984 kb
Host smart-184b76bf-9e9b-4afe-bdc9-d03e9b54ce45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535618277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2535618277
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3945571924
Short name T174
Test name
Test status
Simulation time 367179232026 ps
CPU time 168.64 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 03:55:31 PM PDT 24
Peak memory 191128 kb
Host smart-0d877929-a0e2-43c6-9b10-292e532e7900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945571924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3945571924
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1285758245
Short name T233
Test name
Test status
Simulation time 370219009287 ps
CPU time 2282.78 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 04:30:49 PM PDT 24
Peak memory 191184 kb
Host smart-db2591ca-f619-4c1b-ac17-657bec93ce83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285758245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1285758245
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3037669482
Short name T300
Test name
Test status
Simulation time 201669817752 ps
CPU time 164.82 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 03:55:18 PM PDT 24
Peak memory 191184 kb
Host smart-368ef7cd-06f4-4b5d-8333-96a470768722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037669482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3037669482
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.490848679
Short name T287
Test name
Test status
Simulation time 18323830406 ps
CPU time 29.9 seconds
Started Jun 05 03:52:03 PM PDT 24
Finished Jun 05 03:52:34 PM PDT 24
Peak memory 182856 kb
Host smart-cf07102f-e531-4424-aa2f-5fe09cf8187d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490848679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.490848679
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3872099342
Short name T391
Test name
Test status
Simulation time 161412135547 ps
CPU time 70.23 seconds
Started Jun 05 03:52:00 PM PDT 24
Finished Jun 05 03:53:11 PM PDT 24
Peak memory 182996 kb
Host smart-7e2f30ac-41bf-4b60-b058-ba720d39b889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872099342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3872099342
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1488550435
Short name T428
Test name
Test status
Simulation time 96068649235 ps
CPU time 91.12 seconds
Started Jun 05 03:51:55 PM PDT 24
Finished Jun 05 03:53:27 PM PDT 24
Peak memory 191212 kb
Host smart-36e6b91a-4315-40c3-9ede-697a3d2601e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488550435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1488550435
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2674340013
Short name T232
Test name
Test status
Simulation time 31252840404 ps
CPU time 269.94 seconds
Started Jun 05 03:51:55 PM PDT 24
Finished Jun 05 03:56:25 PM PDT 24
Peak memory 191192 kb
Host smart-d09eb7df-63c4-47d6-a545-0a8603ecf6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674340013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2674340013
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2095684442
Short name T260
Test name
Test status
Simulation time 574729750316 ps
CPU time 367.42 seconds
Started Jun 05 03:51:58 PM PDT 24
Finished Jun 05 03:58:06 PM PDT 24
Peak memory 194732 kb
Host smart-065dca93-e397-418b-ac34-c7a3808cd3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095684442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2095684442
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3577270781
Short name T124
Test name
Test status
Simulation time 749292506973 ps
CPU time 850.56 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 04:06:44 PM PDT 24
Peak memory 191184 kb
Host smart-2de1d039-d715-4d75-b655-b6d0513233fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577270781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3577270781
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3811379087
Short name T108
Test name
Test status
Simulation time 579128755532 ps
CPU time 188.29 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 03:55:40 PM PDT 24
Peak memory 191080 kb
Host smart-bfb16c13-8670-40a2-8f89-1ba2ed9bf020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811379087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3811379087
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.229862828
Short name T336
Test name
Test status
Simulation time 38747235745 ps
CPU time 311.46 seconds
Started Jun 05 03:52:42 PM PDT 24
Finished Jun 05 03:57:55 PM PDT 24
Peak memory 182868 kb
Host smart-26523d6c-80d1-49b5-b490-b862086c7271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229862828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.229862828
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3152327460
Short name T88
Test name
Test status
Simulation time 36247811816 ps
CPU time 31.98 seconds
Started Jun 05 03:52:47 PM PDT 24
Finished Jun 05 03:53:20 PM PDT 24
Peak memory 182984 kb
Host smart-7996c88a-8e42-4153-af75-61bb675176a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152327460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3152327460
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1368548040
Short name T211
Test name
Test status
Simulation time 497947724934 ps
CPU time 422.62 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 03:59:41 PM PDT 24
Peak memory 191000 kb
Host smart-54762478-e7ab-4226-a62a-5c12d05786ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368548040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1368548040
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.163342115
Short name T326
Test name
Test status
Simulation time 52619183989 ps
CPU time 102.96 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 03:54:15 PM PDT 24
Peak memory 182860 kb
Host smart-c88bf415-c6c0-49cb-92cf-27c74587463b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163342115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.163342115
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.668013694
Short name T248
Test name
Test status
Simulation time 309630123419 ps
CPU time 203.75 seconds
Started Jun 05 03:52:34 PM PDT 24
Finished Jun 05 03:55:59 PM PDT 24
Peak memory 194724 kb
Host smart-9f2ff536-3a1a-44d2-a3b7-821d524e47b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668013694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.668013694
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.364928684
Short name T115
Test name
Test status
Simulation time 210484982885 ps
CPU time 375.78 seconds
Started Jun 05 03:51:58 PM PDT 24
Finished Jun 05 03:58:15 PM PDT 24
Peak memory 182872 kb
Host smart-94cc49ce-016e-4230-af94-204ff1c407ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364928684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.364928684
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3939543503
Short name T387
Test name
Test status
Simulation time 76463868573 ps
CPU time 53.47 seconds
Started Jun 05 03:52:00 PM PDT 24
Finished Jun 05 03:52:54 PM PDT 24
Peak memory 182888 kb
Host smart-69f96742-8f4d-4f13-8550-71b19b521325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939543503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3939543503
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.140021192
Short name T228
Test name
Test status
Simulation time 381863432563 ps
CPU time 1002.8 seconds
Started Jun 05 03:51:57 PM PDT 24
Finished Jun 05 04:08:41 PM PDT 24
Peak memory 191452 kb
Host smart-95f57d82-448e-4b50-a927-23b6e40caa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140021192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.140021192
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2514450494
Short name T397
Test name
Test status
Simulation time 419199617456 ps
CPU time 190.59 seconds
Started Jun 05 03:52:04 PM PDT 24
Finished Jun 05 03:55:15 PM PDT 24
Peak memory 182868 kb
Host smart-7b4ad74a-d8ba-4553-8799-8c74e07c058d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514450494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2514450494
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3093437137
Short name T348
Test name
Test status
Simulation time 39560208788 ps
CPU time 1420.33 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 04:16:15 PM PDT 24
Peak memory 182980 kb
Host smart-10d43ed2-dcb2-44ea-a349-6c9dae7ee9b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093437137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3093437137
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1652240384
Short name T187
Test name
Test status
Simulation time 191301345977 ps
CPU time 822.23 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 04:06:19 PM PDT 24
Peak memory 191072 kb
Host smart-d0663411-c423-4de0-96c0-abcc3b60e409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652240384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1652240384
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.391454516
Short name T181
Test name
Test status
Simulation time 233366160497 ps
CPU time 1045.91 seconds
Started Jun 05 03:52:37 PM PDT 24
Finished Jun 05 04:10:04 PM PDT 24
Peak memory 190956 kb
Host smart-15f856c4-150b-4f4b-acd7-8dfbc708824a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391454516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.391454516
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1557317083
Short name T135
Test name
Test status
Simulation time 890295790926 ps
CPU time 507.19 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 04:01:03 PM PDT 24
Peak memory 191184 kb
Host smart-36d99915-d256-44a4-bfc4-21578a4d4609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557317083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1557317083
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.574718147
Short name T390
Test name
Test status
Simulation time 44908153258 ps
CPU time 69.04 seconds
Started Jun 05 03:52:51 PM PDT 24
Finished Jun 05 03:54:01 PM PDT 24
Peak memory 182868 kb
Host smart-52ac869a-e099-4d1c-962a-ff71e90c0b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574718147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.574718147
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2942987915
Short name T449
Test name
Test status
Simulation time 687131399531 ps
CPU time 613.47 seconds
Started Jun 05 03:52:31 PM PDT 24
Finished Jun 05 04:02:46 PM PDT 24
Peak memory 191188 kb
Host smart-856f8608-86e6-4d79-8ea1-aab9d06b490f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942987915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2942987915
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.772388672
Short name T275
Test name
Test status
Simulation time 100314488907 ps
CPU time 166.77 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 03:55:20 PM PDT 24
Peak memory 191128 kb
Host smart-6c7847b8-b349-45a9-a7be-41d2d0dcd46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772388672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.772388672
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2263262737
Short name T349
Test name
Test status
Simulation time 127915637611 ps
CPU time 316.17 seconds
Started Jun 05 03:52:34 PM PDT 24
Finished Jun 05 03:57:51 PM PDT 24
Peak memory 191068 kb
Host smart-c276e068-3cbe-4c83-be5e-8dc770caa7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263262737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2263262737
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.609707958
Short name T7
Test name
Test status
Simulation time 378167990808 ps
CPU time 901.74 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 04:07:39 PM PDT 24
Peak memory 193688 kb
Host smart-a66808ef-4ffa-4693-8797-a7666a465452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609707958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.609707958
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.626504323
Short name T373
Test name
Test status
Simulation time 286142538862 ps
CPU time 109.29 seconds
Started Jun 05 03:51:59 PM PDT 24
Finished Jun 05 03:53:49 PM PDT 24
Peak memory 182868 kb
Host smart-84ca2d18-19f0-4add-b912-f1af93023a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626504323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.626504323
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1924570912
Short name T341
Test name
Test status
Simulation time 8311516545 ps
CPU time 14.08 seconds
Started Jun 05 03:52:08 PM PDT 24
Finished Jun 05 03:52:23 PM PDT 24
Peak memory 182872 kb
Host smart-d9b6da0a-fa8a-4831-9ad0-1d7999439b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924570912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1924570912
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3061356
Short name T303
Test name
Test status
Simulation time 882963833108 ps
CPU time 517.15 seconds
Started Jun 05 03:52:09 PM PDT 24
Finished Jun 05 04:00:47 PM PDT 24
Peak memory 182888 kb
Host smart-74c5f321-11c8-4b6c-82dd-5eb83921f165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3061356
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1304623803
Short name T172
Test name
Test status
Simulation time 311806487658 ps
CPU time 686.5 seconds
Started Jun 05 03:52:11 PM PDT 24
Finished Jun 05 04:03:38 PM PDT 24
Peak memory 191072 kb
Host smart-d1ccc3b3-0d1c-4288-bc6b-0eecb517173f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304623803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1304623803
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.582980720
Short name T37
Test name
Test status
Simulation time 100831842518 ps
CPU time 271.14 seconds
Started Jun 05 03:52:32 PM PDT 24
Finished Jun 05 03:57:05 PM PDT 24
Peak memory 183268 kb
Host smart-2ef4d132-5a6d-49f8-a3e1-46eb02fb6995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582980720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.582980720
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.423853814
Short name T136
Test name
Test status
Simulation time 113417286574 ps
CPU time 260.74 seconds
Started Jun 05 03:52:33 PM PDT 24
Finished Jun 05 03:56:55 PM PDT 24
Peak memory 191060 kb
Host smart-50425c72-a342-4d53-99d5-a93db6713dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423853814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.423853814
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2502509780
Short name T350
Test name
Test status
Simulation time 49304861658 ps
CPU time 830.79 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 04:06:27 PM PDT 24
Peak memory 191076 kb
Host smart-70762d44-7a28-4313-a169-d3c72c6646da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502509780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2502509780
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3727439063
Short name T294
Test name
Test status
Simulation time 35814662013 ps
CPU time 60.13 seconds
Started Jun 05 03:52:35 PM PDT 24
Finished Jun 05 03:53:36 PM PDT 24
Peak memory 182964 kb
Host smart-57f70385-6db5-42f4-836f-d2abc67f5d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727439063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3727439063
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2247247546
Short name T100
Test name
Test status
Simulation time 219569322132 ps
CPU time 314.34 seconds
Started Jun 05 03:52:40 PM PDT 24
Finished Jun 05 03:57:55 PM PDT 24
Peak memory 191080 kb
Host smart-74beb942-29f5-432a-b50e-6621c0fd1b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247247546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2247247546
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3150128659
Short name T158
Test name
Test status
Simulation time 138588929034 ps
CPU time 431.82 seconds
Started Jun 05 03:52:45 PM PDT 24
Finished Jun 05 03:59:58 PM PDT 24
Peak memory 194256 kb
Host smart-b7d8706f-1815-4024-830f-dbf6973cb4f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150128659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3150128659
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1231963071
Short name T140
Test name
Test status
Simulation time 200535239488 ps
CPU time 116.12 seconds
Started Jun 05 03:52:36 PM PDT 24
Finished Jun 05 03:54:33 PM PDT 24
Peak memory 191184 kb
Host smart-22cee652-deb5-4a61-b21e-ee5041ba7e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231963071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1231963071
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2032302955
Short name T246
Test name
Test status
Simulation time 650949591484 ps
CPU time 326.92 seconds
Started Jun 05 03:52:40 PM PDT 24
Finished Jun 05 03:58:08 PM PDT 24
Peak memory 191164 kb
Host smart-20f4062d-4933-46f3-bccd-e9ecea760ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032302955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2032302955
Directory /workspace/99.rv_timer_random/latest
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