Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
135678334 |
1 |
|
T1 |
37 |
|
T2 |
275680 |
|
T3 |
23504 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
72445801 |
1 |
|
T1 |
37 |
|
T2 |
21420 |
|
T3 |
23443 |
auto[1] |
63232533 |
1 |
|
T2 |
254260 |
|
T3 |
61 |
|
T4 |
68535 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
135672278 |
1 |
|
T1 |
37 |
|
T2 |
275667 |
|
T3 |
23500 |
auto[1] |
6056 |
1 |
|
T2 |
13 |
|
T3 |
4 |
|
T4 |
14 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
72442637 |
1 |
|
T1 |
37 |
|
T2 |
21416 |
|
T3 |
23441 |
all_values[0] |
auto[0] |
auto[1] |
3164 |
1 |
|
T2 |
4 |
|
T3 |
2 |
|
T4 |
7 |
all_values[0] |
auto[1] |
auto[0] |
63229641 |
1 |
|
T2 |
254251 |
|
T3 |
59 |
|
T4 |
68528 |
all_values[0] |
auto[1] |
auto[1] |
2892 |
1 |
|
T2 |
9 |
|
T3 |
2 |
|
T4 |
7 |