Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
1295 |
1 |
|
T10 |
4 |
|
T32 |
11 |
|
T11 |
27 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
726 |
1 |
|
T10 |
2 |
|
T32 |
5 |
|
T11 |
17 |
auto[1] |
569 |
1 |
|
T10 |
2 |
|
T32 |
6 |
|
T11 |
10 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
492 |
1 |
|
T10 |
1 |
|
T32 |
4 |
|
T11 |
4 |
auto[1] |
803 |
1 |
|
T10 |
3 |
|
T32 |
7 |
|
T11 |
23 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
738 |
1 |
|
T10 |
1 |
|
T32 |
5 |
|
T11 |
10 |
auto[1] |
557 |
1 |
|
T10 |
3 |
|
T32 |
6 |
|
T11 |
17 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
273 |
1 |
|
T32 |
1 |
|
T11 |
3 |
|
T44 |
2 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
140 |
1 |
|
T32 |
1 |
|
T11 |
5 |
|
T44 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
219 |
1 |
|
T10 |
1 |
|
T32 |
3 |
|
T11 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
106 |
1 |
|
T11 |
1 |
|
T12 |
1 |
|
T65 |
2 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
313 |
1 |
|
T10 |
2 |
|
T32 |
3 |
|
T11 |
9 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
244 |
1 |
|
T10 |
1 |
|
T32 |
3 |
|
T11 |
8 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |