Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 585
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T510 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2323975900 Jun 06 01:16:35 PM PDT 24 Jun 06 01:16:37 PM PDT 24 55955014 ps
T95 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3519042950 Jun 06 01:16:34 PM PDT 24 Jun 06 01:16:36 PM PDT 24 12687726 ps
T511 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.106407695 Jun 06 01:16:24 PM PDT 24 Jun 06 01:16:27 PM PDT 24 502708509 ps
T512 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.490860083 Jun 06 01:16:33 PM PDT 24 Jun 06 01:16:35 PM PDT 24 115374006 ps
T513 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3833138736 Jun 06 01:16:33 PM PDT 24 Jun 06 01:16:37 PM PDT 24 754522277 ps
T514 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2226605060 Jun 06 01:15:55 PM PDT 24 Jun 06 01:15:57 PM PDT 24 12954938 ps
T515 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2795875950 Jun 06 01:16:06 PM PDT 24 Jun 06 01:16:08 PM PDT 24 14457327 ps
T516 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1169747983 Jun 06 01:16:25 PM PDT 24 Jun 06 01:16:28 PM PDT 24 107945801 ps
T517 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2449995867 Jun 06 01:16:25 PM PDT 24 Jun 06 01:16:27 PM PDT 24 19597448 ps
T518 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.528220469 Jun 06 01:16:23 PM PDT 24 Jun 06 01:16:25 PM PDT 24 100718569 ps
T519 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.247476314 Jun 06 01:16:43 PM PDT 24 Jun 06 01:16:45 PM PDT 24 15273876 ps
T520 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.892961038 Jun 06 01:16:19 PM PDT 24 Jun 06 01:16:21 PM PDT 24 11755978 ps
T521 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3171146276 Jun 06 01:16:26 PM PDT 24 Jun 06 01:16:27 PM PDT 24 187418120 ps
T522 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3687987501 Jun 06 01:16:46 PM PDT 24 Jun 06 01:16:47 PM PDT 24 54014099 ps
T523 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.460465339 Jun 06 01:15:54 PM PDT 24 Jun 06 01:15:56 PM PDT 24 14470942 ps
T524 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.705702966 Jun 06 01:16:42 PM PDT 24 Jun 06 01:16:44 PM PDT 24 44737491 ps
T525 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.4109588206 Jun 06 01:16:05 PM PDT 24 Jun 06 01:16:07 PM PDT 24 378812414 ps
T96 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1449788004 Jun 06 01:15:54 PM PDT 24 Jun 06 01:15:55 PM PDT 24 58582184 ps
T526 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4210691873 Jun 06 01:16:48 PM PDT 24 Jun 06 01:16:49 PM PDT 24 15140451 ps
T527 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.455504872 Jun 06 01:15:55 PM PDT 24 Jun 06 01:15:57 PM PDT 24 25701693 ps
T528 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1126796681 Jun 06 01:16:24 PM PDT 24 Jun 06 01:16:25 PM PDT 24 28140341 ps
T529 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4137004501 Jun 06 01:15:55 PM PDT 24 Jun 06 01:15:57 PM PDT 24 38708426 ps
T123 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3948994234 Jun 06 01:16:33 PM PDT 24 Jun 06 01:16:35 PM PDT 24 76215227 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1447864264 Jun 06 01:15:55 PM PDT 24 Jun 06 01:15:57 PM PDT 24 314812653 ps
T531 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1561675821 Jun 06 01:16:16 PM PDT 24 Jun 06 01:16:19 PM PDT 24 40197196 ps
T532 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.190522208 Jun 06 01:16:18 PM PDT 24 Jun 06 01:16:20 PM PDT 24 37937884 ps
T533 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2661720160 Jun 06 01:16:32 PM PDT 24 Jun 06 01:16:33 PM PDT 24 56968617 ps
T534 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3055432690 Jun 06 01:16:18 PM PDT 24 Jun 06 01:16:20 PM PDT 24 19903493 ps
T535 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3147345321 Jun 06 01:16:33 PM PDT 24 Jun 06 01:16:35 PM PDT 24 30267714 ps
T536 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2752650201 Jun 06 01:16:32 PM PDT 24 Jun 06 01:16:34 PM PDT 24 11608642 ps
T537 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3652546460 Jun 06 01:16:29 PM PDT 24 Jun 06 01:16:31 PM PDT 24 12403304 ps
T538 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3395592519 Jun 06 01:16:41 PM PDT 24 Jun 06 01:16:43 PM PDT 24 19941933 ps
T539 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2957686302 Jun 06 01:16:41 PM PDT 24 Jun 06 01:16:43 PM PDT 24 223374307 ps
T540 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1109125821 Jun 06 01:16:08 PM PDT 24 Jun 06 01:16:11 PM PDT 24 55160346 ps
T541 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3426759270 Jun 06 01:15:56 PM PDT 24 Jun 06 01:15:59 PM PDT 24 109686457 ps
T542 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3066008475 Jun 06 01:16:29 PM PDT 24 Jun 06 01:16:32 PM PDT 24 37941744 ps
T543 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1598380072 Jun 06 01:16:08 PM PDT 24 Jun 06 01:16:10 PM PDT 24 229779228 ps
T97 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1305709425 Jun 06 01:16:07 PM PDT 24 Jun 06 01:16:09 PM PDT 24 14046858 ps
T544 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3873152458 Jun 06 01:16:34 PM PDT 24 Jun 06 01:16:36 PM PDT 24 41372156 ps
T545 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3289335607 Jun 06 01:16:25 PM PDT 24 Jun 06 01:16:28 PM PDT 24 41949006 ps
T546 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3148500232 Jun 06 01:16:18 PM PDT 24 Jun 06 01:16:21 PM PDT 24 22354971 ps
T547 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.252014719 Jun 06 01:16:17 PM PDT 24 Jun 06 01:16:19 PM PDT 24 24879560 ps
T98 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.217363519 Jun 06 01:15:57 PM PDT 24 Jun 06 01:15:59 PM PDT 24 86952391 ps
T548 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3169717064 Jun 06 01:16:32 PM PDT 24 Jun 06 01:16:34 PM PDT 24 66127760 ps
T549 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.417321209 Jun 06 01:15:55 PM PDT 24 Jun 06 01:15:57 PM PDT 24 57816815 ps
T119 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3168756332 Jun 06 01:16:07 PM PDT 24 Jun 06 01:16:09 PM PDT 24 305976738 ps
T120 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1950593236 Jun 06 01:16:41 PM PDT 24 Jun 06 01:16:43 PM PDT 24 306608131 ps
T550 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3444465385 Jun 06 01:16:34 PM PDT 24 Jun 06 01:16:36 PM PDT 24 29748970 ps
T551 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2352539535 Jun 06 01:16:25 PM PDT 24 Jun 06 01:16:27 PM PDT 24 52465196 ps
T552 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3115792453 Jun 06 01:16:42 PM PDT 24 Jun 06 01:16:44 PM PDT 24 22279128 ps
T553 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2530477551 Jun 06 01:16:35 PM PDT 24 Jun 06 01:16:37 PM PDT 24 23985454 ps
T99 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3693174427 Jun 06 01:16:08 PM PDT 24 Jun 06 01:16:10 PM PDT 24 86648001 ps
T554 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2168642609 Jun 06 01:16:06 PM PDT 24 Jun 06 01:16:07 PM PDT 24 165788700 ps
T555 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3859998699 Jun 06 01:15:55 PM PDT 24 Jun 06 01:15:57 PM PDT 24 32553046 ps
T556 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.762291608 Jun 06 01:16:07 PM PDT 24 Jun 06 01:16:10 PM PDT 24 315603384 ps
T557 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3865464805 Jun 06 01:15:56 PM PDT 24 Jun 06 01:15:59 PM PDT 24 460119444 ps
T558 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2869572746 Jun 06 01:16:36 PM PDT 24 Jun 06 01:16:38 PM PDT 24 64852246 ps
T559 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1531616397 Jun 06 01:16:15 PM PDT 24 Jun 06 01:16:18 PM PDT 24 101139278 ps
T560 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.780182164 Jun 06 01:16:15 PM PDT 24 Jun 06 01:16:18 PM PDT 24 624876608 ps
T561 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4131454434 Jun 06 01:16:24 PM PDT 24 Jun 06 01:16:25 PM PDT 24 181262751 ps
T562 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3020963043 Jun 06 01:16:06 PM PDT 24 Jun 06 01:16:07 PM PDT 24 15148889 ps
T563 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2078551486 Jun 06 01:16:41 PM PDT 24 Jun 06 01:16:42 PM PDT 24 16455811 ps
T564 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2848017636 Jun 06 01:16:09 PM PDT 24 Jun 06 01:16:11 PM PDT 24 20724373 ps
T565 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3836551414 Jun 06 01:16:18 PM PDT 24 Jun 06 01:16:21 PM PDT 24 187335006 ps
T566 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.534825399 Jun 06 01:16:09 PM PDT 24 Jun 06 01:16:11 PM PDT 24 14194191 ps
T567 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1559270770 Jun 06 01:16:42 PM PDT 24 Jun 06 01:16:44 PM PDT 24 27279339 ps
T568 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.200057852 Jun 06 01:16:42 PM PDT 24 Jun 06 01:16:45 PM PDT 24 11088462 ps
T100 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2107579809 Jun 06 01:16:28 PM PDT 24 Jun 06 01:16:30 PM PDT 24 48926220 ps
T569 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2012038444 Jun 06 01:16:30 PM PDT 24 Jun 06 01:16:32 PM PDT 24 44234143 ps
T570 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3853765711 Jun 06 01:16:17 PM PDT 24 Jun 06 01:16:19 PM PDT 24 26736399 ps
T571 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.742631230 Jun 06 01:16:07 PM PDT 24 Jun 06 01:16:09 PM PDT 24 24083708 ps
T572 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.744955408 Jun 06 01:16:32 PM PDT 24 Jun 06 01:16:33 PM PDT 24 78664578 ps
T573 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.234438803 Jun 06 01:16:18 PM PDT 24 Jun 06 01:16:21 PM PDT 24 35784865 ps
T574 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3769229324 Jun 06 01:16:08 PM PDT 24 Jun 06 01:16:10 PM PDT 24 27351678 ps
T575 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1455553816 Jun 06 01:16:41 PM PDT 24 Jun 06 01:16:43 PM PDT 24 27917040 ps
T576 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1879500074 Jun 06 01:16:05 PM PDT 24 Jun 06 01:16:08 PM PDT 24 305697396 ps
T577 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4177925108 Jun 06 01:16:30 PM PDT 24 Jun 06 01:16:32 PM PDT 24 26987069 ps
T578 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1272253423 Jun 06 01:15:56 PM PDT 24 Jun 06 01:15:58 PM PDT 24 41911665 ps
T579 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1087971749 Jun 06 01:16:23 PM PDT 24 Jun 06 01:16:24 PM PDT 24 46197626 ps
T580 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3400525301 Jun 06 01:15:56 PM PDT 24 Jun 06 01:15:58 PM PDT 24 14522431 ps
T581 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3727812037 Jun 06 01:16:10 PM PDT 24 Jun 06 01:16:12 PM PDT 24 24227227 ps
T582 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.48210199 Jun 06 01:16:31 PM PDT 24 Jun 06 01:16:33 PM PDT 24 35514855 ps
T583 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3787253863 Jun 06 01:15:54 PM PDT 24 Jun 06 01:15:55 PM PDT 24 43014760 ps
T584 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2318209074 Jun 06 01:16:25 PM PDT 24 Jun 06 01:16:29 PM PDT 24 60462978 ps
T585 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3782297374 Jun 06 01:16:44 PM PDT 24 Jun 06 01:16:46 PM PDT 24 16415124 ps

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.4179907053
Short name T10
Test name
Test status
Simulation time 81085863467 ps
CPU time 210.69 seconds
Started Jun 06 02:21:12 PM PDT 24
Finished Jun 06 02:24:48 PM PDT 24
Peak memory 197680 kb
Host smart-649caa7c-bdab-4c11-ad6b-8565e8af6872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179907053 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.4179907053
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1052943284
Short name T4
Test name
Test status
Simulation time 152089447579 ps
CPU time 548.98 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:30:19 PM PDT 24
Peak memory 191208 kb
Host smart-732506b7-c5b1-4159-bab6-4e87137b5a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052943284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1052943284
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3727268666
Short name T66
Test name
Test status
Simulation time 2199034112661 ps
CPU time 1478.92 seconds
Started Jun 06 02:20:42 PM PDT 24
Finished Jun 06 02:45:23 PM PDT 24
Peak memory 191260 kb
Host smart-b9d3446d-1526-4858-9ad6-5d81c6194293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727268666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3727268666
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.578263006
Short name T68
Test name
Test status
Simulation time 965012631514 ps
CPU time 1588.47 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:47:42 PM PDT 24
Peak memory 191224 kb
Host smart-53f99aad-501c-4fc2-ae04-51f38e5dc5dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578263006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
578263006
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2804832833
Short name T27
Test name
Test status
Simulation time 270136381 ps
CPU time 1.11 seconds
Started Jun 06 01:16:07 PM PDT 24
Finished Jun 06 01:16:09 PM PDT 24
Peak memory 183308 kb
Host smart-816313aa-858d-4894-b88e-ebbaee40a0d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804832833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2804832833
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3415424955
Short name T70
Test name
Test status
Simulation time 484558733707 ps
CPU time 2002.15 seconds
Started Jun 06 02:20:36 PM PDT 24
Finished Jun 06 02:53:59 PM PDT 24
Peak memory 191228 kb
Host smart-fd532765-3351-4dc3-b602-93ffa646cbbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415424955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3415424955
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3390509087
Short name T130
Test name
Test status
Simulation time 720461784607 ps
CPU time 2179.2 seconds
Started Jun 06 02:20:40 PM PDT 24
Finished Jun 06 02:57:01 PM PDT 24
Peak memory 191220 kb
Host smart-32b8383c-53fd-4d71-ab33-a0e5b1c8a93c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390509087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3390509087
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2073929465
Short name T53
Test name
Test status
Simulation time 28728093 ps
CPU time 0.61 seconds
Started Jun 06 01:16:25 PM PDT 24
Finished Jun 06 01:16:27 PM PDT 24
Peak memory 182744 kb
Host smart-4ad5ef8a-deaa-4be2-8ccd-858dd9325d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073929465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2073929465
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3722234582
Short name T193
Test name
Test status
Simulation time 3681661707325 ps
CPU time 4704.33 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 03:39:27 PM PDT 24
Peak memory 195880 kb
Host smart-aad37fa3-8b95-419b-80f2-7d21589cddb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722234582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3722234582
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1529003512
Short name T189
Test name
Test status
Simulation time 513739871621 ps
CPU time 2994.13 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 03:10:33 PM PDT 24
Peak memory 191456 kb
Host smart-a77d4061-445a-4857-85e5-b936ea24d2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529003512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1529003512
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1562796668
Short name T244
Test name
Test status
Simulation time 2296315516934 ps
CPU time 2186.27 seconds
Started Jun 06 02:20:51 PM PDT 24
Finished Jun 06 02:57:19 PM PDT 24
Peak memory 191228 kb
Host smart-47a2e5c2-ef05-431c-8251-41a43fc73bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562796668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1562796668
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3405733939
Short name T340
Test name
Test status
Simulation time 3734215758622 ps
CPU time 2744.76 seconds
Started Jun 06 02:20:30 PM PDT 24
Finished Jun 06 03:06:16 PM PDT 24
Peak memory 194976 kb
Host smart-5e601fbd-0e03-45e8-b0ab-c8a5617a7f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405733939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3405733939
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4103084607
Short name T176
Test name
Test status
Simulation time 2313122642080 ps
CPU time 1365.37 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:43:53 PM PDT 24
Peak memory 196000 kb
Host smart-b237086d-32b0-4495-909e-066a74a92da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103084607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4103084607
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.998627991
Short name T13
Test name
Test status
Simulation time 344052927 ps
CPU time 0.91 seconds
Started Jun 06 02:20:32 PM PDT 24
Finished Jun 06 02:20:34 PM PDT 24
Peak memory 214308 kb
Host smart-ddaafc04-0caa-4bdc-bd99-9ee4a197f590
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998627991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.998627991
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/186.rv_timer_random.1549240273
Short name T5
Test name
Test status
Simulation time 576943921922 ps
CPU time 325.7 seconds
Started Jun 06 02:21:32 PM PDT 24
Finished Jun 06 02:26:59 PM PDT 24
Peak memory 191216 kb
Host smart-b3a148dd-0c81-4be1-8a82-53d0caf1c310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549240273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1549240273
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2018416811
Short name T67
Test name
Test status
Simulation time 444174593144 ps
CPU time 1343.4 seconds
Started Jun 06 02:21:11 PM PDT 24
Finished Jun 06 02:43:36 PM PDT 24
Peak memory 191252 kb
Host smart-10d16943-a8cf-4d41-ba2a-05f1016c9ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018416811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2018416811
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3257766775
Short name T165
Test name
Test status
Simulation time 3558951093610 ps
CPU time 1297.76 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:42:29 PM PDT 24
Peak memory 191236 kb
Host smart-41671b45-0114-4dba-b358-9e3df96e0a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257766775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3257766775
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1366941455
Short name T184
Test name
Test status
Simulation time 2090309970501 ps
CPU time 999.79 seconds
Started Jun 06 02:20:51 PM PDT 24
Finished Jun 06 02:37:32 PM PDT 24
Peak memory 191204 kb
Host smart-dc731e15-f3fa-460d-9839-911b7deff3a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366941455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1366941455
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/84.rv_timer_random.2914738932
Short name T115
Test name
Test status
Simulation time 772227730948 ps
CPU time 414.79 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:27:58 PM PDT 24
Peak memory 191200 kb
Host smart-357e18f3-4ace-4d2c-b69b-47324db6819c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914738932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2914738932
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1337552619
Short name T205
Test name
Test status
Simulation time 870882887777 ps
CPU time 481.39 seconds
Started Jun 06 02:21:28 PM PDT 24
Finished Jun 06 02:29:31 PM PDT 24
Peak memory 183076 kb
Host smart-72222767-2518-4c11-9059-7cd8a0c97f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337552619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1337552619
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1053670258
Short name T72
Test name
Test status
Simulation time 1840054926281 ps
CPU time 1369.16 seconds
Started Jun 06 02:20:33 PM PDT 24
Finished Jun 06 02:43:33 PM PDT 24
Peak memory 191232 kb
Host smart-9dae6be6-a34d-45af-aba6-11aa669ce771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053670258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1053670258
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.2134247097
Short name T2
Test name
Test status
Simulation time 551014720276 ps
CPU time 436.77 seconds
Started Jun 06 02:21:22 PM PDT 24
Finished Jun 06 02:28:40 PM PDT 24
Peak memory 191312 kb
Host smart-7a61bfd4-33f5-4b18-b253-0728ad04c9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134247097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2134247097
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3524028254
Short name T269
Test name
Test status
Simulation time 2740203143628 ps
CPU time 5742.7 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 03:56:53 PM PDT 24
Peak memory 191204 kb
Host smart-05d88d13-f76c-4016-bfc9-00fbec04c18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524028254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3524028254
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1454027390
Short name T151
Test name
Test status
Simulation time 932627104088 ps
CPU time 745.8 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:33:23 PM PDT 24
Peak memory 191304 kb
Host smart-4b005a1c-27ab-478e-a6bd-0e8c2c208463
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454027390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1454027390
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_random.2490163182
Short name T188
Test name
Test status
Simulation time 172368228382 ps
CPU time 649.43 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:31:35 PM PDT 24
Peak memory 191240 kb
Host smart-1e86c2fe-eb11-4eb1-b318-e4e1ce278ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490163182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2490163182
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.450189903
Short name T277
Test name
Test status
Simulation time 641527345953 ps
CPU time 367.4 seconds
Started Jun 06 02:20:55 PM PDT 24
Finished Jun 06 02:27:03 PM PDT 24
Peak memory 191252 kb
Host smart-47a837cb-7fc5-4f1f-8920-e9630ed6f7f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450189903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.450189903
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4213198772
Short name T290
Test name
Test status
Simulation time 668310242268 ps
CPU time 669.98 seconds
Started Jun 06 02:21:17 PM PDT 24
Finished Jun 06 02:32:28 PM PDT 24
Peak memory 191452 kb
Host smart-8ba93ace-2209-48b4-8012-29f642ab55cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213198772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4213198772
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2201968329
Short name T125
Test name
Test status
Simulation time 349837017533 ps
CPU time 891.63 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:35:54 PM PDT 24
Peak memory 191196 kb
Host smart-df264138-46cc-4f95-8c8b-7428925d73ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201968329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2201968329
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/63.rv_timer_random.2131880845
Short name T166
Test name
Test status
Simulation time 410886985550 ps
CPU time 388.46 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:27:32 PM PDT 24
Peak memory 195180 kb
Host smart-a828cd3c-574b-446b-89bd-0760a5d03f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131880845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2131880845
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.437254580
Short name T103
Test name
Test status
Simulation time 26227863 ps
CPU time 0.72 seconds
Started Jun 06 01:16:19 PM PDT 24
Finished Jun 06 01:16:21 PM PDT 24
Peak memory 191732 kb
Host smart-2fc0a9ce-54a5-4d53-af75-8ee4c1487875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437254580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.437254580
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/173.rv_timer_random.7991671
Short name T248
Test name
Test status
Simulation time 499515300586 ps
CPU time 1107.89 seconds
Started Jun 06 02:21:21 PM PDT 24
Finished Jun 06 02:39:51 PM PDT 24
Peak memory 191204 kb
Host smart-e0ab199d-5f33-4952-88f2-62f130dadbde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7991671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.7991671
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3247007049
Short name T228
Test name
Test status
Simulation time 772075776258 ps
CPU time 4913.84 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 03:42:58 PM PDT 24
Peak memory 195884 kb
Host smart-2ed23ee0-1124-410b-9ab3-04289f7c25b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247007049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3247007049
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3956070254
Short name T150
Test name
Test status
Simulation time 3250481829541 ps
CPU time 2866.15 seconds
Started Jun 06 02:20:31 PM PDT 24
Finished Jun 06 03:08:19 PM PDT 24
Peak memory 191256 kb
Host smart-efc006b0-eb03-496d-bd3c-e63e7f4638b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956070254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3956070254
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2216233588
Short name T281
Test name
Test status
Simulation time 623308994224 ps
CPU time 470.8 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:28:37 PM PDT 24
Peak memory 192944 kb
Host smart-c8cd1d18-0df8-4296-b374-34eb010626ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216233588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2216233588
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2024282205
Short name T272
Test name
Test status
Simulation time 102648621099 ps
CPU time 189.58 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:24:18 PM PDT 24
Peak memory 191224 kb
Host smart-76c672d2-3abe-4cf4-8436-15262248cfb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024282205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2024282205
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2258404059
Short name T255
Test name
Test status
Simulation time 317210133500 ps
CPU time 769.87 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:34:11 PM PDT 24
Peak memory 191196 kb
Host smart-0dbf9405-6750-492f-8cb5-233e89c97634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258404059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2258404059
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3728578796
Short name T278
Test name
Test status
Simulation time 191852407777 ps
CPU time 1658.18 seconds
Started Jun 06 02:21:04 PM PDT 24
Finished Jun 06 02:48:43 PM PDT 24
Peak memory 194732 kb
Host smart-1a73384c-48b8-4c8f-843d-c16d82d1efe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728578796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3728578796
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3530548115
Short name T86
Test name
Test status
Simulation time 89302033798 ps
CPU time 150.9 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 02:23:09 PM PDT 24
Peak memory 191272 kb
Host smart-f3d56bdd-01aa-4bcf-8fbc-a3eab27e42e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530548115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3530548115
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3025828679
Short name T293
Test name
Test status
Simulation time 549246198585 ps
CPU time 264.69 seconds
Started Jun 06 02:21:23 PM PDT 24
Finished Jun 06 02:25:49 PM PDT 24
Peak memory 191232 kb
Host smart-23c5670b-d293-41f7-9b1b-98c0e3c4201c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025828679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3025828679
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3620405159
Short name T59
Test name
Test status
Simulation time 172259947625 ps
CPU time 326.57 seconds
Started Jun 06 02:21:25 PM PDT 24
Finished Jun 06 02:26:52 PM PDT 24
Peak memory 191448 kb
Host smart-674e38a4-35c8-4fff-bb03-3b43d57a60d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620405159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3620405159
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.430954597
Short name T338
Test name
Test status
Simulation time 965693125407 ps
CPU time 997.99 seconds
Started Jun 06 02:21:04 PM PDT 24
Finished Jun 06 02:37:43 PM PDT 24
Peak memory 191232 kb
Host smart-db5c438c-770c-4291-8329-245e55a3bf79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430954597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
430954597
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random.4166669706
Short name T212
Test name
Test status
Simulation time 422840547814 ps
CPU time 475.28 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:29:02 PM PDT 24
Peak memory 191200 kb
Host smart-e48d49f8-f53b-4f7a-a75b-52c041135397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166669706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.4166669706
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.512203620
Short name T201
Test name
Test status
Simulation time 840259274903 ps
CPU time 464.6 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:28:55 PM PDT 24
Peak memory 191204 kb
Host smart-f4a4055a-fc94-4535-924b-6a5651b1daeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512203620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.512203620
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3841036653
Short name T195
Test name
Test status
Simulation time 234487372686 ps
CPU time 393.86 seconds
Started Jun 06 02:20:39 PM PDT 24
Finished Jun 06 02:27:14 PM PDT 24
Peak memory 191204 kb
Host smart-a5bb6fc8-3c6c-4dba-8e4f-7fb29e6bdfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841036653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3841036653
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/185.rv_timer_random.1345703799
Short name T251
Test name
Test status
Simulation time 122872624098 ps
CPU time 388.51 seconds
Started Jun 06 02:21:26 PM PDT 24
Finished Jun 06 02:27:55 PM PDT 24
Peak memory 191200 kb
Host smart-b1089c1d-d60f-4eb8-9c2c-a7fc0cadce21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345703799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1345703799
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1246001608
Short name T309
Test name
Test status
Simulation time 333744359766 ps
CPU time 433.87 seconds
Started Jun 06 02:21:24 PM PDT 24
Finished Jun 06 02:28:39 PM PDT 24
Peak memory 191212 kb
Host smart-3ab0982d-4f54-48ae-b753-fd8a60a9077b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246001608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1246001608
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3544938631
Short name T170
Test name
Test status
Simulation time 143635341255 ps
CPU time 244.1 seconds
Started Jun 06 02:21:31 PM PDT 24
Finished Jun 06 02:25:36 PM PDT 24
Peak memory 191220 kb
Host smart-fcc9ea4e-52b4-4622-9630-c19830261411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544938631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3544938631
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2532570657
Short name T303
Test name
Test status
Simulation time 677138368274 ps
CPU time 815.41 seconds
Started Jun 06 02:20:26 PM PDT 24
Finished Jun 06 02:34:02 PM PDT 24
Peak memory 195896 kb
Host smart-c7c076bc-4a91-4c07-818f-19858a25b439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532570657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2532570657
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/55.rv_timer_random.2033410614
Short name T61
Test name
Test status
Simulation time 759500952708 ps
CPU time 918.58 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:36:26 PM PDT 24
Peak memory 191260 kb
Host smart-46a353a9-1fc6-439c-80c6-511ef334f148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033410614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2033410614
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2658334679
Short name T444
Test name
Test status
Simulation time 406375076793 ps
CPU time 522.03 seconds
Started Jun 06 02:21:05 PM PDT 24
Finished Jun 06 02:29:48 PM PDT 24
Peak memory 191216 kb
Host smart-915839c2-7307-4294-9d7e-324111983c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658334679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2658334679
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.1688475698
Short name T222
Test name
Test status
Simulation time 583051527888 ps
CPU time 1340.25 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:43:06 PM PDT 24
Peak memory 191232 kb
Host smart-57c2fd12-8b5a-40a4-a4a0-6054bc3dd8e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688475698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1688475698
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3865464805
Short name T557
Test name
Test status
Simulation time 460119444 ps
CPU time 1.31 seconds
Started Jun 06 01:15:56 PM PDT 24
Finished Jun 06 01:15:59 PM PDT 24
Peak memory 183300 kb
Host smart-1fffe553-c6c9-4a95-8b63-e319e4959d86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865464805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3865464805
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_random.3741643759
Short name T236
Test name
Test status
Simulation time 304153121483 ps
CPU time 193.96 seconds
Started Jun 06 02:20:26 PM PDT 24
Finished Jun 06 02:23:41 PM PDT 24
Peak memory 191248 kb
Host smart-fbb1edd7-3efb-4008-aca4-012f1a45b612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741643759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3741643759
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3739677746
Short name T243
Test name
Test status
Simulation time 85272507334 ps
CPU time 143.28 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:23:20 PM PDT 24
Peak memory 191212 kb
Host smart-563e9a60-1f03-4a99-a253-55140e75bf6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739677746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3739677746
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3123198158
Short name T344
Test name
Test status
Simulation time 200701570769 ps
CPU time 711.02 seconds
Started Jun 06 02:21:16 PM PDT 24
Finished Jun 06 02:33:08 PM PDT 24
Peak memory 191444 kb
Host smart-7f279e5b-1d12-4121-acc4-2d62b051e555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123198158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3123198158
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2982433513
Short name T245
Test name
Test status
Simulation time 186681926567 ps
CPU time 354.04 seconds
Started Jun 06 02:20:39 PM PDT 24
Finished Jun 06 02:26:34 PM PDT 24
Peak memory 195064 kb
Host smart-455bbc76-365a-415f-9208-d9578beff126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982433513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2982433513
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.4273524412
Short name T238
Test name
Test status
Simulation time 232303744958 ps
CPU time 516.83 seconds
Started Jun 06 02:21:12 PM PDT 24
Finished Jun 06 02:29:50 PM PDT 24
Peak memory 191260 kb
Host smart-6be1d246-d3b6-45e1-8495-8f73a228f3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273524412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4273524412
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.4294277677
Short name T331
Test name
Test status
Simulation time 270154058112 ps
CPU time 368.36 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:27:20 PM PDT 24
Peak memory 191268 kb
Host smart-631823a0-520b-4668-a9a8-a676bfcebef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294277677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.4294277677
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.159994208
Short name T271
Test name
Test status
Simulation time 524111267709 ps
CPU time 315.97 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:26:26 PM PDT 24
Peak memory 191244 kb
Host smart-d20073f5-e55d-43be-962c-9f19594e650b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159994208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.159994208
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3460678702
Short name T204
Test name
Test status
Simulation time 91993553013 ps
CPU time 141.49 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:23:42 PM PDT 24
Peak memory 191260 kb
Host smart-b6437226-574e-4c9f-bfa5-06b5f920d8c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460678702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3460678702
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1492562384
Short name T327
Test name
Test status
Simulation time 309317720842 ps
CPU time 222.85 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:24:40 PM PDT 24
Peak memory 191304 kb
Host smart-202f7088-193d-4f96-beda-d3605e340fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492562384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1492562384
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.903289054
Short name T158
Test name
Test status
Simulation time 1307524399587 ps
CPU time 655.31 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:31:48 PM PDT 24
Peak memory 183068 kb
Host smart-ab00fa5e-1257-4d4b-a9e9-1db0046bfa89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903289054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.903289054
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.2689088578
Short name T111
Test name
Test status
Simulation time 573982906416 ps
CPU time 779.91 seconds
Started Jun 06 02:20:46 PM PDT 24
Finished Jun 06 02:33:47 PM PDT 24
Peak memory 194312 kb
Host smart-1afda361-3dca-4128-b902-8bd57a85f080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689088578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2689088578
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.10058696
Short name T71
Test name
Test status
Simulation time 482943246942 ps
CPU time 1139.68 seconds
Started Jun 06 02:20:27 PM PDT 24
Finished Jun 06 02:39:28 PM PDT 24
Peak memory 191244 kb
Host smart-76097405-31a7-448f-8b2d-d3906b9f87c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.10058696
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random.2048866330
Short name T258
Test name
Test status
Simulation time 239193388889 ps
CPU time 1242.26 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:41:46 PM PDT 24
Peak memory 191264 kb
Host smart-3f638dd5-a6cf-45de-a074-1f9c01cda53c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048866330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2048866330
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4028252346
Short name T292
Test name
Test status
Simulation time 2237711977254 ps
CPU time 1495.87 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:46:17 PM PDT 24
Peak memory 191260 kb
Host smart-b72fad7a-25fe-4cbb-9b48-c4a20f1ee561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028252346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4028252346
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2476951418
Short name T78
Test name
Test status
Simulation time 5846674741 ps
CPU time 3.78 seconds
Started Jun 06 02:20:43 PM PDT 24
Finished Jun 06 02:20:47 PM PDT 24
Peak memory 183084 kb
Host smart-4dcba529-3fac-48c0-83dc-4be7f2a9a9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476951418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2476951418
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/97.rv_timer_random.1023658057
Short name T192
Test name
Test status
Simulation time 488110421737 ps
CPU time 1909.02 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:53:04 PM PDT 24
Peak memory 194084 kb
Host smart-03ff8feb-7205-4a34-b958-17e019c25364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023658057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1023658057
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3948994234
Short name T123
Test name
Test status
Simulation time 76215227 ps
CPU time 0.84 seconds
Started Jun 06 01:16:33 PM PDT 24
Finished Jun 06 01:16:35 PM PDT 24
Peak memory 193696 kb
Host smart-2a9e79a8-1a30-4641-8508-7fc603ea4723
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948994234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3948994234
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_random.732282646
Short name T217
Test name
Test status
Simulation time 743389104612 ps
CPU time 1072.98 seconds
Started Jun 06 02:20:49 PM PDT 24
Finished Jun 06 02:38:43 PM PDT 24
Peak memory 191196 kb
Host smart-9fc31df1-6081-4d3a-bc7c-ca70f1ce88aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732282646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.732282646
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3348003619
Short name T349
Test name
Test status
Simulation time 110953379444 ps
CPU time 177.59 seconds
Started Jun 06 02:21:00 PM PDT 24
Finished Jun 06 02:23:58 PM PDT 24
Peak memory 191240 kb
Host smart-aeb23378-19d5-4a0a-a10e-9f4ee34aedbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348003619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3348003619
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.587948277
Short name T285
Test name
Test status
Simulation time 186361396034 ps
CPU time 139.79 seconds
Started Jun 06 02:21:14 PM PDT 24
Finished Jun 06 02:23:35 PM PDT 24
Peak memory 191260 kb
Host smart-c6d06ecb-fb8d-4c0b-9ff0-9dc036f9bca6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587948277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.587948277
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.2595799123
Short name T320
Test name
Test status
Simulation time 59902338368 ps
CPU time 50.42 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:22:12 PM PDT 24
Peak memory 191192 kb
Host smart-5d2cb0c1-53b4-4384-9580-16aebeee5651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595799123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2595799123
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.231092913
Short name T328
Test name
Test status
Simulation time 433935941711 ps
CPU time 130.66 seconds
Started Jun 06 02:21:11 PM PDT 24
Finished Jun 06 02:23:23 PM PDT 24
Peak memory 183004 kb
Host smart-440c5cae-6012-4030-97d3-cd025d0d6924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231092913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.231092913
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4176038411
Short name T332
Test name
Test status
Simulation time 96897916697 ps
CPU time 528.57 seconds
Started Jun 06 02:21:31 PM PDT 24
Finished Jun 06 02:30:20 PM PDT 24
Peak memory 191260 kb
Host smart-05ab6876-981f-4bea-a358-71f69b9c8c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176038411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4176038411
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3445886666
Short name T18
Test name
Test status
Simulation time 473027691784 ps
CPU time 63.96 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:22:00 PM PDT 24
Peak memory 183248 kb
Host smart-82e7b383-bd00-4b93-bec1-c61324d06850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445886666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3445886666
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2631360678
Short name T241
Test name
Test status
Simulation time 2057072847650 ps
CPU time 1644.23 seconds
Started Jun 06 02:20:49 PM PDT 24
Finished Jun 06 02:48:14 PM PDT 24
Peak memory 195028 kb
Host smart-83f3ccbd-2587-4a37-86c2-4becdf0adeb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631360678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2631360678
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.3299787975
Short name T341
Test name
Test status
Simulation time 93851411076 ps
CPU time 411 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:28:05 PM PDT 24
Peak memory 191196 kb
Host smart-071ea387-1503-4020-ac03-370f9f198907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299787975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3299787975
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.4065388190
Short name T141
Test name
Test status
Simulation time 771019005643 ps
CPU time 2648.74 seconds
Started Jun 06 02:21:28 PM PDT 24
Finished Jun 06 03:05:38 PM PDT 24
Peak memory 191224 kb
Host smart-bdadbe91-29d6-4e6f-a933-8a465cd20276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065388190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4065388190
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3049059508
Short name T343
Test name
Test status
Simulation time 495787191440 ps
CPU time 762.76 seconds
Started Jun 06 02:21:25 PM PDT 24
Finished Jun 06 02:34:09 PM PDT 24
Peak memory 191208 kb
Host smart-9e84db9b-27e3-47c4-a925-5f3937455f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049059508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3049059508
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3192937499
Short name T162
Test name
Test status
Simulation time 1340757664685 ps
CPU time 386.36 seconds
Started Jun 06 02:20:53 PM PDT 24
Finished Jun 06 02:27:21 PM PDT 24
Peak memory 191216 kb
Host smart-843d178b-4d21-4fc3-8251-f90edb2c0cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192937499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3192937499
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_random.2455862277
Short name T177
Test name
Test status
Simulation time 394927192699 ps
CPU time 681.3 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:32:18 PM PDT 24
Peak memory 191212 kb
Host smart-e4ba36c0-399c-46a1-ae9e-c8f2957d4674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455862277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2455862277
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.56198527
Short name T43
Test name
Test status
Simulation time 377308296316 ps
CPU time 598.85 seconds
Started Jun 06 02:20:59 PM PDT 24
Finished Jun 06 02:30:59 PM PDT 24
Peak memory 183008 kb
Host smart-3ed4e59e-f18b-4369-af25-4b1a4d77c7ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56198527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.rv_timer_cfg_update_on_fly.56198527
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1204706048
Short name T284
Test name
Test status
Simulation time 273367328039 ps
CPU time 450.39 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 02:28:09 PM PDT 24
Peak memory 183000 kb
Host smart-d7d47526-9f4f-43c1-a925-c91c671ef5b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204706048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1204706048
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2781086073
Short name T335
Test name
Test status
Simulation time 683909216932 ps
CPU time 183.18 seconds
Started Jun 06 02:21:04 PM PDT 24
Finished Jun 06 02:24:08 PM PDT 24
Peak memory 191228 kb
Host smart-67bc79e1-e7b2-411b-8ad2-a30bfb3f2ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781086073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2781086073
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1436619057
Short name T157
Test name
Test status
Simulation time 212838421659 ps
CPU time 360.03 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:26:53 PM PDT 24
Peak memory 183068 kb
Host smart-57ff7139-9150-41ff-a658-383bc8779e54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436619057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1436619057
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/65.rv_timer_random.3913442087
Short name T300
Test name
Test status
Simulation time 115064330717 ps
CPU time 302.2 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:26:06 PM PDT 24
Peak memory 191256 kb
Host smart-5083592c-8073-4a4a-8995-3a6a68f98f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913442087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3913442087
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3101474811
Short name T289
Test name
Test status
Simulation time 490983166734 ps
CPU time 363.4 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:27:11 PM PDT 24
Peak memory 193744 kb
Host smart-45b5b495-68df-4d74-ac19-8ebe37000e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101474811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3101474811
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3784262912
Short name T352
Test name
Test status
Simulation time 634578025644 ps
CPU time 387.46 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:27:38 PM PDT 24
Peak memory 191228 kb
Host smart-f68b2124-0614-4104-89bb-a01a6eb38fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784262912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3784262912
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1300107908
Short name T93
Test name
Test status
Simulation time 74606406 ps
CPU time 0.71 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 191956 kb
Host smart-060f141d-8c5a-463e-aba8-2626b4a6af1a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300107908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1300107908
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1126335484
Short name T464
Test name
Test status
Simulation time 750437712 ps
CPU time 2.52 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:59 PM PDT 24
Peak memory 191236 kb
Host smart-4f19fb70-06f1-4c57-a355-5d0b9431f098
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126335484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1126335484
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1283485223
Short name T486
Test name
Test status
Simulation time 15453600 ps
CPU time 0.55 seconds
Started Jun 06 01:15:54 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 182232 kb
Host smart-5e1acb7a-2596-497a-9ef6-5a24b730154d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283485223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1283485223
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1272253423
Short name T578
Test name
Test status
Simulation time 41911665 ps
CPU time 0.73 seconds
Started Jun 06 01:15:56 PM PDT 24
Finished Jun 06 01:15:58 PM PDT 24
Peak memory 195112 kb
Host smart-3b70442e-6867-42de-b308-2ae5221ec472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272253423 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1272253423
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.417321209
Short name T549
Test name
Test status
Simulation time 57816815 ps
CPU time 0.58 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 182636 kb
Host smart-4c237cd7-4368-4d1a-bb83-9ff803b0dd53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417321209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.417321209
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.460465339
Short name T523
Test name
Test status
Simulation time 14470942 ps
CPU time 0.52 seconds
Started Jun 06 01:15:54 PM PDT 24
Finished Jun 06 01:15:56 PM PDT 24
Peak memory 182288 kb
Host smart-a7b89e06-8d9c-4c23-9af9-28602529d95e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460465339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.460465339
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2210465385
Short name T489
Test name
Test status
Simulation time 22795980 ps
CPU time 1.11 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 197392 kb
Host smart-8369a4a3-d200-4a75-9e8a-3aec71c302d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210465385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2210465385
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1447864264
Short name T530
Test name
Test status
Simulation time 314812653 ps
CPU time 0.76 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 193288 kb
Host smart-9bb66da3-53ab-497f-a577-410ac645814e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447864264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1447864264
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.217363519
Short name T98
Test name
Test status
Simulation time 86952391 ps
CPU time 0.73 seconds
Started Jun 06 01:15:57 PM PDT 24
Finished Jun 06 01:15:59 PM PDT 24
Peak memory 191984 kb
Host smart-173cf545-5579-452e-ac5b-9b43fea6312c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217363519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.217363519
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3426759270
Short name T541
Test name
Test status
Simulation time 109686457 ps
CPU time 1.48 seconds
Started Jun 06 01:15:56 PM PDT 24
Finished Jun 06 01:15:59 PM PDT 24
Peak memory 182932 kb
Host smart-8520112a-2624-4bf8-ba5c-688f36a52afb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426759270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3426759270
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3978497825
Short name T64
Test name
Test status
Simulation time 24067079 ps
CPU time 0.56 seconds
Started Jun 06 01:15:53 PM PDT 24
Finished Jun 06 01:15:54 PM PDT 24
Peak memory 182696 kb
Host smart-8bac78dd-1960-41c4-b6d9-17582428aaa9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978497825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3978497825
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4137004501
Short name T529
Test name
Test status
Simulation time 38708426 ps
CPU time 0.61 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 193428 kb
Host smart-c2023c38-594b-4bfd-8068-588ca536a1a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137004501 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4137004501
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3787253863
Short name T583
Test name
Test status
Simulation time 43014760 ps
CPU time 0.56 seconds
Started Jun 06 01:15:54 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 182668 kb
Host smart-e559808f-9bbc-42b0-af7b-81d185ce8e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787253863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3787253863
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.455504872
Short name T527
Test name
Test status
Simulation time 25701693 ps
CPU time 0.56 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 182600 kb
Host smart-b8b6d142-609b-415e-9581-d8c3b4be9596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455504872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.455504872
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3859998699
Short name T555
Test name
Test status
Simulation time 32553046 ps
CPU time 0.75 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 193260 kb
Host smart-a61108ba-74ff-459c-b922-b16c1c304272
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859998699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3859998699
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3316374092
Short name T462
Test name
Test status
Simulation time 517477531 ps
CPU time 1.81 seconds
Started Jun 06 01:15:56 PM PDT 24
Finished Jun 06 01:15:59 PM PDT 24
Peak memory 197684 kb
Host smart-13c668a7-1073-48d0-a8e8-32c1f376dd09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316374092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3316374092
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.744955408
Short name T572
Test name
Test status
Simulation time 78664578 ps
CPU time 0.75 seconds
Started Jun 06 01:16:32 PM PDT 24
Finished Jun 06 01:16:33 PM PDT 24
Peak memory 195720 kb
Host smart-5ddcd73a-3bbc-47e6-9f13-0d7e69be48b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744955408 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.744955408
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4131454434
Short name T561
Test name
Test status
Simulation time 181262751 ps
CPU time 0.61 seconds
Started Jun 06 01:16:24 PM PDT 24
Finished Jun 06 01:16:25 PM PDT 24
Peak memory 182752 kb
Host smart-9872b24c-cdba-4b38-9065-5531d3a7e595
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131454434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4131454434
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3764603539
Short name T485
Test name
Test status
Simulation time 19015172 ps
CPU time 0.55 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:20 PM PDT 24
Peak memory 182548 kb
Host smart-aa6abded-b253-4220-b8a7-50490abd0133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764603539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3764603539
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1126796681
Short name T528
Test name
Test status
Simulation time 28140341 ps
CPU time 0.71 seconds
Started Jun 06 01:16:24 PM PDT 24
Finished Jun 06 01:16:25 PM PDT 24
Peak memory 192116 kb
Host smart-a497ff0b-a354-4da6-afb9-cf63c1aa8014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126796681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1126796681
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1561675821
Short name T531
Test name
Test status
Simulation time 40197196 ps
CPU time 1.92 seconds
Started Jun 06 01:16:16 PM PDT 24
Finished Jun 06 01:16:19 PM PDT 24
Peak memory 197660 kb
Host smart-ac80884e-9715-4663-bf0a-2f49d100b7dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561675821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1561675821
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2867148034
Short name T29
Test name
Test status
Simulation time 47692811 ps
CPU time 0.82 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:18 PM PDT 24
Peak memory 193896 kb
Host smart-43f1789a-69d4-43e4-b573-d594a47b89b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867148034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2867148034
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2661720160
Short name T533
Test name
Test status
Simulation time 56968617 ps
CPU time 0.76 seconds
Started Jun 06 01:16:32 PM PDT 24
Finished Jun 06 01:16:33 PM PDT 24
Peak memory 195376 kb
Host smart-e069b9ba-e95d-4007-a19f-83c1a2f19304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661720160 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2661720160
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.645578837
Short name T91
Test name
Test status
Simulation time 15000633 ps
CPU time 0.58 seconds
Started Jun 06 01:16:32 PM PDT 24
Finished Jun 06 01:16:33 PM PDT 24
Peak memory 182752 kb
Host smart-574625e4-1cf9-423d-aaf8-63b416762162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645578837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.645578837
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2449995867
Short name T517
Test name
Test status
Simulation time 19597448 ps
CPU time 0.56 seconds
Started Jun 06 01:16:25 PM PDT 24
Finished Jun 06 01:16:27 PM PDT 24
Peak memory 182668 kb
Host smart-d983c859-75f9-46e9-832c-f5db25abb412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449995867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2449995867
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3169717064
Short name T548
Test name
Test status
Simulation time 66127760 ps
CPU time 0.76 seconds
Started Jun 06 01:16:32 PM PDT 24
Finished Jun 06 01:16:34 PM PDT 24
Peak memory 193596 kb
Host smart-65a6802e-388d-431d-8b3b-c7a925ab359e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169717064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3169717064
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.106407695
Short name T511
Test name
Test status
Simulation time 502708509 ps
CPU time 2.56 seconds
Started Jun 06 01:16:24 PM PDT 24
Finished Jun 06 01:16:27 PM PDT 24
Peak memory 197656 kb
Host smart-870fb502-50f6-4e71-b5f8-c7ddf41f051b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106407695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.106407695
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3603027055
Short name T118
Test name
Test status
Simulation time 345696786 ps
CPU time 1.26 seconds
Started Jun 06 01:16:31 PM PDT 24
Finished Jun 06 01:16:33 PM PDT 24
Peak memory 195292 kb
Host smart-6678da5e-3ed8-4c1f-9a5b-29a488e76b91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603027055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3603027055
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3066008475
Short name T542
Test name
Test status
Simulation time 37941744 ps
CPU time 0.93 seconds
Started Jun 06 01:16:29 PM PDT 24
Finished Jun 06 01:16:32 PM PDT 24
Peak memory 197292 kb
Host smart-0963b931-2bdc-4945-8db9-362bd90fc536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066008475 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3066008475
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4096527780
Short name T63
Test name
Test status
Simulation time 14239598 ps
CPU time 0.64 seconds
Started Jun 06 01:16:37 PM PDT 24
Finished Jun 06 01:16:38 PM PDT 24
Peak memory 182740 kb
Host smart-0098cfc2-099f-49c0-9796-304900e4d5ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096527780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4096527780
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3734867112
Short name T496
Test name
Test status
Simulation time 49902954 ps
CPU time 0.6 seconds
Started Jun 06 01:16:26 PM PDT 24
Finished Jun 06 01:16:28 PM PDT 24
Peak memory 182604 kb
Host smart-2a7b591c-568c-4790-877d-d36da36da2ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734867112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3734867112
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2434892044
Short name T94
Test name
Test status
Simulation time 290154770 ps
CPU time 0.6 seconds
Started Jun 06 01:16:24 PM PDT 24
Finished Jun 06 01:16:26 PM PDT 24
Peak memory 191624 kb
Host smart-70d89f7a-c361-4833-bbcc-48d44d97bda9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434892044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2434892044
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2973432280
Short name T494
Test name
Test status
Simulation time 461030905 ps
CPU time 2.56 seconds
Started Jun 06 01:16:27 PM PDT 24
Finished Jun 06 01:16:30 PM PDT 24
Peak memory 197576 kb
Host smart-8e3bb1db-b733-4817-89f4-e8fdf0828b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973432280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2973432280
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.528220469
Short name T518
Test name
Test status
Simulation time 100718569 ps
CPU time 1.11 seconds
Started Jun 06 01:16:23 PM PDT 24
Finished Jun 06 01:16:25 PM PDT 24
Peak memory 183584 kb
Host smart-438d7493-c19a-43a4-be2e-e79adedcdb76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528220469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.528220469
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3642460024
Short name T483
Test name
Test status
Simulation time 32301148 ps
CPU time 0.9 seconds
Started Jun 06 01:16:23 PM PDT 24
Finished Jun 06 01:16:25 PM PDT 24
Peak memory 196932 kb
Host smart-5eede15d-94ed-48b5-8b84-ebfa38edfe15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642460024 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3642460024
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2107579809
Short name T100
Test name
Test status
Simulation time 48926220 ps
CPU time 0.54 seconds
Started Jun 06 01:16:28 PM PDT 24
Finished Jun 06 01:16:30 PM PDT 24
Peak memory 182716 kb
Host smart-eedb8521-cbc2-4e54-bf25-1675de626e98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107579809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2107579809
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3652546460
Short name T537
Test name
Test status
Simulation time 12403304 ps
CPU time 0.53 seconds
Started Jun 06 01:16:29 PM PDT 24
Finished Jun 06 01:16:31 PM PDT 24
Peak memory 182552 kb
Host smart-df0c6998-8813-4adb-bcd1-f8abad5a059f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652546460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3652546460
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.48210199
Short name T582
Test name
Test status
Simulation time 35514855 ps
CPU time 0.79 seconds
Started Jun 06 01:16:31 PM PDT 24
Finished Jun 06 01:16:33 PM PDT 24
Peak memory 193532 kb
Host smart-934f45ce-89b6-4c5e-8a1c-bb594f8a4538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48210199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_tim
er_same_csr_outstanding.48210199
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2318209074
Short name T584
Test name
Test status
Simulation time 60462978 ps
CPU time 2.92 seconds
Started Jun 06 01:16:25 PM PDT 24
Finished Jun 06 01:16:29 PM PDT 24
Peak memory 197588 kb
Host smart-b2ca84ee-623a-482e-834a-7b9989c15214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318209074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2318209074
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1087971749
Short name T579
Test name
Test status
Simulation time 46197626 ps
CPU time 0.84 seconds
Started Jun 06 01:16:23 PM PDT 24
Finished Jun 06 01:16:24 PM PDT 24
Peak memory 193692 kb
Host smart-4472d94d-1bf7-47b6-a3a8-518c2af043f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087971749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1087971749
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1169747983
Short name T516
Test name
Test status
Simulation time 107945801 ps
CPU time 0.88 seconds
Started Jun 06 01:16:25 PM PDT 24
Finished Jun 06 01:16:28 PM PDT 24
Peak memory 196104 kb
Host smart-a2f07296-b2ff-4da7-9d4f-4ae8b231d54a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169747983 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1169747983
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4177925108
Short name T577
Test name
Test status
Simulation time 26987069 ps
CPU time 0.54 seconds
Started Jun 06 01:16:30 PM PDT 24
Finished Jun 06 01:16:32 PM PDT 24
Peak memory 182656 kb
Host smart-d5ff51c5-aa60-4fa5-a9f5-f990c6116eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177925108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4177925108
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2352539535
Short name T551
Test name
Test status
Simulation time 52465196 ps
CPU time 0.66 seconds
Started Jun 06 01:16:25 PM PDT 24
Finished Jun 06 01:16:27 PM PDT 24
Peak memory 191292 kb
Host smart-a2484c1c-a203-4a4c-987f-b80177ac2970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352539535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2352539535
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3289335607
Short name T545
Test name
Test status
Simulation time 41949006 ps
CPU time 2.13 seconds
Started Jun 06 01:16:25 PM PDT 24
Finished Jun 06 01:16:28 PM PDT 24
Peak memory 197496 kb
Host smart-986c93bc-bbf7-4c9f-a668-51f473838bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289335607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3289335607
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2951827996
Short name T122
Test name
Test status
Simulation time 76285420 ps
CPU time 1.13 seconds
Started Jun 06 01:16:24 PM PDT 24
Finished Jun 06 01:16:26 PM PDT 24
Peak memory 183340 kb
Host smart-bf6a9dbb-c792-4c10-a5d0-975ef121bf16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951827996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2951827996
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3873152458
Short name T544
Test name
Test status
Simulation time 41372156 ps
CPU time 0.96 seconds
Started Jun 06 01:16:34 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 197036 kb
Host smart-5960d67a-b0e8-4a2f-9e35-7355a8812d23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873152458 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3873152458
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.419325217
Short name T54
Test name
Test status
Simulation time 20503031 ps
CPU time 0.52 seconds
Started Jun 06 01:16:32 PM PDT 24
Finished Jun 06 01:16:33 PM PDT 24
Peak memory 182464 kb
Host smart-6a9e3a40-8df7-4760-833b-f0082c4a4ccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419325217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.419325217
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2012038444
Short name T569
Test name
Test status
Simulation time 44234143 ps
CPU time 0.52 seconds
Started Jun 06 01:16:30 PM PDT 24
Finished Jun 06 01:16:32 PM PDT 24
Peak memory 182068 kb
Host smart-12ed759b-bfe4-4ceb-817d-44ed7012f076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012038444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2012038444
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3147345321
Short name T535
Test name
Test status
Simulation time 30267714 ps
CPU time 0.79 seconds
Started Jun 06 01:16:33 PM PDT 24
Finished Jun 06 01:16:35 PM PDT 24
Peak memory 193328 kb
Host smart-9d65d7a5-37b4-4693-b482-fb071347f315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147345321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3147345321
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1249395899
Short name T463
Test name
Test status
Simulation time 37705732 ps
CPU time 1.76 seconds
Started Jun 06 01:16:32 PM PDT 24
Finished Jun 06 01:16:34 PM PDT 24
Peak memory 197640 kb
Host smart-48abd8c4-795b-47b4-a1c5-07fe8e303016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249395899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1249395899
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.728612650
Short name T499
Test name
Test status
Simulation time 150803157 ps
CPU time 1.04 seconds
Started Jun 06 01:16:28 PM PDT 24
Finished Jun 06 01:16:31 PM PDT 24
Peak memory 183268 kb
Host smart-ffd9f3f1-d96b-4707-871d-ed0b483301c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728612650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.728612650
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3611134450
Short name T466
Test name
Test status
Simulation time 74737593 ps
CPU time 0.97 seconds
Started Jun 06 01:16:35 PM PDT 24
Finished Jun 06 01:16:37 PM PDT 24
Peak memory 196748 kb
Host smart-a76508c9-d80d-46f5-8fcd-af51529acf6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611134450 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3611134450
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3519042950
Short name T95
Test name
Test status
Simulation time 12687726 ps
CPU time 0.57 seconds
Started Jun 06 01:16:34 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 182672 kb
Host smart-19078440-e351-44c2-ba59-b14eebeedcab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519042950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3519042950
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2530477551
Short name T553
Test name
Test status
Simulation time 23985454 ps
CPU time 0.56 seconds
Started Jun 06 01:16:35 PM PDT 24
Finished Jun 06 01:16:37 PM PDT 24
Peak memory 182584 kb
Host smart-fbc92dec-3858-4772-a2ee-1bed40f18a83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530477551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2530477551
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1541970124
Short name T107
Test name
Test status
Simulation time 35484711 ps
CPU time 0.59 seconds
Started Jun 06 01:16:35 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 192028 kb
Host smart-612ce917-87f4-4e92-996f-48e672623875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541970124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1541970124
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3833138736
Short name T513
Test name
Test status
Simulation time 754522277 ps
CPU time 2.4 seconds
Started Jun 06 01:16:33 PM PDT 24
Finished Jun 06 01:16:37 PM PDT 24
Peak memory 197636 kb
Host smart-e28b22e0-788d-4b67-8ef8-76fdea3645eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833138736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3833138736
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3653794184
Short name T487
Test name
Test status
Simulation time 135913861 ps
CPU time 0.8 seconds
Started Jun 06 01:16:33 PM PDT 24
Finished Jun 06 01:16:35 PM PDT 24
Peak memory 193728 kb
Host smart-39abe0d2-8fb9-41e5-b7f0-c4693f9a87f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653794184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3653794184
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3444465385
Short name T550
Test name
Test status
Simulation time 29748970 ps
CPU time 0.59 seconds
Started Jun 06 01:16:34 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 193528 kb
Host smart-3e4ef4c9-cc2e-4c55-a3c6-420243ee2063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444465385 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3444465385
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.292023444
Short name T30
Test name
Test status
Simulation time 48977935 ps
CPU time 0.55 seconds
Started Jun 06 01:16:35 PM PDT 24
Finished Jun 06 01:16:37 PM PDT 24
Peak memory 182648 kb
Host smart-4e561334-4db9-4a54-ab58-9cf5d92fc04b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292023444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.292023444
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2752650201
Short name T536
Test name
Test status
Simulation time 11608642 ps
CPU time 0.56 seconds
Started Jun 06 01:16:32 PM PDT 24
Finished Jun 06 01:16:34 PM PDT 24
Peak memory 182624 kb
Host smart-3238d7ab-7d96-4e37-b72a-1945e582cf2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752650201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2752650201
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4131501830
Short name T102
Test name
Test status
Simulation time 109405741 ps
CPU time 0.71 seconds
Started Jun 06 01:16:34 PM PDT 24
Finished Jun 06 01:16:35 PM PDT 24
Peak memory 193140 kb
Host smart-722b9511-2226-4534-b95c-d6f5da081d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131501830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.4131501830
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3598218250
Short name T495
Test name
Test status
Simulation time 156682515 ps
CPU time 2.02 seconds
Started Jun 06 01:16:33 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 197616 kb
Host smart-6c78c972-c431-4c75-bcf7-3b58a0b0c3dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598218250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3598218250
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2869572746
Short name T558
Test name
Test status
Simulation time 64852246 ps
CPU time 0.83 seconds
Started Jun 06 01:16:36 PM PDT 24
Finished Jun 06 01:16:38 PM PDT 24
Peak memory 193384 kb
Host smart-fba9fea2-35c5-4990-b606-4201f66cd8cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869572746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2869572746
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2047000443
Short name T503
Test name
Test status
Simulation time 285079839 ps
CPU time 0.88 seconds
Started Jun 06 01:16:36 PM PDT 24
Finished Jun 06 01:16:38 PM PDT 24
Peak memory 197460 kb
Host smart-40eed01e-6480-41db-b466-5092a88bfad8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047000443 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2047000443
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1901141251
Short name T498
Test name
Test status
Simulation time 103272479 ps
CPU time 0.52 seconds
Started Jun 06 01:16:34 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 182360 kb
Host smart-c3d9a03e-124e-4a5e-a531-2f1b4178754b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901141251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1901141251
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4210691873
Short name T526
Test name
Test status
Simulation time 15140451 ps
CPU time 0.58 seconds
Started Jun 06 01:16:48 PM PDT 24
Finished Jun 06 01:16:49 PM PDT 24
Peak memory 182676 kb
Host smart-ca5e725f-f773-4bfd-b018-118d9c452f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210691873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4210691873
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.490860083
Short name T512
Test name
Test status
Simulation time 115374006 ps
CPU time 0.7 seconds
Started Jun 06 01:16:33 PM PDT 24
Finished Jun 06 01:16:35 PM PDT 24
Peak memory 193288 kb
Host smart-df788a2a-de48-4f35-9351-45e045426852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490860083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.490860083
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1786118578
Short name T473
Test name
Test status
Simulation time 526214429 ps
CPU time 2.56 seconds
Started Jun 06 01:16:32 PM PDT 24
Finished Jun 06 01:16:36 PM PDT 24
Peak memory 197600 kb
Host smart-75efb2d8-5da6-4d85-8519-84b35f17dc4d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786118578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1786118578
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2634702984
Short name T501
Test name
Test status
Simulation time 91448511 ps
CPU time 0.7 seconds
Started Jun 06 01:16:44 PM PDT 24
Finished Jun 06 01:16:46 PM PDT 24
Peak memory 194688 kb
Host smart-04e4d134-f030-4017-8c06-684324adb898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634702984 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2634702984
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3687987501
Short name T522
Test name
Test status
Simulation time 54014099 ps
CPU time 0.56 seconds
Started Jun 06 01:16:46 PM PDT 24
Finished Jun 06 01:16:47 PM PDT 24
Peak memory 182740 kb
Host smart-7c28af7a-ac1c-4532-8ef7-e22d0deafd31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687987501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3687987501
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3441323283
Short name T478
Test name
Test status
Simulation time 44229089 ps
CPU time 0.56 seconds
Started Jun 06 01:16:50 PM PDT 24
Finished Jun 06 01:16:51 PM PDT 24
Peak memory 182600 kb
Host smart-812fe103-8454-406a-94a6-b009561c4cd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441323283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3441323283
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1245131850
Short name T105
Test name
Test status
Simulation time 18956592 ps
CPU time 0.74 seconds
Started Jun 06 01:16:45 PM PDT 24
Finished Jun 06 01:16:47 PM PDT 24
Peak memory 193076 kb
Host smart-86cfaa5d-0774-40cc-92be-9e9e201e9993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245131850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1245131850
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3067434780
Short name T502
Test name
Test status
Simulation time 146604657 ps
CPU time 2.91 seconds
Started Jun 06 01:16:33 PM PDT 24
Finished Jun 06 01:16:37 PM PDT 24
Peak memory 197648 kb
Host smart-ca33ff65-f30e-48d4-8c85-587f785e5eb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067434780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3067434780
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1950593236
Short name T120
Test name
Test status
Simulation time 306608131 ps
CPU time 1.1 seconds
Started Jun 06 01:16:41 PM PDT 24
Finished Jun 06 01:16:43 PM PDT 24
Peak memory 195212 kb
Host smart-16db8d38-7be8-4386-abb2-627aab7d13f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950593236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1950593236
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1449788004
Short name T96
Test name
Test status
Simulation time 58582184 ps
CPU time 0.62 seconds
Started Jun 06 01:15:54 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 182664 kb
Host smart-09fd6bc6-1920-4036-a060-69d2246a422c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449788004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1449788004
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1522167249
Short name T484
Test name
Test status
Simulation time 284573082 ps
CPU time 3.41 seconds
Started Jun 06 01:15:54 PM PDT 24
Finished Jun 06 01:15:58 PM PDT 24
Peak memory 193896 kb
Host smart-3d2d5329-0fbb-4745-901d-61b695de0744
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522167249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1522167249
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1609996896
Short name T31
Test name
Test status
Simulation time 18570979 ps
CPU time 0.54 seconds
Started Jun 06 01:15:54 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 182252 kb
Host smart-cbac0599-86d2-45a7-a410-e6b6c85281cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609996896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1609996896
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3727812037
Short name T581
Test name
Test status
Simulation time 24227227 ps
CPU time 0.62 seconds
Started Jun 06 01:16:10 PM PDT 24
Finished Jun 06 01:16:12 PM PDT 24
Peak memory 193332 kb
Host smart-9daabf63-c6f8-443e-b0ab-6f66760178dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727812037 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3727812037
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2226605060
Short name T514
Test name
Test status
Simulation time 12954938 ps
CPU time 0.55 seconds
Started Jun 06 01:15:55 PM PDT 24
Finished Jun 06 01:15:57 PM PDT 24
Peak memory 182664 kb
Host smart-6a5e2960-e01c-4734-bfcd-6f3b61c32812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226605060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2226605060
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3400525301
Short name T580
Test name
Test status
Simulation time 14522431 ps
CPU time 0.55 seconds
Started Jun 06 01:15:56 PM PDT 24
Finished Jun 06 01:15:58 PM PDT 24
Peak memory 182120 kb
Host smart-ad960903-7e7e-4339-8ddc-5b812c8f49a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400525301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3400525301
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2036568522
Short name T104
Test name
Test status
Simulation time 13136556 ps
CPU time 0.57 seconds
Started Jun 06 01:15:57 PM PDT 24
Finished Jun 06 01:15:58 PM PDT 24
Peak memory 191356 kb
Host smart-726bf6da-5606-4bc2-ae86-ad2906caa0fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036568522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2036568522
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.34915707
Short name T492
Test name
Test status
Simulation time 864701970 ps
CPU time 2.22 seconds
Started Jun 06 01:15:53 PM PDT 24
Finished Jun 06 01:15:55 PM PDT 24
Peak memory 197620 kb
Host smart-2a6443c7-0e10-4316-8620-6d2e15fd720b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34915707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.34915707
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2875875329
Short name T50
Test name
Test status
Simulation time 60150486 ps
CPU time 0.84 seconds
Started Jun 06 01:15:54 PM PDT 24
Finished Jun 06 01:15:56 PM PDT 24
Peak memory 193748 kb
Host smart-5722617c-035d-4e16-86c3-44758d9609ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875875329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2875875329
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2957686302
Short name T539
Test name
Test status
Simulation time 223374307 ps
CPU time 0.54 seconds
Started Jun 06 01:16:41 PM PDT 24
Finished Jun 06 01:16:43 PM PDT 24
Peak memory 182624 kb
Host smart-3c67970b-ce17-427c-8e4c-ccf86e75ad09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957686302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2957686302
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1532997818
Short name T477
Test name
Test status
Simulation time 44377598 ps
CPU time 0.55 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182548 kb
Host smart-3a3b3e6a-eddc-4f92-bed1-6c73a49e5f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532997818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1532997818
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.705702966
Short name T524
Test name
Test status
Simulation time 44737491 ps
CPU time 0.57 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182692 kb
Host smart-43b97daf-1839-459f-8ef6-cf1401523a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705702966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.705702966
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1455553816
Short name T575
Test name
Test status
Simulation time 27917040 ps
CPU time 0.52 seconds
Started Jun 06 01:16:41 PM PDT 24
Finished Jun 06 01:16:43 PM PDT 24
Peak memory 182108 kb
Host smart-069c3c8a-1b11-414b-bfb8-e4b2c708de7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455553816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1455553816
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4158997872
Short name T504
Test name
Test status
Simulation time 183978378 ps
CPU time 0.55 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182588 kb
Host smart-fd00567c-f15a-4dd2-9dee-00bdc625bf30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158997872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.4158997872
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3183677251
Short name T480
Test name
Test status
Simulation time 15591606 ps
CPU time 0.57 seconds
Started Jun 06 01:16:43 PM PDT 24
Finished Jun 06 01:16:45 PM PDT 24
Peak memory 182672 kb
Host smart-4fd44b2a-9908-470d-9f25-015a1a81b4f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183677251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3183677251
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3306576784
Short name T508
Test name
Test status
Simulation time 59128704 ps
CPU time 0.56 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182800 kb
Host smart-f672946e-13d4-4fd5-ad53-3d9551f4af48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306576784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3306576784
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2422631779
Short name T468
Test name
Test status
Simulation time 46091931 ps
CPU time 0.57 seconds
Started Jun 06 01:16:44 PM PDT 24
Finished Jun 06 01:16:46 PM PDT 24
Peak memory 182472 kb
Host smart-92a7917e-4eab-4c52-b1d7-8d2bbba4fa2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422631779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2422631779
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.247476314
Short name T519
Test name
Test status
Simulation time 15273876 ps
CPU time 0.57 seconds
Started Jun 06 01:16:43 PM PDT 24
Finished Jun 06 01:16:45 PM PDT 24
Peak memory 182632 kb
Host smart-0e452898-086f-493f-aa5e-dd5efb488d79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247476314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.247476314
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.323098571
Short name T470
Test name
Test status
Simulation time 20421234 ps
CPU time 0.55 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182012 kb
Host smart-b1b6d480-2221-4d4c-b608-680e6254eb89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323098571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.323098571
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2848017636
Short name T564
Test name
Test status
Simulation time 20724373 ps
CPU time 0.62 seconds
Started Jun 06 01:16:09 PM PDT 24
Finished Jun 06 01:16:11 PM PDT 24
Peak memory 182764 kb
Host smart-27ffb5cb-a658-4d29-8588-8785d3d15506
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848017636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2848017636
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.150614298
Short name T48
Test name
Test status
Simulation time 128972210 ps
CPU time 1.6 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 191120 kb
Host smart-200f5764-3dde-47e5-b4a4-32e4e9d4dbaa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150614298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.150614298
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3693174427
Short name T99
Test name
Test status
Simulation time 86648001 ps
CPU time 0.56 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 182636 kb
Host smart-f5cdfec7-f642-4aaa-8c66-bb3266ea0ff2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693174427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3693174427
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.742631230
Short name T571
Test name
Test status
Simulation time 24083708 ps
CPU time 0.69 seconds
Started Jun 06 01:16:07 PM PDT 24
Finished Jun 06 01:16:09 PM PDT 24
Peak memory 194352 kb
Host smart-30e865f9-b706-4c3b-9cfc-cacb4700e17a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742631230 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.742631230
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3020963043
Short name T562
Test name
Test status
Simulation time 15148889 ps
CPU time 0.58 seconds
Started Jun 06 01:16:06 PM PDT 24
Finished Jun 06 01:16:07 PM PDT 24
Peak memory 182752 kb
Host smart-63389b12-f8e8-4f93-b33a-c49a814734d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020963043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3020963043
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3531976495
Short name T460
Test name
Test status
Simulation time 14277048 ps
CPU time 0.55 seconds
Started Jun 06 01:16:10 PM PDT 24
Finished Jun 06 01:16:12 PM PDT 24
Peak memory 182688 kb
Host smart-fa4baeee-4d26-459e-844b-fc091e40d82f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531976495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3531976495
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4238482881
Short name T101
Test name
Test status
Simulation time 169717289 ps
CPU time 0.67 seconds
Started Jun 06 01:16:06 PM PDT 24
Finished Jun 06 01:16:08 PM PDT 24
Peak memory 192004 kb
Host smart-ac0ac5e4-6d80-43bf-8ce1-d098417ac564
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238482881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4238482881
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.762291608
Short name T556
Test name
Test status
Simulation time 315603384 ps
CPU time 2.59 seconds
Started Jun 06 01:16:07 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 197644 kb
Host smart-cf77294e-6b11-453a-9930-f3ec61abc4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762291608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.762291608
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.4109588206
Short name T525
Test name
Test status
Simulation time 378812414 ps
CPU time 1.28 seconds
Started Jun 06 01:16:05 PM PDT 24
Finished Jun 06 01:16:07 PM PDT 24
Peak memory 195276 kb
Host smart-e7683bbe-0ba4-4cb9-9040-139721e1e73c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109588206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.4109588206
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3115792453
Short name T552
Test name
Test status
Simulation time 22279128 ps
CPU time 0.5 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182088 kb
Host smart-f191d41a-0770-42ae-80f0-fba19bf7c188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115792453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3115792453
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2250916838
Short name T500
Test name
Test status
Simulation time 40934387 ps
CPU time 0.51 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:43 PM PDT 24
Peak memory 182072 kb
Host smart-30452618-4a51-49a8-bbdf-c0210952eed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250916838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2250916838
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3782297374
Short name T585
Test name
Test status
Simulation time 16415124 ps
CPU time 0.61 seconds
Started Jun 06 01:16:44 PM PDT 24
Finished Jun 06 01:16:46 PM PDT 24
Peak memory 182540 kb
Host smart-3116cff0-487c-4658-a847-e38e4680487c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782297374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3782297374
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1737122395
Short name T476
Test name
Test status
Simulation time 16842389 ps
CPU time 0.58 seconds
Started Jun 06 01:16:41 PM PDT 24
Finished Jun 06 01:16:42 PM PDT 24
Peak memory 182596 kb
Host smart-02a072a0-89e3-4daa-8769-b90b0ae80984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737122395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1737122395
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1559270770
Short name T567
Test name
Test status
Simulation time 27279339 ps
CPU time 0.59 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182696 kb
Host smart-7cd91d8a-a7a8-4732-941a-394663c3acdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559270770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1559270770
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1489939414
Short name T505
Test name
Test status
Simulation time 26351925 ps
CPU time 0.56 seconds
Started Jun 06 01:16:41 PM PDT 24
Finished Jun 06 01:16:43 PM PDT 24
Peak memory 182092 kb
Host smart-57997ef9-6dbf-4f31-b3dd-fa9b06ddcbb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489939414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1489939414
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2484375131
Short name T481
Test name
Test status
Simulation time 14248256 ps
CPU time 0.58 seconds
Started Jun 06 01:16:44 PM PDT 24
Finished Jun 06 01:16:46 PM PDT 24
Peak memory 181964 kb
Host smart-6f2aa4cb-6da7-4503-8fa8-cef3c9b67aea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484375131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2484375131
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.17088052
Short name T491
Test name
Test status
Simulation time 68081719 ps
CPU time 0.56 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:43 PM PDT 24
Peak memory 182636 kb
Host smart-dc325269-59d1-41b8-b479-bc6e6dc976fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17088052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.17088052
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4024856680
Short name T497
Test name
Test status
Simulation time 12281746 ps
CPU time 0.54 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182592 kb
Host smart-42729fb8-8bd1-4bdf-b2e3-80c74ffa1d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024856680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4024856680
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3731815851
Short name T490
Test name
Test status
Simulation time 46617836 ps
CPU time 0.56 seconds
Started Jun 06 01:16:43 PM PDT 24
Finished Jun 06 01:16:45 PM PDT 24
Peak memory 182588 kb
Host smart-767e4d91-dd3d-4818-85eb-9e3a1770d9de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731815851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3731815851
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1307358183
Short name T90
Test name
Test status
Simulation time 54992810 ps
CPU time 0.84 seconds
Started Jun 06 01:16:13 PM PDT 24
Finished Jun 06 01:16:14 PM PDT 24
Peak memory 192604 kb
Host smart-9f7578b8-e177-4b36-b627-5601ab610a78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307358183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1307358183
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3322737755
Short name T469
Test name
Test status
Simulation time 203090089 ps
CPU time 1.57 seconds
Started Jun 06 01:16:22 PM PDT 24
Finished Jun 06 01:16:25 PM PDT 24
Peak memory 193372 kb
Host smart-213ae8de-8301-4812-940e-19866e3006a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322737755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3322737755
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1711343289
Short name T493
Test name
Test status
Simulation time 46365276 ps
CPU time 0.56 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 182740 kb
Host smart-6cae32b8-2f3d-434d-963e-3ba4b5b1aefd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711343289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1711343289
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.190522208
Short name T532
Test name
Test status
Simulation time 37937884 ps
CPU time 0.77 seconds
Started Jun 06 01:16:18 PM PDT 24
Finished Jun 06 01:16:20 PM PDT 24
Peak memory 195096 kb
Host smart-f4a0c46f-93a2-4036-ba8f-771c1f375855
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190522208 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.190522208
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.534825399
Short name T566
Test name
Test status
Simulation time 14194191 ps
CPU time 0.57 seconds
Started Jun 06 01:16:09 PM PDT 24
Finished Jun 06 01:16:11 PM PDT 24
Peak memory 182744 kb
Host smart-7a86d0ff-2bca-4340-8d4e-fbe65c23e884
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534825399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.534825399
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1254023024
Short name T507
Test name
Test status
Simulation time 21876697 ps
CPU time 0.55 seconds
Started Jun 06 01:16:06 PM PDT 24
Finished Jun 06 01:16:08 PM PDT 24
Peak memory 182640 kb
Host smart-b11a4736-cafa-4723-b3f1-ca0a8c38acae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254023024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1254023024
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4137992507
Short name T49
Test name
Test status
Simulation time 21853429 ps
CPU time 0.64 seconds
Started Jun 06 01:16:09 PM PDT 24
Finished Jun 06 01:16:11 PM PDT 24
Peak memory 191996 kb
Host smart-db4a9f34-cc44-4eb9-9a06-bde7f135e924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137992507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.4137992507
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1109125821
Short name T540
Test name
Test status
Simulation time 55160346 ps
CPU time 1.25 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:11 PM PDT 24
Peak memory 197480 kb
Host smart-824241b1-e430-4c73-bdea-ff75fb86db0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109125821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1109125821
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2144949966
Short name T461
Test name
Test status
Simulation time 42396361 ps
CPU time 0.55 seconds
Started Jun 06 01:16:40 PM PDT 24
Finished Jun 06 01:16:42 PM PDT 24
Peak memory 182664 kb
Host smart-e52297e4-5b4f-4d29-853d-59d26a2c3db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144949966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2144949966
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1430040393
Short name T509
Test name
Test status
Simulation time 63806942 ps
CPU time 0.57 seconds
Started Jun 06 01:16:45 PM PDT 24
Finished Jun 06 01:16:46 PM PDT 24
Peak memory 182656 kb
Host smart-a724baf6-bdd2-4c43-ac27-8d32ee17996d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430040393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1430040393
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2601759029
Short name T475
Test name
Test status
Simulation time 36304777 ps
CPU time 0.53 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182116 kb
Host smart-2377e290-9eff-4c4d-87fd-7f3e9bdfa163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601759029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2601759029
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1971174955
Short name T472
Test name
Test status
Simulation time 56825083 ps
CPU time 0.58 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:45 PM PDT 24
Peak memory 182612 kb
Host smart-6220d79e-c43a-437e-b91c-b506d866af9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971174955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1971174955
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3322367640
Short name T467
Test name
Test status
Simulation time 21512907 ps
CPU time 0.59 seconds
Started Jun 06 01:16:43 PM PDT 24
Finished Jun 06 01:16:45 PM PDT 24
Peak memory 182548 kb
Host smart-2df47262-cd32-4389-894d-32c14b19d3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322367640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3322367640
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3395592519
Short name T538
Test name
Test status
Simulation time 19941933 ps
CPU time 0.55 seconds
Started Jun 06 01:16:41 PM PDT 24
Finished Jun 06 01:16:43 PM PDT 24
Peak memory 182076 kb
Host smart-aaa80c6a-9202-40f0-8b10-78a30bb5c87d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395592519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3395592519
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2959615781
Short name T488
Test name
Test status
Simulation time 42521488 ps
CPU time 0.54 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:44 PM PDT 24
Peak memory 182612 kb
Host smart-04edee82-2bc1-4614-b6c7-beca181687e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959615781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2959615781
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.200057852
Short name T568
Test name
Test status
Simulation time 11088462 ps
CPU time 0.55 seconds
Started Jun 06 01:16:42 PM PDT 24
Finished Jun 06 01:16:45 PM PDT 24
Peak memory 182084 kb
Host smart-c846c5d7-3ba5-480f-a3cd-0fcec7e4147a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200057852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.200057852
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2078551486
Short name T563
Test name
Test status
Simulation time 16455811 ps
CPU time 0.55 seconds
Started Jun 06 01:16:41 PM PDT 24
Finished Jun 06 01:16:42 PM PDT 24
Peak memory 182568 kb
Host smart-a16da13e-7c2d-4a4c-96a0-46299a25c7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078551486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2078551486
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1408543181
Short name T479
Test name
Test status
Simulation time 17185437 ps
CPU time 0.58 seconds
Started Jun 06 01:16:43 PM PDT 24
Finished Jun 06 01:16:45 PM PDT 24
Peak memory 182616 kb
Host smart-bbde13e2-30be-41b4-9093-d0f76004a79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408543181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1408543181
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2168642609
Short name T554
Test name
Test status
Simulation time 165788700 ps
CPU time 0.81 seconds
Started Jun 06 01:16:06 PM PDT 24
Finished Jun 06 01:16:07 PM PDT 24
Peak memory 195588 kb
Host smart-e597441c-ec5c-408e-b83f-9cb85a731036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168642609 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2168642609
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2795875950
Short name T515
Test name
Test status
Simulation time 14457327 ps
CPU time 0.55 seconds
Started Jun 06 01:16:06 PM PDT 24
Finished Jun 06 01:16:08 PM PDT 24
Peak memory 182360 kb
Host smart-b0ab2e93-cdd2-4975-b9da-2b3281747957
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795875950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2795875950
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3769229324
Short name T574
Test name
Test status
Simulation time 27351678 ps
CPU time 0.54 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 182592 kb
Host smart-ba1d3cc5-6c25-4891-a602-b2e28e5a9db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769229324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3769229324
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2221608529
Short name T106
Test name
Test status
Simulation time 36927952 ps
CPU time 0.61 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 191336 kb
Host smart-456e093d-74c7-433d-962d-b34c38c8e207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221608529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2221608529
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1879500074
Short name T576
Test name
Test status
Simulation time 305697396 ps
CPU time 1.88 seconds
Started Jun 06 01:16:05 PM PDT 24
Finished Jun 06 01:16:08 PM PDT 24
Peak memory 197596 kb
Host smart-727743fc-57db-424e-bd3e-c2186bbfeeac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879500074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1879500074
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3168756332
Short name T119
Test name
Test status
Simulation time 305976738 ps
CPU time 1.09 seconds
Started Jun 06 01:16:07 PM PDT 24
Finished Jun 06 01:16:09 PM PDT 24
Peak memory 195484 kb
Host smart-75cf85f9-a142-4d21-8ea2-d1eb9a77efa7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168756332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3168756332
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3148500232
Short name T546
Test name
Test status
Simulation time 22354971 ps
CPU time 0.75 seconds
Started Jun 06 01:16:18 PM PDT 24
Finished Jun 06 01:16:21 PM PDT 24
Peak memory 195384 kb
Host smart-e5be8ea8-e075-4ed1-872b-29eccee75a7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148500232 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3148500232
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1305709425
Short name T97
Test name
Test status
Simulation time 14046858 ps
CPU time 0.53 seconds
Started Jun 06 01:16:07 PM PDT 24
Finished Jun 06 01:16:09 PM PDT 24
Peak memory 182428 kb
Host smart-c9484c5b-9612-4c7f-a131-2ebe4642a7f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305709425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1305709425
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.22924220
Short name T506
Test name
Test status
Simulation time 109058620 ps
CPU time 0.54 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 182548 kb
Host smart-7e0943bd-1369-4f3f-8fb9-96f6d5016244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22924220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.22924220
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1598380072
Short name T543
Test name
Test status
Simulation time 229779228 ps
CPU time 0.76 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 193428 kb
Host smart-f25e635c-4863-4c02-b84b-d09237d76811
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598380072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1598380072
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1713707510
Short name T482
Test name
Test status
Simulation time 49600469 ps
CPU time 1.12 seconds
Started Jun 06 01:16:08 PM PDT 24
Finished Jun 06 01:16:10 PM PDT 24
Peak memory 197536 kb
Host smart-efbec28f-0054-416c-8e33-be12e19f5a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713707510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1713707510
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3357466222
Short name T121
Test name
Test status
Simulation time 274851852 ps
CPU time 1.08 seconds
Started Jun 06 01:16:09 PM PDT 24
Finished Jun 06 01:16:12 PM PDT 24
Peak memory 183404 kb
Host smart-111aee2b-b142-418d-accf-3a43e5180fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357466222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3357466222
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2673825243
Short name T471
Test name
Test status
Simulation time 46511837 ps
CPU time 0.85 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:19 PM PDT 24
Peak memory 196180 kb
Host smart-b5e35aa6-894c-4532-8c1f-033dedfefcf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673825243 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2673825243
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3183910490
Short name T474
Test name
Test status
Simulation time 11640814 ps
CPU time 0.57 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:20 PM PDT 24
Peak memory 182744 kb
Host smart-b79fa296-9067-4b60-9657-9e1069a09954
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183910490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3183910490
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.252014719
Short name T547
Test name
Test status
Simulation time 24879560 ps
CPU time 0.54 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:19 PM PDT 24
Peak memory 182676 kb
Host smart-9fdf5eed-20fb-4c56-9349-a6fe309b5e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252014719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.252014719
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3171146276
Short name T521
Test name
Test status
Simulation time 187418120 ps
CPU time 0.62 seconds
Started Jun 06 01:16:26 PM PDT 24
Finished Jun 06 01:16:27 PM PDT 24
Peak memory 191940 kb
Host smart-4f0779f0-990c-48e5-9a3c-593989140f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171146276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3171146276
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1933029078
Short name T51
Test name
Test status
Simulation time 283284165 ps
CPU time 1.63 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:21 PM PDT 24
Peak memory 196744 kb
Host smart-9bc2f6d3-0eff-4fc3-9c4b-cb07820d158e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933029078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1933029078
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3836551414
Short name T565
Test name
Test status
Simulation time 187335006 ps
CPU time 0.87 seconds
Started Jun 06 01:16:18 PM PDT 24
Finished Jun 06 01:16:21 PM PDT 24
Peak memory 193760 kb
Host smart-80c3aad6-0b0f-4899-ab64-c7d84b814423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836551414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3836551414
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3853765711
Short name T570
Test name
Test status
Simulation time 26736399 ps
CPU time 0.7 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:19 PM PDT 24
Peak memory 193996 kb
Host smart-c9cb94e6-c4de-4a54-bcd5-e2cbbf8512a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853765711 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3853765711
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2323975900
Short name T510
Test name
Test status
Simulation time 55955014 ps
CPU time 0.58 seconds
Started Jun 06 01:16:35 PM PDT 24
Finished Jun 06 01:16:37 PM PDT 24
Peak memory 182468 kb
Host smart-a40139a2-668d-4277-9826-e7d7f464ef1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323975900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2323975900
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3143504477
Short name T465
Test name
Test status
Simulation time 34710487 ps
CPU time 0.58 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:19 PM PDT 24
Peak memory 182588 kb
Host smart-75bb2775-e5ad-4e68-b0cc-c1d7ddb8162d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143504477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3143504477
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3055432690
Short name T534
Test name
Test status
Simulation time 19903493 ps
CPU time 0.74 seconds
Started Jun 06 01:16:18 PM PDT 24
Finished Jun 06 01:16:20 PM PDT 24
Peak memory 193248 kb
Host smart-9a2fdfbd-3a86-406e-9b98-3c2e728c5679
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055432690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3055432690
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.780182164
Short name T560
Test name
Test status
Simulation time 624876608 ps
CPU time 2.25 seconds
Started Jun 06 01:16:15 PM PDT 24
Finished Jun 06 01:16:18 PM PDT 24
Peak memory 197604 kb
Host smart-d2a111d9-048d-43ca-9c67-1d59a718fad5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780182164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.780182164
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2018423075
Short name T28
Test name
Test status
Simulation time 79052119 ps
CPU time 1.09 seconds
Started Jun 06 01:16:17 PM PDT 24
Finished Jun 06 01:16:19 PM PDT 24
Peak memory 195020 kb
Host smart-d0af24c9-34f0-4bbe-a30b-a73c929c45c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018423075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2018423075
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1197506832
Short name T47
Test name
Test status
Simulation time 38918563 ps
CPU time 0.94 seconds
Started Jun 06 01:16:16 PM PDT 24
Finished Jun 06 01:16:18 PM PDT 24
Peak memory 196844 kb
Host smart-50771b08-068d-408d-9e35-1e603a776a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197506832 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1197506832
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.892961038
Short name T520
Test name
Test status
Simulation time 11755978 ps
CPU time 0.55 seconds
Started Jun 06 01:16:19 PM PDT 24
Finished Jun 06 01:16:21 PM PDT 24
Peak memory 182656 kb
Host smart-628953d1-0a35-4c9c-af94-13afd05ec181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892961038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.892961038
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.234438803
Short name T573
Test name
Test status
Simulation time 35784865 ps
CPU time 0.55 seconds
Started Jun 06 01:16:18 PM PDT 24
Finished Jun 06 01:16:21 PM PDT 24
Peak memory 182688 kb
Host smart-28c2d32d-5e5e-45a9-bae1-396a14ceb19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234438803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.234438803
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1093546528
Short name T92
Test name
Test status
Simulation time 132563595 ps
CPU time 0.81 seconds
Started Jun 06 01:16:25 PM PDT 24
Finished Jun 06 01:16:27 PM PDT 24
Peak memory 193528 kb
Host smart-e830d985-7b0f-4fbb-b74b-5ab5f05b7c7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093546528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1093546528
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1687342387
Short name T52
Test name
Test status
Simulation time 138639696 ps
CPU time 2.54 seconds
Started Jun 06 01:16:18 PM PDT 24
Finished Jun 06 01:16:23 PM PDT 24
Peak memory 197868 kb
Host smart-7e105dcd-05de-47fa-85f1-9e27050f9c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687342387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1687342387
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1531616397
Short name T559
Test name
Test status
Simulation time 101139278 ps
CPU time 1.34 seconds
Started Jun 06 01:16:15 PM PDT 24
Finished Jun 06 01:16:18 PM PDT 24
Peak memory 195352 kb
Host smart-d4dd2de4-6f61-4763-a9e5-1336ed97af6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531616397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1531616397
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2580851699
Short name T55
Test name
Test status
Simulation time 268131866704 ps
CPU time 233.39 seconds
Started Jun 06 02:20:21 PM PDT 24
Finished Jun 06 02:24:16 PM PDT 24
Peak memory 183068 kb
Host smart-b665f970-cf66-4ff8-9958-bd0dfa638184
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580851699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2580851699
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2023203726
Short name T402
Test name
Test status
Simulation time 111431683181 ps
CPU time 150.03 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:22:53 PM PDT 24
Peak memory 183024 kb
Host smart-fe0eda6e-96eb-4f35-ba74-9f16736e7ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023203726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2023203726
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1863279423
Short name T433
Test name
Test status
Simulation time 86027506 ps
CPU time 0.63 seconds
Started Jun 06 02:20:23 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 182700 kb
Host smart-d080e9ac-971f-4b02-8468-23561f3e92b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863279423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1863279423
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2811393582
Short name T429
Test name
Test status
Simulation time 38958876646 ps
CPU time 72.41 seconds
Started Jun 06 02:20:23 PM PDT 24
Finished Jun 06 02:21:37 PM PDT 24
Peak memory 183060 kb
Host smart-7630fd84-e609-4b38-9ae4-8d90d0c3f897
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811393582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2811393582
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2192136778
Short name T368
Test name
Test status
Simulation time 12932099744 ps
CPU time 11.04 seconds
Started Jun 06 02:20:40 PM PDT 24
Finished Jun 06 02:20:52 PM PDT 24
Peak memory 183076 kb
Host smart-e274cfb0-9a3d-482d-914f-3aed4deade1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192136778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2192136778
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.965697149
Short name T16
Test name
Test status
Simulation time 158464279 ps
CPU time 0.79 seconds
Started Jun 06 02:20:23 PM PDT 24
Finished Jun 06 02:20:25 PM PDT 24
Peak memory 213380 kb
Host smart-02fc73c3-0d81-47ca-85a4-3711aa1cad8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965697149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.965697149
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3734867427
Short name T148
Test name
Test status
Simulation time 128243746563 ps
CPU time 175.99 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 02:23:34 PM PDT 24
Peak memory 183072 kb
Host smart-92390d2b-c0ed-4cf1-8dc2-f7b78c947819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734867427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3734867427
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3063939494
Short name T20
Test name
Test status
Simulation time 88965041285 ps
CPU time 51.16 seconds
Started Jun 06 02:20:43 PM PDT 24
Finished Jun 06 02:21:36 PM PDT 24
Peak memory 183072 kb
Host smart-7470ea5a-e14b-40f6-a8f7-38bcaebf5f4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063939494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3063939494
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2025198416
Short name T388
Test name
Test status
Simulation time 675297523539 ps
CPU time 288.83 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:25:34 PM PDT 24
Peak memory 183084 kb
Host smart-618f1b77-1461-44ab-9721-660380a6605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025198416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2025198416
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4137683901
Short name T425
Test name
Test status
Simulation time 800271601 ps
CPU time 1.58 seconds
Started Jun 06 02:20:46 PM PDT 24
Finished Jun 06 02:20:49 PM PDT 24
Peak memory 183012 kb
Host smart-4248c8c9-6e7d-4b59-b8ad-9bf19715c8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137683901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4137683901
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.670770910
Short name T426
Test name
Test status
Simulation time 23918685200 ps
CPU time 249.33 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:24:55 PM PDT 24
Peak memory 205752 kb
Host smart-8b0cd1b0-6f51-470c-9760-c7de8bf966aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670770910 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.670770910
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.4039344228
Short name T273
Test name
Test status
Simulation time 1346949643962 ps
CPU time 512.04 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:29:44 PM PDT 24
Peak memory 191204 kb
Host smart-ff211123-1d4d-4c63-bf2e-7defa90113dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039344228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4039344228
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.716793018
Short name T457
Test name
Test status
Simulation time 157342858038 ps
CPU time 511.73 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:29:41 PM PDT 24
Peak memory 191300 kb
Host smart-5dca0cf4-d6ac-49aa-9015-cbcbd782083a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716793018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.716793018
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.750157576
Short name T208
Test name
Test status
Simulation time 653714788391 ps
CPU time 679.53 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:32:28 PM PDT 24
Peak memory 191212 kb
Host smart-9a345ee0-6043-498c-bda2-f186f8d497b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750157576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.750157576
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2239708335
Short name T25
Test name
Test status
Simulation time 63307570219 ps
CPU time 94.45 seconds
Started Jun 06 02:21:14 PM PDT 24
Finished Jun 06 02:22:50 PM PDT 24
Peak memory 191216 kb
Host smart-ba77cab6-0d75-49b2-b61f-7116062419a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239708335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2239708335
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1267657466
Short name T449
Test name
Test status
Simulation time 1660660620 ps
CPU time 2.48 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:21:13 PM PDT 24
Peak memory 182960 kb
Host smart-b5eefbc4-6287-481d-b14c-bae16f978731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267657466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1267657466
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1053562897
Short name T334
Test name
Test status
Simulation time 5156940711 ps
CPU time 6.17 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:21:15 PM PDT 24
Peak memory 182992 kb
Host smart-5405d45a-7bfe-48d7-8d4a-bafd9e04bced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053562897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1053562897
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3744320858
Short name T333
Test name
Test status
Simulation time 174317671723 ps
CPU time 134.52 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:23:21 PM PDT 24
Peak memory 191256 kb
Host smart-7ca3b7e9-5902-4e18-82d2-de59cfc8c8fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744320858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3744320858
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3914949178
Short name T359
Test name
Test status
Simulation time 48047107713 ps
CPU time 84.61 seconds
Started Jun 06 02:20:59 PM PDT 24
Finished Jun 06 02:22:24 PM PDT 24
Peak memory 191260 kb
Host smart-c4d9f336-2229-4bf5-b90f-90b3db763895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914949178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3914949178
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3793509689
Short name T127
Test name
Test status
Simulation time 63036081755 ps
CPU time 107.52 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:22:59 PM PDT 24
Peak memory 191260 kb
Host smart-c0cdda08-8506-47a5-900d-a5da7adf5952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793509689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3793509689
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3587122324
Short name T154
Test name
Test status
Simulation time 4471666534899 ps
CPU time 1330.33 seconds
Started Jun 06 02:20:53 PM PDT 24
Finished Jun 06 02:43:05 PM PDT 24
Peak memory 183068 kb
Host smart-c54f7786-09fa-4c6f-baf9-770ef57cae1a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587122324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3587122324
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2245346446
Short name T410
Test name
Test status
Simulation time 173490155748 ps
CPU time 146.67 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:23:20 PM PDT 24
Peak memory 183072 kb
Host smart-1647c196-9b7c-4a0c-bcc1-2a894399e42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245346446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2245346446
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3736387870
Short name T297
Test name
Test status
Simulation time 68562826509 ps
CPU time 54.48 seconds
Started Jun 06 02:20:36 PM PDT 24
Finished Jun 06 02:21:32 PM PDT 24
Peak memory 183100 kb
Host smart-fe0b3155-8002-4188-909f-1dec9dc0faf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736387870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3736387870
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1816535721
Short name T225
Test name
Test status
Simulation time 135819878405 ps
CPU time 335.44 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:26:26 PM PDT 24
Peak memory 183048 kb
Host smart-a7a08870-48a6-43ca-a644-7c7a311c4379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816535721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1816535721
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.559367677
Short name T279
Test name
Test status
Simulation time 39698844020 ps
CPU time 58.75 seconds
Started Jun 06 02:21:12 PM PDT 24
Finished Jun 06 02:22:12 PM PDT 24
Peak memory 193260 kb
Host smart-58ad79a1-d8bf-40c8-835f-b5c6599ff86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559367677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.559367677
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.482533800
Short name T411
Test name
Test status
Simulation time 241826223975 ps
CPU time 153.33 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:23:48 PM PDT 24
Peak memory 191232 kb
Host smart-77758700-955a-49e8-86d6-bdf086f805d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482533800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.482533800
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2184649789
Short name T224
Test name
Test status
Simulation time 216811629598 ps
CPU time 71.98 seconds
Started Jun 06 02:21:21 PM PDT 24
Finished Jun 06 02:22:34 PM PDT 24
Peak memory 191248 kb
Host smart-f0aa0d18-96ba-4888-aed5-a63ee1444d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184649789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2184649789
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2328533021
Short name T109
Test name
Test status
Simulation time 106629899498 ps
CPU time 198.82 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:24:28 PM PDT 24
Peak memory 194088 kb
Host smart-51e85cd4-f3a5-4966-b414-d01d38847a7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328533021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2328533021
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1686983770
Short name T256
Test name
Test status
Simulation time 124771915848 ps
CPU time 202.68 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:24:37 PM PDT 24
Peak memory 193728 kb
Host smart-2630345d-a9fb-43e1-a541-6ed905fe956c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686983770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1686983770
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1949903164
Short name T347
Test name
Test status
Simulation time 131448030200 ps
CPU time 287.47 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:25:59 PM PDT 24
Peak memory 194236 kb
Host smart-4771c8da-5d93-481a-a5c0-cda6e0d61cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949903164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1949903164
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2663421613
Short name T152
Test name
Test status
Simulation time 91152947559 ps
CPU time 253.93 seconds
Started Jun 06 02:21:12 PM PDT 24
Finished Jun 06 02:25:27 PM PDT 24
Peak memory 191212 kb
Host smart-4401ce9a-e019-42cb-8826-3a0f171bf0c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663421613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2663421613
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3995651503
Short name T138
Test name
Test status
Simulation time 221410348814 ps
CPU time 399.84 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:27:25 PM PDT 24
Peak memory 183068 kb
Host smart-3e02a203-0444-4c7a-8b1b-4c835e4bc2a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995651503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3995651503
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3008388940
Short name T362
Test name
Test status
Simulation time 428326376336 ps
CPU time 163.4 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:23:33 PM PDT 24
Peak memory 183000 kb
Host smart-9d5e6ad6-087c-4566-bb47-68bd6e3b617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008388940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3008388940
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2873340898
Short name T432
Test name
Test status
Simulation time 44557579075 ps
CPU time 398.96 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:27:32 PM PDT 24
Peak memory 183036 kb
Host smart-736e02a3-11b4-4e0e-9615-b2aaa528b4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873340898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2873340898
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3314024562
Short name T65
Test name
Test status
Simulation time 76076362252 ps
CPU time 110.2 seconds
Started Jun 06 02:20:49 PM PDT 24
Finished Jun 06 02:22:40 PM PDT 24
Peak memory 191224 kb
Host smart-b917ffaf-f5ca-4e05-b8d5-3b53b1a351fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314024562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3314024562
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.3912774142
Short name T116
Test name
Test status
Simulation time 85879116180 ps
CPU time 74.17 seconds
Started Jun 06 02:21:21 PM PDT 24
Finished Jun 06 02:22:36 PM PDT 24
Peak memory 183064 kb
Host smart-8e4f0205-934b-4898-8cd3-fc1dd1fa9785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912774142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3912774142
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.978819404
Short name T326
Test name
Test status
Simulation time 382986424711 ps
CPU time 416.33 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:28:25 PM PDT 24
Peak memory 190944 kb
Host smart-903bcf87-fcf3-4756-8362-3ef3b80b7fcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978819404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.978819404
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3648971748
Short name T423
Test name
Test status
Simulation time 72246790415 ps
CPU time 66.48 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:22:28 PM PDT 24
Peak memory 183016 kb
Host smart-b819a016-6ca2-43fc-b9c8-dbc846d055ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648971748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3648971748
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3977234223
Short name T360
Test name
Test status
Simulation time 135745431001 ps
CPU time 1515.07 seconds
Started Jun 06 02:21:16 PM PDT 24
Finished Jun 06 02:46:32 PM PDT 24
Peak memory 191208 kb
Host smart-c898c5b0-d4cc-44c3-b7fa-84e8e18731db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977234223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3977234223
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2597775212
Short name T446
Test name
Test status
Simulation time 48755609674 ps
CPU time 249.49 seconds
Started Jun 06 02:21:26 PM PDT 24
Finished Jun 06 02:25:37 PM PDT 24
Peak memory 191224 kb
Host smart-b526398f-31dd-4152-b26d-18c7e7a971da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597775212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2597775212
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2015231831
Short name T322
Test name
Test status
Simulation time 896744316057 ps
CPU time 1006.58 seconds
Started Jun 06 02:21:21 PM PDT 24
Finished Jun 06 02:38:09 PM PDT 24
Peak memory 191232 kb
Host smart-59afee0c-4dd6-427f-8802-7e645389e5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015231831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2015231831
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3949030005
Short name T354
Test name
Test status
Simulation time 27436501694 ps
CPU time 16.24 seconds
Started Jun 06 02:20:39 PM PDT 24
Finished Jun 06 02:20:57 PM PDT 24
Peak memory 183080 kb
Host smart-9424a58d-6afe-433c-880d-31e2d2cb57ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949030005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3949030005
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3399295520
Short name T378
Test name
Test status
Simulation time 245052752674 ps
CPU time 108.88 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:22:40 PM PDT 24
Peak memory 183048 kb
Host smart-962fe1b0-ed9b-4281-9698-76be157de4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399295520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3399295520
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1774971518
Short name T375
Test name
Test status
Simulation time 288703821 ps
CPU time 0.8 seconds
Started Jun 06 02:20:40 PM PDT 24
Finished Jun 06 02:20:41 PM PDT 24
Peak memory 182816 kb
Host smart-51e2ef35-ab97-4c95-8f09-506b513263bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774971518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1774971518
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1373739347
Short name T37
Test name
Test status
Simulation time 48381723344 ps
CPU time 539.46 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:29:52 PM PDT 24
Peak memory 197664 kb
Host smart-6f15f53b-f640-4f79-ad9e-c5fdee4f3642
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373739347 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1373739347
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.207436266
Short name T110
Test name
Test status
Simulation time 385084645710 ps
CPU time 595.56 seconds
Started Jun 06 02:21:17 PM PDT 24
Finished Jun 06 02:31:13 PM PDT 24
Peak memory 191220 kb
Host smart-eb4324a8-a828-4c44-96a2-cca354fc99cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207436266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.207436266
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2156532728
Short name T181
Test name
Test status
Simulation time 127688592263 ps
CPU time 215.81 seconds
Started Jun 06 02:21:19 PM PDT 24
Finished Jun 06 02:24:55 PM PDT 24
Peak memory 191224 kb
Host smart-a28c5f02-e2a0-4223-8b4f-a7529f2aa04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156532728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2156532728
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1442772427
Short name T191
Test name
Test status
Simulation time 290900966835 ps
CPU time 180.14 seconds
Started Jun 06 02:21:30 PM PDT 24
Finished Jun 06 02:24:31 PM PDT 24
Peak memory 191256 kb
Host smart-4ddd9556-4370-4254-a8c1-cc3bd1df4525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442772427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1442772427
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2094696290
Short name T454
Test name
Test status
Simulation time 671988689490 ps
CPU time 351 seconds
Started Jun 06 02:21:18 PM PDT 24
Finished Jun 06 02:27:10 PM PDT 24
Peak memory 191224 kb
Host smart-53673aca-d3b2-4f03-bc88-00cca2938a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094696290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2094696290
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3365572345
Short name T436
Test name
Test status
Simulation time 12021005288 ps
CPU time 20.06 seconds
Started Jun 06 02:21:24 PM PDT 24
Finished Jun 06 02:21:45 PM PDT 24
Peak memory 191200 kb
Host smart-f4fd0ea0-44d8-44aa-a17f-a334fa0b79b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365572345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3365572345
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1435045379
Short name T259
Test name
Test status
Simulation time 369184087567 ps
CPU time 211.01 seconds
Started Jun 06 02:21:29 PM PDT 24
Finished Jun 06 02:25:00 PM PDT 24
Peak memory 191264 kb
Host smart-8086cff9-e4d3-4c54-8229-2eac1f241a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435045379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1435045379
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2900092546
Short name T202
Test name
Test status
Simulation time 162994175879 ps
CPU time 625.73 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:31:48 PM PDT 24
Peak memory 191252 kb
Host smart-2f30d1b4-26f5-4a1e-883a-5e7b7b047edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900092546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2900092546
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1195875837
Short name T386
Test name
Test status
Simulation time 106387613860 ps
CPU time 178.98 seconds
Started Jun 06 02:21:25 PM PDT 24
Finished Jun 06 02:24:25 PM PDT 24
Peak memory 183024 kb
Host smart-aba46daa-926f-4c8d-8667-237e6d4837d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195875837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1195875837
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3390946022
Short name T361
Test name
Test status
Simulation time 152821138924 ps
CPU time 156.55 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:23:48 PM PDT 24
Peak memory 191216 kb
Host smart-629f21f0-66ea-4d2c-abd7-525977727fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390946022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3390946022
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1604615234
Short name T137
Test name
Test status
Simulation time 208400877407 ps
CPU time 690.44 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:32:44 PM PDT 24
Peak memory 191224 kb
Host smart-ee01c42c-5dc4-4389-881a-7889a0f27191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604615234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1604615234
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.154274473
Short name T282
Test name
Test status
Simulation time 20576234525 ps
CPU time 32.01 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:21:17 PM PDT 24
Peak memory 182996 kb
Host smart-e040556f-35cb-4e71-9c55-a7d69fdac6c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154274473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.154274473
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3860078945
Short name T112
Test name
Test status
Simulation time 109483929240 ps
CPU time 49.59 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:21:35 PM PDT 24
Peak memory 183060 kb
Host smart-412280d4-06ea-4cea-b228-72c465b9d8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860078945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3860078945
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.653185623
Short name T129
Test name
Test status
Simulation time 143254137979 ps
CPU time 520.89 seconds
Started Jun 06 02:20:35 PM PDT 24
Finished Jun 06 02:29:17 PM PDT 24
Peak memory 191252 kb
Host smart-2906bb00-558a-45d9-9521-25f94912ed1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653185623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.653185623
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1807164767
Short name T419
Test name
Test status
Simulation time 357305874 ps
CPU time 0.92 seconds
Started Jun 06 02:20:43 PM PDT 24
Finished Jun 06 02:20:44 PM PDT 24
Peak memory 182860 kb
Host smart-56617c38-250d-4087-9e77-b2e7a9e9930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807164767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1807164767
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.2115481132
Short name T267
Test name
Test status
Simulation time 116154957841 ps
CPU time 1351.99 seconds
Started Jun 06 02:21:26 PM PDT 24
Finished Jun 06 02:43:59 PM PDT 24
Peak memory 191232 kb
Host smart-21da6e80-64fd-4775-a7ad-33fd7b537ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115481132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2115481132
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1877809016
Short name T41
Test name
Test status
Simulation time 177067390464 ps
CPU time 505.24 seconds
Started Jun 06 02:21:11 PM PDT 24
Finished Jun 06 02:29:38 PM PDT 24
Peak memory 191212 kb
Host smart-56450e42-2481-4231-afbd-5584d7300322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877809016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1877809016
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2697924976
Short name T175
Test name
Test status
Simulation time 171497307991 ps
CPU time 2486.94 seconds
Started Jun 06 02:21:17 PM PDT 24
Finished Jun 06 03:02:45 PM PDT 24
Peak memory 191244 kb
Host smart-07f1ac09-1e10-4221-a3c5-041c87241470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697924976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2697924976
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1111747811
Short name T240
Test name
Test status
Simulation time 31810405624 ps
CPU time 38.35 seconds
Started Jun 06 02:21:25 PM PDT 24
Finished Jun 06 02:22:05 PM PDT 24
Peak memory 183016 kb
Host smart-4c80680b-5d2a-44cb-b2bd-3bf827f22860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111747811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1111747811
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1437939352
Short name T302
Test name
Test status
Simulation time 161398697863 ps
CPU time 80.44 seconds
Started Jun 06 02:21:16 PM PDT 24
Finished Jun 06 02:22:37 PM PDT 24
Peak memory 191252 kb
Host smart-76e46290-6bdb-457e-bac5-5030c6298dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437939352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1437939352
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1261596621
Short name T325
Test name
Test status
Simulation time 9260458471 ps
CPU time 15.29 seconds
Started Jun 06 02:21:14 PM PDT 24
Finished Jun 06 02:21:30 PM PDT 24
Peak memory 182996 kb
Host smart-0d34ea7f-4034-4768-b71d-3265519a5be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261596621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1261596621
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1396120462
Short name T350
Test name
Test status
Simulation time 176542857648 ps
CPU time 113.69 seconds
Started Jun 06 02:21:22 PM PDT 24
Finished Jun 06 02:23:17 PM PDT 24
Peak memory 183008 kb
Host smart-a5fba479-ed16-40d0-8897-929dc09dba63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396120462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1396120462
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3297993785
Short name T223
Test name
Test status
Simulation time 148051555000 ps
CPU time 277.04 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:25:30 PM PDT 24
Peak memory 183076 kb
Host smart-a7a323e0-283d-45b2-a5a3-b9f04ba0e476
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297993785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3297993785
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2172410545
Short name T392
Test name
Test status
Simulation time 159294643554 ps
CPU time 122.45 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:22:44 PM PDT 24
Peak memory 183088 kb
Host smart-bc6b2573-0537-4ea6-a5c0-7c518f87e19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172410545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2172410545
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.781225537
Short name T134
Test name
Test status
Simulation time 64232261951 ps
CPU time 116.13 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:22:51 PM PDT 24
Peak memory 191216 kb
Host smart-bb8bd56e-9c4d-48fb-9f64-2444c536d93d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781225537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.781225537
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.4257910663
Short name T194
Test name
Test status
Simulation time 481798848279 ps
CPU time 1238.04 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:41:20 PM PDT 24
Peak memory 191216 kb
Host smart-bf48031f-1d87-43d0-8942-a985ca254910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257910663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.4257910663
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.168311042
Short name T211
Test name
Test status
Simulation time 143963555341 ps
CPU time 117.66 seconds
Started Jun 06 02:21:23 PM PDT 24
Finished Jun 06 02:23:22 PM PDT 24
Peak memory 183024 kb
Host smart-15c6f994-03eb-407e-8300-27f8149526b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168311042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.168311042
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2287194416
Short name T329
Test name
Test status
Simulation time 85711168447 ps
CPU time 237.6 seconds
Started Jun 06 02:21:15 PM PDT 24
Finished Jun 06 02:25:13 PM PDT 24
Peak memory 183080 kb
Host smart-daf11538-3332-4bf8-9a8a-a06e7a3c9364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287194416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2287194416
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.503610757
Short name T207
Test name
Test status
Simulation time 619809870228 ps
CPU time 911.19 seconds
Started Jun 06 02:21:25 PM PDT 24
Finished Jun 06 02:36:37 PM PDT 24
Peak memory 193912 kb
Host smart-02426a8f-baaa-482d-b41b-866ae8ec78cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503610757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.503610757
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2669258643
Short name T288
Test name
Test status
Simulation time 25789694699 ps
CPU time 177.7 seconds
Started Jun 06 02:21:23 PM PDT 24
Finished Jun 06 02:24:22 PM PDT 24
Peak memory 191224 kb
Host smart-3f3a5a0f-b7d9-46e7-9dd8-6387b2c9b89d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669258643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2669258643
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3912435674
Short name T261
Test name
Test status
Simulation time 436318800563 ps
CPU time 204.54 seconds
Started Jun 06 02:21:14 PM PDT 24
Finished Jun 06 02:24:40 PM PDT 24
Peak memory 191208 kb
Host smart-c9973276-bd8c-4eeb-a593-fe751c54179f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912435674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3912435674
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3382864643
Short name T167
Test name
Test status
Simulation time 254821883781 ps
CPU time 108.18 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:23:09 PM PDT 24
Peak memory 191256 kb
Host smart-9b950b04-f367-46f1-b225-682849d55509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382864643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3382864643
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4102777478
Short name T249
Test name
Test status
Simulation time 115885292146 ps
CPU time 122.25 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:23:30 PM PDT 24
Peak memory 191232 kb
Host smart-05b679b5-f16d-4c31-a2d1-a1fd141b3b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102777478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4102777478
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.609310140
Short name T190
Test name
Test status
Simulation time 151429519487 ps
CPU time 760.85 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:34:02 PM PDT 24
Peak memory 191240 kb
Host smart-c9ad96d8-e4e7-4849-a55f-bdc47799f306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609310140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.609310140
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2748208949
Short name T304
Test name
Test status
Simulation time 313572166987 ps
CPU time 500.28 seconds
Started Jun 06 02:20:42 PM PDT 24
Finished Jun 06 02:29:04 PM PDT 24
Peak memory 183072 kb
Host smart-1103b730-25fb-44a3-88af-5209028f60b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748208949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2748208949
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.4173100417
Short name T364
Test name
Test status
Simulation time 125854258674 ps
CPU time 179.16 seconds
Started Jun 06 02:21:03 PM PDT 24
Finished Jun 06 02:24:04 PM PDT 24
Peak memory 183032 kb
Host smart-52f5a11a-48e8-4311-b95f-1e6e4a9ff7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173100417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.4173100417
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/160.rv_timer_random.3937443082
Short name T229
Test name
Test status
Simulation time 306599073408 ps
CPU time 291.45 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:26:06 PM PDT 24
Peak memory 191256 kb
Host smart-b6b3fb61-6433-4fca-8522-c03b493e7115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937443082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3937443082
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2467368385
Short name T213
Test name
Test status
Simulation time 145251886672 ps
CPU time 262.17 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:25:50 PM PDT 24
Peak memory 191232 kb
Host smart-9de8d1c4-126e-4fac-b82e-827f9cbf7fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467368385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2467368385
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1282072448
Short name T216
Test name
Test status
Simulation time 83160327219 ps
CPU time 125.91 seconds
Started Jun 06 02:21:12 PM PDT 24
Finished Jun 06 02:23:19 PM PDT 24
Peak memory 194812 kb
Host smart-842609ee-763d-432f-8afc-d4bf9023dd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282072448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1282072448
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3435582122
Short name T214
Test name
Test status
Simulation time 98275245611 ps
CPU time 193.5 seconds
Started Jun 06 02:21:23 PM PDT 24
Finished Jun 06 02:24:37 PM PDT 24
Peak memory 191192 kb
Host smart-94253d98-c82a-4df0-b5b1-e3f82c36bc4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435582122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3435582122
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.4198012678
Short name T447
Test name
Test status
Simulation time 159995471555 ps
CPU time 390.04 seconds
Started Jun 06 02:21:22 PM PDT 24
Finished Jun 06 02:27:53 PM PDT 24
Peak memory 183056 kb
Host smart-5f6a5290-7388-4865-bdc1-a48c9d1a7438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198012678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4198012678
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3385216442
Short name T307
Test name
Test status
Simulation time 53170388778 ps
CPU time 25.65 seconds
Started Jun 06 02:21:23 PM PDT 24
Finished Jun 06 02:21:49 PM PDT 24
Peak memory 183068 kb
Host smart-fdeb6a1d-bc60-451e-996d-49b9b94071ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385216442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3385216442
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.4001396308
Short name T310
Test name
Test status
Simulation time 161717664018 ps
CPU time 122.53 seconds
Started Jun 06 02:21:12 PM PDT 24
Finished Jun 06 02:23:16 PM PDT 24
Peak memory 191268 kb
Host smart-609dbffb-a5a5-4589-bf35-6b61eb2c6722
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001396308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.4001396308
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3855163776
Short name T301
Test name
Test status
Simulation time 123227857481 ps
CPU time 82.63 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:22:44 PM PDT 24
Peak memory 191200 kb
Host smart-b149d47c-2c53-4dfc-a7be-447550703546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855163776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3855163776
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2661279811
Short name T396
Test name
Test status
Simulation time 348239723971 ps
CPU time 108.39 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:22:59 PM PDT 24
Peak memory 191268 kb
Host smart-3af8a3e1-7bf7-4ae7-81ed-0ae7711d7e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661279811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2661279811
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.635434999
Short name T356
Test name
Test status
Simulation time 278144701461 ps
CPU time 149.73 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:23:41 PM PDT 24
Peak memory 183056 kb
Host smart-e2b0abfa-7338-4fe6-8050-48ca8745bc33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635434999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.635434999
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.4267072604
Short name T377
Test name
Test status
Simulation time 333629248842 ps
CPU time 188.34 seconds
Started Jun 06 02:20:40 PM PDT 24
Finished Jun 06 02:23:50 PM PDT 24
Peak memory 183076 kb
Host smart-054348f5-bde3-4597-999e-abd30edf8a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267072604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.4267072604
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3766498020
Short name T337
Test name
Test status
Simulation time 16642362493 ps
CPU time 31.24 seconds
Started Jun 06 02:20:51 PM PDT 24
Finished Jun 06 02:21:23 PM PDT 24
Peak memory 182964 kb
Host smart-5688fc58-a62b-40f1-84b4-a84be648e91b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766498020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3766498020
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.66062168
Short name T391
Test name
Test status
Simulation time 24063166610 ps
CPU time 14.81 seconds
Started Jun 06 02:20:53 PM PDT 24
Finished Jun 06 02:21:09 PM PDT 24
Peak memory 194636 kb
Host smart-3dac63e3-a4fc-4bcb-82d9-d5db671e33aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66062168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.66062168
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.140782559
Short name T12
Test name
Test status
Simulation time 11834377635 ps
CPU time 97.77 seconds
Started Jun 06 02:20:38 PM PDT 24
Finished Jun 06 02:22:17 PM PDT 24
Peak memory 197732 kb
Host smart-036c8413-95a7-49a8-837b-f06c7483e00f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140782559 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.140782559
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2439646881
Short name T317
Test name
Test status
Simulation time 180465144934 ps
CPU time 740.29 seconds
Started Jun 06 02:21:14 PM PDT 24
Finished Jun 06 02:33:36 PM PDT 24
Peak memory 183068 kb
Host smart-e5d7493b-e3df-40cc-ab6b-055dcabab37a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439646881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2439646881
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2106095661
Short name T263
Test name
Test status
Simulation time 64870806614 ps
CPU time 48.45 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:22:17 PM PDT 24
Peak memory 190936 kb
Host smart-d9cf41ec-aa63-45e9-93ff-77a9c67e9696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106095661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2106095661
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2980546684
Short name T199
Test name
Test status
Simulation time 188476919369 ps
CPU time 241.92 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:25:23 PM PDT 24
Peak memory 191264 kb
Host smart-27027c16-f1dd-4170-a955-0939655d4ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980546684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2980546684
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1825573663
Short name T124
Test name
Test status
Simulation time 394290621472 ps
CPU time 224.61 seconds
Started Jun 06 02:21:17 PM PDT 24
Finished Jun 06 02:25:02 PM PDT 24
Peak memory 191252 kb
Host smart-4ed50800-5ef3-460e-885c-35cc70bc1018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825573663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1825573663
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1661403493
Short name T174
Test name
Test status
Simulation time 571369276037 ps
CPU time 342.41 seconds
Started Jun 06 02:21:22 PM PDT 24
Finished Jun 06 02:27:05 PM PDT 24
Peak memory 191320 kb
Host smart-ef6bc82c-dda2-4c78-942a-520d9f4b45e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661403493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1661403493
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2074097928
Short name T23
Test name
Test status
Simulation time 300312952131 ps
CPU time 198.03 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:24:46 PM PDT 24
Peak memory 191264 kb
Host smart-63d51ee5-de80-45d6-8095-22e957f0a039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074097928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2074097928
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2248102998
Short name T226
Test name
Test status
Simulation time 118454866691 ps
CPU time 118.85 seconds
Started Jun 06 02:20:57 PM PDT 24
Finished Jun 06 02:22:56 PM PDT 24
Peak memory 183036 kb
Host smart-e76168da-6fd9-4059-ba10-a2c08bbddb5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248102998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2248102998
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2850242052
Short name T6
Test name
Test status
Simulation time 162009611223 ps
CPU time 273.29 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:25:32 PM PDT 24
Peak memory 183012 kb
Host smart-71cb5ec1-d291-472d-a338-ea15f1d18147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850242052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2850242052
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2878717748
Short name T459
Test name
Test status
Simulation time 13869991397 ps
CPU time 14.96 seconds
Started Jun 06 02:20:53 PM PDT 24
Finished Jun 06 02:21:09 PM PDT 24
Peak memory 183064 kb
Host smart-0dcdb7fb-b66f-4a01-a990-a61edf1530be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878717748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2878717748
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1046007607
Short name T9
Test name
Test status
Simulation time 44967190822 ps
CPU time 91.46 seconds
Started Jun 06 02:20:42 PM PDT 24
Finished Jun 06 02:22:14 PM PDT 24
Peak memory 183016 kb
Host smart-1dd86b86-e83c-4a07-ae73-38a7fb7513a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046007607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1046007607
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2751327087
Short name T424
Test name
Test status
Simulation time 101479789397 ps
CPU time 165.92 seconds
Started Jun 06 02:21:03 PM PDT 24
Finished Jun 06 02:23:50 PM PDT 24
Peak memory 195636 kb
Host smart-f0877210-ab4e-40ca-b2c4-479ed20049f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751327087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2751327087
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.540079145
Short name T36
Test name
Test status
Simulation time 21868850456 ps
CPU time 162.08 seconds
Started Jun 06 02:20:47 PM PDT 24
Finished Jun 06 02:23:30 PM PDT 24
Peak memory 197716 kb
Host smart-d7c78b83-407b-4b9a-b659-4785a7d76816
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540079145 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.540079145
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3641625036
Short name T220
Test name
Test status
Simulation time 252404115147 ps
CPU time 129.85 seconds
Started Jun 06 02:21:22 PM PDT 24
Finished Jun 06 02:23:33 PM PDT 24
Peak memory 191208 kb
Host smart-f919eaa1-3e72-41c5-a9aa-58d1223e6414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641625036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3641625036
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3963042181
Short name T246
Test name
Test status
Simulation time 30532221394 ps
CPU time 52.06 seconds
Started Jun 06 02:21:23 PM PDT 24
Finished Jun 06 02:22:16 PM PDT 24
Peak memory 183032 kb
Host smart-9a4a9f44-78d9-4809-b227-a5f9f2bfe4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963042181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3963042181
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.602796348
Short name T283
Test name
Test status
Simulation time 66790644791 ps
CPU time 49.02 seconds
Started Jun 06 02:21:14 PM PDT 24
Finished Jun 06 02:22:04 PM PDT 24
Peak memory 183036 kb
Host smart-c37c0fba-5ff3-4c0d-af75-128227c80e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602796348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.602796348
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1692063045
Short name T315
Test name
Test status
Simulation time 67526177852 ps
CPU time 110.24 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:23:18 PM PDT 24
Peak memory 191264 kb
Host smart-237b79c4-ad49-4ee9-a7f9-aa7b9be9747e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692063045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1692063045
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2956304694
Short name T324
Test name
Test status
Simulation time 81616770201 ps
CPU time 72.28 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:22:40 PM PDT 24
Peak memory 183068 kb
Host smart-fc0f9f19-5b38-4bf8-bd7e-1ae05f4b8a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956304694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2956304694
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2388393857
Short name T22
Test name
Test status
Simulation time 57525435287 ps
CPU time 99.1 seconds
Started Jun 06 02:20:46 PM PDT 24
Finished Jun 06 02:22:26 PM PDT 24
Peak memory 183068 kb
Host smart-3dcbc19a-e162-472b-9670-85a8fd1494c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388393857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2388393857
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.23002865
Short name T394
Test name
Test status
Simulation time 573442921839 ps
CPU time 181.87 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:23:52 PM PDT 24
Peak memory 183080 kb
Host smart-66383032-facf-424f-a63b-70ad568694e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23002865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.23002865
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.890740229
Short name T316
Test name
Test status
Simulation time 149432564175 ps
CPU time 1276.09 seconds
Started Jun 06 02:20:47 PM PDT 24
Finished Jun 06 02:42:04 PM PDT 24
Peak memory 191244 kb
Host smart-44f35e14-7dc0-477d-8fa9-9c5534af30be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890740229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.890740229
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.4231112437
Short name T365
Test name
Test status
Simulation time 135675848 ps
CPU time 0.63 seconds
Started Jun 06 02:20:46 PM PDT 24
Finished Jun 06 02:20:47 PM PDT 24
Peak memory 182796 kb
Host smart-6e5e0524-7498-42f1-9728-cbec7140751a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231112437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4231112437
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.3382384721
Short name T73
Test name
Test status
Simulation time 123892019284 ps
CPU time 165.54 seconds
Started Jun 06 02:21:30 PM PDT 24
Finished Jun 06 02:24:16 PM PDT 24
Peak memory 191224 kb
Host smart-a311355b-59b5-4343-a045-e9fc62d6a359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382384721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3382384721
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1229793935
Short name T274
Test name
Test status
Simulation time 74760447156 ps
CPU time 69.72 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:22:38 PM PDT 24
Peak memory 191244 kb
Host smart-824cc849-aeaf-4321-99fc-6a8bdef15dff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229793935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1229793935
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1225502925
Short name T172
Test name
Test status
Simulation time 148849156342 ps
CPU time 230.16 seconds
Started Jun 06 02:21:27 PM PDT 24
Finished Jun 06 02:25:18 PM PDT 24
Peak memory 191220 kb
Host smart-4e629107-b870-4884-8b8a-c8d0fdc205a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225502925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1225502925
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.442703361
Short name T234
Test name
Test status
Simulation time 1107233764517 ps
CPU time 2124.12 seconds
Started Jun 06 02:21:28 PM PDT 24
Finished Jun 06 02:56:53 PM PDT 24
Peak memory 191224 kb
Host smart-01805c84-6204-4f29-be0d-4f84c2a7584a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442703361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.442703361
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.772225712
Short name T58
Test name
Test status
Simulation time 96975993522 ps
CPU time 85.5 seconds
Started Jun 06 02:21:30 PM PDT 24
Finished Jun 06 02:22:56 PM PDT 24
Peak memory 183044 kb
Host smart-88fe89ec-4d36-4cb1-9ccc-5b36cebb60e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772225712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.772225712
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.565999785
Short name T40
Test name
Test status
Simulation time 86737428571 ps
CPU time 37.04 seconds
Started Jun 06 02:21:25 PM PDT 24
Finished Jun 06 02:22:03 PM PDT 24
Peak memory 183020 kb
Host smart-0bed7998-af93-408e-8d4d-8def876091ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565999785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.565999785
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.789044850
Short name T418
Test name
Test status
Simulation time 14818943599 ps
CPU time 26.44 seconds
Started Jun 06 02:21:21 PM PDT 24
Finished Jun 06 02:21:49 PM PDT 24
Peak memory 183076 kb
Host smart-0d7bb8a6-bb45-49fb-9cb1-d9a36d3dee7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789044850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.789044850
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.45775822
Short name T183
Test name
Test status
Simulation time 98095700992 ps
CPU time 328.99 seconds
Started Jun 06 02:21:14 PM PDT 24
Finished Jun 06 02:26:44 PM PDT 24
Peak memory 191232 kb
Host smart-46322afb-f462-4178-a814-1d555f2bce61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45775822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.45775822
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1407213757
Short name T308
Test name
Test status
Simulation time 105118423176 ps
CPU time 96.45 seconds
Started Jun 06 02:20:42 PM PDT 24
Finished Jun 06 02:22:19 PM PDT 24
Peak memory 183020 kb
Host smart-478077a5-2341-4508-b5e0-1ebf88316808
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407213757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1407213757
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3525666343
Short name T387
Test name
Test status
Simulation time 381512515647 ps
CPU time 164.29 seconds
Started Jun 06 02:20:27 PM PDT 24
Finished Jun 06 02:23:12 PM PDT 24
Peak memory 183048 kb
Host smart-6c3ffd3d-2f4b-4d82-bd23-0620f568e45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525666343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3525666343
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.20998144
Short name T149
Test name
Test status
Simulation time 226160747578 ps
CPU time 1881.3 seconds
Started Jun 06 02:20:43 PM PDT 24
Finished Jun 06 02:52:06 PM PDT 24
Peak memory 191216 kb
Host smart-469b093f-80a4-470d-b575-e47a6852077a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20998144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.20998144
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3538152084
Short name T355
Test name
Test status
Simulation time 281769166791 ps
CPU time 63.96 seconds
Started Jun 06 02:20:40 PM PDT 24
Finished Jun 06 02:21:45 PM PDT 24
Peak memory 191272 kb
Host smart-92535866-1637-4606-a88c-c61b83ef151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538152084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3538152084
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1809770095
Short name T15
Test name
Test status
Simulation time 198886079 ps
CPU time 0.76 seconds
Started Jun 06 02:20:48 PM PDT 24
Finished Jun 06 02:20:49 PM PDT 24
Peak memory 213444 kb
Host smart-2dff005f-b0a2-46f1-a961-c82b2fd295a5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809770095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1809770095
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.296238374
Short name T69
Test name
Test status
Simulation time 709315034809 ps
CPU time 282 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:25:23 PM PDT 24
Peak memory 191300 kb
Host smart-c50afbf4-fd3b-43e4-9a0e-18b419aebad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296238374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.296238374
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2495458090
Short name T34
Test name
Test status
Simulation time 29217700705 ps
CPU time 307.65 seconds
Started Jun 06 02:20:35 PM PDT 24
Finished Jun 06 02:25:44 PM PDT 24
Peak memory 197748 kb
Host smart-1449cbb2-8284-4711-b6e8-39980ba3bce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495458090 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2495458090
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3236160779
Short name T178
Test name
Test status
Simulation time 283753086823 ps
CPU time 280.63 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:25:39 PM PDT 24
Peak memory 183032 kb
Host smart-eef5158d-a967-4fb9-842c-797913225504
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236160779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3236160779
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3477174124
Short name T441
Test name
Test status
Simulation time 32543381349 ps
CPU time 52.31 seconds
Started Jun 06 02:20:57 PM PDT 24
Finished Jun 06 02:21:50 PM PDT 24
Peak memory 183020 kb
Host smart-1d218374-0ee9-43c1-96b3-7de7cc7d3d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477174124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3477174124
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2020275787
Short name T314
Test name
Test status
Simulation time 71054494255 ps
CPU time 110.34 seconds
Started Jun 06 02:20:35 PM PDT 24
Finished Jun 06 02:22:26 PM PDT 24
Peak memory 191208 kb
Host smart-497190f5-f04f-4c35-bfbb-4e3a4e9e254c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020275787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2020275787
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4209537344
Short name T428
Test name
Test status
Simulation time 293578181904 ps
CPU time 185.9 seconds
Started Jun 06 02:20:51 PM PDT 24
Finished Jun 06 02:23:58 PM PDT 24
Peak memory 191188 kb
Host smart-e0d5919e-c374-4441-9d6a-acb6f3d15ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209537344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4209537344
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2165724618
Short name T39
Test name
Test status
Simulation time 38475997078 ps
CPU time 119.33 seconds
Started Jun 06 02:20:40 PM PDT 24
Finished Jun 06 02:22:40 PM PDT 24
Peak memory 197652 kb
Host smart-e3530a22-ccd2-4f1e-86e6-b4a038e00eb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165724618 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2165724618
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.203485740
Short name T408
Test name
Test status
Simulation time 322137512232 ps
CPU time 136.75 seconds
Started Jun 06 02:20:38 PM PDT 24
Finished Jun 06 02:22:56 PM PDT 24
Peak memory 183032 kb
Host smart-8fb14b7e-17f9-40ca-a94b-33ab1bba8738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203485740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.203485740
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1351882428
Short name T351
Test name
Test status
Simulation time 51834893401 ps
CPU time 80.29 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:22:13 PM PDT 24
Peak memory 191248 kb
Host smart-377f9539-1f7b-4937-8093-3e0ef3ee73d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351882428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1351882428
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.264906015
Short name T294
Test name
Test status
Simulation time 316103164893 ps
CPU time 526.79 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:29:40 PM PDT 24
Peak memory 191184 kb
Host smart-d36cd853-1840-4513-bd17-8ea2d4b77852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264906015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.264906015
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1263251123
Short name T264
Test name
Test status
Simulation time 213554114841 ps
CPU time 348.74 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:26:45 PM PDT 24
Peak memory 183092 kb
Host smart-6a8854a7-d3d7-47db-9d53-59b116e0f6bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263251123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1263251123
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1828226866
Short name T89
Test name
Test status
Simulation time 232838631163 ps
CPU time 197 seconds
Started Jun 06 02:20:51 PM PDT 24
Finished Jun 06 02:24:09 PM PDT 24
Peak memory 183068 kb
Host smart-e1538c80-00d6-4cb9-a49a-5481acf57ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828226866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1828226866
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3264297767
Short name T200
Test name
Test status
Simulation time 82904491427 ps
CPU time 281.85 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:25:42 PM PDT 24
Peak memory 191248 kb
Host smart-91eed73b-ee9c-428a-ae48-a3839c95be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264297767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3264297767
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4194714922
Short name T379
Test name
Test status
Simulation time 16476741 ps
CPU time 0.56 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:20:51 PM PDT 24
Peak memory 182840 kb
Host smart-7befe15f-b61f-4d35-8ff1-64308e072398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194714922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4194714922
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2034207234
Short name T442
Test name
Test status
Simulation time 229523713816 ps
CPU time 419.98 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:27:55 PM PDT 24
Peak memory 183028 kb
Host smart-0e72ab00-01ac-436b-88db-d881581cf2c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034207234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2034207234
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1343967903
Short name T60
Test name
Test status
Simulation time 286557278677 ps
CPU time 112.29 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 02:22:31 PM PDT 24
Peak memory 183020 kb
Host smart-220e8582-aade-4752-b3a8-686fcad1bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343967903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1343967903
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3363582298
Short name T88
Test name
Test status
Simulation time 1324933363172 ps
CPU time 413.62 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:28:02 PM PDT 24
Peak memory 191248 kb
Host smart-0e50bd8e-10f1-43c7-b107-f08b1b7921b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363582298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3363582298
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3178234651
Short name T417
Test name
Test status
Simulation time 544966914809 ps
CPU time 185.01 seconds
Started Jun 06 02:20:48 PM PDT 24
Finished Jun 06 02:23:53 PM PDT 24
Peak memory 191220 kb
Host smart-792a4b3b-8299-430f-adae-113e8b9fa22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178234651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3178234651
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2810090363
Short name T265
Test name
Test status
Simulation time 420659173456 ps
CPU time 325.27 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:26:23 PM PDT 24
Peak memory 195552 kb
Host smart-8665bddb-5366-4493-a6fd-260153468053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810090363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2810090363
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.16409985
Short name T421
Test name
Test status
Simulation time 62453089632 ps
CPU time 80.27 seconds
Started Jun 06 02:20:43 PM PDT 24
Finished Jun 06 02:22:04 PM PDT 24
Peak memory 183068 kb
Host smart-10097cef-ed2e-471f-8f09-68d38686c7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16409985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.16409985
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3870538553
Short name T142
Test name
Test status
Simulation time 599881042036 ps
CPU time 175.91 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:23:53 PM PDT 24
Peak memory 183008 kb
Host smart-3360b40b-bafe-4725-a3a6-2941c1310897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870538553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3870538553
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3877303786
Short name T276
Test name
Test status
Simulation time 81238985965 ps
CPU time 152.66 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:23:36 PM PDT 24
Peak memory 191200 kb
Host smart-8128a06f-a44b-44ae-81ad-8ab4b4b7b2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877303786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3877303786
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2674953079
Short name T239
Test name
Test status
Simulation time 153161116394 ps
CPU time 170.48 seconds
Started Jun 06 02:21:03 PM PDT 24
Finished Jun 06 02:23:54 PM PDT 24
Peak memory 194812 kb
Host smart-61512562-eb17-4d26-927c-bb30288bd5da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674953079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2674953079
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1968566738
Short name T114
Test name
Test status
Simulation time 137794451855 ps
CPU time 54.3 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:21:52 PM PDT 24
Peak memory 183020 kb
Host smart-2667f118-c4aa-4862-874d-6b436ab9118e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968566738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1968566738
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1026736306
Short name T458
Test name
Test status
Simulation time 85144136258 ps
CPU time 35.37 seconds
Started Jun 06 02:20:48 PM PDT 24
Finished Jun 06 02:21:24 PM PDT 24
Peak memory 183252 kb
Host smart-3a685828-edd1-4c1a-8b6d-0de046e0e758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026736306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1026736306
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2774786197
Short name T311
Test name
Test status
Simulation time 30357362534 ps
CPU time 1039.87 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:38:19 PM PDT 24
Peak memory 183008 kb
Host smart-e12359dd-217c-41f0-8502-ea3822fa399a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774786197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2774786197
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2803745924
Short name T437
Test name
Test status
Simulation time 604251492 ps
CPU time 1.4 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:20:53 PM PDT 24
Peak memory 183032 kb
Host smart-398c1c82-1954-4698-9cf9-2c7488d6c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803745924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2803745924
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1665216910
Short name T32
Test name
Test status
Simulation time 214473728212 ps
CPU time 286.93 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:25:46 PM PDT 24
Peak memory 183068 kb
Host smart-383c6126-4a86-4fa2-8358-cf5d59837b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665216910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1665216910
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.795113332
Short name T422
Test name
Test status
Simulation time 62818362891 ps
CPU time 132.04 seconds
Started Jun 06 02:20:42 PM PDT 24
Finished Jun 06 02:22:55 PM PDT 24
Peak memory 197680 kb
Host smart-76054175-126a-44ab-b5bf-07fb9980b745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795113332 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.795113332
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2468023096
Short name T305
Test name
Test status
Simulation time 789279979438 ps
CPU time 192.07 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:23:54 PM PDT 24
Peak memory 183028 kb
Host smart-acd12273-638a-4c51-991b-779ca7fa7de3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468023096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2468023096
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.349315580
Short name T74
Test name
Test status
Simulation time 95646674675 ps
CPU time 164.16 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 02:23:27 PM PDT 24
Peak memory 183048 kb
Host smart-a86547d1-5e9e-4255-a13a-e969462211f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349315580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.349315580
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.195520942
Short name T171
Test name
Test status
Simulation time 561346547008 ps
CPU time 416.15 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 02:27:34 PM PDT 24
Peak memory 191208 kb
Host smart-90aa46e8-5be6-42c6-8d80-6274f3644002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195520942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.195520942
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.685250903
Short name T84
Test name
Test status
Simulation time 29913292 ps
CPU time 0.57 seconds
Started Jun 06 02:20:49 PM PDT 24
Finished Jun 06 02:20:50 PM PDT 24
Peak memory 182832 kb
Host smart-987a46f4-76ea-4660-aaec-d550859e34d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685250903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.685250903
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2554775334
Short name T452
Test name
Test status
Simulation time 248057595746 ps
CPU time 360.41 seconds
Started Jun 06 02:21:05 PM PDT 24
Finished Jun 06 02:27:07 PM PDT 24
Peak memory 191268 kb
Host smart-39bff3ac-bb5c-4bed-ae5e-67bdb17dda79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554775334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2554775334
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.306206841
Short name T8
Test name
Test status
Simulation time 137936214587 ps
CPU time 252.21 seconds
Started Jun 06 02:20:47 PM PDT 24
Finished Jun 06 02:25:00 PM PDT 24
Peak memory 183028 kb
Host smart-8c6aa10e-9d3b-40c0-8702-5f1848a4cccd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306206841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.306206841
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3043178013
Short name T363
Test name
Test status
Simulation time 14374003765 ps
CPU time 20.57 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:21:07 PM PDT 24
Peak memory 183076 kb
Host smart-4ff545be-99f4-477b-8184-0469f0dea6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043178013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3043178013
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.524599961
Short name T80
Test name
Test status
Simulation time 51422988964 ps
CPU time 95.16 seconds
Started Jun 06 02:20:46 PM PDT 24
Finished Jun 06 02:22:22 PM PDT 24
Peak memory 191208 kb
Host smart-3d4f9428-b6be-4042-a3b6-f1e7c389113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524599961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.524599961
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3328559809
Short name T445
Test name
Test status
Simulation time 123492087753 ps
CPU time 500.34 seconds
Started Jun 06 02:20:55 PM PDT 24
Finished Jun 06 02:29:16 PM PDT 24
Peak memory 191208 kb
Host smart-60b06d81-8f4d-4ef6-9571-284252adc31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328559809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3328559809
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3063946252
Short name T11
Test name
Test status
Simulation time 71506844808 ps
CPU time 145.4 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:23:16 PM PDT 24
Peak memory 205840 kb
Host smart-08e15bdc-b6a7-4009-8ddd-3e82c13f4b99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063946252 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3063946252
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2267822446
Short name T209
Test name
Test status
Simulation time 362591966482 ps
CPU time 678.53 seconds
Started Jun 06 02:20:42 PM PDT 24
Finished Jun 06 02:32:02 PM PDT 24
Peak memory 183068 kb
Host smart-11e10ecf-2c83-4466-a143-7fc799e53a3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267822446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2267822446
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2007424786
Short name T415
Test name
Test status
Simulation time 55679162620 ps
CPU time 83.82 seconds
Started Jun 06 02:20:46 PM PDT 24
Finished Jun 06 02:22:11 PM PDT 24
Peak memory 183008 kb
Host smart-0a2cc023-8034-40f3-8a0b-7ed9051af0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007424786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2007424786
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3703034811
Short name T221
Test name
Test status
Simulation time 46733070006 ps
CPU time 135.73 seconds
Started Jun 06 02:20:39 PM PDT 24
Finished Jun 06 02:23:01 PM PDT 24
Peak memory 191268 kb
Host smart-60ac0ab5-f58f-4387-a30d-f32e4607fe30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703034811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3703034811
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.192858372
Short name T79
Test name
Test status
Simulation time 22272347435 ps
CPU time 27.88 seconds
Started Jun 06 02:20:43 PM PDT 24
Finished Jun 06 02:21:13 PM PDT 24
Peak memory 183004 kb
Host smart-a0ce28c6-a16a-4e93-b599-808cd9a451e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192858372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.192858372
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2655611765
Short name T406
Test name
Test status
Simulation time 26498135920 ps
CPU time 54.73 seconds
Started Jun 06 02:20:49 PM PDT 24
Finished Jun 06 02:21:45 PM PDT 24
Peak memory 197640 kb
Host smart-d0c5dc34-6c0c-4d5a-9251-a1a7b9341003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655611765 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2655611765
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.311665302
Short name T21
Test name
Test status
Simulation time 175811612569 ps
CPU time 325.42 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:26:11 PM PDT 24
Peak memory 183020 kb
Host smart-21dd764a-ebd2-4a67-bb90-145082dabe47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311665302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.311665302
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.263353284
Short name T382
Test name
Test status
Simulation time 68555536427 ps
CPU time 26.92 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:21:26 PM PDT 24
Peak memory 183072 kb
Host smart-40d6e83a-4453-4e6f-bded-d7881bee8ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263353284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.263353284
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1476726826
Short name T198
Test name
Test status
Simulation time 102360211254 ps
CPU time 1230.68 seconds
Started Jun 06 02:20:38 PM PDT 24
Finished Jun 06 02:41:10 PM PDT 24
Peak memory 191192 kb
Host smart-311e6f55-05fe-4e4c-a654-d551590f98eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476726826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1476726826
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3440730355
Short name T453
Test name
Test status
Simulation time 1386013380 ps
CPU time 0.82 seconds
Started Jun 06 02:20:40 PM PDT 24
Finished Jun 06 02:20:42 PM PDT 24
Peak memory 191464 kb
Host smart-013792ac-95ae-4619-8e2e-c148b3301f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440730355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3440730355
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2054796628
Short name T266
Test name
Test status
Simulation time 1655021703347 ps
CPU time 1985.8 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:54:08 PM PDT 24
Peak memory 191296 kb
Host smart-dff46694-3551-4ab4-8625-536eeaabe1e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054796628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2054796628
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3596250245
Short name T403
Test name
Test status
Simulation time 853209962043 ps
CPU time 196.05 seconds
Started Jun 06 02:20:39 PM PDT 24
Finished Jun 06 02:23:56 PM PDT 24
Peak memory 183076 kb
Host smart-68165b5f-37ae-447f-943c-0107e6e49392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596250245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3596250245
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1954413437
Short name T260
Test name
Test status
Simulation time 462892271365 ps
CPU time 188.13 seconds
Started Jun 06 02:20:24 PM PDT 24
Finished Jun 06 02:23:34 PM PDT 24
Peak memory 191200 kb
Host smart-b9ec80f5-6df2-46db-8d86-2a2d7d833503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954413437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1954413437
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.852832590
Short name T323
Test name
Test status
Simulation time 9082652769 ps
CPU time 15.21 seconds
Started Jun 06 02:20:21 PM PDT 24
Finished Jun 06 02:20:38 PM PDT 24
Peak memory 183084 kb
Host smart-952322e8-7b31-482d-a0dc-7be0a9ab7cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852832590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.852832590
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2432989684
Short name T14
Test name
Test status
Simulation time 121723345 ps
CPU time 0.81 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:20:52 PM PDT 24
Peak memory 214104 kb
Host smart-9006d350-f2bd-4a53-9311-90fd329d6a7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432989684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2432989684
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1259838721
Short name T312
Test name
Test status
Simulation time 854855447699 ps
CPU time 877.79 seconds
Started Jun 06 02:20:39 PM PDT 24
Finished Jun 06 02:35:17 PM PDT 24
Peak memory 191248 kb
Host smart-7c02fc22-76ee-4e86-a27d-ef77d5c54eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259838721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1259838721
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.728549924
Short name T358
Test name
Test status
Simulation time 65146481541 ps
CPU time 39.42 seconds
Started Jun 06 02:20:55 PM PDT 24
Finished Jun 06 02:21:36 PM PDT 24
Peak memory 183004 kb
Host smart-5c7bb9d6-967a-4d22-b8e0-9aa0540f787c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728549924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.728549924
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.972246203
Short name T448
Test name
Test status
Simulation time 132851801796 ps
CPU time 193.3 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:23:58 PM PDT 24
Peak memory 183056 kb
Host smart-c0e4b6e9-14d7-41ad-a910-a28625100841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972246203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.972246203
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3198922627
Short name T145
Test name
Test status
Simulation time 386187599950 ps
CPU time 179.85 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:23:54 PM PDT 24
Peak memory 191304 kb
Host smart-b05f24da-11d4-4d05-b736-18cc0f5daa04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198922627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3198922627
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3747252741
Short name T384
Test name
Test status
Simulation time 821072239 ps
CPU time 1.84 seconds
Started Jun 06 02:20:51 PM PDT 24
Finished Jun 06 02:20:54 PM PDT 24
Peak memory 182828 kb
Host smart-499e5c59-41f6-4bb8-a157-830a22d4c162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747252741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3747252741
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2254717912
Short name T420
Test name
Test status
Simulation time 31857952736 ps
CPU time 160.49 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:23:38 PM PDT 24
Peak memory 197656 kb
Host smart-af94c58e-d0b4-4f7e-af8f-c94805ebf81d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254717912 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2254717912
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3013108723
Short name T173
Test name
Test status
Simulation time 755542505716 ps
CPU time 541.56 seconds
Started Jun 06 02:21:00 PM PDT 24
Finished Jun 06 02:30:03 PM PDT 24
Peak memory 182976 kb
Host smart-5ca20138-cd62-44e8-9373-f99a6af3d8d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013108723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3013108723
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3874140248
Short name T62
Test name
Test status
Simulation time 291386767987 ps
CPU time 103.69 seconds
Started Jun 06 02:20:49 PM PDT 24
Finished Jun 06 02:22:34 PM PDT 24
Peak memory 183060 kb
Host smart-dec415ae-97b8-4e70-b798-1671556d72c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874140248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3874140248
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1313789668
Short name T412
Test name
Test status
Simulation time 7075574837 ps
CPU time 14.42 seconds
Started Jun 06 02:20:46 PM PDT 24
Finished Jun 06 02:21:01 PM PDT 24
Peak memory 183048 kb
Host smart-c86f39a5-8e7d-48bc-ac4b-6094b7b9a031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313789668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1313789668
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2368591069
Short name T430
Test name
Test status
Simulation time 718588303 ps
CPU time 0.91 seconds
Started Jun 06 02:20:48 PM PDT 24
Finished Jun 06 02:20:49 PM PDT 24
Peak memory 182772 kb
Host smart-b978153f-2c40-4f92-9704-21e227b40d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368591069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2368591069
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3211547754
Short name T455
Test name
Test status
Simulation time 2119224871458 ps
CPU time 1213.6 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 183004 kb
Host smart-f3552b2c-66f0-4074-816b-c1574d3131ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211547754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3211547754
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.4263744192
Short name T376
Test name
Test status
Simulation time 75993326104 ps
CPU time 94.03 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:22:27 PM PDT 24
Peak memory 183080 kb
Host smart-11306844-6166-4d81-b347-aa7f4c444dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263744192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4263744192
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3841365564
Short name T24
Test name
Test status
Simulation time 57473859345 ps
CPU time 100.2 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:22:26 PM PDT 24
Peak memory 191456 kb
Host smart-0250bb05-3ebe-4ef3-bb1a-88362510e686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841365564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3841365564
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1891070435
Short name T156
Test name
Test status
Simulation time 32273385793 ps
CPU time 383.91 seconds
Started Jun 06 02:21:05 PM PDT 24
Finished Jun 06 02:27:30 PM PDT 24
Peak memory 183024 kb
Host smart-f9239ba2-80b7-4f71-ade0-6d1672dc28eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891070435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1891070435
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2279303508
Short name T401
Test name
Test status
Simulation time 181532025180 ps
CPU time 170.06 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:23:45 PM PDT 24
Peak memory 183080 kb
Host smart-e670cb52-ef48-4925-bf08-1ae6bf0d40a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279303508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2279303508
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3668230763
Short name T369
Test name
Test status
Simulation time 229931275108 ps
CPU time 195.3 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:24:12 PM PDT 24
Peak memory 183072 kb
Host smart-4a2fbe65-c910-4232-8217-190ce8634859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668230763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3668230763
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.825172242
Short name T348
Test name
Test status
Simulation time 142465960723 ps
CPU time 100.39 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:22:42 PM PDT 24
Peak memory 191256 kb
Host smart-348b2708-89c9-483c-840d-9f6f0933ad70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825172242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.825172242
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2295833145
Short name T210
Test name
Test status
Simulation time 81985571173 ps
CPU time 430.39 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:27:57 PM PDT 24
Peak memory 191276 kb
Host smart-e0354369-bc17-4c31-b792-c839f2be1140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295833145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2295833145
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1544409110
Short name T395
Test name
Test status
Simulation time 149377981149 ps
CPU time 229.21 seconds
Started Jun 06 02:21:05 PM PDT 24
Finished Jun 06 02:24:55 PM PDT 24
Peak memory 183036 kb
Host smart-eb162e05-988d-47ab-bc7b-3fd6679c23e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544409110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1544409110
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2427689372
Short name T262
Test name
Test status
Simulation time 369660030841 ps
CPU time 610.89 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:31:21 PM PDT 24
Peak memory 183048 kb
Host smart-516e91ea-b369-4901-977e-4bfd3d205a5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427689372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2427689372
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3261644630
Short name T75
Test name
Test status
Simulation time 18716004236 ps
CPU time 19.07 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:21:04 PM PDT 24
Peak memory 182976 kb
Host smart-2cd31fcf-7051-417e-b416-bbd95a3070d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261644630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3261644630
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.233225719
Short name T416
Test name
Test status
Simulation time 189890474258 ps
CPU time 102.39 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:22:46 PM PDT 24
Peak memory 183004 kb
Host smart-e04687b7-a275-4a85-8c3f-4597bf0e29ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233225719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.233225719
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1424968543
Short name T135
Test name
Test status
Simulation time 17955749791 ps
CPU time 232.05 seconds
Started Jun 06 02:21:03 PM PDT 24
Finished Jun 06 02:24:57 PM PDT 24
Peak memory 183052 kb
Host smart-083b1270-8ed1-48c9-8782-b09de682fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424968543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1424968543
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.658067538
Short name T196
Test name
Test status
Simulation time 67854507469 ps
CPU time 38.66 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:21:41 PM PDT 24
Peak memory 183016 kb
Host smart-076924d5-dcb3-4ddf-ae0c-005f847289ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658067538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.658067538
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random.2166863270
Short name T231
Test name
Test status
Simulation time 450550586216 ps
CPU time 447.6 seconds
Started Jun 06 02:20:55 PM PDT 24
Finished Jun 06 02:28:23 PM PDT 24
Peak memory 191236 kb
Host smart-8e147bb1-86f7-4ce9-a5fe-04dd982b4617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166863270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2166863270
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3627286837
Short name T7
Test name
Test status
Simulation time 87139474519 ps
CPU time 384.06 seconds
Started Jun 06 02:20:59 PM PDT 24
Finished Jun 06 02:27:24 PM PDT 24
Peak memory 183024 kb
Host smart-05e61134-f657-4330-862b-2f8bed054c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627286837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3627286837
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.221502476
Short name T291
Test name
Test status
Simulation time 10216549033 ps
CPU time 9.48 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:21:08 PM PDT 24
Peak memory 182936 kb
Host smart-a79d9815-c724-4e93-b4a3-f3b4d48202c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221502476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.221502476
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1748354012
Short name T380
Test name
Test status
Simulation time 111925685796 ps
CPU time 160.62 seconds
Started Jun 06 02:20:59 PM PDT 24
Finished Jun 06 02:23:40 PM PDT 24
Peak memory 183088 kb
Host smart-647fcdf0-3ec9-48df-9f10-30565d93d1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748354012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1748354012
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2795699147
Short name T286
Test name
Test status
Simulation time 332103442526 ps
CPU time 207 seconds
Started Jun 06 02:20:55 PM PDT 24
Finished Jun 06 02:24:23 PM PDT 24
Peak memory 192228 kb
Host smart-044dfcb5-ea41-4a4e-9549-b85a459e6226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795699147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2795699147
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3991398833
Short name T147
Test name
Test status
Simulation time 40216694277 ps
CPU time 1417.23 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:44:32 PM PDT 24
Peak memory 183060 kb
Host smart-c26f685f-ba95-4e7e-b5fb-b7389a6d84e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991398833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3991398833
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2975385099
Short name T33
Test name
Test status
Simulation time 111086765824 ps
CPU time 133.1 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:22:59 PM PDT 24
Peak memory 205924 kb
Host smart-305abc9d-50db-45c5-b954-bc3c34f04110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975385099 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2975385099
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.956865204
Short name T159
Test name
Test status
Simulation time 2281028445109 ps
CPU time 1131.36 seconds
Started Jun 06 02:20:55 PM PDT 24
Finished Jun 06 02:39:47 PM PDT 24
Peak memory 183008 kb
Host smart-b532f715-f34f-44b1-b8ea-9e50c4ed31c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956865204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.956865204
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.638857266
Short name T82
Test name
Test status
Simulation time 230330480326 ps
CPU time 88.2 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:22:21 PM PDT 24
Peak memory 183024 kb
Host smart-1ec037ca-e495-4449-a9ee-c088b8c85781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638857266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.638857266
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2958121986
Short name T83
Test name
Test status
Simulation time 12998749067 ps
CPU time 26.53 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:21:33 PM PDT 24
Peak memory 183012 kb
Host smart-829376d4-b404-41dc-bb0d-42bd62aa2b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958121986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2958121986
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.542496890
Short name T389
Test name
Test status
Simulation time 318954651 ps
CPU time 0.96 seconds
Started Jun 06 02:21:00 PM PDT 24
Finished Jun 06 02:21:02 PM PDT 24
Peak memory 182988 kb
Host smart-36abad9b-0745-490c-b6b1-be37581e7cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542496890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.542496890
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.611998081
Short name T235
Test name
Test status
Simulation time 82249584994 ps
CPU time 723.92 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:33:11 PM PDT 24
Peak memory 195668 kb
Host smart-15a859cd-1f66-4979-ad0a-29904f6b25cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611998081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
611998081
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.165363340
Short name T345
Test name
Test status
Simulation time 519430847938 ps
CPU time 289.25 seconds
Started Jun 06 02:21:03 PM PDT 24
Finished Jun 06 02:25:53 PM PDT 24
Peak memory 183048 kb
Host smart-fb8ca9d1-fc9f-4b90-a4a4-38b8ae74bbe7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165363340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.165363340
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.439087212
Short name T397
Test name
Test status
Simulation time 146257731563 ps
CPU time 224.71 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:24:53 PM PDT 24
Peak memory 183032 kb
Host smart-56d4262f-45bf-4f8e-80c2-e118f5200635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439087212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.439087212
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3096362060
Short name T179
Test name
Test status
Simulation time 157068633162 ps
CPU time 247.05 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:24:53 PM PDT 24
Peak memory 191208 kb
Host smart-20f0f58b-f983-4f68-abe1-c67c7e458949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096362060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3096362060
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3585677624
Short name T81
Test name
Test status
Simulation time 375313846035 ps
CPU time 161.82 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:23:51 PM PDT 24
Peak memory 183040 kb
Host smart-d609fcd8-50b1-4ebf-9f5f-61635eb49a4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585677624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3585677624
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3803346214
Short name T404
Test name
Test status
Simulation time 748316866280 ps
CPU time 221.83 seconds
Started Jun 06 02:20:57 PM PDT 24
Finished Jun 06 02:24:40 PM PDT 24
Peak memory 183024 kb
Host smart-be92376d-7578-417b-845a-287b534f8df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803346214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3803346214
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1883877013
Short name T253
Test name
Test status
Simulation time 667175774640 ps
CPU time 530.56 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:29:54 PM PDT 24
Peak memory 191296 kb
Host smart-5b87f8d3-730a-46af-b09e-464acfeb539a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883877013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1883877013
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3705011410
Short name T230
Test name
Test status
Simulation time 154841549568 ps
CPU time 264.23 seconds
Started Jun 06 02:21:03 PM PDT 24
Finished Jun 06 02:25:28 PM PDT 24
Peak memory 183048 kb
Host smart-d7535534-ca5b-4ee6-8ba0-6a302abe3228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705011410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3705011410
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3019138369
Short name T270
Test name
Test status
Simulation time 215529907901 ps
CPU time 341.16 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:26:05 PM PDT 24
Peak memory 183084 kb
Host smart-10d18de6-7867-473b-8fda-3459e3a77d25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019138369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3019138369
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.590939817
Short name T366
Test name
Test status
Simulation time 124065764856 ps
CPU time 198.79 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 02:23:57 PM PDT 24
Peak memory 183068 kb
Host smart-eb04145f-872d-4539-9195-f152bb3b5ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590939817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.590939817
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2307070669
Short name T254
Test name
Test status
Simulation time 171188899356 ps
CPU time 280.99 seconds
Started Jun 06 02:20:37 PM PDT 24
Finished Jun 06 02:25:19 PM PDT 24
Peak memory 191268 kb
Host smart-f733b69a-ffd2-49e4-bfb2-afcf03d08377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307070669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2307070669
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.580630651
Short name T233
Test name
Test status
Simulation time 409541054695 ps
CPU time 1328.06 seconds
Started Jun 06 02:20:22 PM PDT 24
Finished Jun 06 02:42:32 PM PDT 24
Peak memory 183056 kb
Host smart-537f6a60-90f0-4882-8489-341464f96e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580630651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.580630651
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2628275166
Short name T17
Test name
Test status
Simulation time 66648074 ps
CPU time 0.73 seconds
Started Jun 06 02:20:34 PM PDT 24
Finished Jun 06 02:20:35 PM PDT 24
Peak memory 214040 kb
Host smart-f9490188-6e42-4c98-b948-42cecddaa36a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628275166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2628275166
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2245312906
Short name T370
Test name
Test status
Simulation time 182949844250 ps
CPU time 250.53 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:25:21 PM PDT 24
Peak memory 183048 kb
Host smart-09a0e23a-0814-4c3a-859d-be91e5fd7987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245312906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2245312906
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.4161679949
Short name T26
Test name
Test status
Simulation time 30272661157 ps
CPU time 826.36 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:34:46 PM PDT 24
Peak memory 191220 kb
Host smart-a36c01db-5b97-420f-a9b4-37b0e820a4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161679949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.4161679949
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3848442104
Short name T409
Test name
Test status
Simulation time 171472510651 ps
CPU time 401.27 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:27:52 PM PDT 24
Peak memory 191260 kb
Host smart-bcf9be65-4323-4603-a891-dfd596f6a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848442104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3848442104
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.4270705871
Short name T218
Test name
Test status
Simulation time 144966537798 ps
CPU time 916.44 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:36:20 PM PDT 24
Peak memory 194764 kb
Host smart-b9c8d40a-a78a-4863-86c2-2b7452b9e9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270705871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.4270705871
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1509968781
Short name T77
Test name
Test status
Simulation time 396270728838 ps
CPU time 225.68 seconds
Started Jun 06 02:20:59 PM PDT 24
Finished Jun 06 02:24:46 PM PDT 24
Peak memory 183080 kb
Host smart-cbf8df56-dec3-4057-828a-c71979c63eda
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509968781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1509968781
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3672573445
Short name T374
Test name
Test status
Simulation time 483666621408 ps
CPU time 186.69 seconds
Started Jun 06 02:21:14 PM PDT 24
Finished Jun 06 02:24:22 PM PDT 24
Peak memory 183064 kb
Host smart-8e1a59fe-8e19-4763-8ab7-855078212ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672573445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3672573445
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4207282283
Short name T42
Test name
Test status
Simulation time 91216478874 ps
CPU time 196.49 seconds
Started Jun 06 02:20:57 PM PDT 24
Finished Jun 06 02:24:14 PM PDT 24
Peak memory 183040 kb
Host smart-047d5713-aba3-4306-ade1-15779c31b8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207282283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4207282283
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1805086075
Short name T398
Test name
Test status
Simulation time 57439025336 ps
CPU time 105.85 seconds
Started Jun 06 02:20:59 PM PDT 24
Finished Jun 06 02:22:46 PM PDT 24
Peak memory 183076 kb
Host smart-4bc2af76-1099-42f2-803f-dc701d4bc557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805086075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1805086075
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1028744583
Short name T182
Test name
Test status
Simulation time 4797342481591 ps
CPU time 2414.21 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 03:01:17 PM PDT 24
Peak memory 195696 kb
Host smart-e23b321f-118c-45ec-a722-7cff544a584b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028744583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1028744583
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.980822149
Short name T431
Test name
Test status
Simulation time 90161261616 ps
CPU time 54.64 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:22:04 PM PDT 24
Peak memory 183036 kb
Host smart-a73d509f-2523-4732-9756-4a654941c63c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980822149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.980822149
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1111929778
Short name T456
Test name
Test status
Simulation time 144790747932 ps
CPU time 101.22 seconds
Started Jun 06 02:21:04 PM PDT 24
Finished Jun 06 02:22:46 PM PDT 24
Peak memory 183040 kb
Host smart-480a5685-f52e-48a1-95d7-419c4fb22d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111929778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1111929778
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2956447008
Short name T146
Test name
Test status
Simulation time 918766379030 ps
CPU time 292.7 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:26:03 PM PDT 24
Peak memory 191228 kb
Host smart-fd518616-4dd0-4f26-a706-89e5ec009804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956447008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2956447008
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.453472734
Short name T381
Test name
Test status
Simulation time 672415451 ps
CPU time 1.27 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:21:04 PM PDT 24
Peak memory 191204 kb
Host smart-a227638d-c6c4-495c-9451-65f0e4b1747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453472734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.453472734
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2756556018
Short name T187
Test name
Test status
Simulation time 331374527613 ps
CPU time 547.46 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:30:03 PM PDT 24
Peak memory 191260 kb
Host smart-e29a35a9-2b00-48ac-b7f9-199bf9a96a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756556018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2756556018
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2136375933
Short name T237
Test name
Test status
Simulation time 107841058149 ps
CPU time 167.72 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:23:51 PM PDT 24
Peak memory 183044 kb
Host smart-1f8e96c3-2f92-4e4e-a06f-549c3fc113ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136375933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2136375933
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.641854128
Short name T371
Test name
Test status
Simulation time 227785231686 ps
CPU time 77.56 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:22:28 PM PDT 24
Peak memory 183048 kb
Host smart-ff2b167b-0107-46ef-aad9-32181b0f3ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641854128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.641854128
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3322743564
Short name T451
Test name
Test status
Simulation time 158787262794 ps
CPU time 30.34 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:21:32 PM PDT 24
Peak memory 191212 kb
Host smart-23fe9c38-912e-4ccb-9921-a00b3c4c7b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322743564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3322743564
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.4208748856
Short name T133
Test name
Test status
Simulation time 283874767460 ps
CPU time 158.84 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:23:34 PM PDT 24
Peak memory 183016 kb
Host smart-14b4c35a-06b2-4c55-9dee-52c77e758733
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208748856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.4208748856
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3748503294
Short name T414
Test name
Test status
Simulation time 152855977244 ps
CPU time 240.97 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 183040 kb
Host smart-66c558a4-c1f6-43d0-a047-3cc50ffca9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748503294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3748503294
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2282513834
Short name T153
Test name
Test status
Simulation time 326398373133 ps
CPU time 214.17 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:24:37 PM PDT 24
Peak memory 191272 kb
Host smart-ed336908-e4be-43ca-a8bb-091580cbcb66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282513834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2282513834
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3611007036
Short name T373
Test name
Test status
Simulation time 95757557 ps
CPU time 0.6 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:20:54 PM PDT 24
Peak memory 183056 kb
Host smart-9a415826-8e6e-471f-a9d2-f27ad2a53a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611007036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3611007036
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1630772665
Short name T206
Test name
Test status
Simulation time 1962866451069 ps
CPU time 1094.47 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:39:25 PM PDT 24
Peak memory 191208 kb
Host smart-041d83da-754e-4fce-b19f-cb0f57b64347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630772665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1630772665
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.263037362
Short name T336
Test name
Test status
Simulation time 132166741347 ps
CPU time 211.81 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:24:27 PM PDT 24
Peak memory 183012 kb
Host smart-db01c590-dbcd-4e35-af9b-edefb86dcab8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263037362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.263037362
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2531753836
Short name T367
Test name
Test status
Simulation time 383821476571 ps
CPU time 77.91 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:22:25 PM PDT 24
Peak memory 183012 kb
Host smart-641c7c43-cffa-48fc-a9db-a2690ae0eb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531753836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2531753836
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.260171405
Short name T399
Test name
Test status
Simulation time 165320727518 ps
CPU time 56.21 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:21:59 PM PDT 24
Peak memory 183016 kb
Host smart-3a5c9167-07d2-4c03-bbab-1ab5dc0b1df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260171405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.260171405
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2875506743
Short name T215
Test name
Test status
Simulation time 87978491272 ps
CPU time 152.8 seconds
Started Jun 06 02:21:18 PM PDT 24
Finished Jun 06 02:23:52 PM PDT 24
Peak memory 195916 kb
Host smart-68990eaf-9358-4bf5-996f-67caa7f876ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875506743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2875506743
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3724155409
Short name T405
Test name
Test status
Simulation time 9416612631 ps
CPU time 17.71 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:21:15 PM PDT 24
Peak memory 183096 kb
Host smart-3f0f531b-8d84-430a-8dfc-2ff549cbfebd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724155409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3724155409
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.818369916
Short name T383
Test name
Test status
Simulation time 36760690704 ps
CPU time 7.09 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:21:17 PM PDT 24
Peak memory 183044 kb
Host smart-592aeb34-fb9f-462a-9cac-1f26d37e4f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818369916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.818369916
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3125213829
Short name T132
Test name
Test status
Simulation time 76616250390 ps
CPU time 68.6 seconds
Started Jun 06 02:20:57 PM PDT 24
Finished Jun 06 02:22:06 PM PDT 24
Peak memory 183064 kb
Host smart-226653c6-e0d6-43d9-a424-028d76ecfa3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125213829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3125213829
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1379033681
Short name T232
Test name
Test status
Simulation time 47565096133 ps
CPU time 82.2 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:22:21 PM PDT 24
Peak memory 182932 kb
Host smart-bbe2f0ef-a15a-40ad-aa6f-bb82982cceed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379033681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1379033681
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4190734454
Short name T136
Test name
Test status
Simulation time 1199726121308 ps
CPU time 1436.39 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:45:04 PM PDT 24
Peak memory 191196 kb
Host smart-30044655-2b9b-4944-95c5-025d88ca13c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190734454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4190734454
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3776309379
Short name T440
Test name
Test status
Simulation time 240994909229 ps
CPU time 438.73 seconds
Started Jun 06 02:21:03 PM PDT 24
Finished Jun 06 02:28:23 PM PDT 24
Peak memory 183032 kb
Host smart-14c585e2-b182-43c2-bfdd-d81929050226
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776309379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3776309379
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2922429451
Short name T372
Test name
Test status
Simulation time 199658220466 ps
CPU time 162.62 seconds
Started Jun 06 02:21:04 PM PDT 24
Finished Jun 06 02:23:48 PM PDT 24
Peak memory 183024 kb
Host smart-e743b151-27b6-4686-a1b6-44fd6392810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922429451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2922429451
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3564418526
Short name T185
Test name
Test status
Simulation time 78762198270 ps
CPU time 138.64 seconds
Started Jun 06 02:21:12 PM PDT 24
Finished Jun 06 02:23:32 PM PDT 24
Peak memory 191216 kb
Host smart-78159f76-3f7f-47d1-80ae-405772391108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564418526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3564418526
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2878815869
Short name T390
Test name
Test status
Simulation time 351792182 ps
CPU time 0.65 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:20:59 PM PDT 24
Peak memory 183052 kb
Host smart-172fdf87-504e-499d-9a95-cce68a16d3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878815869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2878815869
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3492831241
Short name T44
Test name
Test status
Simulation time 936647923041 ps
CPU time 398.55 seconds
Started Jun 06 02:21:17 PM PDT 24
Finished Jun 06 02:27:57 PM PDT 24
Peak memory 191276 kb
Host smart-c66d2ff5-afeb-4cad-ae82-6d3e9f508ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492831241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3492831241
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.4060482971
Short name T38
Test name
Test status
Simulation time 155344557207 ps
CPU time 540.43 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:30:07 PM PDT 24
Peak memory 205896 kb
Host smart-05a49e4d-237d-4f6f-8ec8-cc75f49884a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060482971 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.4060482971
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2565747865
Short name T443
Test name
Test status
Simulation time 169809909402 ps
CPU time 268.94 seconds
Started Jun 06 02:21:17 PM PDT 24
Finished Jun 06 02:25:47 PM PDT 24
Peak memory 183040 kb
Host smart-f5cd1e47-6712-40b5-a107-7f5bddd6b4ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565747865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2565747865
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1303807981
Short name T19
Test name
Test status
Simulation time 535023893436 ps
CPU time 131.9 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:23:20 PM PDT 24
Peak memory 183052 kb
Host smart-b2d2527a-20e6-41c4-8597-88eeda03ad79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303807981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1303807981
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2516570348
Short name T296
Test name
Test status
Simulation time 102098760783 ps
CPU time 309.97 seconds
Started Jun 06 02:21:04 PM PDT 24
Finished Jun 06 02:26:15 PM PDT 24
Peak memory 191228 kb
Host smart-7b087307-c1bd-4602-a16c-aacdeb82030e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516570348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2516570348
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.4059760599
Short name T180
Test name
Test status
Simulation time 26058005011 ps
CPU time 654.71 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:32:05 PM PDT 24
Peak memory 183032 kb
Host smart-857a8dbb-efbf-420f-ac7c-3bf90403a3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059760599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4059760599
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.704138614
Short name T117
Test name
Test status
Simulation time 130926330920 ps
CPU time 300.9 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:25:55 PM PDT 24
Peak memory 208152 kb
Host smart-27717213-ecea-4799-abb4-9df58127eec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704138614 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.704138614
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2963974214
Short name T242
Test name
Test status
Simulation time 475951648784 ps
CPU time 442.25 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:28:33 PM PDT 24
Peak memory 183068 kb
Host smart-e6f6d476-bf81-453d-88d1-c3a9c69db1a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963974214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2963974214
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2256210432
Short name T439
Test name
Test status
Simulation time 114292921289 ps
CPU time 77.59 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:22:27 PM PDT 24
Peak memory 183088 kb
Host smart-83daaa22-da92-495f-8938-0c5956edb39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256210432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2256210432
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1999683698
Short name T57
Test name
Test status
Simulation time 628649985522 ps
CPU time 238.95 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:25:08 PM PDT 24
Peak memory 191268 kb
Host smart-8f9d4f60-c24f-4b8b-b6de-bb1d8a703df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999683698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1999683698
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1560961888
Short name T400
Test name
Test status
Simulation time 4994547402 ps
CPU time 10.13 seconds
Started Jun 06 02:21:20 PM PDT 24
Finished Jun 06 02:21:32 PM PDT 24
Peak memory 191228 kb
Host smart-657e387f-bed2-4fce-9f65-fa57af70b439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560961888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1560961888
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.828486839
Short name T76
Test name
Test status
Simulation time 339226737949 ps
CPU time 280.74 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:25:50 PM PDT 24
Peak memory 194624 kb
Host smart-be595218-e259-4fd3-9785-0866cc7b6365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828486839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
828486839
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3810520685
Short name T318
Test name
Test status
Simulation time 914657183359 ps
CPU time 359.95 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:26:42 PM PDT 24
Peak memory 182956 kb
Host smart-45658065-be3e-49ed-afd5-e6a27142af1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810520685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3810520685
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3721490769
Short name T393
Test name
Test status
Simulation time 215974841009 ps
CPU time 90.67 seconds
Started Jun 06 02:20:33 PM PDT 24
Finished Jun 06 02:22:05 PM PDT 24
Peak memory 183020 kb
Host smart-9cf22a9e-00ff-4f78-a4ac-19b4907249ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721490769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3721490769
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.556057359
Short name T298
Test name
Test status
Simulation time 118308553012 ps
CPU time 178.19 seconds
Started Jun 06 02:20:36 PM PDT 24
Finished Jun 06 02:23:35 PM PDT 24
Peak memory 191216 kb
Host smart-897ead46-1f49-46fb-97af-d5bdfbb58ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556057359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.556057359
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3732887584
Short name T250
Test name
Test status
Simulation time 41077784453 ps
CPU time 80.7 seconds
Started Jun 06 02:20:43 PM PDT 24
Finished Jun 06 02:22:04 PM PDT 24
Peak memory 183000 kb
Host smart-cbb105a4-3c1d-4a68-afdb-d80565704ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732887584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3732887584
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1612383193
Short name T357
Test name
Test status
Simulation time 42540735941 ps
CPU time 74.83 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:22:29 PM PDT 24
Peak memory 182956 kb
Host smart-ea00c1f4-5a2b-4697-ad4d-3bb6c062c039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612383193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1612383193
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.806697671
Short name T434
Test name
Test status
Simulation time 8361819318 ps
CPU time 12.83 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:21:22 PM PDT 24
Peak memory 182904 kb
Host smart-13fd73c6-498e-4d7e-ad35-3799e23cfb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806697671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.806697671
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2367697469
Short name T257
Test name
Test status
Simulation time 89704044920 ps
CPU time 188.12 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:24:15 PM PDT 24
Peak memory 194652 kb
Host smart-90b92fcd-caf6-4e00-8292-8e2389e86e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367697469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2367697469
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3129602821
Short name T252
Test name
Test status
Simulation time 52437795781 ps
CPU time 84.59 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:22:28 PM PDT 24
Peak memory 194148 kb
Host smart-45141ed1-5f07-4acf-bec5-4024505c59c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129602821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3129602821
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3920797660
Short name T306
Test name
Test status
Simulation time 533265047613 ps
CPU time 640.24 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:31:52 PM PDT 24
Peak memory 191216 kb
Host smart-6a46556b-e3b5-4654-9ae3-b38a6ab3cdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920797660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3920797660
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.352502816
Short name T321
Test name
Test status
Simulation time 12829262979 ps
CPU time 7.07 seconds
Started Jun 06 02:21:22 PM PDT 24
Finished Jun 06 02:21:31 PM PDT 24
Peak memory 183032 kb
Host smart-eada33ca-77c3-4422-8abc-1aa5e021451c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352502816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.352502816
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.4247854855
Short name T168
Test name
Test status
Simulation time 126870309004 ps
CPU time 397.29 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:27:41 PM PDT 24
Peak memory 191228 kb
Host smart-86ad752b-6924-4208-8f86-4969f346b316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247854855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.4247854855
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3706426527
Short name T413
Test name
Test status
Simulation time 38190869347 ps
CPU time 73.56 seconds
Started Jun 06 02:20:58 PM PDT 24
Finished Jun 06 02:22:13 PM PDT 24
Peak memory 191292 kb
Host smart-5e9a1004-ada4-4f98-a04b-4d8f8befb35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706426527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3706426527
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2331649562
Short name T87
Test name
Test status
Simulation time 527260272041 ps
CPU time 419.05 seconds
Started Jun 06 02:20:29 PM PDT 24
Finished Jun 06 02:27:29 PM PDT 24
Peak memory 183016 kb
Host smart-a7a91177-8dde-47d1-b664-d95f9b9e4ff8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331649562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2331649562
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1454577393
Short name T427
Test name
Test status
Simulation time 254681710024 ps
CPU time 122.69 seconds
Started Jun 06 02:20:47 PM PDT 24
Finished Jun 06 02:22:50 PM PDT 24
Peak memory 183028 kb
Host smart-e6a0cba6-0eef-4c44-8f9b-1adfdfbb093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454577393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1454577393
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2754362774
Short name T219
Test name
Test status
Simulation time 167998647367 ps
CPU time 91.18 seconds
Started Jun 06 02:20:27 PM PDT 24
Finished Jun 06 02:21:59 PM PDT 24
Peak memory 191256 kb
Host smart-0a5c330b-d9bf-4f9b-ac11-25a54b6b398b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754362774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2754362774
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3795023917
Short name T45
Test name
Test status
Simulation time 88049904748 ps
CPU time 138.07 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:23:30 PM PDT 24
Peak memory 191232 kb
Host smart-23561152-aae0-4d07-87c0-b3eaf37c1764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795023917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3795023917
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.67694657
Short name T169
Test name
Test status
Simulation time 158617367741 ps
CPU time 1410.39 seconds
Started Jun 06 02:20:56 PM PDT 24
Finished Jun 06 02:44:28 PM PDT 24
Peak memory 193364 kb
Host smart-7563e263-9260-48ea-beb4-7916895e9b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67694657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.67694657
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2363173449
Short name T160
Test name
Test status
Simulation time 139129034834 ps
CPU time 391.92 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:27:44 PM PDT 24
Peak memory 191256 kb
Host smart-947232d2-6038-4502-8063-7c6dd32de8a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363173449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2363173449
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3707160216
Short name T295
Test name
Test status
Simulation time 407640462607 ps
CPU time 280.94 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:25:51 PM PDT 24
Peak memory 191268 kb
Host smart-3947dd7b-752b-4824-ad29-62d8249fa8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707160216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3707160216
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.507312611
Short name T155
Test name
Test status
Simulation time 118281733995 ps
CPU time 228.91 seconds
Started Jun 06 02:21:07 PM PDT 24
Finished Jun 06 02:24:57 PM PDT 24
Peak memory 191224 kb
Host smart-be922cff-13ee-41f9-8808-536825502761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507312611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.507312611
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.4075915048
Short name T227
Test name
Test status
Simulation time 244587255889 ps
CPU time 198.51 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:24:30 PM PDT 24
Peak memory 191260 kb
Host smart-489c1416-11b6-493f-b744-6ae54b454007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075915048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.4075915048
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.458524445
Short name T197
Test name
Test status
Simulation time 909247450404 ps
CPU time 458.8 seconds
Started Jun 06 02:20:26 PM PDT 24
Finished Jun 06 02:28:06 PM PDT 24
Peak memory 183068 kb
Host smart-8eb1a874-ea76-4df0-b736-f7ef3a47fb48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458524445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.458524445
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.998432516
Short name T108
Test name
Test status
Simulation time 183327332164 ps
CPU time 74.97 seconds
Started Jun 06 02:20:29 PM PDT 24
Finished Jun 06 02:21:45 PM PDT 24
Peak memory 183084 kb
Host smart-4091087d-0f30-46a9-add7-e236a39dc8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998432516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.998432516
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.19044913
Short name T385
Test name
Test status
Simulation time 654190650 ps
CPU time 2.13 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:20:44 PM PDT 24
Peak memory 183024 kb
Host smart-ac4bad12-6cbe-4425-bf45-de3605820c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19044913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.19044913
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3209300512
Short name T46
Test name
Test status
Simulation time 174056289523 ps
CPU time 479.96 seconds
Started Jun 06 02:20:39 PM PDT 24
Finished Jun 06 02:28:40 PM PDT 24
Peak memory 192372 kb
Host smart-b15886fd-198c-4ccb-82ed-63f8acc0244e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209300512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3209300512
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2109736253
Short name T85
Test name
Test status
Simulation time 33996346155 ps
CPU time 514.84 seconds
Started Jun 06 02:20:38 PM PDT 24
Finished Jun 06 02:29:14 PM PDT 24
Peak memory 205900 kb
Host smart-f27234cb-c2cc-4657-b1da-46214cf657d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109736253 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2109736253
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1467613678
Short name T280
Test name
Test status
Simulation time 631281740930 ps
CPU time 2223.61 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:58:11 PM PDT 24
Peak memory 191084 kb
Host smart-f1b72319-ce16-40a3-879a-85d34e93828e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467613678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1467613678
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1589155412
Short name T163
Test name
Test status
Simulation time 191986615269 ps
CPU time 1309.33 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:42:52 PM PDT 24
Peak memory 191256 kb
Host smart-591c0b61-c24b-46ee-88c2-38466f5f9708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589155412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1589155412
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1227430146
Short name T128
Test name
Test status
Simulation time 309608384882 ps
CPU time 273.82 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:25:43 PM PDT 24
Peak memory 193280 kb
Host smart-16b628c1-cccc-478c-9d0e-bf2d6791635c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227430146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1227430146
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3031120396
Short name T268
Test name
Test status
Simulation time 350906538945 ps
CPU time 227.78 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:24:58 PM PDT 24
Peak memory 191248 kb
Host smart-f5f5072a-094e-471a-a2d2-8353bed9a9e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031120396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3031120396
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.4184410226
Short name T435
Test name
Test status
Simulation time 86156499384 ps
CPU time 150.65 seconds
Started Jun 06 02:21:13 PM PDT 24
Finished Jun 06 02:23:45 PM PDT 24
Peak memory 191212 kb
Host smart-280696c6-3498-4e99-8f8b-d6845adaa309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184410226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.4184410226
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3002559285
Short name T143
Test name
Test status
Simulation time 427853087464 ps
CPU time 84.95 seconds
Started Jun 06 02:21:05 PM PDT 24
Finished Jun 06 02:22:31 PM PDT 24
Peak memory 183068 kb
Host smart-da4fc237-95ab-4001-96b5-5f8ee5748943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002559285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3002559285
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.4191801249
Short name T140
Test name
Test status
Simulation time 351567889607 ps
CPU time 161.11 seconds
Started Jun 06 02:21:06 PM PDT 24
Finished Jun 06 02:23:53 PM PDT 24
Peak memory 191268 kb
Host smart-e40202a2-29d2-4a52-981e-85ca00ceeea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191801249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4191801249
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2592077784
Short name T339
Test name
Test status
Simulation time 20308988275 ps
CPU time 32.57 seconds
Started Jun 06 02:21:19 PM PDT 24
Finished Jun 06 02:21:53 PM PDT 24
Peak memory 183096 kb
Host smart-a21c2292-9eea-4646-8a81-de6806e6f988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592077784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2592077784
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1038679612
Short name T353
Test name
Test status
Simulation time 69149464504 ps
CPU time 70.9 seconds
Started Jun 06 02:20:44 PM PDT 24
Finished Jun 06 02:21:56 PM PDT 24
Peak memory 183056 kb
Host smart-4aaf92c8-b2f6-44e8-9534-b87b1c3ae84d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038679612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1038679612
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.414782888
Short name T438
Test name
Test status
Simulation time 388453295188 ps
CPU time 174.88 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:23:57 PM PDT 24
Peak memory 183072 kb
Host smart-b3724178-c538-48d9-90de-fd31ab308203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414782888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.414782888
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.4203741015
Short name T247
Test name
Test status
Simulation time 123463644654 ps
CPU time 444.36 seconds
Started Jun 06 02:20:54 PM PDT 24
Finished Jun 06 02:28:20 PM PDT 24
Peak memory 191236 kb
Host smart-10d72ede-04d5-4432-bce6-4605b6835b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203741015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.4203741015
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1148865872
Short name T1
Test name
Test status
Simulation time 187095876 ps
CPU time 0.68 seconds
Started Jun 06 02:20:39 PM PDT 24
Finished Jun 06 02:20:40 PM PDT 24
Peak memory 182880 kb
Host smart-0573c269-437a-4522-9adc-9750be7ba768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148865872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1148865872
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.2774290410
Short name T35
Test name
Test status
Simulation time 47157017668 ps
CPU time 241.41 seconds
Started Jun 06 02:20:45 PM PDT 24
Finished Jun 06 02:24:47 PM PDT 24
Peak memory 197636 kb
Host smart-0c967bc5-100f-48ee-bcad-e835d365348f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774290410 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.2774290410
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.40226674
Short name T113
Test name
Test status
Simulation time 343570267385 ps
CPU time 361.3 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:27:12 PM PDT 24
Peak memory 191220 kb
Host smart-bb9a2cf7-f884-4419-b0a9-49598f196b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.40226674
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3337129913
Short name T450
Test name
Test status
Simulation time 9669203054 ps
CPU time 15.32 seconds
Started Jun 06 02:21:17 PM PDT 24
Finished Jun 06 02:21:33 PM PDT 24
Peak memory 191220 kb
Host smart-6d0e9cf1-25c2-4dad-8c76-83d3c5d04441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337129913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3337129913
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1057774042
Short name T126
Test name
Test status
Simulation time 591439397956 ps
CPU time 197.25 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:24:21 PM PDT 24
Peak memory 191148 kb
Host smart-308c5738-dd65-4165-994b-7d78a2e224b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057774042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1057774042
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.651308588
Short name T131
Test name
Test status
Simulation time 198724006541 ps
CPU time 316.78 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:26:19 PM PDT 24
Peak memory 191260 kb
Host smart-7a87459c-340f-4ac1-9573-e9d58fd53cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651308588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.651308588
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3584383255
Short name T346
Test name
Test status
Simulation time 1052441367970 ps
CPU time 775.13 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:34:05 PM PDT 24
Peak memory 191232 kb
Host smart-6ae595c4-96ae-48b8-a5f3-e46cc383fbb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584383255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3584383255
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1992979268
Short name T144
Test name
Test status
Simulation time 194406491025 ps
CPU time 489.11 seconds
Started Jun 06 02:21:09 PM PDT 24
Finished Jun 06 02:29:20 PM PDT 24
Peak memory 191228 kb
Host smart-03254c1f-835d-4077-b86c-cd6b7dd3cde6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992979268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1992979268
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1153939756
Short name T299
Test name
Test status
Simulation time 285362494775 ps
CPU time 497.27 seconds
Started Jun 06 02:21:16 PM PDT 24
Finished Jun 06 02:29:34 PM PDT 24
Peak memory 191256 kb
Host smart-0d58c515-cc9f-46bb-962e-07b1bb9ff5dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153939756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1153939756
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2011040470
Short name T319
Test name
Test status
Simulation time 137231754687 ps
CPU time 143.21 seconds
Started Jun 06 02:21:05 PM PDT 24
Finished Jun 06 02:23:29 PM PDT 24
Peak memory 191220 kb
Host smart-e6eedc3a-7fe6-4001-bd65-572a4a27491f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011040470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2011040470
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.4058344947
Short name T330
Test name
Test status
Simulation time 232433148462 ps
CPU time 701.22 seconds
Started Jun 06 02:21:02 PM PDT 24
Finished Jun 06 02:32:44 PM PDT 24
Peak memory 193960 kb
Host smart-2ae75f23-8d83-43cd-9b01-670ebe430af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058344947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.4058344947
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.686703927
Short name T139
Test name
Test status
Simulation time 576582181915 ps
CPU time 248.83 seconds
Started Jun 06 02:20:51 PM PDT 24
Finished Jun 06 02:25:01 PM PDT 24
Peak memory 183008 kb
Host smart-f5ed52c9-054c-46f3-8ca5-ff72e904c38a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686703927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.686703927
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.905154757
Short name T407
Test name
Test status
Simulation time 38138782831 ps
CPU time 61.46 seconds
Started Jun 06 02:20:41 PM PDT 24
Finished Jun 06 02:21:43 PM PDT 24
Peak memory 183064 kb
Host smart-6cee6326-7c29-43b5-b0fe-154bb9709f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905154757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.905154757
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.755604875
Short name T203
Test name
Test status
Simulation time 110298524773 ps
CPU time 90.7 seconds
Started Jun 06 02:20:50 PM PDT 24
Finished Jun 06 02:22:22 PM PDT 24
Peak memory 191216 kb
Host smart-c7882fea-8eee-4e15-9510-b7238801aa33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755604875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.755604875
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2279817894
Short name T56
Test name
Test status
Simulation time 88752773498 ps
CPU time 37.16 seconds
Started Jun 06 02:20:52 PM PDT 24
Finished Jun 06 02:21:30 PM PDT 24
Peak memory 191236 kb
Host smart-e7661d52-1789-49ca-8eaa-f9156b04d22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279817894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2279817894
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1603951746
Short name T3
Test name
Test status
Simulation time 130055267086 ps
CPU time 82.48 seconds
Started Jun 06 02:21:04 PM PDT 24
Finished Jun 06 02:22:28 PM PDT 24
Peak memory 191220 kb
Host smart-d6cb1323-6c80-49e5-b694-7ab48121674f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603951746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1603951746
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3215948707
Short name T275
Test name
Test status
Simulation time 69893954864 ps
CPU time 61.78 seconds
Started Jun 06 02:21:18 PM PDT 24
Finished Jun 06 02:22:21 PM PDT 24
Peak memory 183020 kb
Host smart-60f6d146-17e2-412c-9b9e-bab74ac2abca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215948707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3215948707
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3038968042
Short name T342
Test name
Test status
Simulation time 129924656684 ps
CPU time 239.3 seconds
Started Jun 06 02:21:17 PM PDT 24
Finished Jun 06 02:25:17 PM PDT 24
Peak memory 191220 kb
Host smart-d639bd0a-1b48-4e07-8896-1464290f1dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038968042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3038968042
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2766442876
Short name T164
Test name
Test status
Simulation time 139233163791 ps
CPU time 300.39 seconds
Started Jun 06 02:21:10 PM PDT 24
Finished Jun 06 02:26:12 PM PDT 24
Peak memory 191220 kb
Host smart-d0c6c575-c5ae-44e4-b31c-965a8aaac194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766442876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2766442876
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2681351478
Short name T161
Test name
Test status
Simulation time 104143376543 ps
CPU time 168.32 seconds
Started Jun 06 02:21:19 PM PDT 24
Finished Jun 06 02:24:09 PM PDT 24
Peak memory 191228 kb
Host smart-50032b1e-98e5-4020-b757-f5f229764de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681351478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2681351478
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.67202260
Short name T186
Test name
Test status
Simulation time 455897876859 ps
CPU time 470.46 seconds
Started Jun 06 02:21:08 PM PDT 24
Finished Jun 06 02:29:00 PM PDT 24
Peak memory 191216 kb
Host smart-b20da002-255f-48e0-bfd0-2da000200315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67202260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.67202260
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1978117691
Short name T287
Test name
Test status
Simulation time 56273903299 ps
CPU time 110.74 seconds
Started Jun 06 02:20:59 PM PDT 24
Finished Jun 06 02:22:50 PM PDT 24
Peak memory 191212 kb
Host smart-87018d36-42d3-4a42-9db6-8dbd0f5629dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978117691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1978117691
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2418935060
Short name T313
Test name
Test status
Simulation time 191301127227 ps
CPU time 384.53 seconds
Started Jun 06 02:21:01 PM PDT 24
Finished Jun 06 02:27:27 PM PDT 24
Peak memory 191440 kb
Host smart-44403e70-4cff-4fe2-aca8-ec69d33079b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418935060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2418935060
Directory /workspace/99.rv_timer_random/latest
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