Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
124476820 |
1 |
|
T1 |
15773 |
|
T2 |
2173 |
|
T3 |
87232 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
64567768 |
1 |
|
T1 |
5538 |
|
T2 |
118 |
|
T3 |
87232 |
auto[1] |
59909052 |
1 |
|
T1 |
10235 |
|
T2 |
2055 |
|
T4 |
17441 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
124470882 |
1 |
|
T1 |
15769 |
|
T2 |
2169 |
|
T3 |
87227 |
auto[1] |
5938 |
1 |
|
T1 |
4 |
|
T2 |
4 |
|
T3 |
5 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
64564688 |
1 |
|
T1 |
5536 |
|
T2 |
116 |
|
T3 |
87227 |
all_values[0] |
auto[0] |
auto[1] |
3080 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
5 |
all_values[0] |
auto[1] |
auto[0] |
59906194 |
1 |
|
T1 |
10233 |
|
T2 |
2053 |
|
T4 |
17439 |
all_values[0] |
auto[1] |
auto[1] |
2858 |
1 |
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
2 |