Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T510 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1366604123 Jun 07 06:02:39 PM PDT 24 Jun 07 06:02:40 PM PDT 24 29508953 ps
T98 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1044998129 Jun 07 05:59:24 PM PDT 24 Jun 07 05:59:26 PM PDT 24 117368747 ps
T511 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3067280078 Jun 07 06:00:29 PM PDT 24 Jun 07 06:00:30 PM PDT 24 15696253 ps
T512 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3615319470 Jun 07 06:00:26 PM PDT 24 Jun 07 06:00:27 PM PDT 24 37991077 ps
T513 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2401239373 Jun 07 05:59:18 PM PDT 24 Jun 07 05:59:20 PM PDT 24 832644438 ps
T514 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3518118697 Jun 07 06:03:20 PM PDT 24 Jun 07 06:03:21 PM PDT 24 16499371 ps
T515 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.85782537 Jun 07 06:01:27 PM PDT 24 Jun 07 06:01:28 PM PDT 24 22372379 ps
T516 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.963317821 Jun 07 06:03:24 PM PDT 24 Jun 07 06:03:26 PM PDT 24 81960662 ps
T517 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2022867682 Jun 07 06:03:24 PM PDT 24 Jun 07 06:03:26 PM PDT 24 267622512 ps
T82 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2254316574 Jun 07 06:00:44 PM PDT 24 Jun 07 06:00:45 PM PDT 24 19841363 ps
T518 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3085746321 Jun 07 06:03:19 PM PDT 24 Jun 07 06:03:20 PM PDT 24 12271641 ps
T83 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.821987893 Jun 07 06:03:53 PM PDT 24 Jun 07 06:03:54 PM PDT 24 41752877 ps
T519 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4217140817 Jun 07 06:04:01 PM PDT 24 Jun 07 06:04:02 PM PDT 24 49146616 ps
T520 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3646413873 Jun 07 05:59:49 PM PDT 24 Jun 07 05:59:50 PM PDT 24 16420653 ps
T521 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3163844620 Jun 07 06:03:16 PM PDT 24 Jun 07 06:03:19 PM PDT 24 115423299 ps
T99 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.96705802 Jun 07 06:04:16 PM PDT 24 Jun 07 06:04:18 PM PDT 24 456162036 ps
T522 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.372863099 Jun 07 06:00:38 PM PDT 24 Jun 07 06:00:39 PM PDT 24 393501158 ps
T523 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1792113194 Jun 07 06:04:01 PM PDT 24 Jun 07 06:04:05 PM PDT 24 161144300 ps
T524 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1133755257 Jun 07 06:03:24 PM PDT 24 Jun 07 06:03:25 PM PDT 24 28563478 ps
T525 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1759302541 Jun 07 06:00:19 PM PDT 24 Jun 07 06:00:20 PM PDT 24 19301365 ps
T526 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3646937190 Jun 07 06:00:02 PM PDT 24 Jun 07 06:00:03 PM PDT 24 27206075 ps
T527 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3757418304 Jun 07 05:59:18 PM PDT 24 Jun 07 05:59:19 PM PDT 24 32064814 ps
T528 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2869585923 Jun 07 06:00:56 PM PDT 24 Jun 07 06:00:57 PM PDT 24 58756835 ps
T84 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.363437018 Jun 07 06:03:56 PM PDT 24 Jun 07 06:03:58 PM PDT 24 32142205 ps
T529 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2985574088 Jun 07 06:04:00 PM PDT 24 Jun 07 06:04:01 PM PDT 24 41203504 ps
T530 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.791651925 Jun 07 06:00:19 PM PDT 24 Jun 07 06:00:20 PM PDT 24 59433539 ps
T531 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1420260978 Jun 07 06:01:27 PM PDT 24 Jun 07 06:01:30 PM PDT 24 96565741 ps
T532 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2268198164 Jun 07 06:03:16 PM PDT 24 Jun 07 06:03:17 PM PDT 24 23335397 ps
T85 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2753415002 Jun 07 06:04:06 PM PDT 24 Jun 07 06:04:07 PM PDT 24 204410569 ps
T533 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3864633870 Jun 07 05:59:46 PM PDT 24 Jun 07 05:59:47 PM PDT 24 24154801 ps
T534 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4138433997 Jun 07 06:04:23 PM PDT 24 Jun 07 06:04:24 PM PDT 24 233875491 ps
T535 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3424649150 Jun 07 06:03:17 PM PDT 24 Jun 07 06:03:19 PM PDT 24 23933939 ps
T536 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3133379941 Jun 07 06:00:37 PM PDT 24 Jun 07 06:00:39 PM PDT 24 117900212 ps
T537 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.66676236 Jun 07 06:04:09 PM PDT 24 Jun 07 06:04:10 PM PDT 24 27825303 ps
T538 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4096465911 Jun 07 06:01:33 PM PDT 24 Jun 07 06:01:34 PM PDT 24 41982952 ps
T86 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3124558748 Jun 07 06:01:15 PM PDT 24 Jun 07 06:01:16 PM PDT 24 13595666 ps
T539 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1722618758 Jun 07 06:03:38 PM PDT 24 Jun 07 06:03:40 PM PDT 24 60397121 ps
T540 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1227166433 Jun 07 06:00:25 PM PDT 24 Jun 07 06:00:27 PM PDT 24 105569205 ps
T541 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2444247713 Jun 07 06:04:23 PM PDT 24 Jun 07 06:04:24 PM PDT 24 51964864 ps
T542 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2986236840 Jun 07 06:03:36 PM PDT 24 Jun 07 06:03:37 PM PDT 24 75491249 ps
T88 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3960678850 Jun 07 06:04:05 PM PDT 24 Jun 07 06:04:06 PM PDT 24 50262168 ps
T543 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2892446170 Jun 07 06:04:00 PM PDT 24 Jun 07 06:04:01 PM PDT 24 12045655 ps
T544 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2917353977 Jun 07 06:03:32 PM PDT 24 Jun 07 06:03:35 PM PDT 24 162750867 ps
T545 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4097841588 Jun 07 05:59:49 PM PDT 24 Jun 07 05:59:52 PM PDT 24 285392469 ps
T546 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2507878752 Jun 07 06:04:06 PM PDT 24 Jun 07 06:04:07 PM PDT 24 43840587 ps
T547 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2945328592 Jun 07 06:00:43 PM PDT 24 Jun 07 06:00:44 PM PDT 24 37655663 ps
T548 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1308123319 Jun 07 06:03:20 PM PDT 24 Jun 07 06:03:21 PM PDT 24 47218085 ps
T549 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1396345208 Jun 07 06:04:18 PM PDT 24 Jun 07 06:04:20 PM PDT 24 167791529 ps
T550 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.548230029 Jun 07 06:03:35 PM PDT 24 Jun 07 06:03:36 PM PDT 24 18253121 ps
T551 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1704355922 Jun 07 06:01:00 PM PDT 24 Jun 07 06:01:01 PM PDT 24 73351518 ps
T552 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3184704655 Jun 07 06:04:24 PM PDT 24 Jun 07 06:04:25 PM PDT 24 74311280 ps
T553 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4165952521 Jun 07 06:03:51 PM PDT 24 Jun 07 06:03:53 PM PDT 24 35609146 ps
T554 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1649719140 Jun 07 06:01:23 PM PDT 24 Jun 07 06:01:24 PM PDT 24 22100757 ps
T555 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3718476365 Jun 07 06:04:15 PM PDT 24 Jun 07 06:04:16 PM PDT 24 210398455 ps
T556 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.956700073 Jun 07 06:01:46 PM PDT 24 Jun 07 06:01:48 PM PDT 24 137064066 ps
T557 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2238913591 Jun 07 06:01:36 PM PDT 24 Jun 07 06:01:38 PM PDT 24 84672767 ps
T558 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2195817031 Jun 07 06:01:35 PM PDT 24 Jun 07 06:01:36 PM PDT 24 44289874 ps
T559 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.187607902 Jun 07 06:03:53 PM PDT 24 Jun 07 06:03:54 PM PDT 24 31730357 ps
T560 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3375947055 Jun 07 06:03:55 PM PDT 24 Jun 07 06:03:57 PM PDT 24 11728945 ps
T561 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1643296943 Jun 07 06:04:10 PM PDT 24 Jun 07 06:04:11 PM PDT 24 21189319 ps
T562 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.516410120 Jun 07 06:00:34 PM PDT 24 Jun 07 06:00:35 PM PDT 24 59653540 ps
T563 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3822988259 Jun 07 05:59:38 PM PDT 24 Jun 07 05:59:39 PM PDT 24 14136347 ps
T564 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.464367248 Jun 07 06:03:47 PM PDT 24 Jun 07 06:03:49 PM PDT 24 34331863 ps
T565 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1147704638 Jun 07 06:00:22 PM PDT 24 Jun 07 06:00:22 PM PDT 24 42555700 ps
T566 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1227892800 Jun 07 05:59:55 PM PDT 24 Jun 07 05:59:56 PM PDT 24 16081012 ps
T567 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1753320695 Jun 07 06:03:51 PM PDT 24 Jun 07 06:03:52 PM PDT 24 35141193 ps
T568 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4170400199 Jun 07 06:03:24 PM PDT 24 Jun 07 06:03:25 PM PDT 24 37044608 ps
T569 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4067816622 Jun 07 06:04:10 PM PDT 24 Jun 07 06:04:13 PM PDT 24 301302536 ps
T570 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3907410321 Jun 07 06:04:24 PM PDT 24 Jun 07 06:04:27 PM PDT 24 1131858383 ps
T571 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2337764883 Jun 07 06:03:53 PM PDT 24 Jun 07 06:03:54 PM PDT 24 43664080 ps
T572 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4150502619 Jun 07 06:00:20 PM PDT 24 Jun 07 06:00:21 PM PDT 24 22373157 ps
T573 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.518551343 Jun 07 06:01:55 PM PDT 24 Jun 07 06:01:57 PM PDT 24 136131989 ps
T87 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.87213008 Jun 07 06:02:28 PM PDT 24 Jun 07 06:02:32 PM PDT 24 171584375 ps
T574 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4064872167 Jun 07 06:01:35 PM PDT 24 Jun 07 06:01:36 PM PDT 24 13479951 ps
T575 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3742871416 Jun 07 06:04:09 PM PDT 24 Jun 07 06:04:11 PM PDT 24 72049928 ps
T576 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2893953147 Jun 07 06:04:08 PM PDT 24 Jun 07 06:04:09 PM PDT 24 14995212 ps
T577 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2008476838 Jun 07 06:00:37 PM PDT 24 Jun 07 06:00:38 PM PDT 24 38220400 ps
T578 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.218095840 Jun 07 06:04:09 PM PDT 24 Jun 07 06:04:13 PM PDT 24 416617831 ps
T579 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2844553214 Jun 07 05:59:40 PM PDT 24 Jun 07 05:59:41 PM PDT 24 16351546 ps
T580 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3587477847 Jun 07 06:00:05 PM PDT 24 Jun 07 06:00:06 PM PDT 24 30869056 ps

Test location /workspace/coverage/default/63.rv_timer_random.4129184451
Short name T4
Test name
Test status
Simulation time 104590374635 ps
CPU time 207.94 seconds
Started Jun 07 06:17:13 PM PDT 24
Finished Jun 07 06:20:41 PM PDT 24
Peak memory 191136 kb
Host smart-e740803e-8e4d-4e6c-a0b7-3d11dd08aa83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129184451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4129184451
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1555279401
Short name T11
Test name
Test status
Simulation time 95617202871 ps
CPU time 805.58 seconds
Started Jun 07 06:16:43 PM PDT 24
Finished Jun 07 06:30:10 PM PDT 24
Peak memory 208472 kb
Host smart-dfd64ad5-886e-4803-9b7d-150f07a70f9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555279401 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1555279401
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.624573654
Short name T129
Test name
Test status
Simulation time 2622022985989 ps
CPU time 1881.99 seconds
Started Jun 07 06:16:54 PM PDT 24
Finished Jun 07 06:48:16 PM PDT 24
Peak memory 196076 kb
Host smart-1443bcbc-eb2a-4508-9de4-2d7a53a53675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624573654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
624573654
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3332747709
Short name T15
Test name
Test status
Simulation time 86797634 ps
CPU time 0.9 seconds
Started Jun 07 06:16:37 PM PDT 24
Finished Jun 07 06:16:39 PM PDT 24
Peak memory 214376 kb
Host smart-583d1399-eea6-41de-9914-d9c66e8e2d45
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332747709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3332747709
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1642072805
Short name T183
Test name
Test status
Simulation time 2277772192636 ps
CPU time 3899.41 seconds
Started Jun 07 06:16:34 PM PDT 24
Finished Jun 07 07:21:34 PM PDT 24
Peak memory 191068 kb
Host smart-33f86362-f8ef-4f9d-985e-0d0e8443c41d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642072805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1642072805
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.898175136
Short name T56
Test name
Test status
Simulation time 18932591 ps
CPU time 0.6 seconds
Started Jun 07 06:03:47 PM PDT 24
Finished Jun 07 06:03:48 PM PDT 24
Peak memory 182524 kb
Host smart-0720fbd1-f496-4af4-a492-53bcf578e75a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898175136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.898175136
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1632869797
Short name T72
Test name
Test status
Simulation time 1933888620036 ps
CPU time 1777.34 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:46:54 PM PDT 24
Peak memory 191168 kb
Host smart-cfd3e086-4254-4ce2-87fc-3aefa68015a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632869797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1632869797
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.183091018
Short name T122
Test name
Test status
Simulation time 541560622777 ps
CPU time 1040.91 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:34:07 PM PDT 24
Peak memory 191088 kb
Host smart-3266f729-f696-4930-8133-b7b6f16926ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183091018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.183091018
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2599615292
Short name T112
Test name
Test status
Simulation time 1176395011878 ps
CPU time 3323.88 seconds
Started Jun 07 06:17:08 PM PDT 24
Finished Jun 07 07:12:33 PM PDT 24
Peak memory 191084 kb
Host smart-401cf90e-ca8a-4bdf-a8f9-06fa445b0965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599615292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2599615292
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1347138767
Short name T230
Test name
Test status
Simulation time 1316910786278 ps
CPU time 2246.82 seconds
Started Jun 07 06:16:53 PM PDT 24
Finished Jun 07 06:54:20 PM PDT 24
Peak memory 195840 kb
Host smart-d68583fb-b872-44ff-adee-823954d25391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347138767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1347138767
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1252109674
Short name T28
Test name
Test status
Simulation time 95962931 ps
CPU time 0.79 seconds
Started Jun 07 06:03:20 PM PDT 24
Finished Jun 07 06:03:22 PM PDT 24
Peak memory 182576 kb
Host smart-c77091f3-9be1-452a-b8ce-619e8628ec13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252109674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1252109674
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3633646399
Short name T71
Test name
Test status
Simulation time 1763690821300 ps
CPU time 1080.71 seconds
Started Jun 07 06:17:04 PM PDT 24
Finished Jun 07 06:35:05 PM PDT 24
Peak memory 191184 kb
Host smart-aab7ab7f-15e2-4d2c-ae2f-783c20b36340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633646399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3633646399
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.244572463
Short name T149
Test name
Test status
Simulation time 321800735872 ps
CPU time 994.88 seconds
Started Jun 07 06:17:06 PM PDT 24
Finished Jun 07 06:33:42 PM PDT 24
Peak memory 191060 kb
Host smart-7a6baf8b-4ec0-413b-90c3-694ad5766f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244572463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
244572463
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.696597278
Short name T103
Test name
Test status
Simulation time 1113652587949 ps
CPU time 1108.45 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:35:27 PM PDT 24
Peak memory 191072 kb
Host smart-acb22814-aa01-4b96-bfa9-64f70ffdcaa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696597278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
696597278
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3615897992
Short name T70
Test name
Test status
Simulation time 336672140129 ps
CPU time 902.5 seconds
Started Jun 07 06:16:47 PM PDT 24
Finished Jun 07 06:31:50 PM PDT 24
Peak memory 196308 kb
Host smart-fcdce42b-f954-41c3-8283-7a5963724eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615897992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3615897992
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1162553566
Short name T157
Test name
Test status
Simulation time 1621257849709 ps
CPU time 1233.38 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:37:45 PM PDT 24
Peak memory 191072 kb
Host smart-a528b9e8-9b2c-452e-9f26-32e39f5ab586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162553566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1162553566
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.3421801527
Short name T110
Test name
Test status
Simulation time 562664892939 ps
CPU time 1487.09 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:42:04 PM PDT 24
Peak memory 191040 kb
Host smart-7f390d2c-d030-4ba1-8919-1e7b2568a919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421801527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3421801527
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2576784784
Short name T73
Test name
Test status
Simulation time 1440777840114 ps
CPU time 1020.06 seconds
Started Jun 07 06:16:47 PM PDT 24
Finished Jun 07 06:33:48 PM PDT 24
Peak memory 193608 kb
Host smart-4608ac72-b6cb-4b40-9dd4-97a5c86b3b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576784784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2576784784
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.982622154
Short name T263
Test name
Test status
Simulation time 866304529918 ps
CPU time 650.42 seconds
Started Jun 07 06:17:27 PM PDT 24
Finished Jun 07 06:28:18 PM PDT 24
Peak memory 191180 kb
Host smart-9e3c77c5-c1a2-4cb1-8c5f-e30a9baa3d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982622154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.982622154
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4255253565
Short name T236
Test name
Test status
Simulation time 1334448061831 ps
CPU time 1447.63 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:41:07 PM PDT 24
Peak memory 191160 kb
Host smart-3a3d79f2-9106-4335-85fb-2f5b0d57cf4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255253565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4255253565
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3049071742
Short name T135
Test name
Test status
Simulation time 2345052562326 ps
CPU time 1275.76 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:38:00 PM PDT 24
Peak memory 191044 kb
Host smart-e945ae29-5fd2-4736-8e53-3eed1709f27e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049071742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3049071742
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3503640785
Short name T109
Test name
Test status
Simulation time 69023819103 ps
CPU time 133.36 seconds
Started Jun 07 06:17:13 PM PDT 24
Finished Jun 07 06:19:27 PM PDT 24
Peak memory 191092 kb
Host smart-9b279cd1-44e9-47c7-ac0d-ad9ba90b6ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503640785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3503640785
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2289563210
Short name T146
Test name
Test status
Simulation time 162580348839 ps
CPU time 303.05 seconds
Started Jun 07 06:17:21 PM PDT 24
Finished Jun 07 06:22:25 PM PDT 24
Peak memory 191200 kb
Host smart-669900eb-04ea-4f63-a85b-7d8e3e3afa9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289563210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2289563210
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4060909063
Short name T168
Test name
Test status
Simulation time 212124237438 ps
CPU time 255.33 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 06:21:35 PM PDT 24
Peak memory 191196 kb
Host smart-2506258e-9aff-47ac-b563-3b5e8357477b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060909063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4060909063
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1026025473
Short name T325
Test name
Test status
Simulation time 137396319686 ps
CPU time 252.48 seconds
Started Jun 07 06:17:33 PM PDT 24
Finished Jun 07 06:21:46 PM PDT 24
Peak memory 191084 kb
Host smart-ca0f9e1f-dd53-4603-b3bf-d9520ef971ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026025473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1026025473
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.223574773
Short name T180
Test name
Test status
Simulation time 312937233353 ps
CPU time 317.21 seconds
Started Jun 07 06:17:39 PM PDT 24
Finished Jun 07 06:22:57 PM PDT 24
Peak memory 191096 kb
Host smart-cab0dbdf-8253-4dfe-ad96-db8cc7ffca81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223574773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.223574773
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3427011911
Short name T264
Test name
Test status
Simulation time 326354092030 ps
CPU time 394.5 seconds
Started Jun 07 06:16:21 PM PDT 24
Finished Jun 07 06:22:56 PM PDT 24
Peak memory 182900 kb
Host smart-b481f833-6fde-452e-8b44-186099342b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427011911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3427011911
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2149242669
Short name T43
Test name
Test status
Simulation time 129966956799 ps
CPU time 293.67 seconds
Started Jun 07 06:17:21 PM PDT 24
Finished Jun 07 06:22:16 PM PDT 24
Peak memory 191064 kb
Host smart-8939426a-d955-4b17-9b10-ad4599e23f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149242669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2149242669
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2642454068
Short name T204
Test name
Test status
Simulation time 97055939902 ps
CPU time 178.35 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 06:20:19 PM PDT 24
Peak memory 182880 kb
Host smart-ad2e0736-36ca-4c8b-8217-f3c53fc7e181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642454068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2642454068
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3229693646
Short name T176
Test name
Test status
Simulation time 102783013395 ps
CPU time 228.03 seconds
Started Jun 07 06:17:26 PM PDT 24
Finished Jun 07 06:21:14 PM PDT 24
Peak memory 194440 kb
Host smart-7a6fb332-9e12-4564-aaa2-ea9697acc9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229693646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3229693646
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2026875027
Short name T163
Test name
Test status
Simulation time 185431915779 ps
CPU time 2572.79 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 07:00:13 PM PDT 24
Peak memory 191100 kb
Host smart-de70d73c-9696-488c-b42a-949b7898a709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026875027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2026875027
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1273402147
Short name T113
Test name
Test status
Simulation time 748837275264 ps
CPU time 770.63 seconds
Started Jun 07 06:16:46 PM PDT 24
Finished Jun 07 06:29:37 PM PDT 24
Peak memory 191028 kb
Host smart-b51d7acb-8930-4387-b784-5151b9c5b107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273402147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1273402147
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.1270472881
Short name T226
Test name
Test status
Simulation time 165001493720 ps
CPU time 575.44 seconds
Started Jun 07 06:17:17 PM PDT 24
Finished Jun 07 06:26:53 PM PDT 24
Peak memory 191092 kb
Host smart-3a3dcf4c-c3ca-4720-87c2-2e878cbf57d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270472881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1270472881
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2108568596
Short name T203
Test name
Test status
Simulation time 247851111580 ps
CPU time 154.78 seconds
Started Jun 07 06:17:46 PM PDT 24
Finished Jun 07 06:20:21 PM PDT 24
Peak memory 191204 kb
Host smart-1afbd4fa-a7d4-41e9-b42e-d4a9b505b385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108568596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2108568596
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1445161383
Short name T144
Test name
Test status
Simulation time 129761796472 ps
CPU time 340.49 seconds
Started Jun 07 06:17:48 PM PDT 24
Finished Jun 07 06:23:29 PM PDT 24
Peak memory 191160 kb
Host smart-6b14f222-2bc2-4b70-8d5b-4a2aef060224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445161383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1445161383
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.3080183943
Short name T238
Test name
Test status
Simulation time 106363803043 ps
CPU time 932.03 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:32:35 PM PDT 24
Peak memory 191184 kb
Host smart-48a51032-c072-4eac-b0b5-0bf1a8759acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080183943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3080183943
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.817971709
Short name T33
Test name
Test status
Simulation time 26280879 ps
CPU time 0.77 seconds
Started Jun 07 05:59:27 PM PDT 24
Finished Jun 07 05:59:28 PM PDT 24
Peak memory 191512 kb
Host smart-35088f60-6896-4ee3-ad35-1a6b98faa41d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817971709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.817971709
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/123.rv_timer_random.3806236590
Short name T341
Test name
Test status
Simulation time 166292392456 ps
CPU time 434.39 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:24:31 PM PDT 24
Peak memory 191088 kb
Host smart-482d52a4-ee3b-4660-aef0-ef0bf30ab7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806236590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3806236590
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3956804863
Short name T121
Test name
Test status
Simulation time 726991628976 ps
CPU time 363.44 seconds
Started Jun 07 06:17:26 PM PDT 24
Finished Jun 07 06:23:30 PM PDT 24
Peak memory 191088 kb
Host smart-53c6794b-dd3d-44a4-9842-8b2d79b53ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956804863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3956804863
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1749102067
Short name T200
Test name
Test status
Simulation time 646364891467 ps
CPU time 382.46 seconds
Started Jun 07 06:17:45 PM PDT 24
Finished Jun 07 06:24:08 PM PDT 24
Peak memory 191072 kb
Host smart-c1c1c9c7-ec51-4253-a5a6-d558fd4e90e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749102067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1749102067
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.4287411689
Short name T283
Test name
Test status
Simulation time 3431661012471 ps
CPU time 703.89 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:28:46 PM PDT 24
Peak memory 191096 kb
Host smart-52395f88-03a5-46a1-a8e3-0262308499ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287411689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4287411689
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1677679001
Short name T311
Test name
Test status
Simulation time 3397366845158 ps
CPU time 502.38 seconds
Started Jun 07 06:16:40 PM PDT 24
Finished Jun 07 06:25:03 PM PDT 24
Peak memory 191144 kb
Host smart-b7e762e1-c9cc-47a6-b02a-8c890f3c7ac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677679001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1677679001
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/106.rv_timer_random.2674100380
Short name T132
Test name
Test status
Simulation time 94625938185 ps
CPU time 189.38 seconds
Started Jun 07 06:17:22 PM PDT 24
Finished Jun 07 06:20:32 PM PDT 24
Peak memory 191192 kb
Host smart-320c574f-4177-449c-a829-4ec513833a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674100380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2674100380
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.3980534513
Short name T277
Test name
Test status
Simulation time 439963001354 ps
CPU time 221.46 seconds
Started Jun 07 06:17:22 PM PDT 24
Finished Jun 07 06:21:05 PM PDT 24
Peak memory 191020 kb
Host smart-13af587d-8749-4ebf-ba29-c7cff7c70c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980534513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3980534513
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2615634
Short name T240
Test name
Test status
Simulation time 362149677812 ps
CPU time 312.76 seconds
Started Jun 07 06:17:21 PM PDT 24
Finished Jun 07 06:22:34 PM PDT 24
Peak memory 191180 kb
Host smart-975adaaf-a9cf-486f-bcf5-7f7db3b06bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2615634
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.447229852
Short name T130
Test name
Test status
Simulation time 452356666454 ps
CPU time 441.45 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:24:07 PM PDT 24
Peak memory 191096 kb
Host smart-b9336945-d3a3-43c1-b355-0f6d92588114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447229852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.447229852
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.80140785
Short name T267
Test name
Test status
Simulation time 136464068283 ps
CPU time 667.26 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:27:52 PM PDT 24
Peak memory 191108 kb
Host smart-a68257b8-d804-4919-abe7-881085ca6b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80140785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.80140785
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.2977842628
Short name T111
Test name
Test status
Simulation time 3125595927172 ps
CPU time 1063.08 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:34:39 PM PDT 24
Peak memory 191184 kb
Host smart-641a194f-377f-4aa4-8668-216e8dbae7df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977842628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2977842628
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random.1778077741
Short name T250
Test name
Test status
Simulation time 558187122590 ps
CPU time 349.33 seconds
Started Jun 07 06:17:08 PM PDT 24
Finished Jun 07 06:22:58 PM PDT 24
Peak memory 191080 kb
Host smart-9aff71ea-0813-4a67-a5a4-81dec5cada8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778077741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1778077741
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2993559387
Short name T23
Test name
Test status
Simulation time 574225835812 ps
CPU time 794.28 seconds
Started Jun 07 06:17:24 PM PDT 24
Finished Jun 07 06:30:39 PM PDT 24
Peak memory 191116 kb
Host smart-46409377-5b76-44e5-8331-551ef2f094e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993559387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2993559387
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1617959728
Short name T97
Test name
Test status
Simulation time 433512900 ps
CPU time 1.3 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 05:59:51 PM PDT 24
Peak memory 194868 kb
Host smart-8f457811-2643-4fef-ae8f-d57c6c1bff1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617959728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1617959728
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/111.rv_timer_random.513692042
Short name T450
Test name
Test status
Simulation time 432678738606 ps
CPU time 401.46 seconds
Started Jun 07 06:17:17 PM PDT 24
Finished Jun 07 06:23:59 PM PDT 24
Peak memory 191092 kb
Host smart-0f5018e0-762e-4eae-82ff-cf11786b296c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513692042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.513692042
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.900818329
Short name T106
Test name
Test status
Simulation time 146238568957 ps
CPU time 246.14 seconds
Started Jun 07 06:17:24 PM PDT 24
Finished Jun 07 06:21:30 PM PDT 24
Peak memory 191080 kb
Host smart-b9c421f6-2aa5-4023-95b5-8842a354bf4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900818329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.900818329
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.271177787
Short name T266
Test name
Test status
Simulation time 578424988073 ps
CPU time 280.08 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 06:22:00 PM PDT 24
Peak memory 191088 kb
Host smart-1070d21a-1cbf-4e25-a6f7-84eee1df65f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271177787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.271177787
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3783878203
Short name T254
Test name
Test status
Simulation time 104491605898 ps
CPU time 663.94 seconds
Started Jun 07 06:17:23 PM PDT 24
Finished Jun 07 06:28:27 PM PDT 24
Peak memory 193424 kb
Host smart-066ad026-2108-4f1c-a1c4-69178d2dddb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783878203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3783878203
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1894925874
Short name T181
Test name
Test status
Simulation time 1142235177787 ps
CPU time 653.75 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:27:42 PM PDT 24
Peak memory 182972 kb
Host smart-05bf9421-8b3c-4160-ad1c-c98632894751
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894925874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1894925874
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/197.rv_timer_random.1486871806
Short name T165
Test name
Test status
Simulation time 172644403658 ps
CPU time 318.28 seconds
Started Jun 07 06:17:44 PM PDT 24
Finished Jun 07 06:23:02 PM PDT 24
Peak memory 191092 kb
Host smart-1d221af1-cef3-4fcd-9cba-94dfb5b69ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486871806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1486871806
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2252764564
Short name T198
Test name
Test status
Simulation time 339287221935 ps
CPU time 682.86 seconds
Started Jun 07 06:16:52 PM PDT 24
Finished Jun 07 06:28:16 PM PDT 24
Peak memory 191040 kb
Host smart-d51b52ba-6b76-4d78-a5ca-d3f54976703a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252764564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2252764564
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/57.rv_timer_random.626698526
Short name T228
Test name
Test status
Simulation time 765449097994 ps
CPU time 307.93 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:22:20 PM PDT 24
Peak memory 191152 kb
Host smart-74169bcb-3540-4663-acbd-302c761f6260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626698526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.626698526
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3898453197
Short name T310
Test name
Test status
Simulation time 1686523360523 ps
CPU time 1942.03 seconds
Started Jun 07 06:16:34 PM PDT 24
Finished Jun 07 06:48:57 PM PDT 24
Peak memory 194816 kb
Host smart-fb14d6db-9ff6-4f37-9a3e-0e07f99429a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898453197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3898453197
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/98.rv_timer_random.719433770
Short name T320
Test name
Test status
Simulation time 62532636515 ps
CPU time 265.23 seconds
Started Jun 07 06:17:17 PM PDT 24
Finished Jun 07 06:21:43 PM PDT 24
Peak memory 191140 kb
Host smart-a5bcebc7-7255-46f1-af12-4fc99ccd9e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719433770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.719433770
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.1522990306
Short name T249
Test name
Test status
Simulation time 87052719442 ps
CPU time 185.97 seconds
Started Jun 07 06:16:35 PM PDT 24
Finished Jun 07 06:19:42 PM PDT 24
Peak memory 191100 kb
Host smart-384f2de3-56c3-4234-bf6a-173befd7a476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522990306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1522990306
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.399428573
Short name T153
Test name
Test status
Simulation time 122111151068 ps
CPU time 32.56 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:17:18 PM PDT 24
Peak memory 194692 kb
Host smart-901dcc94-8353-4e3e-82a3-e8562eb5b832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399428573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.399428573
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.4179083548
Short name T160
Test name
Test status
Simulation time 19439833924 ps
CPU time 19.06 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:17:08 PM PDT 24
Peak memory 182872 kb
Host smart-8b88b573-1281-4599-bfcf-3c555728f4fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179083548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.4179083548
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random.958161314
Short name T332
Test name
Test status
Simulation time 855864820979 ps
CPU time 1576.04 seconds
Started Jun 07 06:16:55 PM PDT 24
Finished Jun 07 06:43:12 PM PDT 24
Peak memory 191044 kb
Host smart-74dbef86-9db1-4d10-8cd4-205893d86c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958161314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.958161314
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.4210303929
Short name T261
Test name
Test status
Simulation time 143318758121 ps
CPU time 266 seconds
Started Jun 07 06:17:28 PM PDT 24
Finished Jun 07 06:21:54 PM PDT 24
Peak memory 191204 kb
Host smart-3d11030c-7c17-4106-9f7a-f261ec365be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210303929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.4210303929
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3983692709
Short name T243
Test name
Test status
Simulation time 1566035729121 ps
CPU time 657.06 seconds
Started Jun 07 06:17:31 PM PDT 24
Finished Jun 07 06:28:29 PM PDT 24
Peak memory 191188 kb
Host smart-716ea053-db24-4659-9c4c-ca46127f8f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983692709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3983692709
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3721538790
Short name T248
Test name
Test status
Simulation time 200970912274 ps
CPU time 341.24 seconds
Started Jun 07 06:17:33 PM PDT 24
Finished Jun 07 06:23:15 PM PDT 24
Peak memory 191132 kb
Host smart-b3cd660d-90aa-4f8d-ab42-1476e79b5426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721538790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3721538790
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4102242041
Short name T190
Test name
Test status
Simulation time 160475075540 ps
CPU time 283.95 seconds
Started Jun 07 06:17:36 PM PDT 24
Finished Jun 07 06:22:20 PM PDT 24
Peak memory 191088 kb
Host smart-eef87f75-38d9-4caf-b3c2-128c4ad15bf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102242041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4102242041
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.331840654
Short name T177
Test name
Test status
Simulation time 128074034896 ps
CPU time 290.84 seconds
Started Jun 07 06:17:41 PM PDT 24
Finished Jun 07 06:22:32 PM PDT 24
Peak memory 191204 kb
Host smart-494c50d6-0f9d-4ef1-95cd-060de463924a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331840654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.331840654
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3985569194
Short name T270
Test name
Test status
Simulation time 168065397910 ps
CPU time 1995.26 seconds
Started Jun 07 06:17:46 PM PDT 24
Finished Jun 07 06:51:02 PM PDT 24
Peak memory 191172 kb
Host smart-e96990cb-7984-418b-8a47-cf329dca7a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985569194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3985569194
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.1516939796
Short name T49
Test name
Test status
Simulation time 344909400220 ps
CPU time 366.17 seconds
Started Jun 07 06:17:09 PM PDT 24
Finished Jun 07 06:23:15 PM PDT 24
Peak memory 191036 kb
Host smart-fa37ea97-9463-47df-ac9d-ebc09c171795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516939796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1516939796
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.399602334
Short name T293
Test name
Test status
Simulation time 581745739674 ps
CPU time 1126.96 seconds
Started Jun 07 06:17:04 PM PDT 24
Finished Jun 07 06:35:51 PM PDT 24
Peak memory 194644 kb
Host smart-b3e455ae-5e52-4ac0-93bd-fe0baca66b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399602334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
399602334
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1347615257
Short name T241
Test name
Test status
Simulation time 991872837349 ps
CPU time 300.26 seconds
Started Jun 07 06:17:06 PM PDT 24
Finished Jun 07 06:22:06 PM PDT 24
Peak memory 195740 kb
Host smart-3a4dee24-cba1-4cd2-8d15-42e064cd7181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347615257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1347615257
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/67.rv_timer_random.4122568091
Short name T61
Test name
Test status
Simulation time 98601751734 ps
CPU time 145.12 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:19:41 PM PDT 24
Peak memory 191048 kb
Host smart-8cb7bda4-dc80-4027-bf66-b694c001cd42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122568091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4122568091
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.476860557
Short name T227
Test name
Test status
Simulation time 626313359477 ps
CPU time 211.25 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:20:48 PM PDT 24
Peak memory 191056 kb
Host smart-21ea8477-3cc1-488e-8eb3-828f037ab125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476860557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.476860557
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.129354888
Short name T213
Test name
Test status
Simulation time 388904880873 ps
CPU time 567.29 seconds
Started Jun 07 06:17:20 PM PDT 24
Finished Jun 07 06:26:48 PM PDT 24
Peak memory 191096 kb
Host smart-dcdfd0ef-f2b9-449a-af4a-73712b881f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129354888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.129354888
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1007781378
Short name T350
Test name
Test status
Simulation time 102147686027 ps
CPU time 48.53 seconds
Started Jun 07 06:17:20 PM PDT 24
Finished Jun 07 06:18:09 PM PDT 24
Peak memory 182892 kb
Host smart-eb934467-f14e-48d4-b989-c5dbd222c0b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007781378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1007781378
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1097192549
Short name T214
Test name
Test status
Simulation time 81197160848 ps
CPU time 145.85 seconds
Started Jun 07 06:17:21 PM PDT 24
Finished Jun 07 06:19:48 PM PDT 24
Peak memory 191100 kb
Host smart-a782856b-f7ff-499d-87f2-3be97c137ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097192549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1097192549
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.145104450
Short name T167
Test name
Test status
Simulation time 147507865803 ps
CPU time 123.89 seconds
Started Jun 07 06:17:22 PM PDT 24
Finished Jun 07 06:19:27 PM PDT 24
Peak memory 194692 kb
Host smart-467671d5-d8e5-45dc-91fb-b0959df487a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145104450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.145104450
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.2791698569
Short name T179
Test name
Test status
Simulation time 144083968537 ps
CPU time 372.28 seconds
Started Jun 07 06:16:37 PM PDT 24
Finished Jun 07 06:22:49 PM PDT 24
Peak memory 191204 kb
Host smart-98519d63-ce1f-40bc-ad56-0d857d3592ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791698569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2791698569
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2320865875
Short name T215
Test name
Test status
Simulation time 195127648940 ps
CPU time 340.91 seconds
Started Jun 07 06:17:22 PM PDT 24
Finished Jun 07 06:23:04 PM PDT 24
Peak memory 191044 kb
Host smart-4d979f80-6142-40f6-adbb-ac2f804859c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320865875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2320865875
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4091062164
Short name T285
Test name
Test status
Simulation time 82567545329 ps
CPU time 45.1 seconds
Started Jun 07 06:16:52 PM PDT 24
Finished Jun 07 06:17:37 PM PDT 24
Peak memory 194200 kb
Host smart-287f4f8f-fcf8-4200-8518-034514c7d298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091062164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4091062164
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.69297497
Short name T34
Test name
Test status
Simulation time 214708772255 ps
CPU time 182.52 seconds
Started Jun 07 06:16:46 PM PDT 24
Finished Jun 07 06:19:49 PM PDT 24
Peak memory 194592 kb
Host smart-8de011ba-47c5-4d86-baa0-3fec8306d31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69297497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.69297497
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.257431762
Short name T194
Test name
Test status
Simulation time 205043207466 ps
CPU time 2748.44 seconds
Started Jun 07 06:17:30 PM PDT 24
Finished Jun 07 07:03:19 PM PDT 24
Peak memory 191212 kb
Host smart-18127e51-384a-4810-9a7c-034dea4003c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257431762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.257431762
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.125658240
Short name T24
Test name
Test status
Simulation time 177102350229 ps
CPU time 268.19 seconds
Started Jun 07 06:17:38 PM PDT 24
Finished Jun 07 06:22:07 PM PDT 24
Peak memory 192204 kb
Host smart-f7e7b52d-3b8b-48a0-bc52-a87754ef21a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125658240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.125658240
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3270725830
Short name T244
Test name
Test status
Simulation time 1264139048120 ps
CPU time 700.63 seconds
Started Jun 07 06:16:51 PM PDT 24
Finished Jun 07 06:28:33 PM PDT 24
Peak memory 182988 kb
Host smart-1215c45a-6108-4c5e-be89-76621263d673
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270725830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3270725830
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2554702107
Short name T69
Test name
Test status
Simulation time 646040842460 ps
CPU time 1416.49 seconds
Started Jun 07 06:16:46 PM PDT 24
Finished Jun 07 06:40:24 PM PDT 24
Peak memory 191284 kb
Host smart-f089d0e2-b6e6-4bf0-b7ca-83b5000d2e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554702107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2554702107
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.1145506329
Short name T262
Test name
Test status
Simulation time 327783875756 ps
CPU time 326.05 seconds
Started Jun 07 06:17:44 PM PDT 24
Finished Jun 07 06:23:11 PM PDT 24
Peak memory 191088 kb
Host smart-0868152a-66d5-4907-add4-db9e8b717d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145506329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1145506329
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2625834700
Short name T211
Test name
Test status
Simulation time 360225520106 ps
CPU time 295.18 seconds
Started Jun 07 06:17:44 PM PDT 24
Finished Jun 07 06:22:40 PM PDT 24
Peak memory 182852 kb
Host smart-8b21a85c-30b2-44db-88a2-ed4331ac4d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625834700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2625834700
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.3831485628
Short name T331
Test name
Test status
Simulation time 361859131813 ps
CPU time 246.76 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:21:03 PM PDT 24
Peak memory 191040 kb
Host smart-229d2866-6243-4d16-bc6c-d6022d07e8f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831485628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3831485628
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1158729965
Short name T306
Test name
Test status
Simulation time 12996068845 ps
CPU time 9.07 seconds
Started Jun 07 06:16:38 PM PDT 24
Finished Jun 07 06:16:48 PM PDT 24
Peak memory 191064 kb
Host smart-22a241a2-328e-459c-8f68-849c21bdbb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158729965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1158729965
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_random.2469669271
Short name T269
Test name
Test status
Simulation time 163269660829 ps
CPU time 1293.54 seconds
Started Jun 07 06:17:04 PM PDT 24
Finished Jun 07 06:38:38 PM PDT 24
Peak memory 191180 kb
Host smart-466d8965-767d-4f7a-bdb0-4ef189557391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469669271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2469669271
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random.2285156516
Short name T8
Test name
Test status
Simulation time 91971201874 ps
CPU time 168.61 seconds
Started Jun 07 06:17:12 PM PDT 24
Finished Jun 07 06:20:01 PM PDT 24
Peak memory 191024 kb
Host smart-5b9e6d78-2ee3-4615-a3ff-078221d2be4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285156516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2285156516
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.259280356
Short name T298
Test name
Test status
Simulation time 41387443436 ps
CPU time 73.5 seconds
Started Jun 07 06:16:47 PM PDT 24
Finished Jun 07 06:18:02 PM PDT 24
Peak memory 194436 kb
Host smart-47b85d61-fd29-49b3-89bd-88266893175c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259280356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.259280356
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1606760820
Short name T182
Test name
Test status
Simulation time 17887975632 ps
CPU time 28.15 seconds
Started Jun 07 06:17:22 PM PDT 24
Finished Jun 07 06:17:51 PM PDT 24
Peak memory 182816 kb
Host smart-f1c0cb93-e13e-4c47-bef1-d027df4bcf31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606760820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1606760820
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.857669530
Short name T79
Test name
Test status
Simulation time 36253704 ps
CPU time 0.85 seconds
Started Jun 07 06:00:49 PM PDT 24
Finished Jun 07 06:00:50 PM PDT 24
Peak memory 192304 kb
Host smart-e0074d31-e99e-4ac7-adc6-c311d9189c2f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857669530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.857669530
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.372863099
Short name T522
Test name
Test status
Simulation time 393501158 ps
CPU time 1.5 seconds
Started Jun 07 06:00:38 PM PDT 24
Finished Jun 07 06:00:39 PM PDT 24
Peak memory 193236 kb
Host smart-38927e46-44cd-42f6-839e-38e306f91900
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372863099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.372863099
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3375947055
Short name T560
Test name
Test status
Simulation time 11728945 ps
CPU time 0.57 seconds
Started Jun 07 06:03:55 PM PDT 24
Finished Jun 07 06:03:57 PM PDT 24
Peak memory 181524 kb
Host smart-1afc26fd-f1cf-4c67-8db7-ec0634cb9ce3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375947055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3375947055
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1583893067
Short name T494
Test name
Test status
Simulation time 44777700 ps
CPU time 0.67 seconds
Started Jun 07 05:59:40 PM PDT 24
Finished Jun 07 05:59:41 PM PDT 24
Peak memory 194348 kb
Host smart-9f968e45-923b-4daa-b8e2-d13c8a3b0584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583893067 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1583893067
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2254316574
Short name T82
Test name
Test status
Simulation time 19841363 ps
CPU time 0.68 seconds
Started Jun 07 06:00:44 PM PDT 24
Finished Jun 07 06:00:45 PM PDT 24
Peak memory 182872 kb
Host smart-24dfe00f-8778-42a5-9ed6-2ccbc4a20495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254316574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2254316574
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1227892800
Short name T566
Test name
Test status
Simulation time 16081012 ps
CPU time 0.56 seconds
Started Jun 07 05:59:55 PM PDT 24
Finished Jun 07 05:59:56 PM PDT 24
Peak memory 182428 kb
Host smart-19a56719-0d1d-4979-a359-1ab083bd4816
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227892800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1227892800
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4018311700
Short name T92
Test name
Test status
Simulation time 19541576 ps
CPU time 0.71 seconds
Started Jun 07 06:00:40 PM PDT 24
Finished Jun 07 06:00:41 PM PDT 24
Peak memory 193036 kb
Host smart-03ce67f5-19d9-410e-b74b-014e6c955555
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018311700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4018311700
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3517926628
Short name T472
Test name
Test status
Simulation time 180264332 ps
CPU time 2.09 seconds
Started Jun 07 06:03:23 PM PDT 24
Finished Jun 07 06:03:26 PM PDT 24
Peak memory 196204 kb
Host smart-93e9b556-5cc4-4bb2-9da0-82937f66c83e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517926628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3517926628
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2401239373
Short name T513
Test name
Test status
Simulation time 832644438 ps
CPU time 1.37 seconds
Started Jun 07 05:59:18 PM PDT 24
Finished Jun 07 05:59:20 PM PDT 24
Peak memory 195188 kb
Host smart-d9ffeb9f-e5c7-4f4d-b244-ba1dec36903b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401239373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2401239373
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3718476365
Short name T555
Test name
Test status
Simulation time 210398455 ps
CPU time 0.77 seconds
Started Jun 07 06:04:15 PM PDT 24
Finished Jun 07 06:04:16 PM PDT 24
Peak memory 192296 kb
Host smart-ce2e5cc0-36e6-42cf-8cdf-6a713c40e476
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718476365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3718476365
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.87213008
Short name T87
Test name
Test status
Simulation time 171584375 ps
CPU time 3.09 seconds
Started Jun 07 06:02:28 PM PDT 24
Finished Jun 07 06:02:32 PM PDT 24
Peak memory 192176 kb
Host smart-da7cfd67-7a58-41c7-a83d-ab56ca5e2e61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87213008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ba
sh.87213008
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4255517929
Short name T95
Test name
Test status
Simulation time 100637442 ps
CPU time 0.58 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:04:11 PM PDT 24
Peak memory 181428 kb
Host smart-dc27fd4e-a8a8-4a5e-aeb5-bffcc5d7419a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255517929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4255517929
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1643296943
Short name T561
Test name
Test status
Simulation time 21189319 ps
CPU time 0.66 seconds
Started Jun 07 06:04:10 PM PDT 24
Finished Jun 07 06:04:11 PM PDT 24
Peak memory 194588 kb
Host smart-ab8950ed-2487-4c20-97a4-e83507cb15bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643296943 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1643296943
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2916427640
Short name T81
Test name
Test status
Simulation time 20982597 ps
CPU time 0.59 seconds
Started Jun 07 06:00:29 PM PDT 24
Finished Jun 07 06:00:30 PM PDT 24
Peak memory 182784 kb
Host smart-c9fa4ebe-9516-40f7-b94a-03923f997cef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916427640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2916427640
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3067280078
Short name T511
Test name
Test status
Simulation time 15696253 ps
CPU time 0.64 seconds
Started Jun 07 06:00:29 PM PDT 24
Finished Jun 07 06:00:30 PM PDT 24
Peak memory 182496 kb
Host smart-f7c5fc18-3744-43f0-b0d8-0468525516b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067280078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3067280078
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1360476741
Short name T465
Test name
Test status
Simulation time 70218351 ps
CPU time 1.97 seconds
Started Jun 07 06:04:02 PM PDT 24
Finished Jun 07 06:04:04 PM PDT 24
Peak memory 196576 kb
Host smart-5c12df8b-0a46-40df-b685-458041777fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360476741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1360476741
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4096378557
Short name T101
Test name
Test status
Simulation time 350714112 ps
CPU time 1.35 seconds
Started Jun 07 06:00:15 PM PDT 24
Finished Jun 07 06:00:17 PM PDT 24
Peak memory 195424 kb
Host smart-aaffb963-c082-40bd-a864-33dba548ebb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096378557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4096378557
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2869585923
Short name T528
Test name
Test status
Simulation time 58756835 ps
CPU time 0.88 seconds
Started Jun 07 06:00:56 PM PDT 24
Finished Jun 07 06:00:57 PM PDT 24
Peak memory 196788 kb
Host smart-75750af7-435a-48ad-94aa-de6f2d76ff12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869585923 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2869585923
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1970551000
Short name T78
Test name
Test status
Simulation time 34151948 ps
CPU time 0.55 seconds
Started Jun 07 06:03:32 PM PDT 24
Finished Jun 07 06:03:32 PM PDT 24
Peak memory 182504 kb
Host smart-a07a190c-3238-4cfa-9fb5-9e6d9b0f6ca2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970551000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1970551000
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3822988259
Short name T563
Test name
Test status
Simulation time 14136347 ps
CPU time 0.57 seconds
Started Jun 07 05:59:38 PM PDT 24
Finished Jun 07 05:59:39 PM PDT 24
Peak memory 182344 kb
Host smart-b354cd82-e9a1-452e-aa84-2aedc070177d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822988259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3822988259
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3506889791
Short name T54
Test name
Test status
Simulation time 40716184 ps
CPU time 0.78 seconds
Started Jun 07 06:01:23 PM PDT 24
Finished Jun 07 06:01:24 PM PDT 24
Peak memory 193296 kb
Host smart-5a0b63ac-f267-4f9e-bf44-a01d2945d687
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506889791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3506889791
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.84053417
Short name T505
Test name
Test status
Simulation time 193375844 ps
CPU time 2.56 seconds
Started Jun 07 06:01:38 PM PDT 24
Finished Jun 07 06:01:41 PM PDT 24
Peak memory 197756 kb
Host smart-d6edc341-71c1-46ea-b7aa-1e1cb08362d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84053417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.84053417
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.187607902
Short name T559
Test name
Test status
Simulation time 31730357 ps
CPU time 0.8 seconds
Started Jun 07 06:03:53 PM PDT 24
Finished Jun 07 06:03:54 PM PDT 24
Peak memory 196152 kb
Host smart-dfc069ce-0c19-496d-b675-d550b8d0140f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187607902 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.187607902
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2268198164
Short name T532
Test name
Test status
Simulation time 23335397 ps
CPU time 0.64 seconds
Started Jun 07 06:03:16 PM PDT 24
Finished Jun 07 06:03:17 PM PDT 24
Peak memory 180900 kb
Host smart-115e0405-b6dc-4694-b75c-e2097dad378c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268198164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2268198164
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2337764883
Short name T571
Test name
Test status
Simulation time 43664080 ps
CPU time 0.62 seconds
Started Jun 07 06:03:53 PM PDT 24
Finished Jun 07 06:03:54 PM PDT 24
Peak memory 181420 kb
Host smart-d7d1f5b3-108b-4de8-be29-8211991b5db1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337764883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2337764883
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.791651925
Short name T530
Test name
Test status
Simulation time 59433539 ps
CPU time 0.64 seconds
Started Jun 07 06:00:19 PM PDT 24
Finished Jun 07 06:00:20 PM PDT 24
Peak memory 191404 kb
Host smart-d9d5d0bb-d878-4e53-acc7-b6dcf12eac9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791651925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.791651925
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2917353977
Short name T544
Test name
Test status
Simulation time 162750867 ps
CPU time 2.17 seconds
Started Jun 07 06:03:32 PM PDT 24
Finished Jun 07 06:03:35 PM PDT 24
Peak memory 197356 kb
Host smart-6ab72002-cca8-40c8-b6ab-00222280bdd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917353977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2917353977
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.790305123
Short name T499
Test name
Test status
Simulation time 708207106 ps
CPU time 1.32 seconds
Started Jun 07 06:03:21 PM PDT 24
Finished Jun 07 06:03:23 PM PDT 24
Peak memory 194932 kb
Host smart-429ac37b-67b0-4a96-a020-9b8c24eb9bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790305123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.790305123
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.192354412
Short name T492
Test name
Test status
Simulation time 126300539 ps
CPU time 0.84 seconds
Started Jun 07 05:59:35 PM PDT 24
Finished Jun 07 05:59:37 PM PDT 24
Peak memory 196388 kb
Host smart-84c065a4-1908-4b3a-956c-a1847e4e8765
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192354412 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.192354412
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2844553214
Short name T579
Test name
Test status
Simulation time 16351546 ps
CPU time 0.53 seconds
Started Jun 07 05:59:40 PM PDT 24
Finished Jun 07 05:59:41 PM PDT 24
Peak memory 182272 kb
Host smart-0df1b7b9-f4f5-4260-b374-489ca61831bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844553214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2844553214
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.66676236
Short name T537
Test name
Test status
Simulation time 27825303 ps
CPU time 0.52 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:04:10 PM PDT 24
Peak memory 182432 kb
Host smart-d0db5fed-4d0c-49ce-a1a5-5111e14e5c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66676236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.66676236
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1722618758
Short name T539
Test name
Test status
Simulation time 60397121 ps
CPU time 0.66 seconds
Started Jun 07 06:03:38 PM PDT 24
Finished Jun 07 06:03:40 PM PDT 24
Peak memory 190188 kb
Host smart-79cc65f3-2802-4fdf-b2b2-2146bda872c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722618758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1722618758
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1792113194
Short name T523
Test name
Test status
Simulation time 161144300 ps
CPU time 3.07 seconds
Started Jun 07 06:04:01 PM PDT 24
Finished Jun 07 06:04:05 PM PDT 24
Peak memory 196556 kb
Host smart-617b990f-fe64-4e7f-83e4-55a628e7e763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792113194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1792113194
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1396345208
Short name T549
Test name
Test status
Simulation time 167791529 ps
CPU time 1.15 seconds
Started Jun 07 06:04:18 PM PDT 24
Finished Jun 07 06:04:20 PM PDT 24
Peak memory 194880 kb
Host smart-b5521a56-7e0f-4653-85f8-6ef561cf8187
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396345208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1396345208
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2561467101
Short name T476
Test name
Test status
Simulation time 51345309 ps
CPU time 0.67 seconds
Started Jun 07 06:03:47 PM PDT 24
Finished Jun 07 06:03:48 PM PDT 24
Peak memory 193500 kb
Host smart-72b63e3b-41f6-477d-bafd-0dccbfbeacf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561467101 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2561467101
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3864633870
Short name T533
Test name
Test status
Simulation time 24154801 ps
CPU time 0.55 seconds
Started Jun 07 05:59:46 PM PDT 24
Finished Jun 07 05:59:47 PM PDT 24
Peak memory 182500 kb
Host smart-e5eb40d6-8fd0-4651-9fb2-282401e63cc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864633870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3864633870
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3518118697
Short name T514
Test name
Test status
Simulation time 16499371 ps
CPU time 0.55 seconds
Started Jun 07 06:03:20 PM PDT 24
Finished Jun 07 06:03:21 PM PDT 24
Peak memory 182276 kb
Host smart-2a4fd4de-c18c-4459-ad2f-978be32cecc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518118697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3518118697
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2121249697
Short name T93
Test name
Test status
Simulation time 21762911 ps
CPU time 0.73 seconds
Started Jun 07 06:02:24 PM PDT 24
Finished Jun 07 06:02:25 PM PDT 24
Peak memory 191696 kb
Host smart-e9ea0330-ff53-4f0b-9954-90c5fb9edd65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121249697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2121249697
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1420260978
Short name T531
Test name
Test status
Simulation time 96565741 ps
CPU time 2.34 seconds
Started Jun 07 06:01:27 PM PDT 24
Finished Jun 07 06:01:30 PM PDT 24
Peak memory 197392 kb
Host smart-fde35e5c-9d89-4e37-825b-a6795e09f533
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420260978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1420260978
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1625668667
Short name T30
Test name
Test status
Simulation time 152564987 ps
CPU time 0.85 seconds
Started Jun 07 06:03:38 PM PDT 24
Finished Jun 07 06:03:40 PM PDT 24
Peak memory 192264 kb
Host smart-0e87e5ef-cfb4-4c0c-a9ef-c1d61e76ac9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625668667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1625668667
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.132590544
Short name T487
Test name
Test status
Simulation time 94587118 ps
CPU time 1.48 seconds
Started Jun 07 06:03:19 PM PDT 24
Finished Jun 07 06:03:21 PM PDT 24
Peak memory 197084 kb
Host smart-419c1ed8-ea2c-4b60-a8f3-bc23ab19b92f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132590544 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.132590544
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3646413873
Short name T520
Test name
Test status
Simulation time 16420653 ps
CPU time 0.61 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 05:59:50 PM PDT 24
Peak memory 182496 kb
Host smart-0aa48aed-15f9-4e1d-b2e6-348e052f209a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646413873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3646413873
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1425362248
Short name T507
Test name
Test status
Simulation time 13158090 ps
CPU time 0.54 seconds
Started Jun 07 06:03:53 PM PDT 24
Finished Jun 07 06:03:54 PM PDT 24
Peak memory 181972 kb
Host smart-c650fe76-b945-40e5-b84d-7b114b7498fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425362248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1425362248
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4064872167
Short name T574
Test name
Test status
Simulation time 13479951 ps
CPU time 0.62 seconds
Started Jun 07 06:01:35 PM PDT 24
Finished Jun 07 06:01:36 PM PDT 24
Peak memory 191360 kb
Host smart-fcc62f4d-28d2-435e-aa4b-bd8b9edf0e3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064872167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.4064872167
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1474988082
Short name T479
Test name
Test status
Simulation time 73158621 ps
CPU time 1.06 seconds
Started Jun 07 06:04:05 PM PDT 24
Finished Jun 07 06:04:07 PM PDT 24
Peak memory 197372 kb
Host smart-1c5b2477-7244-4368-a2fe-5ddfff437f6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474988082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1474988082
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3486461058
Short name T100
Test name
Test status
Simulation time 44719525 ps
CPU time 0.86 seconds
Started Jun 07 06:01:33 PM PDT 24
Finished Jun 07 06:01:34 PM PDT 24
Peak memory 182976 kb
Host smart-6f6dd4e6-11ba-4b81-a174-541c9708d96b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486461058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3486461058
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1384472467
Short name T74
Test name
Test status
Simulation time 22313606 ps
CPU time 0.63 seconds
Started Jun 07 06:00:06 PM PDT 24
Finished Jun 07 06:00:07 PM PDT 24
Peak memory 192748 kb
Host smart-e32ab037-72fe-443b-9b0d-e0f64bb53c11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384472467 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1384472467
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3646937190
Short name T526
Test name
Test status
Simulation time 27206075 ps
CPU time 0.59 seconds
Started Jun 07 06:00:02 PM PDT 24
Finished Jun 07 06:00:03 PM PDT 24
Peak memory 182400 kb
Host smart-92f1a6be-9728-4c0f-83ac-23119a118c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646937190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3646937190
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.837762468
Short name T53
Test name
Test status
Simulation time 35565252 ps
CPU time 0.74 seconds
Started Jun 07 06:00:04 PM PDT 24
Finished Jun 07 06:00:05 PM PDT 24
Peak memory 193052 kb
Host smart-4eda3fe7-66b4-4907-9dd3-47267019824f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837762468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.837762468
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.464367248
Short name T564
Test name
Test status
Simulation time 34331863 ps
CPU time 1.66 seconds
Started Jun 07 06:03:47 PM PDT 24
Finished Jun 07 06:03:49 PM PDT 24
Peak memory 197196 kb
Host smart-f9df272c-3201-422f-85ea-0ecceadddb3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464367248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.464367248
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3163844620
Short name T521
Test name
Test status
Simulation time 115423299 ps
CPU time 1.33 seconds
Started Jun 07 06:03:16 PM PDT 24
Finished Jun 07 06:03:19 PM PDT 24
Peak memory 194960 kb
Host smart-f8c1073c-ce20-4ea8-8a60-e5594b054b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163844620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3163844620
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1711551689
Short name T502
Test name
Test status
Simulation time 44712354 ps
CPU time 1.04 seconds
Started Jun 07 06:00:06 PM PDT 24
Finished Jun 07 06:00:07 PM PDT 24
Peak memory 197228 kb
Host smart-a7426baa-35e3-458a-bd20-988af19409dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711551689 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1711551689
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.467557453
Short name T467
Test name
Test status
Simulation time 12669174 ps
CPU time 0.59 seconds
Started Jun 07 06:03:23 PM PDT 24
Finished Jun 07 06:03:26 PM PDT 24
Peak memory 179948 kb
Host smart-9c8f2ca1-028a-440c-b3d7-5f294ec6bb9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467557453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.467557453
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3681849568
Short name T489
Test name
Test status
Simulation time 62110637 ps
CPU time 0.56 seconds
Started Jun 07 06:00:06 PM PDT 24
Finished Jun 07 06:00:07 PM PDT 24
Peak memory 182468 kb
Host smart-5288e6ee-550c-4163-9b12-f8dcbfa39a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681849568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3681849568
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3635669043
Short name T90
Test name
Test status
Simulation time 19143152 ps
CPU time 0.74 seconds
Started Jun 07 06:04:16 PM PDT 24
Finished Jun 07 06:04:18 PM PDT 24
Peak memory 193320 kb
Host smart-efb0fcb7-bb5b-49af-b450-93e49f7df141
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635669043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3635669043
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3742871416
Short name T575
Test name
Test status
Simulation time 72049928 ps
CPU time 1.43 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:04:11 PM PDT 24
Peak memory 197384 kb
Host smart-ea6ed92f-8ea9-41bf-8e2b-cb00a5745dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742871416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3742871416
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2022867682
Short name T517
Test name
Test status
Simulation time 267622512 ps
CPU time 1.03 seconds
Started Jun 07 06:03:24 PM PDT 24
Finished Jun 07 06:03:26 PM PDT 24
Peak memory 193160 kb
Host smart-d30ffc56-8d67-4de4-a76b-6435534e6fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022867682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2022867682
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1805055828
Short name T493
Test name
Test status
Simulation time 23101482 ps
CPU time 0.72 seconds
Started Jun 07 06:00:09 PM PDT 24
Finished Jun 07 06:00:10 PM PDT 24
Peak memory 194396 kb
Host smart-800d0151-5fad-4881-a4cc-e0897b25bea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805055828 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1805055828
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1696780064
Short name T76
Test name
Test status
Simulation time 14901092 ps
CPU time 0.56 seconds
Started Jun 07 06:04:16 PM PDT 24
Finished Jun 07 06:04:17 PM PDT 24
Peak memory 181504 kb
Host smart-f3f8a257-4578-4e98-aaf9-4175f7daf8ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696780064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1696780064
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1796775047
Short name T486
Test name
Test status
Simulation time 19751002 ps
CPU time 0.57 seconds
Started Jun 07 06:03:16 PM PDT 24
Finished Jun 07 06:03:17 PM PDT 24
Peak memory 181664 kb
Host smart-940606db-8138-45f6-add3-6a7ccacd2ecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796775047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1796775047
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3587477847
Short name T580
Test name
Test status
Simulation time 30869056 ps
CPU time 0.76 seconds
Started Jun 07 06:00:05 PM PDT 24
Finished Jun 07 06:00:06 PM PDT 24
Peak memory 193448 kb
Host smart-75d5f4f9-458f-45b0-8716-3c8c0baeff96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587477847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3587477847
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1082232060
Short name T55
Test name
Test status
Simulation time 170482778 ps
CPU time 1.64 seconds
Started Jun 07 06:03:23 PM PDT 24
Finished Jun 07 06:03:27 PM PDT 24
Peak memory 195296 kb
Host smart-707dfb78-841b-44ce-b5af-335e2b66d58e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082232060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1082232060
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3782083470
Short name T96
Test name
Test status
Simulation time 292445786 ps
CPU time 0.87 seconds
Started Jun 07 06:02:04 PM PDT 24
Finished Jun 07 06:02:05 PM PDT 24
Peak memory 193384 kb
Host smart-01afa446-2463-43a8-a75a-8549b768a728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782083470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3782083470
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3133379941
Short name T536
Test name
Test status
Simulation time 117900212 ps
CPU time 1.26 seconds
Started Jun 07 06:00:37 PM PDT 24
Finished Jun 07 06:00:39 PM PDT 24
Peak memory 197396 kb
Host smart-c5937da7-de50-40be-8b53-394243a2e47d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133379941 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3133379941
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3772346151
Short name T500
Test name
Test status
Simulation time 83965252 ps
CPU time 0.62 seconds
Started Jun 07 06:00:03 PM PDT 24
Finished Jun 07 06:00:04 PM PDT 24
Peak memory 182552 kb
Host smart-85d8d076-dcb8-4c9f-8776-e9994ee6f36d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772346151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3772346151
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2025774616
Short name T477
Test name
Test status
Simulation time 14761510 ps
CPU time 0.56 seconds
Started Jun 07 06:03:46 PM PDT 24
Finished Jun 07 06:03:47 PM PDT 24
Peak memory 181640 kb
Host smart-9b094bb3-5963-4b15-a323-0cdbab7f8f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025774616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2025774616
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2008476838
Short name T577
Test name
Test status
Simulation time 38220400 ps
CPU time 0.76 seconds
Started Jun 07 06:00:37 PM PDT 24
Finished Jun 07 06:00:38 PM PDT 24
Peak memory 193300 kb
Host smart-21d6e4f5-fa0c-405d-b7b3-17a5659c43d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008476838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2008476838
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.956700073
Short name T556
Test name
Test status
Simulation time 137064066 ps
CPU time 2.64 seconds
Started Jun 07 06:01:46 PM PDT 24
Finished Jun 07 06:01:48 PM PDT 24
Peak memory 197420 kb
Host smart-6ff60533-8993-4132-b220-b42d3c07a478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956700073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.956700073
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1227166433
Short name T540
Test name
Test status
Simulation time 105569205 ps
CPU time 1.3 seconds
Started Jun 07 06:00:25 PM PDT 24
Finished Jun 07 06:00:27 PM PDT 24
Peak memory 195272 kb
Host smart-13ba142b-2d92-4c76-9f7b-4568f063365b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227166433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1227166433
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2986236840
Short name T542
Test name
Test status
Simulation time 75491249 ps
CPU time 0.76 seconds
Started Jun 07 06:03:36 PM PDT 24
Finished Jun 07 06:03:37 PM PDT 24
Peak memory 194984 kb
Host smart-6db99503-9b6c-4f00-add3-2c4dc044c0c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986236840 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2986236840
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2940578297
Short name T80
Test name
Test status
Simulation time 14484191 ps
CPU time 0.56 seconds
Started Jun 07 06:03:31 PM PDT 24
Finished Jun 07 06:03:32 PM PDT 24
Peak memory 182504 kb
Host smart-ae05d5f3-280e-4f2e-a547-11d99177a56a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940578297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2940578297
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4170400199
Short name T568
Test name
Test status
Simulation time 37044608 ps
CPU time 0.57 seconds
Started Jun 07 06:03:24 PM PDT 24
Finished Jun 07 06:03:25 PM PDT 24
Peak memory 180216 kb
Host smart-a4803de8-6151-4d82-859f-12bea239747d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170400199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4170400199
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.799068217
Short name T91
Test name
Test status
Simulation time 22804458 ps
CPU time 0.73 seconds
Started Jun 07 06:00:21 PM PDT 24
Finished Jun 07 06:00:22 PM PDT 24
Peak memory 192132 kb
Host smart-6b0eaacd-ead8-4be2-9d94-17ce1acee3d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799068217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.799068217
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2561009814
Short name T462
Test name
Test status
Simulation time 105856688 ps
CPU time 2.67 seconds
Started Jun 07 06:00:14 PM PDT 24
Finished Jun 07 06:00:17 PM PDT 24
Peak memory 197560 kb
Host smart-bd2c0190-248a-4666-97d6-99fb072d3d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561009814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2561009814
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.963317821
Short name T516
Test name
Test status
Simulation time 81960662 ps
CPU time 1.04 seconds
Started Jun 07 06:03:24 PM PDT 24
Finished Jun 07 06:03:26 PM PDT 24
Peak memory 194620 kb
Host smart-73e2dbcc-630a-4271-b53c-3e851607cb9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963317821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.963317821
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2753415002
Short name T85
Test name
Test status
Simulation time 204410569 ps
CPU time 0.78 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:04:07 PM PDT 24
Peak memory 182440 kb
Host smart-d2b7386e-fd27-4c45-ac98-1d03aee29eb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753415002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2753415002
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2582570655
Short name T94
Test name
Test status
Simulation time 194452185 ps
CPU time 2.62 seconds
Started Jun 07 06:02:15 PM PDT 24
Finished Jun 07 06:02:18 PM PDT 24
Peak memory 190944 kb
Host smart-6e65389f-40a8-4a5e-9b8f-f1c4d32c1ee6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582570655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2582570655
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.272075094
Short name T460
Test name
Test status
Simulation time 31993669 ps
CPU time 0.62 seconds
Started Jun 07 06:00:24 PM PDT 24
Finished Jun 07 06:00:25 PM PDT 24
Peak memory 182872 kb
Host smart-40d8a33b-dbbb-4ae3-b2c2-c39581fcd64c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272075094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.272075094
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1609783666
Short name T503
Test name
Test status
Simulation time 46701305 ps
CPU time 1.11 seconds
Started Jun 07 06:02:48 PM PDT 24
Finished Jun 07 06:02:49 PM PDT 24
Peak memory 197348 kb
Host smart-4d089926-aeee-4bf3-9937-e4508b2f4f30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609783666 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1609783666
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1915502368
Short name T77
Test name
Test status
Simulation time 30941010 ps
CPU time 0.59 seconds
Started Jun 07 06:03:51 PM PDT 24
Finished Jun 07 06:03:52 PM PDT 24
Peak memory 180308 kb
Host smart-aaf6ab1e-0e78-4ad6-84f6-2752a09fff4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915502368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1915502368
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1640885138
Short name T469
Test name
Test status
Simulation time 72552683 ps
CPU time 0.53 seconds
Started Jun 07 06:04:10 PM PDT 24
Finished Jun 07 06:04:11 PM PDT 24
Peak memory 182104 kb
Host smart-4393a871-e5b0-47f5-8d48-c35814ce4bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640885138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1640885138
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1556020198
Short name T89
Test name
Test status
Simulation time 39719490 ps
CPU time 0.65 seconds
Started Jun 07 06:01:02 PM PDT 24
Finished Jun 07 06:01:03 PM PDT 24
Peak memory 191936 kb
Host smart-e24acb4d-fe0c-4a2c-953c-a14f5b882c66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556020198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1556020198
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4097841588
Short name T545
Test name
Test status
Simulation time 285392469 ps
CPU time 1.8 seconds
Started Jun 07 05:59:49 PM PDT 24
Finished Jun 07 05:59:52 PM PDT 24
Peak memory 195904 kb
Host smart-8a1eea06-44c9-4079-830c-9f7fe41b5632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097841588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4097841588
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1133755257
Short name T524
Test name
Test status
Simulation time 28563478 ps
CPU time 0.58 seconds
Started Jun 07 06:03:24 PM PDT 24
Finished Jun 07 06:03:25 PM PDT 24
Peak memory 180844 kb
Host smart-20117028-a48e-4981-b2e1-8bc2d5eec32b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133755257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1133755257
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1759302541
Short name T525
Test name
Test status
Simulation time 19301365 ps
CPU time 0.59 seconds
Started Jun 07 06:00:19 PM PDT 24
Finished Jun 07 06:00:20 PM PDT 24
Peak memory 182428 kb
Host smart-6d37460a-52b4-43e9-8ac1-6d477d5e0786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759302541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1759302541
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.548230029
Short name T550
Test name
Test status
Simulation time 18253121 ps
CPU time 0.56 seconds
Started Jun 07 06:03:35 PM PDT 24
Finished Jun 07 06:03:36 PM PDT 24
Peak memory 182468 kb
Host smart-738926f5-c65c-4dbd-9dc6-c8fdd4ef4384
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548230029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.548230029
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3475657562
Short name T478
Test name
Test status
Simulation time 17219841 ps
CPU time 0.57 seconds
Started Jun 07 06:03:36 PM PDT 24
Finished Jun 07 06:03:37 PM PDT 24
Peak memory 182416 kb
Host smart-103657e8-f103-438d-ad9e-f625cf30bc7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475657562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3475657562
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2138716753
Short name T459
Test name
Test status
Simulation time 24062140 ps
CPU time 0.56 seconds
Started Jun 07 06:00:32 PM PDT 24
Finished Jun 07 06:00:33 PM PDT 24
Peak memory 182460 kb
Host smart-db81a828-bd77-495f-a7ab-f02c26efffe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138716753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2138716753
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1704355922
Short name T551
Test name
Test status
Simulation time 73351518 ps
CPU time 0.53 seconds
Started Jun 07 06:01:00 PM PDT 24
Finished Jun 07 06:01:01 PM PDT 24
Peak memory 181852 kb
Host smart-c5502ffc-2653-47e4-bb69-fad9cd2a9966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704355922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1704355922
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.85782537
Short name T515
Test name
Test status
Simulation time 22372379 ps
CPU time 0.57 seconds
Started Jun 07 06:01:27 PM PDT 24
Finished Jun 07 06:01:28 PM PDT 24
Peak memory 182212 kb
Host smart-425e4721-e767-48f9-b2c1-88dae1905e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85782537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.85782537
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1147704638
Short name T565
Test name
Test status
Simulation time 42555700 ps
CPU time 0.58 seconds
Started Jun 07 06:00:22 PM PDT 24
Finished Jun 07 06:00:22 PM PDT 24
Peak memory 182036 kb
Host smart-f6bd3303-97d8-4d51-9fdc-40d2927d3ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147704638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1147704638
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2945328592
Short name T547
Test name
Test status
Simulation time 37655663 ps
CPU time 0.52 seconds
Started Jun 07 06:00:43 PM PDT 24
Finished Jun 07 06:00:44 PM PDT 24
Peak memory 181868 kb
Host smart-1c6ff94b-eaa8-43cc-b3e2-378b182049cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945328592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2945328592
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3615319470
Short name T512
Test name
Test status
Simulation time 37991077 ps
CPU time 0.55 seconds
Started Jun 07 06:00:26 PM PDT 24
Finished Jun 07 06:00:27 PM PDT 24
Peak memory 182404 kb
Host smart-3aabfc69-2bdd-473c-85de-26960b3b6c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615319470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3615319470
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.821987893
Short name T83
Test name
Test status
Simulation time 41752877 ps
CPU time 0.82 seconds
Started Jun 07 06:03:53 PM PDT 24
Finished Jun 07 06:03:54 PM PDT 24
Peak memory 191516 kb
Host smart-1856a739-126c-47c5-9d95-18dab370349d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821987893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.821987893
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2519276925
Short name T488
Test name
Test status
Simulation time 625318399 ps
CPU time 3.33 seconds
Started Jun 07 06:02:46 PM PDT 24
Finished Jun 07 06:02:49 PM PDT 24
Peak memory 190944 kb
Host smart-259662cc-e566-480b-a214-6dc5d6cae152
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519276925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2519276925
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1396060018
Short name T508
Test name
Test status
Simulation time 85114011 ps
CPU time 0.56 seconds
Started Jun 07 06:02:16 PM PDT 24
Finished Jun 07 06:02:17 PM PDT 24
Peak memory 182508 kb
Host smart-6c0d6435-324d-4e24-9c46-2f1ef0c44203
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396060018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1396060018
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1740417587
Short name T504
Test name
Test status
Simulation time 166976248 ps
CPU time 0.96 seconds
Started Jun 07 06:03:51 PM PDT 24
Finished Jun 07 06:03:52 PM PDT 24
Peak memory 195176 kb
Host smart-58da5ed7-6ac6-4ff8-b511-73ca996f0974
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740417587 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1740417587
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3740950698
Short name T75
Test name
Test status
Simulation time 24600657 ps
CPU time 0.56 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:04:10 PM PDT 24
Peak memory 182508 kb
Host smart-21e65d20-ee05-47ce-b613-5aa3f546de45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740950698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3740950698
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2195817031
Short name T558
Test name
Test status
Simulation time 44289874 ps
CPU time 0.52 seconds
Started Jun 07 06:01:35 PM PDT 24
Finished Jun 07 06:01:36 PM PDT 24
Peak memory 182104 kb
Host smart-2c412c96-ac04-4053-8922-751a886f2fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195817031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2195817031
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4165952521
Short name T553
Test name
Test status
Simulation time 35609146 ps
CPU time 0.8 seconds
Started Jun 07 06:03:51 PM PDT 24
Finished Jun 07 06:03:53 PM PDT 24
Peak memory 192960 kb
Host smart-4fe63dc7-d7e9-4004-bc20-3188d23a8e16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165952521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4165952521
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.4262865725
Short name T463
Test name
Test status
Simulation time 86623042 ps
CPU time 1.89 seconds
Started Jun 07 06:00:19 PM PDT 24
Finished Jun 07 06:00:21 PM PDT 24
Peak memory 197364 kb
Host smart-546eb007-5f87-4aff-96c2-41d414936734
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262865725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4262865725
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.4079192487
Short name T29
Test name
Test status
Simulation time 645690826 ps
CPU time 1.42 seconds
Started Jun 07 06:02:48 PM PDT 24
Finished Jun 07 06:02:50 PM PDT 24
Peak memory 195512 kb
Host smart-fa90253a-4a33-46c2-b30e-25460d832504
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079192487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.4079192487
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1308123319
Short name T548
Test name
Test status
Simulation time 47218085 ps
CPU time 0.55 seconds
Started Jun 07 06:03:20 PM PDT 24
Finished Jun 07 06:03:21 PM PDT 24
Peak memory 182348 kb
Host smart-6c67c3b9-8bc6-4966-9ee1-588ccb8453ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308123319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1308123319
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1099837648
Short name T501
Test name
Test status
Simulation time 102608671 ps
CPU time 0.58 seconds
Started Jun 07 06:00:40 PM PDT 24
Finished Jun 07 06:00:41 PM PDT 24
Peak memory 182400 kb
Host smart-e2d3fdfb-3dc0-4407-82ff-91563d793474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099837648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1099837648
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3085746321
Short name T518
Test name
Test status
Simulation time 12271641 ps
CPU time 0.56 seconds
Started Jun 07 06:03:19 PM PDT 24
Finished Jun 07 06:03:20 PM PDT 24
Peak memory 181052 kb
Host smart-5c7b1d4e-d5bc-4c49-a809-72473590e009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085746321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3085746321
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3384237566
Short name T491
Test name
Test status
Simulation time 18347501 ps
CPU time 0.55 seconds
Started Jun 07 06:01:08 PM PDT 24
Finished Jun 07 06:01:09 PM PDT 24
Peak memory 182200 kb
Host smart-4c72322a-8c73-4dfa-a79f-f6b759e464fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384237566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3384237566
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3178650702
Short name T483
Test name
Test status
Simulation time 13886201 ps
CPU time 0.53 seconds
Started Jun 07 06:03:23 PM PDT 24
Finished Jun 07 06:03:24 PM PDT 24
Peak memory 182332 kb
Host smart-39b9f97a-a0dd-4ee5-a7e7-221e81914606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178650702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3178650702
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2327631294
Short name T461
Test name
Test status
Simulation time 63495288 ps
CPU time 0.56 seconds
Started Jun 07 06:03:21 PM PDT 24
Finished Jun 07 06:03:23 PM PDT 24
Peak memory 180716 kb
Host smart-64ea5518-efe7-4373-a97c-7c627344dc45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327631294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2327631294
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1851146538
Short name T495
Test name
Test status
Simulation time 45107396 ps
CPU time 0.54 seconds
Started Jun 07 06:03:23 PM PDT 24
Finished Jun 07 06:03:24 PM PDT 24
Peak memory 182368 kb
Host smart-3d6019a0-500c-4936-9b8f-a02a2d52b7c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851146538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1851146538
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2507878752
Short name T546
Test name
Test status
Simulation time 43840587 ps
CPU time 0.55 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:04:07 PM PDT 24
Peak memory 182016 kb
Host smart-0a877e96-df91-44a2-bd01-38a21cd824cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507878752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2507878752
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3190046941
Short name T484
Test name
Test status
Simulation time 20108894 ps
CPU time 0.61 seconds
Started Jun 07 06:03:21 PM PDT 24
Finished Jun 07 06:03:23 PM PDT 24
Peak memory 181340 kb
Host smart-1d806397-fcae-43a0-857d-bdef25e6ce9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190046941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3190046941
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1649719140
Short name T554
Test name
Test status
Simulation time 22100757 ps
CPU time 0.57 seconds
Started Jun 07 06:01:23 PM PDT 24
Finished Jun 07 06:01:24 PM PDT 24
Peak memory 181852 kb
Host smart-a4e7200b-cc59-482e-911a-f2d0ab3c8a70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649719140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1649719140
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.363437018
Short name T84
Test name
Test status
Simulation time 32142205 ps
CPU time 0.84 seconds
Started Jun 07 06:03:56 PM PDT 24
Finished Jun 07 06:03:58 PM PDT 24
Peak memory 192444 kb
Host smart-ac54578f-7162-421d-b7d5-f4bd1793e2d2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363437018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.363437018
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3907410321
Short name T570
Test name
Test status
Simulation time 1131858383 ps
CPU time 2.53 seconds
Started Jun 07 06:04:24 PM PDT 24
Finished Jun 07 06:04:27 PM PDT 24
Peak memory 190940 kb
Host smart-354612b4-5076-400d-ae1e-5bbc56406a30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907410321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3907410321
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2444247713
Short name T541
Test name
Test status
Simulation time 51964864 ps
CPU time 0.56 seconds
Started Jun 07 06:04:23 PM PDT 24
Finished Jun 07 06:04:24 PM PDT 24
Peak memory 182528 kb
Host smart-fea5e18f-2c61-4a79-b4a7-153bbbcfba2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444247713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2444247713
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3115524815
Short name T51
Test name
Test status
Simulation time 112990737 ps
CPU time 0.7 seconds
Started Jun 07 06:02:46 PM PDT 24
Finished Jun 07 06:02:47 PM PDT 24
Peak memory 194084 kb
Host smart-96e6ea4d-2e18-4785-94be-a989de42d64d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115524815 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3115524815
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2647673234
Short name T52
Test name
Test status
Simulation time 28786547 ps
CPU time 0.51 seconds
Started Jun 07 06:04:25 PM PDT 24
Finished Jun 07 06:04:26 PM PDT 24
Peak memory 182252 kb
Host smart-c7d2102c-f678-4847-8f8d-250abf22b103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647673234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2647673234
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.4283569657
Short name T497
Test name
Test status
Simulation time 24780666 ps
CPU time 0.54 seconds
Started Jun 07 06:03:55 PM PDT 24
Finished Jun 07 06:03:56 PM PDT 24
Peak memory 181788 kb
Host smart-3a5193e0-dbf1-46f8-a727-f53ec1e49d80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283569657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.4283569657
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.516410120
Short name T562
Test name
Test status
Simulation time 59653540 ps
CPU time 0.72 seconds
Started Jun 07 06:00:34 PM PDT 24
Finished Jun 07 06:00:35 PM PDT 24
Peak memory 191532 kb
Host smart-2b3bc861-e8ca-404a-8d57-28470230d202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516410120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.516410120
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.218095840
Short name T578
Test name
Test status
Simulation time 416617831 ps
CPU time 3.15 seconds
Started Jun 07 06:04:09 PM PDT 24
Finished Jun 07 06:04:13 PM PDT 24
Peak memory 197432 kb
Host smart-e270da8d-0bf0-4590-b676-a3af84987c96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218095840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.218095840
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4138433997
Short name T534
Test name
Test status
Simulation time 233875491 ps
CPU time 0.8 seconds
Started Jun 07 06:04:23 PM PDT 24
Finished Jun 07 06:04:24 PM PDT 24
Peak memory 182856 kb
Host smart-94754f96-cf12-4efd-849c-c230b09d0c03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138433997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4138433997
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1753320695
Short name T567
Test name
Test status
Simulation time 35141193 ps
CPU time 0.61 seconds
Started Jun 07 06:03:51 PM PDT 24
Finished Jun 07 06:03:52 PM PDT 24
Peak memory 180520 kb
Host smart-7e220ec9-fa96-4ccc-9af6-3ec913f95e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753320695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1753320695
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.42045109
Short name T466
Test name
Test status
Simulation time 10674737 ps
CPU time 0.56 seconds
Started Jun 07 06:04:00 PM PDT 24
Finished Jun 07 06:04:01 PM PDT 24
Peak memory 181072 kb
Host smart-98988e10-10e7-4024-a218-284313989055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42045109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.42045109
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3424649150
Short name T535
Test name
Test status
Simulation time 23933939 ps
CPU time 0.59 seconds
Started Jun 07 06:03:17 PM PDT 24
Finished Jun 07 06:03:19 PM PDT 24
Peak memory 180876 kb
Host smart-ce52d2e9-3cae-4f40-87cd-1be6284817bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424649150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3424649150
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4217140817
Short name T519
Test name
Test status
Simulation time 49146616 ps
CPU time 0.53 seconds
Started Jun 07 06:04:01 PM PDT 24
Finished Jun 07 06:04:02 PM PDT 24
Peak memory 182136 kb
Host smart-b56307bd-8bbe-4c8e-a52d-cd067d837833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217140817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4217140817
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3805044888
Short name T473
Test name
Test status
Simulation time 21438770 ps
CPU time 0.56 seconds
Started Jun 07 06:01:22 PM PDT 24
Finished Jun 07 06:01:23 PM PDT 24
Peak memory 182056 kb
Host smart-a130aebd-7a15-4243-afc3-0afdcccc2417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805044888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3805044888
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2985574088
Short name T529
Test name
Test status
Simulation time 41203504 ps
CPU time 0.51 seconds
Started Jun 07 06:04:00 PM PDT 24
Finished Jun 07 06:04:01 PM PDT 24
Peak memory 181864 kb
Host smart-b5cbc5dc-dbc1-46fd-8fa0-5ae17d422eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985574088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2985574088
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1917526036
Short name T485
Test name
Test status
Simulation time 23681302 ps
CPU time 0.51 seconds
Started Jun 07 06:04:01 PM PDT 24
Finished Jun 07 06:04:02 PM PDT 24
Peak memory 181640 kb
Host smart-848a8961-df2a-4976-9202-d69880f40eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917526036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1917526036
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3326761625
Short name T498
Test name
Test status
Simulation time 37442076 ps
CPU time 0.52 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:04:06 PM PDT 24
Peak memory 181772 kb
Host smart-d4dfb1a3-7a08-4588-930d-099245925f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326761625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3326761625
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4096465911
Short name T538
Test name
Test status
Simulation time 41982952 ps
CPU time 0.56 seconds
Started Jun 07 06:01:33 PM PDT 24
Finished Jun 07 06:01:34 PM PDT 24
Peak memory 182384 kb
Host smart-94734425-0dd4-4f31-8f94-49aa605d7acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096465911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4096465911
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1335006210
Short name T475
Test name
Test status
Simulation time 48031110 ps
CPU time 0.62 seconds
Started Jun 07 06:03:51 PM PDT 24
Finished Jun 07 06:03:52 PM PDT 24
Peak memory 180300 kb
Host smart-bb03dbd0-3ec0-4273-84a4-c29dce11cfbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335006210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1335006210
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2277978082
Short name T480
Test name
Test status
Simulation time 34971409 ps
CPU time 0.65 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:04:07 PM PDT 24
Peak memory 192556 kb
Host smart-6f7ea867-74eb-44b0-a35b-6a1ce8d1871e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277978082 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2277978082
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3757418304
Short name T527
Test name
Test status
Simulation time 32064814 ps
CPU time 0.54 seconds
Started Jun 07 05:59:18 PM PDT 24
Finished Jun 07 05:59:19 PM PDT 24
Peak memory 182196 kb
Host smart-a38acf9e-0104-4948-8bda-4bcaac73e7f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757418304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3757418304
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1366604123
Short name T510
Test name
Test status
Simulation time 29508953 ps
CPU time 0.55 seconds
Started Jun 07 06:02:39 PM PDT 24
Finished Jun 07 06:02:40 PM PDT 24
Peak memory 181840 kb
Host smart-7aa36117-4839-4ed8-abb3-7754c4cd54e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366604123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1366604123
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3829079761
Short name T66
Test name
Test status
Simulation time 21981109 ps
CPU time 0.61 seconds
Started Jun 07 06:04:23 PM PDT 24
Finished Jun 07 06:04:24 PM PDT 24
Peak memory 191892 kb
Host smart-151c3c4a-884a-46a4-9b31-ca99c3aac662
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829079761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3829079761
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4067816622
Short name T569
Test name
Test status
Simulation time 301302536 ps
CPU time 2.3 seconds
Started Jun 07 06:04:10 PM PDT 24
Finished Jun 07 06:04:13 PM PDT 24
Peak memory 197444 kb
Host smart-87500ff5-ab14-41b7-8082-a430ac3c8d32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067816622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4067816622
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1044998129
Short name T98
Test name
Test status
Simulation time 117368747 ps
CPU time 1.35 seconds
Started Jun 07 05:59:24 PM PDT 24
Finished Jun 07 05:59:26 PM PDT 24
Peak memory 194936 kb
Host smart-8842e899-35e2-4e66-b055-db9f82dbb209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044998129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1044998129
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3770063274
Short name T474
Test name
Test status
Simulation time 15706382 ps
CPU time 0.68 seconds
Started Jun 07 06:00:50 PM PDT 24
Finished Jun 07 06:00:51 PM PDT 24
Peak memory 194044 kb
Host smart-5e244bee-6abd-40d6-ab59-177bf7cc461e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770063274 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3770063274
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3960678850
Short name T88
Test name
Test status
Simulation time 50262168 ps
CPU time 0.58 seconds
Started Jun 07 06:04:05 PM PDT 24
Finished Jun 07 06:04:06 PM PDT 24
Peak memory 182476 kb
Host smart-c453c385-44ef-4eed-a7c0-3b4c705f7cbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960678850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3960678850
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2892446170
Short name T543
Test name
Test status
Simulation time 12045655 ps
CPU time 0.57 seconds
Started Jun 07 06:04:00 PM PDT 24
Finished Jun 07 06:04:01 PM PDT 24
Peak memory 181184 kb
Host smart-f6a24fcc-8adf-43b6-9660-1e6bf5507730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892446170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2892446170
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.4124945891
Short name T57
Test name
Test status
Simulation time 117744219 ps
CPU time 0.73 seconds
Started Jun 07 06:04:00 PM PDT 24
Finished Jun 07 06:04:01 PM PDT 24
Peak memory 191688 kb
Host smart-5cf3c8d8-8b38-43b5-b353-41ddc8c9e128
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124945891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.4124945891
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3371994709
Short name T481
Test name
Test status
Simulation time 102125401 ps
CPU time 1.49 seconds
Started Jun 07 06:02:50 PM PDT 24
Finished Jun 07 06:02:52 PM PDT 24
Peak memory 197380 kb
Host smart-9fdb2657-29ed-4fff-823b-6e50bc24a56d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371994709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3371994709
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3184704655
Short name T552
Test name
Test status
Simulation time 74311280 ps
CPU time 0.8 seconds
Started Jun 07 06:04:24 PM PDT 24
Finished Jun 07 06:04:25 PM PDT 24
Peak memory 193524 kb
Host smart-9808f534-5fd4-4cf8-941c-83bce3c9527e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184704655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3184704655
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2121225445
Short name T31
Test name
Test status
Simulation time 70602922 ps
CPU time 0.71 seconds
Started Jun 07 06:01:02 PM PDT 24
Finished Jun 07 06:01:03 PM PDT 24
Peak memory 194208 kb
Host smart-f5fabe77-d5c2-488d-b770-de609e92b51a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121225445 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2121225445
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2104709671
Short name T509
Test name
Test status
Simulation time 10932685 ps
CPU time 0.51 seconds
Started Jun 07 06:04:06 PM PDT 24
Finished Jun 07 06:04:07 PM PDT 24
Peak memory 181776 kb
Host smart-2f3b114a-858c-47db-854c-0567f320fdd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104709671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2104709671
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3141078719
Short name T464
Test name
Test status
Simulation time 12969113 ps
CPU time 0.51 seconds
Started Jun 07 06:04:10 PM PDT 24
Finished Jun 07 06:04:11 PM PDT 24
Peak memory 181900 kb
Host smart-e33fede6-6095-45e6-98c4-6b321d4eedde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141078719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3141078719
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2238913591
Short name T557
Test name
Test status
Simulation time 84672767 ps
CPU time 0.67 seconds
Started Jun 07 06:01:36 PM PDT 24
Finished Jun 07 06:01:38 PM PDT 24
Peak memory 192064 kb
Host smart-6f6a9b8a-5912-4081-a47d-b7ba9595da17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238913591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2238913591
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4275428498
Short name T482
Test name
Test status
Simulation time 609944895 ps
CPU time 2.12 seconds
Started Jun 07 06:01:36 PM PDT 24
Finished Jun 07 06:01:39 PM PDT 24
Peak memory 197436 kb
Host smart-698a9e24-f0a6-4dab-97a8-591ca5d1d31f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275428498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4275428498
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.96705802
Short name T99
Test name
Test status
Simulation time 456162036 ps
CPU time 1.32 seconds
Started Jun 07 06:04:16 PM PDT 24
Finished Jun 07 06:04:18 PM PDT 24
Peak memory 195184 kb
Host smart-f574e6af-9c8f-4388-9c2b-6e25c4eae50b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96705802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg
_err.96705802
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.989288930
Short name T470
Test name
Test status
Simulation time 82851312 ps
CPU time 1.03 seconds
Started Jun 07 06:02:52 PM PDT 24
Finished Jun 07 06:02:53 PM PDT 24
Peak memory 196308 kb
Host smart-85c3d64f-2848-4fbd-87cf-cf7359e59216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989288930 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.989288930
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.653462159
Short name T496
Test name
Test status
Simulation time 15343800 ps
CPU time 0.61 seconds
Started Jun 07 05:59:41 PM PDT 24
Finished Jun 07 05:59:42 PM PDT 24
Peak memory 182528 kb
Host smart-bed94262-5e29-46fa-ba83-541d1520cbb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653462159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.653462159
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4150502619
Short name T572
Test name
Test status
Simulation time 22373157 ps
CPU time 0.59 seconds
Started Jun 07 06:00:20 PM PDT 24
Finished Jun 07 06:00:21 PM PDT 24
Peak memory 182504 kb
Host smart-c2f2e8db-ff68-40e0-a375-caa5037e0bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150502619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4150502619
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2893953147
Short name T576
Test name
Test status
Simulation time 14995212 ps
CPU time 0.71 seconds
Started Jun 07 06:04:08 PM PDT 24
Finished Jun 07 06:04:09 PM PDT 24
Peak memory 190728 kb
Host smart-0116f1b7-4cc2-4be7-911f-f07e5d41ead2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893953147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2893953147
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3611469723
Short name T471
Test name
Test status
Simulation time 261810639 ps
CPU time 2.41 seconds
Started Jun 07 06:02:05 PM PDT 24
Finished Jun 07 06:02:08 PM PDT 24
Peak memory 197448 kb
Host smart-db462856-6f04-46ff-be71-3dd75cb8232d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611469723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3611469723
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.518551343
Short name T573
Test name
Test status
Simulation time 136131989 ps
CPU time 1.39 seconds
Started Jun 07 06:01:55 PM PDT 24
Finished Jun 07 06:01:57 PM PDT 24
Peak memory 195244 kb
Host smart-53a0433f-e5b1-43d2-b3a3-47c9857417fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518551343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.518551343
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.209662623
Short name T32
Test name
Test status
Simulation time 34507481 ps
CPU time 0.94 seconds
Started Jun 07 06:01:09 PM PDT 24
Finished Jun 07 06:01:11 PM PDT 24
Peak memory 196908 kb
Host smart-13dc1bd1-cd8c-460d-b925-da91b43c95dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209662623 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.209662623
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3124558748
Short name T86
Test name
Test status
Simulation time 13595666 ps
CPU time 0.59 seconds
Started Jun 07 06:01:15 PM PDT 24
Finished Jun 07 06:01:16 PM PDT 24
Peak memory 182496 kb
Host smart-c3b89f8f-29c7-4deb-9059-6de0208afbe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124558748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3124558748
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.436714314
Short name T468
Test name
Test status
Simulation time 13504937 ps
CPU time 0.56 seconds
Started Jun 07 06:01:47 PM PDT 24
Finished Jun 07 06:01:47 PM PDT 24
Peak memory 182456 kb
Host smart-b611296e-f5a5-471b-bd0a-39b84a16a95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436714314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.436714314
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2216934532
Short name T506
Test name
Test status
Simulation time 39194182 ps
CPU time 0.84 seconds
Started Jun 07 06:03:19 PM PDT 24
Finished Jun 07 06:03:21 PM PDT 24
Peak memory 189956 kb
Host smart-5acb4f51-a13d-495d-82df-6697415d1008
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216934532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2216934532
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1451079093
Short name T490
Test name
Test status
Simulation time 23415419 ps
CPU time 1.2 seconds
Started Jun 07 06:00:43 PM PDT 24
Finished Jun 07 06:00:44 PM PDT 24
Peak memory 197444 kb
Host smart-5a888ac5-aa3f-4fcf-8039-b9794a6e96d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451079093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1451079093
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3093267371
Short name T67
Test name
Test status
Simulation time 84233501 ps
CPU time 1.03 seconds
Started Jun 07 06:03:20 PM PDT 24
Finished Jun 07 06:03:22 PM PDT 24
Peak memory 194452 kb
Host smart-fb69830b-a6fd-4859-86e3-31e294ccde87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093267371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3093267371
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1115534055
Short name T185
Test name
Test status
Simulation time 83385622982 ps
CPU time 129.22 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:18:58 PM PDT 24
Peak memory 182876 kb
Host smart-78984221-6848-4538-8c06-e425f99c4009
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115534055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1115534055
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2230703667
Short name T379
Test name
Test status
Simulation time 63642358133 ps
CPU time 105.5 seconds
Started Jun 07 06:16:21 PM PDT 24
Finished Jun 07 06:18:08 PM PDT 24
Peak memory 182868 kb
Host smart-28d15518-c9c6-4f8c-a5e6-c670f8fb1140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230703667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2230703667
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1509037153
Short name T361
Test name
Test status
Simulation time 7667124260 ps
CPU time 13.25 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:17:03 PM PDT 24
Peak memory 183156 kb
Host smart-e1791a2a-4c61-40ac-8657-37413c70f078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509037153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1509037153
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3415194333
Short name T253
Test name
Test status
Simulation time 450921175196 ps
CPU time 428.12 seconds
Started Jun 07 06:16:41 PM PDT 24
Finished Jun 07 06:23:50 PM PDT 24
Peak memory 183148 kb
Host smart-fad63921-5e73-45b9-a922-46df840bd423
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415194333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3415194333
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3189330714
Short name T378
Test name
Test status
Simulation time 89007128016 ps
CPU time 137.27 seconds
Started Jun 07 06:16:47 PM PDT 24
Finished Jun 07 06:19:05 PM PDT 24
Peak memory 182920 kb
Host smart-2bdd0da2-ae3e-4d37-a668-17c38da61f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189330714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3189330714
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2538304125
Short name T16
Test name
Test status
Simulation time 220132663 ps
CPU time 0.8 seconds
Started Jun 07 06:16:33 PM PDT 24
Finished Jun 07 06:16:34 PM PDT 24
Peak memory 213424 kb
Host smart-80127a87-d102-47df-92f0-d8abbca6e84c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538304125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2538304125
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.367274642
Short name T389
Test name
Test status
Simulation time 116325240971 ps
CPU time 183.79 seconds
Started Jun 07 06:16:47 PM PDT 24
Finished Jun 07 06:19:52 PM PDT 24
Peak memory 182960 kb
Host smart-ac3d0b62-0402-4ada-b570-ca4fda93e3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367274642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.367274642
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.780729503
Short name T301
Test name
Test status
Simulation time 99316662678 ps
CPU time 665.27 seconds
Started Jun 07 06:16:50 PM PDT 24
Finished Jun 07 06:27:56 PM PDT 24
Peak memory 191184 kb
Host smart-6b7ac67d-ce88-4a50-9ebe-d74803d359fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780729503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.780729503
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.1579455626
Short name T209
Test name
Test status
Simulation time 128577894658 ps
CPU time 390.53 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:23:47 PM PDT 24
Peak memory 191192 kb
Host smart-1202f493-1a1f-44e5-b5ea-3e13dbc93991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579455626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1579455626
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3966217796
Short name T260
Test name
Test status
Simulation time 126350690342 ps
CPU time 198.21 seconds
Started Jun 07 06:17:24 PM PDT 24
Finished Jun 07 06:20:43 PM PDT 24
Peak memory 191168 kb
Host smart-81200846-c46c-46d0-95a5-4b7b3b140a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966217796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3966217796
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1776641675
Short name T172
Test name
Test status
Simulation time 263705369651 ps
CPU time 127.72 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 06:19:27 PM PDT 24
Peak memory 191096 kb
Host smart-8cb05d1a-4027-4334-a10e-9f71c344e04a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776641675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1776641675
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1492484803
Short name T188
Test name
Test status
Simulation time 724154057689 ps
CPU time 536.91 seconds
Started Jun 07 06:17:17 PM PDT 24
Finished Jun 07 06:26:14 PM PDT 24
Peak memory 191060 kb
Host smart-6dcc2639-23d3-49ce-9fb3-34b229cd12a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492484803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1492484803
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3309546515
Short name T354
Test name
Test status
Simulation time 175265988 ps
CPU time 0.69 seconds
Started Jun 07 06:17:23 PM PDT 24
Finished Jun 07 06:17:24 PM PDT 24
Peak memory 182792 kb
Host smart-1b29c144-ef46-4f10-af03-dc2136251f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309546515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3309546515
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2251190433
Short name T290
Test name
Test status
Simulation time 99698111209 ps
CPU time 236.69 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 06:21:17 PM PDT 24
Peak memory 191044 kb
Host smart-3742727b-1df0-44ca-8088-163a85eab107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251190433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2251190433
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3147144003
Short name T340
Test name
Test status
Simulation time 28372175547 ps
CPU time 28.46 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:17:31 PM PDT 24
Peak memory 182976 kb
Host smart-0cfa5418-4770-4ed1-ac1f-51680384bea0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147144003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3147144003
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1672019360
Short name T388
Test name
Test status
Simulation time 290674909412 ps
CPU time 66.72 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:18:09 PM PDT 24
Peak memory 182968 kb
Host smart-88392585-e13e-4b51-8986-25faafc3213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672019360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1672019360
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2665070386
Short name T175
Test name
Test status
Simulation time 166334691241 ps
CPU time 625.48 seconds
Started Jun 07 06:16:42 PM PDT 24
Finished Jun 07 06:27:08 PM PDT 24
Peak memory 191180 kb
Host smart-1fc68870-6e6f-407c-8d17-c4c2e3ce461b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665070386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2665070386
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4067183508
Short name T108
Test name
Test status
Simulation time 74657257736 ps
CPU time 129.94 seconds
Started Jun 07 06:16:43 PM PDT 24
Finished Jun 07 06:18:54 PM PDT 24
Peak memory 182984 kb
Host smart-0b909682-cfef-45d6-91e4-eccbe919deb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067183508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4067183508
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.4260696568
Short name T316
Test name
Test status
Simulation time 226896415695 ps
CPU time 210.79 seconds
Started Jun 07 06:17:22 PM PDT 24
Finished Jun 07 06:20:53 PM PDT 24
Peak memory 191200 kb
Host smart-7a4994f0-b360-4724-a036-66bf16f30b43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260696568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.4260696568
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3200014870
Short name T456
Test name
Test status
Simulation time 76873748586 ps
CPU time 38.94 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:17:55 PM PDT 24
Peak memory 182976 kb
Host smart-155e6b3a-9e07-4282-83f4-baa95b754e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200014870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3200014870
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1805700596
Short name T162
Test name
Test status
Simulation time 431583885781 ps
CPU time 2325.53 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 06:56:05 PM PDT 24
Peak memory 191072 kb
Host smart-db5e8199-b4bb-4322-8472-989bc4c6269a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805700596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1805700596
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3006540848
Short name T279
Test name
Test status
Simulation time 76042548348 ps
CPU time 156.42 seconds
Started Jun 07 06:17:24 PM PDT 24
Finished Jun 07 06:20:01 PM PDT 24
Peak memory 194308 kb
Host smart-23026812-3518-42d2-88d1-4ed699c0ff97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006540848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3006540848
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1452997814
Short name T196
Test name
Test status
Simulation time 145246487377 ps
CPU time 141.05 seconds
Started Jun 07 06:17:24 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 191164 kb
Host smart-d13dcf53-2cf2-49b5-83f7-1d3e98e067ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452997814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1452997814
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.315830781
Short name T208
Test name
Test status
Simulation time 720750792094 ps
CPU time 175.61 seconds
Started Jun 07 06:16:41 PM PDT 24
Finished Jun 07 06:19:38 PM PDT 24
Peak memory 182872 kb
Host smart-345beeee-14b6-4246-be5d-ae862f930251
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315830781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.315830781
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.525374378
Short name T446
Test name
Test status
Simulation time 292417372756 ps
CPU time 235.89 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 182824 kb
Host smart-fcac6a12-7c06-4f72-910e-75a6ae459cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525374378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.525374378
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2132044871
Short name T62
Test name
Test status
Simulation time 30675274756 ps
CPU time 51.76 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:17:37 PM PDT 24
Peak memory 191168 kb
Host smart-4bfce11c-b42f-4871-af2c-1164e8ca6e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132044871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2132044871
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.961842364
Short name T161
Test name
Test status
Simulation time 183744940956 ps
CPU time 302.77 seconds
Started Jun 07 06:16:41 PM PDT 24
Finished Jun 07 06:21:45 PM PDT 24
Peak memory 194388 kb
Host smart-0cf7460a-07b5-406b-a12e-8b9f2067a18b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961842364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
961842364
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.1685780194
Short name T220
Test name
Test status
Simulation time 54817960866 ps
CPU time 108.88 seconds
Started Jun 07 06:17:20 PM PDT 24
Finished Jun 07 06:19:10 PM PDT 24
Peak memory 191180 kb
Host smart-b7b1b8e0-c420-4df2-be87-0af07c49fe45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685780194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1685780194
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3079175670
Short name T148
Test name
Test status
Simulation time 90331565321 ps
CPU time 319.13 seconds
Started Jun 07 06:17:22 PM PDT 24
Finished Jun 07 06:22:42 PM PDT 24
Peak memory 191200 kb
Host smart-38fff02d-42ad-4375-9f23-0ea05498387a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079175670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3079175670
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3771763575
Short name T225
Test name
Test status
Simulation time 1384097698780 ps
CPU time 535.45 seconds
Started Jun 07 06:17:24 PM PDT 24
Finished Jun 07 06:26:20 PM PDT 24
Peak memory 191064 kb
Host smart-59945069-b298-47e0-bc31-a23d8c66273b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771763575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3771763575
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2180284931
Short name T447
Test name
Test status
Simulation time 408050542051 ps
CPU time 847.93 seconds
Started Jun 07 06:17:26 PM PDT 24
Finished Jun 07 06:31:35 PM PDT 24
Peak memory 194592 kb
Host smart-4a7ecfc1-1e9f-4ad4-95a3-c9f59d9e93e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180284931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2180284931
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3911120305
Short name T330
Test name
Test status
Simulation time 276756673302 ps
CPU time 135.41 seconds
Started Jun 07 06:17:28 PM PDT 24
Finished Jun 07 06:19:44 PM PDT 24
Peak memory 191088 kb
Host smart-9a757143-54d5-4715-9179-1cc9137414d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911120305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3911120305
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3265727368
Short name T272
Test name
Test status
Simulation time 119314673329 ps
CPU time 178.32 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 182972 kb
Host smart-d893690f-284f-4f73-abc9-c4ed088a11ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265727368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3265727368
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3793482115
Short name T371
Test name
Test status
Simulation time 170290124128 ps
CPU time 67.29 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:17:56 PM PDT 24
Peak memory 182836 kb
Host smart-870e81b1-199c-4038-98e2-9d27bb1387b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793482115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3793482115
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3541093320
Short name T265
Test name
Test status
Simulation time 92856846787 ps
CPU time 369.81 seconds
Started Jun 07 06:16:40 PM PDT 24
Finished Jun 07 06:22:50 PM PDT 24
Peak memory 183096 kb
Host smart-e0674f3e-31de-4a8a-91ed-b61531600e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541093320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3541093320
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.4276262937
Short name T12
Test name
Test status
Simulation time 77162666089 ps
CPU time 163.31 seconds
Started Jun 07 06:16:47 PM PDT 24
Finished Jun 07 06:19:32 PM PDT 24
Peak memory 197508 kb
Host smart-2bcd34da-912c-49a2-ace7-93ca62f24da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276262937 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.4276262937
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1659390491
Short name T44
Test name
Test status
Simulation time 126088366603 ps
CPU time 65.21 seconds
Started Jun 07 06:17:31 PM PDT 24
Finished Jun 07 06:18:37 PM PDT 24
Peak memory 182872 kb
Host smart-55169648-8bae-4804-99b6-669f9edde8f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659390491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1659390491
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2635657015
Short name T317
Test name
Test status
Simulation time 1577204688105 ps
CPU time 2045.03 seconds
Started Jun 07 06:17:24 PM PDT 24
Finished Jun 07 06:51:30 PM PDT 24
Peak memory 191176 kb
Host smart-bfe19a7d-c645-4601-b3f2-b42eecabd107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635657015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2635657015
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.14227453
Short name T27
Test name
Test status
Simulation time 68786058208 ps
CPU time 148.47 seconds
Started Jun 07 06:17:27 PM PDT 24
Finished Jun 07 06:19:56 PM PDT 24
Peak memory 191208 kb
Host smart-e55cd806-d0bb-488b-96aa-73377aec2aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14227453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.14227453
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3168151711
Short name T191
Test name
Test status
Simulation time 164176549758 ps
CPU time 311.71 seconds
Started Jun 07 06:17:26 PM PDT 24
Finished Jun 07 06:22:38 PM PDT 24
Peak memory 191044 kb
Host smart-89757d98-153a-424f-9e56-6ed3a9faaeab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168151711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3168151711
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3230558096
Short name T239
Test name
Test status
Simulation time 2420108737748 ps
CPU time 525.28 seconds
Started Jun 07 06:17:26 PM PDT 24
Finished Jun 07 06:26:11 PM PDT 24
Peak memory 191356 kb
Host smart-05f11a25-daff-43f8-950b-05338d49a45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230558096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3230558096
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2630236867
Short name T439
Test name
Test status
Simulation time 74164501249 ps
CPU time 20.28 seconds
Started Jun 07 06:17:28 PM PDT 24
Finished Jun 07 06:17:49 PM PDT 24
Peak memory 182852 kb
Host smart-d9b9c817-2324-46d5-85ea-9ca2b6be3b86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630236867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2630236867
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4221522677
Short name T337
Test name
Test status
Simulation time 85449661031 ps
CPU time 74.22 seconds
Started Jun 07 06:17:27 PM PDT 24
Finished Jun 07 06:18:42 PM PDT 24
Peak memory 191088 kb
Host smart-e192f1df-58d8-4d96-bc69-04aedfd77a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221522677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4221522677
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2040854070
Short name T116
Test name
Test status
Simulation time 109014807221 ps
CPU time 213.69 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:20:18 PM PDT 24
Peak memory 182872 kb
Host smart-c4045ba5-bedc-4bea-ad47-9cd810fb7e9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040854070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2040854070
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2241515538
Short name T423
Test name
Test status
Simulation time 246156291950 ps
CPU time 90.02 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:18:20 PM PDT 24
Peak memory 182976 kb
Host smart-529d342e-f231-4a5d-9931-ac4f1745980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241515538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2241515538
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.882238315
Short name T313
Test name
Test status
Simulation time 80863965996 ps
CPU time 21.11 seconds
Started Jun 07 06:16:46 PM PDT 24
Finished Jun 07 06:17:08 PM PDT 24
Peak memory 182876 kb
Host smart-99720958-0e97-457f-9925-7edd94512d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882238315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
882238315
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.3614185866
Short name T258
Test name
Test status
Simulation time 48357407258 ps
CPU time 83.16 seconds
Started Jun 07 06:17:26 PM PDT 24
Finished Jun 07 06:18:50 PM PDT 24
Peak memory 182936 kb
Host smart-1359a3c5-ccbb-419c-9930-d8e5137133b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614185866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3614185866
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.152800845
Short name T158
Test name
Test status
Simulation time 104881024631 ps
CPU time 476.33 seconds
Started Jun 07 06:17:25 PM PDT 24
Finished Jun 07 06:25:22 PM PDT 24
Peak memory 191040 kb
Host smart-d104dfe6-15de-455d-8855-231807fec188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152800845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.152800845
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.906056636
Short name T405
Test name
Test status
Simulation time 295050200007 ps
CPU time 931.21 seconds
Started Jun 07 06:17:33 PM PDT 24
Finished Jun 07 06:33:05 PM PDT 24
Peak memory 193132 kb
Host smart-dd1f8fb1-c926-46fa-b9d0-bd99b13041d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906056636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.906056636
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.4120149846
Short name T393
Test name
Test status
Simulation time 120475321096 ps
CPU time 58.43 seconds
Started Jun 07 06:17:31 PM PDT 24
Finished Jun 07 06:18:30 PM PDT 24
Peak memory 183004 kb
Host smart-8ff01204-3106-4b7b-b52a-fcf7b11ae8a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120149846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.4120149846
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2783870437
Short name T224
Test name
Test status
Simulation time 197347925361 ps
CPU time 730.67 seconds
Started Jun 07 06:17:33 PM PDT 24
Finished Jun 07 06:29:44 PM PDT 24
Peak memory 191064 kb
Host smart-bd595d8a-396f-4619-87e2-11478e68828b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783870437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2783870437
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2032518887
Short name T212
Test name
Test status
Simulation time 422000262588 ps
CPU time 195.3 seconds
Started Jun 07 06:17:35 PM PDT 24
Finished Jun 07 06:20:50 PM PDT 24
Peak memory 191160 kb
Host smart-2535c216-8ecd-4fbc-a90b-cb777452e37f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032518887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2032518887
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3136698481
Short name T296
Test name
Test status
Simulation time 415375221844 ps
CPU time 296.67 seconds
Started Jun 07 06:17:32 PM PDT 24
Finished Jun 07 06:22:30 PM PDT 24
Peak memory 191204 kb
Host smart-016e1330-5e8c-4067-90b6-d78c692d7304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136698481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3136698481
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.163431487
Short name T173
Test name
Test status
Simulation time 185954742668 ps
CPU time 173.99 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 182840 kb
Host smart-2c0a82e8-22b2-45ae-96c3-6cacfcda7817
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163431487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.163431487
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3758375214
Short name T390
Test name
Test status
Simulation time 57004671835 ps
CPU time 74.36 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:18:04 PM PDT 24
Peak memory 182832 kb
Host smart-b58acfe4-0c6a-4446-b15e-a028ece56ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758375214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3758375214
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.520635625
Short name T345
Test name
Test status
Simulation time 141828672081 ps
CPU time 229.24 seconds
Started Jun 07 06:16:55 PM PDT 24
Finished Jun 07 06:20:45 PM PDT 24
Peak memory 191192 kb
Host smart-9f919e26-d148-46d5-8784-4893ac9bc4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520635625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.520635625
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3878124005
Short name T409
Test name
Test status
Simulation time 261015105 ps
CPU time 0.74 seconds
Started Jun 07 06:16:47 PM PDT 24
Finished Jun 07 06:16:49 PM PDT 24
Peak memory 182884 kb
Host smart-9e89896f-2f41-46d4-b5b6-7c126d36612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878124005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3878124005
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/152.rv_timer_random.4012881731
Short name T139
Test name
Test status
Simulation time 46951310586 ps
CPU time 82.6 seconds
Started Jun 07 06:17:31 PM PDT 24
Finished Jun 07 06:18:54 PM PDT 24
Peak memory 191076 kb
Host smart-1795f12c-2f73-443b-981b-dd1076558309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012881731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4012881731
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2530820067
Short name T164
Test name
Test status
Simulation time 2372984941700 ps
CPU time 1096.61 seconds
Started Jun 07 06:17:34 PM PDT 24
Finished Jun 07 06:35:51 PM PDT 24
Peak memory 191200 kb
Host smart-ac9fa51a-d8a0-4992-b762-a7c294d7cfab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530820067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2530820067
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3415003108
Short name T59
Test name
Test status
Simulation time 202100304407 ps
CPU time 449.48 seconds
Started Jun 07 06:17:34 PM PDT 24
Finished Jun 07 06:25:04 PM PDT 24
Peak memory 191204 kb
Host smart-d0320a15-3dd0-453b-a342-ebdde6a5c3e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415003108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3415003108
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3082219617
Short name T216
Test name
Test status
Simulation time 30174738467 ps
CPU time 27.1 seconds
Started Jun 07 06:17:33 PM PDT 24
Finished Jun 07 06:18:01 PM PDT 24
Peak memory 183096 kb
Host smart-791588d3-c6a3-4d1c-b957-230ef257abfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082219617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3082219617
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3512360688
Short name T291
Test name
Test status
Simulation time 568448682255 ps
CPU time 414.6 seconds
Started Jun 07 06:17:31 PM PDT 24
Finished Jun 07 06:24:26 PM PDT 24
Peak memory 190984 kb
Host smart-ead09815-f831-4cc8-81aa-aa9d99f8ac66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512360688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3512360688
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3875304533
Short name T210
Test name
Test status
Simulation time 355184035134 ps
CPU time 326.09 seconds
Started Jun 07 06:17:29 PM PDT 24
Finished Jun 07 06:22:56 PM PDT 24
Peak memory 191056 kb
Host smart-53510bd8-667d-4c8a-99e8-f094f1a4a651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875304533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3875304533
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2622806948
Short name T276
Test name
Test status
Simulation time 381350110318 ps
CPU time 401.3 seconds
Started Jun 07 06:17:27 PM PDT 24
Finished Jun 07 06:24:09 PM PDT 24
Peak memory 191080 kb
Host smart-7fc4eff4-aa70-4404-9df2-6ccf5ec6fa34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622806948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2622806948
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1101815363
Short name T348
Test name
Test status
Simulation time 961855329120 ps
CPU time 464.44 seconds
Started Jun 07 06:16:52 PM PDT 24
Finished Jun 07 06:24:37 PM PDT 24
Peak memory 182976 kb
Host smart-64bea5f0-6386-4003-bd83-7e46dd8ffa9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101815363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1101815363
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1652470229
Short name T377
Test name
Test status
Simulation time 276297717879 ps
CPU time 101.75 seconds
Started Jun 07 06:16:47 PM PDT 24
Finished Jun 07 06:18:29 PM PDT 24
Peak memory 182976 kb
Host smart-59ceada5-bc37-46c5-b52b-c3839fd571e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652470229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1652470229
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.202412035
Short name T375
Test name
Test status
Simulation time 52019684594 ps
CPU time 220.66 seconds
Started Jun 07 06:16:52 PM PDT 24
Finished Jun 07 06:20:33 PM PDT 24
Peak memory 182848 kb
Host smart-ae56fcc8-7cef-4615-89b2-2710c4359e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202412035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.202412035
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3053290673
Short name T334
Test name
Test status
Simulation time 161434736910 ps
CPU time 306.57 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:21:56 PM PDT 24
Peak memory 191160 kb
Host smart-0f070836-7cb3-44bf-9627-ca809a009da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053290673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3053290673
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1806573079
Short name T7
Test name
Test status
Simulation time 530370058579 ps
CPU time 2020.87 seconds
Started Jun 07 06:17:31 PM PDT 24
Finished Jun 07 06:51:12 PM PDT 24
Peak memory 190984 kb
Host smart-ac2a8b2d-8ac8-4db2-9cd9-60dfaf43b924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806573079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1806573079
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2368549996
Short name T189
Test name
Test status
Simulation time 232622651304 ps
CPU time 494.7 seconds
Started Jun 07 06:17:31 PM PDT 24
Finished Jun 07 06:25:46 PM PDT 24
Peak memory 191204 kb
Host smart-00322cef-8ae2-458e-b884-4043d3f65e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368549996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2368549996
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2369964215
Short name T6
Test name
Test status
Simulation time 255472641716 ps
CPU time 258.92 seconds
Started Jun 07 06:17:32 PM PDT 24
Finished Jun 07 06:21:52 PM PDT 24
Peak memory 191124 kb
Host smart-53994a41-d070-43f1-bfc5-febcb70e9abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369964215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2369964215
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3214009165
Short name T312
Test name
Test status
Simulation time 82120009791 ps
CPU time 199.93 seconds
Started Jun 07 06:17:31 PM PDT 24
Finished Jun 07 06:20:52 PM PDT 24
Peak memory 182896 kb
Host smart-60cb0e5b-5e25-4a98-b52f-ae497c527e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214009165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3214009165
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1110774595
Short name T222
Test name
Test status
Simulation time 29314700215 ps
CPU time 76.02 seconds
Started Jun 07 06:17:28 PM PDT 24
Finished Jun 07 06:18:44 PM PDT 24
Peak memory 191168 kb
Host smart-8a79b346-c40b-4a72-800c-e05475f27ba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110774595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1110774595
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3937625733
Short name T207
Test name
Test status
Simulation time 149909015827 ps
CPU time 267.35 seconds
Started Jun 07 06:17:38 PM PDT 24
Finished Jun 07 06:22:06 PM PDT 24
Peak memory 191088 kb
Host smart-bb71bcda-908f-445c-875e-7a1cb874ddbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937625733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3937625733
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.163954285
Short name T137
Test name
Test status
Simulation time 114131356427 ps
CPU time 968.01 seconds
Started Jun 07 06:17:36 PM PDT 24
Finished Jun 07 06:33:45 PM PDT 24
Peak memory 183004 kb
Host smart-6a818b32-341a-421c-9baf-ba1d0fd1853f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163954285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.163954285
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.680334326
Short name T422
Test name
Test status
Simulation time 702843584722 ps
CPU time 974.25 seconds
Started Jun 07 06:17:34 PM PDT 24
Finished Jun 07 06:33:49 PM PDT 24
Peak memory 191208 kb
Host smart-30cd9478-8504-4915-801b-6b4c63ea23ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680334326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.680334326
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.812809747
Short name T435
Test name
Test status
Simulation time 20905465396 ps
CPU time 35.05 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:17:24 PM PDT 24
Peak memory 182960 kb
Host smart-c90491e4-c6fd-46c6-8952-fd6e3e00eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812809747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.812809747
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1548721841
Short name T321
Test name
Test status
Simulation time 41915919725 ps
CPU time 298.29 seconds
Started Jun 07 06:16:43 PM PDT 24
Finished Jun 07 06:21:42 PM PDT 24
Peak memory 191044 kb
Host smart-f2dd9b76-7788-44ef-a1c9-e602db3ab6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548721841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1548721841
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.683605077
Short name T217
Test name
Test status
Simulation time 271723097994 ps
CPU time 1050.49 seconds
Started Jun 07 06:16:50 PM PDT 24
Finished Jun 07 06:34:21 PM PDT 24
Peak memory 191068 kb
Host smart-929a847d-36e5-46bd-a41b-0b9fa4c844e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683605077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.683605077
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3725324798
Short name T155
Test name
Test status
Simulation time 316242950842 ps
CPU time 1277.5 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:38:06 PM PDT 24
Peak memory 191036 kb
Host smart-8e76aa5f-845b-4e16-b319-1bf3b77876d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725324798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3725324798
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.1934290191
Short name T47
Test name
Test status
Simulation time 218027652491 ps
CPU time 944.62 seconds
Started Jun 07 06:17:40 PM PDT 24
Finished Jun 07 06:33:25 PM PDT 24
Peak memory 191196 kb
Host smart-b5840e7b-39c8-40db-baba-76603f4d104a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934290191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1934290191
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.665385460
Short name T278
Test name
Test status
Simulation time 126556136062 ps
CPU time 610.53 seconds
Started Jun 07 06:17:37 PM PDT 24
Finished Jun 07 06:27:48 PM PDT 24
Peak memory 191208 kb
Host smart-02ab92f2-eb62-4aa0-abb8-8acd4d448a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665385460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.665385460
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1627722936
Short name T268
Test name
Test status
Simulation time 205739947121 ps
CPU time 560.81 seconds
Started Jun 07 06:17:38 PM PDT 24
Finished Jun 07 06:27:00 PM PDT 24
Peak memory 191056 kb
Host smart-e5342441-5e42-4c6b-b565-1cf1fd101dac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627722936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1627722936
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3162449987
Short name T197
Test name
Test status
Simulation time 449394688815 ps
CPU time 223.26 seconds
Started Jun 07 06:17:39 PM PDT 24
Finished Jun 07 06:21:23 PM PDT 24
Peak memory 194636 kb
Host smart-2f233a20-6a81-42a8-bd5b-474e05e449f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162449987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3162449987
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2056686874
Short name T288
Test name
Test status
Simulation time 447926910 ps
CPU time 1.32 seconds
Started Jun 07 06:17:43 PM PDT 24
Finished Jun 07 06:17:45 PM PDT 24
Peak memory 182760 kb
Host smart-b2d04e72-a48b-49bf-96e1-19c7f8382f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056686874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2056686874
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.4096058779
Short name T352
Test name
Test status
Simulation time 219170041339 ps
CPU time 417.44 seconds
Started Jun 07 06:17:36 PM PDT 24
Finished Jun 07 06:24:34 PM PDT 24
Peak memory 191168 kb
Host smart-d5ffbf57-1c0f-4fd7-8c10-4dbd87a5b5e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096058779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4096058779
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1515069032
Short name T22
Test name
Test status
Simulation time 910247857526 ps
CPU time 246.92 seconds
Started Jun 07 06:17:43 PM PDT 24
Finished Jun 07 06:21:51 PM PDT 24
Peak memory 191168 kb
Host smart-4771da41-6be9-4713-93f6-0afbbf3e8d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515069032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1515069032
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.860482564
Short name T294
Test name
Test status
Simulation time 68480509180 ps
CPU time 52.35 seconds
Started Jun 07 06:17:36 PM PDT 24
Finished Jun 07 06:18:29 PM PDT 24
Peak memory 182748 kb
Host smart-c503c1c3-491f-4e45-944e-be3518c4821b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860482564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.860482564
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1670764464
Short name T367
Test name
Test status
Simulation time 315584931227 ps
CPU time 226.65 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:20:36 PM PDT 24
Peak memory 182832 kb
Host smart-42ad0a00-c15e-4ebd-acc1-19d42981be00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670764464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1670764464
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3350010831
Short name T326
Test name
Test status
Simulation time 47455384631 ps
CPU time 119.8 seconds
Started Jun 07 06:16:51 PM PDT 24
Finished Jun 07 06:18:52 PM PDT 24
Peak memory 182944 kb
Host smart-6e53690b-546d-4879-a0fa-37083e2f903b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350010831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3350010831
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1917617805
Short name T2
Test name
Test status
Simulation time 40939484119 ps
CPU time 69.28 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:18:06 PM PDT 24
Peak memory 182816 kb
Host smart-f46576c2-a93a-4c51-ab51-9f1bdcc42659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917617805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1917617805
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.84192943
Short name T223
Test name
Test status
Simulation time 552794766965 ps
CPU time 269.67 seconds
Started Jun 07 06:17:38 PM PDT 24
Finished Jun 07 06:22:08 PM PDT 24
Peak memory 191180 kb
Host smart-2c5fafb6-4d35-46d8-a407-063048ca6e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84192943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.84192943
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.856719101
Short name T338
Test name
Test status
Simulation time 25729657735 ps
CPU time 43.43 seconds
Started Jun 07 06:17:45 PM PDT 24
Finished Jun 07 06:18:29 PM PDT 24
Peak memory 182996 kb
Host smart-480fefa0-129f-4fd9-8a54-bd5aa4c4538d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856719101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.856719101
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.841448921
Short name T314
Test name
Test status
Simulation time 313595699721 ps
CPU time 129.62 seconds
Started Jun 07 06:17:45 PM PDT 24
Finished Jun 07 06:19:56 PM PDT 24
Peak memory 191088 kb
Host smart-3c7c64db-2ce6-431c-a93a-bb39a266d7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841448921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.841448921
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3615228642
Short name T159
Test name
Test status
Simulation time 390218612984 ps
CPU time 944.16 seconds
Started Jun 07 06:17:42 PM PDT 24
Finished Jun 07 06:33:27 PM PDT 24
Peak memory 191052 kb
Host smart-e891ef96-7f67-43be-86ca-bdc1d4938c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615228642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3615228642
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3650644111
Short name T131
Test name
Test status
Simulation time 100877254809 ps
CPU time 444.79 seconds
Started Jun 07 06:17:45 PM PDT 24
Finished Jun 07 06:25:10 PM PDT 24
Peak memory 191204 kb
Host smart-5c0646c9-3ad1-4880-bcb7-162bff86f6a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650644111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3650644111
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.319054613
Short name T427
Test name
Test status
Simulation time 73076537667 ps
CPU time 43.7 seconds
Started Jun 07 06:16:52 PM PDT 24
Finished Jun 07 06:17:36 PM PDT 24
Peak memory 182988 kb
Host smart-4d0b6a66-39d2-4a57-aea2-4cc29033ad25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319054613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.319054613
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2380684894
Short name T448
Test name
Test status
Simulation time 107183963079 ps
CPU time 65.09 seconds
Started Jun 07 06:16:51 PM PDT 24
Finished Jun 07 06:17:57 PM PDT 24
Peak memory 182860 kb
Host smart-4ac21a1d-2dd8-45bc-b2d3-35c0147be7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380684894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2380684894
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1701121403
Short name T436
Test name
Test status
Simulation time 793266258 ps
CPU time 1.53 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:17:03 PM PDT 24
Peak memory 182916 kb
Host smart-7cb8dc9b-584e-4883-af28-914be7b9cbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701121403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1701121403
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3090777585
Short name T199
Test name
Test status
Simulation time 581154694638 ps
CPU time 414.04 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:23:53 PM PDT 24
Peak memory 191180 kb
Host smart-cb8c0ada-58c9-4df5-a0c5-43e14d863ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090777585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3090777585
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.3894789201
Short name T333
Test name
Test status
Simulation time 179421239307 ps
CPU time 262.93 seconds
Started Jun 07 06:17:45 PM PDT 24
Finished Jun 07 06:22:09 PM PDT 24
Peak memory 191092 kb
Host smart-89c8c0be-7ee7-4d97-9a83-d31f45073e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894789201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3894789201
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.945661584
Short name T124
Test name
Test status
Simulation time 94981447018 ps
CPU time 178.35 seconds
Started Jun 07 06:17:45 PM PDT 24
Finished Jun 07 06:20:44 PM PDT 24
Peak memory 191212 kb
Host smart-471a0825-9141-436e-9bb2-92f12af42981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945661584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.945661584
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3753911347
Short name T351
Test name
Test status
Simulation time 425872734074 ps
CPU time 1058.94 seconds
Started Jun 07 06:17:44 PM PDT 24
Finished Jun 07 06:35:23 PM PDT 24
Peak memory 190992 kb
Host smart-81950dc7-8431-4c4b-9be9-1e584b452deb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753911347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3753911347
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3396274286
Short name T20
Test name
Test status
Simulation time 139613858018 ps
CPU time 465.01 seconds
Started Jun 07 06:17:48 PM PDT 24
Finished Jun 07 06:25:33 PM PDT 24
Peak memory 191168 kb
Host smart-377ba993-a864-457e-b63c-b981602d7a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396274286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3396274286
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1865234173
Short name T60
Test name
Test status
Simulation time 370801388938 ps
CPU time 1683.94 seconds
Started Jun 07 06:17:46 PM PDT 24
Finished Jun 07 06:45:50 PM PDT 24
Peak memory 191184 kb
Host smart-d5158d44-6ac6-444e-91d7-ae6574a759d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865234173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1865234173
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1194198303
Short name T206
Test name
Test status
Simulation time 184388096705 ps
CPU time 246.26 seconds
Started Jun 07 06:17:45 PM PDT 24
Finished Jun 07 06:21:52 PM PDT 24
Peak memory 193224 kb
Host smart-d15ed41b-3226-4a42-8b45-531db95c76fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194198303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1194198303
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1750795106
Short name T440
Test name
Test status
Simulation time 150671916369 ps
CPU time 528.08 seconds
Started Jun 07 06:17:45 PM PDT 24
Finished Jun 07 06:26:34 PM PDT 24
Peak memory 191188 kb
Host smart-c49337bf-e4bb-46e1-8939-f3d2b9b80d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750795106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1750795106
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.547025494
Short name T242
Test name
Test status
Simulation time 263513087533 ps
CPU time 1555.08 seconds
Started Jun 07 06:17:46 PM PDT 24
Finished Jun 07 06:43:41 PM PDT 24
Peak memory 191100 kb
Host smart-4b5aaea9-7dfe-4927-8e67-fd311f3bace0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547025494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.547025494
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2012173901
Short name T256
Test name
Test status
Simulation time 869749204787 ps
CPU time 430.09 seconds
Started Jun 07 06:16:29 PM PDT 24
Finished Jun 07 06:23:40 PM PDT 24
Peak memory 182836 kb
Host smart-5673ad6e-de42-480c-b39a-aad84b1455eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012173901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2012173901
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2122207550
Short name T410
Test name
Test status
Simulation time 412209643774 ps
CPU time 86.94 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:18:13 PM PDT 24
Peak memory 182664 kb
Host smart-9833acc2-8135-417a-9c57-4b008c51f60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122207550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2122207550
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3644289805
Short name T17
Test name
Test status
Simulation time 123539011 ps
CPU time 0.84 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:16:47 PM PDT 24
Peak memory 213268 kb
Host smart-fa8643e8-dee2-47dc-92d2-eb692d11c571
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644289805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3644289805
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1281336568
Short name T219
Test name
Test status
Simulation time 130013166409 ps
CPU time 680.29 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:28:05 PM PDT 24
Peak memory 195080 kb
Host smart-511bec3d-5961-4dcc-a5da-b307387eed89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281336568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1281336568
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.361269319
Short name T273
Test name
Test status
Simulation time 49680816066 ps
CPU time 26.75 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:17:30 PM PDT 24
Peak memory 182988 kb
Host smart-7b921611-6087-4bad-8598-5e81fa988e5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361269319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.361269319
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3139314933
Short name T9
Test name
Test status
Simulation time 112336369519 ps
CPU time 95.13 seconds
Started Jun 07 06:16:51 PM PDT 24
Finished Jun 07 06:18:27 PM PDT 24
Peak memory 182984 kb
Host smart-68730176-1efa-4521-a5e1-1e42bd40733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139314933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3139314933
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1881799709
Short name T281
Test name
Test status
Simulation time 173687813687 ps
CPU time 80.91 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:18:24 PM PDT 24
Peak memory 191100 kb
Host smart-fe27818c-ddee-4b3f-87db-4e652b9089c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881799709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1881799709
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3182922589
Short name T396
Test name
Test status
Simulation time 90868724921 ps
CPU time 35.12 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:17:25 PM PDT 24
Peak memory 182836 kb
Host smart-868ec791-8a06-40cd-a537-a1aed92ada3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182922589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3182922589
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2277789749
Short name T363
Test name
Test status
Simulation time 919529714620 ps
CPU time 183.77 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:20:06 PM PDT 24
Peak memory 182804 kb
Host smart-b20ee3de-f418-4844-b16f-48a7e86b3d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277789749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2277789749
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2763779313
Short name T232
Test name
Test status
Simulation time 1016395581424 ps
CPU time 611.13 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:27:14 PM PDT 24
Peak memory 182852 kb
Host smart-98c907f8-1ba5-43bc-8899-82848765411a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763779313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2763779313
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1080800763
Short name T392
Test name
Test status
Simulation time 119534109420 ps
CPU time 75.71 seconds
Started Jun 07 06:16:53 PM PDT 24
Finished Jun 07 06:18:09 PM PDT 24
Peak memory 182860 kb
Host smart-ffe7889d-4470-43d4-b82e-8fcafb026fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080800763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1080800763
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.4145724947
Short name T417
Test name
Test status
Simulation time 318383007079 ps
CPU time 1763.99 seconds
Started Jun 07 06:17:04 PM PDT 24
Finished Jun 07 06:46:29 PM PDT 24
Peak memory 191184 kb
Host smart-6f85c2de-b8d1-466d-a42d-4b4b69d41180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145724947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.4145724947
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2872311608
Short name T247
Test name
Test status
Simulation time 168131301497 ps
CPU time 234.21 seconds
Started Jun 07 06:16:53 PM PDT 24
Finished Jun 07 06:20:48 PM PDT 24
Peak memory 191040 kb
Host smart-609052d7-09fc-426a-89fe-3de32f102e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872311608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2872311608
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.864167952
Short name T452
Test name
Test status
Simulation time 57785440 ps
CPU time 0.54 seconds
Started Jun 07 06:16:53 PM PDT 24
Finished Jun 07 06:16:54 PM PDT 24
Peak memory 182644 kb
Host smart-1208cb87-44f4-4ba0-8708-98445fe91b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864167952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
864167952
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3641814477
Short name T252
Test name
Test status
Simulation time 447131612781 ps
CPU time 227.02 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:20:46 PM PDT 24
Peak memory 182852 kb
Host smart-9abb9815-ebf7-48b7-85ed-8562985c39f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641814477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3641814477
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3305570596
Short name T381
Test name
Test status
Simulation time 104465851598 ps
CPU time 171.65 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:19:59 PM PDT 24
Peak memory 182832 kb
Host smart-3f0ffe6f-2b40-4925-a0ea-189770aa3fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305570596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3305570596
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2311730387
Short name T229
Test name
Test status
Simulation time 144987557302 ps
CPU time 324.01 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:22:32 PM PDT 24
Peak memory 191080 kb
Host smart-a43cc3e8-46d6-4bd2-a8fd-3427dc1b2f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311730387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2311730387
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4285910886
Short name T127
Test name
Test status
Simulation time 127448190346 ps
CPU time 34.47 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:17:32 PM PDT 24
Peak memory 193040 kb
Host smart-d8c02c9f-a5ac-4302-90b5-32a6aa668616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285910886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4285910886
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3461193065
Short name T398
Test name
Test status
Simulation time 693093256836 ps
CPU time 172.71 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:20:08 PM PDT 24
Peak memory 182876 kb
Host smart-87e0801f-7aa5-4061-91b0-3f12d83b7304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461193065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3461193065
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3937480680
Short name T36
Test name
Test status
Simulation time 68192463976 ps
CPU time 522.57 seconds
Started Jun 07 06:16:50 PM PDT 24
Finished Jun 07 06:25:34 PM PDT 24
Peak memory 205888 kb
Host smart-ef88606b-d25f-430f-ada3-383284edb567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937480680 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3937480680
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2901204357
Short name T414
Test name
Test status
Simulation time 8049732099 ps
CPU time 15.29 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:17:27 PM PDT 24
Peak memory 182884 kb
Host smart-8f45a6ca-f85e-41ee-86fc-0d91dee606b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901204357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2901204357
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3228942298
Short name T360
Test name
Test status
Simulation time 339215621905 ps
CPU time 220.87 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:20:39 PM PDT 24
Peak memory 182856 kb
Host smart-bb899f27-ef9e-4d50-8b6b-8c87027196d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228942298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3228942298
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3928700120
Short name T372
Test name
Test status
Simulation time 200333163 ps
CPU time 4.02 seconds
Started Jun 07 06:16:51 PM PDT 24
Finished Jun 07 06:16:55 PM PDT 24
Peak memory 191112 kb
Host smart-357c7943-fc0b-4539-b7a6-89edbadc77aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928700120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3928700120
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3959339698
Short name T68
Test name
Test status
Simulation time 377987054302 ps
CPU time 152.6 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:19:29 PM PDT 24
Peak memory 182892 kb
Host smart-a1eff058-14ff-48c6-b85f-9193ecc29f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959339698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3959339698
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3273880908
Short name T445
Test name
Test status
Simulation time 120479294601 ps
CPU time 228.26 seconds
Started Jun 07 06:17:09 PM PDT 24
Finished Jun 07 06:20:58 PM PDT 24
Peak memory 182980 kb
Host smart-20afa3a7-7b11-44fe-aad6-4ee6c2f3d1f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273880908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3273880908
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3523360202
Short name T370
Test name
Test status
Simulation time 68680963164 ps
CPU time 100.09 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:18:29 PM PDT 24
Peak memory 182860 kb
Host smart-0067311c-a437-4fcf-a4ea-af456ed0999a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523360202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3523360202
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1117657287
Short name T152
Test name
Test status
Simulation time 64616325044 ps
CPU time 120.25 seconds
Started Jun 07 06:17:13 PM PDT 24
Finished Jun 07 06:19:14 PM PDT 24
Peak memory 191040 kb
Host smart-f24b2c5d-c446-42b6-b645-4abadd33016f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117657287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1117657287
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.941718950
Short name T193
Test name
Test status
Simulation time 284745465508 ps
CPU time 1406.17 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:40:38 PM PDT 24
Peak memory 191180 kb
Host smart-23057bee-1070-4daf-a558-48997a3ad170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941718950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.941718950
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1601199425
Short name T125
Test name
Test status
Simulation time 274919301288 ps
CPU time 249.16 seconds
Started Jun 07 06:16:50 PM PDT 24
Finished Jun 07 06:21:00 PM PDT 24
Peak memory 182984 kb
Host smart-02cf58df-db10-4021-bdf5-9add62258b1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601199425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1601199425
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.884613172
Short name T374
Test name
Test status
Simulation time 40408921236 ps
CPU time 59.13 seconds
Started Jun 07 06:16:51 PM PDT 24
Finished Jun 07 06:17:51 PM PDT 24
Peak memory 182944 kb
Host smart-49574e3f-c3d3-4a3d-b890-a8fe9c6542a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884613172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.884613172
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.771606681
Short name T426
Test name
Test status
Simulation time 114589633503 ps
CPU time 168.64 seconds
Started Jun 07 06:16:54 PM PDT 24
Finished Jun 07 06:19:43 PM PDT 24
Peak memory 191072 kb
Host smart-219b482f-c318-40e3-ad34-8e30f2a1c3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771606681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.771606681
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2630752401
Short name T419
Test name
Test status
Simulation time 63433739 ps
CPU time 0.56 seconds
Started Jun 07 06:16:52 PM PDT 24
Finished Jun 07 06:16:53 PM PDT 24
Peak memory 182132 kb
Host smart-14d7f8ec-0d6d-460b-9802-bfb34a4e0758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630752401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2630752401
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3558600274
Short name T289
Test name
Test status
Simulation time 9573712771 ps
CPU time 6.04 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:17:06 PM PDT 24
Peak memory 182976 kb
Host smart-5d8c6cad-989f-46ab-89a9-92461cfd4079
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558600274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3558600274
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2241874229
Short name T383
Test name
Test status
Simulation time 70870728408 ps
CPU time 99.13 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:18:35 PM PDT 24
Peak memory 182956 kb
Host smart-a3335b91-b4c0-4725-bce6-fe097206997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241874229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2241874229
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2784314872
Short name T318
Test name
Test status
Simulation time 134292701040 ps
CPU time 84.66 seconds
Started Jun 07 06:16:53 PM PDT 24
Finished Jun 07 06:18:18 PM PDT 24
Peak memory 191056 kb
Host smart-5ecc6f66-1871-4267-972d-a3e48a16839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784314872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2784314872
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1930677935
Short name T170
Test name
Test status
Simulation time 662855676459 ps
CPU time 408.81 seconds
Started Jun 07 06:16:57 PM PDT 24
Finished Jun 07 06:23:46 PM PDT 24
Peak memory 191080 kb
Host smart-06ab681b-be9a-44a6-b1b7-66b97725a107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930677935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1930677935
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3707505205
Short name T287
Test name
Test status
Simulation time 73958614904 ps
CPU time 137.69 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:19:14 PM PDT 24
Peak memory 182932 kb
Host smart-b2530d33-e8fb-4cf9-bebc-e8f8c61b5328
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707505205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3707505205
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3952839944
Short name T397
Test name
Test status
Simulation time 309522517174 ps
CPU time 64.09 seconds
Started Jun 07 06:16:53 PM PDT 24
Finished Jun 07 06:17:58 PM PDT 24
Peak memory 182824 kb
Host smart-6b102f32-2047-42ac-9fd7-92f8f76c4b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952839944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3952839944
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3493267896
Short name T205
Test name
Test status
Simulation time 487418001458 ps
CPU time 422.27 seconds
Started Jun 07 06:16:50 PM PDT 24
Finished Jun 07 06:23:53 PM PDT 24
Peak memory 191204 kb
Host smart-4e2d8a65-7e90-4e0c-a55b-b27fd76e46f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493267896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3493267896
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3873616378
Short name T136
Test name
Test status
Simulation time 79051122118 ps
CPU time 39.03 seconds
Started Jun 07 06:17:12 PM PDT 24
Finished Jun 07 06:17:52 PM PDT 24
Peak memory 182832 kb
Host smart-21d302f8-36d8-4f22-8fcc-64f17deb5084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873616378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3873616378
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3187574061
Short name T259
Test name
Test status
Simulation time 207494317371 ps
CPU time 368.42 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:23:12 PM PDT 24
Peak memory 182892 kb
Host smart-5d76da80-0c0c-4428-9e66-d24ea26ff561
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187574061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3187574061
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1845378943
Short name T356
Test name
Test status
Simulation time 212725332088 ps
CPU time 97.48 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:18:41 PM PDT 24
Peak memory 182876 kb
Host smart-be168ed9-ddc2-4381-bd14-49f82f30d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845378943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1845378943
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2821485412
Short name T458
Test name
Test status
Simulation time 3172310650 ps
CPU time 5.8 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:17:07 PM PDT 24
Peak memory 182844 kb
Host smart-3bd6dd2d-ae2b-4f32-802d-98b9442eee48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821485412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2821485412
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3444884462
Short name T382
Test name
Test status
Simulation time 368931576097 ps
CPU time 1230.41 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:37:29 PM PDT 24
Peak memory 191040 kb
Host smart-0680caba-6fca-41e7-ae78-0591133b273a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444884462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3444884462
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1549879238
Short name T420
Test name
Test status
Simulation time 76129145978 ps
CPU time 98.09 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:18:35 PM PDT 24
Peak memory 182872 kb
Host smart-9fd68bd3-a544-41cb-ace0-8e6545e5af93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549879238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1549879238
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.4210300637
Short name T25
Test name
Test status
Simulation time 8321959381 ps
CPU time 8.93 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:17:09 PM PDT 24
Peak memory 182860 kb
Host smart-b77c58fb-b2f5-46d9-8cb8-cb62d2bbe0dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210300637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.4210300637
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3247050304
Short name T65
Test name
Test status
Simulation time 97179789574 ps
CPU time 150.29 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:19:33 PM PDT 24
Peak memory 182868 kb
Host smart-46199538-8b6c-4314-a70a-e0d8fce7cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247050304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3247050304
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.4062622596
Short name T115
Test name
Test status
Simulation time 105328143267 ps
CPU time 228.56 seconds
Started Jun 07 06:17:06 PM PDT 24
Finished Jun 07 06:20:55 PM PDT 24
Peak memory 191048 kb
Host smart-2bde3862-3b92-4036-9549-8ed533a5ff62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062622596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.4062622596
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.963921796
Short name T295
Test name
Test status
Simulation time 91147409872 ps
CPU time 78.6 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:18:15 PM PDT 24
Peak memory 191172 kb
Host smart-f2c92f9d-0680-482c-b6d0-050dc1542b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963921796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.963921796
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2724603418
Short name T37
Test name
Test status
Simulation time 24483404088 ps
CPU time 192.3 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:20:12 PM PDT 24
Peak memory 197648 kb
Host smart-bb5900d4-850e-416c-921e-ac084fe4110b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724603418 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2724603418
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1986912625
Short name T237
Test name
Test status
Simulation time 278011738097 ps
CPU time 467.43 seconds
Started Jun 07 06:16:37 PM PDT 24
Finished Jun 07 06:24:25 PM PDT 24
Peak memory 182844 kb
Host smart-55bafb93-5d13-4271-8ef1-93750165c489
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986912625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1986912625
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3317366502
Short name T391
Test name
Test status
Simulation time 34805425044 ps
CPU time 43.64 seconds
Started Jun 07 06:16:42 PM PDT 24
Finished Jun 07 06:17:26 PM PDT 24
Peak memory 182876 kb
Host smart-22d15fb0-2337-4252-93f0-996b9ddfa803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317366502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3317366502
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3447851356
Short name T151
Test name
Test status
Simulation time 107276668000 ps
CPU time 230.92 seconds
Started Jun 07 06:16:46 PM PDT 24
Finished Jun 07 06:20:38 PM PDT 24
Peak memory 191056 kb
Host smart-04f4ea4f-9d00-4282-b115-2a60ab70accb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447851356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3447851356
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2024992029
Short name T195
Test name
Test status
Simulation time 50948241794 ps
CPU time 136.76 seconds
Started Jun 07 06:16:34 PM PDT 24
Finished Jun 07 06:18:51 PM PDT 24
Peak memory 191184 kb
Host smart-a6016552-ab7f-40b9-941e-c5c4fd6d0d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024992029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2024992029
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2467017137
Short name T14
Test name
Test status
Simulation time 184527864 ps
CPU time 0.77 seconds
Started Jun 07 06:16:29 PM PDT 24
Finished Jun 07 06:16:30 PM PDT 24
Peak memory 213268 kb
Host smart-1f13bd1f-a6a3-4343-8526-4b3e3f82c6bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467017137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2467017137
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1805356914
Short name T394
Test name
Test status
Simulation time 366082702777 ps
CPU time 580.13 seconds
Started Jun 07 06:16:40 PM PDT 24
Finished Jun 07 06:26:20 PM PDT 24
Peak memory 191000 kb
Host smart-6f58d27d-62ae-4b74-bac0-b9395c98b09c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805356914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1805356914
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.356590165
Short name T40
Test name
Test status
Simulation time 62509082409 ps
CPU time 123.03 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:18:49 PM PDT 24
Peak memory 197324 kb
Host smart-67d52cf2-dd4c-4cb9-8891-f32a42cadc9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356590165 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.356590165
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4226607046
Short name T187
Test name
Test status
Simulation time 260988393722 ps
CPU time 281.11 seconds
Started Jun 07 06:16:55 PM PDT 24
Finished Jun 07 06:21:37 PM PDT 24
Peak memory 182844 kb
Host smart-42ce23ec-71c9-4e0b-ba18-0164b3c322f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226607046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.4226607046
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2152004625
Short name T387
Test name
Test status
Simulation time 721552536568 ps
CPU time 307.12 seconds
Started Jun 07 06:16:55 PM PDT 24
Finished Jun 07 06:22:03 PM PDT 24
Peak memory 182972 kb
Host smart-ffe1598d-17b2-4f93-929b-16e774ed8bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152004625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2152004625
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.604803950
Short name T128
Test name
Test status
Simulation time 742824706569 ps
CPU time 437.51 seconds
Started Jun 07 06:17:04 PM PDT 24
Finished Jun 07 06:24:22 PM PDT 24
Peak memory 191200 kb
Host smart-595ca911-54fb-443c-a356-543fbc99447e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604803950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.604803950
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1686942559
Short name T1
Test name
Test status
Simulation time 73510310624 ps
CPU time 125.57 seconds
Started Jun 07 06:16:57 PM PDT 24
Finished Jun 07 06:19:03 PM PDT 24
Peak memory 182832 kb
Host smart-25d67d05-c1c3-42ee-9c9a-7cb3467830c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686942559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1686942559
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.605021674
Short name T451
Test name
Test status
Simulation time 2815333432270 ps
CPU time 632.12 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:27:31 PM PDT 24
Peak memory 191060 kb
Host smart-00ba9e1a-ca64-472c-a5ea-86da35c041bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605021674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
605021674
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2329028311
Short name T38
Test name
Test status
Simulation time 2707147865 ps
CPU time 28.45 seconds
Started Jun 07 06:17:00 PM PDT 24
Finished Jun 07 06:17:29 PM PDT 24
Peak memory 197492 kb
Host smart-6e0582bf-203b-44f4-be89-49c6d6374ddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329028311 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2329028311
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3281556090
Short name T126
Test name
Test status
Simulation time 281407575351 ps
CPU time 453.45 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:24:33 PM PDT 24
Peak memory 182844 kb
Host smart-fcc93cd2-9b9a-48ff-bc16-a4ad8646333b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281556090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3281556090
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2770542244
Short name T443
Test name
Test status
Simulation time 125984206375 ps
CPU time 175.8 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:19:57 PM PDT 24
Peak memory 182864 kb
Host smart-84f79da8-db07-4157-9057-6ae7ba44ec94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770542244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2770542244
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3152723623
Short name T401
Test name
Test status
Simulation time 83976585 ps
CPU time 0.59 seconds
Started Jun 07 06:16:55 PM PDT 24
Finished Jun 07 06:16:56 PM PDT 24
Peak memory 182780 kb
Host smart-755ddb06-90a9-436a-8dd8-6b6feb15373f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152723623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3152723623
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.350585077
Short name T118
Test name
Test status
Simulation time 3101796963530 ps
CPU time 897.23 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:32:00 PM PDT 24
Peak memory 196584 kb
Host smart-c56867d2-942f-45de-ad59-19a5db26afb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350585077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
350585077
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.208643498
Short name T50
Test name
Test status
Simulation time 19252082909 ps
CPU time 71.9 seconds
Started Jun 07 06:17:00 PM PDT 24
Finished Jun 07 06:18:12 PM PDT 24
Peak memory 197628 kb
Host smart-ff159d1e-ceb4-44e7-907e-6f738355c5ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208643498 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.208643498
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2042696253
Short name T347
Test name
Test status
Simulation time 178592936557 ps
CPU time 165.13 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:19:45 PM PDT 24
Peak memory 182860 kb
Host smart-f3bb6bf9-213d-4606-bab6-8a187b1fbdc8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042696253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2042696253
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.280221752
Short name T412
Test name
Test status
Simulation time 631737788792 ps
CPU time 275.14 seconds
Started Jun 07 06:17:04 PM PDT 24
Finished Jun 07 06:21:40 PM PDT 24
Peak memory 182800 kb
Host smart-6ad4c923-89e9-4387-9a45-0fd360ede344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280221752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.280221752
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1599687663
Short name T3
Test name
Test status
Simulation time 150008409180 ps
CPU time 125.69 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:19:08 PM PDT 24
Peak memory 191208 kb
Host smart-a2ecf3ce-8a6b-477e-8d70-2f6595ad5dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599687663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1599687663
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1472156732
Short name T143
Test name
Test status
Simulation time 22833165523 ps
CPU time 39.71 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:17:43 PM PDT 24
Peak memory 191016 kb
Host smart-fafeae60-20e9-4e57-8a36-50f7e3f790aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472156732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1472156732
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3668479036
Short name T415
Test name
Test status
Simulation time 420051070036 ps
CPU time 165.85 seconds
Started Jun 07 06:17:10 PM PDT 24
Finished Jun 07 06:19:56 PM PDT 24
Peak memory 194476 kb
Host smart-444cb6d1-44aa-4e59-8a82-7ce3cc3a1789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668479036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3668479036
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2421334931
Short name T335
Test name
Test status
Simulation time 1920775943 ps
CPU time 3.96 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:17:03 PM PDT 24
Peak memory 182640 kb
Host smart-fd8d5e89-414d-4186-95b3-6c6625d7cfb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421334931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2421334931
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.85376173
Short name T365
Test name
Test status
Simulation time 90742518788 ps
CPU time 75.62 seconds
Started Jun 07 06:17:00 PM PDT 24
Finished Jun 07 06:18:16 PM PDT 24
Peak memory 182860 kb
Host smart-72cc91af-98a1-4bf5-8ccf-5949c827430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85376173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.85376173
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1615061870
Short name T123
Test name
Test status
Simulation time 328710682232 ps
CPU time 342.89 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:22:43 PM PDT 24
Peak memory 191092 kb
Host smart-960db834-f054-4146-9d6e-853ada2b5037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615061870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1615061870
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2795115582
Short name T454
Test name
Test status
Simulation time 29560739810 ps
CPU time 144.9 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:19:24 PM PDT 24
Peak memory 182988 kb
Host smart-ded49ebb-f6a3-4f1b-a42e-ddcfcd0bf57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795115582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2795115582
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4050880135
Short name T35
Test name
Test status
Simulation time 38691262267 ps
CPU time 55.74 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:17:57 PM PDT 24
Peak memory 182880 kb
Host smart-8b112d11-cc5a-4989-988d-6201d933a5dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050880135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4050880135
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.378712027
Short name T431
Test name
Test status
Simulation time 123715833406 ps
CPU time 213.33 seconds
Started Jun 07 06:16:55 PM PDT 24
Finished Jun 07 06:20:29 PM PDT 24
Peak memory 182828 kb
Host smart-5139c11e-1d3c-4757-ad9e-95c081ad7253
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378712027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.378712027
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3743993517
Short name T19
Test name
Test status
Simulation time 74328008434 ps
CPU time 58.1 seconds
Started Jun 07 06:16:57 PM PDT 24
Finished Jun 07 06:17:56 PM PDT 24
Peak memory 182956 kb
Host smart-918c2c20-f174-4cf3-bf10-648eb9998796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743993517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3743993517
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2364667152
Short name T154
Test name
Test status
Simulation time 31594823416 ps
CPU time 48.57 seconds
Started Jun 07 06:17:00 PM PDT 24
Finished Jun 07 06:17:49 PM PDT 24
Peak memory 191088 kb
Host smart-1557e1cf-8db8-4a2f-8d99-c27b575df7a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364667152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2364667152
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2233400679
Short name T449
Test name
Test status
Simulation time 459320649 ps
CPU time 1.31 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:17:02 PM PDT 24
Peak memory 190968 kb
Host smart-031d2534-5ee2-4c70-97c0-a62330cb0a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233400679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2233400679
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3981008026
Short name T416
Test name
Test status
Simulation time 95523977221 ps
CPU time 49.41 seconds
Started Jun 07 06:16:58 PM PDT 24
Finished Jun 07 06:17:48 PM PDT 24
Peak memory 182924 kb
Host smart-cb23c29c-cf5c-4e05-88cf-cf112ce76795
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981008026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3981008026
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3883425240
Short name T358
Test name
Test status
Simulation time 28732970093 ps
CPU time 45.61 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:17:49 PM PDT 24
Peak memory 182940 kb
Host smart-c4e84f0f-01b0-4cd8-afd6-7b189bed07a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883425240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3883425240
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.56539192
Short name T336
Test name
Test status
Simulation time 115649324081 ps
CPU time 52.87 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:17:55 PM PDT 24
Peak memory 182892 kb
Host smart-8992a165-592f-48ab-927e-3cbf9fcf061c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56539192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.56539192
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1633359590
Short name T251
Test name
Test status
Simulation time 34128365646 ps
CPU time 31.44 seconds
Started Jun 07 06:17:04 PM PDT 24
Finished Jun 07 06:17:36 PM PDT 24
Peak memory 194400 kb
Host smart-841ab719-9509-4f40-a116-db59a6ae4924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633359590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1633359590
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4234501839
Short name T141
Test name
Test status
Simulation time 1832301164346 ps
CPU time 2684.86 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 07:01:47 PM PDT 24
Peak memory 195856 kb
Host smart-6749e541-18cc-4492-b8d2-63e0ea9f05f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234501839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4234501839
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4112610565
Short name T156
Test name
Test status
Simulation time 954699760491 ps
CPU time 229.5 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:20:51 PM PDT 24
Peak memory 182856 kb
Host smart-a5cf0449-c9a0-4f40-99e1-57b350259e59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112610565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4112610565
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3342668382
Short name T408
Test name
Test status
Simulation time 100523259152 ps
CPU time 146.56 seconds
Started Jun 07 06:16:57 PM PDT 24
Finished Jun 07 06:19:24 PM PDT 24
Peak memory 182904 kb
Host smart-02f7e549-f5c1-400f-ba2e-77a58f3b7a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342668382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3342668382
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1573526539
Short name T411
Test name
Test status
Simulation time 400838956699 ps
CPU time 184.71 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:20:08 PM PDT 24
Peak memory 191088 kb
Host smart-b614f63e-2c5e-4762-899d-27a31195254b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573526539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1573526539
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2340157313
Short name T441
Test name
Test status
Simulation time 27678626402 ps
CPU time 43.76 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:17:46 PM PDT 24
Peak memory 182880 kb
Host smart-b897879e-9cce-4808-b02b-bd7e64d8123c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340157313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2340157313
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.4218151771
Short name T201
Test name
Test status
Simulation time 1222663360258 ps
CPU time 855.94 seconds
Started Jun 07 06:17:04 PM PDT 24
Finished Jun 07 06:31:20 PM PDT 24
Peak memory 191080 kb
Host smart-52caa9b1-ce27-4d2c-bd71-ea83c48341cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218151771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.4218151771
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.264391805
Short name T134
Test name
Test status
Simulation time 15586035177 ps
CPU time 8.42 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:17:11 PM PDT 24
Peak memory 182876 kb
Host smart-83eba814-2a54-4375-a01d-e1360ade69ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264391805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.264391805
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1128847597
Short name T406
Test name
Test status
Simulation time 8529250970 ps
CPU time 13.05 seconds
Started Jun 07 06:16:56 PM PDT 24
Finished Jun 07 06:17:09 PM PDT 24
Peak memory 182952 kb
Host smart-52e47425-5955-45ff-8e6a-7a26a4b33eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128847597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1128847597
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.4132206416
Short name T309
Test name
Test status
Simulation time 239334968374 ps
CPU time 448.36 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:24:32 PM PDT 24
Peak memory 191100 kb
Host smart-39e1f98e-5230-433c-81f9-468ab30d6b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132206416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.4132206416
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2817827847
Short name T307
Test name
Test status
Simulation time 30845800401 ps
CPU time 53.39 seconds
Started Jun 07 06:16:59 PM PDT 24
Finished Jun 07 06:17:53 PM PDT 24
Peak memory 191064 kb
Host smart-66e95120-721f-4c13-9ae6-c355911dacea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817827847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2817827847
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.210662490
Short name T329
Test name
Test status
Simulation time 337313483730 ps
CPU time 603.68 seconds
Started Jun 07 06:17:09 PM PDT 24
Finished Jun 07 06:27:13 PM PDT 24
Peak memory 182976 kb
Host smart-944b508c-3438-4299-beba-85cbbed550e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210662490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.210662490
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3511134075
Short name T453
Test name
Test status
Simulation time 626552010084 ps
CPU time 294.46 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:22:10 PM PDT 24
Peak memory 182920 kb
Host smart-7cee6364-4038-4da3-82a1-ed5de22d4120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511134075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3511134075
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4080958965
Short name T246
Test name
Test status
Simulation time 330720837547 ps
CPU time 97.69 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:18:41 PM PDT 24
Peak memory 194700 kb
Host smart-1cb2b9f1-c227-4d41-88f9-5c89aa94e4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080958965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4080958965
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1337841930
Short name T218
Test name
Test status
Simulation time 382812032647 ps
CPU time 329.27 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:22:46 PM PDT 24
Peak memory 182884 kb
Host smart-f591ad6a-33cd-4f05-9bf8-57045b0e7075
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337841930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1337841930
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.837482957
Short name T362
Test name
Test status
Simulation time 206048984335 ps
CPU time 169.26 seconds
Started Jun 07 06:17:05 PM PDT 24
Finished Jun 07 06:19:55 PM PDT 24
Peak memory 182976 kb
Host smart-6234c0df-8505-4429-a44a-db0d1d91061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837482957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.837482957
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.338157243
Short name T58
Test name
Test status
Simulation time 187093666435 ps
CPU time 88.42 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:18:40 PM PDT 24
Peak memory 191092 kb
Host smart-115a18eb-09b4-41b2-9c01-a1653c28df55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338157243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.338157243
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2179983554
Short name T353
Test name
Test status
Simulation time 119160872467 ps
CPU time 717.87 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:29:01 PM PDT 24
Peak memory 182820 kb
Host smart-e3b75d81-219b-4a32-92bf-420ce05239af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179983554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2179983554
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2905469337
Short name T364
Test name
Test status
Simulation time 259103138005 ps
CPU time 392.43 seconds
Started Jun 07 06:17:05 PM PDT 24
Finished Jun 07 06:23:38 PM PDT 24
Peak memory 194892 kb
Host smart-e8bf1545-57d6-41c6-8e25-14ac887aff5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905469337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2905469337
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.926681920
Short name T105
Test name
Test status
Simulation time 274590491816 ps
CPU time 155.69 seconds
Started Jun 07 06:16:38 PM PDT 24
Finished Jun 07 06:19:14 PM PDT 24
Peak memory 182852 kb
Host smart-33f72ec8-830a-4552-9141-1b36333c375a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926681920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.926681920
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2963096318
Short name T359
Test name
Test status
Simulation time 6125571101 ps
CPU time 4.97 seconds
Started Jun 07 06:16:38 PM PDT 24
Finished Jun 07 06:16:44 PM PDT 24
Peak memory 182848 kb
Host smart-d488979f-c972-40e1-878d-092803796158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963096318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2963096318
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2430780396
Short name T346
Test name
Test status
Simulation time 263013335632 ps
CPU time 141.34 seconds
Started Jun 07 06:16:50 PM PDT 24
Finished Jun 07 06:19:11 PM PDT 24
Peak memory 191052 kb
Host smart-300b6d2f-6d1a-456f-a3e8-7ef2cd66999a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430780396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2430780396
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1341514809
Short name T140
Test name
Test status
Simulation time 64192783781 ps
CPU time 98.23 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:18:28 PM PDT 24
Peak memory 182980 kb
Host smart-04bb29e7-a0c3-4e2c-a66b-e03499c91bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341514809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1341514809
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3370389531
Short name T18
Test name
Test status
Simulation time 109950624 ps
CPU time 0.85 seconds
Started Jun 07 06:16:34 PM PDT 24
Finished Jun 07 06:16:36 PM PDT 24
Peak memory 213360 kb
Host smart-697b2e10-b588-4d78-8dfc-c900e8ee7c52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370389531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3370389531
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3802137980
Short name T404
Test name
Test status
Simulation time 814244547186 ps
CPU time 424.83 seconds
Started Jun 07 06:17:08 PM PDT 24
Finished Jun 07 06:24:13 PM PDT 24
Peak memory 182984 kb
Host smart-68be4c23-995c-47a3-bf24-88f1970f8173
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802137980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3802137980
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3182642020
Short name T421
Test name
Test status
Simulation time 123345208777 ps
CPU time 120.4 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:19:08 PM PDT 24
Peak memory 182968 kb
Host smart-c1d0929f-f536-4034-b2a5-32889f2d6ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182642020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3182642020
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3413197474
Short name T275
Test name
Test status
Simulation time 140454901726 ps
CPU time 729.19 seconds
Started Jun 07 06:17:02 PM PDT 24
Finished Jun 07 06:29:12 PM PDT 24
Peak memory 190996 kb
Host smart-be3c4558-6e64-4759-b1c3-51425d9395e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413197474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3413197474
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3431288779
Short name T282
Test name
Test status
Simulation time 200556287592 ps
CPU time 377.56 seconds
Started Jun 07 06:17:06 PM PDT 24
Finished Jun 07 06:23:24 PM PDT 24
Peak memory 194472 kb
Host smart-b9af7c5e-6bfb-4c76-bab6-c5c1bde06083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431288779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3431288779
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.4025494887
Short name T322
Test name
Test status
Simulation time 1130797012071 ps
CPU time 535.84 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:26:07 PM PDT 24
Peak memory 191080 kb
Host smart-d6f6a258-45ba-4034-8a8d-033b243e4c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025494887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.4025494887
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2687538976
Short name T150
Test name
Test status
Simulation time 549370711000 ps
CPU time 303.29 seconds
Started Jun 07 06:17:08 PM PDT 24
Finished Jun 07 06:22:12 PM PDT 24
Peak memory 182840 kb
Host smart-0fb4c18a-11c2-4e69-87cd-c911dbf10e1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687538976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2687538976
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.989662080
Short name T376
Test name
Test status
Simulation time 39328549810 ps
CPU time 64.84 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:18:21 PM PDT 24
Peak memory 182868 kb
Host smart-620204b5-7797-40b0-8509-f50a0cdf0c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989662080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.989662080
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3632314193
Short name T425
Test name
Test status
Simulation time 168690900037 ps
CPU time 57.5 seconds
Started Jun 07 06:17:06 PM PDT 24
Finished Jun 07 06:18:04 PM PDT 24
Peak memory 182856 kb
Host smart-1a2aa438-9aa4-42a8-a216-5d9082f99044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632314193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3632314193
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.4101866171
Short name T432
Test name
Test status
Simulation time 63139438310 ps
CPU time 115.32 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:19:03 PM PDT 24
Peak memory 191168 kb
Host smart-018e62e7-f0fa-4de8-af5e-ce65ff72b7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101866171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.4101866171
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.1121711639
Short name T41
Test name
Test status
Simulation time 45263745819 ps
CPU time 465.35 seconds
Started Jun 07 06:17:05 PM PDT 24
Finished Jun 07 06:24:51 PM PDT 24
Peak memory 205732 kb
Host smart-b8f8826f-b177-4608-9bdb-8774f14b328c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121711639 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.1121711639
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1104274622
Short name T344
Test name
Test status
Simulation time 591559781559 ps
CPU time 302.3 seconds
Started Jun 07 06:17:08 PM PDT 24
Finished Jun 07 06:22:11 PM PDT 24
Peak memory 182972 kb
Host smart-6e9bd79d-d23a-4ce6-b52d-ba1195901755
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104274622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1104274622
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1271184825
Short name T386
Test name
Test status
Simulation time 45464863225 ps
CPU time 17.66 seconds
Started Jun 07 06:17:08 PM PDT 24
Finished Jun 07 06:17:26 PM PDT 24
Peak memory 182968 kb
Host smart-578b9172-7153-4cf7-8c1e-ce47326b5573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271184825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1271184825
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1533087667
Short name T138
Test name
Test status
Simulation time 188451770454 ps
CPU time 646.74 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:28:02 PM PDT 24
Peak memory 191068 kb
Host smart-f8e58562-b0af-4068-b595-e4699824802b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533087667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1533087667
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2218606211
Short name T434
Test name
Test status
Simulation time 406445175223 ps
CPU time 1476.42 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:41:44 PM PDT 24
Peak memory 191088 kb
Host smart-5306fd04-c40b-4033-abbf-756c6fe4a51c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218606211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2218606211
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1432775550
Short name T13
Test name
Test status
Simulation time 11073151778 ps
CPU time 120.12 seconds
Started Jun 07 06:17:03 PM PDT 24
Finished Jun 07 06:19:04 PM PDT 24
Peak memory 197636 kb
Host smart-5a3c4ea9-3739-44d5-9bd7-89ce40988d65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432775550 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1432775550
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1559343414
Short name T305
Test name
Test status
Simulation time 8364699808 ps
CPU time 16.35 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:17:32 PM PDT 24
Peak memory 182884 kb
Host smart-b53fe85c-6d87-4717-9907-db283ca5aba0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559343414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1559343414
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3900073083
Short name T455
Test name
Test status
Simulation time 93495941171 ps
CPU time 127.67 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:19:22 PM PDT 24
Peak memory 182984 kb
Host smart-361c3ee8-05f0-4cfa-bf0d-48c8c7580ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900073083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3900073083
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.4172857491
Short name T117
Test name
Test status
Simulation time 458594575673 ps
CPU time 197.06 seconds
Started Jun 07 06:17:13 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 191040 kb
Host smart-0c947b4e-182e-437d-bde6-10c346fe7278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172857491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4172857491
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.4226191745
Short name T292
Test name
Test status
Simulation time 90616156444 ps
CPU time 172.05 seconds
Started Jun 07 06:17:06 PM PDT 24
Finished Jun 07 06:19:58 PM PDT 24
Peak memory 194956 kb
Host smart-64c5826b-ac85-4255-a5e2-a08a198b1f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226191745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4226191745
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1416679007
Short name T42
Test name
Test status
Simulation time 37995165018 ps
CPU time 162.47 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:19:49 PM PDT 24
Peak memory 197600 kb
Host smart-3d1c9465-bca1-4f65-804e-1810ac58cc19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416679007 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1416679007
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.4175372532
Short name T245
Test name
Test status
Simulation time 5954553712 ps
CPU time 5.64 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:17:08 PM PDT 24
Peak memory 183004 kb
Host smart-dd4c0dd7-8fc5-4fb1-89c1-d03f8d89dd82
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175372532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.4175372532
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1888571605
Short name T402
Test name
Test status
Simulation time 505285583204 ps
CPU time 215.47 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:20:50 PM PDT 24
Peak memory 182808 kb
Host smart-5f66a6a9-0ec2-427b-851a-181fd6650198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888571605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1888571605
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1325577723
Short name T323
Test name
Test status
Simulation time 279561549698 ps
CPU time 314.17 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:22:21 PM PDT 24
Peak memory 191052 kb
Host smart-6c2e7b4c-c2e6-4249-92d6-8b5c98c149d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325577723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1325577723
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.590357461
Short name T300
Test name
Test status
Simulation time 179593387612 ps
CPU time 998.61 seconds
Started Jun 07 06:17:06 PM PDT 24
Finished Jun 07 06:33:45 PM PDT 24
Peak memory 191348 kb
Host smart-c9793981-906f-4cae-9a4a-515bbea1c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590357461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.590357461
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3773181538
Short name T430
Test name
Test status
Simulation time 763640986334 ps
CPU time 331.55 seconds
Started Jun 07 06:17:09 PM PDT 24
Finished Jun 07 06:22:41 PM PDT 24
Peak memory 182968 kb
Host smart-26a8152d-d514-4839-9235-fe219b400b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773181538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3773181538
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2205218491
Short name T286
Test name
Test status
Simulation time 407487254665 ps
CPU time 665.16 seconds
Started Jun 07 06:17:05 PM PDT 24
Finished Jun 07 06:28:11 PM PDT 24
Peak memory 182892 kb
Host smart-12646cc2-412a-4839-8666-15b53a3e6d4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205218491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2205218491
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2159525200
Short name T395
Test name
Test status
Simulation time 175537290040 ps
CPU time 135.56 seconds
Started Jun 07 06:17:05 PM PDT 24
Finished Jun 07 06:19:21 PM PDT 24
Peak memory 182984 kb
Host smart-44f74998-35c4-4ede-b553-a8681b5bac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159525200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2159525200
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3133594036
Short name T400
Test name
Test status
Simulation time 105978887036 ps
CPU time 118.89 seconds
Started Jun 07 06:17:05 PM PDT 24
Finished Jun 07 06:19:04 PM PDT 24
Peak memory 182984 kb
Host smart-1d546437-60c9-4105-a5d9-4cda7b7fbbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133594036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3133594036
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3003606059
Short name T46
Test name
Test status
Simulation time 224092059823 ps
CPU time 222.1 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:20:58 PM PDT 24
Peak memory 182880 kb
Host smart-326b137e-8a0c-433a-abad-898c721e36cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003606059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3003606059
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.938841837
Short name T424
Test name
Test status
Simulation time 149354746212 ps
CPU time 117.72 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:19:13 PM PDT 24
Peak memory 182852 kb
Host smart-162134a6-336a-47c3-8cf4-34db4d2bbfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938841837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.938841837
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1750602304
Short name T302
Test name
Test status
Simulation time 553173746008 ps
CPU time 955.22 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:33:03 PM PDT 24
Peak memory 191176 kb
Host smart-fc0558af-c10a-40ed-ac33-f75f4c9bbbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750602304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1750602304
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1514882476
Short name T355
Test name
Test status
Simulation time 1416131877 ps
CPU time 1.21 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:17:16 PM PDT 24
Peak memory 182656 kb
Host smart-a4ba9fef-9c2f-4ba1-af38-fcef28870466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514882476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1514882476
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.740356201
Short name T444
Test name
Test status
Simulation time 864044987036 ps
CPU time 718.28 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:29:13 PM PDT 24
Peak memory 195172 kb
Host smart-4db3499f-f8dd-4e3f-8ea5-6ee7b9a7f567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740356201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
740356201
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.1211229219
Short name T39
Test name
Test status
Simulation time 20438209991 ps
CPU time 196.56 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:20:31 PM PDT 24
Peak memory 197492 kb
Host smart-0fa8b3f7-82a2-490f-9c9b-6de8b7224d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211229219 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.1211229219
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3604538299
Short name T145
Test name
Test status
Simulation time 789629128432 ps
CPU time 815.2 seconds
Started Jun 07 06:17:13 PM PDT 24
Finished Jun 07 06:30:49 PM PDT 24
Peak memory 182980 kb
Host smart-8b1f98e8-b39e-4f8f-8cd0-12c0cf7caf21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604538299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3604538299
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2305044106
Short name T368
Test name
Test status
Simulation time 178930275312 ps
CPU time 250.83 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:21:27 PM PDT 24
Peak memory 182868 kb
Host smart-5aaeea7a-0d0a-4231-8d7c-7266085d4cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305044106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2305044106
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3712461919
Short name T10
Test name
Test status
Simulation time 965214396567 ps
CPU time 179.64 seconds
Started Jun 07 06:17:07 PM PDT 24
Finished Jun 07 06:20:07 PM PDT 24
Peak memory 191176 kb
Host smart-3ad6a90f-7fc2-4357-8971-689c40e2ef13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712461919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3712461919
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1019204362
Short name T5
Test name
Test status
Simulation time 22479704396 ps
CPU time 16.37 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:17:31 PM PDT 24
Peak memory 190992 kb
Host smart-8418f7ef-18d7-4c0d-85f4-08f47e21d5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019204362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1019204362
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3572705652
Short name T235
Test name
Test status
Simulation time 1388733008507 ps
CPU time 668.73 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:28:20 PM PDT 24
Peak memory 191196 kb
Host smart-835d7e90-edf3-447f-8cae-2522af7e1c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572705652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3572705652
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3677408954
Short name T299
Test name
Test status
Simulation time 475500048970 ps
CPU time 246.88 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:21:23 PM PDT 24
Peak memory 182884 kb
Host smart-58cfb810-9310-4349-ba22-86757217a926
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677408954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3677408954
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.928169403
Short name T357
Test name
Test status
Simulation time 258568725061 ps
CPU time 48.87 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:18:03 PM PDT 24
Peak memory 182824 kb
Host smart-e243a5ec-1aa1-4e5c-90ba-acba4d22ee66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928169403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.928169403
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.315720093
Short name T324
Test name
Test status
Simulation time 139997498877 ps
CPU time 519.35 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:25:51 PM PDT 24
Peak memory 191040 kb
Host smart-835c7021-5189-48f7-a407-55b2b4118488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315720093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.315720093
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.4282299121
Short name T174
Test name
Test status
Simulation time 53620302990 ps
CPU time 118.86 seconds
Started Jun 07 06:17:17 PM PDT 24
Finished Jun 07 06:19:16 PM PDT 24
Peak memory 182960 kb
Host smart-eb040bf0-ea56-40fa-83ac-50b93d6e3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282299121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4282299121
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1234924360
Short name T437
Test name
Test status
Simulation time 6722868618 ps
CPU time 12.88 seconds
Started Jun 07 06:17:23 PM PDT 24
Finished Jun 07 06:17:36 PM PDT 24
Peak memory 182992 kb
Host smart-3fbdfaf1-f29c-41bc-873f-958cc2b9e042
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234924360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1234924360
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2789687323
Short name T369
Test name
Test status
Simulation time 80054899415 ps
CPU time 73.21 seconds
Started Jun 07 06:17:13 PM PDT 24
Finished Jun 07 06:18:27 PM PDT 24
Peak memory 182868 kb
Host smart-30caee2f-c5b0-4ffa-9b59-78d6788e40ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789687323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2789687323
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2991688326
Short name T457
Test name
Test status
Simulation time 2520487625 ps
CPU time 4.89 seconds
Started Jun 07 06:17:18 PM PDT 24
Finished Jun 07 06:17:23 PM PDT 24
Peak memory 182892 kb
Host smart-857e506c-9c0d-43f6-9df1-d3d2245547c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991688326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2991688326
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1748984195
Short name T142
Test name
Test status
Simulation time 378225000985 ps
CPU time 566.87 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:26:43 PM PDT 24
Peak memory 191176 kb
Host smart-6bd71423-3d55-4488-88b4-8debce68d538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748984195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1748984195
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2348077552
Short name T373
Test name
Test status
Simulation time 60519506 ps
CPU time 0.53 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:17:12 PM PDT 24
Peak memory 182324 kb
Host smart-18b417f6-b01c-4573-97c5-45b749759305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348077552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2348077552
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2398784672
Short name T399
Test name
Test status
Simulation time 4118622261 ps
CPU time 7.62 seconds
Started Jun 07 06:16:48 PM PDT 24
Finished Jun 07 06:16:57 PM PDT 24
Peak memory 182952 kb
Host smart-293546a4-05bd-47cc-ac62-78e4d8aa6697
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398784672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2398784672
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2904458285
Short name T380
Test name
Test status
Simulation time 199313967685 ps
CPU time 197.1 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:20:07 PM PDT 24
Peak memory 182984 kb
Host smart-3d84071d-630e-4cda-a44c-91ff103bed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904458285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2904458285
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2036477486
Short name T349
Test name
Test status
Simulation time 49615647208 ps
CPU time 627.38 seconds
Started Jun 07 06:16:42 PM PDT 24
Finished Jun 07 06:27:10 PM PDT 24
Peak memory 191212 kb
Host smart-2ee9b564-5773-47b1-9ed8-55c84e41047b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036477486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2036477486
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.774571025
Short name T328
Test name
Test status
Simulation time 65648506062 ps
CPU time 92.29 seconds
Started Jun 07 06:16:46 PM PDT 24
Finished Jun 07 06:18:19 PM PDT 24
Peak memory 194720 kb
Host smart-3e6ce863-c7ae-4bb4-b7cb-2b2c19d06df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774571025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.774571025
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.362913764
Short name T171
Test name
Test status
Simulation time 86324655639 ps
CPU time 640.93 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:27:56 PM PDT 24
Peak memory 191088 kb
Host smart-d51e87cc-8c8f-4973-a413-414276749506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362913764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.362913764
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4101611441
Short name T64
Test name
Test status
Simulation time 19080202394 ps
CPU time 28.91 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:17:46 PM PDT 24
Peak memory 191092 kb
Host smart-0b139933-9a9a-4a42-b0fd-26ed1bcbfdfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101611441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4101611441
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2298446668
Short name T192
Test name
Test status
Simulation time 238161530910 ps
CPU time 384 seconds
Started Jun 07 06:17:13 PM PDT 24
Finished Jun 07 06:23:37 PM PDT 24
Peak memory 191096 kb
Host smart-6353bae9-50b6-472f-8a1b-b0c1ec22bd70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298446668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2298446668
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3800777645
Short name T221
Test name
Test status
Simulation time 79658946999 ps
CPU time 133.75 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:19:30 PM PDT 24
Peak memory 191100 kb
Host smart-f9f36f9a-9084-4e77-b176-80587555157d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800777645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3800777645
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1837544868
Short name T63
Test name
Test status
Simulation time 170985052421 ps
CPU time 505.73 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:25:42 PM PDT 24
Peak memory 191092 kb
Host smart-05f6858e-cdac-4df6-9fc9-9ff1cabdce5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837544868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1837544868
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3158760159
Short name T343
Test name
Test status
Simulation time 259013671682 ps
CPU time 759.05 seconds
Started Jun 07 06:17:18 PM PDT 24
Finished Jun 07 06:29:58 PM PDT 24
Peak memory 194496 kb
Host smart-4976a901-dad3-4e50-810a-66ab28a19dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158760159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3158760159
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1042950614
Short name T413
Test name
Test status
Simulation time 27175637955 ps
CPU time 37.89 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:17:52 PM PDT 24
Peak memory 182676 kb
Host smart-8e11fba4-58ca-448d-a9b5-abe55df56c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042950614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1042950614
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.155046862
Short name T284
Test name
Test status
Simulation time 675548550118 ps
CPU time 386.52 seconds
Started Jun 07 06:17:20 PM PDT 24
Finished Jun 07 06:23:47 PM PDT 24
Peak memory 191088 kb
Host smart-d6455651-bb6a-4f77-bb2d-6992b0be7a33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155046862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.155046862
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1921594666
Short name T119
Test name
Test status
Simulation time 9404973855 ps
CPU time 5.63 seconds
Started Jun 07 06:16:42 PM PDT 24
Finished Jun 07 06:16:48 PM PDT 24
Peak memory 182872 kb
Host smart-ed82ec02-2a8f-4655-aeaa-b2f2b0992d8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921594666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1921594666
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2797275457
Short name T433
Test name
Test status
Simulation time 67227674989 ps
CPU time 55.08 seconds
Started Jun 07 06:16:51 PM PDT 24
Finished Jun 07 06:17:47 PM PDT 24
Peak memory 182856 kb
Host smart-a9c0fd7b-27a2-4819-8e41-b9553614d592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797275457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2797275457
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1490692902
Short name T418
Test name
Test status
Simulation time 10613790747 ps
CPU time 18.01 seconds
Started Jun 07 06:16:39 PM PDT 24
Finished Jun 07 06:16:58 PM PDT 24
Peak memory 182988 kb
Host smart-13fdaa15-6045-4cd7-963d-9dcd39bf04ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490692902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1490692902
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2571345112
Short name T280
Test name
Test status
Simulation time 26949127572 ps
CPU time 34.18 seconds
Started Jun 07 06:16:32 PM PDT 24
Finished Jun 07 06:17:07 PM PDT 24
Peak memory 191064 kb
Host smart-38d5a218-47e3-4915-afdc-61c318c0f3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571345112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2571345112
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1040419659
Short name T438
Test name
Test status
Simulation time 24038898980 ps
CPU time 42.56 seconds
Started Jun 07 06:17:14 PM PDT 24
Finished Jun 07 06:17:57 PM PDT 24
Peak memory 191072 kb
Host smart-c6cd0b2c-883d-417e-ac92-e5a094e66a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040419659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1040419659
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3507146992
Short name T178
Test name
Test status
Simulation time 374859992355 ps
CPU time 203.06 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:20:40 PM PDT 24
Peak memory 191204 kb
Host smart-bb1bac90-530e-4b2e-973e-d7b12893d2f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507146992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3507146992
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1596709375
Short name T184
Test name
Test status
Simulation time 19878460121 ps
CPU time 29.2 seconds
Started Jun 07 06:17:20 PM PDT 24
Finished Jun 07 06:17:50 PM PDT 24
Peak memory 191092 kb
Host smart-cd6c2576-e584-4ae4-a26e-2496d5b22174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596709375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1596709375
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1972274229
Short name T303
Test name
Test status
Simulation time 371443625819 ps
CPU time 646.2 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:28:03 PM PDT 24
Peak memory 191084 kb
Host smart-2dc4821e-363f-4b62-96bb-6502f490e301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972274229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1972274229
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2370970945
Short name T297
Test name
Test status
Simulation time 325370805426 ps
CPU time 853.82 seconds
Started Jun 07 06:17:09 PM PDT 24
Finished Jun 07 06:31:23 PM PDT 24
Peak memory 191084 kb
Host smart-8f87899d-b0dd-477c-b022-0054491fa073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370970945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2370970945
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.49223252
Short name T304
Test name
Test status
Simulation time 103381646170 ps
CPU time 233.93 seconds
Started Jun 07 06:17:11 PM PDT 24
Finished Jun 07 06:21:06 PM PDT 24
Peak memory 182952 kb
Host smart-5ab1b14f-e78f-470b-8210-3ff350bc626a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49223252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.49223252
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2157890706
Short name T231
Test name
Test status
Simulation time 124868402658 ps
CPU time 285.84 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:22:02 PM PDT 24
Peak memory 194752 kb
Host smart-086998a9-84e3-4d6e-9842-011674acb1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157890706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2157890706
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3453427911
Short name T21
Test name
Test status
Simulation time 2614832275348 ps
CPU time 867.02 seconds
Started Jun 07 06:16:50 PM PDT 24
Finished Jun 07 06:31:18 PM PDT 24
Peak memory 182864 kb
Host smart-262398be-1864-4373-ac63-24d5b45f2894
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453427911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3453427911
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.101158888
Short name T384
Test name
Test status
Simulation time 8693679307 ps
CPU time 3.96 seconds
Started Jun 07 06:16:44 PM PDT 24
Finished Jun 07 06:16:49 PM PDT 24
Peak memory 182688 kb
Host smart-aa93c74b-642c-43d4-9a42-d7b4604c6e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101158888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.101158888
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2131209450
Short name T308
Test name
Test status
Simulation time 59359637208 ps
CPU time 93.6 seconds
Started Jun 07 06:16:41 PM PDT 24
Finished Jun 07 06:18:15 PM PDT 24
Peak memory 191064 kb
Host smart-336fe436-88ab-45fe-b0f2-1e09dcb4c8b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131209450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2131209450
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2065385265
Short name T271
Test name
Test status
Simulation time 411668275809 ps
CPU time 238.68 seconds
Started Jun 07 06:16:57 PM PDT 24
Finished Jun 07 06:20:56 PM PDT 24
Peak memory 191180 kb
Host smart-0f5821c5-f752-4f9d-bd71-9011affdb0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065385265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2065385265
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.4279455769
Short name T315
Test name
Test status
Simulation time 171296852260 ps
CPU time 454.58 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:24:50 PM PDT 24
Peak memory 191192 kb
Host smart-f2f3e920-557d-4d6b-81ca-1438152c2dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279455769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4279455769
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1366951650
Short name T45
Test name
Test status
Simulation time 59787950118 ps
CPU time 23.98 seconds
Started Jun 07 06:17:23 PM PDT 24
Finished Jun 07 06:17:47 PM PDT 24
Peak memory 182760 kb
Host smart-794a8226-fa2e-4fb8-a62f-1058d19965a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366951650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1366951650
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.784421372
Short name T120
Test name
Test status
Simulation time 39015927831 ps
CPU time 79.97 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:18:35 PM PDT 24
Peak memory 182980 kb
Host smart-43a457f9-63e5-4eb4-8d43-4f7bae927631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784421372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.784421372
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2617108159
Short name T102
Test name
Test status
Simulation time 676524290843 ps
CPU time 724.32 seconds
Started Jun 07 06:17:12 PM PDT 24
Finished Jun 07 06:29:17 PM PDT 24
Peak memory 190996 kb
Host smart-b7938514-0253-4563-b6b9-5f2486ffa2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617108159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2617108159
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.445549658
Short name T107
Test name
Test status
Simulation time 536218858768 ps
CPU time 350.97 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:23:07 PM PDT 24
Peak memory 191096 kb
Host smart-edb0f4d2-5e17-4dfe-812b-5cd99b0a7406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445549658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.445549658
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3664153305
Short name T133
Test name
Test status
Simulation time 179666051451 ps
CPU time 538.18 seconds
Started Jun 07 06:17:12 PM PDT 24
Finished Jun 07 06:26:10 PM PDT 24
Peak memory 191204 kb
Host smart-d4e8b8d9-3aa3-4109-a386-d638e0b63efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664153305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3664153305
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2613717597
Short name T147
Test name
Test status
Simulation time 145890286188 ps
CPU time 654.84 seconds
Started Jun 07 06:17:12 PM PDT 24
Finished Jun 07 06:28:08 PM PDT 24
Peak memory 191200 kb
Host smart-43bb567a-a636-4eab-a656-bb578d488468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613717597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2613717597
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.410362721
Short name T442
Test name
Test status
Simulation time 591707837785 ps
CPU time 584.48 seconds
Started Jun 07 06:17:15 PM PDT 24
Finished Jun 07 06:27:00 PM PDT 24
Peak memory 191132 kb
Host smart-8a55acdd-4c8a-4e4b-bc75-d684cafaf8b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410362721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.410362721
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.314872697
Short name T169
Test name
Test status
Simulation time 125627109830 ps
CPU time 662.96 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:28:19 PM PDT 24
Peak memory 194568 kb
Host smart-41d7fa49-ef78-40aa-8dee-00e7ffa0a56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314872697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.314872697
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1214973234
Short name T274
Test name
Test status
Simulation time 282374930421 ps
CPU time 288.76 seconds
Started Jun 07 06:17:18 PM PDT 24
Finished Jun 07 06:22:07 PM PDT 24
Peak memory 194716 kb
Host smart-ceda5584-2733-4c16-ad14-b1cddde7751c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214973234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1214973234
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2132681607
Short name T407
Test name
Test status
Simulation time 41332148332 ps
CPU time 26.89 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:17:13 PM PDT 24
Peak memory 182972 kb
Host smart-c1ffdee2-144a-41f2-88be-276aa2b03ffa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132681607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2132681607
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3680590517
Short name T428
Test name
Test status
Simulation time 162086602916 ps
CPU time 22.83 seconds
Started Jun 07 06:16:50 PM PDT 24
Finished Jun 07 06:17:13 PM PDT 24
Peak memory 182920 kb
Host smart-71c4ac52-a42b-4462-9db0-8fd9f1bc44b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680590517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3680590517
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3969109391
Short name T104
Test name
Test status
Simulation time 39320547825 ps
CPU time 126.27 seconds
Started Jun 07 06:16:41 PM PDT 24
Finished Jun 07 06:18:48 PM PDT 24
Peak memory 191068 kb
Host smart-54cfda17-e7a3-4766-b3e5-41cdd0de5c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969109391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3969109391
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1381070672
Short name T186
Test name
Test status
Simulation time 87173209345 ps
CPU time 60.98 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:17:51 PM PDT 24
Peak memory 191040 kb
Host smart-9182094f-0c45-498f-b9be-f563d800d130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381070672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1381070672
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1216111706
Short name T366
Test name
Test status
Simulation time 122941381773 ps
CPU time 165.25 seconds
Started Jun 07 06:16:38 PM PDT 24
Finished Jun 07 06:19:23 PM PDT 24
Peak memory 194652 kb
Host smart-cff54081-8abb-4334-a646-fc34c8584c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216111706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1216111706
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.796559194
Short name T319
Test name
Test status
Simulation time 125237131074 ps
CPU time 404.38 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:24:01 PM PDT 24
Peak memory 191088 kb
Host smart-6bfed2b8-b53b-4a8f-a6e9-c7952bf98f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796559194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.796559194
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2958114235
Short name T429
Test name
Test status
Simulation time 2117177475 ps
CPU time 2.14 seconds
Started Jun 07 06:17:16 PM PDT 24
Finished Jun 07 06:17:19 PM PDT 24
Peak memory 182636 kb
Host smart-ed1b0705-a2b5-4b52-ad44-ac38bb8c46f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958114235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2958114235
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1533346114
Short name T233
Test name
Test status
Simulation time 616439139436 ps
CPU time 382.05 seconds
Started Jun 07 06:17:12 PM PDT 24
Finished Jun 07 06:23:35 PM PDT 24
Peak memory 191200 kb
Host smart-a00b96e9-ee1b-4fa6-9ec9-d85b15a6b396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533346114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1533346114
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.821181802
Short name T255
Test name
Test status
Simulation time 109491555240 ps
CPU time 812.53 seconds
Started Jun 07 06:17:21 PM PDT 24
Finished Jun 07 06:30:54 PM PDT 24
Peak memory 182988 kb
Host smart-c846de69-332c-47e2-8461-2e5b497f70cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821181802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.821181802
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2059535381
Short name T114
Test name
Test status
Simulation time 288413985115 ps
CPU time 347.97 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 06:23:08 PM PDT 24
Peak memory 191128 kb
Host smart-df68e8f4-a79d-4cc0-9ced-3b1c23f88052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059535381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2059535381
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1291029856
Short name T257
Test name
Test status
Simulation time 1621585100897 ps
CPU time 720.7 seconds
Started Jun 07 06:16:45 PM PDT 24
Finished Jun 07 06:28:47 PM PDT 24
Peak memory 182876 kb
Host smart-488647a2-53e1-43e4-8022-cc094cfe0e05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291029856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1291029856
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2222988892
Short name T403
Test name
Test status
Simulation time 126832881115 ps
CPU time 49.86 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:17:39 PM PDT 24
Peak memory 182824 kb
Host smart-4961ec62-7075-414b-b388-25b50b7beeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222988892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2222988892
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1782785308
Short name T234
Test name
Test status
Simulation time 645933988867 ps
CPU time 376.49 seconds
Started Jun 07 06:17:01 PM PDT 24
Finished Jun 07 06:23:18 PM PDT 24
Peak memory 191108 kb
Host smart-7c081c35-6bb1-4c36-9e12-8e9a8a5b6026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782785308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1782785308
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.188181043
Short name T385
Test name
Test status
Simulation time 2925804622 ps
CPU time 15.56 seconds
Started Jun 07 06:16:49 PM PDT 24
Finished Jun 07 06:17:05 PM PDT 24
Peak memory 191088 kb
Host smart-5f0a36f2-69f3-43e7-9814-f429f83668bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188181043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.188181043
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.2445335034
Short name T26
Test name
Test status
Simulation time 449478180835 ps
CPU time 995.78 seconds
Started Jun 07 06:17:17 PM PDT 24
Finished Jun 07 06:33:53 PM PDT 24
Peak memory 191180 kb
Host smart-00113a49-d141-4d70-85da-504950f7f569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445335034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2445335034
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3045008733
Short name T327
Test name
Test status
Simulation time 50172665267 ps
CPU time 34.94 seconds
Started Jun 07 06:17:19 PM PDT 24
Finished Jun 07 06:17:55 PM PDT 24
Peak memory 182752 kb
Host smart-24ff292a-2a65-4f3e-b4d1-a4941a57f90d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045008733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3045008733
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.4130295876
Short name T339
Test name
Test status
Simulation time 154573921985 ps
CPU time 134.59 seconds
Started Jun 07 06:17:20 PM PDT 24
Finished Jun 07 06:19:35 PM PDT 24
Peak memory 182892 kb
Host smart-1e0c4a71-6177-408d-a2e8-a4f08366e1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130295876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4130295876
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1311989229
Short name T342
Test name
Test status
Simulation time 11468599940 ps
CPU time 14.16 seconds
Started Jun 07 06:17:22 PM PDT 24
Finished Jun 07 06:17:37 PM PDT 24
Peak memory 191076 kb
Host smart-c9459570-bc52-475f-bdb1-3b9531ab3921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311989229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1311989229
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1869586669
Short name T202
Test name
Test status
Simulation time 427497182005 ps
CPU time 148.82 seconds
Started Jun 07 06:17:20 PM PDT 24
Finished Jun 07 06:19:49 PM PDT 24
Peak memory 193292 kb
Host smart-fbd9ceb7-85fe-4b98-b41e-780346f5a869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869586669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1869586669
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4232602914
Short name T166
Test name
Test status
Simulation time 14705145861 ps
CPU time 21.1 seconds
Started Jun 07 06:17:20 PM PDT 24
Finished Jun 07 06:17:42 PM PDT 24
Peak memory 191172 kb
Host smart-cff4946f-c515-4bda-94f0-a6f945a4394d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232602914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4232602914
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.394699528
Short name T48
Test name
Test status
Simulation time 183038444053 ps
CPU time 133.78 seconds
Started Jun 07 06:17:18 PM PDT 24
Finished Jun 07 06:19:32 PM PDT 24
Peak memory 182980 kb
Host smart-3f579ff7-3341-4fc5-8923-84bac1fb683f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394699528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.394699528
Directory /workspace/99.rv_timer_random/latest
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