Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
139532838 |
1 |
|
T1 |
512218 |
|
T2 |
40427 |
|
T3 |
38806 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
67929924 |
1 |
|
T1 |
512192 |
|
T2 |
11363 |
|
T3 |
31229 |
auto[1] |
71602914 |
1 |
|
T1 |
26 |
|
T2 |
29064 |
|
T3 |
7577 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
139526884 |
1 |
|
T1 |
512213 |
|
T2 |
40417 |
|
T3 |
38800 |
auto[1] |
5954 |
1 |
|
T1 |
5 |
|
T2 |
10 |
|
T3 |
6 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
67926847 |
1 |
|
T1 |
512187 |
|
T2 |
11359 |
|
T3 |
31227 |
all_values[0] |
auto[0] |
auto[1] |
3077 |
1 |
|
T1 |
5 |
|
T2 |
4 |
|
T3 |
2 |
all_values[0] |
auto[1] |
auto[0] |
71600037 |
1 |
|
T1 |
26 |
|
T2 |
29058 |
|
T3 |
7573 |
all_values[0] |
auto[1] |
auto[1] |
2877 |
1 |
|
T2 |
6 |
|
T3 |
4 |
|
T5 |
4 |