Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T510 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1395362976 Jun 09 12:39:54 PM PDT 24 Jun 09 12:39:55 PM PDT 24 13133673 ps
T109 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.635871154 Jun 09 12:39:30 PM PDT 24 Jun 09 12:39:31 PM PDT 24 75977642 ps
T89 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1359057191 Jun 09 12:39:29 PM PDT 24 Jun 09 12:39:30 PM PDT 24 38710168 ps
T511 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2003433717 Jun 09 12:39:45 PM PDT 24 Jun 09 12:39:46 PM PDT 24 24408393 ps
T512 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4041564332 Jun 09 12:39:07 PM PDT 24 Jun 09 12:39:08 PM PDT 24 21058328 ps
T101 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.469093401 Jun 09 12:39:24 PM PDT 24 Jun 09 12:39:25 PM PDT 24 143365084 ps
T513 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1857826934 Jun 09 12:39:27 PM PDT 24 Jun 09 12:39:28 PM PDT 24 150456912 ps
T90 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3010626164 Jun 09 12:39:08 PM PDT 24 Jun 09 12:39:09 PM PDT 24 144184076 ps
T514 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1093109943 Jun 09 12:39:12 PM PDT 24 Jun 09 12:39:13 PM PDT 24 58894978 ps
T515 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2803207788 Jun 09 12:39:09 PM PDT 24 Jun 09 12:39:10 PM PDT 24 14119235 ps
T516 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3759118447 Jun 09 12:39:22 PM PDT 24 Jun 09 12:39:23 PM PDT 24 302460463 ps
T517 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1482178465 Jun 09 12:39:24 PM PDT 24 Jun 09 12:39:25 PM PDT 24 15845327 ps
T518 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1663821962 Jun 09 12:39:51 PM PDT 24 Jun 09 12:39:52 PM PDT 24 39617463 ps
T519 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3463275337 Jun 09 12:39:28 PM PDT 24 Jun 09 12:39:30 PM PDT 24 320709982 ps
T520 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3432329219 Jun 09 12:39:47 PM PDT 24 Jun 09 12:39:48 PM PDT 24 13780402 ps
T521 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.432245647 Jun 09 12:39:52 PM PDT 24 Jun 09 12:39:53 PM PDT 24 50239556 ps
T522 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3839293516 Jun 09 12:39:14 PM PDT 24 Jun 09 12:39:15 PM PDT 24 170920863 ps
T523 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.938677418 Jun 09 12:39:30 PM PDT 24 Jun 09 12:39:31 PM PDT 24 58335244 ps
T524 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.874990738 Jun 09 12:39:42 PM PDT 24 Jun 09 12:39:43 PM PDT 24 30015887 ps
T525 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.752921377 Jun 09 12:39:44 PM PDT 24 Jun 09 12:39:44 PM PDT 24 33577444 ps
T526 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2001241854 Jun 09 12:39:21 PM PDT 24 Jun 09 12:39:22 PM PDT 24 72753240 ps
T527 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2241528687 Jun 09 12:39:47 PM PDT 24 Jun 09 12:39:50 PM PDT 24 209066753 ps
T528 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3363083810 Jun 09 12:39:39 PM PDT 24 Jun 09 12:39:41 PM PDT 24 35482200 ps
T529 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2060829380 Jun 09 12:39:21 PM PDT 24 Jun 09 12:39:22 PM PDT 24 413600496 ps
T530 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.815300333 Jun 09 12:39:25 PM PDT 24 Jun 09 12:39:27 PM PDT 24 526760804 ps
T531 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3313894850 Jun 09 12:39:29 PM PDT 24 Jun 09 12:39:30 PM PDT 24 33830698 ps
T532 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3962508220 Jun 09 12:39:38 PM PDT 24 Jun 09 12:39:39 PM PDT 24 55143549 ps
T533 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2468826837 Jun 09 12:39:49 PM PDT 24 Jun 09 12:39:50 PM PDT 24 70360687 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1800027378 Jun 09 12:39:33 PM PDT 24 Jun 09 12:39:36 PM PDT 24 73715408 ps
T535 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.650877122 Jun 09 12:39:47 PM PDT 24 Jun 09 12:39:48 PM PDT 24 73954150 ps
T536 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1839629023 Jun 09 12:39:27 PM PDT 24 Jun 09 12:39:28 PM PDT 24 36896446 ps
T537 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2851123621 Jun 09 12:39:26 PM PDT 24 Jun 09 12:39:27 PM PDT 24 38888553 ps
T538 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3274599846 Jun 09 12:39:54 PM PDT 24 Jun 09 12:39:55 PM PDT 24 13381555 ps
T539 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1849096376 Jun 09 12:39:11 PM PDT 24 Jun 09 12:39:12 PM PDT 24 29234334 ps
T540 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.143735825 Jun 09 12:39:34 PM PDT 24 Jun 09 12:39:35 PM PDT 24 45623759 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1868804593 Jun 09 12:39:33 PM PDT 24 Jun 09 12:39:33 PM PDT 24 11468742 ps
T542 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.738026035 Jun 09 12:39:32 PM PDT 24 Jun 09 12:39:34 PM PDT 24 67009436 ps
T543 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.685721648 Jun 09 12:39:11 PM PDT 24 Jun 09 12:39:12 PM PDT 24 25535329 ps
T91 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2726131226 Jun 09 12:39:14 PM PDT 24 Jun 09 12:39:15 PM PDT 24 13913231 ps
T544 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2212123051 Jun 09 12:39:24 PM PDT 24 Jun 09 12:39:26 PM PDT 24 128652184 ps
T545 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1994417019 Jun 09 12:39:13 PM PDT 24 Jun 09 12:39:15 PM PDT 24 140673826 ps
T546 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1836157820 Jun 09 12:39:54 PM PDT 24 Jun 09 12:39:55 PM PDT 24 39864170 ps
T547 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3672748665 Jun 09 12:39:27 PM PDT 24 Jun 09 12:39:28 PM PDT 24 65050725 ps
T548 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3188350982 Jun 09 12:39:25 PM PDT 24 Jun 09 12:39:26 PM PDT 24 14734029 ps
T549 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1897496762 Jun 09 12:39:17 PM PDT 24 Jun 09 12:39:18 PM PDT 24 33440358 ps
T550 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3871735267 Jun 09 12:39:34 PM PDT 24 Jun 09 12:39:36 PM PDT 24 121872364 ps
T92 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.272549137 Jun 09 12:39:35 PM PDT 24 Jun 09 12:39:36 PM PDT 24 65538706 ps
T551 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2022823907 Jun 09 12:39:32 PM PDT 24 Jun 09 12:39:33 PM PDT 24 16314249 ps
T93 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2609316363 Jun 09 12:39:10 PM PDT 24 Jun 09 12:39:11 PM PDT 24 15245965 ps
T94 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1436709309 Jun 09 12:39:33 PM PDT 24 Jun 09 12:39:34 PM PDT 24 29297244 ps
T552 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1949238950 Jun 09 12:39:44 PM PDT 24 Jun 09 12:39:45 PM PDT 24 33996720 ps
T553 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.734033563 Jun 09 12:39:18 PM PDT 24 Jun 09 12:39:19 PM PDT 24 13252898 ps
T554 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.376675284 Jun 09 12:39:25 PM PDT 24 Jun 09 12:39:26 PM PDT 24 35522461 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2323350378 Jun 09 12:39:19 PM PDT 24 Jun 09 12:39:20 PM PDT 24 29373959 ps
T556 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2766409017 Jun 09 12:39:53 PM PDT 24 Jun 09 12:39:54 PM PDT 24 35824078 ps
T557 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1898374543 Jun 09 12:39:52 PM PDT 24 Jun 09 12:39:53 PM PDT 24 19245572 ps
T558 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.313257811 Jun 09 12:39:53 PM PDT 24 Jun 09 12:39:54 PM PDT 24 49879148 ps
T559 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2045176910 Jun 09 12:39:51 PM PDT 24 Jun 09 12:39:51 PM PDT 24 27244935 ps
T560 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2337957094 Jun 09 12:39:12 PM PDT 24 Jun 09 12:39:13 PM PDT 24 216107936 ps
T561 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1833786270 Jun 09 12:39:28 PM PDT 24 Jun 09 12:39:30 PM PDT 24 26422323 ps
T95 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.395305328 Jun 09 12:39:18 PM PDT 24 Jun 09 12:39:19 PM PDT 24 38560436 ps
T562 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2420086310 Jun 09 12:39:13 PM PDT 24 Jun 09 12:39:14 PM PDT 24 44567825 ps
T563 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2735544900 Jun 09 12:39:12 PM PDT 24 Jun 09 12:39:13 PM PDT 24 12588238 ps
T564 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.766598352 Jun 09 12:39:36 PM PDT 24 Jun 09 12:39:37 PM PDT 24 125316808 ps
T565 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1497982421 Jun 09 12:39:46 PM PDT 24 Jun 09 12:39:48 PM PDT 24 149137942 ps
T566 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.686565550 Jun 09 12:39:25 PM PDT 24 Jun 09 12:39:27 PM PDT 24 723987690 ps
T567 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.825883020 Jun 09 12:39:51 PM PDT 24 Jun 09 12:39:51 PM PDT 24 116593266 ps
T568 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.725409719 Jun 09 12:39:17 PM PDT 24 Jun 09 12:39:18 PM PDT 24 15214813 ps
T569 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1543640169 Jun 09 12:39:44 PM PDT 24 Jun 09 12:39:46 PM PDT 24 58057759 ps
T570 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2695158506 Jun 09 12:39:30 PM PDT 24 Jun 09 12:39:31 PM PDT 24 76113257 ps
T571 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.907710095 Jun 09 12:39:44 PM PDT 24 Jun 09 12:39:46 PM PDT 24 560500346 ps
T572 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2495530402 Jun 09 12:39:54 PM PDT 24 Jun 09 12:39:55 PM PDT 24 22569227 ps
T573 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3214774517 Jun 09 12:39:46 PM PDT 24 Jun 09 12:39:47 PM PDT 24 109365484 ps
T574 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2551312583 Jun 09 12:39:56 PM PDT 24 Jun 09 12:39:57 PM PDT 24 40983194 ps
T575 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.140777761 Jun 09 12:39:34 PM PDT 24 Jun 09 12:39:35 PM PDT 24 52664596 ps
T576 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1581170473 Jun 09 12:39:55 PM PDT 24 Jun 09 12:39:56 PM PDT 24 25605445 ps
T577 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.529470898 Jun 09 12:39:41 PM PDT 24 Jun 09 12:39:42 PM PDT 24 25182647 ps
T578 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1819378494 Jun 09 12:39:26 PM PDT 24 Jun 09 12:39:27 PM PDT 24 54412637 ps
T579 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1599703592 Jun 09 12:39:25 PM PDT 24 Jun 09 12:39:27 PM PDT 24 143665084 ps
T580 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3740295853 Jun 09 12:39:43 PM PDT 24 Jun 09 12:39:45 PM PDT 24 409394716 ps
T581 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2233816470 Jun 09 12:39:27 PM PDT 24 Jun 09 12:39:28 PM PDT 24 129919384 ps
T582 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2703335196 Jun 09 12:39:35 PM PDT 24 Jun 09 12:39:36 PM PDT 24 59692096 ps

Test location /workspace/coverage/default/48.rv_timer_stress_all.1111346072
Short name T9
Test name
Test status
Simulation time 489986011890 ps
CPU time 777.85 seconds
Started Jun 09 12:53:26 PM PDT 24
Finished Jun 09 01:06:24 PM PDT 24
Peak memory 191188 kb
Host smart-fa1304fd-c1a7-4cd9-809e-2d9eaf03ada4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111346072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1111346072
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.315492859
Short name T33
Test name
Test status
Simulation time 22069206117 ps
CPU time 171.1 seconds
Started Jun 09 12:53:22 PM PDT 24
Finished Jun 09 12:56:14 PM PDT 24
Peak memory 197628 kb
Host smart-0358eb7f-83a9-4c85-a937-83b96f9f3d6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315492859 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.315492859
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2096336303
Short name T68
Test name
Test status
Simulation time 2066647831378 ps
CPU time 971.12 seconds
Started Jun 09 12:53:17 PM PDT 24
Finished Jun 09 01:09:28 PM PDT 24
Peak memory 191204 kb
Host smart-7384fbf5-2f65-485f-9862-c14a6e38f648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096336303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2096336303
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.39581594
Short name T28
Test name
Test status
Simulation time 101089888 ps
CPU time 1.4 seconds
Started Jun 09 12:39:40 PM PDT 24
Finished Jun 09 12:39:42 PM PDT 24
Peak memory 195412 kb
Host smart-e7717848-04d3-498c-a851-f872366b6f1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_int
g_err.39581594
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3431385105
Short name T139
Test name
Test status
Simulation time 1312318394740 ps
CPU time 3421 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 01:48:37 PM PDT 24
Peak memory 191184 kb
Host smart-c835655e-3a2a-4424-bcb3-d170ec08c712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431385105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3431385105
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2049566316
Short name T59
Test name
Test status
Simulation time 474124707320 ps
CPU time 839.32 seconds
Started Jun 09 12:53:29 PM PDT 24
Finished Jun 09 01:07:29 PM PDT 24
Peak memory 194904 kb
Host smart-8383405e-aedc-4c9f-8bad-7a35433d3c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049566316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2049566316
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.583885837
Short name T60
Test name
Test status
Simulation time 915484942255 ps
CPU time 809.56 seconds
Started Jun 09 12:53:23 PM PDT 24
Finished Jun 09 01:06:52 PM PDT 24
Peak memory 191140 kb
Host smart-23451bef-df6c-4a3f-856e-c13a90793b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583885837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
583885837
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.534476011
Short name T207
Test name
Test status
Simulation time 1443358568017 ps
CPU time 4102.48 seconds
Started Jun 09 12:52:11 PM PDT 24
Finished Jun 09 02:00:35 PM PDT 24
Peak memory 194816 kb
Host smart-f2d4d73f-e97a-4495-9ba1-63bc0b7dc7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534476011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
534476011
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.349770757
Short name T63
Test name
Test status
Simulation time 2065039807804 ps
CPU time 1134.07 seconds
Started Jun 09 12:52:37 PM PDT 24
Finished Jun 09 01:11:31 PM PDT 24
Peak memory 191192 kb
Host smart-be29e734-d909-44ff-bb12-d178037d817b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349770757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
349770757
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1930162118
Short name T221
Test name
Test status
Simulation time 640735869705 ps
CPU time 1156.93 seconds
Started Jun 09 12:51:37 PM PDT 24
Finished Jun 09 01:10:54 PM PDT 24
Peak memory 195620 kb
Host smart-c68e68ad-2089-4243-96ce-f3e7123d2532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930162118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1930162118
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.485890132
Short name T12
Test name
Test status
Simulation time 216931526984 ps
CPU time 577.55 seconds
Started Jun 09 12:53:12 PM PDT 24
Finished Jun 09 01:02:50 PM PDT 24
Peak memory 206848 kb
Host smart-6850ad6f-d4bc-4ead-aaf7-0167f2f9e37e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485890132 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.485890132
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4061998633
Short name T211
Test name
Test status
Simulation time 832897782905 ps
CPU time 1694.81 seconds
Started Jun 09 12:52:02 PM PDT 24
Finished Jun 09 01:20:18 PM PDT 24
Peak memory 195612 kb
Host smart-80dfbed4-4e34-4db4-9328-44ca6a459a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061998633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4061998633
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.330224962
Short name T228
Test name
Test status
Simulation time 680565294793 ps
CPU time 1628.27 seconds
Started Jun 09 12:53:11 PM PDT 24
Finished Jun 09 01:20:20 PM PDT 24
Peak memory 191188 kb
Host smart-e873ba8b-6dae-483c-917a-1c23bab2542f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330224962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
330224962
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2651580609
Short name T112
Test name
Test status
Simulation time 1049311064133 ps
CPU time 1052.22 seconds
Started Jun 09 12:52:16 PM PDT 24
Finished Jun 09 01:09:48 PM PDT 24
Peak memory 191200 kb
Host smart-3cb17919-a3f3-4ed7-8443-1cd3e958edb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651580609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2651580609
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3515196442
Short name T16
Test name
Test status
Simulation time 102728177 ps
CPU time 0.95 seconds
Started Jun 09 12:51:22 PM PDT 24
Finished Jun 09 12:51:24 PM PDT 24
Peak memory 214408 kb
Host smart-1dd863d0-2b5c-4853-bad5-a873984120d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515196442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3515196442
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.60249858
Short name T317
Test name
Test status
Simulation time 2454622702095 ps
CPU time 2855.27 seconds
Started Jun 09 12:52:32 PM PDT 24
Finished Jun 09 01:40:08 PM PDT 24
Peak memory 195880 kb
Host smart-6689cdd0-6507-491a-bc4a-9362b40e19cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60249858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.60249858
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2766318191
Short name T7
Test name
Test status
Simulation time 928140691068 ps
CPU time 1533.85 seconds
Started Jun 09 12:51:40 PM PDT 24
Finished Jun 09 01:17:15 PM PDT 24
Peak memory 191200 kb
Host smart-ece8c48a-7d6a-414e-a777-f2375ca8c9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766318191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2766318191
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/122.rv_timer_random.1509530070
Short name T135
Test name
Test status
Simulation time 1430890583181 ps
CPU time 925.86 seconds
Started Jun 09 12:54:20 PM PDT 24
Finished Jun 09 01:09:46 PM PDT 24
Peak memory 191196 kb
Host smart-2f4dda7c-abac-4a77-9ce7-08709b07cf88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509530070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1509530070
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3161293275
Short name T155
Test name
Test status
Simulation time 329825269097 ps
CPU time 734.02 seconds
Started Jun 09 12:51:28 PM PDT 24
Finished Jun 09 01:03:42 PM PDT 24
Peak memory 191196 kb
Host smart-a1e116c5-8562-4c11-96a8-89c56cf7d883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161293275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3161293275
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2285539898
Short name T227
Test name
Test status
Simulation time 2255618109182 ps
CPU time 4487.34 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 02:07:53 PM PDT 24
Peak memory 191476 kb
Host smart-0efe6009-0331-4aac-b0f3-7a2ff836403d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285539898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2285539898
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.900434892
Short name T52
Test name
Test status
Simulation time 2809034361311 ps
CPU time 4285.78 seconds
Started Jun 09 12:52:26 PM PDT 24
Finished Jun 09 02:03:53 PM PDT 24
Peak memory 191200 kb
Host smart-99ad16fe-2686-4a28-8293-4510ab0c616b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900434892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
900434892
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random.1004366763
Short name T185
Test name
Test status
Simulation time 738723152524 ps
CPU time 285.96 seconds
Started Jun 09 12:53:22 PM PDT 24
Finished Jun 09 12:58:08 PM PDT 24
Peak memory 190812 kb
Host smart-edf6dfaa-140c-4ce2-b006-07082c904c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004366763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1004366763
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3055425018
Short name T76
Test name
Test status
Simulation time 1788814348690 ps
CPU time 1979.4 seconds
Started Jun 09 12:52:00 PM PDT 24
Finished Jun 09 01:25:00 PM PDT 24
Peak memory 194952 kb
Host smart-7b243df7-515e-4680-8193-512b3ed89d0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055425018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3055425018
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.693070187
Short name T194
Test name
Test status
Simulation time 391440244815 ps
CPU time 1148.12 seconds
Started Jun 09 12:52:16 PM PDT 24
Finished Jun 09 01:11:24 PM PDT 24
Peak memory 191100 kb
Host smart-2468fd68-6a08-43f5-b57e-40bc0e7402ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693070187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
693070187
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.1688038442
Short name T334
Test name
Test status
Simulation time 600641543105 ps
CPU time 693.36 seconds
Started Jun 09 12:52:27 PM PDT 24
Finished Jun 09 01:04:00 PM PDT 24
Peak memory 191208 kb
Host smart-b4c77d3f-6fdc-4cce-a747-641c39004bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688038442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1688038442
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1294120096
Short name T241
Test name
Test status
Simulation time 183280470539 ps
CPU time 435.14 seconds
Started Jun 09 12:53:21 PM PDT 24
Finished Jun 09 01:00:36 PM PDT 24
Peak memory 191164 kb
Host smart-6c5e68fc-442b-400b-80a7-e020bf6f3000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294120096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1294120096
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/68.rv_timer_random.3333333443
Short name T2
Test name
Test status
Simulation time 213907076782 ps
CPU time 193.36 seconds
Started Jun 09 12:53:45 PM PDT 24
Finished Jun 09 12:56:59 PM PDT 24
Peak memory 191212 kb
Host smart-d01a74bd-2a71-45f8-9031-707f6e4d32a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333333443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3333333443
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3572414153
Short name T156
Test name
Test status
Simulation time 271909931863 ps
CPU time 280.39 seconds
Started Jun 09 12:54:27 PM PDT 24
Finished Jun 09 12:59:08 PM PDT 24
Peak memory 191200 kb
Host smart-7576c499-9e8a-4d39-b56d-6b38f71c158f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572414153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3572414153
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3194750779
Short name T324
Test name
Test status
Simulation time 145612293334 ps
CPU time 408.82 seconds
Started Jun 09 12:54:13 PM PDT 24
Finished Jun 09 01:01:03 PM PDT 24
Peak memory 191184 kb
Host smart-6a018f29-a139-4715-a3cd-fb38380bd06a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194750779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3194750779
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2282803013
Short name T270
Test name
Test status
Simulation time 174224501843 ps
CPU time 306.52 seconds
Started Jun 09 12:54:15 PM PDT 24
Finished Jun 09 12:59:22 PM PDT 24
Peak memory 191172 kb
Host smart-c8139048-c536-482d-8279-da2e84504f7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282803013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2282803013
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.706310864
Short name T177
Test name
Test status
Simulation time 373633380206 ps
CPU time 961.13 seconds
Started Jun 09 12:52:05 PM PDT 24
Finished Jun 09 01:08:06 PM PDT 24
Peak memory 191208 kb
Host smart-cdcf68e5-e359-48a7-a213-a8c99aa01c27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706310864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.706310864
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3870459967
Short name T148
Test name
Test status
Simulation time 195415251361 ps
CPU time 296.7 seconds
Started Jun 09 12:52:46 PM PDT 24
Finished Jun 09 12:57:43 PM PDT 24
Peak memory 191128 kb
Host smart-a5f55d2d-a300-40b2-834c-102e7993b9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870459967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3870459967
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.3098835029
Short name T118
Test name
Test status
Simulation time 440190097608 ps
CPU time 387.12 seconds
Started Jun 09 12:54:56 PM PDT 24
Finished Jun 09 01:01:23 PM PDT 24
Peak memory 191204 kb
Host smart-96307211-46d9-41bb-9b5d-eb7d102b9be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098835029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3098835029
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1228377507
Short name T244
Test name
Test status
Simulation time 584151642900 ps
CPU time 416.77 seconds
Started Jun 09 12:52:03 PM PDT 24
Finished Jun 09 12:59:01 PM PDT 24
Peak memory 191184 kb
Host smart-24feb0a6-3f03-4c31-8dc9-f6043a8788ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228377507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1228377507
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1490059513
Short name T125
Test name
Test status
Simulation time 994083777546 ps
CPU time 596.34 seconds
Started Jun 09 12:52:51 PM PDT 24
Finished Jun 09 01:02:48 PM PDT 24
Peak memory 183008 kb
Host smart-6fd35d82-d010-4e69-a3ee-3d67d4558414
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490059513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1490059513
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2666314742
Short name T10
Test name
Test status
Simulation time 145164496600 ps
CPU time 345.21 seconds
Started Jun 09 12:52:53 PM PDT 24
Finished Jun 09 12:58:39 PM PDT 24
Peak memory 191208 kb
Host smart-399eb3f3-e0c4-4bf2-8783-c67e921ea206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666314742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2666314742
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3045951429
Short name T296
Test name
Test status
Simulation time 666509630137 ps
CPU time 1606.76 seconds
Started Jun 09 12:53:05 PM PDT 24
Finished Jun 09 01:19:52 PM PDT 24
Peak memory 194396 kb
Host smart-eb23f673-4b60-4cbc-9fd7-c5f880175929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045951429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3045951429
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/104.rv_timer_random.2051877177
Short name T203
Test name
Test status
Simulation time 200490591131 ps
CPU time 86.51 seconds
Started Jun 09 12:54:09 PM PDT 24
Finished Jun 09 12:55:36 PM PDT 24
Peak memory 191188 kb
Host smart-bb25f6ae-0a0a-46f6-8fd5-844724b5f825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051877177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2051877177
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.891119959
Short name T183
Test name
Test status
Simulation time 712911004509 ps
CPU time 676.52 seconds
Started Jun 09 12:54:44 PM PDT 24
Finished Jun 09 01:06:01 PM PDT 24
Peak memory 191208 kb
Host smart-afb1a6c0-18ea-48ae-a790-200cd1012896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891119959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.891119959
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.109183022
Short name T145
Test name
Test status
Simulation time 159633016935 ps
CPU time 284.73 seconds
Started Jun 09 12:51:54 PM PDT 24
Finished Jun 09 12:56:39 PM PDT 24
Peak memory 191188 kb
Host smart-78db39c2-65db-4bf6-8cf4-615203dcd6f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109183022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.109183022
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2963976612
Short name T231
Test name
Test status
Simulation time 900714381874 ps
CPU time 743.91 seconds
Started Jun 09 12:52:18 PM PDT 24
Finished Jun 09 01:04:42 PM PDT 24
Peak memory 191204 kb
Host smart-faddf391-e62a-4b2d-a11e-f422b1e16403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963976612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2963976612
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2645855962
Short name T260
Test name
Test status
Simulation time 1619434966014 ps
CPU time 636.15 seconds
Started Jun 09 12:52:27 PM PDT 24
Finished Jun 09 01:03:04 PM PDT 24
Peak memory 193188 kb
Host smart-5604c598-12e3-4b1b-bea3-13121e020735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645855962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2645855962
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3216524240
Short name T301
Test name
Test status
Simulation time 744673955565 ps
CPU time 1213.51 seconds
Started Jun 09 12:53:20 PM PDT 24
Finished Jun 09 01:13:34 PM PDT 24
Peak memory 182980 kb
Host smart-69243306-fd7c-442e-b49b-8af690302d61
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216524240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3216524240
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/54.rv_timer_random.2522664118
Short name T250
Test name
Test status
Simulation time 108877456283 ps
CPU time 182.7 seconds
Started Jun 09 12:53:41 PM PDT 24
Finished Jun 09 12:56:44 PM PDT 24
Peak memory 191220 kb
Host smart-d3ae1e5d-8a61-4ff8-9922-636bd7a288c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522664118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2522664118
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3580217306
Short name T293
Test name
Test status
Simulation time 543476749385 ps
CPU time 274.02 seconds
Started Jun 09 12:51:38 PM PDT 24
Finished Jun 09 12:56:13 PM PDT 24
Peak memory 182984 kb
Host smart-476b01dc-49e9-402e-a0eb-a274ef13035d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580217306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3580217306
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/176.rv_timer_random.4193500893
Short name T39
Test name
Test status
Simulation time 112774430888 ps
CPU time 541.07 seconds
Started Jun 09 12:54:54 PM PDT 24
Finished Jun 09 01:03:56 PM PDT 24
Peak memory 191204 kb
Host smart-dc2f7928-919c-4d15-a79c-a3dafd07156e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193500893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4193500893
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.2604880374
Short name T247
Test name
Test status
Simulation time 396413208390 ps
CPU time 321.3 seconds
Started Jun 09 12:52:16 PM PDT 24
Finished Jun 09 12:57:38 PM PDT 24
Peak memory 191212 kb
Host smart-337b71a5-5056-4332-8c52-9eaa9f8ca8e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604880374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2604880374
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3932368723
Short name T298
Test name
Test status
Simulation time 239341429027 ps
CPU time 292.59 seconds
Started Jun 09 12:52:43 PM PDT 24
Finished Jun 09 12:57:35 PM PDT 24
Peak memory 182920 kb
Host smart-5148a26a-f3d9-483b-8b07-8855c1a66d81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932368723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3932368723
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.1667438141
Short name T81
Test name
Test status
Simulation time 466906494560 ps
CPU time 1284.26 seconds
Started Jun 09 12:53:28 PM PDT 24
Finished Jun 09 01:14:52 PM PDT 24
Peak memory 214040 kb
Host smart-cc9b991a-7728-4dd7-a2e9-4962e1b8ec9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667438141 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.1667438141
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3490729554
Short name T171
Test name
Test status
Simulation time 1467596714997 ps
CPU time 1464.8 seconds
Started Jun 09 12:53:34 PM PDT 24
Finished Jun 09 01:17:59 PM PDT 24
Peak memory 191192 kb
Host smart-1751e0bc-56da-4351-8910-8f63506572d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490729554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3490729554
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/58.rv_timer_random.1922347746
Short name T306
Test name
Test status
Simulation time 183645259712 ps
CPU time 68.84 seconds
Started Jun 09 12:53:42 PM PDT 24
Finished Jun 09 12:54:51 PM PDT 24
Peak memory 191208 kb
Host smart-d49a369c-9ba7-489b-ba3f-40af86f47eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922347746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1922347746
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1987207295
Short name T421
Test name
Test status
Simulation time 1355903870974 ps
CPU time 1036.12 seconds
Started Jun 09 12:53:39 PM PDT 24
Finished Jun 09 01:10:56 PM PDT 24
Peak memory 191200 kb
Host smart-86d70cd3-f07d-45a6-8fd1-56f3de42ece0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987207295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1987207295
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1269025544
Short name T138
Test name
Test status
Simulation time 547924768083 ps
CPU time 434.92 seconds
Started Jun 09 12:54:09 PM PDT 24
Finished Jun 09 01:01:25 PM PDT 24
Peak memory 191216 kb
Host smart-cd058a19-07f6-42f7-ae51-4358b8b45583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269025544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1269025544
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1615568060
Short name T242
Test name
Test status
Simulation time 202373625813 ps
CPU time 214.68 seconds
Started Jun 09 12:54:03 PM PDT 24
Finished Jun 09 12:57:38 PM PDT 24
Peak memory 191212 kb
Host smart-69e3a524-a8ac-4f17-9422-a358f84c5b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615568060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1615568060
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3010626164
Short name T90
Test name
Test status
Simulation time 144184076 ps
CPU time 0.74 seconds
Started Jun 09 12:39:08 PM PDT 24
Finished Jun 09 12:39:09 PM PDT 24
Peak memory 191968 kb
Host smart-b03d6558-5ac1-4181-ac6a-c37a4058a82d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010626164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3010626164
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3519355700
Short name T49
Test name
Test status
Simulation time 78340953 ps
CPU time 0.6 seconds
Started Jun 09 12:39:38 PM PDT 24
Finished Jun 09 12:39:39 PM PDT 24
Peak memory 191444 kb
Host smart-19d66493-8b63-43d7-bf0e-335e208d8083
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519355700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3519355700
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2602498794
Short name T106
Test name
Test status
Simulation time 137817509 ps
CPU time 1.43 seconds
Started Jun 09 12:39:33 PM PDT 24
Finished Jun 09 12:39:35 PM PDT 24
Peak memory 195452 kb
Host smart-8db4e2f7-3df6-4e13-ad7c-9112543fc758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602498794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2602498794
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2222774847
Short name T277
Test name
Test status
Simulation time 175855098260 ps
CPU time 67.27 seconds
Started Jun 09 12:51:22 PM PDT 24
Finished Jun 09 12:52:30 PM PDT 24
Peak memory 182824 kb
Host smart-0a5aa807-9fd2-4acd-b883-e047603ff76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222774847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2222774847
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2259998604
Short name T204
Test name
Test status
Simulation time 743690387022 ps
CPU time 657.89 seconds
Started Jun 09 12:51:23 PM PDT 24
Finished Jun 09 01:02:21 PM PDT 24
Peak memory 195328 kb
Host smart-6e32bdac-c809-4fe9-b6bf-2ecb843a617e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259998604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2259998604
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.1941154854
Short name T73
Test name
Test status
Simulation time 733788994097 ps
CPU time 663.99 seconds
Started Jun 09 12:54:08 PM PDT 24
Finished Jun 09 01:05:13 PM PDT 24
Peak memory 193508 kb
Host smart-c7b27a7d-74aa-4264-8384-3d1bbbb2ac89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941154854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1941154854
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.1963258405
Short name T55
Test name
Test status
Simulation time 66528069170 ps
CPU time 81.47 seconds
Started Jun 09 12:54:14 PM PDT 24
Finished Jun 09 12:55:36 PM PDT 24
Peak memory 191208 kb
Host smart-870396a8-cf52-4ede-ad7f-f08efc904f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963258405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1963258405
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2232756987
Short name T170
Test name
Test status
Simulation time 662457716723 ps
CPU time 680.23 seconds
Started Jun 09 12:51:47 PM PDT 24
Finished Jun 09 01:03:08 PM PDT 24
Peak memory 182980 kb
Host smart-4faac364-8fc6-4ab3-8175-c417d5b29431
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232756987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2232756987
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_random.2366094448
Short name T346
Test name
Test status
Simulation time 120220316772 ps
CPU time 450.17 seconds
Started Jun 09 12:51:47 PM PDT 24
Finished Jun 09 12:59:18 PM PDT 24
Peak memory 191212 kb
Host smart-5faebc6c-2e6a-479e-8854-6e22b94d1901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366094448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2366094448
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3869082651
Short name T233
Test name
Test status
Simulation time 79053051344 ps
CPU time 140.33 seconds
Started Jun 09 12:51:50 PM PDT 24
Finished Jun 09 12:54:11 PM PDT 24
Peak memory 182956 kb
Host smart-6ebb89be-e908-47eb-aa3d-9565a52ce730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869082651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3869082651
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/164.rv_timer_random.1435995458
Short name T259
Test name
Test status
Simulation time 125213628565 ps
CPU time 232.95 seconds
Started Jun 09 12:54:49 PM PDT 24
Finished Jun 09 12:58:42 PM PDT 24
Peak memory 191196 kb
Host smart-6d24d803-42a7-48ca-97e2-1908825708eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435995458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1435995458
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.1881048876
Short name T114
Test name
Test status
Simulation time 232523582213 ps
CPU time 464.41 seconds
Started Jun 09 12:52:17 PM PDT 24
Finished Jun 09 01:00:02 PM PDT 24
Peak memory 191212 kb
Host smart-26cc3844-df39-4d8e-afaf-345ad4ce2035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881048876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1881048876
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random.3527028962
Short name T272
Test name
Test status
Simulation time 642258924835 ps
CPU time 3556.91 seconds
Started Jun 09 12:51:29 PM PDT 24
Finished Jun 09 01:50:46 PM PDT 24
Peak memory 191216 kb
Host smart-0ca3e912-366c-4911-848f-fd427040b051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527028962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3527028962
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2912525165
Short name T320
Test name
Test status
Simulation time 395255851359 ps
CPU time 384.38 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 12:59:30 PM PDT 24
Peak memory 182992 kb
Host smart-ef3b65d7-ae53-4afb-831a-2ee8e362bbe7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912525165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2912525165
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/55.rv_timer_random.3996577005
Short name T23
Test name
Test status
Simulation time 477204806884 ps
CPU time 1932.63 seconds
Started Jun 09 12:53:39 PM PDT 24
Finished Jun 09 01:25:52 PM PDT 24
Peak memory 191160 kb
Host smart-f394f90b-a3cf-4833-9f1c-449364543a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996577005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3996577005
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.240900854
Short name T201
Test name
Test status
Simulation time 317913920962 ps
CPU time 1491.42 seconds
Started Jun 09 12:53:50 PM PDT 24
Finished Jun 09 01:18:42 PM PDT 24
Peak memory 191188 kb
Host smart-62b1b4e5-b575-41e6-b353-2250d747ca14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240900854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.240900854
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3923014342
Short name T289
Test name
Test status
Simulation time 171277941676 ps
CPU time 762.85 seconds
Started Jun 09 12:53:51 PM PDT 24
Finished Jun 09 01:06:34 PM PDT 24
Peak memory 193436 kb
Host smart-31f30806-271a-4c05-9a71-1b09c28be1dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923014342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3923014342
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.1776146502
Short name T163
Test name
Test status
Simulation time 176740328626 ps
CPU time 211.22 seconds
Started Jun 09 12:51:19 PM PDT 24
Finished Jun 09 12:54:51 PM PDT 24
Peak memory 191216 kb
Host smart-b940262f-9246-4563-ab12-07c43efc25b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776146502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1776146502
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4046042952
Short name T442
Test name
Test status
Simulation time 112701520973 ps
CPU time 213.68 seconds
Started Jun 09 12:51:22 PM PDT 24
Finished Jun 09 12:54:56 PM PDT 24
Peak memory 195636 kb
Host smart-734394e6-29ed-4750-b6a8-8cf88965cfac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046042952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4046042952
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/119.rv_timer_random.1663378680
Short name T174
Test name
Test status
Simulation time 315580773942 ps
CPU time 893.45 seconds
Started Jun 09 12:54:21 PM PDT 24
Finished Jun 09 01:09:15 PM PDT 24
Peak memory 191208 kb
Host smart-ae1adfdb-f43d-4a6f-bae4-1456faca0922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663378680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1663378680
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.513523824
Short name T262
Test name
Test status
Simulation time 680686689481 ps
CPU time 319.28 seconds
Started Jun 09 12:51:45 PM PDT 24
Finished Jun 09 12:57:05 PM PDT 24
Peak memory 191196 kb
Host smart-3789f67c-7058-437a-846c-c75aaa77c189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513523824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.513523824
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1391785480
Short name T226
Test name
Test status
Simulation time 70397935371 ps
CPU time 1169.72 seconds
Started Jun 09 12:54:26 PM PDT 24
Finished Jun 09 01:13:56 PM PDT 24
Peak memory 194028 kb
Host smart-d95f05fd-ab87-406a-a8ec-0603e015516a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391785480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1391785480
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1078802254
Short name T342
Test name
Test status
Simulation time 73034853513 ps
CPU time 580.75 seconds
Started Jun 09 12:54:26 PM PDT 24
Finished Jun 09 01:04:07 PM PDT 24
Peak memory 191112 kb
Host smart-9f800593-797e-4ea1-b101-735b0200fcdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078802254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1078802254
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.486565905
Short name T252
Test name
Test status
Simulation time 229958594687 ps
CPU time 256.2 seconds
Started Jun 09 12:54:31 PM PDT 24
Finished Jun 09 12:58:48 PM PDT 24
Peak memory 191128 kb
Host smart-994cf336-ff0c-4683-a7e7-ce630e689547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486565905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.486565905
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3175668941
Short name T119
Test name
Test status
Simulation time 150724143755 ps
CPU time 147.1 seconds
Started Jun 09 12:54:30 PM PDT 24
Finished Jun 09 12:56:57 PM PDT 24
Peak memory 194732 kb
Host smart-b0a23128-6b38-419d-832a-7e14211566ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175668941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3175668941
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3889616449
Short name T134
Test name
Test status
Simulation time 81695284214 ps
CPU time 436.87 seconds
Started Jun 09 12:54:31 PM PDT 24
Finished Jun 09 01:01:48 PM PDT 24
Peak memory 191204 kb
Host smart-f45bdd28-3686-46f0-85fa-6d9caa6e7494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889616449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3889616449
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.4154130160
Short name T167
Test name
Test status
Simulation time 512878628596 ps
CPU time 2565.88 seconds
Started Jun 09 12:54:31 PM PDT 24
Finished Jun 09 01:37:17 PM PDT 24
Peak memory 191200 kb
Host smart-1304a017-1a68-4b52-9810-e3bdaf0a609f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154130160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4154130160
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.194313073
Short name T343
Test name
Test status
Simulation time 1090546651575 ps
CPU time 686.54 seconds
Started Jun 09 12:51:49 PM PDT 24
Finished Jun 09 01:03:16 PM PDT 24
Peak memory 182992 kb
Host smart-a347e82c-99c2-4a9b-b41e-23e293872f8f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194313073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.194313073
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/159.rv_timer_random.707585488
Short name T319
Test name
Test status
Simulation time 369688223809 ps
CPU time 654.5 seconds
Started Jun 09 12:54:42 PM PDT 24
Finished Jun 09 01:05:37 PM PDT 24
Peak memory 191444 kb
Host smart-788a3492-d604-4d63-8995-6e07f71361f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707585488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.707585488
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2619219423
Short name T217
Test name
Test status
Simulation time 7088605938 ps
CPU time 12 seconds
Started Jun 09 12:51:59 PM PDT 24
Finished Jun 09 12:52:12 PM PDT 24
Peak memory 182912 kb
Host smart-16f8c657-cb27-48e2-b600-fdfe343ceb95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619219423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2619219423
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/194.rv_timer_random.3785183420
Short name T222
Test name
Test status
Simulation time 176722700643 ps
CPU time 692.7 seconds
Started Jun 09 12:55:05 PM PDT 24
Finished Jun 09 01:06:38 PM PDT 24
Peak memory 194600 kb
Host smart-d40beaba-db64-46bd-9127-86ebe942edc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785183420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3785183420
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.897856332
Short name T54
Test name
Test status
Simulation time 43637605040 ps
CPU time 354.64 seconds
Started Jun 09 12:52:01 PM PDT 24
Finished Jun 09 12:57:56 PM PDT 24
Peak memory 191204 kb
Host smart-530e787b-53a1-48c3-902c-dc2df641e98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897856332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.897856332
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.83530393
Short name T240
Test name
Test status
Simulation time 953764817095 ps
CPU time 1403.14 seconds
Started Jun 09 12:52:16 PM PDT 24
Finished Jun 09 01:15:40 PM PDT 24
Peak memory 191212 kb
Host smart-9e90f076-9cfd-4d82-8f8d-8e754384bdc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83530393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.83530393
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.951474999
Short name T132
Test name
Test status
Simulation time 1862422655690 ps
CPU time 569.18 seconds
Started Jun 09 12:52:50 PM PDT 24
Finished Jun 09 01:02:20 PM PDT 24
Peak memory 191172 kb
Host smart-16d58d9e-5499-4888-8093-3b4b5c7d7f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951474999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
951474999
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.986888551
Short name T191
Test name
Test status
Simulation time 634094755100 ps
CPU time 326.13 seconds
Started Jun 09 12:51:29 PM PDT 24
Finished Jun 09 12:56:55 PM PDT 24
Peak memory 182980 kb
Host smart-9d521136-1122-4c56-bc68-8e32c50376ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986888551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.986888551
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1585673042
Short name T281
Test name
Test status
Simulation time 3615616910 ps
CPU time 2.88 seconds
Started Jun 09 12:53:04 PM PDT 24
Finished Jun 09 12:53:07 PM PDT 24
Peak memory 191176 kb
Host smart-0fa372d8-171b-464b-b830-e65f546b0664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585673042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1585673042
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.847584794
Short name T1
Test name
Test status
Simulation time 102528474303 ps
CPU time 461.56 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 01:00:48 PM PDT 24
Peak memory 182968 kb
Host smart-f90a2b61-806a-49bf-a9ef-8403ea82c7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847584794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.847584794
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3683195033
Short name T243
Test name
Test status
Simulation time 9358587006 ps
CPU time 20.35 seconds
Started Jun 09 12:53:27 PM PDT 24
Finished Jun 09 12:53:47 PM PDT 24
Peak memory 182984 kb
Host smart-6353287d-b7e8-4c45-a87d-cf79a9a32cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683195033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3683195033
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/88.rv_timer_random.3223456124
Short name T121
Test name
Test status
Simulation time 375624125999 ps
CPU time 398.77 seconds
Started Jun 09 12:53:59 PM PDT 24
Finished Jun 09 01:00:38 PM PDT 24
Peak memory 191416 kb
Host smart-707d3fcf-a604-480a-8a3b-0b6794b3bdc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223456124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3223456124
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4010025766
Short name T50
Test name
Test status
Simulation time 2529954600 ps
CPU time 3.68 seconds
Started Jun 09 12:39:12 PM PDT 24
Finished Jun 09 12:39:16 PM PDT 24
Peak memory 194472 kb
Host smart-d32aa5d2-3c25-440e-a10b-70e83b114e44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010025766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.4010025766
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2609316363
Short name T93
Test name
Test status
Simulation time 15245965 ps
CPU time 0.55 seconds
Started Jun 09 12:39:10 PM PDT 24
Finished Jun 09 12:39:11 PM PDT 24
Peak memory 182216 kb
Host smart-75e12306-826c-47a0-b26a-5f2cd26e8ef2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609316363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2609316363
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2735544900
Short name T563
Test name
Test status
Simulation time 12588238 ps
CPU time 0.71 seconds
Started Jun 09 12:39:12 PM PDT 24
Finished Jun 09 12:39:13 PM PDT 24
Peak memory 193832 kb
Host smart-46142a78-477e-490d-9143-e6bb1daec62f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735544900 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2735544900
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2803207788
Short name T515
Test name
Test status
Simulation time 14119235 ps
CPU time 0.6 seconds
Started Jun 09 12:39:09 PM PDT 24
Finished Jun 09 12:39:10 PM PDT 24
Peak memory 182728 kb
Host smart-f1c53c44-7c3a-42db-bae2-adfb51b91259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803207788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2803207788
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4041564332
Short name T512
Test name
Test status
Simulation time 21058328 ps
CPU time 0.55 seconds
Started Jun 09 12:39:07 PM PDT 24
Finished Jun 09 12:39:08 PM PDT 24
Peak memory 182268 kb
Host smart-f910c31e-7fbc-4fac-a6e3-96f29e72a7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041564332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.4041564332
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2420086310
Short name T562
Test name
Test status
Simulation time 44567825 ps
CPU time 0.62 seconds
Started Jun 09 12:39:13 PM PDT 24
Finished Jun 09 12:39:14 PM PDT 24
Peak memory 191500 kb
Host smart-7ebae636-7cc6-4e79-b7da-7b8ff0019e5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420086310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2420086310
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1753600507
Short name T453
Test name
Test status
Simulation time 278652642 ps
CPU time 2.96 seconds
Started Jun 09 12:39:13 PM PDT 24
Finished Jun 09 12:39:16 PM PDT 24
Peak memory 197600 kb
Host smart-6a9663ac-4364-48ca-83ca-90ec1390e5ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753600507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1753600507
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1785236143
Short name T480
Test name
Test status
Simulation time 184614187 ps
CPU time 0.87 seconds
Started Jun 09 12:39:08 PM PDT 24
Finished Jun 09 12:39:09 PM PDT 24
Peak memory 193740 kb
Host smart-4d45c8c3-0233-45a3-bcb7-02a42b3e3de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785236143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1785236143
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1907737358
Short name T505
Test name
Test status
Simulation time 12693920 ps
CPU time 0.61 seconds
Started Jun 09 12:39:11 PM PDT 24
Finished Jun 09 12:39:12 PM PDT 24
Peak memory 182744 kb
Host smart-cfd1e127-e4e6-468f-94a5-8eb80d430b82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907737358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1907737358
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1142252824
Short name T499
Test name
Test status
Simulation time 431561666 ps
CPU time 3.67 seconds
Started Jun 09 12:39:12 PM PDT 24
Finished Jun 09 12:39:16 PM PDT 24
Peak memory 191004 kb
Host smart-ad4e0bb3-9961-4d93-a7cf-be210012a83e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142252824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1142252824
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1849096376
Short name T539
Test name
Test status
Simulation time 29234334 ps
CPU time 0.58 seconds
Started Jun 09 12:39:11 PM PDT 24
Finished Jun 09 12:39:12 PM PDT 24
Peak memory 182680 kb
Host smart-2ba50895-dbd9-4462-a3f3-baabbf56711f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849096376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1849096376
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1093109943
Short name T514
Test name
Test status
Simulation time 58894978 ps
CPU time 0.69 seconds
Started Jun 09 12:39:12 PM PDT 24
Finished Jun 09 12:39:13 PM PDT 24
Peak memory 194304 kb
Host smart-362fe3f8-178f-4b7e-98f7-22788b0d07ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093109943 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1093109943
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2726131226
Short name T91
Test name
Test status
Simulation time 13913231 ps
CPU time 0.63 seconds
Started Jun 09 12:39:14 PM PDT 24
Finished Jun 09 12:39:15 PM PDT 24
Peak memory 182652 kb
Host smart-5df8fbbd-9c1a-472d-97ad-9f406bcea740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726131226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2726131226
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3042097439
Short name T473
Test name
Test status
Simulation time 43406354 ps
CPU time 0.56 seconds
Started Jun 09 12:39:13 PM PDT 24
Finished Jun 09 12:39:14 PM PDT 24
Peak memory 182660 kb
Host smart-7ebfff4f-a2c2-436d-a86e-25865a68f5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042097439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3042097439
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1897496762
Short name T549
Test name
Test status
Simulation time 33440358 ps
CPU time 0.6 seconds
Started Jun 09 12:39:17 PM PDT 24
Finished Jun 09 12:39:18 PM PDT 24
Peak memory 191436 kb
Host smart-87d54156-bcb9-4f8e-8214-161d89d7817a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897496762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1897496762
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2559982497
Short name T490
Test name
Test status
Simulation time 87283723 ps
CPU time 2.3 seconds
Started Jun 09 12:39:11 PM PDT 24
Finished Jun 09 12:39:14 PM PDT 24
Peak memory 197596 kb
Host smart-6c90f8c6-0dae-4403-8f79-f092f08c1987
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559982497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2559982497
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2246019906
Short name T501
Test name
Test status
Simulation time 86318790 ps
CPU time 1.12 seconds
Started Jun 09 12:39:13 PM PDT 24
Finished Jun 09 12:39:14 PM PDT 24
Peak memory 195232 kb
Host smart-298505ef-388c-46ee-af84-0a75415e6208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246019906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2246019906
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.738026035
Short name T542
Test name
Test status
Simulation time 67009436 ps
CPU time 0.79 seconds
Started Jun 09 12:39:32 PM PDT 24
Finished Jun 09 12:39:34 PM PDT 24
Peak memory 195028 kb
Host smart-eb97aa99-4b91-4b80-87c9-8c7b6161ca69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738026035 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.738026035
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.272549137
Short name T92
Test name
Test status
Simulation time 65538706 ps
CPU time 0.59 seconds
Started Jun 09 12:39:35 PM PDT 24
Finished Jun 09 12:39:36 PM PDT 24
Peak memory 182744 kb
Host smart-c5b950b1-a1e8-4133-affd-e838647cb026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272549137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.272549137
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1868804593
Short name T541
Test name
Test status
Simulation time 11468742 ps
CPU time 0.54 seconds
Started Jun 09 12:39:33 PM PDT 24
Finished Jun 09 12:39:33 PM PDT 24
Peak memory 182668 kb
Host smart-8206b263-f2cd-4356-8f52-4c62cff39755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868804593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1868804593
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2022823907
Short name T551
Test name
Test status
Simulation time 16314249 ps
CPU time 0.75 seconds
Started Jun 09 12:39:32 PM PDT 24
Finished Jun 09 12:39:33 PM PDT 24
Peak memory 193044 kb
Host smart-3bb6c33c-a27f-4c1f-b760-239df4807baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022823907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2022823907
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3463275337
Short name T519
Test name
Test status
Simulation time 320709982 ps
CPU time 1.83 seconds
Started Jun 09 12:39:28 PM PDT 24
Finished Jun 09 12:39:30 PM PDT 24
Peak memory 197604 kb
Host smart-2fcbd3aa-294e-4a55-9398-dd0657b78323
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463275337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3463275337
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.635871154
Short name T109
Test name
Test status
Simulation time 75977642 ps
CPU time 0.79 seconds
Started Jun 09 12:39:30 PM PDT 24
Finished Jun 09 12:39:31 PM PDT 24
Peak memory 193428 kb
Host smart-307c8d24-a6f3-47d1-8bdd-fdd84957d085
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635871154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.635871154
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3871735267
Short name T550
Test name
Test status
Simulation time 121872364 ps
CPU time 1.63 seconds
Started Jun 09 12:39:34 PM PDT 24
Finished Jun 09 12:39:36 PM PDT 24
Peak memory 197604 kb
Host smart-7bab80e2-0ceb-4542-bfa8-2c1d5f3f63d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871735267 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3871735267
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1436709309
Short name T94
Test name
Test status
Simulation time 29297244 ps
CPU time 0.57 seconds
Started Jun 09 12:39:33 PM PDT 24
Finished Jun 09 12:39:34 PM PDT 24
Peak memory 182652 kb
Host smart-f6ae4860-c80a-4e1f-b4c0-9f70070a444c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436709309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1436709309
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2552470176
Short name T467
Test name
Test status
Simulation time 42210269 ps
CPU time 0.62 seconds
Started Jun 09 12:39:34 PM PDT 24
Finished Jun 09 12:39:35 PM PDT 24
Peak memory 182564 kb
Host smart-7765026d-9247-46d7-94a1-e9da1e5e6d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552470176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2552470176
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2703335196
Short name T582
Test name
Test status
Simulation time 59692096 ps
CPU time 0.71 seconds
Started Jun 09 12:39:35 PM PDT 24
Finished Jun 09 12:39:36 PM PDT 24
Peak memory 193116 kb
Host smart-523b3e13-016e-4f06-a482-e37cdcab4592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703335196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2703335196
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1800027378
Short name T534
Test name
Test status
Simulation time 73715408 ps
CPU time 1.69 seconds
Started Jun 09 12:39:33 PM PDT 24
Finished Jun 09 12:39:36 PM PDT 24
Peak memory 197636 kb
Host smart-1b27c739-3b6d-45f2-a4ac-2bd67a39fe1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800027378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1800027378
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.874990738
Short name T524
Test name
Test status
Simulation time 30015887 ps
CPU time 1.25 seconds
Started Jun 09 12:39:42 PM PDT 24
Finished Jun 09 12:39:43 PM PDT 24
Peak memory 197608 kb
Host smart-fc034e62-ed19-4772-9898-d7fc330492dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874990738 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.874990738
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3962508220
Short name T532
Test name
Test status
Simulation time 55143549 ps
CPU time 0.57 seconds
Started Jun 09 12:39:38 PM PDT 24
Finished Jun 09 12:39:39 PM PDT 24
Peak memory 182456 kb
Host smart-1e7813a0-48d1-4c82-baa1-549d03f16485
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962508220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3962508220
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.143735825
Short name T540
Test name
Test status
Simulation time 45623759 ps
CPU time 0.55 seconds
Started Jun 09 12:39:34 PM PDT 24
Finished Jun 09 12:39:35 PM PDT 24
Peak memory 182576 kb
Host smart-616f63a7-9b81-444b-be3f-8731629bf097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143735825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.143735825
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1443007068
Short name T489
Test name
Test status
Simulation time 69823202 ps
CPU time 1.55 seconds
Started Jun 09 12:39:33 PM PDT 24
Finished Jun 09 12:39:35 PM PDT 24
Peak memory 197648 kb
Host smart-4e1443d7-9b89-4c54-8e5f-3b46428ca79e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443007068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1443007068
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.140777761
Short name T575
Test name
Test status
Simulation time 52664596 ps
CPU time 0.81 seconds
Started Jun 09 12:39:34 PM PDT 24
Finished Jun 09 12:39:35 PM PDT 24
Peak memory 182988 kb
Host smart-46bc9609-e240-44fd-a420-da49f0a895e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140777761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.140777761
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2367303715
Short name T509
Test name
Test status
Simulation time 57251487 ps
CPU time 0.83 seconds
Started Jun 09 12:39:38 PM PDT 24
Finished Jun 09 12:39:39 PM PDT 24
Peak memory 195436 kb
Host smart-4b9356a7-156c-430d-b2a2-9df9949190c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367303715 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2367303715
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.529470898
Short name T577
Test name
Test status
Simulation time 25182647 ps
CPU time 0.58 seconds
Started Jun 09 12:39:41 PM PDT 24
Finished Jun 09 12:39:42 PM PDT 24
Peak memory 182728 kb
Host smart-9b0e4194-1cec-4ac6-936a-e8243f15c109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529470898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.529470898
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1272374363
Short name T478
Test name
Test status
Simulation time 18676977 ps
CPU time 0.57 seconds
Started Jun 09 12:39:39 PM PDT 24
Finished Jun 09 12:39:40 PM PDT 24
Peak memory 182612 kb
Host smart-6141b80a-7b95-4a79-8439-c8ca836f01a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272374363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1272374363
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.671060603
Short name T98
Test name
Test status
Simulation time 16299222 ps
CPU time 0.72 seconds
Started Jun 09 12:39:37 PM PDT 24
Finished Jun 09 12:39:38 PM PDT 24
Peak memory 193236 kb
Host smart-08ac0149-fc94-4c84-816d-fa43b253ad40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671060603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.671060603
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.766598352
Short name T564
Test name
Test status
Simulation time 125316808 ps
CPU time 1.28 seconds
Started Jun 09 12:39:36 PM PDT 24
Finished Jun 09 12:39:37 PM PDT 24
Peak memory 197356 kb
Host smart-cc64e979-b796-4e1d-977b-91ac6541d959
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766598352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.766598352
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.327405681
Short name T508
Test name
Test status
Simulation time 353151809 ps
CPU time 1.11 seconds
Started Jun 09 12:39:39 PM PDT 24
Finished Jun 09 12:39:40 PM PDT 24
Peak memory 195204 kb
Host smart-2fac9d60-5831-4566-b1c2-8987a8459b7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327405681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.327405681
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1543640169
Short name T569
Test name
Test status
Simulation time 58057759 ps
CPU time 1.28 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 197616 kb
Host smart-15850971-09a5-425f-b321-2ac524b6ed30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543640169 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1543640169
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1420877801
Short name T103
Test name
Test status
Simulation time 26664745 ps
CPU time 0.58 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 182724 kb
Host smart-0884484c-806d-4a96-ba87-0339c96c70ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420877801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1420877801
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3419685106
Short name T483
Test name
Test status
Simulation time 30919363 ps
CPU time 0.52 seconds
Started Jun 09 12:39:35 PM PDT 24
Finished Jun 09 12:39:36 PM PDT 24
Peak memory 182100 kb
Host smart-e3e53a82-13a0-463c-b957-49d618b82923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419685106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3419685106
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3811854513
Short name T85
Test name
Test status
Simulation time 26483835 ps
CPU time 0.6 seconds
Started Jun 09 12:39:43 PM PDT 24
Finished Jun 09 12:39:44 PM PDT 24
Peak memory 191408 kb
Host smart-bcf5c1e0-7293-461d-87e6-7d061b853f2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811854513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3811854513
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3363083810
Short name T528
Test name
Test status
Simulation time 35482200 ps
CPU time 1.85 seconds
Started Jun 09 12:39:39 PM PDT 24
Finished Jun 09 12:39:41 PM PDT 24
Peak memory 197572 kb
Host smart-d2171379-b108-4378-a648-c67db29e8c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363083810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3363083810
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2468826837
Short name T533
Test name
Test status
Simulation time 70360687 ps
CPU time 0.69 seconds
Started Jun 09 12:39:49 PM PDT 24
Finished Jun 09 12:39:50 PM PDT 24
Peak memory 194772 kb
Host smart-d71f91ff-981c-42cc-8d24-8ca8d86e32e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468826837 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2468826837
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1989987488
Short name T102
Test name
Test status
Simulation time 16311210 ps
CPU time 0.63 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 182744 kb
Host smart-3bc3d534-9720-43ee-9085-b776cb410926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989987488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1989987488
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2003433717
Short name T511
Test name
Test status
Simulation time 24408393 ps
CPU time 0.58 seconds
Started Jun 09 12:39:45 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 182648 kb
Host smart-802d9755-e735-4d13-a6a2-9f3aae87417e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003433717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2003433717
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1949238950
Short name T552
Test name
Test status
Simulation time 33996720 ps
CPU time 0.77 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 193324 kb
Host smart-9bf3bdc7-c456-499d-961c-1f9fcd05b58e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949238950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1949238950
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1144076604
Short name T460
Test name
Test status
Simulation time 45895199 ps
CPU time 2.19 seconds
Started Jun 09 12:39:43 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 197600 kb
Host smart-0c3007a9-9c07-48f3-b505-66b63782e56a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144076604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1144076604
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3897113822
Short name T30
Test name
Test status
Simulation time 51138743 ps
CPU time 0.82 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 193656 kb
Host smart-cf706cc0-7818-4d72-a2f8-7039f4fc95bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897113822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3897113822
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1263382585
Short name T496
Test name
Test status
Simulation time 100804844 ps
CPU time 1.22 seconds
Started Jun 09 12:39:47 PM PDT 24
Finished Jun 09 12:39:48 PM PDT 24
Peak memory 197612 kb
Host smart-bf16190f-c2d1-4f1a-be3d-66e88e7a7d8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263382585 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1263382585
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.752921377
Short name T525
Test name
Test status
Simulation time 33577444 ps
CPU time 0.56 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:44 PM PDT 24
Peak memory 182732 kb
Host smart-6cc70e5f-3467-4473-b39b-fef9820f0ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752921377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.752921377
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3616637966
Short name T455
Test name
Test status
Simulation time 19474779 ps
CPU time 0.56 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 182628 kb
Host smart-bedf28cf-c508-4318-985f-90caed3d5938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616637966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3616637966
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1166865772
Short name T96
Test name
Test status
Simulation time 21992060 ps
CPU time 0.71 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 192044 kb
Host smart-28f21fa3-040f-4131-bef8-52f841304e00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166865772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1166865772
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.863616406
Short name T470
Test name
Test status
Simulation time 115470218 ps
CPU time 1.37 seconds
Started Jun 09 12:39:43 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 197656 kb
Host smart-82253842-e011-4af8-b125-e7a18d81fea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863616406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.863616406
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3740295853
Short name T580
Test name
Test status
Simulation time 409394716 ps
CPU time 1.12 seconds
Started Jun 09 12:39:43 PM PDT 24
Finished Jun 09 12:39:45 PM PDT 24
Peak memory 183424 kb
Host smart-cc44ad72-8836-4930-abd7-d91bca07a5cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740295853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3740295853
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3727147305
Short name T465
Test name
Test status
Simulation time 33616924 ps
CPU time 0.84 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:56 PM PDT 24
Peak memory 196056 kb
Host smart-c83f740c-13c2-4641-81ff-dd41ef0aeb1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727147305 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3727147305
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.739051272
Short name T82
Test name
Test status
Simulation time 21244591 ps
CPU time 0.6 seconds
Started Jun 09 12:39:49 PM PDT 24
Finished Jun 09 12:39:50 PM PDT 24
Peak memory 182704 kb
Host smart-ce42f1df-1571-4ad9-9451-2b11c9004465
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739051272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.739051272
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.909345614
Short name T459
Test name
Test status
Simulation time 65814556 ps
CPU time 0.58 seconds
Started Jun 09 12:39:48 PM PDT 24
Finished Jun 09 12:39:49 PM PDT 24
Peak memory 182580 kb
Host smart-227738f5-4424-4751-a272-c20914d60063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909345614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.909345614
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.689987485
Short name T97
Test name
Test status
Simulation time 22661866 ps
CPU time 0.82 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 193440 kb
Host smart-0272bcaa-f508-4e61-a3c9-c1cc74b76a39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689987485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.689987485
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2241528687
Short name T527
Test name
Test status
Simulation time 209066753 ps
CPU time 2.78 seconds
Started Jun 09 12:39:47 PM PDT 24
Finished Jun 09 12:39:50 PM PDT 24
Peak memory 197632 kb
Host smart-c55c0300-9f49-4b22-8568-90b48a684a61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241528687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2241528687
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.907710095
Short name T571
Test name
Test status
Simulation time 560500346 ps
CPU time 1.36 seconds
Started Jun 09 12:39:44 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 194736 kb
Host smart-43b4063b-1d78-408c-b3a0-fc00e0165d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907710095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.907710095
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1836157820
Short name T546
Test name
Test status
Simulation time 39864170 ps
CPU time 0.97 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 196832 kb
Host smart-28805b1c-d158-4b2b-b696-27c185edb2eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836157820 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1836157820
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1958410242
Short name T471
Test name
Test status
Simulation time 32247275 ps
CPU time 0.63 seconds
Started Jun 09 12:39:47 PM PDT 24
Finished Jun 09 12:39:48 PM PDT 24
Peak memory 182732 kb
Host smart-5f1cfc5d-52b0-4187-8b80-c388893d74b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958410242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1958410242
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2438977378
Short name T504
Test name
Test status
Simulation time 15940031 ps
CPU time 0.54 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182520 kb
Host smart-96829df3-b54b-4497-91a0-1926c1bbafec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438977378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2438977378
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3002720647
Short name T31
Test name
Test status
Simulation time 22391041 ps
CPU time 0.8 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 193440 kb
Host smart-fb7e7d57-b2f1-454d-917c-59f2b079e8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002720647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3002720647
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1859759783
Short name T458
Test name
Test status
Simulation time 29427509 ps
CPU time 1.42 seconds
Started Jun 09 12:39:46 PM PDT 24
Finished Jun 09 12:39:47 PM PDT 24
Peak memory 197624 kb
Host smart-9072b79a-0ef7-4aff-9b4f-953556e625d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859759783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1859759783
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2485171104
Short name T105
Test name
Test status
Simulation time 129056593 ps
CPU time 1.41 seconds
Started Jun 09 12:39:47 PM PDT 24
Finished Jun 09 12:39:49 PM PDT 24
Peak memory 183476 kb
Host smart-391c4c92-1df2-4032-95ea-371bf1935036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485171104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2485171104
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3214774517
Short name T573
Test name
Test status
Simulation time 109365484 ps
CPU time 0.85 seconds
Started Jun 09 12:39:46 PM PDT 24
Finished Jun 09 12:39:47 PM PDT 24
Peak memory 195664 kb
Host smart-ea578479-b588-4d56-9ecd-79ca9894fa47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214774517 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3214774517
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.460646816
Short name T104
Test name
Test status
Simulation time 11966424 ps
CPU time 0.54 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182400 kb
Host smart-bb051eaf-51ef-4786-9dcc-0ffbb2202e8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460646816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.460646816
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.313257811
Short name T558
Test name
Test status
Simulation time 49879148 ps
CPU time 0.54 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182596 kb
Host smart-4b6a626b-2f9a-4cd5-b185-c1a9ea02b23e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313257811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.313257811
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4244935204
Short name T99
Test name
Test status
Simulation time 207521567 ps
CPU time 0.61 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 191160 kb
Host smart-7962e002-df9b-4ca8-8280-ab11dbe0aa67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244935204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4244935204
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.628376181
Short name T463
Test name
Test status
Simulation time 105599433 ps
CPU time 2.1 seconds
Started Jun 09 12:39:48 PM PDT 24
Finished Jun 09 12:39:50 PM PDT 24
Peak memory 197580 kb
Host smart-d3ea0340-caf8-4920-9b3b-55e4e3ae3d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628376181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.628376181
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1497982421
Short name T565
Test name
Test status
Simulation time 149137942 ps
CPU time 1.34 seconds
Started Jun 09 12:39:46 PM PDT 24
Finished Jun 09 12:39:48 PM PDT 24
Peak memory 183200 kb
Host smart-f50b4c7e-5cdc-414f-a3ba-b2bc128b42cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497982421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1497982421
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1240352543
Short name T87
Test name
Test status
Simulation time 39931278 ps
CPU time 0.85 seconds
Started Jun 09 12:39:15 PM PDT 24
Finished Jun 09 12:39:16 PM PDT 24
Peak memory 192616 kb
Host smart-c8a3f09a-1011-44ca-8ef4-3078f96d9260
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240352543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1240352543
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1994417019
Short name T545
Test name
Test status
Simulation time 140673826 ps
CPU time 1.4 seconds
Started Jun 09 12:39:13 PM PDT 24
Finished Jun 09 12:39:15 PM PDT 24
Peak memory 192868 kb
Host smart-07811a36-47fc-4162-ac24-4767c941d6b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994417019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1994417019
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4104693757
Short name T86
Test name
Test status
Simulation time 35366871 ps
CPU time 0.52 seconds
Started Jun 09 12:39:17 PM PDT 24
Finished Jun 09 12:39:18 PM PDT 24
Peak memory 182240 kb
Host smart-cca93db9-040a-480d-b133-06631a846452
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104693757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.4104693757
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3839293516
Short name T522
Test name
Test status
Simulation time 170920863 ps
CPU time 0.71 seconds
Started Jun 09 12:39:14 PM PDT 24
Finished Jun 09 12:39:15 PM PDT 24
Peak memory 194700 kb
Host smart-1e324827-9d6c-4707-9673-222f5d7ea468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839293516 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3839293516
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.685721648
Short name T543
Test name
Test status
Simulation time 25535329 ps
CPU time 0.62 seconds
Started Jun 09 12:39:11 PM PDT 24
Finished Jun 09 12:39:12 PM PDT 24
Peak memory 182732 kb
Host smart-87f28023-75c0-4490-95f6-0442b0b19672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685721648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.685721648
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1702692486
Short name T468
Test name
Test status
Simulation time 12732355 ps
CPU time 0.56 seconds
Started Jun 09 12:39:17 PM PDT 24
Finished Jun 09 12:39:18 PM PDT 24
Peak memory 182688 kb
Host smart-75f14963-7578-4388-a71c-0db4c8100a1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702692486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1702692486
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.658539214
Short name T84
Test name
Test status
Simulation time 30667081 ps
CPU time 0.75 seconds
Started Jun 09 12:39:14 PM PDT 24
Finished Jun 09 12:39:15 PM PDT 24
Peak memory 193272 kb
Host smart-3ef14cb0-2bd8-4c85-8a9f-88063684245e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658539214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.658539214
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2307492874
Short name T495
Test name
Test status
Simulation time 25297853 ps
CPU time 1.33 seconds
Started Jun 09 12:39:14 PM PDT 24
Finished Jun 09 12:39:16 PM PDT 24
Peak memory 197580 kb
Host smart-565acc3b-3c20-4080-a9e2-b744dd19b8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307492874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2307492874
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2337957094
Short name T560
Test name
Test status
Simulation time 216107936 ps
CPU time 1.29 seconds
Started Jun 09 12:39:12 PM PDT 24
Finished Jun 09 12:39:13 PM PDT 24
Peak memory 195248 kb
Host smart-8bc14467-7a14-4445-91f9-d9a5dae7c803
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337957094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2337957094
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1576430819
Short name T493
Test name
Test status
Simulation time 41089120 ps
CPU time 0.54 seconds
Started Jun 09 12:39:48 PM PDT 24
Finished Jun 09 12:39:49 PM PDT 24
Peak memory 182104 kb
Host smart-fd7de7a6-f0da-4a4a-917e-a1f12aebac39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576430819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1576430819
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1663821962
Short name T518
Test name
Test status
Simulation time 39617463 ps
CPU time 0.54 seconds
Started Jun 09 12:39:51 PM PDT 24
Finished Jun 09 12:39:52 PM PDT 24
Peak memory 182604 kb
Host smart-28aee84c-cc81-4e1a-8ce8-d5d9b2f994b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663821962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1663821962
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1443634717
Short name T506
Test name
Test status
Simulation time 15495776 ps
CPU time 0.52 seconds
Started Jun 09 12:39:51 PM PDT 24
Finished Jun 09 12:39:52 PM PDT 24
Peak memory 182564 kb
Host smart-dcf361e0-aad8-4eac-8850-c83247164636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443634717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1443634717
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.789556740
Short name T461
Test name
Test status
Simulation time 21173495 ps
CPU time 0.54 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 182040 kb
Host smart-91e2ac67-2535-45c2-a50c-15444e91f76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789556740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.789556740
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3274599846
Short name T538
Test name
Test status
Simulation time 13381555 ps
CPU time 0.54 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 182036 kb
Host smart-ed5ad473-ee81-4ae4-9e77-516f520e7888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274599846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3274599846
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2941929208
Short name T491
Test name
Test status
Simulation time 18540253 ps
CPU time 0.58 seconds
Started Jun 09 12:39:46 PM PDT 24
Finished Jun 09 12:39:46 PM PDT 24
Peak memory 182792 kb
Host smart-37197bc8-6cf1-4dca-b91a-5a95e5a23a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941929208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2941929208
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1012561897
Short name T462
Test name
Test status
Simulation time 83555155 ps
CPU time 0.54 seconds
Started Jun 09 12:39:48 PM PDT 24
Finished Jun 09 12:39:49 PM PDT 24
Peak memory 182092 kb
Host smart-2681486e-e2eb-4aa1-8242-a5158560eaef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012561897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1012561897
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3432329219
Short name T520
Test name
Test status
Simulation time 13780402 ps
CPU time 0.53 seconds
Started Jun 09 12:39:47 PM PDT 24
Finished Jun 09 12:39:48 PM PDT 24
Peak memory 182612 kb
Host smart-0e70647f-8eec-4c23-8ef4-f0e60806df6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432329219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3432329219
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.650877122
Short name T535
Test name
Test status
Simulation time 73954150 ps
CPU time 0.56 seconds
Started Jun 09 12:39:47 PM PDT 24
Finished Jun 09 12:39:48 PM PDT 24
Peak memory 182704 kb
Host smart-04c5820f-58bc-4d9f-a8ba-61ef13ef1e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650877122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.650877122
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.933556314
Short name T456
Test name
Test status
Simulation time 30751910 ps
CPU time 0.57 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 182708 kb
Host smart-a1374b52-b072-42b9-a3d6-ed16d0c028cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933556314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.933556314
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2323350378
Short name T555
Test name
Test status
Simulation time 29373959 ps
CPU time 0.6 seconds
Started Jun 09 12:39:19 PM PDT 24
Finished Jun 09 12:39:20 PM PDT 24
Peak memory 191964 kb
Host smart-f6ab27b2-fc5a-4644-9f1a-7d691e2b6aef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323350378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2323350378
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.52719879
Short name T487
Test name
Test status
Simulation time 103033300 ps
CPU time 1.43 seconds
Started Jun 09 12:39:22 PM PDT 24
Finished Jun 09 12:39:24 PM PDT 24
Peak memory 191148 kb
Host smart-9fd8b045-9015-4548-8638-9a8276e5e298
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52719879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ba
sh.52719879
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3175414885
Short name T472
Test name
Test status
Simulation time 15158220 ps
CPU time 0.56 seconds
Started Jun 09 12:39:20 PM PDT 24
Finished Jun 09 12:39:20 PM PDT 24
Peak memory 182764 kb
Host smart-80a30738-a016-430f-b54f-18134c1d88c8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175414885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3175414885
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.725409719
Short name T568
Test name
Test status
Simulation time 15214813 ps
CPU time 0.63 seconds
Started Jun 09 12:39:17 PM PDT 24
Finished Jun 09 12:39:18 PM PDT 24
Peak memory 193328 kb
Host smart-8ec08992-c211-41bf-bde3-4c9d2a9c04e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725409719 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.725409719
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1582424051
Short name T88
Test name
Test status
Simulation time 18546338 ps
CPU time 0.61 seconds
Started Jun 09 12:39:21 PM PDT 24
Finished Jun 09 12:39:22 PM PDT 24
Peak memory 182728 kb
Host smart-c98ee86c-8d3b-497e-8e62-c949461a3541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582424051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1582424051
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2001241854
Short name T526
Test name
Test status
Simulation time 72753240 ps
CPU time 0.53 seconds
Started Jun 09 12:39:21 PM PDT 24
Finished Jun 09 12:39:22 PM PDT 24
Peak memory 182016 kb
Host smart-561f7bbc-bf38-4bb9-ba4c-5bf168405b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001241854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2001241854
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2405369291
Short name T100
Test name
Test status
Simulation time 32146729 ps
CPU time 0.81 seconds
Started Jun 09 12:39:18 PM PDT 24
Finished Jun 09 12:39:19 PM PDT 24
Peak memory 193460 kb
Host smart-a27da3a6-8663-4f6e-aeca-e3d19bc6c1ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405369291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2405369291
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2404750905
Short name T488
Test name
Test status
Simulation time 213520919 ps
CPU time 2.38 seconds
Started Jun 09 12:39:11 PM PDT 24
Finished Jun 09 12:39:13 PM PDT 24
Peak memory 197644 kb
Host smart-08d8778f-7889-4312-b9a5-51288c7871ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404750905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2404750905
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.96652723
Short name T107
Test name
Test status
Simulation time 77497924 ps
CPU time 1.1 seconds
Started Jun 09 12:39:20 PM PDT 24
Finished Jun 09 12:39:21 PM PDT 24
Peak memory 195196 kb
Host smart-b9c5bf28-ce9e-416b-bc14-0c70495980e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96652723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg
_err.96652723
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.875021783
Short name T452
Test name
Test status
Simulation time 31801281 ps
CPU time 0.55 seconds
Started Jun 09 12:39:51 PM PDT 24
Finished Jun 09 12:39:52 PM PDT 24
Peak memory 182636 kb
Host smart-f40580f0-bc61-491e-9af3-df0e86239c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875021783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.875021783
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2491303982
Short name T497
Test name
Test status
Simulation time 11662643 ps
CPU time 0.56 seconds
Started Jun 09 12:39:51 PM PDT 24
Finished Jun 09 12:39:52 PM PDT 24
Peak memory 182640 kb
Host smart-e60a9791-d6f4-4151-a405-8477a98f4e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491303982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2491303982
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1581170473
Short name T576
Test name
Test status
Simulation time 25605445 ps
CPU time 0.56 seconds
Started Jun 09 12:39:55 PM PDT 24
Finished Jun 09 12:39:56 PM PDT 24
Peak memory 182668 kb
Host smart-25b0236e-19fe-4710-80e5-cd77e0ae15db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581170473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1581170473
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.684617920
Short name T494
Test name
Test status
Simulation time 43030611 ps
CPU time 0.54 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182608 kb
Host smart-b733364d-2840-45a9-a6c0-0b20174fd89b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684617920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.684617920
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.432245647
Short name T521
Test name
Test status
Simulation time 50239556 ps
CPU time 0.56 seconds
Started Jun 09 12:39:52 PM PDT 24
Finished Jun 09 12:39:53 PM PDT 24
Peak memory 182728 kb
Host smart-7cd4347c-953f-41e1-bcb9-896b7c1c8187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432245647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.432245647
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3801146864
Short name T454
Test name
Test status
Simulation time 24697221 ps
CPU time 0.55 seconds
Started Jun 09 12:39:51 PM PDT 24
Finished Jun 09 12:39:52 PM PDT 24
Peak memory 182612 kb
Host smart-fb2bcc53-b3b5-42d2-8c39-f5f37b0f3793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801146864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3801146864
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1191761657
Short name T457
Test name
Test status
Simulation time 35257326 ps
CPU time 0.54 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182072 kb
Host smart-0c205d8c-d711-4838-8d14-14079b9cbe1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191761657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1191761657
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2045176910
Short name T559
Test name
Test status
Simulation time 27244935 ps
CPU time 0.52 seconds
Started Jun 09 12:39:51 PM PDT 24
Finished Jun 09 12:39:51 PM PDT 24
Peak memory 182500 kb
Host smart-67c15fdb-dbb5-4e26-9426-6c248e005b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045176910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2045176910
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2551312583
Short name T574
Test name
Test status
Simulation time 40983194 ps
CPU time 0.53 seconds
Started Jun 09 12:39:56 PM PDT 24
Finished Jun 09 12:39:57 PM PDT 24
Peak memory 182612 kb
Host smart-97fb3f4a-430d-4268-b9d5-be25f6a52877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551312583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2551312583
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1395362976
Short name T510
Test name
Test status
Simulation time 13133673 ps
CPU time 0.54 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 182080 kb
Host smart-a678da0d-33cc-4849-8bb3-c0836d61b4f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395362976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1395362976
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1819378494
Short name T578
Test name
Test status
Simulation time 54412637 ps
CPU time 0.73 seconds
Started Jun 09 12:39:26 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 192552 kb
Host smart-6b2d17de-9ab8-40b7-b0f2-1902e2216983
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819378494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1819378494
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1599703592
Short name T579
Test name
Test status
Simulation time 143665084 ps
CPU time 1.61 seconds
Started Jun 09 12:39:25 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 191148 kb
Host smart-c8d1b0ce-e35a-4bb5-9639-015e51fb8a00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599703592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1599703592
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.395305328
Short name T95
Test name
Test status
Simulation time 38560436 ps
CPU time 0.56 seconds
Started Jun 09 12:39:18 PM PDT 24
Finished Jun 09 12:39:19 PM PDT 24
Peak memory 182388 kb
Host smart-8f8334e8-7e8a-4165-a7ff-ebf89c6b7b26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395305328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.395305328
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1857826934
Short name T513
Test name
Test status
Simulation time 150456912 ps
CPU time 1 seconds
Started Jun 09 12:39:27 PM PDT 24
Finished Jun 09 12:39:28 PM PDT 24
Peak memory 197348 kb
Host smart-f9a170d4-ca45-42f7-b75c-1764115c326d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857826934 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1857826934
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2998093452
Short name T479
Test name
Test status
Simulation time 51139548 ps
CPU time 0.59 seconds
Started Jun 09 12:39:18 PM PDT 24
Finished Jun 09 12:39:19 PM PDT 24
Peak memory 191968 kb
Host smart-9b5a4bae-5313-46cd-8bfd-3971c0cc9785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998093452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2998093452
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.734033563
Short name T553
Test name
Test status
Simulation time 13252898 ps
CPU time 0.53 seconds
Started Jun 09 12:39:18 PM PDT 24
Finished Jun 09 12:39:19 PM PDT 24
Peak memory 182596 kb
Host smart-4e3022dc-741c-4b1b-ba38-59ead8d620c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734033563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.734033563
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.376675284
Short name T554
Test name
Test status
Simulation time 35522461 ps
CPU time 0.79 seconds
Started Jun 09 12:39:25 PM PDT 24
Finished Jun 09 12:39:26 PM PDT 24
Peak memory 193448 kb
Host smart-9d00fdd1-c244-46a9-80c7-62106b1260fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376675284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.376675284
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3811900964
Short name T474
Test name
Test status
Simulation time 86077384 ps
CPU time 1.56 seconds
Started Jun 09 12:39:18 PM PDT 24
Finished Jun 09 12:39:20 PM PDT 24
Peak memory 197576 kb
Host smart-e585ac4b-390b-48e6-851f-c48201d12cd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811900964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3811900964
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2060829380
Short name T529
Test name
Test status
Simulation time 413600496 ps
CPU time 0.85 seconds
Started Jun 09 12:39:21 PM PDT 24
Finished Jun 09 12:39:22 PM PDT 24
Peak memory 193424 kb
Host smart-213845e7-8dfe-4032-b4a6-dda37dc214b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060829380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2060829380
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2766409017
Short name T556
Test name
Test status
Simulation time 35824078 ps
CPU time 0.54 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182568 kb
Host smart-01434a42-fdef-4664-a2c1-beb316eccbb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766409017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2766409017
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1254054265
Short name T466
Test name
Test status
Simulation time 61694902 ps
CPU time 0.52 seconds
Started Jun 09 12:39:51 PM PDT 24
Finished Jun 09 12:39:52 PM PDT 24
Peak memory 182000 kb
Host smart-8d91f734-50a0-4ed0-a7dc-1250a51f9a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254054265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1254054265
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3046603268
Short name T507
Test name
Test status
Simulation time 37958556 ps
CPU time 0.55 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182276 kb
Host smart-62818944-b8a2-4409-bb42-a16cabab9bfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046603268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3046603268
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2495530402
Short name T572
Test name
Test status
Simulation time 22569227 ps
CPU time 0.53 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 182256 kb
Host smart-000eae85-3eb7-4cae-8ed7-12f9148a6062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495530402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2495530402
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1164507686
Short name T477
Test name
Test status
Simulation time 13647045 ps
CPU time 0.54 seconds
Started Jun 09 12:39:56 PM PDT 24
Finished Jun 09 12:39:56 PM PDT 24
Peak memory 182664 kb
Host smart-ae43e018-5d46-455e-bfd4-e60a979ebb63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164507686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1164507686
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.825883020
Short name T567
Test name
Test status
Simulation time 116593266 ps
CPU time 0.54 seconds
Started Jun 09 12:39:51 PM PDT 24
Finished Jun 09 12:39:51 PM PDT 24
Peak memory 182532 kb
Host smart-a31f24a9-c884-4a32-abb0-90abc92d7375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825883020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.825883020
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.883571370
Short name T503
Test name
Test status
Simulation time 42775836 ps
CPU time 0.55 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182672 kb
Host smart-9e213635-6d6c-4643-8236-9a10071b3d25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883571370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.883571370
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2200975712
Short name T484
Test name
Test status
Simulation time 12004203 ps
CPU time 0.57 seconds
Started Jun 09 12:39:53 PM PDT 24
Finished Jun 09 12:39:54 PM PDT 24
Peak memory 182600 kb
Host smart-f5742f8d-d73b-42f8-8633-7b9390059b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200975712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2200975712
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2766642152
Short name T475
Test name
Test status
Simulation time 149658079 ps
CPU time 0.55 seconds
Started Jun 09 12:39:54 PM PDT 24
Finished Jun 09 12:39:55 PM PDT 24
Peak memory 182680 kb
Host smart-e4e40c3e-b058-4970-b67a-9368a3e4a949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766642152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2766642152
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1898374543
Short name T557
Test name
Test status
Simulation time 19245572 ps
CPU time 0.56 seconds
Started Jun 09 12:39:52 PM PDT 24
Finished Jun 09 12:39:53 PM PDT 24
Peak memory 182240 kb
Host smart-a0995052-60ae-4114-9e68-23ef3984c2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898374543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1898374543
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2233816470
Short name T581
Test name
Test status
Simulation time 129919384 ps
CPU time 0.92 seconds
Started Jun 09 12:39:27 PM PDT 24
Finished Jun 09 12:39:28 PM PDT 24
Peak memory 196880 kb
Host smart-ca52de23-2a9c-452a-8479-54c6efeb72e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233816470 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2233816470
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.545631717
Short name T83
Test name
Test status
Simulation time 18104799 ps
CPU time 0.55 seconds
Started Jun 09 12:39:24 PM PDT 24
Finished Jun 09 12:39:25 PM PDT 24
Peak memory 182708 kb
Host smart-5e805032-40dc-47f8-9939-3a5287afbbb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545631717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.545631717
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1748102716
Short name T469
Test name
Test status
Simulation time 12714235 ps
CPU time 0.54 seconds
Started Jun 09 12:39:30 PM PDT 24
Finished Jun 09 12:39:31 PM PDT 24
Peak memory 182036 kb
Host smart-19a08be1-395c-4a99-ab99-914de7cd3d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748102716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1748102716
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1482178465
Short name T517
Test name
Test status
Simulation time 15845327 ps
CPU time 0.71 seconds
Started Jun 09 12:39:24 PM PDT 24
Finished Jun 09 12:39:25 PM PDT 24
Peak memory 192292 kb
Host smart-2291d929-4c95-4769-83b9-3d0f5f0f8246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482178465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1482178465
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2212123051
Short name T544
Test name
Test status
Simulation time 128652184 ps
CPU time 0.87 seconds
Started Jun 09 12:39:24 PM PDT 24
Finished Jun 09 12:39:26 PM PDT 24
Peak memory 196500 kb
Host smart-ac8a45c3-e6a3-48a9-8ed7-b95c931f63de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212123051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2212123051
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3759118447
Short name T516
Test name
Test status
Simulation time 302460463 ps
CPU time 1.12 seconds
Started Jun 09 12:39:22 PM PDT 24
Finished Jun 09 12:39:23 PM PDT 24
Peak memory 195052 kb
Host smart-ac861c18-f413-4ed4-9b4e-4fa9bc58a538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759118447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3759118447
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3905640784
Short name T481
Test name
Test status
Simulation time 19139081 ps
CPU time 0.77 seconds
Started Jun 09 12:39:23 PM PDT 24
Finished Jun 09 12:39:24 PM PDT 24
Peak memory 195816 kb
Host smart-bba77dac-b324-448c-913a-fe6e24537b44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905640784 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3905640784
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2510933225
Short name T476
Test name
Test status
Simulation time 15406132 ps
CPU time 0.62 seconds
Started Jun 09 12:39:26 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 182728 kb
Host smart-1bf0d488-abae-41d0-b1e2-820bb14ba1e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510933225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2510933225
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.938677418
Short name T523
Test name
Test status
Simulation time 58335244 ps
CPU time 0.55 seconds
Started Jun 09 12:39:30 PM PDT 24
Finished Jun 09 12:39:31 PM PDT 24
Peak memory 182512 kb
Host smart-8616ea35-92b2-4bf8-a159-0dfdde0c2fdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938677418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.938677418
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.469093401
Short name T101
Test name
Test status
Simulation time 143365084 ps
CPU time 0.67 seconds
Started Jun 09 12:39:24 PM PDT 24
Finished Jun 09 12:39:25 PM PDT 24
Peak memory 192044 kb
Host smart-61880206-9071-4273-8185-814ac96846c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469093401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.469093401
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.815300333
Short name T530
Test name
Test status
Simulation time 526760804 ps
CPU time 2.25 seconds
Started Jun 09 12:39:25 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 197620 kb
Host smart-1cdacb5a-c547-4990-9911-dd4691285189
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815300333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.815300333
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1972435202
Short name T492
Test name
Test status
Simulation time 347122834 ps
CPU time 1.38 seconds
Started Jun 09 12:39:26 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 195356 kb
Host smart-6b18697a-0112-4a43-b859-876e87242ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972435202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1972435202
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2804751517
Short name T486
Test name
Test status
Simulation time 34790086 ps
CPU time 1.56 seconds
Started Jun 09 12:39:23 PM PDT 24
Finished Jun 09 12:39:25 PM PDT 24
Peak memory 197652 kb
Host smart-d8c546a8-c374-4236-b780-2ca41a6ca6e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804751517 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2804751517
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3188350982
Short name T548
Test name
Test status
Simulation time 14734029 ps
CPU time 0.61 seconds
Started Jun 09 12:39:25 PM PDT 24
Finished Jun 09 12:39:26 PM PDT 24
Peak memory 182712 kb
Host smart-201f1517-9c66-4190-b228-d2ba6ca6bd1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188350982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3188350982
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3660696361
Short name T485
Test name
Test status
Simulation time 11450767 ps
CPU time 0.58 seconds
Started Jun 09 12:39:24 PM PDT 24
Finished Jun 09 12:39:24 PM PDT 24
Peak memory 182736 kb
Host smart-d0f91159-74f7-4e9b-b200-501b4bc7c360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660696361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3660696361
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2851123621
Short name T537
Test name
Test status
Simulation time 38888553 ps
CPU time 0.77 seconds
Started Jun 09 12:39:26 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 193420 kb
Host smart-8314066b-b8da-4149-80cf-1e7af308c626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851123621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2851123621
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3241882721
Short name T500
Test name
Test status
Simulation time 92059680 ps
CPU time 1.26 seconds
Started Jun 09 12:39:27 PM PDT 24
Finished Jun 09 12:39:28 PM PDT 24
Peak memory 196216 kb
Host smart-72605df2-58a8-4846-ab26-32027377d613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241882721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3241882721
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2174512418
Short name T108
Test name
Test status
Simulation time 70978660 ps
CPU time 1.1 seconds
Started Jun 09 12:39:23 PM PDT 24
Finished Jun 09 12:39:25 PM PDT 24
Peak memory 195028 kb
Host smart-98326b13-45b0-41f8-82a8-71b7c5ba649f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174512418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2174512418
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1833786270
Short name T561
Test name
Test status
Simulation time 26422323 ps
CPU time 0.8 seconds
Started Jun 09 12:39:28 PM PDT 24
Finished Jun 09 12:39:30 PM PDT 24
Peak memory 196464 kb
Host smart-11e141f6-7c03-440f-986a-013b9f032eaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833786270 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1833786270
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4181713945
Short name T482
Test name
Test status
Simulation time 19145845 ps
CPU time 0.58 seconds
Started Jun 09 12:39:31 PM PDT 24
Finished Jun 09 12:39:32 PM PDT 24
Peak memory 182728 kb
Host smart-722ad479-185a-4b24-ac5a-0f9c206f0c9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181713945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4181713945
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1839629023
Short name T536
Test name
Test status
Simulation time 36896446 ps
CPU time 0.54 seconds
Started Jun 09 12:39:27 PM PDT 24
Finished Jun 09 12:39:28 PM PDT 24
Peak memory 182320 kb
Host smart-85a4efab-52a8-4a00-802c-1207834d8aab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839629023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1839629023
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3313894850
Short name T531
Test name
Test status
Simulation time 33830698 ps
CPU time 0.79 seconds
Started Jun 09 12:39:29 PM PDT 24
Finished Jun 09 12:39:30 PM PDT 24
Peak memory 191760 kb
Host smart-b403f844-0ab3-4b34-89ed-ca2c20360e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313894850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3313894850
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1103777769
Short name T498
Test name
Test status
Simulation time 149846276 ps
CPU time 1 seconds
Started Jun 09 12:39:29 PM PDT 24
Finished Jun 09 12:39:30 PM PDT 24
Peak memory 197236 kb
Host smart-9ebda491-0131-4a27-bb85-1ef16f233e55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103777769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1103777769
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.686565550
Short name T566
Test name
Test status
Simulation time 723987690 ps
CPU time 1.48 seconds
Started Jun 09 12:39:25 PM PDT 24
Finished Jun 09 12:39:27 PM PDT 24
Peak memory 195460 kb
Host smart-7f9352d0-9941-4a2a-91ab-46414605b25d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686565550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.686565550
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2695158506
Short name T570
Test name
Test status
Simulation time 76113257 ps
CPU time 0.74 seconds
Started Jun 09 12:39:30 PM PDT 24
Finished Jun 09 12:39:31 PM PDT 24
Peak memory 195888 kb
Host smart-6dbc5ae6-ba67-4fec-bb68-cfcb6205dd12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695158506 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2695158506
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1359057191
Short name T89
Test name
Test status
Simulation time 38710168 ps
CPU time 0.56 seconds
Started Jun 09 12:39:29 PM PDT 24
Finished Jun 09 12:39:30 PM PDT 24
Peak memory 182736 kb
Host smart-d18d38d9-52df-4097-b70e-24ae204dfafd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359057191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1359057191
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.462965847
Short name T502
Test name
Test status
Simulation time 130873829 ps
CPU time 0.57 seconds
Started Jun 09 12:39:29 PM PDT 24
Finished Jun 09 12:39:30 PM PDT 24
Peak memory 182648 kb
Host smart-c9c6b900-e79e-42df-81ef-91cae8e30709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462965847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.462965847
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3672748665
Short name T547
Test name
Test status
Simulation time 65050725 ps
CPU time 0.68 seconds
Started Jun 09 12:39:27 PM PDT 24
Finished Jun 09 12:39:28 PM PDT 24
Peak memory 193108 kb
Host smart-41108f88-04c5-4fa9-9c1f-b17fd99de046
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672748665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3672748665
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3822702615
Short name T464
Test name
Test status
Simulation time 208417901 ps
CPU time 2.43 seconds
Started Jun 09 12:39:28 PM PDT 24
Finished Jun 09 12:39:31 PM PDT 24
Peak memory 197624 kb
Host smart-3e15919f-95c3-49d5-8284-923dc4bfb479
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822702615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3822702615
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3672440831
Short name T29
Test name
Test status
Simulation time 277945806 ps
CPU time 1.3 seconds
Started Jun 09 12:39:26 PM PDT 24
Finished Jun 09 12:39:28 PM PDT 24
Peak memory 194848 kb
Host smart-31cf2321-cd7d-4696-9265-727ba3cdafec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672440831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3672440831
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3432537024
Short name T245
Test name
Test status
Simulation time 578658974448 ps
CPU time 341.41 seconds
Started Jun 09 12:51:23 PM PDT 24
Finished Jun 09 12:57:05 PM PDT 24
Peak memory 182976 kb
Host smart-082c02b9-b3b1-41fc-b6b4-0c2a445e0bae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432537024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3432537024
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2859548543
Short name T447
Test name
Test status
Simulation time 11522128731 ps
CPU time 18.34 seconds
Started Jun 09 12:51:16 PM PDT 24
Finished Jun 09 12:51:35 PM PDT 24
Peak memory 182976 kb
Host smart-1390e3bd-0e03-413d-b1fd-8c6202a4c415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859548543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2859548543
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1076619792
Short name T308
Test name
Test status
Simulation time 756782234008 ps
CPU time 401.4 seconds
Started Jun 09 12:51:25 PM PDT 24
Finished Jun 09 12:58:07 PM PDT 24
Peak memory 182960 kb
Host smart-8627722e-1a5f-491a-a068-86a5ee6f79c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076619792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1076619792
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3328957727
Short name T435
Test name
Test status
Simulation time 441140865262 ps
CPU time 345.1 seconds
Started Jun 09 12:51:22 PM PDT 24
Finished Jun 09 12:57:08 PM PDT 24
Peak memory 182892 kb
Host smart-dce8b580-78ee-46b0-8873-1d0f5b49447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328957727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3328957727
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3603312862
Short name T165
Test name
Test status
Simulation time 108262435316 ps
CPU time 1464.91 seconds
Started Jun 09 12:51:22 PM PDT 24
Finished Jun 09 01:15:47 PM PDT 24
Peak memory 194524 kb
Host smart-f33ad5ad-0a90-4823-82d8-4f78403525a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603312862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3603312862
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3517829592
Short name T365
Test name
Test status
Simulation time 9106352963 ps
CPU time 16.81 seconds
Started Jun 09 12:51:23 PM PDT 24
Finished Jun 09 12:51:40 PM PDT 24
Peak memory 191192 kb
Host smart-82656f65-68c6-45d3-b366-19de9fb874eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517829592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3517829592
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.4215212318
Short name T17
Test name
Test status
Simulation time 74614498 ps
CPU time 0.79 seconds
Started Jun 09 12:51:22 PM PDT 24
Finished Jun 09 12:51:23 PM PDT 24
Peak memory 213276 kb
Host smart-f864a019-e14f-45a2-b80d-1565a79ef3fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215212318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4215212318
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3980587472
Short name T391
Test name
Test status
Simulation time 49246548392 ps
CPU time 66.77 seconds
Started Jun 09 12:51:40 PM PDT 24
Finished Jun 09 12:52:47 PM PDT 24
Peak memory 182992 kb
Host smart-7f5b1285-cf1c-45db-97d5-0a5fc40cbe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980587472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3980587472
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3587680063
Short name T416
Test name
Test status
Simulation time 145662720607 ps
CPU time 987.8 seconds
Started Jun 09 12:51:38 PM PDT 24
Finished Jun 09 01:08:06 PM PDT 24
Peak memory 191128 kb
Host smart-8ef4f33d-289f-4b98-86be-5a3ac810cce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587680063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3587680063
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1359909723
Short name T3
Test name
Test status
Simulation time 48701145853 ps
CPU time 98.63 seconds
Started Jun 09 12:51:41 PM PDT 24
Finished Jun 09 12:53:20 PM PDT 24
Peak memory 191188 kb
Host smart-8de8e5b5-245b-4fbd-b9f8-2255fd9d3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359909723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1359909723
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2585638797
Short name T25
Test name
Test status
Simulation time 148207109601 ps
CPU time 260.89 seconds
Started Jun 09 12:51:46 PM PDT 24
Finished Jun 09 12:56:07 PM PDT 24
Peak memory 183000 kb
Host smart-732efaea-ea2c-4a06-a77a-185a3f78a033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585638797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2585638797
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.3815798354
Short name T37
Test name
Test status
Simulation time 19115000660 ps
CPU time 63.75 seconds
Started Jun 09 12:51:41 PM PDT 24
Finished Jun 09 12:52:45 PM PDT 24
Peak memory 197620 kb
Host smart-bf9272f0-5c9c-4f1c-9da4-b37e14ae9567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815798354 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.3815798354
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.2116801343
Short name T335
Test name
Test status
Simulation time 346697456116 ps
CPU time 512.44 seconds
Started Jun 09 12:54:09 PM PDT 24
Finished Jun 09 01:02:41 PM PDT 24
Peak memory 191204 kb
Host smart-7238ff7f-7c6c-4f1b-b6b8-5c736a3a6f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116801343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2116801343
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3094466060
Short name T38
Test name
Test status
Simulation time 37362228567 ps
CPU time 52.56 seconds
Started Jun 09 12:54:11 PM PDT 24
Finished Jun 09 12:55:03 PM PDT 24
Peak memory 182860 kb
Host smart-e3a847a6-511f-4391-b885-11f2d25cf4f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094466060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3094466060
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1474973655
Short name T269
Test name
Test status
Simulation time 7434743681 ps
CPU time 16.09 seconds
Started Jun 09 12:54:08 PM PDT 24
Finished Jun 09 12:54:25 PM PDT 24
Peak memory 183236 kb
Host smart-65adba1e-3032-45cb-9ed4-60e6e6fcf333
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474973655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1474973655
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1343997404
Short name T276
Test name
Test status
Simulation time 231391134091 ps
CPU time 134.66 seconds
Started Jun 09 12:54:10 PM PDT 24
Finished Jun 09 12:56:25 PM PDT 24
Peak memory 191204 kb
Host smart-6f152b1f-d08f-4cd8-9560-1ec34100219a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343997404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1343997404
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3494793085
Short name T345
Test name
Test status
Simulation time 38929983787 ps
CPU time 33.37 seconds
Started Jun 09 12:54:15 PM PDT 24
Finished Jun 09 12:54:48 PM PDT 24
Peak memory 182996 kb
Host smart-4bba53ad-26db-4441-9e60-75218e98101c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494793085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3494793085
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1791063059
Short name T441
Test name
Test status
Simulation time 47684319358 ps
CPU time 77.6 seconds
Started Jun 09 12:54:14 PM PDT 24
Finished Jun 09 12:55:32 PM PDT 24
Peak memory 191180 kb
Host smart-c95bf354-d12b-4054-b63e-64a010551ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791063059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1791063059
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.359113628
Short name T434
Test name
Test status
Simulation time 78451923865 ps
CPU time 130.07 seconds
Started Jun 09 12:51:48 PM PDT 24
Finished Jun 09 12:53:59 PM PDT 24
Peak memory 183232 kb
Host smart-477e14c9-efe0-4b3d-bd7e-35d2f89b0003
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359113628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.359113628
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.67125512
Short name T438
Test name
Test status
Simulation time 58830390077 ps
CPU time 46.04 seconds
Started Jun 09 12:51:45 PM PDT 24
Finished Jun 09 12:52:32 PM PDT 24
Peak memory 182960 kb
Host smart-968b0614-a8cc-444c-bddc-36883d675e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67125512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.67125512
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.835007683
Short name T208
Test name
Test status
Simulation time 50007450749 ps
CPU time 96.35 seconds
Started Jun 09 12:51:45 PM PDT 24
Finished Jun 09 12:53:21 PM PDT 24
Peak memory 191212 kb
Host smart-2e38c6b5-3307-424a-a1ba-7000b94f95e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835007683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.835007683
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.427934644
Short name T374
Test name
Test status
Simulation time 160853344698 ps
CPU time 103.67 seconds
Started Jun 09 12:51:48 PM PDT 24
Finished Jun 09 12:53:32 PM PDT 24
Peak memory 183236 kb
Host smart-3487241a-055d-49cc-86b6-230c5d0ed8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427934644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.427934644
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3246476102
Short name T62
Test name
Test status
Simulation time 1751998522384 ps
CPU time 441.18 seconds
Started Jun 09 12:51:47 PM PDT 24
Finished Jun 09 12:59:08 PM PDT 24
Peak memory 191188 kb
Host smart-3d1039a3-119c-4f3d-aa86-d334a5058908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246476102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3246476102
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2659732375
Short name T354
Test name
Test status
Simulation time 37681227435 ps
CPU time 63.67 seconds
Started Jun 09 12:54:14 PM PDT 24
Finished Jun 09 12:55:18 PM PDT 24
Peak memory 183004 kb
Host smart-d9bbfdcd-8717-4e2e-87f2-34a72009b46e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659732375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2659732375
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1283476225
Short name T141
Test name
Test status
Simulation time 43710413450 ps
CPU time 258.22 seconds
Started Jun 09 12:54:21 PM PDT 24
Finished Jun 09 12:58:39 PM PDT 24
Peak memory 183008 kb
Host smart-77f90acd-8897-47c0-b144-0406dc990919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283476225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1283476225
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2349767746
Short name T424
Test name
Test status
Simulation time 622380650768 ps
CPU time 796.9 seconds
Started Jun 09 12:54:19 PM PDT 24
Finished Jun 09 01:07:37 PM PDT 24
Peak memory 191196 kb
Host smart-63d50184-e8c0-4f29-a65d-c30c2278a3cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349767746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2349767746
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1242774669
Short name T439
Test name
Test status
Simulation time 84218056430 ps
CPU time 126.38 seconds
Started Jun 09 12:54:20 PM PDT 24
Finished Jun 09 12:56:26 PM PDT 24
Peak memory 191180 kb
Host smart-62b6940c-1d97-40cf-aad4-dbbd552c4ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242774669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1242774669
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.809115506
Short name T129
Test name
Test status
Simulation time 46065502501 ps
CPU time 82.7 seconds
Started Jun 09 12:54:20 PM PDT 24
Finished Jun 09 12:55:43 PM PDT 24
Peak memory 182952 kb
Host smart-244c49c0-e100-45ec-9dd1-41e84cfdb305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809115506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.809115506
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1280530321
Short name T116
Test name
Test status
Simulation time 142638114120 ps
CPU time 263.18 seconds
Started Jun 09 12:54:21 PM PDT 24
Finished Jun 09 12:58:44 PM PDT 24
Peak memory 191116 kb
Host smart-6f96a426-3337-44ed-94b1-b7a4ba4415e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280530321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1280530321
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2386680158
Short name T41
Test name
Test status
Simulation time 797298410082 ps
CPU time 716.95 seconds
Started Jun 09 12:54:21 PM PDT 24
Finished Jun 09 01:06:18 PM PDT 24
Peak memory 191200 kb
Host smart-b1dbf524-b062-476b-bc74-0fd2af4fe55f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386680158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2386680158
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.470148571
Short name T219
Test name
Test status
Simulation time 5996398421 ps
CPU time 10.72 seconds
Started Jun 09 12:54:23 PM PDT 24
Finished Jun 09 12:54:34 PM PDT 24
Peak memory 183012 kb
Host smart-85d77ba0-ad24-4d37-919d-64ae4c02ff2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470148571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.470148571
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3022716201
Short name T27
Test name
Test status
Simulation time 19091747359 ps
CPU time 19.44 seconds
Started Jun 09 12:51:46 PM PDT 24
Finished Jun 09 12:52:06 PM PDT 24
Peak memory 183008 kb
Host smart-942a0e18-8939-408f-81a7-0f26d58683f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022716201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3022716201
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2549468504
Short name T422
Test name
Test status
Simulation time 119350454910 ps
CPU time 82.07 seconds
Started Jun 09 12:51:46 PM PDT 24
Finished Jun 09 12:53:08 PM PDT 24
Peak memory 182952 kb
Host smart-9d70e4b3-5947-4e42-a4a8-b9bcc27405c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549468504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2549468504
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2559185714
Short name T77
Test name
Test status
Simulation time 222235486363 ps
CPU time 151.56 seconds
Started Jun 09 12:51:45 PM PDT 24
Finished Jun 09 12:54:17 PM PDT 24
Peak memory 194980 kb
Host smart-f482eb02-8342-4303-874d-16186dc35bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559185714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2559185714
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2277228125
Short name T388
Test name
Test status
Simulation time 23825386 ps
CPU time 0.58 seconds
Started Jun 09 12:51:47 PM PDT 24
Finished Jun 09 12:51:47 PM PDT 24
Peak memory 182692 kb
Host smart-18233fde-4de2-42ea-8118-6abd83913644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277228125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2277228125
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.3840942408
Short name T80
Test name
Test status
Simulation time 24158409367 ps
CPU time 259.39 seconds
Started Jun 09 12:51:47 PM PDT 24
Finished Jun 09 12:56:06 PM PDT 24
Peak memory 197660 kb
Host smart-5c9fb443-741b-4a81-bbe6-2d2ba6f3aa4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840942408 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.3840942408
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1301267981
Short name T316
Test name
Test status
Simulation time 15899955735 ps
CPU time 134.34 seconds
Started Jun 09 12:54:19 PM PDT 24
Finished Jun 09 12:56:34 PM PDT 24
Peak memory 182976 kb
Host smart-9f40dfac-e299-4384-8dd6-64cd6bf4f3ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301267981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1301267981
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.744958891
Short name T161
Test name
Test status
Simulation time 344705738014 ps
CPU time 188.66 seconds
Started Jun 09 12:54:21 PM PDT 24
Finished Jun 09 12:57:30 PM PDT 24
Peak memory 191224 kb
Host smart-9f65e102-8c1d-4001-8be2-4be5568eed9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744958891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.744958891
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3896094236
Short name T123
Test name
Test status
Simulation time 44568142958 ps
CPU time 90.74 seconds
Started Jun 09 12:54:20 PM PDT 24
Finished Jun 09 12:55:51 PM PDT 24
Peak memory 191208 kb
Host smart-01cd4602-397d-4aa5-929a-586f51f58474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896094236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3896094236
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1154111267
Short name T229
Test name
Test status
Simulation time 511582374462 ps
CPU time 1933.26 seconds
Started Jun 09 12:54:26 PM PDT 24
Finished Jun 09 01:26:40 PM PDT 24
Peak memory 191208 kb
Host smart-99e0f831-3e4c-4da1-af4e-ddb75383dec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154111267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1154111267
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1729127019
Short name T268
Test name
Test status
Simulation time 122541548444 ps
CPU time 97.22 seconds
Started Jun 09 12:54:26 PM PDT 24
Finished Jun 09 12:56:03 PM PDT 24
Peak memory 191148 kb
Host smart-81531f21-020a-4ad7-857f-7b3e432eb202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729127019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1729127019
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3678474442
Short name T154
Test name
Test status
Simulation time 401311269598 ps
CPU time 1648.68 seconds
Started Jun 09 12:54:27 PM PDT 24
Finished Jun 09 01:21:56 PM PDT 24
Peak memory 191184 kb
Host smart-76fb117f-a3bd-4202-b0b2-f33d4c50cd10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678474442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3678474442
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1313960329
Short name T450
Test name
Test status
Simulation time 573204230472 ps
CPU time 303.68 seconds
Started Jun 09 12:54:27 PM PDT 24
Finished Jun 09 12:59:31 PM PDT 24
Peak memory 191204 kb
Host smart-4933c571-bab9-4f70-9765-95d1995465ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313960329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1313960329
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.4008966482
Short name T396
Test name
Test status
Simulation time 657137386272 ps
CPU time 271.15 seconds
Started Jun 09 12:51:45 PM PDT 24
Finished Jun 09 12:56:16 PM PDT 24
Peak memory 182984 kb
Host smart-8011e2f9-15b2-46a3-bc4e-93098f06ec26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008966482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.4008966482
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1905376975
Short name T173
Test name
Test status
Simulation time 107531210485 ps
CPU time 782.77 seconds
Started Jun 09 12:51:45 PM PDT 24
Finished Jun 09 01:04:48 PM PDT 24
Peak memory 191404 kb
Host smart-041c6d20-6687-4c22-b229-252e6ac4b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905376975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1905376975
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.4022176710
Short name T122
Test name
Test status
Simulation time 735926500648 ps
CPU time 4546.74 seconds
Started Jun 09 12:51:49 PM PDT 24
Finished Jun 09 02:07:36 PM PDT 24
Peak memory 191436 kb
Host smart-b6193087-1bda-4e6f-a31b-4461e46d6e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022176710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.4022176710
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3679781332
Short name T36
Test name
Test status
Simulation time 43548585349 ps
CPU time 344.07 seconds
Started Jun 09 12:51:45 PM PDT 24
Finished Jun 09 12:57:29 PM PDT 24
Peak memory 197652 kb
Host smart-6db22d37-731b-4666-b6f3-de30fa857082
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679781332 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3679781332
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.4070712740
Short name T46
Test name
Test status
Simulation time 135831900391 ps
CPU time 70.51 seconds
Started Jun 09 12:54:28 PM PDT 24
Finished Jun 09 12:55:39 PM PDT 24
Peak memory 191200 kb
Host smart-5ba5d0c5-0f24-4a56-8d9d-e90b34af359d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070712740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.4070712740
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2681580047
Short name T57
Test name
Test status
Simulation time 259690809235 ps
CPU time 169.29 seconds
Started Jun 09 12:54:25 PM PDT 24
Finished Jun 09 12:57:15 PM PDT 24
Peak memory 191184 kb
Host smart-e5670690-8612-41a7-858f-4ea8262ddadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681580047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2681580047
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.100481147
Short name T275
Test name
Test status
Simulation time 27448275129 ps
CPU time 143.91 seconds
Started Jun 09 12:54:27 PM PDT 24
Finished Jun 09 12:56:51 PM PDT 24
Peak memory 183004 kb
Host smart-121c67b1-7847-4c11-9e88-e6188e09b943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100481147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.100481147
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3570924168
Short name T158
Test name
Test status
Simulation time 68205813580 ps
CPU time 72.63 seconds
Started Jun 09 12:54:31 PM PDT 24
Finished Jun 09 12:55:44 PM PDT 24
Peak memory 182972 kb
Host smart-407a9c39-ab74-4f69-a61d-3434c45cfe72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570924168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3570924168
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.974842071
Short name T267
Test name
Test status
Simulation time 245346393139 ps
CPU time 587.96 seconds
Started Jun 09 12:54:31 PM PDT 24
Finished Jun 09 01:04:19 PM PDT 24
Peak memory 182920 kb
Host smart-67b50fd3-7efd-4d3b-8377-47c80c5b78f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974842071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.974842071
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3812791209
Short name T224
Test name
Test status
Simulation time 244227105960 ps
CPU time 160.12 seconds
Started Jun 09 12:54:32 PM PDT 24
Finished Jun 09 12:57:12 PM PDT 24
Peak memory 191148 kb
Host smart-d4433741-c1b0-48f2-9b18-05f6cc140f83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812791209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3812791209
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3708985372
Short name T172
Test name
Test status
Simulation time 2164096923 ps
CPU time 3.99 seconds
Started Jun 09 12:51:50 PM PDT 24
Finished Jun 09 12:51:54 PM PDT 24
Peak memory 183008 kb
Host smart-6306a8c3-33e7-4bbc-9763-11f6b5efbc2a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708985372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3708985372
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3795580178
Short name T410
Test name
Test status
Simulation time 233399704145 ps
CPU time 88.35 seconds
Started Jun 09 12:51:57 PM PDT 24
Finished Jun 09 12:53:26 PM PDT 24
Peak memory 182980 kb
Host smart-f361f77e-cf09-40d8-bb71-46c42740fa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795580178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3795580178
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.592138926
Short name T65
Test name
Test status
Simulation time 195091470047 ps
CPU time 178.54 seconds
Started Jun 09 12:51:48 PM PDT 24
Finished Jun 09 12:54:46 PM PDT 24
Peak memory 191120 kb
Host smart-f8296689-cdea-4ce1-911a-04cd851dad8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592138926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.592138926
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2432365965
Short name T413
Test name
Test status
Simulation time 292685633231 ps
CPU time 484.34 seconds
Started Jun 09 12:51:51 PM PDT 24
Finished Jun 09 12:59:56 PM PDT 24
Peak memory 191192 kb
Host smart-24a2fd99-d6ce-415e-a944-e212c9c9ab7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432365965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2432365965
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.706672548
Short name T24
Test name
Test status
Simulation time 81648789942 ps
CPU time 303.58 seconds
Started Jun 09 12:51:49 PM PDT 24
Finished Jun 09 12:56:53 PM PDT 24
Peak memory 197616 kb
Host smart-465b5649-fe57-4db2-a3c5-597652d313f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706672548 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.706672548
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3412427338
Short name T300
Test name
Test status
Simulation time 146048792989 ps
CPU time 275.83 seconds
Started Jun 09 12:54:31 PM PDT 24
Finished Jun 09 12:59:07 PM PDT 24
Peak memory 194460 kb
Host smart-33262c3f-5cf0-4cdc-bfd9-eaf70b1fafde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412427338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3412427338
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4263105607
Short name T429
Test name
Test status
Simulation time 445855976198 ps
CPU time 168.94 seconds
Started Jun 09 12:54:32 PM PDT 24
Finished Jun 09 12:57:21 PM PDT 24
Peak memory 194324 kb
Host smart-a547ae90-c93b-45c3-8ad1-1b907a5069bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263105607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4263105607
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1970776505
Short name T340
Test name
Test status
Simulation time 346169953863 ps
CPU time 489.91 seconds
Started Jun 09 12:54:39 PM PDT 24
Finished Jun 09 01:02:49 PM PDT 24
Peak memory 191200 kb
Host smart-be71be62-ef21-42f8-bc3b-4c4032d45a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970776505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1970776505
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.4008934387
Short name T263
Test name
Test status
Simulation time 1854112675589 ps
CPU time 379.09 seconds
Started Jun 09 12:54:37 PM PDT 24
Finished Jun 09 01:00:56 PM PDT 24
Peak memory 191204 kb
Host smart-dda3ab70-bd85-411f-b638-0dd72ebf7418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008934387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.4008934387
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1668216077
Short name T347
Test name
Test status
Simulation time 705200172066 ps
CPU time 341.52 seconds
Started Jun 09 12:54:36 PM PDT 24
Finished Jun 09 01:00:18 PM PDT 24
Peak memory 193548 kb
Host smart-dddbadb4-309a-42a2-89bd-c758bf59e464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668216077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1668216077
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1189997580
Short name T113
Test name
Test status
Simulation time 37910774607 ps
CPU time 27.28 seconds
Started Jun 09 12:54:40 PM PDT 24
Finished Jun 09 12:55:07 PM PDT 24
Peak memory 183008 kb
Host smart-1603f9fc-c172-4c69-a4e6-6445c326e1f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189997580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1189997580
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.528257883
Short name T223
Test name
Test status
Simulation time 244784890318 ps
CPU time 2067.79 seconds
Started Jun 09 12:54:37 PM PDT 24
Finished Jun 09 01:29:05 PM PDT 24
Peak memory 191212 kb
Host smart-9b72f6da-3153-4bed-a704-47b5de92ba70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528257883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.528257883
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2998660711
Short name T111
Test name
Test status
Simulation time 1958418046704 ps
CPU time 342.65 seconds
Started Jun 09 12:54:36 PM PDT 24
Finished Jun 09 01:00:19 PM PDT 24
Peak memory 191204 kb
Host smart-73bf63b8-3648-4aed-ac6d-f8aeab711da5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998660711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2998660711
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.44587518
Short name T384
Test name
Test status
Simulation time 53831276468 ps
CPU time 257.32 seconds
Started Jun 09 12:54:39 PM PDT 24
Finished Jun 09 12:58:57 PM PDT 24
Peak memory 183012 kb
Host smart-15fbae7c-782a-4d6f-abfa-8941f0e2fb6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44587518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.44587518
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1288622533
Short name T382
Test name
Test status
Simulation time 144121765604 ps
CPU time 213.23 seconds
Started Jun 09 12:51:48 PM PDT 24
Finished Jun 09 12:55:22 PM PDT 24
Peak memory 182988 kb
Host smart-5ce16620-299b-4424-9404-d5f58b3270e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288622533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1288622533
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1238339644
Short name T433
Test name
Test status
Simulation time 26429907743 ps
CPU time 29.66 seconds
Started Jun 09 12:51:51 PM PDT 24
Finished Jun 09 12:52:21 PM PDT 24
Peak memory 182808 kb
Host smart-bfc48812-0380-4a94-9625-6f3d4e9ca0b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238339644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1238339644
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.872499149
Short name T21
Test name
Test status
Simulation time 8199436425 ps
CPU time 14.33 seconds
Started Jun 09 12:51:49 PM PDT 24
Finished Jun 09 12:52:03 PM PDT 24
Peak memory 191172 kb
Host smart-2633c8fb-5e27-4e48-83d5-e8488b049035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872499149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.872499149
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.4040608718
Short name T19
Test name
Test status
Simulation time 1517358165363 ps
CPU time 1677.94 seconds
Started Jun 09 12:51:50 PM PDT 24
Finished Jun 09 01:19:48 PM PDT 24
Peak memory 191192 kb
Host smart-482e8010-52a8-4615-b86f-421271f9a9c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040608718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.4040608718
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1228458474
Short name T44
Test name
Test status
Simulation time 12982532659 ps
CPU time 8.28 seconds
Started Jun 09 12:54:37 PM PDT 24
Finished Jun 09 12:54:46 PM PDT 24
Peak memory 183004 kb
Host smart-13615895-795b-4c93-a16b-7003fc1e10fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228458474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1228458474
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3310295042
Short name T157
Test name
Test status
Simulation time 497933666068 ps
CPU time 456.48 seconds
Started Jun 09 12:54:37 PM PDT 24
Finished Jun 09 01:02:13 PM PDT 24
Peak memory 191432 kb
Host smart-05c999f4-1425-4e6a-a09e-d2499118a00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310295042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3310295042
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1053290750
Short name T246
Test name
Test status
Simulation time 18672007881 ps
CPU time 28.55 seconds
Started Jun 09 12:54:38 PM PDT 24
Finished Jun 09 12:55:07 PM PDT 24
Peak memory 183012 kb
Host smart-f4403329-cb25-49fe-b2f8-99473eedec11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053290750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1053290750
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3128855666
Short name T184
Test name
Test status
Simulation time 253927438 ps
CPU time 0.9 seconds
Started Jun 09 12:54:39 PM PDT 24
Finished Jun 09 12:54:40 PM PDT 24
Peak memory 182800 kb
Host smart-a6cffd14-670a-430f-82bb-a6e184953a80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128855666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3128855666
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.4266769185
Short name T307
Test name
Test status
Simulation time 250439428387 ps
CPU time 344.94 seconds
Started Jun 09 12:54:43 PM PDT 24
Finished Jun 09 01:00:28 PM PDT 24
Peak memory 191212 kb
Host smart-f244ca77-9f38-4292-bea2-eded74442f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266769185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.4266769185
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.479302639
Short name T143
Test name
Test status
Simulation time 472159273369 ps
CPU time 474.83 seconds
Started Jun 09 12:54:49 PM PDT 24
Finished Jun 09 01:02:44 PM PDT 24
Peak memory 191212 kb
Host smart-d97e81a1-f94e-46e3-89ef-2f9119326608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479302639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.479302639
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3273641075
Short name T408
Test name
Test status
Simulation time 4551325881 ps
CPU time 3.62 seconds
Started Jun 09 12:54:47 PM PDT 24
Finished Jun 09 12:54:51 PM PDT 24
Peak memory 182996 kb
Host smart-48141d0e-dc98-40bc-8846-7920a6824e4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273641075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3273641075
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3834570879
Short name T146
Test name
Test status
Simulation time 1022731136332 ps
CPU time 688.82 seconds
Started Jun 09 12:54:42 PM PDT 24
Finished Jun 09 01:06:11 PM PDT 24
Peak memory 191184 kb
Host smart-4cf6905f-69eb-4f6e-ba67-24f41f4b16d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834570879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3834570879
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3890976837
Short name T120
Test name
Test status
Simulation time 191077497283 ps
CPU time 311.06 seconds
Started Jun 09 12:51:55 PM PDT 24
Finished Jun 09 12:57:06 PM PDT 24
Peak memory 182948 kb
Host smart-43a8acb2-01fe-4cb0-8215-3afb33fb927f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890976837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3890976837
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3912781135
Short name T401
Test name
Test status
Simulation time 125278862356 ps
CPU time 84.52 seconds
Started Jun 09 12:51:49 PM PDT 24
Finished Jun 09 12:53:14 PM PDT 24
Peak memory 182980 kb
Host smart-4ea76e78-fade-4442-bd72-6849f892f914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912781135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3912781135
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1318415892
Short name T42
Test name
Test status
Simulation time 56892225541 ps
CPU time 748.1 seconds
Started Jun 09 12:51:49 PM PDT 24
Finished Jun 09 01:04:18 PM PDT 24
Peak memory 191108 kb
Host smart-369cc3d0-ff00-4acc-adf2-9b7ec77e39cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318415892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1318415892
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2229113569
Short name T45
Test name
Test status
Simulation time 29285753999 ps
CPU time 397.19 seconds
Started Jun 09 12:51:57 PM PDT 24
Finished Jun 09 12:58:35 PM PDT 24
Peak memory 182984 kb
Host smart-f86c9f1b-1cb9-4c3d-bd00-cb1e45476161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229113569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2229113569
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2333467335
Short name T197
Test name
Test status
Simulation time 64510014226 ps
CPU time 23.87 seconds
Started Jun 09 12:51:57 PM PDT 24
Finished Jun 09 12:52:22 PM PDT 24
Peak memory 191192 kb
Host smart-2c8e25ca-eb0c-4815-bb1d-033925da1bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333467335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2333467335
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.2702026200
Short name T331
Test name
Test status
Simulation time 31352222665 ps
CPU time 15.58 seconds
Started Jun 09 12:54:44 PM PDT 24
Finished Jun 09 12:54:59 PM PDT 24
Peak memory 183004 kb
Host smart-f114b4bd-4eb5-4619-89f9-ac7734704de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702026200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2702026200
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.4105862627
Short name T193
Test name
Test status
Simulation time 70747483287 ps
CPU time 372.18 seconds
Started Jun 09 12:54:45 PM PDT 24
Finished Jun 09 01:00:57 PM PDT 24
Peak memory 191204 kb
Host smart-c2a78528-26d5-43d6-b77c-2be713f28532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105862627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4105862627
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1152469896
Short name T115
Test name
Test status
Simulation time 183230261253 ps
CPU time 98.54 seconds
Started Jun 09 12:54:49 PM PDT 24
Finished Jun 09 12:56:28 PM PDT 24
Peak memory 191200 kb
Host smart-e9060135-e62a-4ebd-b3ea-5fe35c6a0861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152469896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1152469896
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.61224523
Short name T440
Test name
Test status
Simulation time 48889140198 ps
CPU time 42.93 seconds
Started Jun 09 12:54:48 PM PDT 24
Finished Jun 09 12:55:32 PM PDT 24
Peak memory 182996 kb
Host smart-9466282f-6671-4c0b-83eb-00ba8bb99fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61224523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.61224523
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1478098728
Short name T67
Test name
Test status
Simulation time 104798029435 ps
CPU time 948.76 seconds
Started Jun 09 12:54:48 PM PDT 24
Finished Jun 09 01:10:37 PM PDT 24
Peak memory 182992 kb
Host smart-5e5a3a69-f60c-4363-98bb-d80da06946ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478098728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1478098728
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1872102124
Short name T338
Test name
Test status
Simulation time 210370388719 ps
CPU time 276.36 seconds
Started Jun 09 12:54:48 PM PDT 24
Finished Jun 09 12:59:25 PM PDT 24
Peak memory 183008 kb
Host smart-49494c78-a042-479a-b285-77e2bf00c691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872102124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1872102124
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.523577776
Short name T72
Test name
Test status
Simulation time 224431688823 ps
CPU time 84.72 seconds
Started Jun 09 12:54:49 PM PDT 24
Finished Jun 09 12:56:14 PM PDT 24
Peak memory 191208 kb
Host smart-93c51ebd-b0d8-41ae-952a-c83af4e9a4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523577776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.523577776
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2364826257
Short name T195
Test name
Test status
Simulation time 202986058271 ps
CPU time 251.75 seconds
Started Jun 09 12:54:51 PM PDT 24
Finished Jun 09 12:59:03 PM PDT 24
Peak memory 191204 kb
Host smart-9cea1617-d444-4ebc-a3aa-549e062c16f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364826257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2364826257
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3554055554
Short name T179
Test name
Test status
Simulation time 615426147374 ps
CPU time 570.58 seconds
Started Jun 09 12:54:48 PM PDT 24
Finished Jun 09 01:04:19 PM PDT 24
Peak memory 191192 kb
Host smart-a4640c71-e371-40ea-b3e4-40c9d00b90ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554055554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3554055554
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4116693155
Short name T235
Test name
Test status
Simulation time 246359708838 ps
CPU time 451.67 seconds
Started Jun 09 12:52:01 PM PDT 24
Finished Jun 09 12:59:33 PM PDT 24
Peak memory 183008 kb
Host smart-f32b2f61-81de-44a5-8e18-3698fccb2c75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116693155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4116693155
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1906252873
Short name T404
Test name
Test status
Simulation time 548209645957 ps
CPU time 241.15 seconds
Started Jun 09 12:52:00 PM PDT 24
Finished Jun 09 12:56:01 PM PDT 24
Peak memory 182984 kb
Host smart-b38cb0b0-a551-42f2-ab92-5ac613f8878b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906252873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1906252873
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3447985712
Short name T393
Test name
Test status
Simulation time 520480065 ps
CPU time 1.04 seconds
Started Jun 09 12:51:57 PM PDT 24
Finished Jun 09 12:51:58 PM PDT 24
Peak memory 193412 kb
Host smart-d7b2be35-80ef-4e38-9bca-d9bc82e66971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447985712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3447985712
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3877029357
Short name T214
Test name
Test status
Simulation time 2161483974148 ps
CPU time 424.32 seconds
Started Jun 09 12:51:56 PM PDT 24
Finished Jun 09 12:59:00 PM PDT 24
Peak memory 191200 kb
Host smart-d23ff556-bb6d-4bd0-9652-701bd6a29d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877029357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3877029357
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.2098779770
Short name T218
Test name
Test status
Simulation time 61511101069 ps
CPU time 19.29 seconds
Started Jun 09 12:54:51 PM PDT 24
Finished Jun 09 12:55:10 PM PDT 24
Peak memory 183008 kb
Host smart-39aeae93-dc7d-4fb9-95d6-d53f50d709cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098779770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2098779770
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3331839043
Short name T117
Test name
Test status
Simulation time 424116564315 ps
CPU time 1900.22 seconds
Started Jun 09 12:54:48 PM PDT 24
Finished Jun 09 01:26:29 PM PDT 24
Peak memory 191200 kb
Host smart-7a12b709-8b55-47f5-a6eb-430ed26cd054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331839043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3331839043
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1585581639
Short name T150
Test name
Test status
Simulation time 65716644778 ps
CPU time 110.73 seconds
Started Jun 09 12:54:55 PM PDT 24
Finished Jun 09 12:56:46 PM PDT 24
Peak memory 191152 kb
Host smart-9a98dfa9-5615-4fc5-a193-68c94e05b263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585581639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1585581639
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1583834343
Short name T168
Test name
Test status
Simulation time 198018276108 ps
CPU time 95.18 seconds
Started Jun 09 12:54:58 PM PDT 24
Finished Jun 09 12:56:34 PM PDT 24
Peak memory 191204 kb
Host smart-e85965f9-84a0-42cc-99fd-239b75ac86c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583834343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1583834343
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1449795950
Short name T190
Test name
Test status
Simulation time 147823810323 ps
CPU time 1377.4 seconds
Started Jun 09 12:54:53 PM PDT 24
Finished Jun 09 01:17:51 PM PDT 24
Peak memory 191144 kb
Host smart-951eaad4-a6a2-4715-b11d-7fcd172d8b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449795950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1449795950
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3852735306
Short name T169
Test name
Test status
Simulation time 181935316370 ps
CPU time 607.02 seconds
Started Jun 09 12:54:54 PM PDT 24
Finished Jun 09 01:05:02 PM PDT 24
Peak memory 191196 kb
Host smart-1fd6d313-03b5-460d-88a4-86145ed41789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852735306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3852735306
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3477782164
Short name T274
Test name
Test status
Simulation time 184317450807 ps
CPU time 67.54 seconds
Started Jun 09 12:54:59 PM PDT 24
Finished Jun 09 12:56:06 PM PDT 24
Peak memory 183004 kb
Host smart-7e4beae1-390f-4b1b-b50d-b18939780623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477782164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3477782164
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3273355991
Short name T280
Test name
Test status
Simulation time 110427224347 ps
CPU time 218.53 seconds
Started Jun 09 12:54:58 PM PDT 24
Finished Jun 09 12:58:37 PM PDT 24
Peak memory 191204 kb
Host smart-19aa4f0d-a103-44d9-8ed9-be661f073336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273355991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3273355991
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2676342119
Short name T137
Test name
Test status
Simulation time 51779305114 ps
CPU time 401.69 seconds
Started Jun 09 12:54:55 PM PDT 24
Finished Jun 09 01:01:37 PM PDT 24
Peak memory 191180 kb
Host smart-9b8e56c4-eed7-417b-a22c-326d5afcc683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676342119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2676342119
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3020193318
Short name T322
Test name
Test status
Simulation time 957902443491 ps
CPU time 600.92 seconds
Started Jun 09 12:51:55 PM PDT 24
Finished Jun 09 01:01:57 PM PDT 24
Peak memory 182992 kb
Host smart-b5d5114f-1c78-40a3-8cb6-3c4ad599bc94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020193318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3020193318
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3402538135
Short name T367
Test name
Test status
Simulation time 486801986126 ps
CPU time 404.78 seconds
Started Jun 09 12:51:56 PM PDT 24
Finished Jun 09 12:58:41 PM PDT 24
Peak memory 182984 kb
Host smart-1abf803c-0d9a-425a-9e51-1fe68795c2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402538135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3402538135
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1248954222
Short name T261
Test name
Test status
Simulation time 63972403764 ps
CPU time 1127.97 seconds
Started Jun 09 12:51:54 PM PDT 24
Finished Jun 09 01:10:42 PM PDT 24
Peak memory 183000 kb
Host smart-0d86a6b7-9f09-4ed8-9f14-2276205b2f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248954222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1248954222
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3003083532
Short name T26
Test name
Test status
Simulation time 36802847938 ps
CPU time 67.02 seconds
Started Jun 09 12:52:00 PM PDT 24
Finished Jun 09 12:53:07 PM PDT 24
Peak memory 191180 kb
Host smart-be79dcdb-b01a-42a3-84a9-1f3103e4747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003083532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3003083532
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2333316466
Short name T230
Test name
Test status
Simulation time 556898904636 ps
CPU time 674.02 seconds
Started Jun 09 12:54:56 PM PDT 24
Finished Jun 09 01:06:10 PM PDT 24
Peak memory 191188 kb
Host smart-50d1eaad-4376-4257-a9b5-b5170f2c2c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333316466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2333316466
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3636362866
Short name T110
Test name
Test status
Simulation time 199504973665 ps
CPU time 626.44 seconds
Started Jun 09 12:54:59 PM PDT 24
Finished Jun 09 01:05:26 PM PDT 24
Peak memory 191204 kb
Host smart-c13be36a-3e0d-4916-ad83-c86e3ddfc543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636362866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3636362866
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1872028227
Short name T336
Test name
Test status
Simulation time 199196373361 ps
CPU time 78.62 seconds
Started Jun 09 12:55:00 PM PDT 24
Finished Jun 09 12:56:19 PM PDT 24
Peak memory 183008 kb
Host smart-d7d0e82b-b19f-4351-884f-e63cd56a1fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872028227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1872028227
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2217717386
Short name T329
Test name
Test status
Simulation time 57600549731 ps
CPU time 88.62 seconds
Started Jun 09 12:55:00 PM PDT 24
Finished Jun 09 12:56:29 PM PDT 24
Peak memory 191176 kb
Host smart-5f73f432-ddb6-4ba3-b436-3220bf7d0b56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217717386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2217717386
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2129130303
Short name T405
Test name
Test status
Simulation time 23919975882 ps
CPU time 157.64 seconds
Started Jun 09 12:54:59 PM PDT 24
Finished Jun 09 12:57:37 PM PDT 24
Peak memory 182980 kb
Host smart-52507b69-9f8b-4e4b-bed7-7f08128f203c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129130303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2129130303
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2871740209
Short name T225
Test name
Test status
Simulation time 105729508074 ps
CPU time 171.6 seconds
Started Jun 09 12:54:59 PM PDT 24
Finished Jun 09 12:57:51 PM PDT 24
Peak memory 193712 kb
Host smart-be966c4a-9a4b-4d0a-b7fd-0b487458f050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871740209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2871740209
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.4258663791
Short name T318
Test name
Test status
Simulation time 137776037848 ps
CPU time 247.16 seconds
Started Jun 09 12:55:00 PM PDT 24
Finished Jun 09 12:59:07 PM PDT 24
Peak memory 191188 kb
Host smart-b605530b-ccb7-43c5-ac3c-2f6c9eef48d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258663791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.4258663791
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1986684981
Short name T337
Test name
Test status
Simulation time 125218249937 ps
CPU time 256.72 seconds
Started Jun 09 12:54:58 PM PDT 24
Finished Jun 09 12:59:15 PM PDT 24
Peak memory 191412 kb
Host smart-01632426-7133-41fd-b97d-0d1ef1c7686c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986684981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1986684981
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.19110321
Short name T290
Test name
Test status
Simulation time 507597795169 ps
CPU time 360.43 seconds
Started Jun 09 12:55:00 PM PDT 24
Finished Jun 09 01:01:01 PM PDT 24
Peak memory 191204 kb
Host smart-fb88d216-489f-490d-abab-0cf1888462d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.19110321
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2339299513
Short name T359
Test name
Test status
Simulation time 170890630091 ps
CPU time 273.94 seconds
Started Jun 09 12:52:01 PM PDT 24
Finished Jun 09 12:56:35 PM PDT 24
Peak memory 182976 kb
Host smart-f4fda17c-c764-4f92-bb44-d98d580129b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339299513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2339299513
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1468749211
Short name T151
Test name
Test status
Simulation time 33100318992 ps
CPU time 114.43 seconds
Started Jun 09 12:52:01 PM PDT 24
Finished Jun 09 12:53:56 PM PDT 24
Peak memory 191172 kb
Host smart-80578c9c-a987-4871-85da-72a4e0fea307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468749211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1468749211
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1730376648
Short name T397
Test name
Test status
Simulation time 229746084632 ps
CPU time 363.6 seconds
Started Jun 09 12:52:02 PM PDT 24
Finished Jun 09 12:58:05 PM PDT 24
Peak memory 194556 kb
Host smart-37441fb7-e24a-46dd-99f9-e3f95bd36db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730376648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1730376648
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1093849791
Short name T51
Test name
Test status
Simulation time 491259727973 ps
CPU time 658.26 seconds
Started Jun 09 12:55:01 PM PDT 24
Finished Jun 09 01:06:00 PM PDT 24
Peak memory 191208 kb
Host smart-a07f39f4-bd5b-45eb-8ff1-7f56f55ba0f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093849791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1093849791
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1245367410
Short name T205
Test name
Test status
Simulation time 505694647854 ps
CPU time 253.5 seconds
Started Jun 09 12:55:07 PM PDT 24
Finished Jun 09 12:59:21 PM PDT 24
Peak memory 191216 kb
Host smart-0030f30b-2160-4c36-8848-0b5a4ac6b236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245367410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1245367410
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3399445397
Short name T292
Test name
Test status
Simulation time 440122200944 ps
CPU time 637.41 seconds
Started Jun 09 12:55:05 PM PDT 24
Finished Jun 09 01:05:43 PM PDT 24
Peak memory 191208 kb
Host smart-26c659c8-f9cf-4a45-b5c3-f73e6a031587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399445397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3399445397
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1095997769
Short name T309
Test name
Test status
Simulation time 211111084362 ps
CPU time 193.59 seconds
Started Jun 09 12:55:07 PM PDT 24
Finished Jun 09 12:58:21 PM PDT 24
Peak memory 194020 kb
Host smart-3e772b23-2fb9-4df0-afb1-b03230e177b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095997769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1095997769
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.664263536
Short name T136
Test name
Test status
Simulation time 2986899853 ps
CPU time 3.91 seconds
Started Jun 09 12:55:04 PM PDT 24
Finished Jun 09 12:55:08 PM PDT 24
Peak memory 182996 kb
Host smart-999990d8-797f-4792-9da1-a09cfe2141eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664263536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.664263536
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2815011581
Short name T288
Test name
Test status
Simulation time 137449717347 ps
CPU time 84.98 seconds
Started Jun 09 12:55:03 PM PDT 24
Finished Jun 09 12:56:28 PM PDT 24
Peak memory 183012 kb
Host smart-fcd5a14b-e5c1-44ad-9907-eea57ad0cdf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815011581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2815011581
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.285035199
Short name T166
Test name
Test status
Simulation time 191378364435 ps
CPU time 179.43 seconds
Started Jun 09 12:55:05 PM PDT 24
Finished Jun 09 12:58:05 PM PDT 24
Peak memory 191208 kb
Host smart-aa39de4e-7ae1-4f9b-bd13-dd6ab7fbd15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285035199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.285035199
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2412636499
Short name T128
Test name
Test status
Simulation time 340074802277 ps
CPU time 285.37 seconds
Started Jun 09 12:55:09 PM PDT 24
Finished Jun 09 12:59:54 PM PDT 24
Peak memory 191204 kb
Host smart-e5d83c0f-a07f-4b9b-a23e-4abc968f7a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412636499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2412636499
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3097934784
Short name T314
Test name
Test status
Simulation time 163056117916 ps
CPU time 293.74 seconds
Started Jun 09 12:55:10 PM PDT 24
Finished Jun 09 01:00:04 PM PDT 24
Peak memory 191216 kb
Host smart-b43087cb-5a84-41a1-8c8e-605851d4cfa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097934784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3097934784
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1547723886
Short name T286
Test name
Test status
Simulation time 173684498545 ps
CPU time 267.01 seconds
Started Jun 09 12:51:26 PM PDT 24
Finished Jun 09 12:55:53 PM PDT 24
Peak memory 182912 kb
Host smart-eddd6982-cab2-45b2-97a0-77db0a18a42c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547723886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1547723886
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2284582936
Short name T375
Test name
Test status
Simulation time 287133944099 ps
CPU time 136.99 seconds
Started Jun 09 12:51:27 PM PDT 24
Finished Jun 09 12:53:44 PM PDT 24
Peak memory 182896 kb
Host smart-afbc9cf6-3901-44bb-a202-174473a6b60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284582936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2284582936
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1553911127
Short name T353
Test name
Test status
Simulation time 104830396607 ps
CPU time 64.45 seconds
Started Jun 09 12:51:22 PM PDT 24
Finished Jun 09 12:52:27 PM PDT 24
Peak memory 193112 kb
Host smart-d49ad65d-496c-4e99-aac6-cd7644bb4de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553911127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1553911127
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1691004130
Short name T377
Test name
Test status
Simulation time 5157499880 ps
CPU time 4.94 seconds
Started Jun 09 12:51:28 PM PDT 24
Finished Jun 09 12:51:33 PM PDT 24
Peak memory 195284 kb
Host smart-2be4ea44-552d-4079-aadc-5de31420f34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691004130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1691004130
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.105207359
Short name T18
Test name
Test status
Simulation time 347881316 ps
CPU time 0.82 seconds
Started Jun 09 12:51:28 PM PDT 24
Finished Jun 09 12:51:29 PM PDT 24
Peak memory 213396 kb
Host smart-47dd0a0b-baa0-4b78-ba20-93372e3bb3fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105207359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.105207359
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.110009084
Short name T328
Test name
Test status
Simulation time 512868301552 ps
CPU time 500.41 seconds
Started Jun 09 12:51:29 PM PDT 24
Finished Jun 09 12:59:49 PM PDT 24
Peak memory 195344 kb
Host smart-9e9e6688-8899-49d1-b6b3-7218e7916316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110009084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.110009084
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2202355317
Short name T6
Test name
Test status
Simulation time 253406705021 ps
CPU time 411.78 seconds
Started Jun 09 12:52:01 PM PDT 24
Finished Jun 09 12:58:53 PM PDT 24
Peak memory 182980 kb
Host smart-d440e1d6-bdd6-4e5b-9e0b-72c7f95dd77b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202355317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2202355317
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2392889184
Short name T366
Test name
Test status
Simulation time 47638956743 ps
CPU time 75.93 seconds
Started Jun 09 12:52:02 PM PDT 24
Finished Jun 09 12:53:18 PM PDT 24
Peak memory 183212 kb
Host smart-00901fad-d3bd-4b8e-a745-76050b930507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392889184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2392889184
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1282698665
Short name T407
Test name
Test status
Simulation time 98798700 ps
CPU time 0.68 seconds
Started Jun 09 12:51:59 PM PDT 24
Finished Jun 09 12:52:00 PM PDT 24
Peak memory 182748 kb
Host smart-d2c1bd75-987b-48a1-8bf9-512cd8a8a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282698665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1282698665
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.251069386
Short name T271
Test name
Test status
Simulation time 473962364254 ps
CPU time 420.29 seconds
Started Jun 09 12:52:06 PM PDT 24
Finished Jun 09 12:59:06 PM PDT 24
Peak memory 182956 kb
Host smart-9e03ec9a-d9f3-42f1-b6af-f4fe00ce7c8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251069386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.251069386
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4292651527
Short name T451
Test name
Test status
Simulation time 469175036056 ps
CPU time 386.91 seconds
Started Jun 09 12:52:04 PM PDT 24
Finished Jun 09 12:58:31 PM PDT 24
Peak memory 182976 kb
Host smart-509cc510-6791-4966-be77-d48f85a12cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292651527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4292651527
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.883897482
Short name T368
Test name
Test status
Simulation time 565004284 ps
CPU time 1.35 seconds
Started Jun 09 12:52:06 PM PDT 24
Finished Jun 09 12:52:08 PM PDT 24
Peak memory 182760 kb
Host smart-3cdbcc7f-570d-4958-b5ce-7db2a5da2896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883897482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.883897482
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2101421267
Short name T4
Test name
Test status
Simulation time 136166762649 ps
CPU time 203.86 seconds
Started Jun 09 12:52:06 PM PDT 24
Finished Jun 09 12:55:30 PM PDT 24
Peak memory 182996 kb
Host smart-d0e86ffa-15cb-4def-806d-e64829e90073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101421267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2101421267
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4254579425
Short name T264
Test name
Test status
Simulation time 105262854965 ps
CPU time 200.44 seconds
Started Jun 09 12:52:04 PM PDT 24
Finished Jun 09 12:55:25 PM PDT 24
Peak memory 183212 kb
Host smart-9d86e9af-a272-4dec-afe3-c8ff206b432d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254579425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4254579425
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1157284855
Short name T40
Test name
Test status
Simulation time 19537725263 ps
CPU time 16.96 seconds
Started Jun 09 12:52:06 PM PDT 24
Finished Jun 09 12:52:23 PM PDT 24
Peak memory 182956 kb
Host smart-1ff43c6c-4807-4e75-965f-be6ec3aafc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157284855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1157284855
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1143364463
Short name T305
Test name
Test status
Simulation time 71534414817 ps
CPU time 133.96 seconds
Started Jun 09 12:52:04 PM PDT 24
Finished Jun 09 12:54:19 PM PDT 24
Peak memory 191188 kb
Host smart-84955568-bdd3-4325-a133-04884a566a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143364463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1143364463
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3555723809
Short name T315
Test name
Test status
Simulation time 149999495741 ps
CPU time 1638.07 seconds
Started Jun 09 12:52:03 PM PDT 24
Finished Jun 09 01:19:22 PM PDT 24
Peak memory 182992 kb
Host smart-76b770d3-3cd3-405c-b90c-02f0fc3e3b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555723809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3555723809
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2876369240
Short name T446
Test name
Test status
Simulation time 41449327 ps
CPU time 0.55 seconds
Started Jun 09 12:52:04 PM PDT 24
Finished Jun 09 12:52:04 PM PDT 24
Peak memory 182780 kb
Host smart-fa706058-5616-4aa1-aea5-df7a2c86033d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876369240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2876369240
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2052253268
Short name T412
Test name
Test status
Simulation time 454439220039 ps
CPU time 264.19 seconds
Started Jun 09 12:52:11 PM PDT 24
Finished Jun 09 12:56:36 PM PDT 24
Peak memory 183000 kb
Host smart-6e68b8f9-f7cd-4218-9147-1e978723f092
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052253268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2052253268
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1293092667
Short name T419
Test name
Test status
Simulation time 80802940555 ps
CPU time 60.77 seconds
Started Jun 09 12:52:11 PM PDT 24
Finished Jun 09 12:53:12 PM PDT 24
Peak memory 182972 kb
Host smart-c2d8d512-ea7f-4a82-8e53-7024762614ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293092667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1293092667
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.203801847
Short name T149
Test name
Test status
Simulation time 124351596698 ps
CPU time 88.4 seconds
Started Jun 09 12:52:10 PM PDT 24
Finished Jun 09 12:53:39 PM PDT 24
Peak memory 194316 kb
Host smart-739611c3-4d50-4cd4-94df-d181c045fee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203801847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.203801847
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3738035771
Short name T13
Test name
Test status
Simulation time 17972373473 ps
CPU time 143 seconds
Started Jun 09 12:52:11 PM PDT 24
Finished Jun 09 12:54:34 PM PDT 24
Peak memory 196592 kb
Host smart-0218c9b5-e06c-45bb-b245-975754ed22b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738035771 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3738035771
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1954791523
Short name T131
Test name
Test status
Simulation time 1448026460159 ps
CPU time 356.15 seconds
Started Jun 09 12:52:12 PM PDT 24
Finished Jun 09 12:58:08 PM PDT 24
Peak memory 183232 kb
Host smart-8509fc35-b59f-4297-ac8c-7b31ea427abe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954791523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1954791523
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3234221573
Short name T390
Test name
Test status
Simulation time 362364783529 ps
CPU time 149.91 seconds
Started Jun 09 12:52:10 PM PDT 24
Finished Jun 09 12:54:40 PM PDT 24
Peak memory 182976 kb
Host smart-5fee3a54-d18a-4ca9-a9ab-806a360ce2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234221573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3234221573
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3957915595
Short name T53
Test name
Test status
Simulation time 37154805855 ps
CPU time 514.37 seconds
Started Jun 09 12:52:09 PM PDT 24
Finished Jun 09 01:00:44 PM PDT 24
Peak memory 191148 kb
Host smart-f6877db9-32dc-4754-bb67-0bccf895f398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957915595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3957915595
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2127050608
Short name T273
Test name
Test status
Simulation time 142276496333 ps
CPU time 85.55 seconds
Started Jun 09 12:52:10 PM PDT 24
Finished Jun 09 12:53:36 PM PDT 24
Peak memory 182964 kb
Host smart-6df3f3f9-bc97-48df-9910-2094d45824af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127050608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2127050608
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2714793058
Short name T147
Test name
Test status
Simulation time 423959712129 ps
CPU time 366.97 seconds
Started Jun 09 12:52:11 PM PDT 24
Finished Jun 09 12:58:18 PM PDT 24
Peak memory 183000 kb
Host smart-4bac05e2-502f-4fd6-b9f9-71843c991e8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714793058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2714793058
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3611832675
Short name T394
Test name
Test status
Simulation time 107838041986 ps
CPU time 69.18 seconds
Started Jun 09 12:52:17 PM PDT 24
Finished Jun 09 12:53:26 PM PDT 24
Peak memory 182988 kb
Host smart-3050ec97-e6c5-4835-830e-123be28e0ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611832675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3611832675
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.697082460
Short name T133
Test name
Test status
Simulation time 42656738504 ps
CPU time 350.16 seconds
Started Jun 09 12:52:11 PM PDT 24
Finished Jun 09 12:58:02 PM PDT 24
Peak memory 191096 kb
Host smart-6eb56e0e-7b1d-4da3-9da3-24fdac86e3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697082460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.697082460
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.652084796
Short name T196
Test name
Test status
Simulation time 1535002956084 ps
CPU time 838.87 seconds
Started Jun 09 12:52:16 PM PDT 24
Finished Jun 09 01:06:16 PM PDT 24
Peak memory 182996 kb
Host smart-1c10c3f4-b6d2-4839-b0e6-5ed043df99a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652084796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.652084796
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3666759496
Short name T360
Test name
Test status
Simulation time 261896360271 ps
CPU time 248 seconds
Started Jun 09 12:52:17 PM PDT 24
Finished Jun 09 12:56:25 PM PDT 24
Peak memory 182996 kb
Host smart-9612a327-9877-4f75-b8ea-9b5701740beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666759496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3666759496
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1575518864
Short name T295
Test name
Test status
Simulation time 23021460798 ps
CPU time 61.35 seconds
Started Jun 09 12:52:17 PM PDT 24
Finished Jun 09 12:53:18 PM PDT 24
Peak memory 191184 kb
Host smart-2da1188d-825d-4963-b13b-a8766ec57fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575518864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1575518864
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.4255041075
Short name T428
Test name
Test status
Simulation time 859443997 ps
CPU time 10.04 seconds
Started Jun 09 12:52:17 PM PDT 24
Finished Jun 09 12:52:28 PM PDT 24
Peak memory 194428 kb
Host smart-ccb2ab00-9d3e-471c-bbde-413532fc4ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255041075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.4255041075
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3118618733
Short name T302
Test name
Test status
Simulation time 936995087 ps
CPU time 2.04 seconds
Started Jun 09 12:52:17 PM PDT 24
Finished Jun 09 12:52:20 PM PDT 24
Peak memory 182772 kb
Host smart-4373fb4c-d27e-432a-8439-e0084ad7ce6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118618733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3118618733
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.832979119
Short name T402
Test name
Test status
Simulation time 142170026325 ps
CPU time 233.45 seconds
Started Jun 09 12:52:17 PM PDT 24
Finished Jun 09 12:56:11 PM PDT 24
Peak memory 183240 kb
Host smart-89b106ae-c86c-493e-b17f-2275a4f5ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832979119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.832979119
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3080817279
Short name T423
Test name
Test status
Simulation time 150174313361 ps
CPU time 95.97 seconds
Started Jun 09 12:52:29 PM PDT 24
Finished Jun 09 12:54:05 PM PDT 24
Peak memory 191100 kb
Host smart-cb12bc25-04c5-4477-b096-d71311dc494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080817279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3080817279
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3806303088
Short name T32
Test name
Test status
Simulation time 69643865518 ps
CPU time 734.89 seconds
Started Jun 09 12:52:28 PM PDT 24
Finished Jun 09 01:04:43 PM PDT 24
Peak memory 207296 kb
Host smart-f1f2b539-876e-44a3-863f-d9080336938c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806303088 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3806303088
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3279897257
Short name T181
Test name
Test status
Simulation time 110609941802 ps
CPU time 199.33 seconds
Started Jun 09 12:52:27 PM PDT 24
Finished Jun 09 12:55:47 PM PDT 24
Peak memory 182996 kb
Host smart-e9a3de20-1bd9-476b-b4c2-1ee0a8da2a38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279897257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3279897257
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.24861625
Short name T381
Test name
Test status
Simulation time 77551296002 ps
CPU time 49.63 seconds
Started Jun 09 12:52:28 PM PDT 24
Finished Jun 09 12:53:18 PM PDT 24
Peak memory 182892 kb
Host smart-150dc462-4ae8-4840-92f4-0aa9e76be7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24861625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.24861625
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.764766435
Short name T332
Test name
Test status
Simulation time 51478818484 ps
CPU time 100.87 seconds
Started Jun 09 12:52:23 PM PDT 24
Finished Jun 09 12:54:04 PM PDT 24
Peak memory 191152 kb
Host smart-8247bd2b-b548-41df-a582-84ac9cbed3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764766435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.764766435
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3619831824
Short name T383
Test name
Test status
Simulation time 45175357365 ps
CPU time 133.75 seconds
Started Jun 09 12:52:28 PM PDT 24
Finished Jun 09 12:54:42 PM PDT 24
Peak memory 182988 kb
Host smart-2e807942-fbfd-4abb-9384-07cff09c36ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619831824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3619831824
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1395437299
Short name T427
Test name
Test status
Simulation time 243809007586 ps
CPU time 99.5 seconds
Started Jun 09 12:52:22 PM PDT 24
Finished Jun 09 12:54:02 PM PDT 24
Peak memory 193988 kb
Host smart-9817bd65-770a-468f-b576-55850a7df3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395437299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1395437299
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2021490683
Short name T352
Test name
Test status
Simulation time 48661078236 ps
CPU time 89.92 seconds
Started Jun 09 12:52:28 PM PDT 24
Finished Jun 09 12:53:58 PM PDT 24
Peak memory 183016 kb
Host smart-1e5838e4-4e50-47a9-9b14-9d32e86b7e4a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021490683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2021490683
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1960250568
Short name T399
Test name
Test status
Simulation time 50780965595 ps
CPU time 79.17 seconds
Started Jun 09 12:52:28 PM PDT 24
Finished Jun 09 12:53:48 PM PDT 24
Peak memory 182984 kb
Host smart-2e004dda-667a-4dc5-a7ec-e9a44f10f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960250568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1960250568
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3267332756
Short name T192
Test name
Test status
Simulation time 91474288050 ps
CPU time 83.34 seconds
Started Jun 09 12:52:30 PM PDT 24
Finished Jun 09 12:53:53 PM PDT 24
Peak memory 191192 kb
Host smart-09889615-28bd-43c8-a2dc-b61a25573640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267332756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3267332756
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.637801837
Short name T215
Test name
Test status
Simulation time 503354915187 ps
CPU time 647.87 seconds
Started Jun 09 12:51:28 PM PDT 24
Finished Jun 09 01:02:16 PM PDT 24
Peak memory 182980 kb
Host smart-60322818-5ff3-4e88-883c-7e2128704e7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637801837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.637801837
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.439328028
Short name T437
Test name
Test status
Simulation time 152431273773 ps
CPU time 201.2 seconds
Started Jun 09 12:51:30 PM PDT 24
Finished Jun 09 12:54:51 PM PDT 24
Peak memory 182972 kb
Host smart-de7abc92-7008-4b19-b8cb-09df0d705841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439328028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.439328028
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.737510896
Short name T425
Test name
Test status
Simulation time 517002690187 ps
CPU time 133.98 seconds
Started Jun 09 12:51:29 PM PDT 24
Finished Jun 09 12:53:43 PM PDT 24
Peak memory 183004 kb
Host smart-2573cfe9-a97c-4b37-97ce-c206e6536f05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737510896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.737510896
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3246343972
Short name T380
Test name
Test status
Simulation time 162189793 ps
CPU time 0.59 seconds
Started Jun 09 12:51:27 PM PDT 24
Finished Jun 09 12:51:27 PM PDT 24
Peak memory 182740 kb
Host smart-6469f6a4-dce6-4ee8-9954-f611a83ff0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246343972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3246343972
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.190323033
Short name T14
Test name
Test status
Simulation time 39338202 ps
CPU time 0.75 seconds
Started Jun 09 12:51:27 PM PDT 24
Finished Jun 09 12:51:28 PM PDT 24
Peak memory 213328 kb
Host smart-f5caadff-f116-4e3e-8a98-d3cd395b0341
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190323033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.190323033
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4284847603
Short name T330
Test name
Test status
Simulation time 1966092432475 ps
CPU time 1237.05 seconds
Started Jun 09 12:52:33 PM PDT 24
Finished Jun 09 01:13:10 PM PDT 24
Peak memory 183004 kb
Host smart-365ffec9-2ac2-4c08-b0c2-50d2130ac517
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284847603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.4284847603
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random.2215167755
Short name T140
Test name
Test status
Simulation time 1010040138141 ps
CPU time 2132.89 seconds
Started Jun 09 12:52:26 PM PDT 24
Finished Jun 09 01:27:59 PM PDT 24
Peak memory 191128 kb
Host smart-06422098-624b-4afe-a4a4-cbaeb748acd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215167755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2215167755
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.799173313
Short name T400
Test name
Test status
Simulation time 232288170 ps
CPU time 0.64 seconds
Started Jun 09 12:52:32 PM PDT 24
Finished Jun 09 12:52:33 PM PDT 24
Peak memory 183032 kb
Host smart-044d59bf-be02-496c-83ac-d16f735692b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799173313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.799173313
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1551602160
Short name T213
Test name
Test status
Simulation time 860005600709 ps
CPU time 736.31 seconds
Started Jun 09 12:52:32 PM PDT 24
Finished Jun 09 01:04:49 PM PDT 24
Peak memory 195608 kb
Host smart-bb1c9f9e-7476-47d1-b568-be14a2e2b31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551602160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1551602160
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1627735376
Short name T299
Test name
Test status
Simulation time 610928059153 ps
CPU time 515.93 seconds
Started Jun 09 12:52:33 PM PDT 24
Finished Jun 09 01:01:09 PM PDT 24
Peak memory 183000 kb
Host smart-387c6df1-9f51-4bd1-a073-01ce3cf271b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627735376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1627735376
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2931008701
Short name T364
Test name
Test status
Simulation time 85212481393 ps
CPU time 135.26 seconds
Started Jun 09 12:52:31 PM PDT 24
Finished Jun 09 12:54:46 PM PDT 24
Peak memory 182976 kb
Host smart-d70cbc2b-411c-40f7-bcee-1c876446fc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931008701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2931008701
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.941683116
Short name T304
Test name
Test status
Simulation time 60804127491 ps
CPU time 47.48 seconds
Started Jun 09 12:52:34 PM PDT 24
Finished Jun 09 12:53:21 PM PDT 24
Peak memory 182996 kb
Host smart-f6591995-e067-4368-85d7-e38ab09d63d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941683116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.941683116
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1087486827
Short name T249
Test name
Test status
Simulation time 367442766134 ps
CPU time 205.49 seconds
Started Jun 09 12:52:33 PM PDT 24
Finished Jun 09 12:55:58 PM PDT 24
Peak memory 191160 kb
Host smart-a26fec7e-3a6a-4fb4-8c62-ceca883155a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087486827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1087486827
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.4223699797
Short name T35
Test name
Test status
Simulation time 25299729020 ps
CPU time 214.05 seconds
Started Jun 09 12:52:36 PM PDT 24
Finished Jun 09 12:56:10 PM PDT 24
Peak memory 197632 kb
Host smart-1b288c51-c864-4895-b78d-47378277f3c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223699797 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.4223699797
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1540407106
Short name T321
Test name
Test status
Simulation time 371334911801 ps
CPU time 185.62 seconds
Started Jun 09 12:52:35 PM PDT 24
Finished Jun 09 12:55:41 PM PDT 24
Peak memory 182984 kb
Host smart-0a75c0e4-0e0a-4eb5-bb7e-2a732b25bdbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540407106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1540407106
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.167857991
Short name T449
Test name
Test status
Simulation time 119942656293 ps
CPU time 94.27 seconds
Started Jun 09 12:52:35 PM PDT 24
Finished Jun 09 12:54:09 PM PDT 24
Peak memory 182988 kb
Host smart-e15fb1f0-56e7-48e9-b2da-02ad2fed1b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167857991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.167857991
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1983361495
Short name T255
Test name
Test status
Simulation time 180525217355 ps
CPU time 356.79 seconds
Started Jun 09 12:52:35 PM PDT 24
Finished Jun 09 12:58:32 PM PDT 24
Peak memory 191152 kb
Host smart-e8c6f4c8-8fed-46d1-b99e-0e739c3fbae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983361495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1983361495
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.186331819
Short name T311
Test name
Test status
Simulation time 37805795846 ps
CPU time 19.57 seconds
Started Jun 09 12:52:38 PM PDT 24
Finished Jun 09 12:52:58 PM PDT 24
Peak memory 182956 kb
Host smart-715b20fd-6382-4cb4-857f-dfb1ebe3dadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186331819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.186331819
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3943667172
Short name T64
Test name
Test status
Simulation time 220784429766 ps
CPU time 94.74 seconds
Started Jun 09 12:52:38 PM PDT 24
Finished Jun 09 12:54:13 PM PDT 24
Peak memory 194848 kb
Host smart-fd8d066f-92f1-4332-b22e-958b7ae80d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943667172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3943667172
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.3833730208
Short name T47
Test name
Test status
Simulation time 59154745290 ps
CPU time 116.8 seconds
Started Jun 09 12:52:37 PM PDT 24
Finished Jun 09 12:54:34 PM PDT 24
Peak memory 197696 kb
Host smart-34192542-870e-45a2-832f-d3943ecab353
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833730208 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.3833730208
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4236889747
Short name T257
Test name
Test status
Simulation time 988597498207 ps
CPU time 419.1 seconds
Started Jun 09 12:52:37 PM PDT 24
Finished Jun 09 12:59:36 PM PDT 24
Peak memory 182976 kb
Host smart-e3f21c54-64dc-48ca-a698-28b75c49f3e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236889747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.4236889747
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3571948662
Short name T389
Test name
Test status
Simulation time 51299483299 ps
CPU time 75.59 seconds
Started Jun 09 12:52:38 PM PDT 24
Finished Jun 09 12:53:54 PM PDT 24
Peak memory 182980 kb
Host smart-2f4e71fc-0ca9-4e79-890a-a7c866e2e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571948662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3571948662
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.4000053299
Short name T339
Test name
Test status
Simulation time 71697942989 ps
CPU time 110.84 seconds
Started Jun 09 12:52:37 PM PDT 24
Finished Jun 09 12:54:28 PM PDT 24
Peak memory 191212 kb
Host smart-97d15cba-0344-4183-8b81-4be2a1f07d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000053299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.4000053299
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3133912796
Short name T248
Test name
Test status
Simulation time 209768653200 ps
CPU time 73.14 seconds
Started Jun 09 12:52:37 PM PDT 24
Finished Jun 09 12:53:51 PM PDT 24
Peak memory 191148 kb
Host smart-73da2f42-0af9-4c6d-9bca-a968edc6e4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133912796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3133912796
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2933023040
Short name T234
Test name
Test status
Simulation time 817327629970 ps
CPU time 730.54 seconds
Started Jun 09 12:52:44 PM PDT 24
Finished Jun 09 01:04:55 PM PDT 24
Peak memory 183008 kb
Host smart-3426d380-3299-418e-b94c-c5941c4ea54a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933023040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2933023040
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2779835641
Short name T406
Test name
Test status
Simulation time 51386556909 ps
CPU time 69.83 seconds
Started Jun 09 12:52:45 PM PDT 24
Finished Jun 09 12:53:55 PM PDT 24
Peak memory 182984 kb
Host smart-06d97e58-053c-4837-a1b4-828324f5e5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779835641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2779835641
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.638328219
Short name T206
Test name
Test status
Simulation time 110849258750 ps
CPU time 89.34 seconds
Started Jun 09 12:52:37 PM PDT 24
Finished Jun 09 12:54:07 PM PDT 24
Peak memory 191196 kb
Host smart-7eb6dc7f-ae17-4e01-abbe-b3408dbd19ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638328219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.638328219
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.4176127735
Short name T313
Test name
Test status
Simulation time 7449001369 ps
CPU time 11.3 seconds
Started Jun 09 12:52:42 PM PDT 24
Finished Jun 09 12:52:54 PM PDT 24
Peak memory 183252 kb
Host smart-dc4bcdeb-c4b2-4f60-b1ea-3e39bcf305c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176127735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.4176127735
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3777213104
Short name T431
Test name
Test status
Simulation time 114994996219 ps
CPU time 50.79 seconds
Started Jun 09 12:52:43 PM PDT 24
Finished Jun 09 12:53:34 PM PDT 24
Peak memory 182968 kb
Host smart-a0ac2116-9c5c-4556-80b4-80960f92c83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777213104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3777213104
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1152050067
Short name T5
Test name
Test status
Simulation time 243007308483 ps
CPU time 487.33 seconds
Started Jun 09 12:52:44 PM PDT 24
Finished Jun 09 01:00:52 PM PDT 24
Peak memory 191140 kb
Host smart-09a53d06-fd56-4eb8-8d82-4fdc2cf1a274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152050067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1152050067
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.954088465
Short name T372
Test name
Test status
Simulation time 101308804 ps
CPU time 0.65 seconds
Started Jun 09 12:52:44 PM PDT 24
Finished Jun 09 12:52:45 PM PDT 24
Peak memory 182688 kb
Host smart-ba35b2f3-b345-46ed-ae61-4b04417fc387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954088465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.954088465
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1386272482
Short name T285
Test name
Test status
Simulation time 182037266724 ps
CPU time 109.49 seconds
Started Jun 09 12:52:48 PM PDT 24
Finished Jun 09 12:54:37 PM PDT 24
Peak memory 182984 kb
Host smart-a3aad54f-d20a-4211-89b6-c91c8c6b0e66
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386272482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1386272482
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1072880757
Short name T357
Test name
Test status
Simulation time 990213927248 ps
CPU time 411.41 seconds
Started Jun 09 12:52:48 PM PDT 24
Finished Jun 09 12:59:40 PM PDT 24
Peak memory 182988 kb
Host smart-ff9964fd-0ed1-4a49-b69b-927ba70ac33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072880757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1072880757
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2981807668
Short name T199
Test name
Test status
Simulation time 108079625540 ps
CPU time 357.22 seconds
Started Jun 09 12:52:49 PM PDT 24
Finished Jun 09 12:58:46 PM PDT 24
Peak memory 191184 kb
Host smart-ef0a77a2-b16f-4300-8b47-a823c8e7a5b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981807668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2981807668
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.50180130
Short name T443
Test name
Test status
Simulation time 31270181841 ps
CPU time 122.5 seconds
Started Jun 09 12:52:48 PM PDT 24
Finished Jun 09 12:54:51 PM PDT 24
Peak memory 191172 kb
Host smart-4d9c0b15-7259-4a10-a47e-34a8c3635f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50180130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.50180130
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.670036786
Short name T61
Test name
Test status
Simulation time 6690115127966 ps
CPU time 1827.42 seconds
Started Jun 09 12:52:49 PM PDT 24
Finished Jun 09 01:23:17 PM PDT 24
Peak memory 191188 kb
Host smart-04b629a1-d7bc-4cf2-aa9e-ba9c017d4dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670036786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
670036786
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3659365542
Short name T409
Test name
Test status
Simulation time 106979663207 ps
CPU time 162.07 seconds
Started Jun 09 12:52:55 PM PDT 24
Finished Jun 09 12:55:37 PM PDT 24
Peak memory 182976 kb
Host smart-3c94a3ea-1542-4af8-b854-f0fed89defb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659365542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3659365542
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3669383406
Short name T426
Test name
Test status
Simulation time 143588575312 ps
CPU time 72.57 seconds
Started Jun 09 12:52:49 PM PDT 24
Finished Jun 09 12:54:02 PM PDT 24
Peak memory 182868 kb
Host smart-7b06dbc1-20aa-4624-95d2-a7b28b337f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669383406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3669383406
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3157003070
Short name T403
Test name
Test status
Simulation time 80550900743 ps
CPU time 35.11 seconds
Started Jun 09 12:52:53 PM PDT 24
Finished Jun 09 12:53:29 PM PDT 24
Peak memory 194828 kb
Host smart-6312efcc-4c4e-4e93-aba1-98662c95a0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157003070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3157003070
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.743180704
Short name T11
Test name
Test status
Simulation time 239573064538 ps
CPU time 650.47 seconds
Started Jun 09 12:52:53 PM PDT 24
Finished Jun 09 01:03:44 PM PDT 24
Peak memory 207196 kb
Host smart-c5d146f9-80d6-404a-84d0-dc09d00b43ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743180704 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.743180704
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.632532334
Short name T436
Test name
Test status
Simulation time 21930361063 ps
CPU time 21.67 seconds
Started Jun 09 12:52:55 PM PDT 24
Finished Jun 09 12:53:17 PM PDT 24
Peak memory 183000 kb
Host smart-fe73f086-5a37-4fc7-ba61-3b998275b66f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632532334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.632532334
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2325254724
Short name T414
Test name
Test status
Simulation time 161875893174 ps
CPU time 220.11 seconds
Started Jun 09 12:52:53 PM PDT 24
Finished Jun 09 12:56:34 PM PDT 24
Peak memory 182980 kb
Host smart-ef319b97-cdbf-4642-a48a-6ca93d884212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325254724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2325254724
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2924712382
Short name T22
Test name
Test status
Simulation time 49482727152 ps
CPU time 253.77 seconds
Started Jun 09 12:52:54 PM PDT 24
Finished Jun 09 12:57:08 PM PDT 24
Peak memory 191200 kb
Host smart-ad94aaeb-a9ff-4874-bab9-7dbf74b61d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924712382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2924712382
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.84981716
Short name T350
Test name
Test status
Simulation time 32671442408 ps
CPU time 51.49 seconds
Started Jun 09 12:52:54 PM PDT 24
Finished Jun 09 12:53:46 PM PDT 24
Peak memory 191184 kb
Host smart-f0e33018-d12f-43e7-97b6-55062e8238d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84981716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.84981716
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1278454646
Short name T356
Test name
Test status
Simulation time 595783287456 ps
CPU time 227.18 seconds
Started Jun 09 12:52:59 PM PDT 24
Finished Jun 09 12:56:46 PM PDT 24
Peak memory 182996 kb
Host smart-840f0399-09a1-446b-9173-ffc6121c66bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278454646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1278454646
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1070626807
Short name T210
Test name
Test status
Simulation time 531337172596 ps
CPU time 281.73 seconds
Started Jun 09 12:52:59 PM PDT 24
Finished Jun 09 12:57:41 PM PDT 24
Peak memory 183004 kb
Host smart-025951a6-f259-43e0-9fe4-75419e556688
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070626807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1070626807
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2445529965
Short name T363
Test name
Test status
Simulation time 180699021916 ps
CPU time 269.13 seconds
Started Jun 09 12:52:59 PM PDT 24
Finished Jun 09 12:57:28 PM PDT 24
Peak memory 182960 kb
Host smart-d13a5fd2-89a8-412f-8cea-bca4fdaadf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445529965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2445529965
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3033649239
Short name T56
Test name
Test status
Simulation time 226940193748 ps
CPU time 202.36 seconds
Started Jun 09 12:53:00 PM PDT 24
Finished Jun 09 12:56:22 PM PDT 24
Peak memory 191200 kb
Host smart-04d409c9-4bfc-4737-aeca-7ecf8f3eaf3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033649239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3033649239
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.437511479
Short name T278
Test name
Test status
Simulation time 115772692923 ps
CPU time 788.61 seconds
Started Jun 09 12:53:00 PM PDT 24
Finished Jun 09 01:06:08 PM PDT 24
Peak memory 182972 kb
Host smart-b6f247ea-531b-4d47-822b-b8f4d3150dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437511479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.437511479
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.281645720
Short name T310
Test name
Test status
Simulation time 864036802491 ps
CPU time 2063.46 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 01:27:29 PM PDT 24
Peak memory 194904 kb
Host smart-1422ff95-cb4f-4033-8a8d-5eda3cc92989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281645720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
281645720
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1217243120
Short name T371
Test name
Test status
Simulation time 184842986876 ps
CPU time 264.42 seconds
Started Jun 09 12:51:29 PM PDT 24
Finished Jun 09 12:55:54 PM PDT 24
Peak memory 182988 kb
Host smart-bbe8d1ed-c914-4033-b103-93e64d39143d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217243120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1217243120
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.4137593567
Short name T362
Test name
Test status
Simulation time 301426060 ps
CPU time 0.71 seconds
Started Jun 09 12:51:27 PM PDT 24
Finished Jun 09 12:51:28 PM PDT 24
Peak memory 182768 kb
Host smart-9770b67d-fba7-48aa-9d01-8e6eca41c3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137593567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4137593567
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1538377951
Short name T15
Test name
Test status
Simulation time 86998978 ps
CPU time 0.9 seconds
Started Jun 09 12:51:34 PM PDT 24
Finished Jun 09 12:51:36 PM PDT 24
Peak memory 214568 kb
Host smart-45c1c4b7-8e3d-48e5-9c7f-f12837c8f9ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538377951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1538377951
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1783719594
Short name T238
Test name
Test status
Simulation time 34187280372 ps
CPU time 19.9 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 12:53:26 PM PDT 24
Peak memory 183204 kb
Host smart-7c0de7b3-5472-44c6-805f-11c90ab1231d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783719594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1783719594
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2380098689
Short name T358
Test name
Test status
Simulation time 744430827981 ps
CPU time 128.11 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 12:55:15 PM PDT 24
Peak memory 183212 kb
Host smart-18f2ce6a-552f-421a-b073-e911ac9ec375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380098689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2380098689
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2067795943
Short name T303
Test name
Test status
Simulation time 58361573143 ps
CPU time 153.71 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 12:55:41 PM PDT 24
Peak memory 191208 kb
Host smart-5d305821-b972-42ca-af1b-d54693a51c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067795943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2067795943
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1913955980
Short name T387
Test name
Test status
Simulation time 723729927 ps
CPU time 0.91 seconds
Started Jun 09 12:53:05 PM PDT 24
Finished Jun 09 12:53:06 PM PDT 24
Peak memory 191348 kb
Host smart-2fb9e1d9-5fb9-4a1d-9651-e84e047c53af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913955980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1913955980
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2117964022
Short name T373
Test name
Test status
Simulation time 49331658202 ps
CPU time 73.76 seconds
Started Jun 09 12:53:05 PM PDT 24
Finished Jun 09 12:54:19 PM PDT 24
Peak memory 182924 kb
Host smart-e73b46c5-b6c9-4e48-a5a7-6cbd81802ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117964022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2117964022
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1479524407
Short name T395
Test name
Test status
Simulation time 48779895296 ps
CPU time 83.33 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 12:54:29 PM PDT 24
Peak memory 183020 kb
Host smart-3fa830e1-033d-4b7e-b3d7-1b2888a5f99b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479524407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1479524407
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.3911920925
Short name T48
Test name
Test status
Simulation time 46012816712 ps
CPU time 175.94 seconds
Started Jun 09 12:53:05 PM PDT 24
Finished Jun 09 12:56:02 PM PDT 24
Peak memory 197652 kb
Host smart-fbf43b2d-0d5a-4214-9279-8f02315e571d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911920925 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.3911920925
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.87133979
Short name T333
Test name
Test status
Simulation time 398739853852 ps
CPU time 222.44 seconds
Started Jun 09 12:53:06 PM PDT 24
Finished Jun 09 12:56:49 PM PDT 24
Peak memory 182988 kb
Host smart-ff029778-71c2-470e-bd0e-7f02298f1ddc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87133979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.rv_timer_cfg_update_on_fly.87133979
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1872015371
Short name T43
Test name
Test status
Simulation time 109588726062 ps
CPU time 168.18 seconds
Started Jun 09 12:53:05 PM PDT 24
Finished Jun 09 12:55:53 PM PDT 24
Peak memory 182920 kb
Host smart-36866f1d-cb4d-4dae-8233-2eaa7c4df630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872015371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1872015371
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.71592504
Short name T398
Test name
Test status
Simulation time 43469757268 ps
CPU time 141.63 seconds
Started Jun 09 12:53:05 PM PDT 24
Finished Jun 09 12:55:27 PM PDT 24
Peak memory 183004 kb
Host smart-e18d7f25-0470-4bf6-8995-1f14c7d2a594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71592504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.71592504
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1240502193
Short name T198
Test name
Test status
Simulation time 424215921036 ps
CPU time 1313.88 seconds
Started Jun 09 12:53:12 PM PDT 24
Finished Jun 09 01:15:06 PM PDT 24
Peak memory 196216 kb
Host smart-101cba06-af55-4698-8485-6f7464c03a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240502193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1240502193
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1080944714
Short name T294
Test name
Test status
Simulation time 217688785113 ps
CPU time 82.1 seconds
Started Jun 09 12:53:12 PM PDT 24
Finished Jun 09 12:54:34 PM PDT 24
Peak memory 183000 kb
Host smart-eefa20e4-6de4-474a-a90b-2e4fce056376
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080944714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1080944714
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2374111685
Short name T369
Test name
Test status
Simulation time 157546127463 ps
CPU time 236.63 seconds
Started Jun 09 12:53:11 PM PDT 24
Finished Jun 09 12:57:08 PM PDT 24
Peak memory 182956 kb
Host smart-543afe43-a5b5-4876-b97e-d66fb0135a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374111685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2374111685
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2229675588
Short name T420
Test name
Test status
Simulation time 25540624385 ps
CPU time 798.91 seconds
Started Jun 09 12:53:12 PM PDT 24
Finished Jun 09 01:06:31 PM PDT 24
Peak memory 182984 kb
Host smart-7766aac9-f780-4b52-a534-e9ee5c5f835a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229675588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2229675588
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.547861636
Short name T175
Test name
Test status
Simulation time 111092731370 ps
CPU time 55.05 seconds
Started Jun 09 12:53:11 PM PDT 24
Finished Jun 09 12:54:06 PM PDT 24
Peak memory 191168 kb
Host smart-a7930a2d-60c3-4341-adfe-7476803526a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547861636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.547861636
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3471319546
Short name T254
Test name
Test status
Simulation time 75409735985 ps
CPU time 128.51 seconds
Started Jun 09 12:53:17 PM PDT 24
Finished Jun 09 12:55:25 PM PDT 24
Peak memory 183000 kb
Host smart-e096a029-39bc-4689-97ba-697681c6df52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471319546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3471319546
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2354225039
Short name T392
Test name
Test status
Simulation time 118819457413 ps
CPU time 49.14 seconds
Started Jun 09 12:53:15 PM PDT 24
Finished Jun 09 12:54:04 PM PDT 24
Peak memory 183232 kb
Host smart-d9044824-817c-42e5-ad39-877c8efc81cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354225039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2354225039
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1422575610
Short name T212
Test name
Test status
Simulation time 648963465993 ps
CPU time 427.44 seconds
Started Jun 09 12:53:16 PM PDT 24
Finished Jun 09 01:00:23 PM PDT 24
Peak memory 191208 kb
Host smart-e83bf31e-d031-4f42-baaf-e12227f3fd7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422575610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1422575610
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2987319367
Short name T188
Test name
Test status
Simulation time 103854321748 ps
CPU time 49.85 seconds
Started Jun 09 12:53:16 PM PDT 24
Finished Jun 09 12:54:06 PM PDT 24
Peak memory 193416 kb
Host smart-36178adf-ea56-47b7-86f4-445843df88d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987319367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2987319367
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.639130538
Short name T160
Test name
Test status
Simulation time 448121567578 ps
CPU time 214.83 seconds
Started Jun 09 12:53:16 PM PDT 24
Finished Jun 09 12:56:51 PM PDT 24
Peak memory 182980 kb
Host smart-f7d0fe5a-f79c-4d4f-bad0-c599bf80d126
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639130538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.639130538
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.270045207
Short name T361
Test name
Test status
Simulation time 406461454129 ps
CPU time 151.46 seconds
Started Jun 09 12:53:23 PM PDT 24
Finished Jun 09 12:55:55 PM PDT 24
Peak memory 182988 kb
Host smart-ddc8b711-30fb-4aae-b41f-d61da32005df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270045207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.270045207
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.4277233273
Short name T232
Test name
Test status
Simulation time 71368243931 ps
CPU time 126.33 seconds
Started Jun 09 12:53:22 PM PDT 24
Finished Jun 09 12:55:29 PM PDT 24
Peak memory 182620 kb
Host smart-c3afd097-efbc-457e-b382-4a61fd1921ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277233273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4277233273
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3079721659
Short name T187
Test name
Test status
Simulation time 361912692394 ps
CPU time 625.84 seconds
Started Jun 09 12:53:26 PM PDT 24
Finished Jun 09 01:03:52 PM PDT 24
Peak memory 183012 kb
Host smart-4f72ec64-a434-4be1-bc06-7b26a7ded368
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079721659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3079721659
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1594877409
Short name T370
Test name
Test status
Simulation time 156035297352 ps
CPU time 68.01 seconds
Started Jun 09 12:53:24 PM PDT 24
Finished Jun 09 12:54:32 PM PDT 24
Peak memory 182996 kb
Host smart-b414e1ae-ea83-45b3-994c-8a533788b9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594877409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1594877409
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.4214341865
Short name T180
Test name
Test status
Simulation time 149706650295 ps
CPU time 409.95 seconds
Started Jun 09 12:53:21 PM PDT 24
Finished Jun 09 01:00:11 PM PDT 24
Peak memory 191220 kb
Host smart-5aacef5d-7e42-4f04-8060-191f3bc2d86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214341865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4214341865
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.495092688
Short name T282
Test name
Test status
Simulation time 19739246905 ps
CPU time 38.84 seconds
Started Jun 09 12:53:21 PM PDT 24
Finished Jun 09 12:54:00 PM PDT 24
Peak memory 191180 kb
Host smart-52809e0c-5d24-4e38-922a-364ada9cb74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495092688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.495092688
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2533335961
Short name T66
Test name
Test status
Simulation time 137688910125 ps
CPU time 227.86 seconds
Started Jun 09 12:53:21 PM PDT 24
Finished Jun 09 12:57:09 PM PDT 24
Peak memory 182984 kb
Host smart-6e49f103-8310-4ec2-8d6f-bcf21bf97112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533335961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2533335961
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1447758949
Short name T202
Test name
Test status
Simulation time 340171648093 ps
CPU time 157.41 seconds
Started Jun 09 12:53:28 PM PDT 24
Finished Jun 09 12:56:05 PM PDT 24
Peak memory 194360 kb
Host smart-7f801482-3258-4ca4-9d52-39a81a04caca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447758949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1447758949
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1129589084
Short name T325
Test name
Test status
Simulation time 821783543500 ps
CPU time 462.37 seconds
Started Jun 09 12:53:28 PM PDT 24
Finished Jun 09 01:01:11 PM PDT 24
Peak memory 183004 kb
Host smart-975e469a-bbdd-4e32-989b-4cd24a4bdcbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129589084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1129589084
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2133416080
Short name T444
Test name
Test status
Simulation time 12812172940 ps
CPU time 19.86 seconds
Started Jun 09 12:53:28 PM PDT 24
Finished Jun 09 12:53:48 PM PDT 24
Peak memory 182992 kb
Host smart-2c365877-151b-4181-9470-da80a7de24ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133416080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2133416080
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2383773023
Short name T415
Test name
Test status
Simulation time 96208714063 ps
CPU time 92.27 seconds
Started Jun 09 12:53:29 PM PDT 24
Finished Jun 09 12:55:02 PM PDT 24
Peak memory 191208 kb
Host smart-b5a2badb-2ff7-4805-9984-d1daea2ded54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383773023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2383773023
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2628723883
Short name T445
Test name
Test status
Simulation time 818194775567 ps
CPU time 429.26 seconds
Started Jun 09 12:53:33 PM PDT 24
Finished Jun 09 01:00:43 PM PDT 24
Peak memory 182948 kb
Host smart-a2f493f8-648a-495f-a827-f6cc72e74000
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628723883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2628723883
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1297540590
Short name T379
Test name
Test status
Simulation time 24409225725 ps
CPU time 37.88 seconds
Started Jun 09 12:53:34 PM PDT 24
Finished Jun 09 12:54:12 PM PDT 24
Peak memory 182968 kb
Host smart-57cb9557-f821-4e61-b2e0-96bc39be67ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297540590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1297540590
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1254848085
Short name T344
Test name
Test status
Simulation time 230042358311 ps
CPU time 555.06 seconds
Started Jun 09 12:53:34 PM PDT 24
Finished Jun 09 01:02:50 PM PDT 24
Peak memory 191200 kb
Host smart-b6d892b7-4121-4a57-8b37-2d97db9d4a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254848085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1254848085
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2052544022
Short name T341
Test name
Test status
Simulation time 64281460238 ps
CPU time 94.52 seconds
Started Jun 09 12:53:33 PM PDT 24
Finished Jun 09 12:55:08 PM PDT 24
Peak memory 183112 kb
Host smart-08f28354-c0ec-4e16-9d58-1222254fa775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052544022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2052544022
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.3191282688
Short name T34
Test name
Test status
Simulation time 43658705407 ps
CPU time 160.58 seconds
Started Jun 09 12:53:35 PM PDT 24
Finished Jun 09 12:56:15 PM PDT 24
Peak memory 197656 kb
Host smart-4a2052eb-b039-4ee0-bf1e-94a5279026d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191282688 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.3191282688
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.501660606
Short name T74
Test name
Test status
Simulation time 234190789328 ps
CPU time 236.47 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 12:55:33 PM PDT 24
Peak memory 182984 kb
Host smart-3533f43f-7740-4c39-89af-ff7b5845d8cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501660606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.501660606
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1132253417
Short name T69
Test name
Test status
Simulation time 45044037032 ps
CPU time 74.48 seconds
Started Jun 09 12:51:34 PM PDT 24
Finished Jun 09 12:52:49 PM PDT 24
Peak memory 182992 kb
Host smart-98e22b05-460e-4fe0-aaf1-6092f8a26fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132253417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1132253417
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1901339077
Short name T239
Test name
Test status
Simulation time 39323274687 ps
CPU time 67.27 seconds
Started Jun 09 12:51:34 PM PDT 24
Finished Jun 09 12:52:41 PM PDT 24
Peak memory 191200 kb
Host smart-0b5d3742-0a8f-47be-98b5-a6085d9f7aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901339077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1901339077
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3228514473
Short name T253
Test name
Test status
Simulation time 265427174955 ps
CPU time 128.89 seconds
Started Jun 09 12:51:35 PM PDT 24
Finished Jun 09 12:53:44 PM PDT 24
Peak memory 191152 kb
Host smart-de054c84-c514-42d4-9651-f77aca973d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228514473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3228514473
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.917634973
Short name T79
Test name
Test status
Simulation time 239316849000 ps
CPU time 576.91 seconds
Started Jun 09 12:53:34 PM PDT 24
Finished Jun 09 01:03:11 PM PDT 24
Peak memory 191192 kb
Host smart-5be66125-93ae-4631-8375-ad9b756693e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917634973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.917634973
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2596200663
Short name T153
Test name
Test status
Simulation time 400349137626 ps
CPU time 1486.78 seconds
Started Jun 09 12:53:33 PM PDT 24
Finished Jun 09 01:18:20 PM PDT 24
Peak memory 191192 kb
Host smart-a7ebf3eb-68a4-4ca3-b34a-7c72dae27e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596200663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2596200663
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4232076668
Short name T124
Test name
Test status
Simulation time 2387474708738 ps
CPU time 1586.4 seconds
Started Jun 09 12:53:34 PM PDT 24
Finished Jun 09 01:20:01 PM PDT 24
Peak memory 193524 kb
Host smart-d6f103d8-40b8-4565-9cda-4896a8127435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232076668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4232076668
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.216191300
Short name T142
Test name
Test status
Simulation time 306267324236 ps
CPU time 1570.07 seconds
Started Jun 09 12:53:32 PM PDT 24
Finished Jun 09 01:19:43 PM PDT 24
Peak memory 191208 kb
Host smart-df3d2ab7-7377-49c6-b5e3-96fc0b7eaa24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216191300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.216191300
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1710063625
Short name T430
Test name
Test status
Simulation time 53962156757 ps
CPU time 179.36 seconds
Started Jun 09 12:53:38 PM PDT 24
Finished Jun 09 12:56:37 PM PDT 24
Peak memory 191216 kb
Host smart-1585951e-30f0-43c4-8272-3e8517b707bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710063625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1710063625
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3532348419
Short name T432
Test name
Test status
Simulation time 97469738053 ps
CPU time 207.97 seconds
Started Jun 09 12:53:39 PM PDT 24
Finished Jun 09 12:57:07 PM PDT 24
Peak memory 191220 kb
Host smart-53ea1ad6-01fc-426d-9e48-d6c0fd1429a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532348419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3532348419
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.366202367
Short name T355
Test name
Test status
Simulation time 14443734765 ps
CPU time 14.32 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 12:51:51 PM PDT 24
Peak memory 182884 kb
Host smart-ed8f30f1-ab57-430c-afbd-11a6af1817f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366202367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.366202367
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random.2450836136
Short name T326
Test name
Test status
Simulation time 219951052763 ps
CPU time 433.72 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 12:58:50 PM PDT 24
Peak memory 191208 kb
Host smart-fe565ae5-631c-49a0-81ea-228b3ed41a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450836136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2450836136
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.878087189
Short name T351
Test name
Test status
Simulation time 123908157935 ps
CPU time 308.18 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 12:56:45 PM PDT 24
Peak memory 191172 kb
Host smart-40dad2db-f644-4a1d-853d-3ced397cdffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878087189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.878087189
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.908507160
Short name T126
Test name
Test status
Simulation time 105946941904 ps
CPU time 244.29 seconds
Started Jun 09 12:51:33 PM PDT 24
Finished Jun 09 12:55:38 PM PDT 24
Peak memory 191196 kb
Host smart-ec860e48-016b-4d7d-b39f-39cd807d83d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908507160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.908507160
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.431065742
Short name T323
Test name
Test status
Simulation time 238320347644 ps
CPU time 119.21 seconds
Started Jun 09 12:53:44 PM PDT 24
Finished Jun 09 12:55:43 PM PDT 24
Peak memory 191212 kb
Host smart-b26a2776-44c8-4539-a47e-08394aeb9998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431065742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.431065742
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2910145611
Short name T182
Test name
Test status
Simulation time 34535050801 ps
CPU time 116.07 seconds
Started Jun 09 12:53:44 PM PDT 24
Finished Jun 09 12:55:40 PM PDT 24
Peak memory 191188 kb
Host smart-3dd56c0b-933f-4a97-b4bc-b7db7e1d95d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910145611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2910145611
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.237540408
Short name T256
Test name
Test status
Simulation time 808555508299 ps
CPU time 296.85 seconds
Started Jun 09 12:53:44 PM PDT 24
Finished Jun 09 12:58:41 PM PDT 24
Peak memory 191196 kb
Host smart-90f0e9aa-9578-47c2-b64b-b395be556c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237540408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.237540408
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.611483945
Short name T162
Test name
Test status
Simulation time 216075047797 ps
CPU time 215.15 seconds
Started Jun 09 12:53:43 PM PDT 24
Finished Jun 09 12:57:19 PM PDT 24
Peak memory 191208 kb
Host smart-0c47af6d-c646-4d6c-a221-50ad793745ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611483945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.611483945
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1654261253
Short name T411
Test name
Test status
Simulation time 13691354307 ps
CPU time 7.44 seconds
Started Jun 09 12:53:44 PM PDT 24
Finished Jun 09 12:53:52 PM PDT 24
Peak memory 182980 kb
Host smart-d0f463e3-d862-40a3-bd89-be64f7829be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654261253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1654261253
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1207876156
Short name T237
Test name
Test status
Simulation time 130708626169 ps
CPU time 110.26 seconds
Started Jun 09 12:53:45 PM PDT 24
Finished Jun 09 12:55:36 PM PDT 24
Peak memory 191204 kb
Host smart-be68c7b5-223c-4fcd-8a02-5faa1152789a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207876156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1207876156
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1106135763
Short name T279
Test name
Test status
Simulation time 96580403069 ps
CPU time 173.48 seconds
Started Jun 09 12:53:43 PM PDT 24
Finished Jun 09 12:56:37 PM PDT 24
Peak memory 191444 kb
Host smart-066d103a-5b9f-427d-b808-4e758ea577ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106135763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1106135763
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1869765344
Short name T159
Test name
Test status
Simulation time 290284119992 ps
CPU time 2095.43 seconds
Started Jun 09 12:53:44 PM PDT 24
Finished Jun 09 01:28:40 PM PDT 24
Peak memory 191216 kb
Host smart-ffb0617c-40e2-48d5-bd17-05febc9faf6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869765344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1869765344
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1515935694
Short name T75
Test name
Test status
Simulation time 349098232723 ps
CPU time 320.8 seconds
Started Jun 09 12:51:34 PM PDT 24
Finished Jun 09 12:56:55 PM PDT 24
Peak memory 182984 kb
Host smart-6a31a9d8-1edb-4163-b7e2-a4d3d08f6839
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515935694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1515935694
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3451401
Short name T378
Test name
Test status
Simulation time 442125885085 ps
CPU time 191.54 seconds
Started Jun 09 12:51:37 PM PDT 24
Finished Jun 09 12:54:49 PM PDT 24
Peak memory 182976 kb
Host smart-df45b1e6-5f49-4f58-ba88-f8bb59df82ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3451401
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1319883108
Short name T164
Test name
Test status
Simulation time 151304799856 ps
CPU time 582.91 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 01:01:20 PM PDT 24
Peak memory 194696 kb
Host smart-3223f8e3-fa9c-446d-98da-b4ce6f23ee37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319883108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1319883108
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.170914615
Short name T418
Test name
Test status
Simulation time 14520820 ps
CPU time 0.52 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 12:51:37 PM PDT 24
Peak memory 182800 kb
Host smart-ebf5f95f-68cb-48be-b6c5-f62f50da3bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170914615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.170914615
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2656783869
Short name T376
Test name
Test status
Simulation time 2445530929 ps
CPU time 3.53 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 12:51:40 PM PDT 24
Peak memory 182788 kb
Host smart-a6dfd200-0018-46e5-97c8-fef9b88ef7b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656783869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2656783869
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.4223956563
Short name T178
Test name
Test status
Simulation time 523869329502 ps
CPU time 1061.54 seconds
Started Jun 09 12:53:53 PM PDT 24
Finished Jun 09 01:11:35 PM PDT 24
Peak memory 191192 kb
Host smart-5e01deea-0212-44e9-8d20-d0bafc2834fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223956563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4223956563
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3414179571
Short name T209
Test name
Test status
Simulation time 28205580003 ps
CPU time 83.43 seconds
Started Jun 09 12:53:52 PM PDT 24
Finished Jun 09 12:55:16 PM PDT 24
Peak memory 191204 kb
Host smart-a73a9b98-397c-452b-94e4-5db526baca74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414179571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3414179571
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3802629545
Short name T297
Test name
Test status
Simulation time 173435146297 ps
CPU time 78.4 seconds
Started Jun 09 12:53:51 PM PDT 24
Finished Jun 09 12:55:10 PM PDT 24
Peak memory 191216 kb
Host smart-b04c54ed-e184-467e-855d-8516e73d0b11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802629545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3802629545
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3909400133
Short name T327
Test name
Test status
Simulation time 230203730210 ps
CPU time 17.64 seconds
Started Jun 09 12:53:52 PM PDT 24
Finished Jun 09 12:54:10 PM PDT 24
Peak memory 182992 kb
Host smart-ffe9099c-16f1-4918-a0d7-86924c2d2faf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909400133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3909400133
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.733338326
Short name T251
Test name
Test status
Simulation time 465862233312 ps
CPU time 215.49 seconds
Started Jun 09 12:53:50 PM PDT 24
Finished Jun 09 12:57:26 PM PDT 24
Peak memory 191212 kb
Host smart-6d48af5c-71f7-4c73-9617-8c9bfbcccb69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733338326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.733338326
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.655066773
Short name T265
Test name
Test status
Simulation time 52188507043 ps
CPU time 104.37 seconds
Started Jun 09 12:53:58 PM PDT 24
Finished Jun 09 12:55:43 PM PDT 24
Peak memory 191196 kb
Host smart-d926679c-d33b-4bbf-b2b6-ff026a069ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655066773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.655066773
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3453046937
Short name T258
Test name
Test status
Simulation time 62851152902 ps
CPU time 81.58 seconds
Started Jun 09 12:53:59 PM PDT 24
Finished Jun 09 12:55:21 PM PDT 24
Peak memory 183000 kb
Host smart-ec50d799-96b2-441f-8fa5-f08755a34824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453046937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3453046937
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.679104154
Short name T144
Test name
Test status
Simulation time 357058869119 ps
CPU time 744.82 seconds
Started Jun 09 12:53:59 PM PDT 24
Finished Jun 09 01:06:24 PM PDT 24
Peak memory 191412 kb
Host smart-f8149744-d2a3-460f-88d8-fab29d5c1456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679104154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.679104154
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.318618726
Short name T130
Test name
Test status
Simulation time 556243301717 ps
CPU time 303.89 seconds
Started Jun 09 12:53:58 PM PDT 24
Finished Jun 09 12:59:02 PM PDT 24
Peak memory 191216 kb
Host smart-4ea19c87-76a2-42fe-a528-cd9d18db246b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318618726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.318618726
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1994365189
Short name T189
Test name
Test status
Simulation time 289576539207 ps
CPU time 297.28 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 12:56:34 PM PDT 24
Peak memory 182992 kb
Host smart-f2b57110-461c-4449-9972-0586933d61ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994365189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1994365189
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2186898790
Short name T8
Test name
Test status
Simulation time 530963054415 ps
CPU time 242.24 seconds
Started Jun 09 12:51:35 PM PDT 24
Finished Jun 09 12:55:38 PM PDT 24
Peak memory 182968 kb
Host smart-0f218880-200e-4902-b279-97d0bb887644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186898790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2186898790
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2429748555
Short name T176
Test name
Test status
Simulation time 134805315805 ps
CPU time 513.56 seconds
Started Jun 09 12:51:35 PM PDT 24
Finished Jun 09 01:00:09 PM PDT 24
Peak memory 191128 kb
Host smart-87a1e4e3-9f7a-461f-8462-24af3f7ae9d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429748555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2429748555
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2434848202
Short name T349
Test name
Test status
Simulation time 17528523521 ps
CPU time 69.32 seconds
Started Jun 09 12:51:36 PM PDT 24
Finished Jun 09 12:52:45 PM PDT 24
Peak memory 191184 kb
Host smart-130b4770-1577-44ba-968d-1c61c8878bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434848202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2434848202
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1793268800
Short name T448
Test name
Test status
Simulation time 35539882390 ps
CPU time 151.55 seconds
Started Jun 09 12:51:39 PM PDT 24
Finished Jun 09 12:54:11 PM PDT 24
Peak memory 197652 kb
Host smart-47442ee8-5c8f-4048-9647-d82e846bb831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793268800 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1793268800
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1344828130
Short name T266
Test name
Test status
Simulation time 34298009328 ps
CPU time 61.41 seconds
Started Jun 09 12:53:58 PM PDT 24
Finished Jun 09 12:55:00 PM PDT 24
Peak memory 182992 kb
Host smart-e49b00dc-457f-460b-bfdd-9d43f0230a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344828130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1344828130
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.930047491
Short name T152
Test name
Test status
Simulation time 199166364469 ps
CPU time 194.53 seconds
Started Jun 09 12:53:59 PM PDT 24
Finished Jun 09 12:57:13 PM PDT 24
Peak memory 195272 kb
Host smart-79ee4b13-74d4-4eff-8f50-552191852f3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930047491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.930047491
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.4189574143
Short name T20
Test name
Test status
Simulation time 92400587178 ps
CPU time 1779.09 seconds
Started Jun 09 12:53:57 PM PDT 24
Finished Jun 09 01:23:36 PM PDT 24
Peak memory 191200 kb
Host smart-20c95b14-169b-442d-bb5c-5a9dc32c044a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189574143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.4189574143
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1189140643
Short name T283
Test name
Test status
Simulation time 227053769356 ps
CPU time 887.98 seconds
Started Jun 09 12:53:59 PM PDT 24
Finished Jun 09 01:08:47 PM PDT 24
Peak memory 191212 kb
Host smart-316b7d00-e4eb-472e-b260-23bbf931d47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189140643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1189140643
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1322739542
Short name T200
Test name
Test status
Simulation time 82034259444 ps
CPU time 123.14 seconds
Started Jun 09 12:53:59 PM PDT 24
Finished Jun 09 12:56:02 PM PDT 24
Peak memory 182908 kb
Host smart-44a76a04-b47b-440e-8b3b-0a2a92dcbd97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322739542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1322739542
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3748906140
Short name T291
Test name
Test status
Simulation time 13194210357 ps
CPU time 18.28 seconds
Started Jun 09 12:54:04 PM PDT 24
Finished Jun 09 12:54:22 PM PDT 24
Peak memory 183016 kb
Host smart-529dbc4a-2414-448f-b472-568172962c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748906140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3748906140
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3923575809
Short name T127
Test name
Test status
Simulation time 581985070480 ps
CPU time 287.76 seconds
Started Jun 09 12:54:01 PM PDT 24
Finished Jun 09 12:58:49 PM PDT 24
Peak memory 191136 kb
Host smart-883e358d-b68a-4ac5-b53a-ed18b01f89ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923575809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3923575809
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1588562173
Short name T385
Test name
Test status
Simulation time 180846691834 ps
CPU time 285.78 seconds
Started Jun 09 12:54:00 PM PDT 24
Finished Jun 09 12:58:46 PM PDT 24
Peak memory 191128 kb
Host smart-6f5e6f26-eaf8-432b-88f8-adc76f963e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588562173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1588562173
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1607131679
Short name T386
Test name
Test status
Simulation time 335897657901 ps
CPU time 566.59 seconds
Started Jun 09 12:54:05 PM PDT 24
Finished Jun 09 01:03:32 PM PDT 24
Peak memory 191208 kb
Host smart-be09a0e0-2f73-4a91-8a1b-b0afb4ed795f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607131679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1607131679
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3102315291
Short name T78
Test name
Test status
Simulation time 409012992355 ps
CPU time 347.55 seconds
Started Jun 09 12:51:42 PM PDT 24
Finished Jun 09 12:57:30 PM PDT 24
Peak memory 182980 kb
Host smart-ed9fedc4-f9d4-43aa-a96e-311a01d41d17
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102315291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3102315291
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1152665827
Short name T71
Test name
Test status
Simulation time 206971818730 ps
CPU time 81.43 seconds
Started Jun 09 12:51:39 PM PDT 24
Finished Jun 09 12:53:00 PM PDT 24
Peak memory 182996 kb
Host smart-29493d7a-5a42-47ce-aa06-419c3053c738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152665827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1152665827
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.735985125
Short name T417
Test name
Test status
Simulation time 108881929138 ps
CPU time 427.19 seconds
Started Jun 09 12:51:38 PM PDT 24
Finished Jun 09 12:58:46 PM PDT 24
Peak memory 191180 kb
Host smart-e2cadde3-626b-4f01-9b2c-1c37e78a50e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735985125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.735985125
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1019870432
Short name T216
Test name
Test status
Simulation time 12978525080 ps
CPU time 7.92 seconds
Started Jun 09 12:51:40 PM PDT 24
Finished Jun 09 12:51:48 PM PDT 24
Peak memory 191176 kb
Host smart-ba0eb5f1-d6f4-43c2-9bce-115d7a2417a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019870432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1019870432
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1750558064
Short name T58
Test name
Test status
Simulation time 836673529968 ps
CPU time 1372.98 seconds
Started Jun 09 12:51:40 PM PDT 24
Finished Jun 09 01:14:33 PM PDT 24
Peak memory 191156 kb
Host smart-0c6bf18d-5634-4175-81e5-d88de06f3abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750558064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1750558064
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.2718686852
Short name T220
Test name
Test status
Simulation time 24118323712 ps
CPU time 22.29 seconds
Started Jun 09 12:54:02 PM PDT 24
Finished Jun 09 12:54:25 PM PDT 24
Peak memory 183216 kb
Host smart-5353cf35-cc04-4c46-ae27-085ad8c6272e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718686852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2718686852
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.772370693
Short name T236
Test name
Test status
Simulation time 491989340333 ps
CPU time 126.92 seconds
Started Jun 09 12:54:09 PM PDT 24
Finished Jun 09 12:56:16 PM PDT 24
Peak memory 191212 kb
Host smart-921cee22-5f63-460d-b09c-18c7abde9330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772370693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.772370693
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2860308899
Short name T186
Test name
Test status
Simulation time 187472426295 ps
CPU time 172.71 seconds
Started Jun 09 12:54:08 PM PDT 24
Finished Jun 09 12:57:01 PM PDT 24
Peak memory 191208 kb
Host smart-a5cd96e6-4325-4eaa-959d-d81906768a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860308899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2860308899
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4166130183
Short name T348
Test name
Test status
Simulation time 14076167326 ps
CPU time 20.65 seconds
Started Jun 09 12:54:03 PM PDT 24
Finished Jun 09 12:54:24 PM PDT 24
Peak memory 183000 kb
Host smart-c0c14643-f601-4efd-a706-ccffe194e36a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166130183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4166130183
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3242855856
Short name T284
Test name
Test status
Simulation time 1151131867233 ps
CPU time 510.16 seconds
Started Jun 09 12:54:04 PM PDT 24
Finished Jun 09 01:02:35 PM PDT 24
Peak memory 191192 kb
Host smart-de9ee633-2a75-4da0-a590-e6ca6c6a752a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242855856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3242855856
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.479272210
Short name T70
Test name
Test status
Simulation time 283121837391 ps
CPU time 303.12 seconds
Started Jun 09 12:54:03 PM PDT 24
Finished Jun 09 12:59:07 PM PDT 24
Peak memory 191196 kb
Host smart-7e8d3f51-00e6-4c9e-8f27-8c01ea19ea2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479272210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.479272210
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3408868495
Short name T287
Test name
Test status
Simulation time 321091711144 ps
CPU time 554.54 seconds
Started Jun 09 12:54:08 PM PDT 24
Finished Jun 09 01:03:23 PM PDT 24
Peak memory 191216 kb
Host smart-f8610890-1452-49b1-8c0b-5f597db0cd23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408868495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3408868495
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3037888947
Short name T312
Test name
Test status
Simulation time 174510086462 ps
CPU time 322.17 seconds
Started Jun 09 12:54:07 PM PDT 24
Finished Jun 09 12:59:30 PM PDT 24
Peak memory 191208 kb
Host smart-0f414aff-854c-4a87-afcd-9bf3a29679ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037888947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3037888947
Directory /workspace/99.rv_timer_random/latest
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