Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 584
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1479716915 Jun 10 06:23:12 PM PDT 24 Jun 10 06:23:13 PM PDT 24 24846730 ps
T512 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2367247290 Jun 10 06:22:48 PM PDT 24 Jun 10 06:22:49 PM PDT 24 19374142 ps
T513 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4218988553 Jun 10 06:22:42 PM PDT 24 Jun 10 06:22:43 PM PDT 24 13790222 ps
T514 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3722000014 Jun 10 06:22:52 PM PDT 24 Jun 10 06:22:54 PM PDT 24 31945269 ps
T515 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1069209581 Jun 10 06:21:50 PM PDT 24 Jun 10 06:21:51 PM PDT 24 416949229 ps
T516 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3079900167 Jun 10 06:22:26 PM PDT 24 Jun 10 06:22:27 PM PDT 24 14156642 ps
T517 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3931889313 Jun 10 06:22:33 PM PDT 24 Jun 10 06:22:34 PM PDT 24 140827712 ps
T518 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.418872835 Jun 10 06:23:16 PM PDT 24 Jun 10 06:23:17 PM PDT 24 12643294 ps
T519 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3707860500 Jun 10 06:22:52 PM PDT 24 Jun 10 06:22:54 PM PDT 24 1120919649 ps
T520 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.61959980 Jun 10 06:22:22 PM PDT 24 Jun 10 06:22:23 PM PDT 24 31068798 ps
T93 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3269576880 Jun 10 06:22:34 PM PDT 24 Jun 10 06:22:35 PM PDT 24 32697631 ps
T521 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1913949588 Jun 10 06:22:23 PM PDT 24 Jun 10 06:22:24 PM PDT 24 378708531 ps
T522 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2948127372 Jun 10 06:23:00 PM PDT 24 Jun 10 06:23:01 PM PDT 24 13576170 ps
T523 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3296533037 Jun 10 06:22:03 PM PDT 24 Jun 10 06:22:04 PM PDT 24 26679633 ps
T524 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2287206928 Jun 10 06:23:13 PM PDT 24 Jun 10 06:23:13 PM PDT 24 38491695 ps
T525 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2649476647 Jun 10 06:22:30 PM PDT 24 Jun 10 06:22:31 PM PDT 24 150877312 ps
T526 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3073372480 Jun 10 06:23:07 PM PDT 24 Jun 10 06:23:08 PM PDT 24 54912822 ps
T94 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3634836885 Jun 10 06:22:01 PM PDT 24 Jun 10 06:22:02 PM PDT 24 21321955 ps
T527 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.283442038 Jun 10 06:22:57 PM PDT 24 Jun 10 06:22:59 PM PDT 24 20568584 ps
T528 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.480214832 Jun 10 06:22:06 PM PDT 24 Jun 10 06:22:07 PM PDT 24 54423650 ps
T95 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2083280347 Jun 10 06:22:45 PM PDT 24 Jun 10 06:22:46 PM PDT 24 92029897 ps
T529 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3264598453 Jun 10 06:22:00 PM PDT 24 Jun 10 06:22:01 PM PDT 24 18305128 ps
T530 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1095198509 Jun 10 06:22:07 PM PDT 24 Jun 10 06:22:08 PM PDT 24 74863669 ps
T531 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1564597492 Jun 10 06:23:12 PM PDT 24 Jun 10 06:23:13 PM PDT 24 65733036 ps
T532 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2272706273 Jun 10 06:22:52 PM PDT 24 Jun 10 06:22:53 PM PDT 24 28930934 ps
T533 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3775781643 Jun 10 06:22:19 PM PDT 24 Jun 10 06:22:20 PM PDT 24 16333570 ps
T534 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2677497926 Jun 10 06:21:52 PM PDT 24 Jun 10 06:21:53 PM PDT 24 21834891 ps
T535 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.537890110 Jun 10 06:22:51 PM PDT 24 Jun 10 06:22:52 PM PDT 24 96805758 ps
T536 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.163667649 Jun 10 06:22:26 PM PDT 24 Jun 10 06:22:28 PM PDT 24 67699987 ps
T537 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4099178965 Jun 10 06:22:24 PM PDT 24 Jun 10 06:22:25 PM PDT 24 48928772 ps
T538 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4097681338 Jun 10 06:21:59 PM PDT 24 Jun 10 06:22:00 PM PDT 24 496676215 ps
T539 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4208111183 Jun 10 06:22:32 PM PDT 24 Jun 10 06:22:34 PM PDT 24 113772798 ps
T111 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1518169334 Jun 10 06:22:51 PM PDT 24 Jun 10 06:22:52 PM PDT 24 183823468 ps
T540 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2700066569 Jun 10 06:22:37 PM PDT 24 Jun 10 06:22:37 PM PDT 24 13593333 ps
T112 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1950460693 Jun 10 06:22:09 PM PDT 24 Jun 10 06:22:10 PM PDT 24 360005579 ps
T541 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3228190411 Jun 10 06:23:11 PM PDT 24 Jun 10 06:23:12 PM PDT 24 31943160 ps
T542 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2592345225 Jun 10 06:21:51 PM PDT 24 Jun 10 06:21:51 PM PDT 24 45222030 ps
T543 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2388672273 Jun 10 06:21:56 PM PDT 24 Jun 10 06:22:00 PM PDT 24 284149615 ps
T544 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.266251875 Jun 10 06:22:24 PM PDT 24 Jun 10 06:22:25 PM PDT 24 110167048 ps
T545 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3718785333 Jun 10 06:22:28 PM PDT 24 Jun 10 06:22:29 PM PDT 24 170145030 ps
T546 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2056355687 Jun 10 06:22:42 PM PDT 24 Jun 10 06:22:44 PM PDT 24 194053314 ps
T547 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.600859039 Jun 10 06:23:02 PM PDT 24 Jun 10 06:23:03 PM PDT 24 87076689 ps
T548 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3784107890 Jun 10 06:22:57 PM PDT 24 Jun 10 06:22:57 PM PDT 24 40462944 ps
T549 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1173078638 Jun 10 06:23:07 PM PDT 24 Jun 10 06:23:07 PM PDT 24 19582729 ps
T550 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3088072207 Jun 10 06:22:34 PM PDT 24 Jun 10 06:22:36 PM PDT 24 203152608 ps
T551 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2348310071 Jun 10 06:23:01 PM PDT 24 Jun 10 06:23:03 PM PDT 24 47733087 ps
T552 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3250721830 Jun 10 06:21:53 PM PDT 24 Jun 10 06:21:55 PM PDT 24 478615326 ps
T553 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3041135248 Jun 10 06:23:07 PM PDT 24 Jun 10 06:23:09 PM PDT 24 146630092 ps
T554 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2455094577 Jun 10 06:22:00 PM PDT 24 Jun 10 06:22:04 PM PDT 24 1513495443 ps
T555 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1644229447 Jun 10 06:22:29 PM PDT 24 Jun 10 06:22:30 PM PDT 24 27507998 ps
T96 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.398991724 Jun 10 06:22:39 PM PDT 24 Jun 10 06:22:39 PM PDT 24 35058515 ps
T556 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2354909703 Jun 10 06:23:01 PM PDT 24 Jun 10 06:23:03 PM PDT 24 113057911 ps
T557 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3467882705 Jun 10 06:22:20 PM PDT 24 Jun 10 06:22:21 PM PDT 24 30792936 ps
T558 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2379875263 Jun 10 06:22:44 PM PDT 24 Jun 10 06:22:45 PM PDT 24 50848830 ps
T559 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2601921505 Jun 10 06:23:15 PM PDT 24 Jun 10 06:23:16 PM PDT 24 12541301 ps
T560 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1415361577 Jun 10 06:23:16 PM PDT 24 Jun 10 06:23:17 PM PDT 24 23836545 ps
T561 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4011696076 Jun 10 06:23:03 PM PDT 24 Jun 10 06:23:05 PM PDT 24 130323489 ps
T562 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3764620677 Jun 10 06:23:09 PM PDT 24 Jun 10 06:23:10 PM PDT 24 16702410 ps
T563 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.209157598 Jun 10 06:22:37 PM PDT 24 Jun 10 06:22:38 PM PDT 24 21375254 ps
T564 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2578439263 Jun 10 06:22:38 PM PDT 24 Jun 10 06:22:39 PM PDT 24 29974398 ps
T565 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.622928911 Jun 10 06:23:05 PM PDT 24 Jun 10 06:23:06 PM PDT 24 48975344 ps
T566 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.980585536 Jun 10 06:22:43 PM PDT 24 Jun 10 06:22:45 PM PDT 24 287753211 ps
T567 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1545072844 Jun 10 06:22:18 PM PDT 24 Jun 10 06:22:19 PM PDT 24 53548947 ps
T97 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3573879457 Jun 10 06:22:27 PM PDT 24 Jun 10 06:22:28 PM PDT 24 12280359 ps
T568 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.776554885 Jun 10 06:22:38 PM PDT 24 Jun 10 06:22:39 PM PDT 24 103859523 ps
T569 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.262569977 Jun 10 06:22:44 PM PDT 24 Jun 10 06:22:46 PM PDT 24 31770989 ps
T570 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.383345618 Jun 10 06:22:33 PM PDT 24 Jun 10 06:22:33 PM PDT 24 59440977 ps
T571 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2463673477 Jun 10 06:22:38 PM PDT 24 Jun 10 06:22:39 PM PDT 24 370747868 ps
T572 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2260546675 Jun 10 06:22:44 PM PDT 24 Jun 10 06:22:47 PM PDT 24 1414445882 ps
T573 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3955696223 Jun 10 06:22:42 PM PDT 24 Jun 10 06:22:43 PM PDT 24 142262552 ps
T98 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3097367641 Jun 10 06:22:57 PM PDT 24 Jun 10 06:22:58 PM PDT 24 58916471 ps
T574 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.852124130 Jun 10 06:22:28 PM PDT 24 Jun 10 06:22:29 PM PDT 24 98737056 ps
T575 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.315992077 Jun 10 06:22:41 PM PDT 24 Jun 10 06:22:42 PM PDT 24 135873873 ps
T99 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4126111860 Jun 10 06:21:59 PM PDT 24 Jun 10 06:22:00 PM PDT 24 90475782 ps
T576 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.169396520 Jun 10 06:22:09 PM PDT 24 Jun 10 06:22:12 PM PDT 24 191843849 ps
T577 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2045363885 Jun 10 06:22:50 PM PDT 24 Jun 10 06:22:51 PM PDT 24 13832898 ps
T578 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2045552533 Jun 10 06:22:34 PM PDT 24 Jun 10 06:22:35 PM PDT 24 86868432 ps
T579 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.856756088 Jun 10 06:22:00 PM PDT 24 Jun 10 06:22:01 PM PDT 24 13045221 ps
T100 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.720915563 Jun 10 06:23:00 PM PDT 24 Jun 10 06:23:00 PM PDT 24 14115533 ps
T580 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1039978409 Jun 10 06:22:42 PM PDT 24 Jun 10 06:22:43 PM PDT 24 31207104 ps
T581 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.272507332 Jun 10 06:22:42 PM PDT 24 Jun 10 06:22:43 PM PDT 24 59860157 ps
T582 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2197613176 Jun 10 06:22:17 PM PDT 24 Jun 10 06:22:18 PM PDT 24 31554924 ps
T583 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.825619072 Jun 10 06:22:03 PM PDT 24 Jun 10 06:22:03 PM PDT 24 13415457 ps
T584 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.88191240 Jun 10 06:23:02 PM PDT 24 Jun 10 06:23:04 PM PDT 24 676023804 ps

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3765715470
Short name T2
Test name
Test status
Simulation time 154588214424 ps
CPU time 517.11 seconds
Started Jun 10 06:26:04 PM PDT 24
Finished Jun 10 06:34:42 PM PDT 24
Peak memory 205884 kb
Host smart-c4ad524f-0559-4e62-8674-77444683aa18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765715470 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3765715470
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1678132108
Short name T8
Test name
Test status
Simulation time 687721047176 ps
CPU time 1044.46 seconds
Started Jun 10 06:24:48 PM PDT 24
Finished Jun 10 06:42:13 PM PDT 24
Peak memory 191224 kb
Host smart-4c2e8646-7196-4efe-a885-d90266b35b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678132108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1678132108
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2825292672
Short name T29
Test name
Test status
Simulation time 459659160 ps
CPU time 1.4 seconds
Started Jun 10 06:22:43 PM PDT 24
Finished Jun 10 06:22:44 PM PDT 24
Peak memory 195400 kb
Host smart-3554eb96-2869-47b9-8771-ceab4a40b40d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825292672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2825292672
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.357593390
Short name T24
Test name
Test status
Simulation time 8831829988732 ps
CPU time 2883.45 seconds
Started Jun 10 06:23:37 PM PDT 24
Finished Jun 10 07:11:41 PM PDT 24
Peak memory 191192 kb
Host smart-5df64593-1a4d-4f48-8fb0-89efad2ef2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357593390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.357593390
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3620919141
Short name T120
Test name
Test status
Simulation time 516114736546 ps
CPU time 1856.57 seconds
Started Jun 10 06:25:07 PM PDT 24
Finished Jun 10 06:56:04 PM PDT 24
Peak memory 191236 kb
Host smart-abfe90cc-7184-45da-b022-da38a4826c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620919141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3620919141
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1122593144
Short name T56
Test name
Test status
Simulation time 348132112494 ps
CPU time 713.71 seconds
Started Jun 10 06:23:32 PM PDT 24
Finished Jun 10 06:35:26 PM PDT 24
Peak memory 196008 kb
Host smart-82932704-38c0-435d-8f2e-ac8e337b1976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122593144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1122593144
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3520982911
Short name T182
Test name
Test status
Simulation time 1188811782090 ps
CPU time 2282.22 seconds
Started Jun 10 06:26:29 PM PDT 24
Finished Jun 10 07:04:31 PM PDT 24
Peak memory 191208 kb
Host smart-9d1e385b-7329-4c09-9187-65840f9206ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520982911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3520982911
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1237273544
Short name T125
Test name
Test status
Simulation time 1117175242301 ps
CPU time 3754.09 seconds
Started Jun 10 06:26:08 PM PDT 24
Finished Jun 10 07:28:42 PM PDT 24
Peak memory 195784 kb
Host smart-5dc74afb-c03b-4ae7-a61e-866302437e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237273544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1237273544
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.629854005
Short name T54
Test name
Test status
Simulation time 4017501670779 ps
CPU time 1360.57 seconds
Started Jun 10 06:23:21 PM PDT 24
Finished Jun 10 06:46:02 PM PDT 24
Peak memory 191212 kb
Host smart-04c9af17-81bb-4803-9a41-ec3616e71a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629854005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.629854005
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1941254594
Short name T83
Test name
Test status
Simulation time 15666220 ps
CPU time 0.57 seconds
Started Jun 10 06:22:43 PM PDT 24
Finished Jun 10 06:22:44 PM PDT 24
Peak memory 182656 kb
Host smart-b0e5a23a-2da7-485b-b326-40ad6a0437c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941254594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1941254594
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.418125184
Short name T205
Test name
Test status
Simulation time 372196438761 ps
CPU time 929.47 seconds
Started Jun 10 06:24:02 PM PDT 24
Finished Jun 10 06:39:32 PM PDT 24
Peak memory 191260 kb
Host smart-6a63ac4d-9f56-4cef-979c-218193fd97b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418125184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
418125184
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/122.rv_timer_random.4057700417
Short name T127
Test name
Test status
Simulation time 512736750673 ps
CPU time 516.78 seconds
Started Jun 10 06:27:58 PM PDT 24
Finished Jun 10 06:36:35 PM PDT 24
Peak memory 194920 kb
Host smart-23a17083-06d9-4f93-ad1f-ff3034da87ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057700417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4057700417
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1368361904
Short name T220
Test name
Test status
Simulation time 919297793855 ps
CPU time 1584.26 seconds
Started Jun 10 06:23:30 PM PDT 24
Finished Jun 10 06:49:55 PM PDT 24
Peak memory 191260 kb
Host smart-c0585a91-066f-46f8-aa7e-38bfacdcbba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368361904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1368361904
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3053928912
Short name T201
Test name
Test status
Simulation time 718872938871 ps
CPU time 4028.02 seconds
Started Jun 10 06:24:20 PM PDT 24
Finished Jun 10 07:31:29 PM PDT 24
Peak memory 195592 kb
Host smart-cfa97774-2af5-423d-a61b-6ec3fa55f9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053928912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3053928912
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1802389024
Short name T16
Test name
Test status
Simulation time 190707210 ps
CPU time 0.84 seconds
Started Jun 10 06:23:19 PM PDT 24
Finished Jun 10 06:23:21 PM PDT 24
Peak memory 213556 kb
Host smart-7da15618-596e-452e-8c83-b58528f19502
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802389024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1802389024
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/105.rv_timer_random.1300536859
Short name T212
Test name
Test status
Simulation time 123724148606 ps
CPU time 202.66 seconds
Started Jun 10 06:27:34 PM PDT 24
Finished Jun 10 06:30:57 PM PDT 24
Peak memory 191276 kb
Host smart-c166aea6-2b2c-4ef3-8910-034cb925872c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300536859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1300536859
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2525963974
Short name T57
Test name
Test status
Simulation time 2852354001341 ps
CPU time 790.54 seconds
Started Jun 10 06:23:36 PM PDT 24
Finished Jun 10 06:36:47 PM PDT 24
Peak memory 191240 kb
Host smart-5dfcbef3-299d-449b-acad-f2ac9f108e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525963974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2525963974
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2154493644
Short name T61
Test name
Test status
Simulation time 966786807674 ps
CPU time 1214.13 seconds
Started Jun 10 06:25:27 PM PDT 24
Finished Jun 10 06:45:41 PM PDT 24
Peak memory 194452 kb
Host smart-bb617796-2579-4355-8c46-d80e87ffc78c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154493644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2154493644
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.257160320
Short name T192
Test name
Test status
Simulation time 2278629145907 ps
CPU time 1141.22 seconds
Started Jun 10 06:23:17 PM PDT 24
Finished Jun 10 06:42:19 PM PDT 24
Peak memory 191212 kb
Host smart-738eaba2-35f7-4398-ad1a-0f6e556b5cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257160320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.257160320
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3170296852
Short name T270
Test name
Test status
Simulation time 877179353752 ps
CPU time 1162.35 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:43:14 PM PDT 24
Peak memory 196016 kb
Host smart-1283cda2-d1dc-44d6-9c21-d1e014c6d53a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170296852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3170296852
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3522347000
Short name T240
Test name
Test status
Simulation time 431810672850 ps
CPU time 1297.06 seconds
Started Jun 10 06:24:37 PM PDT 24
Finished Jun 10 06:46:14 PM PDT 24
Peak memory 196368 kb
Host smart-032aa3f4-308c-4c6d-89a0-962dbf3e919f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522347000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3522347000
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.313728181
Short name T236
Test name
Test status
Simulation time 2244427339785 ps
CPU time 1363.93 seconds
Started Jun 10 06:25:22 PM PDT 24
Finished Jun 10 06:48:06 PM PDT 24
Peak memory 191276 kb
Host smart-c7a581c0-4837-4c06-b20c-81d407711190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313728181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
313728181
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3221483906
Short name T184
Test name
Test status
Simulation time 635110411872 ps
CPU time 1378.37 seconds
Started Jun 10 06:26:00 PM PDT 24
Finished Jun 10 06:48:59 PM PDT 24
Peak memory 191236 kb
Host smart-0ff6bda1-008e-4ac6-a4f9-82c129600a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221483906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3221483906
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2683448500
Short name T227
Test name
Test status
Simulation time 685730464469 ps
CPU time 1325.97 seconds
Started Jun 10 06:24:15 PM PDT 24
Finished Jun 10 06:46:22 PM PDT 24
Peak memory 191272 kb
Host smart-d1e2e5e0-ca13-452e-881e-a7215ae457a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683448500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2683448500
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1231829392
Short name T166
Test name
Test status
Simulation time 662331178780 ps
CPU time 800.36 seconds
Started Jun 10 06:26:35 PM PDT 24
Finished Jun 10 06:39:55 PM PDT 24
Peak memory 196024 kb
Host smart-62826bd3-0fb6-4e6e-9333-ece6af235905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231829392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1231829392
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.3067916321
Short name T189
Test name
Test status
Simulation time 458056706017 ps
CPU time 249.74 seconds
Started Jun 10 06:27:44 PM PDT 24
Finished Jun 10 06:31:54 PM PDT 24
Peak memory 191268 kb
Host smart-c1043898-432a-4918-be0f-ff6bfb29a589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067916321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3067916321
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.911630072
Short name T169
Test name
Test status
Simulation time 177947682766 ps
CPU time 360.86 seconds
Started Jun 10 06:28:55 PM PDT 24
Finished Jun 10 06:34:56 PM PDT 24
Peak memory 193876 kb
Host smart-f955194b-cedc-4da1-9960-4ab183e187ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911630072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.911630072
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1798837111
Short name T223
Test name
Test status
Simulation time 104576706282 ps
CPU time 456.45 seconds
Started Jun 10 06:27:33 PM PDT 24
Finished Jun 10 06:35:10 PM PDT 24
Peak memory 191276 kb
Host smart-da1f002c-f541-431d-9cac-88ef448b6c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798837111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1798837111
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.3752188162
Short name T60
Test name
Test status
Simulation time 163597497520 ps
CPU time 730.32 seconds
Started Jun 10 06:24:55 PM PDT 24
Finished Jun 10 06:37:05 PM PDT 24
Peak memory 191300 kb
Host smart-c04bd3ee-5c08-43e7-b043-c8931e5cc4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752188162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3752188162
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2852519585
Short name T129
Test name
Test status
Simulation time 925523109060 ps
CPU time 336.16 seconds
Started Jun 10 06:28:09 PM PDT 24
Finished Jun 10 06:33:45 PM PDT 24
Peak memory 191308 kb
Host smart-cf125553-2761-4e1d-8490-96df2289c4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852519585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2852519585
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1735132215
Short name T53
Test name
Test status
Simulation time 4072532288151 ps
CPU time 1127.28 seconds
Started Jun 10 06:23:57 PM PDT 24
Finished Jun 10 06:42:45 PM PDT 24
Peak memory 196884 kb
Host smart-49a66c12-940a-47b8-a9ab-b2d17e737398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735132215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1735132215
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_random.2931549481
Short name T234
Test name
Test status
Simulation time 900176893964 ps
CPU time 866.45 seconds
Started Jun 10 06:23:55 PM PDT 24
Finished Jun 10 06:38:22 PM PDT 24
Peak memory 191264 kb
Host smart-29a0b68b-e777-4c2e-97a5-8c512e3b893c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931549481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2931549481
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2597274351
Short name T426
Test name
Test status
Simulation time 1800757716563 ps
CPU time 2357.09 seconds
Started Jun 10 06:24:09 PM PDT 24
Finished Jun 10 07:03:27 PM PDT 24
Peak memory 191260 kb
Host smart-ce009043-0fee-4bac-b132-4192fbe2b218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597274351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2597274351
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.200942596
Short name T101
Test name
Test status
Simulation time 30220557 ps
CPU time 0.7 seconds
Started Jun 10 06:22:42 PM PDT 24
Finished Jun 10 06:22:43 PM PDT 24
Peak memory 193280 kb
Host smart-26881da6-2b61-4b78-ad76-8b69c7edc894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200942596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.200942596
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/12.rv_timer_random.222217423
Short name T231
Test name
Test status
Simulation time 181295163169 ps
CPU time 294.5 seconds
Started Jun 10 06:23:43 PM PDT 24
Finished Jun 10 06:28:38 PM PDT 24
Peak memory 191264 kb
Host smart-be71d6b2-36a4-4dd6-b390-7de62f720b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222217423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.222217423
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2464218086
Short name T163
Test name
Test status
Simulation time 64274459107 ps
CPU time 287.14 seconds
Started Jun 10 06:28:50 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 191284 kb
Host smart-240af525-4873-45ab-8855-64fd0c5b3d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464218086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2464218086
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2343962779
Short name T308
Test name
Test status
Simulation time 140086347567 ps
CPU time 2003.63 seconds
Started Jun 10 06:28:53 PM PDT 24
Finished Jun 10 07:02:17 PM PDT 24
Peak memory 191240 kb
Host smart-33f4fca0-bc5c-44b8-b871-825d5b82a174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343962779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2343962779
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4041478064
Short name T117
Test name
Test status
Simulation time 224932694995 ps
CPU time 378.75 seconds
Started Jun 10 06:26:02 PM PDT 24
Finished Jun 10 06:32:21 PM PDT 24
Peak memory 191212 kb
Host smart-a70ed106-8bda-4971-a7fe-5291c878b2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041478064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4041478064
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1575812524
Short name T186
Test name
Test status
Simulation time 961519112060 ps
CPU time 835.94 seconds
Started Jun 10 06:26:28 PM PDT 24
Finished Jun 10 06:40:24 PM PDT 24
Peak memory 191240 kb
Host smart-92633c5d-5d80-41f4-90d2-4fffaa697c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575812524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1575812524
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.3097564433
Short name T351
Test name
Test status
Simulation time 302511481404 ps
CPU time 253.01 seconds
Started Jun 10 06:27:39 PM PDT 24
Finished Jun 10 06:31:52 PM PDT 24
Peak memory 191276 kb
Host smart-58169336-c73d-478c-a0c9-3bf6dc2270f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097564433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3097564433
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1862196414
Short name T72
Test name
Test status
Simulation time 418712615213 ps
CPU time 316.43 seconds
Started Jun 10 06:28:41 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 191288 kb
Host smart-b5d9c09b-7025-4585-bb6a-24514c2c9bb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862196414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1862196414
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1452727238
Short name T11
Test name
Test status
Simulation time 223989487351 ps
CPU time 415.99 seconds
Started Jun 10 06:24:39 PM PDT 24
Finished Jun 10 06:31:35 PM PDT 24
Peak memory 191216 kb
Host smart-60845109-5315-4ab7-b4e7-e043cf25fc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452727238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1452727238
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.580525811
Short name T263
Test name
Test status
Simulation time 162696915218 ps
CPU time 298.38 seconds
Started Jun 10 06:26:27 PM PDT 24
Finished Jun 10 06:31:25 PM PDT 24
Peak memory 183048 kb
Host smart-d7763c98-6049-4e1f-b01f-33c31584767f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580525811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.580525811
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.3270989234
Short name T156
Test name
Test status
Simulation time 388612184637 ps
CPU time 2581.78 seconds
Started Jun 10 06:26:44 PM PDT 24
Finished Jun 10 07:09:46 PM PDT 24
Peak memory 191280 kb
Host smart-cb703af4-a404-49cc-b088-a030ee6c1b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270989234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3270989234
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.2480857579
Short name T203
Test name
Test status
Simulation time 252891138664 ps
CPU time 255.81 seconds
Started Jun 10 06:23:30 PM PDT 24
Finished Jun 10 06:27:46 PM PDT 24
Peak memory 191240 kb
Host smart-01b63abe-086f-421d-92c0-1387c971798a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480857579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2480857579
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3485702017
Short name T135
Test name
Test status
Simulation time 167315739530 ps
CPU time 227.49 seconds
Started Jun 10 06:27:07 PM PDT 24
Finished Jun 10 06:30:54 PM PDT 24
Peak memory 191272 kb
Host smart-39e8a39c-dc3f-4601-83f8-984e7dd24561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485702017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3485702017
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2668256024
Short name T74
Test name
Test status
Simulation time 72799515808 ps
CPU time 163.22 seconds
Started Jun 10 06:27:52 PM PDT 24
Finished Jun 10 06:30:36 PM PDT 24
Peak memory 191284 kb
Host smart-e27b2e8b-d31c-4d89-90af-eae90beac84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668256024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2668256024
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.1280321490
Short name T180
Test name
Test status
Simulation time 133773436170 ps
CPU time 233.66 seconds
Started Jun 10 06:28:08 PM PDT 24
Finished Jun 10 06:32:01 PM PDT 24
Peak memory 191284 kb
Host smart-333ed5a3-b0d4-48c8-8873-ae5d56095d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280321490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1280321490
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2464599216
Short name T249
Test name
Test status
Simulation time 155691030675 ps
CPU time 277.47 seconds
Started Jun 10 06:28:18 PM PDT 24
Finished Jun 10 06:32:56 PM PDT 24
Peak memory 193848 kb
Host smart-0d95cdd4-82a3-4ccd-8a9d-c5fa5ff6d9d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464599216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2464599216
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1600136915
Short name T256
Test name
Test status
Simulation time 65406697727 ps
CPU time 105.24 seconds
Started Jun 10 06:28:23 PM PDT 24
Finished Jun 10 06:30:09 PM PDT 24
Peak memory 191280 kb
Host smart-38472bb6-3175-4cab-97e6-4b4a688f1f9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600136915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1600136915
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.699916417
Short name T130
Test name
Test status
Simulation time 68187980076 ps
CPU time 267.41 seconds
Started Jun 10 06:24:17 PM PDT 24
Finished Jun 10 06:28:45 PM PDT 24
Peak memory 191276 kb
Host smart-cca5bcab-dc44-4949-ad12-bbecd5d54e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699916417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.699916417
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3004395206
Short name T48
Test name
Test status
Simulation time 704228034776 ps
CPU time 922.27 seconds
Started Jun 10 06:26:43 PM PDT 24
Finished Jun 10 06:42:06 PM PDT 24
Peak memory 191268 kb
Host smart-2a2dd024-7fa8-4ce1-b7b4-2b474d85903a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004395206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3004395206
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_random.2917031409
Short name T118
Test name
Test status
Simulation time 542660274199 ps
CPU time 846.55 seconds
Started Jun 10 06:23:33 PM PDT 24
Finished Jun 10 06:37:39 PM PDT 24
Peak memory 193356 kb
Host smart-d58bdbc9-561b-451f-938f-ec9a26549e62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917031409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2917031409
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3425886075
Short name T159
Test name
Test status
Simulation time 216392955711 ps
CPU time 205.08 seconds
Started Jun 10 06:27:31 PM PDT 24
Finished Jun 10 06:30:57 PM PDT 24
Peak memory 191240 kb
Host smart-8810f63d-d310-4c1a-bd23-c19db51e7633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425886075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3425886075
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1950284926
Short name T214
Test name
Test status
Simulation time 355453908909 ps
CPU time 205.34 seconds
Started Jun 10 06:27:48 PM PDT 24
Finished Jun 10 06:31:13 PM PDT 24
Peak memory 191276 kb
Host smart-646d0889-4309-4d2a-bdb6-bde62ff3b4eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950284926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1950284926
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3146461570
Short name T193
Test name
Test status
Simulation time 198110848441 ps
CPU time 509.11 seconds
Started Jun 10 06:28:00 PM PDT 24
Finished Jun 10 06:36:29 PM PDT 24
Peak memory 191236 kb
Host smart-988c347d-a4a2-48c7-9eb3-d34c73759aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146461570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3146461570
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1690745502
Short name T291
Test name
Test status
Simulation time 130624142268 ps
CPU time 233.65 seconds
Started Jun 10 06:28:19 PM PDT 24
Finished Jun 10 06:32:13 PM PDT 24
Peak memory 191264 kb
Host smart-78a31d9f-d33d-4f7f-baf1-8e9d7eae9a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690745502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1690745502
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1008177250
Short name T330
Test name
Test status
Simulation time 50026690454 ps
CPU time 76.1 seconds
Started Jun 10 06:23:52 PM PDT 24
Finished Jun 10 06:25:08 PM PDT 24
Peak memory 191192 kb
Host smart-1df8feb9-5153-4cf5-bbc4-2ce2c060ef3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008177250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1008177250
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.301320299
Short name T124
Test name
Test status
Simulation time 288909435085 ps
CPU time 202.37 seconds
Started Jun 10 06:28:33 PM PDT 24
Finished Jun 10 06:31:55 PM PDT 24
Peak memory 191180 kb
Host smart-87140070-9a01-4bc6-9ce8-ea735290801f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301320299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.301320299
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.195255421
Short name T265
Test name
Test status
Simulation time 74199945017 ps
CPU time 141.03 seconds
Started Jun 10 06:28:40 PM PDT 24
Finished Jun 10 06:31:01 PM PDT 24
Peak memory 191292 kb
Host smart-4ba407a4-c265-471d-9e18-5e55fb662648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195255421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.195255421
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3422529942
Short name T86
Test name
Test status
Simulation time 612653521605 ps
CPU time 463.41 seconds
Started Jun 10 06:28:43 PM PDT 24
Finished Jun 10 06:36:26 PM PDT 24
Peak memory 191284 kb
Host smart-82ed9634-3533-4298-a839-c5c4636e782f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422529942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3422529942
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3469805452
Short name T242
Test name
Test status
Simulation time 823380858571 ps
CPU time 546.07 seconds
Started Jun 10 06:28:50 PM PDT 24
Finished Jun 10 06:37:56 PM PDT 24
Peak memory 191272 kb
Host smart-258e9a61-27e1-4ef0-9a05-a43001e9d865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469805452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3469805452
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.2841529920
Short name T215
Test name
Test status
Simulation time 399432741825 ps
CPU time 230.86 seconds
Started Jun 10 06:24:30 PM PDT 24
Finished Jun 10 06:28:22 PM PDT 24
Peak memory 191276 kb
Host smart-f761d510-4efa-4393-8dfb-5134b232be29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841529920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2841529920
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.420589390
Short name T121
Test name
Test status
Simulation time 387323122395 ps
CPU time 673.19 seconds
Started Jun 10 06:24:40 PM PDT 24
Finished Jun 10 06:35:53 PM PDT 24
Peak memory 183052 kb
Host smart-c84171a6-aa01-4584-b122-ca7caa037387
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420589390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.420589390
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.431792730
Short name T306
Test name
Test status
Simulation time 128290873065 ps
CPU time 334.6 seconds
Started Jun 10 06:25:04 PM PDT 24
Finished Jun 10 06:30:39 PM PDT 24
Peak memory 191244 kb
Host smart-11378541-fc36-4dbd-84d2-c56122cae473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431792730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
431792730
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1821971305
Short name T173
Test name
Test status
Simulation time 405534721866 ps
CPU time 108.87 seconds
Started Jun 10 06:25:24 PM PDT 24
Finished Jun 10 06:27:13 PM PDT 24
Peak memory 183056 kb
Host smart-f2f057e7-8e99-4d47-8eda-390fa71e8c72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821971305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1821971305
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/51.rv_timer_random.4245619995
Short name T302
Test name
Test status
Simulation time 321505757948 ps
CPU time 320.17 seconds
Started Jun 10 06:26:58 PM PDT 24
Finished Jun 10 06:32:19 PM PDT 24
Peak memory 191220 kb
Host smart-2e4f1ff2-7e0e-4a42-96e2-d6853f195de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245619995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4245619995
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3194484083
Short name T250
Test name
Test status
Simulation time 147065216366 ps
CPU time 266.37 seconds
Started Jun 10 06:27:30 PM PDT 24
Finished Jun 10 06:31:56 PM PDT 24
Peak memory 191256 kb
Host smart-60b6cd2b-82f9-4d43-a065-89e47f9ec73a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194484083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3194484083
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2463673477
Short name T571
Test name
Test status
Simulation time 370747868 ps
CPU time 1.33 seconds
Started Jun 10 06:22:38 PM PDT 24
Finished Jun 10 06:22:39 PM PDT 24
Peak memory 183316 kb
Host smart-aef69bbd-f6fd-43fb-8019-925094dcab15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463673477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2463673477
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_random.3903129705
Short name T248
Test name
Test status
Simulation time 52095416924 ps
CPU time 336.43 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:28:53 PM PDT 24
Peak memory 191264 kb
Host smart-d570fa47-7bd9-48a3-982a-e3db94fe6bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903129705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3903129705
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3523882992
Short name T346
Test name
Test status
Simulation time 615776329231 ps
CPU time 332.86 seconds
Started Jun 10 06:23:44 PM PDT 24
Finished Jun 10 06:29:17 PM PDT 24
Peak memory 183024 kb
Host smart-6d9474fb-0034-4c06-9051-2e6506eb7ba9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523882992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3523882992
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/115.rv_timer_random.3624914198
Short name T155
Test name
Test status
Simulation time 122668049440 ps
CPU time 96.97 seconds
Started Jun 10 06:27:47 PM PDT 24
Finished Jun 10 06:29:24 PM PDT 24
Peak memory 191280 kb
Host smart-bf2636ba-55aa-44b4-8524-2fc21f67f5e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624914198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3624914198
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2627677399
Short name T26
Test name
Test status
Simulation time 48692249260 ps
CPU time 93.51 seconds
Started Jun 10 06:27:51 PM PDT 24
Finished Jun 10 06:29:24 PM PDT 24
Peak memory 191228 kb
Host smart-d28a9a47-4685-4746-9e95-023f0ff072cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627677399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2627677399
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.493455653
Short name T287
Test name
Test status
Simulation time 1063680485005 ps
CPU time 554.47 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:33:06 PM PDT 24
Peak memory 183048 kb
Host smart-1c3f1e18-63e5-453e-aa14-d74e139b01ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493455653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.493455653
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/127.rv_timer_random.1385742485
Short name T274
Test name
Test status
Simulation time 102608317629 ps
CPU time 188.94 seconds
Started Jun 10 06:28:03 PM PDT 24
Finished Jun 10 06:31:12 PM PDT 24
Peak memory 191264 kb
Host smart-f7fb5232-b0b9-4d8f-b5b3-23d04fa1973c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385742485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1385742485
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.2298678721
Short name T289
Test name
Test status
Simulation time 110470299675 ps
CPU time 198.81 seconds
Started Jun 10 06:23:48 PM PDT 24
Finished Jun 10 06:27:07 PM PDT 24
Peak memory 191224 kb
Host smart-8519744f-7620-4585-bea5-3ad48f768ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298678721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2298678721
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1888212032
Short name T342
Test name
Test status
Simulation time 12552593182 ps
CPU time 20.78 seconds
Started Jun 10 06:23:50 PM PDT 24
Finished Jun 10 06:24:11 PM PDT 24
Peak memory 182972 kb
Host smart-16902528-54c6-4fb7-b6a6-b7979b03879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888212032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1888212032
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/137.rv_timer_random.1128773230
Short name T221
Test name
Test status
Simulation time 2355067885807 ps
CPU time 799.97 seconds
Started Jun 10 06:28:13 PM PDT 24
Finished Jun 10 06:41:33 PM PDT 24
Peak memory 193304 kb
Host smart-18294537-2a8d-4267-bfb9-aead04104f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128773230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1128773230
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.180524358
Short name T92
Test name
Test status
Simulation time 88308174201 ps
CPU time 158.86 seconds
Started Jun 10 06:28:10 PM PDT 24
Finished Jun 10 06:30:49 PM PDT 24
Peak memory 191312 kb
Host smart-ab7cc052-5767-45a5-9039-2380bf6bb21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180524358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.180524358
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1884283814
Short name T258
Test name
Test status
Simulation time 368927004167 ps
CPU time 599.35 seconds
Started Jun 10 06:23:54 PM PDT 24
Finished Jun 10 06:33:54 PM PDT 24
Peak memory 183068 kb
Host smart-7748332e-3708-4882-b380-f61a0cf873af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884283814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1884283814
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/156.rv_timer_random.2817668362
Short name T128
Test name
Test status
Simulation time 319866935491 ps
CPU time 201.27 seconds
Started Jun 10 06:28:31 PM PDT 24
Finished Jun 10 06:31:52 PM PDT 24
Peak memory 194852 kb
Host smart-db7cac81-c9f2-492e-b461-4f14b26aeddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817668362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2817668362
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3587176758
Short name T281
Test name
Test status
Simulation time 872494586444 ps
CPU time 165.32 seconds
Started Jun 10 06:28:31 PM PDT 24
Finished Jun 10 06:31:16 PM PDT 24
Peak memory 191220 kb
Host smart-09f38bae-1374-48ec-a1cf-0698b83aaa77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587176758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3587176758
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1524039853
Short name T288
Test name
Test status
Simulation time 161829730945 ps
CPU time 381.48 seconds
Started Jun 10 06:28:42 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 191240 kb
Host smart-0cfd7474-cfce-4ca1-b71b-cb0c3eccf979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524039853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1524039853
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.790165992
Short name T232
Test name
Test status
Simulation time 100379847614 ps
CPU time 1076.71 seconds
Started Jun 10 06:28:44 PM PDT 24
Finished Jun 10 06:46:41 PM PDT 24
Peak memory 191288 kb
Host smart-2b45d6e6-bffc-4ea8-8f18-317efc447e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790165992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.790165992
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3921854110
Short name T244
Test name
Test status
Simulation time 982229411426 ps
CPU time 216.04 seconds
Started Jun 10 06:28:46 PM PDT 24
Finished Jun 10 06:32:22 PM PDT 24
Peak memory 191260 kb
Host smart-af81b408-d2de-4f1a-a8c6-bde7608cef0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921854110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3921854110
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4272470326
Short name T267
Test name
Test status
Simulation time 159030232529 ps
CPU time 816.64 seconds
Started Jun 10 06:28:46 PM PDT 24
Finished Jun 10 06:42:23 PM PDT 24
Peak memory 191148 kb
Host smart-494c5f71-c6d9-4f6a-8ecb-90feadbc7701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272470326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4272470326
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1894950792
Short name T177
Test name
Test status
Simulation time 640003588727 ps
CPU time 336.12 seconds
Started Jun 10 06:29:02 PM PDT 24
Finished Jun 10 06:34:39 PM PDT 24
Peak memory 193300 kb
Host smart-7f95d63e-4701-42e3-a773-c4760c1ecc49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894950792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1894950792
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1222567522
Short name T320
Test name
Test status
Simulation time 169773344813 ps
CPU time 140.69 seconds
Started Jun 10 06:24:28 PM PDT 24
Finished Jun 10 06:26:49 PM PDT 24
Peak memory 183076 kb
Host smart-6d4ed006-de3f-48b9-be68-e37e6b995798
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222567522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1222567522
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_random.2168664461
Short name T160
Test name
Test status
Simulation time 121274319875 ps
CPU time 736.95 seconds
Started Jun 10 06:24:32 PM PDT 24
Finished Jun 10 06:36:49 PM PDT 24
Peak memory 191248 kb
Host smart-84b2f09a-13bb-4990-b325-7eb532580bd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168664461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2168664461
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1391382160
Short name T272
Test name
Test status
Simulation time 4598863358476 ps
CPU time 1037.88 seconds
Started Jun 10 06:24:35 PM PDT 24
Finished Jun 10 06:41:53 PM PDT 24
Peak memory 183052 kb
Host smart-705c3a24-9c50-4b2b-bf0e-a62e03bb5a2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391382160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1391382160
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.828886183
Short name T318
Test name
Test status
Simulation time 1126946734016 ps
CPU time 326.29 seconds
Started Jun 10 06:24:44 PM PDT 24
Finished Jun 10 06:30:11 PM PDT 24
Peak memory 191268 kb
Host smart-55f9cc69-23b4-42a0-80d8-07451517bc9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828886183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
828886183
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2646243947
Short name T339
Test name
Test status
Simulation time 419847216342 ps
CPU time 635.21 seconds
Started Jun 10 06:24:51 PM PDT 24
Finished Jun 10 06:35:27 PM PDT 24
Peak memory 183100 kb
Host smart-592bc1bf-9f00-43ac-9344-51cfbc0421a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646243947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2646243947
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random.4045380621
Short name T149
Test name
Test status
Simulation time 135772189906 ps
CPU time 51.84 seconds
Started Jun 10 06:23:23 PM PDT 24
Finished Jun 10 06:24:15 PM PDT 24
Peak memory 193776 kb
Host smart-19ef636e-b125-4558-aab7-4418820d60ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045380621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.4045380621
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.148759100
Short name T337
Test name
Test status
Simulation time 25319632963 ps
CPU time 45.31 seconds
Started Jun 10 06:26:23 PM PDT 24
Finished Jun 10 06:27:09 PM PDT 24
Peak memory 183076 kb
Host smart-92efe0e1-6f77-40cd-a780-2138392dd946
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148759100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.148759100
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/50.rv_timer_random.2945519833
Short name T326
Test name
Test status
Simulation time 388611982948 ps
CPU time 618.6 seconds
Started Jun 10 06:26:56 PM PDT 24
Finished Jun 10 06:37:15 PM PDT 24
Peak memory 191268 kb
Host smart-70c612e3-c006-4897-932c-cb0ae26ece6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945519833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2945519833
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.588366762
Short name T4
Test name
Test status
Simulation time 247115330308 ps
CPU time 1173.63 seconds
Started Jun 10 06:27:26 PM PDT 24
Finished Jun 10 06:47:00 PM PDT 24
Peak memory 191228 kb
Host smart-33d600a2-41b7-4361-b008-9a9fb2f3f6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588366762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.588366762
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1765038527
Short name T77
Test name
Test status
Simulation time 61940071 ps
CPU time 0.82 seconds
Started Jun 10 06:21:56 PM PDT 24
Finished Jun 10 06:21:57 PM PDT 24
Peak memory 182764 kb
Host smart-ab1dcc22-7515-4558-bfd9-0c4760ad7f5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765038527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1765038527
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2388672273
Short name T543
Test name
Test status
Simulation time 284149615 ps
CPU time 3.64 seconds
Started Jun 10 06:21:56 PM PDT 24
Finished Jun 10 06:22:00 PM PDT 24
Peak memory 193964 kb
Host smart-7ff71810-42cb-4c01-aea1-1cdbe6fcfe48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388672273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2388672273
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2163700405
Short name T464
Test name
Test status
Simulation time 36952240 ps
CPU time 0.56 seconds
Started Jun 10 06:21:51 PM PDT 24
Finished Jun 10 06:21:52 PM PDT 24
Peak memory 182740 kb
Host smart-21dd3788-f1d0-40d6-a3e9-55856bea4b48
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163700405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2163700405
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2940796912
Short name T482
Test name
Test status
Simulation time 30000130 ps
CPU time 0.67 seconds
Started Jun 10 06:21:55 PM PDT 24
Finished Jun 10 06:21:56 PM PDT 24
Peak memory 193468 kb
Host smart-dd64fe63-f4c5-4681-a96b-811a55e7987b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940796912 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2940796912
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1612385776
Short name T462
Test name
Test status
Simulation time 15728285 ps
CPU time 0.6 seconds
Started Jun 10 06:21:50 PM PDT 24
Finished Jun 10 06:21:51 PM PDT 24
Peak memory 182680 kb
Host smart-e7abb2df-ede4-473b-a520-789d85ae8c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612385776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1612385776
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2592345225
Short name T542
Test name
Test status
Simulation time 45222030 ps
CPU time 0.55 seconds
Started Jun 10 06:21:51 PM PDT 24
Finished Jun 10 06:21:51 PM PDT 24
Peak memory 182676 kb
Host smart-f3533c6d-ad46-4252-9f55-0c1d83095e5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592345225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2592345225
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2677497926
Short name T534
Test name
Test status
Simulation time 21834891 ps
CPU time 0.61 seconds
Started Jun 10 06:21:52 PM PDT 24
Finished Jun 10 06:21:53 PM PDT 24
Peak memory 192036 kb
Host smart-820d71a9-5c05-4fe8-bc6c-d9cefd52e9ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677497926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2677497926
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2269479525
Short name T472
Test name
Test status
Simulation time 23190397 ps
CPU time 1.19 seconds
Started Jun 10 06:21:46 PM PDT 24
Finished Jun 10 06:21:48 PM PDT 24
Peak memory 197628 kb
Host smart-a9111704-c114-402f-8611-8951e3f578b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269479525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2269479525
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1069209581
Short name T515
Test name
Test status
Simulation time 416949229 ps
CPU time 1.35 seconds
Started Jun 10 06:21:50 PM PDT 24
Finished Jun 10 06:21:51 PM PDT 24
Peak memory 195364 kb
Host smart-19745f98-0e09-4587-a0e3-0a271f7e8926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069209581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1069209581
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1013003840
Short name T78
Test name
Test status
Simulation time 47552115 ps
CPU time 0.72 seconds
Started Jun 10 06:21:58 PM PDT 24
Finished Jun 10 06:21:59 PM PDT 24
Peak memory 192440 kb
Host smart-6831f828-7baf-498b-b772-1ed976528a55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013003840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1013003840
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2455094577
Short name T554
Test name
Test status
Simulation time 1513495443 ps
CPU time 3.52 seconds
Started Jun 10 06:22:00 PM PDT 24
Finished Jun 10 06:22:04 PM PDT 24
Peak memory 193612 kb
Host smart-97e541b5-2f32-49d8-ad82-991529a98abe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455094577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2455094577
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4126111860
Short name T99
Test name
Test status
Simulation time 90475782 ps
CPU time 0.59 seconds
Started Jun 10 06:21:59 PM PDT 24
Finished Jun 10 06:22:00 PM PDT 24
Peak memory 182756 kb
Host smart-df635ef5-83c3-4aba-9676-27920207c0e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126111860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4126111860
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3264598453
Short name T529
Test name
Test status
Simulation time 18305128 ps
CPU time 0.88 seconds
Started Jun 10 06:22:00 PM PDT 24
Finished Jun 10 06:22:01 PM PDT 24
Peak memory 197312 kb
Host smart-a316fb19-c2d7-4f30-bc97-42ce9f53fbb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264598453 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3264598453
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.856756088
Short name T579
Test name
Test status
Simulation time 13045221 ps
CPU time 0.56 seconds
Started Jun 10 06:22:00 PM PDT 24
Finished Jun 10 06:22:01 PM PDT 24
Peak memory 182472 kb
Host smart-aa570864-a0a2-4e07-b941-c0e084091924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856756088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.856756088
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2157146867
Short name T484
Test name
Test status
Simulation time 38323113 ps
CPU time 0.55 seconds
Started Jun 10 06:21:57 PM PDT 24
Finished Jun 10 06:21:58 PM PDT 24
Peak memory 182136 kb
Host smart-a63470c6-062a-4626-9a9d-b5e79366ac15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157146867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2157146867
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3679107737
Short name T107
Test name
Test status
Simulation time 15811250 ps
CPU time 0.62 seconds
Started Jun 10 06:22:00 PM PDT 24
Finished Jun 10 06:22:01 PM PDT 24
Peak memory 192048 kb
Host smart-b9a02046-aaea-4039-971f-e877c5a5b82b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679107737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3679107737
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3250721830
Short name T552
Test name
Test status
Simulation time 478615326 ps
CPU time 2.07 seconds
Started Jun 10 06:21:53 PM PDT 24
Finished Jun 10 06:21:55 PM PDT 24
Peak memory 197688 kb
Host smart-73f7a3ad-e465-42f8-a741-890ce5b4e30d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250721830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3250721830
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4097681338
Short name T538
Test name
Test status
Simulation time 496676215 ps
CPU time 1.09 seconds
Started Jun 10 06:21:59 PM PDT 24
Finished Jun 10 06:22:00 PM PDT 24
Peak memory 183476 kb
Host smart-6f8ec66d-95d4-4649-bec2-9d3e9083286c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097681338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4097681338
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.209157598
Short name T563
Test name
Test status
Simulation time 21375254 ps
CPU time 0.78 seconds
Started Jun 10 06:22:37 PM PDT 24
Finished Jun 10 06:22:38 PM PDT 24
Peak memory 196160 kb
Host smart-99ae2e21-3af5-4697-a40f-9479cd18ac7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209157598 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.209157598
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.398991724
Short name T96
Test name
Test status
Simulation time 35058515 ps
CPU time 0.55 seconds
Started Jun 10 06:22:39 PM PDT 24
Finished Jun 10 06:22:39 PM PDT 24
Peak memory 182404 kb
Host smart-a554c0e3-7f22-44ca-8e7b-d90d63622961
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398991724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.398991724
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2700066569
Short name T540
Test name
Test status
Simulation time 13593333 ps
CPU time 0.57 seconds
Started Jun 10 06:22:37 PM PDT 24
Finished Jun 10 06:22:37 PM PDT 24
Peak memory 182672 kb
Host smart-5dcee1bd-d1f2-4e76-b12e-021e947b2b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700066569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2700066569
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2578439263
Short name T564
Test name
Test status
Simulation time 29974398 ps
CPU time 0.75 seconds
Started Jun 10 06:22:38 PM PDT 24
Finished Jun 10 06:22:39 PM PDT 24
Peak memory 191756 kb
Host smart-a1e41f94-99db-4b66-b9b9-3dc2eeb0032d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578439263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2578439263
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1606926041
Short name T478
Test name
Test status
Simulation time 60942328 ps
CPU time 3.02 seconds
Started Jun 10 06:22:36 PM PDT 24
Finished Jun 10 06:22:39 PM PDT 24
Peak memory 197628 kb
Host smart-c5358e9b-4486-442f-b759-50f7d70ddcff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606926041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1606926041
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.262569977
Short name T569
Test name
Test status
Simulation time 31770989 ps
CPU time 1.37 seconds
Started Jun 10 06:22:44 PM PDT 24
Finished Jun 10 06:22:46 PM PDT 24
Peak memory 197700 kb
Host smart-9b4c5ab3-2add-4d3d-90ca-ce728adec755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262569977 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.262569977
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.315992077
Short name T575
Test name
Test status
Simulation time 135873873 ps
CPU time 0.59 seconds
Started Jun 10 06:22:41 PM PDT 24
Finished Jun 10 06:22:42 PM PDT 24
Peak memory 182372 kb
Host smart-2eee7770-282d-4988-b083-019a8e4d274b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315992077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.315992077
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2379875263
Short name T558
Test name
Test status
Simulation time 50848830 ps
CPU time 0.57 seconds
Started Jun 10 06:22:44 PM PDT 24
Finished Jun 10 06:22:45 PM PDT 24
Peak memory 182500 kb
Host smart-cef33d74-8b69-40d8-8dba-209dbb01b15d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379875263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2379875263
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3955696223
Short name T573
Test name
Test status
Simulation time 142262552 ps
CPU time 0.62 seconds
Started Jun 10 06:22:42 PM PDT 24
Finished Jun 10 06:22:43 PM PDT 24
Peak memory 192112 kb
Host smart-6b26c8e7-3ad2-4fb1-9eb8-09c1c905bf7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955696223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3955696223
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2290449060
Short name T470
Test name
Test status
Simulation time 87456565 ps
CPU time 2.16 seconds
Started Jun 10 06:22:42 PM PDT 24
Finished Jun 10 06:22:44 PM PDT 24
Peak memory 197648 kb
Host smart-8892f259-6b49-4555-baf3-6777340037b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290449060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2290449060
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.980585536
Short name T566
Test name
Test status
Simulation time 287753211 ps
CPU time 1.15 seconds
Started Jun 10 06:22:43 PM PDT 24
Finished Jun 10 06:22:45 PM PDT 24
Peak memory 195436 kb
Host smart-1556290d-fab6-4aa3-abc0-f0971beba286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980585536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.980585536
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4037081690
Short name T506
Test name
Test status
Simulation time 89892230 ps
CPU time 0.79 seconds
Started Jun 10 06:22:44 PM PDT 24
Finished Jun 10 06:22:45 PM PDT 24
Peak memory 195672 kb
Host smart-ac44420c-e33d-422e-8e22-2bd0a341da0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037081690 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.4037081690
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2608943760
Short name T490
Test name
Test status
Simulation time 14804522 ps
CPU time 0.53 seconds
Started Jun 10 06:22:41 PM PDT 24
Finished Jun 10 06:22:42 PM PDT 24
Peak memory 182624 kb
Host smart-e9e0384e-826b-4848-9e6a-39b8de2fd40c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608943760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2608943760
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3991724611
Short name T454
Test name
Test status
Simulation time 33886928 ps
CPU time 1.65 seconds
Started Jun 10 06:22:42 PM PDT 24
Finished Jun 10 06:22:44 PM PDT 24
Peak memory 197640 kb
Host smart-30139ed8-3e07-48d0-8cb5-00ba65bef58c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991724611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3991724611
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.110682701
Short name T495
Test name
Test status
Simulation time 53031286 ps
CPU time 1.14 seconds
Started Jun 10 06:22:50 PM PDT 24
Finished Jun 10 06:22:52 PM PDT 24
Peak memory 197672 kb
Host smart-a96ed1e7-a263-4f86-92e3-9a8e45b54c45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110682701 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.110682701
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2083280347
Short name T95
Test name
Test status
Simulation time 92029897 ps
CPU time 0.59 seconds
Started Jun 10 06:22:45 PM PDT 24
Finished Jun 10 06:22:46 PM PDT 24
Peak memory 182840 kb
Host smart-bc263778-04bf-4e77-9820-6c3f389b4b77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083280347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2083280347
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3180442654
Short name T469
Test name
Test status
Simulation time 13440709 ps
CPU time 0.55 seconds
Started Jun 10 06:22:48 PM PDT 24
Finished Jun 10 06:22:48 PM PDT 24
Peak memory 182636 kb
Host smart-31d57a1b-9bef-4ce0-95ff-b49f84f265d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180442654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3180442654
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.95950709
Short name T501
Test name
Test status
Simulation time 404782555 ps
CPU time 0.73 seconds
Started Jun 10 06:22:46 PM PDT 24
Finished Jun 10 06:22:47 PM PDT 24
Peak memory 193164 kb
Host smart-85b3d773-b5e7-498e-baea-4c3c61166251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95950709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_tim
er_same_csr_outstanding.95950709
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2260546675
Short name T572
Test name
Test status
Simulation time 1414445882 ps
CPU time 2.49 seconds
Started Jun 10 06:22:44 PM PDT 24
Finished Jun 10 06:22:47 PM PDT 24
Peak memory 197628 kb
Host smart-22171aa6-c6ab-4744-8dde-0721f6d2d4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260546675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2260546675
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1486624788
Short name T30
Test name
Test status
Simulation time 529765989 ps
CPU time 1.07 seconds
Started Jun 10 06:22:45 PM PDT 24
Finished Jun 10 06:22:46 PM PDT 24
Peak memory 183360 kb
Host smart-b4e02dac-d1a9-4d89-a7b5-c8030a86d0e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486624788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1486624788
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.466790305
Short name T483
Test name
Test status
Simulation time 106785351 ps
CPU time 1.32 seconds
Started Jun 10 06:22:51 PM PDT 24
Finished Jun 10 06:22:52 PM PDT 24
Peak memory 197640 kb
Host smart-d81e667a-0572-4c4a-960f-cef7fec802de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466790305 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.466790305
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2367247290
Short name T512
Test name
Test status
Simulation time 19374142 ps
CPU time 0.6 seconds
Started Jun 10 06:22:48 PM PDT 24
Finished Jun 10 06:22:49 PM PDT 24
Peak memory 191936 kb
Host smart-5c864c38-ed78-43d4-9b9f-5dc6e6cfae78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367247290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2367247290
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2045363885
Short name T577
Test name
Test status
Simulation time 13832898 ps
CPU time 0.55 seconds
Started Jun 10 06:22:50 PM PDT 24
Finished Jun 10 06:22:51 PM PDT 24
Peak memory 182620 kb
Host smart-df229537-f3bc-4f1b-a295-bb4ebbe6f1b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045363885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2045363885
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2278070834
Short name T102
Test name
Test status
Simulation time 17548091 ps
CPU time 0.64 seconds
Started Jun 10 06:22:49 PM PDT 24
Finished Jun 10 06:22:50 PM PDT 24
Peak memory 192092 kb
Host smart-d525dd55-be79-44d1-8f1d-e09d3b138119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278070834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2278070834
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2538491512
Short name T468
Test name
Test status
Simulation time 96154177 ps
CPU time 1.48 seconds
Started Jun 10 06:22:49 PM PDT 24
Finished Jun 10 06:22:51 PM PDT 24
Peak memory 197668 kb
Host smart-d240c75a-4d9c-4072-99b2-fecb096adb85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538491512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2538491512
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1518169334
Short name T111
Test name
Test status
Simulation time 183823468 ps
CPU time 1.13 seconds
Started Jun 10 06:22:51 PM PDT 24
Finished Jun 10 06:22:52 PM PDT 24
Peak memory 195308 kb
Host smart-70f3fa3c-bf63-46f1-a419-9e1e8b82d4fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518169334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1518169334
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1804210483
Short name T466
Test name
Test status
Simulation time 27493329 ps
CPU time 0.7 seconds
Started Jun 10 06:22:54 PM PDT 24
Finished Jun 10 06:22:55 PM PDT 24
Peak memory 195072 kb
Host smart-ef9742f5-48ad-4087-b4b2-3342f5a6d1c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804210483 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1804210483
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2272706273
Short name T532
Test name
Test status
Simulation time 28930934 ps
CPU time 0.54 seconds
Started Jun 10 06:22:52 PM PDT 24
Finished Jun 10 06:22:53 PM PDT 24
Peak memory 182744 kb
Host smart-a5a01bfe-8a37-4a1b-b0a4-f9eb2e3ad1ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272706273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2272706273
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2825768867
Short name T505
Test name
Test status
Simulation time 13092865 ps
CPU time 0.62 seconds
Started Jun 10 06:22:55 PM PDT 24
Finished Jun 10 06:22:55 PM PDT 24
Peak memory 182576 kb
Host smart-c132ef19-792a-443e-84e1-3e8e2170e79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825768867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2825768867
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2448629176
Short name T80
Test name
Test status
Simulation time 19496137 ps
CPU time 0.78 seconds
Started Jun 10 06:22:53 PM PDT 24
Finished Jun 10 06:22:54 PM PDT 24
Peak memory 191760 kb
Host smart-dac570a3-b51f-49e3-8652-87154dc02ad1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448629176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2448629176
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3707860500
Short name T519
Test name
Test status
Simulation time 1120919649 ps
CPU time 2.57 seconds
Started Jun 10 06:22:52 PM PDT 24
Finished Jun 10 06:22:54 PM PDT 24
Peak memory 197632 kb
Host smart-900097a9-5083-4966-997c-139e1b9f9a8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707860500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3707860500
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2614773675
Short name T31
Test name
Test status
Simulation time 164126450 ps
CPU time 1.13 seconds
Started Jun 10 06:22:54 PM PDT 24
Finished Jun 10 06:22:56 PM PDT 24
Peak memory 195152 kb
Host smart-d83478e7-b9db-4abe-945f-8585e6b306d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614773675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2614773675
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.283442038
Short name T527
Test name
Test status
Simulation time 20568584 ps
CPU time 0.88 seconds
Started Jun 10 06:22:57 PM PDT 24
Finished Jun 10 06:22:59 PM PDT 24
Peak memory 196868 kb
Host smart-463e63b8-e854-4701-9060-497af2a847e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283442038 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.283442038
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3470317825
Short name T480
Test name
Test status
Simulation time 36250844 ps
CPU time 0.52 seconds
Started Jun 10 06:22:56 PM PDT 24
Finished Jun 10 06:22:57 PM PDT 24
Peak memory 182740 kb
Host smart-f9daa643-b6f9-440b-a6ec-8bfc0cfcc2d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470317825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3470317825
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.537890110
Short name T535
Test name
Test status
Simulation time 96805758 ps
CPU time 0.54 seconds
Started Jun 10 06:22:51 PM PDT 24
Finished Jun 10 06:22:52 PM PDT 24
Peak memory 182096 kb
Host smart-254cb347-e991-4342-ae3c-61662bef569e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537890110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.537890110
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.462968511
Short name T82
Test name
Test status
Simulation time 200143097 ps
CPU time 0.83 seconds
Started Jun 10 06:23:08 PM PDT 24
Finished Jun 10 06:23:09 PM PDT 24
Peak memory 191732 kb
Host smart-f5d80c5c-ac2f-4a89-9676-0de1d1b03fd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462968511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.462968511
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3722000014
Short name T514
Test name
Test status
Simulation time 31945269 ps
CPU time 1.45 seconds
Started Jun 10 06:22:52 PM PDT 24
Finished Jun 10 06:22:54 PM PDT 24
Peak memory 197652 kb
Host smart-aa98088d-19c0-406d-a6d3-c925159cf3de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722000014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3722000014
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3681928562
Short name T42
Test name
Test status
Simulation time 137330457 ps
CPU time 1.39 seconds
Started Jun 10 06:22:51 PM PDT 24
Finished Jun 10 06:22:52 PM PDT 24
Peak memory 194432 kb
Host smart-c2b5b09c-ab40-41e6-85c2-fb7a1cdd02ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681928562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3681928562
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2611193501
Short name T498
Test name
Test status
Simulation time 19853619 ps
CPU time 0.9 seconds
Started Jun 10 06:23:06 PM PDT 24
Finished Jun 10 06:23:07 PM PDT 24
Peak memory 197188 kb
Host smart-a493f9cf-08b6-4320-ae1e-ea5b7eb085e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611193501 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2611193501
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3097367641
Short name T98
Test name
Test status
Simulation time 58916471 ps
CPU time 0.61 seconds
Started Jun 10 06:22:57 PM PDT 24
Finished Jun 10 06:22:58 PM PDT 24
Peak memory 182748 kb
Host smart-a2ce7305-16e4-483d-a8c6-a767bb7912c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097367641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3097367641
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3073372480
Short name T526
Test name
Test status
Simulation time 54912822 ps
CPU time 0.54 seconds
Started Jun 10 06:23:07 PM PDT 24
Finished Jun 10 06:23:08 PM PDT 24
Peak memory 181852 kb
Host smart-234a0c04-bb26-49ce-a51d-1cc8f41e7665
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073372480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3073372480
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3784107890
Short name T548
Test name
Test status
Simulation time 40462944 ps
CPU time 0.68 seconds
Started Jun 10 06:22:57 PM PDT 24
Finished Jun 10 06:22:57 PM PDT 24
Peak memory 192172 kb
Host smart-de2ccb28-328d-4315-b20b-2e46e767022b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784107890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3784107890
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.600859039
Short name T547
Test name
Test status
Simulation time 87076689 ps
CPU time 1.13 seconds
Started Jun 10 06:23:02 PM PDT 24
Finished Jun 10 06:23:03 PM PDT 24
Peak memory 197548 kb
Host smart-5a898736-444c-4fce-9339-b7b5d55126a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600859039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.600859039
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3041135248
Short name T553
Test name
Test status
Simulation time 146630092 ps
CPU time 1.4 seconds
Started Jun 10 06:23:07 PM PDT 24
Finished Jun 10 06:23:09 PM PDT 24
Peak memory 183200 kb
Host smart-9ef987b8-2f64-41e8-8297-eba48221c7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041135248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3041135248
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3863947697
Short name T504
Test name
Test status
Simulation time 40175146 ps
CPU time 0.99 seconds
Started Jun 10 06:23:12 PM PDT 24
Finished Jun 10 06:23:13 PM PDT 24
Peak memory 196780 kb
Host smart-579096e7-a0cb-41ca-9ec0-f1698e6b1878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863947697 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3863947697
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.720915563
Short name T100
Test name
Test status
Simulation time 14115533 ps
CPU time 0.56 seconds
Started Jun 10 06:23:00 PM PDT 24
Finished Jun 10 06:23:00 PM PDT 24
Peak memory 182748 kb
Host smart-349b1089-78e6-47c7-927f-131a477c7132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720915563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.720915563
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2948127372
Short name T522
Test name
Test status
Simulation time 13576170 ps
CPU time 0.55 seconds
Started Jun 10 06:23:00 PM PDT 24
Finished Jun 10 06:23:01 PM PDT 24
Peak memory 182064 kb
Host smart-c67c2564-0b76-48cf-8984-be0a96a12167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948127372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2948127372
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3976176737
Short name T43
Test name
Test status
Simulation time 29016890 ps
CPU time 0.76 seconds
Started Jun 10 06:23:02 PM PDT 24
Finished Jun 10 06:23:03 PM PDT 24
Peak memory 192972 kb
Host smart-a00769c6-f770-40ff-956b-cebed8a3ba14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976176737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3976176737
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2354909703
Short name T556
Test name
Test status
Simulation time 113057911 ps
CPU time 1.6 seconds
Started Jun 10 06:23:01 PM PDT 24
Finished Jun 10 06:23:03 PM PDT 24
Peak memory 197664 kb
Host smart-cebcaba2-67b2-4d5b-8699-d442ec786163
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354909703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2354909703
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.88191240
Short name T584
Test name
Test status
Simulation time 676023804 ps
CPU time 1.42 seconds
Started Jun 10 06:23:02 PM PDT 24
Finished Jun 10 06:23:04 PM PDT 24
Peak memory 194528 kb
Host smart-d4b12e66-23e2-447a-99f4-b6c379c24ded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88191240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_int
g_err.88191240
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4011696076
Short name T561
Test name
Test status
Simulation time 130323489 ps
CPU time 1.43 seconds
Started Jun 10 06:23:03 PM PDT 24
Finished Jun 10 06:23:05 PM PDT 24
Peak memory 197596 kb
Host smart-d38060f7-e2a0-4eb7-ac39-5676ec26c53b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011696076 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4011696076
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2929821509
Short name T32
Test name
Test status
Simulation time 13423270 ps
CPU time 0.6 seconds
Started Jun 10 06:23:00 PM PDT 24
Finished Jun 10 06:23:01 PM PDT 24
Peak memory 182744 kb
Host smart-ffd08b06-9818-4933-a88b-87cdb4562ac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929821509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2929821509
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3863546166
Short name T456
Test name
Test status
Simulation time 14982775 ps
CPU time 0.57 seconds
Started Jun 10 06:23:01 PM PDT 24
Finished Jun 10 06:23:02 PM PDT 24
Peak memory 182640 kb
Host smart-3fa93ab7-bd7c-48d4-ad47-5cd6d9c795db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863546166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3863546166
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.505263698
Short name T103
Test name
Test status
Simulation time 38190508 ps
CPU time 0.65 seconds
Started Jun 10 06:23:05 PM PDT 24
Finished Jun 10 06:23:05 PM PDT 24
Peak memory 192168 kb
Host smart-83392400-828b-4b42-a5c0-3a83c38f53d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505263698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.505263698
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.919621358
Short name T488
Test name
Test status
Simulation time 188861353 ps
CPU time 1.82 seconds
Started Jun 10 06:23:00 PM PDT 24
Finished Jun 10 06:23:03 PM PDT 24
Peak memory 197688 kb
Host smart-554d9105-b782-4a00-a188-3e5477503e50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919621358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.919621358
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2348310071
Short name T551
Test name
Test status
Simulation time 47733087 ps
CPU time 0.88 seconds
Started Jun 10 06:23:01 PM PDT 24
Finished Jun 10 06:23:03 PM PDT 24
Peak memory 193348 kb
Host smart-d598be5a-4da0-4622-9d49-967750061c22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348310071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2348310071
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.332691917
Short name T81
Test name
Test status
Simulation time 25643104 ps
CPU time 0.73 seconds
Started Jun 10 06:22:03 PM PDT 24
Finished Jun 10 06:22:05 PM PDT 24
Peak memory 192408 kb
Host smart-3eae9a83-0409-42b1-b23c-49b488045523
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332691917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.332691917
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1701682654
Short name T508
Test name
Test status
Simulation time 1061245563 ps
CPU time 3.64 seconds
Started Jun 10 06:22:03 PM PDT 24
Finished Jun 10 06:22:07 PM PDT 24
Peak memory 191064 kb
Host smart-91557a93-01af-4904-869d-652ff78a8f8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701682654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1701682654
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.825619072
Short name T583
Test name
Test status
Simulation time 13415457 ps
CPU time 0.56 seconds
Started Jun 10 06:22:03 PM PDT 24
Finished Jun 10 06:22:03 PM PDT 24
Peak memory 182336 kb
Host smart-30cafde1-ba92-4533-80e0-3d10103f58aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825619072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.825619072
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2620687135
Short name T465
Test name
Test status
Simulation time 159755202 ps
CPU time 0.86 seconds
Started Jun 10 06:22:06 PM PDT 24
Finished Jun 10 06:22:07 PM PDT 24
Peak memory 196632 kb
Host smart-7be9e0f8-faaa-4bee-ab93-755ef682a65f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620687135 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2620687135
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3634836885
Short name T94
Test name
Test status
Simulation time 21321955 ps
CPU time 0.64 seconds
Started Jun 10 06:22:01 PM PDT 24
Finished Jun 10 06:22:02 PM PDT 24
Peak memory 182748 kb
Host smart-09978139-a682-4f53-8d19-38d49d52c1f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634836885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3634836885
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3296533037
Short name T523
Test name
Test status
Simulation time 26679633 ps
CPU time 0.57 seconds
Started Jun 10 06:22:03 PM PDT 24
Finished Jun 10 06:22:04 PM PDT 24
Peak memory 182568 kb
Host smart-f00680d2-67ef-497a-a630-ec0f3d0ea2f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296533037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3296533037
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3594130328
Short name T509
Test name
Test status
Simulation time 33977719 ps
CPU time 0.83 seconds
Started Jun 10 06:22:07 PM PDT 24
Finished Jun 10 06:22:08 PM PDT 24
Peak memory 193468 kb
Host smart-41ef0871-55a4-4b87-8ee1-2d16a87c5c4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594130328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3594130328
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2655872933
Short name T503
Test name
Test status
Simulation time 308496218 ps
CPU time 1.82 seconds
Started Jun 10 06:22:02 PM PDT 24
Finished Jun 10 06:22:04 PM PDT 24
Peak memory 197584 kb
Host smart-9caa220a-8a7d-4e63-9941-a880ae529af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655872933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2655872933
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2605665300
Short name T110
Test name
Test status
Simulation time 1143518171 ps
CPU time 1.39 seconds
Started Jun 10 06:22:03 PM PDT 24
Finished Jun 10 06:22:04 PM PDT 24
Peak memory 195268 kb
Host smart-b64b615c-b530-493a-9a3a-3013f4367dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605665300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2605665300
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1464471568
Short name T475
Test name
Test status
Simulation time 41016709 ps
CPU time 0.54 seconds
Started Jun 10 06:23:04 PM PDT 24
Finished Jun 10 06:23:05 PM PDT 24
Peak memory 182084 kb
Host smart-efc484aa-502d-4945-be8b-f21e01a70406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464471568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1464471568
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.622928911
Short name T565
Test name
Test status
Simulation time 48975344 ps
CPU time 0.58 seconds
Started Jun 10 06:23:05 PM PDT 24
Finished Jun 10 06:23:06 PM PDT 24
Peak memory 182664 kb
Host smart-b6c6842c-de26-47fa-ae48-643f6104bd58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622928911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.622928911
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.953328503
Short name T507
Test name
Test status
Simulation time 27624330 ps
CPU time 0.56 seconds
Started Jun 10 06:23:03 PM PDT 24
Finished Jun 10 06:23:04 PM PDT 24
Peak memory 182636 kb
Host smart-ee762221-8fe2-4cbc-89b6-2d83da347ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953328503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.953328503
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3922640650
Short name T467
Test name
Test status
Simulation time 53258019 ps
CPU time 0.53 seconds
Started Jun 10 06:23:07 PM PDT 24
Finished Jun 10 06:23:08 PM PDT 24
Peak memory 182572 kb
Host smart-840692a1-ff18-489c-b416-7864a5d3e6f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922640650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3922640650
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1173078638
Short name T549
Test name
Test status
Simulation time 19582729 ps
CPU time 0.54 seconds
Started Jun 10 06:23:07 PM PDT 24
Finished Jun 10 06:23:07 PM PDT 24
Peak memory 182080 kb
Host smart-8c2333cd-0708-4831-85ba-c59d73e356fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173078638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1173078638
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3897004930
Short name T474
Test name
Test status
Simulation time 56480986 ps
CPU time 0.57 seconds
Started Jun 10 06:23:08 PM PDT 24
Finished Jun 10 06:23:09 PM PDT 24
Peak memory 182656 kb
Host smart-28a3502b-103a-4a87-93f9-4f704af89a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897004930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3897004930
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.316787537
Short name T460
Test name
Test status
Simulation time 15828737 ps
CPU time 0.54 seconds
Started Jun 10 06:23:09 PM PDT 24
Finished Jun 10 06:23:09 PM PDT 24
Peak memory 182132 kb
Host smart-ec0501f7-44e8-4ebc-8e00-ebcc3acd99f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316787537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.316787537
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3764620677
Short name T562
Test name
Test status
Simulation time 16702410 ps
CPU time 0.58 seconds
Started Jun 10 06:23:09 PM PDT 24
Finished Jun 10 06:23:10 PM PDT 24
Peak memory 182548 kb
Host smart-6b8bde22-4361-4796-9bf5-5a71ab7562f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764620677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3764620677
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.630187156
Short name T510
Test name
Test status
Simulation time 28388141 ps
CPU time 0.58 seconds
Started Jun 10 06:23:10 PM PDT 24
Finished Jun 10 06:23:11 PM PDT 24
Peak memory 182652 kb
Host smart-5ffd877e-4b77-40e7-b0b5-3f29d280d482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630187156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.630187156
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2205238778
Short name T485
Test name
Test status
Simulation time 49001401 ps
CPU time 0.55 seconds
Started Jun 10 06:23:08 PM PDT 24
Finished Jun 10 06:23:08 PM PDT 24
Peak memory 182096 kb
Host smart-14710bfb-3c28-4aba-8323-62a9f2d17c09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205238778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2205238778
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3227107504
Short name T500
Test name
Test status
Simulation time 26538473 ps
CPU time 0.61 seconds
Started Jun 10 06:22:11 PM PDT 24
Finished Jun 10 06:22:12 PM PDT 24
Peak memory 182708 kb
Host smart-6d6393fa-a35f-45bf-983c-f2b3f8ec377f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227107504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3227107504
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.169396520
Short name T576
Test name
Test status
Simulation time 191843849 ps
CPU time 2.54 seconds
Started Jun 10 06:22:09 PM PDT 24
Finished Jun 10 06:22:12 PM PDT 24
Peak memory 191168 kb
Host smart-729075a5-cd27-4dab-af6a-427ece154030
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169396520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.169396520
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2267923294
Short name T108
Test name
Test status
Simulation time 53088395 ps
CPU time 0.61 seconds
Started Jun 10 06:22:11 PM PDT 24
Finished Jun 10 06:22:12 PM PDT 24
Peak memory 182744 kb
Host smart-bab84e33-e452-440b-8c1f-b80c92d81816
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267923294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2267923294
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2999913553
Short name T473
Test name
Test status
Simulation time 31729285 ps
CPU time 0.73 seconds
Started Jun 10 06:22:12 PM PDT 24
Finished Jun 10 06:22:12 PM PDT 24
Peak memory 195544 kb
Host smart-2e6f07cc-b2ff-4bb2-98ee-4068d3c9d3fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999913553 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2999913553
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1849888925
Short name T79
Test name
Test status
Simulation time 12621366 ps
CPU time 0.57 seconds
Started Jun 10 06:22:09 PM PDT 24
Finished Jun 10 06:22:09 PM PDT 24
Peak memory 182736 kb
Host smart-d0eaf7da-9edf-4207-8e10-e93f559191b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849888925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1849888925
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.480214832
Short name T528
Test name
Test status
Simulation time 54423650 ps
CPU time 0.53 seconds
Started Jun 10 06:22:06 PM PDT 24
Finished Jun 10 06:22:07 PM PDT 24
Peak memory 182660 kb
Host smart-c5c000ec-ea38-45f4-9ec4-6a6b483a0c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480214832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.480214832
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1687643414
Short name T104
Test name
Test status
Simulation time 36436894 ps
CPU time 0.77 seconds
Started Jun 10 06:22:15 PM PDT 24
Finished Jun 10 06:22:16 PM PDT 24
Peak memory 193340 kb
Host smart-94e2915a-d4cb-4874-989c-f381ac84b86f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687643414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1687643414
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1095198509
Short name T530
Test name
Test status
Simulation time 74863669 ps
CPU time 1.58 seconds
Started Jun 10 06:22:07 PM PDT 24
Finished Jun 10 06:22:08 PM PDT 24
Peak memory 197644 kb
Host smart-403c03b0-1c6e-424b-8163-c319fb8491f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095198509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1095198509
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1950460693
Short name T112
Test name
Test status
Simulation time 360005579 ps
CPU time 1.34 seconds
Started Jun 10 06:22:09 PM PDT 24
Finished Jun 10 06:22:10 PM PDT 24
Peak memory 183552 kb
Host smart-7af38478-4d14-472c-a7aa-d46376ef2476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950460693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1950460693
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2279733568
Short name T471
Test name
Test status
Simulation time 15158216 ps
CPU time 0.58 seconds
Started Jun 10 06:23:10 PM PDT 24
Finished Jun 10 06:23:11 PM PDT 24
Peak memory 182664 kb
Host smart-08f8089b-25ab-4d82-abde-84946c7c0f59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279733568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2279733568
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.563712792
Short name T459
Test name
Test status
Simulation time 51636470 ps
CPU time 0.53 seconds
Started Jun 10 06:23:09 PM PDT 24
Finished Jun 10 06:23:10 PM PDT 24
Peak memory 182084 kb
Host smart-576b3369-8d96-4138-baa4-aecca5748cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563712792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.563712792
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1178943596
Short name T479
Test name
Test status
Simulation time 55414035 ps
CPU time 0.55 seconds
Started Jun 10 06:23:08 PM PDT 24
Finished Jun 10 06:23:09 PM PDT 24
Peak memory 182660 kb
Host smart-031a9c94-8589-4c69-9de3-a7646d3dc59d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178943596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1178943596
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2601921505
Short name T559
Test name
Test status
Simulation time 12541301 ps
CPU time 0.52 seconds
Started Jun 10 06:23:15 PM PDT 24
Finished Jun 10 06:23:16 PM PDT 24
Peak memory 182672 kb
Host smart-45ca5b59-8a99-40ef-b9d6-23d9928a8a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601921505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2601921505
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1037742204
Short name T486
Test name
Test status
Simulation time 19286689 ps
CPU time 0.52 seconds
Started Jun 10 06:23:13 PM PDT 24
Finished Jun 10 06:23:14 PM PDT 24
Peak memory 182336 kb
Host smart-3ec2e68e-084a-453c-95d8-abda3876105d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037742204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1037742204
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2399609053
Short name T463
Test name
Test status
Simulation time 12796436 ps
CPU time 0.55 seconds
Started Jun 10 06:23:15 PM PDT 24
Finished Jun 10 06:23:15 PM PDT 24
Peak memory 182100 kb
Host smart-5634f31f-db87-48cd-88ef-1efe03edad11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399609053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2399609053
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2287206928
Short name T524
Test name
Test status
Simulation time 38491695 ps
CPU time 0.53 seconds
Started Jun 10 06:23:13 PM PDT 24
Finished Jun 10 06:23:13 PM PDT 24
Peak memory 182088 kb
Host smart-68e5fa8f-14bd-41b7-b433-fde09907a206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287206928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2287206928
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3228190411
Short name T541
Test name
Test status
Simulation time 31943160 ps
CPU time 0.52 seconds
Started Jun 10 06:23:11 PM PDT 24
Finished Jun 10 06:23:12 PM PDT 24
Peak memory 182112 kb
Host smart-6712f60b-05ac-4fff-918f-e22e1ea628fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228190411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3228190411
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1876259609
Short name T502
Test name
Test status
Simulation time 16983733 ps
CPU time 0.56 seconds
Started Jun 10 06:23:13 PM PDT 24
Finished Jun 10 06:23:14 PM PDT 24
Peak memory 182552 kb
Host smart-5ed3e2eb-4bc9-4b2d-97c3-3e0003619a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876259609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1876259609
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2980104020
Short name T461
Test name
Test status
Simulation time 31640840 ps
CPU time 0.55 seconds
Started Jun 10 06:23:13 PM PDT 24
Finished Jun 10 06:23:14 PM PDT 24
Peak memory 182580 kb
Host smart-d1639fc6-3d95-4167-9f88-204bc8cbbda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980104020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2980104020
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3467882705
Short name T557
Test name
Test status
Simulation time 30792936 ps
CPU time 0.76 seconds
Started Jun 10 06:22:20 PM PDT 24
Finished Jun 10 06:22:21 PM PDT 24
Peak memory 182760 kb
Host smart-ebd06bd0-0c6b-4c69-9358-4ad08f2b3df9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467882705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3467882705
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3709319824
Short name T489
Test name
Test status
Simulation time 195231227 ps
CPU time 2.68 seconds
Started Jun 10 06:22:18 PM PDT 24
Finished Jun 10 06:22:21 PM PDT 24
Peak memory 191164 kb
Host smart-eef27070-711b-49b3-9a94-694b873d4ad4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709319824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3709319824
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2197613176
Short name T582
Test name
Test status
Simulation time 31554924 ps
CPU time 0.57 seconds
Started Jun 10 06:22:17 PM PDT 24
Finished Jun 10 06:22:18 PM PDT 24
Peak memory 182752 kb
Host smart-bf111aa2-1058-448f-8a89-f4f2aa635a74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197613176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2197613176
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.266251875
Short name T544
Test name
Test status
Simulation time 110167048 ps
CPU time 0.67 seconds
Started Jun 10 06:22:24 PM PDT 24
Finished Jun 10 06:22:25 PM PDT 24
Peak memory 194420 kb
Host smart-7239d08e-0c7b-4cf2-956c-4fb39081ba26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266251875 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.266251875
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1545072844
Short name T567
Test name
Test status
Simulation time 53548947 ps
CPU time 0.59 seconds
Started Jun 10 06:22:18 PM PDT 24
Finished Jun 10 06:22:19 PM PDT 24
Peak memory 182768 kb
Host smart-6e0479b9-cf93-4dcc-94a2-43e8e2f4bc56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545072844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1545072844
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3775781643
Short name T533
Test name
Test status
Simulation time 16333570 ps
CPU time 0.55 seconds
Started Jun 10 06:22:19 PM PDT 24
Finished Jun 10 06:22:20 PM PDT 24
Peak memory 182708 kb
Host smart-aeff3662-a409-4723-80da-46648c740614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775781643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3775781643
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4099178965
Short name T537
Test name
Test status
Simulation time 48928772 ps
CPU time 0.6 seconds
Started Jun 10 06:22:24 PM PDT 24
Finished Jun 10 06:22:25 PM PDT 24
Peak memory 191416 kb
Host smart-29422fb2-8c35-4e04-ab10-475bb88e7f19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099178965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.4099178965
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.548487198
Short name T499
Test name
Test status
Simulation time 223357880 ps
CPU time 2.9 seconds
Started Jun 10 06:22:14 PM PDT 24
Finished Jun 10 06:22:17 PM PDT 24
Peak memory 197568 kb
Host smart-7238180a-4327-4063-81de-f24d84ed7e28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548487198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.548487198
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3191627058
Short name T41
Test name
Test status
Simulation time 1280664608 ps
CPU time 1.11 seconds
Started Jun 10 06:22:14 PM PDT 24
Finished Jun 10 06:22:15 PM PDT 24
Peak memory 195220 kb
Host smart-549dcee7-8dc2-465f-bdcc-c199fd1b9947
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191627058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3191627058
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1479716915
Short name T511
Test name
Test status
Simulation time 24846730 ps
CPU time 0.53 seconds
Started Jun 10 06:23:12 PM PDT 24
Finished Jun 10 06:23:13 PM PDT 24
Peak memory 182232 kb
Host smart-654a9920-2c7e-4c72-96e4-5ec5a9b69415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479716915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1479716915
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1564597492
Short name T531
Test name
Test status
Simulation time 65733036 ps
CPU time 0.55 seconds
Started Jun 10 06:23:12 PM PDT 24
Finished Jun 10 06:23:13 PM PDT 24
Peak memory 182628 kb
Host smart-1eaadbf7-d39c-437a-85bb-7f773e3fc90a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564597492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1564597492
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2395144795
Short name T494
Test name
Test status
Simulation time 14205684 ps
CPU time 0.55 seconds
Started Jun 10 06:23:13 PM PDT 24
Finished Jun 10 06:23:14 PM PDT 24
Peak memory 182024 kb
Host smart-05843749-0082-48c7-ae10-c191bf1ba15d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395144795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2395144795
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4039330974
Short name T497
Test name
Test status
Simulation time 62589474 ps
CPU time 0.55 seconds
Started Jun 10 06:23:14 PM PDT 24
Finished Jun 10 06:23:15 PM PDT 24
Peak memory 182596 kb
Host smart-10f6bf8c-62cc-413e-94c9-16f424edce90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039330974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4039330974
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.427234605
Short name T476
Test name
Test status
Simulation time 25876262 ps
CPU time 0.55 seconds
Started Jun 10 06:23:15 PM PDT 24
Finished Jun 10 06:23:16 PM PDT 24
Peak memory 182308 kb
Host smart-132fd51e-d8a5-44de-b4c5-cb9746638357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427234605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.427234605
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.355461450
Short name T492
Test name
Test status
Simulation time 11857970 ps
CPU time 0.54 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:23:17 PM PDT 24
Peak memory 182104 kb
Host smart-d2e3b6a3-8335-4ca6-b98f-a92d1e4bf1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355461450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.355461450
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.418872835
Short name T518
Test name
Test status
Simulation time 12643294 ps
CPU time 0.57 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:23:17 PM PDT 24
Peak memory 182640 kb
Host smart-2d1ed134-5ff6-438f-a253-299d5c75abe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418872835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.418872835
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1415361577
Short name T560
Test name
Test status
Simulation time 23836545 ps
CPU time 0.55 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:23:17 PM PDT 24
Peak memory 182080 kb
Host smart-a45e093b-3310-4b32-bc22-4c14a16ea315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415361577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1415361577
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4223418392
Short name T458
Test name
Test status
Simulation time 28197247 ps
CPU time 0.54 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:23:17 PM PDT 24
Peak memory 182636 kb
Host smart-3f4464d8-7a3f-41b9-a31b-a7e17f145da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223418392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4223418392
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.684559818
Short name T491
Test name
Test status
Simulation time 23422756 ps
CPU time 0.56 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:23:17 PM PDT 24
Peak memory 182624 kb
Host smart-dde9b0cb-a5c3-4cda-9969-9b8bf38520e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684559818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.684559818
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.163667649
Short name T536
Test name
Test status
Simulation time 67699987 ps
CPU time 1.05 seconds
Started Jun 10 06:22:26 PM PDT 24
Finished Jun 10 06:22:28 PM PDT 24
Peak memory 197452 kb
Host smart-b5301320-4dc4-4d00-9ece-9554f05137e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163667649 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.163667649
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.61959980
Short name T520
Test name
Test status
Simulation time 31068798 ps
CPU time 0.59 seconds
Started Jun 10 06:22:22 PM PDT 24
Finished Jun 10 06:22:23 PM PDT 24
Peak memory 182756 kb
Host smart-bc3258e7-0e29-42a0-8613-ae19a170db2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61959980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.61959980
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.517614762
Short name T455
Test name
Test status
Simulation time 15978529 ps
CPU time 0.58 seconds
Started Jun 10 06:22:24 PM PDT 24
Finished Jun 10 06:22:24 PM PDT 24
Peak memory 182584 kb
Host smart-84aaad36-b729-4438-8591-b023ed38f429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517614762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.517614762
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.666438228
Short name T106
Test name
Test status
Simulation time 32555839 ps
CPU time 0.6 seconds
Started Jun 10 06:22:21 PM PDT 24
Finished Jun 10 06:22:21 PM PDT 24
Peak memory 192052 kb
Host smart-12de917d-11f9-4a51-a855-c30a11ce63d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666438228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.666438228
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3279904108
Short name T477
Test name
Test status
Simulation time 126175036 ps
CPU time 1.16 seconds
Started Jun 10 06:22:22 PM PDT 24
Finished Jun 10 06:22:23 PM PDT 24
Peak memory 197648 kb
Host smart-87281c05-8534-454a-93c1-74bd3cdf0717
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279904108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3279904108
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1913949588
Short name T521
Test name
Test status
Simulation time 378708531 ps
CPU time 0.8 seconds
Started Jun 10 06:22:23 PM PDT 24
Finished Jun 10 06:22:24 PM PDT 24
Peak memory 193720 kb
Host smart-0969ef6b-7d37-40d0-ba6c-f85e30849cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913949588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1913949588
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2649476647
Short name T525
Test name
Test status
Simulation time 150877312 ps
CPU time 0.95 seconds
Started Jun 10 06:22:30 PM PDT 24
Finished Jun 10 06:22:31 PM PDT 24
Peak memory 196292 kb
Host smart-bd1a69a0-e3ac-4a25-9db9-dc678ef4a27e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649476647 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2649476647
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3573879457
Short name T97
Test name
Test status
Simulation time 12280359 ps
CPU time 0.57 seconds
Started Jun 10 06:22:27 PM PDT 24
Finished Jun 10 06:22:28 PM PDT 24
Peak memory 182472 kb
Host smart-4e3e3566-2b5e-4b7d-8b96-56ce05535b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573879457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3573879457
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3079900167
Short name T516
Test name
Test status
Simulation time 14156642 ps
CPU time 0.65 seconds
Started Jun 10 06:22:26 PM PDT 24
Finished Jun 10 06:22:27 PM PDT 24
Peak memory 182084 kb
Host smart-e3783aba-745d-4607-8d9f-924e0a846490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079900167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3079900167
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3718785333
Short name T545
Test name
Test status
Simulation time 170145030 ps
CPU time 0.8 seconds
Started Jun 10 06:22:28 PM PDT 24
Finished Jun 10 06:22:29 PM PDT 24
Peak memory 191792 kb
Host smart-907f7725-58e4-47a0-be44-efa1e20672ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718785333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3718785333
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4294434033
Short name T457
Test name
Test status
Simulation time 34954612 ps
CPU time 1.67 seconds
Started Jun 10 06:22:26 PM PDT 24
Finished Jun 10 06:22:28 PM PDT 24
Peak memory 197632 kb
Host smart-04f5b1df-f537-4104-b3f7-8e217e4fc3db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294434033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4294434033
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1175449808
Short name T481
Test name
Test status
Simulation time 69317571 ps
CPU time 1.11 seconds
Started Jun 10 06:22:26 PM PDT 24
Finished Jun 10 06:22:27 PM PDT 24
Peak memory 194304 kb
Host smart-94fce59f-a588-48e1-bdb3-c5144a7c9727
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175449808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1175449808
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2045552533
Short name T578
Test name
Test status
Simulation time 86868432 ps
CPU time 1.02 seconds
Started Jun 10 06:22:34 PM PDT 24
Finished Jun 10 06:22:35 PM PDT 24
Peak memory 197456 kb
Host smart-164fe010-6c5e-41bd-8196-c01c06e1e056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045552533 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2045552533
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.852124130
Short name T574
Test name
Test status
Simulation time 98737056 ps
CPU time 0.57 seconds
Started Jun 10 06:22:28 PM PDT 24
Finished Jun 10 06:22:29 PM PDT 24
Peak memory 182740 kb
Host smart-7411f9d4-5003-4aea-8373-32716f751324
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852124130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.852124130
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1644229447
Short name T555
Test name
Test status
Simulation time 27507998 ps
CPU time 0.53 seconds
Started Jun 10 06:22:29 PM PDT 24
Finished Jun 10 06:22:30 PM PDT 24
Peak memory 182108 kb
Host smart-98bec1e6-228e-41f0-8bb5-0eed967453e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644229447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1644229447
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2288129012
Short name T105
Test name
Test status
Simulation time 55013376 ps
CPU time 0.76 seconds
Started Jun 10 06:22:35 PM PDT 24
Finished Jun 10 06:22:36 PM PDT 24
Peak memory 193540 kb
Host smart-1221b3fe-db38-4fbe-ad0b-3ee2a8d6409e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288129012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2288129012
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4208111183
Short name T539
Test name
Test status
Simulation time 113772798 ps
CPU time 1.98 seconds
Started Jun 10 06:22:32 PM PDT 24
Finished Jun 10 06:22:34 PM PDT 24
Peak memory 197652 kb
Host smart-1f0f6587-66a1-4578-8501-4ecb9e625359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208111183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4208111183
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3828952525
Short name T109
Test name
Test status
Simulation time 136590758 ps
CPU time 1.34 seconds
Started Jun 10 06:22:30 PM PDT 24
Finished Jun 10 06:22:32 PM PDT 24
Peak memory 195452 kb
Host smart-fb766be2-e8b7-4aaf-8cc6-0aa0c3ea4980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828952525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3828952525
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1695402678
Short name T493
Test name
Test status
Simulation time 53257091 ps
CPU time 0.7 seconds
Started Jun 10 06:22:33 PM PDT 24
Finished Jun 10 06:22:34 PM PDT 24
Peak memory 194960 kb
Host smart-f325748e-2c8d-44a8-be1b-681807320f70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695402678 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1695402678
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4067869221
Short name T487
Test name
Test status
Simulation time 12691388 ps
CPU time 0.53 seconds
Started Jun 10 06:22:36 PM PDT 24
Finished Jun 10 06:22:37 PM PDT 24
Peak memory 182548 kb
Host smart-0de72cc5-b64d-45bc-b363-b1c202a17a21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067869221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4067869221
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4218988553
Short name T513
Test name
Test status
Simulation time 13790222 ps
CPU time 0.56 seconds
Started Jun 10 06:22:42 PM PDT 24
Finished Jun 10 06:22:43 PM PDT 24
Peak memory 182592 kb
Host smart-b2edb030-205d-4992-aa95-19e3f7f3a4ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218988553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4218988553
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1039978409
Short name T580
Test name
Test status
Simulation time 31207104 ps
CPU time 0.59 seconds
Started Jun 10 06:22:42 PM PDT 24
Finished Jun 10 06:22:43 PM PDT 24
Peak memory 191536 kb
Host smart-79a2302d-6804-4ec0-9a16-2bc48c1ae113
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039978409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1039978409
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3272586532
Short name T496
Test name
Test status
Simulation time 73997067 ps
CPU time 1.41 seconds
Started Jun 10 06:22:36 PM PDT 24
Finished Jun 10 06:22:38 PM PDT 24
Peak memory 197656 kb
Host smart-8fc511c5-c9d6-4812-ab64-614b45651dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272586532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3272586532
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3088072207
Short name T550
Test name
Test status
Simulation time 203152608 ps
CPU time 1.11 seconds
Started Jun 10 06:22:34 PM PDT 24
Finished Jun 10 06:22:36 PM PDT 24
Peak memory 183460 kb
Host smart-9a43f4d1-6dd6-4f2c-9a63-45dc9d814639
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088072207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3088072207
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.776554885
Short name T568
Test name
Test status
Simulation time 103859523 ps
CPU time 0.87 seconds
Started Jun 10 06:22:38 PM PDT 24
Finished Jun 10 06:22:39 PM PDT 24
Peak memory 196384 kb
Host smart-418b2ac1-dd21-4916-a163-2a8579a61d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776554885 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.776554885
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3269576880
Short name T93
Test name
Test status
Simulation time 32697631 ps
CPU time 0.57 seconds
Started Jun 10 06:22:34 PM PDT 24
Finished Jun 10 06:22:35 PM PDT 24
Peak memory 182744 kb
Host smart-c917597c-4aeb-4ce1-9db7-d188dda24fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269576880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3269576880
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.383345618
Short name T570
Test name
Test status
Simulation time 59440977 ps
CPU time 0.55 seconds
Started Jun 10 06:22:33 PM PDT 24
Finished Jun 10 06:22:33 PM PDT 24
Peak memory 182236 kb
Host smart-d3f79c69-64dc-4511-b522-f3244d41a85c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383345618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.383345618
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.272507332
Short name T581
Test name
Test status
Simulation time 59860157 ps
CPU time 0.82 seconds
Started Jun 10 06:22:42 PM PDT 24
Finished Jun 10 06:22:43 PM PDT 24
Peak memory 193452 kb
Host smart-d1fe95a9-7e3d-44fd-8010-ddc94af50771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272507332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.272507332
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2056355687
Short name T546
Test name
Test status
Simulation time 194053314 ps
CPU time 1.29 seconds
Started Jun 10 06:22:42 PM PDT 24
Finished Jun 10 06:22:44 PM PDT 24
Peak memory 197496 kb
Host smart-ab1dbfc8-6ffc-4ca9-8468-fc756aaa0e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056355687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2056355687
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3931889313
Short name T517
Test name
Test status
Simulation time 140827712 ps
CPU time 0.81 seconds
Started Jun 10 06:22:33 PM PDT 24
Finished Jun 10 06:22:34 PM PDT 24
Peak memory 193952 kb
Host smart-4f28ee0b-7f8c-4a03-81a2-757c86f924f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931889313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3931889313
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.474611028
Short name T296
Test name
Test status
Simulation time 436936707928 ps
CPU time 255.28 seconds
Started Jun 10 06:23:17 PM PDT 24
Finished Jun 10 06:27:33 PM PDT 24
Peak memory 183028 kb
Host smart-44b68234-8237-480f-a62c-16f42ab585ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474611028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.474611028
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2052450091
Short name T379
Test name
Test status
Simulation time 13610493078 ps
CPU time 19.93 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:23:37 PM PDT 24
Peak memory 183060 kb
Host smart-2a820a5a-08a6-4a0d-84ac-76fa09699350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052450091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2052450091
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2300406510
Short name T158
Test name
Test status
Simulation time 140938751579 ps
CPU time 379.58 seconds
Started Jun 10 06:23:18 PM PDT 24
Finished Jun 10 06:29:38 PM PDT 24
Peak memory 191256 kb
Host smart-46f1dec3-15fc-4038-a17e-bc5a559a47c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300406510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2300406510
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2069319594
Short name T123
Test name
Test status
Simulation time 142606474407 ps
CPU time 1564.03 seconds
Started Jun 10 06:23:19 PM PDT 24
Finished Jun 10 06:49:23 PM PDT 24
Peak memory 191256 kb
Host smart-858dc142-a890-4d3f-88e1-22f0d6dedfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069319594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2069319594
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2712770101
Short name T19
Test name
Test status
Simulation time 195913083 ps
CPU time 0.75 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:23:17 PM PDT 24
Peak memory 214108 kb
Host smart-5e7717a2-e5bc-4458-a969-7270b955a624
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712770101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2712770101
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2325077508
Short name T322
Test name
Test status
Simulation time 381855768663 ps
CPU time 658.37 seconds
Started Jun 10 06:23:18 PM PDT 24
Finished Jun 10 06:34:17 PM PDT 24
Peak memory 183056 kb
Host smart-7b28cb6a-f52f-4209-8ac9-a7ea7aff89c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325077508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2325077508
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2726675661
Short name T384
Test name
Test status
Simulation time 11555225247 ps
CPU time 9.68 seconds
Started Jun 10 06:23:16 PM PDT 24
Finished Jun 10 06:23:26 PM PDT 24
Peak memory 183052 kb
Host smart-41b21428-c9b2-410b-90fd-1809b3dca515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726675661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2726675661
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2564215206
Short name T368
Test name
Test status
Simulation time 153699100 ps
CPU time 0.56 seconds
Started Jun 10 06:23:19 PM PDT 24
Finished Jun 10 06:23:20 PM PDT 24
Peak memory 182812 kb
Host smart-a51d8a43-ed97-46bb-b0c0-3fc32a70c35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564215206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2564215206
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2278497197
Short name T209
Test name
Test status
Simulation time 1299371145683 ps
CPU time 665.55 seconds
Started Jun 10 06:23:21 PM PDT 24
Finished Jun 10 06:34:27 PM PDT 24
Peak memory 191100 kb
Host smart-c4f4d58d-c97f-4de3-877a-af78fc90bd04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278497197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2278497197
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.302689723
Short name T436
Test name
Test status
Simulation time 121351554046 ps
CPU time 170.1 seconds
Started Jun 10 06:23:41 PM PDT 24
Finished Jun 10 06:26:32 PM PDT 24
Peak memory 183008 kb
Host smart-647e88ac-3124-40e5-a957-41205ba55c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302689723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.302689723
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.4019499097
Short name T257
Test name
Test status
Simulation time 43390024662 ps
CPU time 176.58 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:26:48 PM PDT 24
Peak memory 183080 kb
Host smart-ed1a7e9b-7247-4c6b-88a4-57a9c7129bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019499097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.4019499097
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1252797534
Short name T412
Test name
Test status
Simulation time 817344268 ps
CPU time 1.68 seconds
Started Jun 10 06:23:44 PM PDT 24
Finished Jun 10 06:23:46 PM PDT 24
Peak memory 182836 kb
Host smart-da85624b-df9d-4541-8ae1-173ba62bc006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252797534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1252797534
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2566960489
Short name T178
Test name
Test status
Simulation time 1716364526726 ps
CPU time 713.3 seconds
Started Jun 10 06:23:45 PM PDT 24
Finished Jun 10 06:35:39 PM PDT 24
Peak memory 195756 kb
Host smart-1020c51c-8a50-4231-ad6b-c0a51b7fe5c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566960489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2566960489
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.1490419549
Short name T59
Test name
Test status
Simulation time 51282182251 ps
CPU time 223.28 seconds
Started Jun 10 06:27:34 PM PDT 24
Finished Jun 10 06:31:18 PM PDT 24
Peak memory 191284 kb
Host smart-8133769f-bebe-426b-b63e-b59dfc8354a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490419549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1490419549
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3171315270
Short name T285
Test name
Test status
Simulation time 457731525585 ps
CPU time 228.28 seconds
Started Jun 10 06:27:35 PM PDT 24
Finished Jun 10 06:31:24 PM PDT 24
Peak memory 191280 kb
Host smart-5fc61dc1-04bd-4510-9d8e-6aaf1a6b497f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171315270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3171315270
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2138241482
Short name T1
Test name
Test status
Simulation time 26890844715 ps
CPU time 42.41 seconds
Started Jun 10 06:27:39 PM PDT 24
Finished Jun 10 06:28:22 PM PDT 24
Peak memory 183108 kb
Host smart-43ac9e72-1a9e-47ec-9e7d-8145f97439d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138241482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2138241482
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.604645812
Short name T317
Test name
Test status
Simulation time 116635133121 ps
CPU time 46.62 seconds
Started Jun 10 06:27:39 PM PDT 24
Finished Jun 10 06:28:26 PM PDT 24
Peak memory 183084 kb
Host smart-d8047108-8510-4a25-bdc6-85f99bcdce7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604645812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.604645812
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3589048972
Short name T3
Test name
Test status
Simulation time 39725906968 ps
CPU time 213.45 seconds
Started Jun 10 06:27:39 PM PDT 24
Finished Jun 10 06:31:13 PM PDT 24
Peak memory 193880 kb
Host smart-ca3716be-17b1-4210-9e97-9e2718fc07ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589048972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3589048972
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.117059897
Short name T353
Test name
Test status
Simulation time 206656217127 ps
CPU time 703.77 seconds
Started Jun 10 06:27:38 PM PDT 24
Finished Jun 10 06:39:22 PM PDT 24
Peak memory 191228 kb
Host smart-895ccbe0-36ea-41a6-9e12-20cea4552741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117059897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.117059897
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.407678658
Short name T448
Test name
Test status
Simulation time 97226785832 ps
CPU time 170.04 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:26:41 PM PDT 24
Peak memory 183044 kb
Host smart-24a020c3-fdc9-49b1-8d38-265f955f99fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407678658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.407678658
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3721747199
Short name T375
Test name
Test status
Simulation time 201151774859 ps
CPU time 175.13 seconds
Started Jun 10 06:23:44 PM PDT 24
Finished Jun 10 06:26:39 PM PDT 24
Peak memory 183040 kb
Host smart-0ec5111a-797c-4af6-81b0-b55aed7dd816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721747199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3721747199
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3966604108
Short name T348
Test name
Test status
Simulation time 75365176126 ps
CPU time 368.62 seconds
Started Jun 10 06:23:43 PM PDT 24
Finished Jun 10 06:29:52 PM PDT 24
Peak memory 191220 kb
Host smart-bf0abddf-acff-4b98-8dff-41d1b3be3e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966604108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3966604108
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1358955304
Short name T408
Test name
Test status
Simulation time 993546092 ps
CPU time 0.71 seconds
Started Jun 10 06:23:45 PM PDT 24
Finished Jun 10 06:23:46 PM PDT 24
Peak memory 182860 kb
Host smart-f38ed918-d185-4ade-9e51-ec098218ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358955304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1358955304
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.218450455
Short name T255
Test name
Test status
Simulation time 2859211888553 ps
CPU time 1014.23 seconds
Started Jun 10 06:23:44 PM PDT 24
Finished Jun 10 06:40:39 PM PDT 24
Peak memory 191248 kb
Host smart-c14526b8-5f8d-4d35-8505-983e30bac7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218450455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
218450455
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.1676724845
Short name T164
Test name
Test status
Simulation time 255276028940 ps
CPU time 288.32 seconds
Started Jun 10 06:27:44 PM PDT 24
Finished Jun 10 06:32:32 PM PDT 24
Peak memory 191260 kb
Host smart-d9d26ac1-031d-4526-8efc-b92f3e4b65a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676724845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1676724845
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2405273994
Short name T161
Test name
Test status
Simulation time 126872253631 ps
CPU time 346.03 seconds
Started Jun 10 06:27:43 PM PDT 24
Finished Jun 10 06:33:29 PM PDT 24
Peak memory 191252 kb
Host smart-031f81ed-9ed7-4f99-b91a-a5896ad585f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405273994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2405273994
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.916583006
Short name T284
Test name
Test status
Simulation time 293939703938 ps
CPU time 345.5 seconds
Started Jun 10 06:27:46 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 191268 kb
Host smart-b7f3243d-081c-42fa-ab08-85425cc915ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916583006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.916583006
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2394890209
Short name T313
Test name
Test status
Simulation time 19493215403 ps
CPU time 35.4 seconds
Started Jun 10 06:27:47 PM PDT 24
Finished Jun 10 06:28:22 PM PDT 24
Peak memory 191184 kb
Host smart-d53b73c8-c60c-4d23-8e6b-a26320940c43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394890209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2394890209
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3435928341
Short name T115
Test name
Test status
Simulation time 103559585446 ps
CPU time 298.52 seconds
Started Jun 10 06:27:48 PM PDT 24
Finished Jun 10 06:32:47 PM PDT 24
Peak memory 191260 kb
Host smart-b8fb09d9-3968-41f3-91dd-97c2665243ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435928341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3435928341
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1940944714
Short name T401
Test name
Test status
Simulation time 194875962056 ps
CPU time 68.85 seconds
Started Jun 10 06:23:43 PM PDT 24
Finished Jun 10 06:24:52 PM PDT 24
Peak memory 183028 kb
Host smart-2ed46457-5ea3-410e-b512-8127bce595ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940944714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1940944714
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.803179077
Short name T386
Test name
Test status
Simulation time 107068061 ps
CPU time 0.68 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:23:52 PM PDT 24
Peak memory 182820 kb
Host smart-eefb66b5-7624-43da-b649-6571367bd444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803179077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.803179077
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1356829521
Short name T58
Test name
Test status
Simulation time 232816475612 ps
CPU time 182.96 seconds
Started Jun 10 06:23:47 PM PDT 24
Finished Jun 10 06:26:51 PM PDT 24
Peak memory 191276 kb
Host smart-41dcc52e-2a9b-4772-ad5a-531bfe64dd9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356829521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1356829521
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.293224708
Short name T297
Test name
Test status
Simulation time 203663947011 ps
CPU time 408.58 seconds
Started Jun 10 06:27:51 PM PDT 24
Finished Jun 10 06:34:40 PM PDT 24
Peak memory 183068 kb
Host smart-d862ecb4-d9cc-4b2f-ac9d-39d149f9af4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293224708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.293224708
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.720956277
Short name T85
Test name
Test status
Simulation time 404512325881 ps
CPU time 226.85 seconds
Started Jun 10 06:27:53 PM PDT 24
Finished Jun 10 06:31:40 PM PDT 24
Peak memory 191292 kb
Host smart-791ce18b-39a3-4720-a96e-432f61e5cb79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720956277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.720956277
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3102713638
Short name T9
Test name
Test status
Simulation time 53429544899 ps
CPU time 56.44 seconds
Started Jun 10 06:27:58 PM PDT 24
Finished Jun 10 06:28:55 PM PDT 24
Peak memory 183084 kb
Host smart-2a64ccad-6e52-4de3-9e2c-8c09e1f6c39b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102713638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3102713638
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1633779922
Short name T204
Test name
Test status
Simulation time 777958578217 ps
CPU time 565.23 seconds
Started Jun 10 06:27:58 PM PDT 24
Finished Jun 10 06:37:24 PM PDT 24
Peak memory 191280 kb
Host smart-537c0634-17c1-433a-b765-31e714f6a7db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633779922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1633779922
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3078774936
Short name T175
Test name
Test status
Simulation time 9303019337 ps
CPU time 336.79 seconds
Started Jun 10 06:28:03 PM PDT 24
Finished Jun 10 06:33:40 PM PDT 24
Peak memory 183076 kb
Host smart-449a4aa0-8c30-44d2-bfea-345ccb6a734e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078774936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3078774936
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1399440349
Short name T224
Test name
Test status
Simulation time 141351752006 ps
CPU time 147.11 seconds
Started Jun 10 06:28:03 PM PDT 24
Finished Jun 10 06:30:31 PM PDT 24
Peak memory 191284 kb
Host smart-666c381b-e7e2-4692-b260-b77668e4b8b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399440349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1399440349
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4147737362
Short name T207
Test name
Test status
Simulation time 214377172413 ps
CPU time 2158.35 seconds
Started Jun 10 06:28:05 PM PDT 24
Finished Jun 10 07:04:04 PM PDT 24
Peak memory 191260 kb
Host smart-213ee539-037d-4690-9bf9-b5e43c70ebee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147737362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4147737362
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4239552804
Short name T271
Test name
Test status
Simulation time 269057879350 ps
CPU time 433.55 seconds
Started Jun 10 06:23:47 PM PDT 24
Finished Jun 10 06:31:01 PM PDT 24
Peak memory 183100 kb
Host smart-b6334848-2d31-46b1-96c9-331e4438febd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239552804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4239552804
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.548088264
Short name T389
Test name
Test status
Simulation time 118346799241 ps
CPU time 158.05 seconds
Started Jun 10 06:23:48 PM PDT 24
Finished Jun 10 06:26:27 PM PDT 24
Peak memory 183000 kb
Host smart-5f2b7740-0f6d-4a59-8601-6456751211c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548088264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.548088264
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.89994755
Short name T445
Test name
Test status
Simulation time 206241700738 ps
CPU time 189.5 seconds
Started Jun 10 06:23:49 PM PDT 24
Finished Jun 10 06:26:59 PM PDT 24
Peak memory 183064 kb
Host smart-37a57cad-854e-4c3a-b25e-58094c32f649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89994755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.89994755
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.3682532990
Short name T52
Test name
Test status
Simulation time 294298912919 ps
CPU time 449.93 seconds
Started Jun 10 06:28:06 PM PDT 24
Finished Jun 10 06:35:37 PM PDT 24
Peak memory 191236 kb
Host smart-988a40d5-c3c5-451f-8d5b-c6e08b9463e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682532990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3682532990
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3099520069
Short name T338
Test name
Test status
Simulation time 193856358332 ps
CPU time 83.88 seconds
Started Jun 10 06:28:08 PM PDT 24
Finished Jun 10 06:29:32 PM PDT 24
Peak memory 183020 kb
Host smart-3409dc43-efc1-4fba-a0cc-981d28c833fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099520069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3099520069
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3206376764
Short name T424
Test name
Test status
Simulation time 459499996237 ps
CPU time 275.83 seconds
Started Jun 10 06:28:08 PM PDT 24
Finished Jun 10 06:32:44 PM PDT 24
Peak memory 191260 kb
Host smart-e5450f4a-0d4c-4985-a2d9-4755e0bbfc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206376764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3206376764
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4149296275
Short name T68
Test name
Test status
Simulation time 173337741194 ps
CPU time 45.58 seconds
Started Jun 10 06:28:08 PM PDT 24
Finished Jun 10 06:28:54 PM PDT 24
Peak memory 183012 kb
Host smart-2c28c917-a1a7-4993-a610-5852935cca88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149296275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4149296275
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3311876885
Short name T298
Test name
Test status
Simulation time 59938506453 ps
CPU time 76.3 seconds
Started Jun 10 06:28:09 PM PDT 24
Finished Jun 10 06:29:26 PM PDT 24
Peak memory 183084 kb
Host smart-107b2499-54d4-43cc-835d-3b3fd3881c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311876885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3311876885
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3308652746
Short name T114
Test name
Test status
Simulation time 1036855101579 ps
CPU time 283.84 seconds
Started Jun 10 06:28:10 PM PDT 24
Finished Jun 10 06:32:54 PM PDT 24
Peak memory 191192 kb
Host smart-1c422dcc-a438-468e-9df3-466bedf5a52e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308652746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3308652746
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2660400012
Short name T157
Test name
Test status
Simulation time 3381001954514 ps
CPU time 1070.65 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:41:42 PM PDT 24
Peak memory 183056 kb
Host smart-6e5e57b4-215c-463f-94fb-1367d81b4618
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660400012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2660400012
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.4148933678
Short name T372
Test name
Test status
Simulation time 45656874539 ps
CPU time 53.78 seconds
Started Jun 10 06:23:49 PM PDT 24
Finished Jun 10 06:24:43 PM PDT 24
Peak memory 183052 kb
Host smart-4b0a7532-5672-4375-a01d-79d1536eb8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148933678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4148933678
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2484082403
Short name T340
Test name
Test status
Simulation time 330835332758 ps
CPU time 194.27 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:27:05 PM PDT 24
Peak memory 191256 kb
Host smart-a7906b90-fce0-467f-adeb-195dd82b50e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484082403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2484082403
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1860768000
Short name T385
Test name
Test status
Simulation time 41578914413 ps
CPU time 23.46 seconds
Started Jun 10 06:23:50 PM PDT 24
Finished Jun 10 06:24:14 PM PDT 24
Peak memory 194724 kb
Host smart-66865237-2c0b-4f01-ab43-9da8240e6515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860768000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1860768000
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1735482245
Short name T13
Test name
Test status
Simulation time 40989938100 ps
CPU time 124.67 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:25:56 PM PDT 24
Peak memory 197532 kb
Host smart-3ae2ab1e-79ee-4170-bc6e-7f9c6e09fb18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735482245 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.1735482245
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1501172660
Short name T254
Test name
Test status
Simulation time 59604585046 ps
CPU time 110.65 seconds
Started Jun 10 06:28:09 PM PDT 24
Finished Jun 10 06:30:00 PM PDT 24
Peak memory 191244 kb
Host smart-16367f98-f301-46ad-8131-610b63b61d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501172660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1501172660
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.276909239
Short name T316
Test name
Test status
Simulation time 124649142246 ps
CPU time 938.4 seconds
Started Jun 10 06:28:16 PM PDT 24
Finished Jun 10 06:43:55 PM PDT 24
Peak memory 191240 kb
Host smart-603e7a76-3dc6-415a-8c7e-e06f494b8bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276909239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.276909239
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2412801501
Short name T202
Test name
Test status
Simulation time 360937405999 ps
CPU time 564.38 seconds
Started Jun 10 06:28:14 PM PDT 24
Finished Jun 10 06:37:39 PM PDT 24
Peak memory 191244 kb
Host smart-cfd93f45-b6ca-410e-9c7c-97ca9b493af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412801501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2412801501
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.4243567014
Short name T252
Test name
Test status
Simulation time 238043443603 ps
CPU time 1900.81 seconds
Started Jun 10 06:28:19 PM PDT 24
Finished Jun 10 07:00:00 PM PDT 24
Peak memory 191232 kb
Host smart-766b0eff-fa6c-440c-b29f-bc68a20e6256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243567014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.4243567014
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.517133674
Short name T345
Test name
Test status
Simulation time 99787763839 ps
CPU time 165.46 seconds
Started Jun 10 06:28:19 PM PDT 24
Finished Jun 10 06:31:05 PM PDT 24
Peak memory 191268 kb
Host smart-87f23c90-b6a1-4b6d-860b-b4ff8c62be63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517133674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.517133674
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.234968389
Short name T325
Test name
Test status
Simulation time 363920292352 ps
CPU time 359.98 seconds
Started Jun 10 06:28:20 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 191120 kb
Host smart-a865a79d-c344-4a4a-8946-b54379cfb334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234968389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.234968389
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.169289528
Short name T91
Test name
Test status
Simulation time 122616104348 ps
CPU time 120.9 seconds
Started Jun 10 06:28:19 PM PDT 24
Finished Jun 10 06:30:20 PM PDT 24
Peak memory 191280 kb
Host smart-e0e21e50-58a0-4c26-b95a-aa3e09413bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169289528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.169289528
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2510236308
Short name T282
Test name
Test status
Simulation time 701061341737 ps
CPU time 349.57 seconds
Started Jun 10 06:28:22 PM PDT 24
Finished Jun 10 06:34:12 PM PDT 24
Peak memory 191284 kb
Host smart-7827eca5-3571-452c-a1a1-49639b7d12c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510236308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2510236308
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2326557715
Short name T71
Test name
Test status
Simulation time 105137177368 ps
CPU time 84.73 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:25:16 PM PDT 24
Peak memory 183028 kb
Host smart-e19f8e8c-9c0d-4be5-b3d7-f8af9b18dc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326557715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2326557715
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3010303208
Short name T278
Test name
Test status
Simulation time 5054500868 ps
CPU time 7.95 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:23:59 PM PDT 24
Peak memory 183048 kb
Host smart-ed7a6747-3f7e-4ef4-836c-55b5634a43c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010303208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3010303208
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3641358871
Short name T55
Test name
Test status
Simulation time 200194752343 ps
CPU time 275.92 seconds
Started Jun 10 06:23:51 PM PDT 24
Finished Jun 10 06:28:27 PM PDT 24
Peak memory 196004 kb
Host smart-1581bc00-5b0c-40d7-8ce3-3b59380e22cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641358871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3641358871
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.2661157851
Short name T151
Test name
Test status
Simulation time 50613799750 ps
CPU time 71.25 seconds
Started Jun 10 06:28:24 PM PDT 24
Finished Jun 10 06:29:36 PM PDT 24
Peak memory 183084 kb
Host smart-a11ae886-60f5-4757-8e03-48f4b86f2b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661157851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2661157851
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.106479761
Short name T145
Test name
Test status
Simulation time 206798184589 ps
CPU time 114.5 seconds
Started Jun 10 06:28:26 PM PDT 24
Finished Jun 10 06:30:21 PM PDT 24
Peak memory 191292 kb
Host smart-bda42e02-6d27-4e70-b33e-c505922dfa2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106479761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.106479761
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.98936269
Short name T279
Test name
Test status
Simulation time 32275340404 ps
CPU time 64.24 seconds
Started Jun 10 06:28:26 PM PDT 24
Finished Jun 10 06:29:31 PM PDT 24
Peak memory 183028 kb
Host smart-96031be5-c129-41b4-b6e8-0fdafc847098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98936269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.98936269
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3353597794
Short name T400
Test name
Test status
Simulation time 147054653752 ps
CPU time 66.89 seconds
Started Jun 10 06:28:27 PM PDT 24
Finished Jun 10 06:29:34 PM PDT 24
Peak memory 183076 kb
Host smart-29d31392-9967-4f87-b4ce-533eecef6df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353597794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3353597794
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3200069463
Short name T200
Test name
Test status
Simulation time 113564724293 ps
CPU time 95.05 seconds
Started Jun 10 06:28:32 PM PDT 24
Finished Jun 10 06:30:07 PM PDT 24
Peak memory 191264 kb
Host smart-0ec18fa2-109d-4d10-a29d-f9e28f5febbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200069463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3200069463
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.902641983
Short name T323
Test name
Test status
Simulation time 91511248881 ps
CPU time 160.91 seconds
Started Jun 10 06:28:31 PM PDT 24
Finished Jun 10 06:31:12 PM PDT 24
Peak memory 193240 kb
Host smart-9a84fd3b-c859-426b-8aa4-0aa8c4f0430c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902641983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.902641983
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1489932413
Short name T228
Test name
Test status
Simulation time 486390311495 ps
CPU time 122.04 seconds
Started Jun 10 06:28:32 PM PDT 24
Finished Jun 10 06:30:35 PM PDT 24
Peak memory 191164 kb
Host smart-958c64e2-a11b-4877-9276-97059f241e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489932413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1489932413
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3433243002
Short name T344
Test name
Test status
Simulation time 252607711260 ps
CPU time 424.92 seconds
Started Jun 10 06:23:53 PM PDT 24
Finished Jun 10 06:30:58 PM PDT 24
Peak memory 183044 kb
Host smart-91544e42-7121-45e0-846e-f624805c7cb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433243002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3433243002
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3496613576
Short name T366
Test name
Test status
Simulation time 98133418073 ps
CPU time 112.87 seconds
Started Jun 10 06:23:52 PM PDT 24
Finished Jun 10 06:25:45 PM PDT 24
Peak memory 183052 kb
Host smart-f09f4c16-4fca-4089-9ce2-a150d91ab67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496613576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3496613576
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1035407476
Short name T185
Test name
Test status
Simulation time 56858889159 ps
CPU time 139.64 seconds
Started Jun 10 06:23:52 PM PDT 24
Finished Jun 10 06:26:12 PM PDT 24
Peak memory 182984 kb
Host smart-0af363f9-83cf-4732-92e4-829fe64509e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035407476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1035407476
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1618736536
Short name T452
Test name
Test status
Simulation time 105457948 ps
CPU time 0.6 seconds
Started Jun 10 06:23:56 PM PDT 24
Finished Jun 10 06:23:57 PM PDT 24
Peak memory 182848 kb
Host smart-b62f6501-11e7-47d0-89df-4df707dea79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618736536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1618736536
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.1359628859
Short name T321
Test name
Test status
Simulation time 159534675735 ps
CPU time 641.75 seconds
Started Jun 10 06:28:34 PM PDT 24
Finished Jun 10 06:39:16 PM PDT 24
Peak memory 191172 kb
Host smart-8406dda8-0e8a-489d-87c8-336995446d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359628859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1359628859
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1429944110
Short name T329
Test name
Test status
Simulation time 185340662938 ps
CPU time 189.81 seconds
Started Jun 10 06:28:39 PM PDT 24
Finished Jun 10 06:31:49 PM PDT 24
Peak memory 191280 kb
Host smart-ea0412b2-68fd-4102-9da8-ccd892042f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429944110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1429944110
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3750477806
Short name T23
Test name
Test status
Simulation time 516107550263 ps
CPU time 545.52 seconds
Started Jun 10 06:28:38 PM PDT 24
Finished Jun 10 06:37:43 PM PDT 24
Peak memory 191284 kb
Host smart-c86272e3-fc0d-43bc-9c37-1c40ed4a76a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750477806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3750477806
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3180828596
Short name T172
Test name
Test status
Simulation time 14385135841 ps
CPU time 12.8 seconds
Started Jun 10 06:28:40 PM PDT 24
Finished Jun 10 06:28:53 PM PDT 24
Peak memory 183104 kb
Host smart-5441e453-d26e-49c8-86b3-b94485cb199e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180828596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3180828596
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4167104706
Short name T191
Test name
Test status
Simulation time 283970649212 ps
CPU time 261.11 seconds
Started Jun 10 06:28:44 PM PDT 24
Finished Jun 10 06:33:06 PM PDT 24
Peak memory 191272 kb
Host smart-ce5a1788-d3a0-4050-9247-94e336b39fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167104706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4167104706
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1446799946
Short name T447
Test name
Test status
Simulation time 194358195302 ps
CPU time 114.15 seconds
Started Jun 10 06:28:41 PM PDT 24
Finished Jun 10 06:30:35 PM PDT 24
Peak memory 191248 kb
Host smart-e87c6703-977d-4757-b0dc-90cadba0978e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446799946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1446799946
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4292390978
Short name T324
Test name
Test status
Simulation time 177691219349 ps
CPU time 330.82 seconds
Started Jun 10 06:24:01 PM PDT 24
Finished Jun 10 06:29:32 PM PDT 24
Peak memory 183052 kb
Host smart-37a95be1-a0c2-4fdc-8940-0d7abd2e6e54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292390978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4292390978
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.286230132
Short name T360
Test name
Test status
Simulation time 67352412009 ps
CPU time 97.77 seconds
Started Jun 10 06:23:55 PM PDT 24
Finished Jun 10 06:25:33 PM PDT 24
Peak memory 183008 kb
Host smart-2f847705-df8e-4b5d-b5ee-c3fb3ff0d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286230132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.286230132
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.588103
Short name T439
Test name
Test status
Simulation time 85942070 ps
CPU time 0.65 seconds
Started Jun 10 06:24:01 PM PDT 24
Finished Jun 10 06:24:01 PM PDT 24
Peak memory 182844 kb
Host smart-b456b28f-3864-40aa-95ed-18cf09315f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.588103
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3939649372
Short name T294
Test name
Test status
Simulation time 142009114635 ps
CPU time 364.73 seconds
Started Jun 10 06:28:44 PM PDT 24
Finished Jun 10 06:34:49 PM PDT 24
Peak memory 183060 kb
Host smart-aee90814-ea65-4c29-8998-da60ce5e9d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939649372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3939649372
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1216784508
Short name T328
Test name
Test status
Simulation time 29667294631 ps
CPU time 49.62 seconds
Started Jun 10 06:28:43 PM PDT 24
Finished Jun 10 06:29:33 PM PDT 24
Peak memory 183024 kb
Host smart-8e452927-c635-4b24-9529-ac82d7ce2c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216784508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1216784508
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2804401300
Short name T352
Test name
Test status
Simulation time 66994526709 ps
CPU time 61.65 seconds
Started Jun 10 06:28:42 PM PDT 24
Finished Jun 10 06:29:44 PM PDT 24
Peak memory 183060 kb
Host smart-32a88e05-77df-422f-8011-7ebbd65eb9e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804401300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2804401300
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1992885044
Short name T188
Test name
Test status
Simulation time 35922386624 ps
CPU time 55.89 seconds
Started Jun 10 06:28:48 PM PDT 24
Finished Jun 10 06:29:44 PM PDT 24
Peak memory 191284 kb
Host smart-9ceb5e70-6315-44fb-afd2-fa6cd6a1b6b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992885044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1992885044
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2844657100
Short name T51
Test name
Test status
Simulation time 68925405619 ps
CPU time 225.33 seconds
Started Jun 10 06:28:48 PM PDT 24
Finished Jun 10 06:32:34 PM PDT 24
Peak memory 192248 kb
Host smart-389284b0-00ef-4141-aac8-0b1c1676e36d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844657100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2844657100
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3695346231
Short name T122
Test name
Test status
Simulation time 409018419093 ps
CPU time 416.57 seconds
Started Jun 10 06:24:04 PM PDT 24
Finished Jun 10 06:31:00 PM PDT 24
Peak memory 183072 kb
Host smart-9ba3eddf-1c3a-424e-a8b3-599771c031cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695346231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3695346231
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1958490648
Short name T374
Test name
Test status
Simulation time 163670773689 ps
CPU time 223.39 seconds
Started Jun 10 06:24:03 PM PDT 24
Finished Jun 10 06:27:47 PM PDT 24
Peak memory 183052 kb
Host smart-56bd7e26-ba3f-449c-92fc-ea7f40310871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958490648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1958490648
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1236151516
Short name T292
Test name
Test status
Simulation time 86010997320 ps
CPU time 151.5 seconds
Started Jun 10 06:24:03 PM PDT 24
Finished Jun 10 06:26:35 PM PDT 24
Peak memory 191260 kb
Host smart-6672fa26-90bf-4b9a-a944-2e93e8d4f079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236151516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1236151516
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1540015676
Short name T301
Test name
Test status
Simulation time 355796996928 ps
CPU time 152.98 seconds
Started Jun 10 06:24:08 PM PDT 24
Finished Jun 10 06:26:41 PM PDT 24
Peak memory 183004 kb
Host smart-5b8aa757-1845-479d-9e04-f1ca3cfff05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540015676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1540015676
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.599147703
Short name T312
Test name
Test status
Simulation time 550284713756 ps
CPU time 469.93 seconds
Started Jun 10 06:24:08 PM PDT 24
Finished Jun 10 06:31:58 PM PDT 24
Peak memory 196040 kb
Host smart-e79ccf86-a3e2-4401-a01e-b86f436a96ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599147703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
599147703
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.3193715487
Short name T119
Test name
Test status
Simulation time 303639916570 ps
CPU time 1562.06 seconds
Started Jun 10 06:28:51 PM PDT 24
Finished Jun 10 06:54:53 PM PDT 24
Peak memory 191232 kb
Host smart-75d97849-3514-4a46-9db8-5147d1ebf189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193715487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3193715487
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.4251475952
Short name T418
Test name
Test status
Simulation time 45797793089 ps
CPU time 69.38 seconds
Started Jun 10 06:28:52 PM PDT 24
Finished Jun 10 06:30:02 PM PDT 24
Peak memory 191276 kb
Host smart-4c342b2d-19af-4d0f-8fba-5cd7ba223114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251475952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.4251475952
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.4196554133
Short name T314
Test name
Test status
Simulation time 59795173583 ps
CPU time 44.22 seconds
Started Jun 10 06:28:51 PM PDT 24
Finished Jun 10 06:29:36 PM PDT 24
Peak memory 183076 kb
Host smart-f5cbb214-3cc8-4ba7-9f21-24181d9b60ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196554133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.4196554133
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1940606970
Short name T213
Test name
Test status
Simulation time 94716598971 ps
CPU time 216.66 seconds
Started Jun 10 06:28:57 PM PDT 24
Finished Jun 10 06:32:34 PM PDT 24
Peak memory 191268 kb
Host smart-986fb7dc-02e9-433f-ae22-4cc1f750bb3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940606970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1940606970
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1464325867
Short name T150
Test name
Test status
Simulation time 3391767709 ps
CPU time 70.23 seconds
Started Jun 10 06:28:56 PM PDT 24
Finished Jun 10 06:30:07 PM PDT 24
Peak memory 183060 kb
Host smart-28d8db3e-353f-472a-84d1-f6a9eeedff8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464325867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1464325867
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.889603485
Short name T162
Test name
Test status
Simulation time 756514689918 ps
CPU time 1707.35 seconds
Started Jun 10 06:28:58 PM PDT 24
Finished Jun 10 06:57:25 PM PDT 24
Peak memory 191224 kb
Host smart-08802730-6a0b-4e4a-80ef-d0bcbe776a14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889603485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.889603485
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1801011464
Short name T381
Test name
Test status
Simulation time 22426806652 ps
CPU time 128.82 seconds
Started Jun 10 06:28:57 PM PDT 24
Finished Jun 10 06:31:06 PM PDT 24
Peak memory 183024 kb
Host smart-ec4bfa6b-9975-42ef-8915-10dcf1d02b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801011464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1801011464
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.4192782630
Short name T243
Test name
Test status
Simulation time 144141665958 ps
CPU time 355.83 seconds
Started Jun 10 06:28:55 PM PDT 24
Finished Jun 10 06:34:52 PM PDT 24
Peak memory 191260 kb
Host smart-cc855c50-1d8a-4071-bcfa-c21bb0181df3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192782630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4192782630
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.289457498
Short name T144
Test name
Test status
Simulation time 1195878506462 ps
CPU time 466.26 seconds
Started Jun 10 06:24:12 PM PDT 24
Finished Jun 10 06:31:59 PM PDT 24
Peak memory 183028 kb
Host smart-7c782b16-700b-456f-a33f-3cc7c87f55c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289457498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.289457498
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.4098928172
Short name T365
Test name
Test status
Simulation time 145357810184 ps
CPU time 207.62 seconds
Started Jun 10 06:24:11 PM PDT 24
Finished Jun 10 06:27:39 PM PDT 24
Peak memory 183064 kb
Host smart-92df6ba1-3fd9-4a3a-8292-97092682d1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098928172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4098928172
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1897554936
Short name T417
Test name
Test status
Simulation time 366386938 ps
CPU time 0.69 seconds
Started Jun 10 06:24:12 PM PDT 24
Finished Jun 10 06:24:13 PM PDT 24
Peak memory 191436 kb
Host smart-bab75289-262a-404a-9fb8-af5f5131b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897554936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1897554936
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/191.rv_timer_random.1113414391
Short name T50
Test name
Test status
Simulation time 840108628622 ps
CPU time 402.68 seconds
Started Jun 10 06:28:59 PM PDT 24
Finished Jun 10 06:35:42 PM PDT 24
Peak memory 191256 kb
Host smart-7647d19f-a199-4e04-8c0c-2405e15f77df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113414391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1113414391
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3137483327
Short name T136
Test name
Test status
Simulation time 260353458023 ps
CPU time 276.92 seconds
Started Jun 10 06:28:59 PM PDT 24
Finished Jun 10 06:33:36 PM PDT 24
Peak memory 191280 kb
Host smart-49d9c957-e439-4709-932f-bac8c770f935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137483327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3137483327
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.655018498
Short name T280
Test name
Test status
Simulation time 39246947301 ps
CPU time 48.89 seconds
Started Jun 10 06:28:59 PM PDT 24
Finished Jun 10 06:29:48 PM PDT 24
Peak memory 182924 kb
Host smart-ca7b15d4-6c44-4eb7-891c-4585d3780793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655018498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.655018498
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.838646719
Short name T235
Test name
Test status
Simulation time 222266260731 ps
CPU time 335.19 seconds
Started Jun 10 06:28:58 PM PDT 24
Finished Jun 10 06:34:34 PM PDT 24
Peak memory 193776 kb
Host smart-01984034-e1c6-488e-a529-f5a9c5a652c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838646719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.838646719
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.854161997
Short name T332
Test name
Test status
Simulation time 96357802994 ps
CPU time 167.03 seconds
Started Jun 10 06:28:58 PM PDT 24
Finished Jun 10 06:31:46 PM PDT 24
Peak memory 191304 kb
Host smart-ecc183a3-2bc9-49de-bc18-3fa6b066a4e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854161997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.854161997
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2350895666
Short name T190
Test name
Test status
Simulation time 63149094009 ps
CPU time 98.85 seconds
Started Jun 10 06:29:02 PM PDT 24
Finished Jun 10 06:30:41 PM PDT 24
Peak memory 191216 kb
Host smart-df644831-4288-43a4-85b3-98a38d150d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350895666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2350895666
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.54919045
Short name T171
Test name
Test status
Simulation time 610862606589 ps
CPU time 549.43 seconds
Started Jun 10 06:29:03 PM PDT 24
Finished Jun 10 06:38:13 PM PDT 24
Peak memory 191260 kb
Host smart-24c13b1c-4285-403a-87e7-b978b57bf057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54919045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.54919045
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2270292463
Short name T146
Test name
Test status
Simulation time 901998561617 ps
CPU time 557.97 seconds
Started Jun 10 06:29:04 PM PDT 24
Finished Jun 10 06:38:22 PM PDT 24
Peak memory 191256 kb
Host smart-00accb21-0f5f-4300-a250-2cac3514f367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270292463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2270292463
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.4005106177
Short name T309
Test name
Test status
Simulation time 338599481179 ps
CPU time 330 seconds
Started Jun 10 06:23:19 PM PDT 24
Finished Jun 10 06:28:49 PM PDT 24
Peak memory 183060 kb
Host smart-5702eef5-2bbe-4e91-8cd5-b57fb1d62f60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005106177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.4005106177
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1600756585
Short name T369
Test name
Test status
Simulation time 151428246834 ps
CPU time 216.2 seconds
Started Jun 10 06:23:26 PM PDT 24
Finished Jun 10 06:27:02 PM PDT 24
Peak memory 182992 kb
Host smart-0b98682b-fa17-49b4-8f56-63d0618211de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600756585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1600756585
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1782070518
Short name T147
Test name
Test status
Simulation time 138477780682 ps
CPU time 171.28 seconds
Started Jun 10 06:23:20 PM PDT 24
Finished Jun 10 06:26:12 PM PDT 24
Peak memory 183068 kb
Host smart-9daf14cc-dae8-467d-b706-1642bb7cb02e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782070518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1782070518
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1589133281
Short name T87
Test name
Test status
Simulation time 78592804311 ps
CPU time 275.71 seconds
Started Jun 10 06:23:23 PM PDT 24
Finished Jun 10 06:27:59 PM PDT 24
Peak memory 183092 kb
Host smart-060d0d7f-274b-468c-bb4d-345849840d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589133281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1589133281
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4028927032
Short name T15
Test name
Test status
Simulation time 159298406 ps
CPU time 0.73 seconds
Started Jun 10 06:23:21 PM PDT 24
Finished Jun 10 06:23:22 PM PDT 24
Peak memory 213428 kb
Host smart-566dce4a-0cd7-45f4-a237-ebd83bcbd901
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028927032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4028927032
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1562920071
Short name T446
Test name
Test status
Simulation time 604924160520 ps
CPU time 345.54 seconds
Started Jun 10 06:24:17 PM PDT 24
Finished Jun 10 06:30:03 PM PDT 24
Peak memory 183080 kb
Host smart-b4a0610f-4fe7-4683-9cf7-7eb171d2abc3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562920071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1562920071
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.808165603
Short name T378
Test name
Test status
Simulation time 89178985521 ps
CPU time 145.98 seconds
Started Jun 10 06:24:17 PM PDT 24
Finished Jun 10 06:26:43 PM PDT 24
Peak memory 183076 kb
Host smart-ac710fd5-3310-4e9b-abeb-2cd89b66ae5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808165603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.808165603
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.233231510
Short name T269
Test name
Test status
Simulation time 7613178992 ps
CPU time 46.13 seconds
Started Jun 10 06:24:21 PM PDT 24
Finished Jun 10 06:25:07 PM PDT 24
Peak memory 182988 kb
Host smart-f67cbdd7-1ace-4418-bc02-74ba6e35f6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233231510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.233231510
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3888957731
Short name T238
Test name
Test status
Simulation time 1065913509428 ps
CPU time 606.73 seconds
Started Jun 10 06:24:18 PM PDT 24
Finished Jun 10 06:34:25 PM PDT 24
Peak memory 183036 kb
Host smart-22a8a4d0-5603-47a7-ba58-353a569df32c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888957731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3888957731
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1469412742
Short name T387
Test name
Test status
Simulation time 233621652896 ps
CPU time 89.53 seconds
Started Jun 10 06:24:20 PM PDT 24
Finished Jun 10 06:25:50 PM PDT 24
Peak memory 183152 kb
Host smart-fed68907-233b-44b1-aedc-962b9eba1bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469412742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1469412742
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2441094957
Short name T195
Test name
Test status
Simulation time 96477216178 ps
CPU time 151.93 seconds
Started Jun 10 06:24:20 PM PDT 24
Finished Jun 10 06:26:52 PM PDT 24
Peak memory 191268 kb
Host smart-79bb7278-cb6b-403f-a8b3-9491e01241f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441094957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2441094957
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.763623897
Short name T290
Test name
Test status
Simulation time 16601360450 ps
CPU time 30.41 seconds
Started Jun 10 06:24:20 PM PDT 24
Finished Jun 10 06:24:50 PM PDT 24
Peak memory 183000 kb
Host smart-befaa7b8-0572-47fb-8026-1820bba28d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763623897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.763623897
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.259206022
Short name T64
Test name
Test status
Simulation time 1008288303663 ps
CPU time 362.52 seconds
Started Jun 10 06:24:26 PM PDT 24
Finished Jun 10 06:30:28 PM PDT 24
Peak memory 191244 kb
Host smart-1d02dddd-3772-457c-8fff-ba3c4a832800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259206022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
259206022
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1425045822
Short name T49
Test name
Test status
Simulation time 336885079269 ps
CPU time 133.37 seconds
Started Jun 10 06:24:28 PM PDT 24
Finished Jun 10 06:26:42 PM PDT 24
Peak memory 183000 kb
Host smart-541ed533-1a9a-4b37-b294-11a779b1c77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425045822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1425045822
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.280877469
Short name T167
Test name
Test status
Simulation time 188559059898 ps
CPU time 312.84 seconds
Started Jun 10 06:24:26 PM PDT 24
Finished Jun 10 06:29:40 PM PDT 24
Peak memory 191252 kb
Host smart-215225b0-745b-4e33-8bbb-27804e165e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280877469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.280877469
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.938950705
Short name T187
Test name
Test status
Simulation time 52274863900 ps
CPU time 90.97 seconds
Started Jun 10 06:24:32 PM PDT 24
Finished Jun 10 06:26:03 PM PDT 24
Peak memory 191300 kb
Host smart-3cbd08a9-ec3c-473f-a4c3-672d9919f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938950705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.938950705
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1010884692
Short name T409
Test name
Test status
Simulation time 107907046 ps
CPU time 0.64 seconds
Started Jun 10 06:24:34 PM PDT 24
Finished Jun 10 06:24:35 PM PDT 24
Peak memory 182860 kb
Host smart-cb909662-7494-4690-80f7-167d7a30ea4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010884692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1010884692
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4174923144
Short name T264
Test name
Test status
Simulation time 720976440979 ps
CPU time 215.8 seconds
Started Jun 10 06:24:35 PM PDT 24
Finished Jun 10 06:28:11 PM PDT 24
Peak memory 183084 kb
Host smart-619605ec-dc92-4855-8d90-b0189139b69e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174923144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4174923144
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3571703803
Short name T383
Test name
Test status
Simulation time 168077425186 ps
CPU time 231.05 seconds
Started Jun 10 06:24:33 PM PDT 24
Finished Jun 10 06:28:24 PM PDT 24
Peak memory 183060 kb
Host smart-c00ef863-67a9-437e-938c-dc1a9a2f5bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571703803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3571703803
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2095573133
Short name T354
Test name
Test status
Simulation time 20683504084 ps
CPU time 29.44 seconds
Started Jun 10 06:24:32 PM PDT 24
Finished Jun 10 06:25:02 PM PDT 24
Peak memory 183020 kb
Host smart-cfcd990e-5e95-48ae-b86e-f7241938c8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095573133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2095573133
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2578758622
Short name T63
Test name
Test status
Simulation time 228523628 ps
CPU time 0.74 seconds
Started Jun 10 06:24:31 PM PDT 24
Finished Jun 10 06:24:32 PM PDT 24
Peak memory 182768 kb
Host smart-9ec42ef0-4936-42d3-8431-289b8972bb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578758622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2578758622
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1323747142
Short name T388
Test name
Test status
Simulation time 134046347527 ps
CPU time 46.81 seconds
Started Jun 10 06:24:38 PM PDT 24
Finished Jun 10 06:25:25 PM PDT 24
Peak memory 183076 kb
Host smart-be9fe69d-6394-4fa6-b268-1f54a8115039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323747142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1323747142
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1318219536
Short name T438
Test name
Test status
Simulation time 73562824 ps
CPU time 0.65 seconds
Started Jun 10 06:24:36 PM PDT 24
Finished Jun 10 06:24:37 PM PDT 24
Peak memory 182836 kb
Host smart-a1f9ba26-2f2b-41fb-9593-35aff255459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318219536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1318219536
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2960844443
Short name T450
Test name
Test status
Simulation time 195648484115 ps
CPU time 241.89 seconds
Started Jun 10 06:24:40 PM PDT 24
Finished Jun 10 06:28:42 PM PDT 24
Peak memory 183048 kb
Host smart-caa32f93-2891-4095-90fb-4c292cc007a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960844443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2960844443
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2569630317
Short name T140
Test name
Test status
Simulation time 67519362498 ps
CPU time 108.18 seconds
Started Jun 10 06:24:40 PM PDT 24
Finished Jun 10 06:26:28 PM PDT 24
Peak memory 191300 kb
Host smart-7fba24d5-3cb4-448d-a91d-cb51922177bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569630317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2569630317
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4166392506
Short name T66
Test name
Test status
Simulation time 481457447877 ps
CPU time 272.07 seconds
Started Jun 10 06:24:44 PM PDT 24
Finished Jun 10 06:29:16 PM PDT 24
Peak memory 183076 kb
Host smart-6f2962de-ed3f-45db-8eef-9d5e0aaef58e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166392506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4166392506
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.4006940258
Short name T453
Test name
Test status
Simulation time 134995452961 ps
CPU time 190.95 seconds
Started Jun 10 06:24:44 PM PDT 24
Finished Jun 10 06:27:55 PM PDT 24
Peak memory 183056 kb
Host smart-dc506f5d-11cd-4ecb-8c46-5af5ff1d498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006940258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.4006940258
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1729528101
Short name T116
Test name
Test status
Simulation time 137639692019 ps
CPU time 405.19 seconds
Started Jun 10 06:24:43 PM PDT 24
Finished Jun 10 06:31:29 PM PDT 24
Peak memory 191280 kb
Host smart-0dc35c23-5519-41a3-9844-754a8cbd94e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729528101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1729528101
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2436119537
Short name T371
Test name
Test status
Simulation time 217064389 ps
CPU time 0.68 seconds
Started Jun 10 06:24:46 PM PDT 24
Finished Jun 10 06:24:47 PM PDT 24
Peak memory 182796 kb
Host smart-54a3042f-6d61-4fea-86e6-edeaa45de0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436119537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2436119537
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.71248234
Short name T237
Test name
Test status
Simulation time 909741365708 ps
CPU time 454.13 seconds
Started Jun 10 06:24:49 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 183068 kb
Host smart-38abe746-a8a4-44a4-9c0e-1a074125f45c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71248234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.rv_timer_cfg_update_on_fly.71248234
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3291567350
Short name T392
Test name
Test status
Simulation time 93220358991 ps
CPU time 148.83 seconds
Started Jun 10 06:24:45 PM PDT 24
Finished Jun 10 06:27:14 PM PDT 24
Peak memory 183020 kb
Host smart-07d8c5f5-9d0c-4859-8217-3cce4b611ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291567350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3291567350
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2298582089
Short name T132
Test name
Test status
Simulation time 26069411301 ps
CPU time 48.53 seconds
Started Jun 10 06:24:48 PM PDT 24
Finished Jun 10 06:25:37 PM PDT 24
Peak memory 183084 kb
Host smart-1b364ace-63b4-4e03-8ee1-6f99dc6dc567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298582089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2298582089
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.522954219
Short name T333
Test name
Test status
Simulation time 184669243628 ps
CPU time 1920.1 seconds
Started Jun 10 06:24:47 PM PDT 24
Finished Jun 10 06:56:47 PM PDT 24
Peak memory 191260 kb
Host smart-1675aa06-28b5-4ba8-bd7b-54cbaf72fb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522954219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.522954219
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2867694058
Short name T433
Test name
Test status
Simulation time 560210842639 ps
CPU time 227.28 seconds
Started Jun 10 06:24:48 PM PDT 24
Finished Jun 10 06:28:36 PM PDT 24
Peak memory 191276 kb
Host smart-cf49371b-3c5e-4ad7-b5b8-4ad70f5bae73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867694058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2867694058
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.618370362
Short name T420
Test name
Test status
Simulation time 57142221311 ps
CPU time 81.24 seconds
Started Jun 10 06:24:50 PM PDT 24
Finished Jun 10 06:26:12 PM PDT 24
Peak memory 183004 kb
Host smart-3c92b9da-e135-4726-8171-681e7b247dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618370362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.618370362
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1300264186
Short name T335
Test name
Test status
Simulation time 67887359187 ps
CPU time 157.67 seconds
Started Jun 10 06:24:50 PM PDT 24
Finished Jun 10 06:27:28 PM PDT 24
Peak memory 193824 kb
Host smart-ec461f34-c7db-40b9-bb93-f54dc3932eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300264186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1300264186
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1168810689
Short name T229
Test name
Test status
Simulation time 25964713135 ps
CPU time 20.71 seconds
Started Jun 10 06:24:52 PM PDT 24
Finished Jun 10 06:25:13 PM PDT 24
Peak memory 191244 kb
Host smart-05df93a1-64b6-4d22-9bf9-b7214ceddace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168810689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1168810689
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2794147173
Short name T407
Test name
Test status
Simulation time 74106254591 ps
CPU time 30.8 seconds
Started Jun 10 06:24:55 PM PDT 24
Finished Jun 10 06:25:25 PM PDT 24
Peak memory 183060 kb
Host smart-9cac9e8b-85e5-4068-86c7-7c8a0f6614d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794147173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2794147173
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.372647393
Short name T40
Test name
Test status
Simulation time 210493324813 ps
CPU time 708.73 seconds
Started Jun 10 06:24:51 PM PDT 24
Finished Jun 10 06:36:40 PM PDT 24
Peak memory 205920 kb
Host smart-60e93603-c927-477b-bbd8-bb0384998b9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372647393 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.372647393
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.88490132
Short name T126
Test name
Test status
Simulation time 3208946929137 ps
CPU time 852.36 seconds
Started Jun 10 06:25:00 PM PDT 24
Finished Jun 10 06:39:13 PM PDT 24
Peak memory 183052 kb
Host smart-0338ffe5-ba30-447a-84f1-921df00c1819
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88490132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.rv_timer_cfg_update_on_fly.88490132
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3609142742
Short name T358
Test name
Test status
Simulation time 258007701922 ps
CPU time 76.18 seconds
Started Jun 10 06:24:54 PM PDT 24
Finished Jun 10 06:26:11 PM PDT 24
Peak memory 183040 kb
Host smart-fbd2f41a-9dcb-4e5d-83e7-ec97e8ed433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609142742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3609142742
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2614524219
Short name T404
Test name
Test status
Simulation time 27200666 ps
CPU time 0.57 seconds
Started Jun 10 06:24:59 PM PDT 24
Finished Jun 10 06:25:00 PM PDT 24
Peak memory 182832 kb
Host smart-6a06d656-1495-484c-86d1-a32dad5edc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614524219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2614524219
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3785984227
Short name T12
Test name
Test status
Simulation time 1403477549036 ps
CPU time 1352.8 seconds
Started Jun 10 06:23:25 PM PDT 24
Finished Jun 10 06:45:58 PM PDT 24
Peak memory 182884 kb
Host smart-54868f6f-c434-48df-b6aa-a8be8bd53637
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785984227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3785984227
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.995001543
Short name T390
Test name
Test status
Simulation time 140399282515 ps
CPU time 209.2 seconds
Started Jun 10 06:23:24 PM PDT 24
Finished Jun 10 06:26:54 PM PDT 24
Peak memory 183044 kb
Host smart-2ece8c5f-d15a-43ae-a80c-4f1525ad8421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995001543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.995001543
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1892170368
Short name T259
Test name
Test status
Simulation time 39777814183 ps
CPU time 47.17 seconds
Started Jun 10 06:23:30 PM PDT 24
Finished Jun 10 06:24:17 PM PDT 24
Peak memory 191224 kb
Host smart-6e74e15f-bd6e-467c-b7c4-2b9fc53e5f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892170368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1892170368
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3651486266
Short name T440
Test name
Test status
Simulation time 703423768 ps
CPU time 1.45 seconds
Started Jun 10 06:23:26 PM PDT 24
Finished Jun 10 06:23:28 PM PDT 24
Peak memory 191132 kb
Host smart-7cf9d3c3-734a-4002-8ced-2a82ba3e6eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651486266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3651486266
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1550947736
Short name T18
Test name
Test status
Simulation time 402545245 ps
CPU time 0.93 seconds
Started Jun 10 06:23:24 PM PDT 24
Finished Jun 10 06:23:25 PM PDT 24
Peak memory 213424 kb
Host smart-6245ecbb-beb8-44bd-ab0e-9cfcddac9500
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550947736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1550947736
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2051875467
Short name T373
Test name
Test status
Simulation time 2926881359183 ps
CPU time 555.39 seconds
Started Jun 10 06:23:24 PM PDT 24
Finished Jun 10 06:32:40 PM PDT 24
Peak memory 191236 kb
Host smart-6b81d864-cac5-4503-a197-febcc392eafd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051875467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2051875467
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2679780440
Short name T443
Test name
Test status
Simulation time 1087742799161 ps
CPU time 617.46 seconds
Started Jun 10 06:25:07 PM PDT 24
Finished Jun 10 06:35:25 PM PDT 24
Peak memory 182992 kb
Host smart-7fcc102d-5c08-4258-b00d-c7c5536f7515
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679780440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2679780440
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2863647778
Short name T394
Test name
Test status
Simulation time 26226209632 ps
CPU time 19.26 seconds
Started Jun 10 06:25:08 PM PDT 24
Finished Jun 10 06:25:28 PM PDT 24
Peak memory 183000 kb
Host smart-cd0d488d-9a35-4d1a-a983-e18a69107a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863647778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2863647778
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2322031247
Short name T199
Test name
Test status
Simulation time 92087324766 ps
CPU time 396.61 seconds
Started Jun 10 06:25:04 PM PDT 24
Finished Jun 10 06:31:41 PM PDT 24
Peak memory 191272 kb
Host smart-00a21387-3512-4fd3-bf5d-4a03758e2e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322031247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2322031247
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3208270646
Short name T179
Test name
Test status
Simulation time 353695932220 ps
CPU time 625.38 seconds
Started Jun 10 06:25:08 PM PDT 24
Finished Jun 10 06:35:34 PM PDT 24
Peak memory 193332 kb
Host smart-b11156be-f759-4525-a6d1-a630b444be4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208270646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3208270646
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3945081120
Short name T327
Test name
Test status
Simulation time 398507644361 ps
CPU time 759.33 seconds
Started Jun 10 06:25:11 PM PDT 24
Finished Jun 10 06:37:51 PM PDT 24
Peak memory 182984 kb
Host smart-3bbf3826-251f-4d38-b2e4-ffa9bc7d2256
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945081120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3945081120
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3081885749
Short name T419
Test name
Test status
Simulation time 35469118282 ps
CPU time 48.99 seconds
Started Jun 10 06:25:07 PM PDT 24
Finished Jun 10 06:25:57 PM PDT 24
Peak memory 183056 kb
Host smart-4e17b569-4e4c-4d35-bc26-3626d4f3db2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081885749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3081885749
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2005645210
Short name T141
Test name
Test status
Simulation time 214004188936 ps
CPU time 197.89 seconds
Started Jun 10 06:25:07 PM PDT 24
Finished Jun 10 06:28:26 PM PDT 24
Peak memory 191236 kb
Host smart-c3939153-5771-4387-a19b-d0de2c2f8d98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005645210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2005645210
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3728199726
Short name T406
Test name
Test status
Simulation time 237991713 ps
CPU time 0.64 seconds
Started Jun 10 06:25:17 PM PDT 24
Finished Jun 10 06:25:18 PM PDT 24
Peak memory 182824 kb
Host smart-bd60e3b6-aa55-43a7-9b76-077203ebdda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728199726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3728199726
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1989015739
Short name T226
Test name
Test status
Simulation time 5765791208003 ps
CPU time 1768.27 seconds
Started Jun 10 06:25:15 PM PDT 24
Finished Jun 10 06:54:44 PM PDT 24
Peak memory 191276 kb
Host smart-2099816a-55d4-4875-850f-2ff89c69f820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989015739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1989015739
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2483711276
Short name T33
Test name
Test status
Simulation time 69082581834 ps
CPU time 132.27 seconds
Started Jun 10 06:25:15 PM PDT 24
Finished Jun 10 06:27:28 PM PDT 24
Peak memory 205868 kb
Host smart-0ffa6445-007c-46ec-ba63-b009f0aaa183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483711276 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2483711276
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2843215852
Short name T377
Test name
Test status
Simulation time 40599591467 ps
CPU time 45.36 seconds
Started Jun 10 06:25:19 PM PDT 24
Finished Jun 10 06:26:05 PM PDT 24
Peak memory 183056 kb
Host smart-a76b9504-c103-4f25-adb0-37d6f381ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843215852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2843215852
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3055870574
Short name T260
Test name
Test status
Simulation time 84213405738 ps
CPU time 940.15 seconds
Started Jun 10 06:25:16 PM PDT 24
Finished Jun 10 06:40:56 PM PDT 24
Peak memory 191284 kb
Host smart-964174ff-0c98-4afe-a796-986d9efda4d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055870574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3055870574
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.846206218
Short name T356
Test name
Test status
Simulation time 262944337036 ps
CPU time 331.34 seconds
Started Jun 10 06:25:24 PM PDT 24
Finished Jun 10 06:30:55 PM PDT 24
Peak memory 191184 kb
Host smart-6744cfc3-6e8b-454c-86d9-f3c71b4fa24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846206218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.846206218
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.723480605
Short name T303
Test name
Test status
Simulation time 204486894239 ps
CPU time 317.9 seconds
Started Jun 10 06:25:27 PM PDT 24
Finished Jun 10 06:30:45 PM PDT 24
Peak memory 183072 kb
Host smart-23554277-d5a0-4fa5-8b10-ba90be94f96b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723480605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.723480605
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1261856104
Short name T395
Test name
Test status
Simulation time 13790079836 ps
CPU time 22.85 seconds
Started Jun 10 06:25:30 PM PDT 24
Finished Jun 10 06:25:53 PM PDT 24
Peak memory 183064 kb
Host smart-77d8c863-6b24-4dda-9674-5064efbb87f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261856104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1261856104
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1011042340
Short name T165
Test name
Test status
Simulation time 1027678901925 ps
CPU time 1297.59 seconds
Started Jun 10 06:25:26 PM PDT 24
Finished Jun 10 06:47:04 PM PDT 24
Peak memory 191288 kb
Host smart-5a43e6b0-5cef-4891-8956-344bc6f756d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011042340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1011042340
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.470226852
Short name T428
Test name
Test status
Simulation time 167039784434 ps
CPU time 83.03 seconds
Started Jun 10 06:25:28 PM PDT 24
Finished Jun 10 06:26:51 PM PDT 24
Peak memory 193860 kb
Host smart-269e3a1f-40a3-4ad3-8690-647a7eae5bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470226852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.470226852
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1042138589
Short name T37
Test name
Test status
Simulation time 12118370908 ps
CPU time 102.13 seconds
Started Jun 10 06:25:27 PM PDT 24
Finished Jun 10 06:27:10 PM PDT 24
Peak memory 197676 kb
Host smart-4e37fa11-6aa9-4da6-aac1-539c027a9d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042138589 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1042138589
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.728188062
Short name T251
Test name
Test status
Simulation time 235770811103 ps
CPU time 203.25 seconds
Started Jun 10 06:25:36 PM PDT 24
Finished Jun 10 06:28:59 PM PDT 24
Peak memory 183036 kb
Host smart-1b84da90-9eb9-4953-92af-f1171b93629c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728188062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.728188062
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3887250799
Short name T367
Test name
Test status
Simulation time 252648898465 ps
CPU time 177.23 seconds
Started Jun 10 06:25:31 PM PDT 24
Finished Jun 10 06:28:28 PM PDT 24
Peak memory 183056 kb
Host smart-a47fe0e9-468a-4629-90f4-a62bff264005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887250799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3887250799
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3659214612
Short name T307
Test name
Test status
Simulation time 61599264608 ps
CPU time 101.34 seconds
Started Jun 10 06:25:31 PM PDT 24
Finished Jun 10 06:27:13 PM PDT 24
Peak memory 194732 kb
Host smart-ce97de80-439b-44ec-aa5c-a6ad6bb31179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659214612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3659214612
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1338446968
Short name T432
Test name
Test status
Simulation time 430634048 ps
CPU time 0.77 seconds
Started Jun 10 06:25:34 PM PDT 24
Finished Jun 10 06:25:35 PM PDT 24
Peak memory 191340 kb
Host smart-6f4a03c9-cb2a-42b5-bbf7-f84f1c8e1c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338446968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1338446968
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.515571472
Short name T230
Test name
Test status
Simulation time 379556543087 ps
CPU time 1161.36 seconds
Started Jun 10 06:25:36 PM PDT 24
Finished Jun 10 06:44:58 PM PDT 24
Peak memory 191228 kb
Host smart-6bc1d40f-b8b8-450d-ad21-b1ffb015c666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515571472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
515571472
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.1054400570
Short name T39
Test name
Test status
Simulation time 271103066781 ps
CPU time 1172.89 seconds
Started Jun 10 06:25:36 PM PDT 24
Finished Jun 10 06:45:10 PM PDT 24
Peak memory 205928 kb
Host smart-c4a12461-cec3-4e21-9589-3792da3d5194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054400570 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.1054400570
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1080920487
Short name T411
Test name
Test status
Simulation time 12687736482 ps
CPU time 13.24 seconds
Started Jun 10 06:25:38 PM PDT 24
Finished Jun 10 06:25:52 PM PDT 24
Peak memory 183056 kb
Host smart-e868fe4e-11fc-4dfb-b59f-37029ed01d88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080920487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1080920487
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1251990959
Short name T402
Test name
Test status
Simulation time 133728964587 ps
CPU time 204.89 seconds
Started Jun 10 06:25:36 PM PDT 24
Finished Jun 10 06:29:01 PM PDT 24
Peak memory 183060 kb
Host smart-ce09c0a9-8819-4a6d-9a20-6c14f3b53347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251990959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1251990959
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2511920765
Short name T181
Test name
Test status
Simulation time 43103584808 ps
CPU time 1289.64 seconds
Started Jun 10 06:25:35 PM PDT 24
Finished Jun 10 06:47:05 PM PDT 24
Peak memory 191276 kb
Host smart-035964ab-02b8-499e-b5c9-7190880a42b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511920765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2511920765
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3027956827
Short name T20
Test name
Test status
Simulation time 61046679217 ps
CPU time 101.52 seconds
Started Jun 10 06:25:42 PM PDT 24
Finished Jun 10 06:27:24 PM PDT 24
Peak memory 194520 kb
Host smart-8c9f8e03-0f50-44f0-8d85-157af94575d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027956827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3027956827
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3246956775
Short name T364
Test name
Test status
Simulation time 1095866172977 ps
CPU time 491.36 seconds
Started Jun 10 06:25:43 PM PDT 24
Finished Jun 10 06:33:55 PM PDT 24
Peak memory 191212 kb
Host smart-3d0aa658-9938-48bb-820c-17faccf86f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246956775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3246956775
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1521805305
Short name T293
Test name
Test status
Simulation time 219478047848 ps
CPU time 142.74 seconds
Started Jun 10 06:25:50 PM PDT 24
Finished Jun 10 06:28:13 PM PDT 24
Peak memory 183076 kb
Host smart-bfb3eb67-c9d6-4f9c-915e-62b7a26836fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521805305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1521805305
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random.1723018218
Short name T216
Test name
Test status
Simulation time 2793564507761 ps
CPU time 989.04 seconds
Started Jun 10 06:25:42 PM PDT 24
Finished Jun 10 06:42:12 PM PDT 24
Peak memory 193880 kb
Host smart-b1b64281-6c36-4686-a037-862faeb84637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723018218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1723018218
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.4170341563
Short name T427
Test name
Test status
Simulation time 42315612333 ps
CPU time 27.06 seconds
Started Jun 10 06:25:46 PM PDT 24
Finished Jun 10 06:26:14 PM PDT 24
Peak memory 191192 kb
Host smart-3157927f-a8b3-4c27-9312-e0861701321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170341563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.4170341563
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.679361432
Short name T245
Test name
Test status
Simulation time 313704913448 ps
CPU time 3748.11 seconds
Started Jun 10 06:25:48 PM PDT 24
Finished Jun 10 07:28:17 PM PDT 24
Peak memory 191268 kb
Host smart-e36afec2-97bc-4eae-9de9-a67de9e26fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679361432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
679361432
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.230364570
Short name T370
Test name
Test status
Simulation time 34494851083 ps
CPU time 21.47 seconds
Started Jun 10 06:25:50 PM PDT 24
Finished Jun 10 06:26:12 PM PDT 24
Peak memory 183060 kb
Host smart-cbdd5798-2a11-4917-802b-8a2239e8d83e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230364570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.230364570
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2495359324
Short name T361
Test name
Test status
Simulation time 33396253881 ps
CPU time 18.2 seconds
Started Jun 10 06:25:51 PM PDT 24
Finished Jun 10 06:26:10 PM PDT 24
Peak memory 183060 kb
Host smart-688681f0-c955-4ff8-8e8d-d555d78a01a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495359324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2495359324
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1315121044
Short name T143
Test name
Test status
Simulation time 2298168325247 ps
CPU time 953.75 seconds
Started Jun 10 06:25:52 PM PDT 24
Finished Jun 10 06:41:46 PM PDT 24
Peak memory 191248 kb
Host smart-7fe239b3-fb85-44b2-a9af-38d0a8926c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315121044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1315121044
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1246889642
Short name T422
Test name
Test status
Simulation time 4122534364 ps
CPU time 7.82 seconds
Started Jun 10 06:25:52 PM PDT 24
Finished Jun 10 06:26:00 PM PDT 24
Peak memory 183036 kb
Host smart-c2ae4736-dd91-426a-8be2-28d7f71f1db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246889642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1246889642
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1488857102
Short name T65
Test name
Test status
Simulation time 199958003 ps
CPU time 0.55 seconds
Started Jun 10 06:25:52 PM PDT 24
Finished Jun 10 06:25:52 PM PDT 24
Peak memory 182772 kb
Host smart-37d9fd21-f2ae-497d-a971-f7122b9fa2a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488857102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1488857102
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1912557447
Short name T211
Test name
Test status
Simulation time 40844694099 ps
CPU time 40.12 seconds
Started Jun 10 06:25:55 PM PDT 24
Finished Jun 10 06:26:35 PM PDT 24
Peak memory 182964 kb
Host smart-a91a8d03-de07-469e-b007-03e2374ef72d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912557447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1912557447
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.495827322
Short name T398
Test name
Test status
Simulation time 115435481288 ps
CPU time 21.6 seconds
Started Jun 10 06:25:55 PM PDT 24
Finished Jun 10 06:26:16 PM PDT 24
Peak memory 183020 kb
Host smart-dfeea121-44c2-4f18-b80f-9e7742130509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495827322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.495827322
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1287851501
Short name T170
Test name
Test status
Simulation time 77136967355 ps
CPU time 178.54 seconds
Started Jun 10 06:25:55 PM PDT 24
Finished Jun 10 06:28:54 PM PDT 24
Peak memory 191284 kb
Host smart-74cc31f6-5b3b-45e0-9269-20e2f695597f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287851501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1287851501
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2904516437
Short name T218
Test name
Test status
Simulation time 401351672767 ps
CPU time 180.42 seconds
Started Jun 10 06:25:59 PM PDT 24
Finished Jun 10 06:29:00 PM PDT 24
Peak memory 183016 kb
Host smart-737a2257-5d07-4104-b376-3e387513b469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904516437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2904516437
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.4017591001
Short name T217
Test name
Test status
Simulation time 180309289421 ps
CPU time 545.77 seconds
Started Jun 10 06:25:59 PM PDT 24
Finished Jun 10 06:35:06 PM PDT 24
Peak memory 210400 kb
Host smart-f1c39a2a-bda1-4341-ba3e-d50b987b1f22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017591001 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.4017591001
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1941062315
Short name T275
Test name
Test status
Simulation time 68205807292 ps
CPU time 119.34 seconds
Started Jun 10 06:26:03 PM PDT 24
Finished Jun 10 06:28:02 PM PDT 24
Peak memory 183080 kb
Host smart-127691a9-2a16-4750-adb9-224854ebe6e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941062315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1941062315
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2945496662
Short name T403
Test name
Test status
Simulation time 18405756408 ps
CPU time 25.98 seconds
Started Jun 10 06:26:00 PM PDT 24
Finished Jun 10 06:26:26 PM PDT 24
Peak memory 183056 kb
Host smart-3d45f3b2-c192-4d9e-8027-9fb57310df05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945496662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2945496662
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3978043140
Short name T441
Test name
Test status
Simulation time 38534421630 ps
CPU time 357.91 seconds
Started Jun 10 06:26:00 PM PDT 24
Finished Jun 10 06:31:58 PM PDT 24
Peak memory 183044 kb
Host smart-6ab9116d-7f48-4037-86be-7f65a07e57ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978043140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3978043140
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1391837970
Short name T405
Test name
Test status
Simulation time 421575977 ps
CPU time 0.88 seconds
Started Jun 10 06:26:04 PM PDT 24
Finished Jun 10 06:26:05 PM PDT 24
Peak memory 182844 kb
Host smart-eb6d41f4-fb96-4b70-abbb-2b174e3e99a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391837970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1391837970
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2765497770
Short name T399
Test name
Test status
Simulation time 18099746643 ps
CPU time 9.63 seconds
Started Jun 10 06:23:24 PM PDT 24
Finished Jun 10 06:23:34 PM PDT 24
Peak memory 183152 kb
Host smart-b39f52e0-a21a-4206-9b1d-616dfacfd86a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765497770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2765497770
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.797690186
Short name T363
Test name
Test status
Simulation time 333190120985 ps
CPU time 282.63 seconds
Started Jun 10 06:23:25 PM PDT 24
Finished Jun 10 06:28:08 PM PDT 24
Peak memory 183044 kb
Host smart-0c8c7a1f-0f43-467d-84d1-f426c41294b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797690186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.797690186
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1552682266
Short name T25
Test name
Test status
Simulation time 29042081825 ps
CPU time 48.72 seconds
Started Jun 10 06:23:24 PM PDT 24
Finished Jun 10 06:24:13 PM PDT 24
Peak memory 182988 kb
Host smart-a173edca-0c95-45c8-b7f9-22edbd740d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552682266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1552682266
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2971728167
Short name T17
Test name
Test status
Simulation time 50212697 ps
CPU time 0.81 seconds
Started Jun 10 06:23:30 PM PDT 24
Finished Jun 10 06:23:31 PM PDT 24
Peak memory 214296 kb
Host smart-aca9e8c4-4267-4c4a-84b0-bb39824e8590
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971728167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2971728167
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.532375086
Short name T311
Test name
Test status
Simulation time 2638066303537 ps
CPU time 464.01 seconds
Started Jun 10 06:23:28 PM PDT 24
Finished Jun 10 06:31:12 PM PDT 24
Peak memory 191240 kb
Host smart-a925da86-e5af-41e1-8bc2-64147d83c60e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532375086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.532375086
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1680522027
Short name T76
Test name
Test status
Simulation time 66133669898 ps
CPU time 684.34 seconds
Started Jun 10 06:23:27 PM PDT 24
Finished Jun 10 06:34:52 PM PDT 24
Peak memory 205912 kb
Host smart-1d4214d2-625b-4cca-9d6f-7f61abc47754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680522027 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1680522027
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.423331989
Short name T21
Test name
Test status
Simulation time 201015824930 ps
CPU time 172.83 seconds
Started Jun 10 06:26:08 PM PDT 24
Finished Jun 10 06:29:01 PM PDT 24
Peak memory 183024 kb
Host smart-230ac62e-1942-43dc-be8b-02cb7726a4bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423331989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.423331989
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2213999062
Short name T75
Test name
Test status
Simulation time 373821172332 ps
CPU time 182.71 seconds
Started Jun 10 06:26:09 PM PDT 24
Finished Jun 10 06:29:12 PM PDT 24
Peak memory 183052 kb
Host smart-d64da3bf-af52-4191-8842-3d21b4fd3843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213999062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2213999062
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.688520113
Short name T113
Test name
Test status
Simulation time 1488789815607 ps
CPU time 358.43 seconds
Started Jun 10 06:26:03 PM PDT 24
Finished Jun 10 06:32:02 PM PDT 24
Peak memory 191296 kb
Host smart-8c1f8885-ad19-4250-bde2-dba9db9dd038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688520113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.688520113
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2989227264
Short name T44
Test name
Test status
Simulation time 256058240 ps
CPU time 0.65 seconds
Started Jun 10 06:26:07 PM PDT 24
Finished Jun 10 06:26:08 PM PDT 24
Peak memory 182836 kb
Host smart-37acfac9-ab22-4ed1-aa7e-cfaa9cd77c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989227264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2989227264
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3555326404
Short name T137
Test name
Test status
Simulation time 499470586064 ps
CPU time 418.92 seconds
Started Jun 10 06:26:14 PM PDT 24
Finished Jun 10 06:33:14 PM PDT 24
Peak memory 182988 kb
Host smart-d3319095-e6ab-4aef-927b-7f732fb2ca69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555326404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3555326404
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3179532048
Short name T437
Test name
Test status
Simulation time 220621932376 ps
CPU time 95.34 seconds
Started Jun 10 06:26:12 PM PDT 24
Finished Jun 10 06:27:47 PM PDT 24
Peak memory 183048 kb
Host smart-9ae2a8c5-2728-4253-889a-3dd2c733a1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179532048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3179532048
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1786739765
Short name T305
Test name
Test status
Simulation time 230266985354 ps
CPU time 208.76 seconds
Started Jun 10 06:26:08 PM PDT 24
Finished Jun 10 06:29:37 PM PDT 24
Peak memory 191272 kb
Host smart-820ea840-aa76-41ab-9b6d-374cecebf2ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786739765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1786739765
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3164399624
Short name T262
Test name
Test status
Simulation time 20878187174 ps
CPU time 38.58 seconds
Started Jun 10 06:26:15 PM PDT 24
Finished Jun 10 06:26:54 PM PDT 24
Peak memory 182944 kb
Host smart-43d19a0d-4ec2-47ee-b216-0f55a72bb90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164399624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3164399624
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.4065838849
Short name T421
Test name
Test status
Simulation time 759027581755 ps
CPU time 606.32 seconds
Started Jun 10 06:26:18 PM PDT 24
Finished Jun 10 06:36:25 PM PDT 24
Peak memory 191240 kb
Host smart-9e5dcf22-bcbd-43b3-b1d0-c5b1e9e66528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065838849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.4065838849
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.384936454
Short name T415
Test name
Test status
Simulation time 23426876695 ps
CPU time 162.78 seconds
Started Jun 10 06:26:14 PM PDT 24
Finished Jun 10 06:28:58 PM PDT 24
Peak memory 197652 kb
Host smart-062d804a-f051-4e59-964e-6dac8b3b1661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384936454 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.384936454
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.239816559
Short name T413
Test name
Test status
Simulation time 71628019140 ps
CPU time 108.21 seconds
Started Jun 10 06:26:20 PM PDT 24
Finished Jun 10 06:28:08 PM PDT 24
Peak memory 183000 kb
Host smart-fc329983-354d-4e94-95e9-699cda7e5426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239816559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.239816559
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3631571849
Short name T134
Test name
Test status
Simulation time 46260216388 ps
CPU time 76 seconds
Started Jun 10 06:26:19 PM PDT 24
Finished Jun 10 06:27:35 PM PDT 24
Peak memory 183056 kb
Host smart-cc2f1231-6150-4984-951c-36027c178801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631571849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3631571849
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2191581162
Short name T28
Test name
Test status
Simulation time 1323281106 ps
CPU time 1.16 seconds
Started Jun 10 06:26:26 PM PDT 24
Finished Jun 10 06:26:28 PM PDT 24
Peak memory 191436 kb
Host smart-7f36fb84-f888-4a1d-a9ba-9b693d289c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191581162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2191581162
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1168877689
Short name T429
Test name
Test status
Simulation time 139438017898 ps
CPU time 227.61 seconds
Started Jun 10 06:26:29 PM PDT 24
Finished Jun 10 06:30:17 PM PDT 24
Peak memory 183040 kb
Host smart-10c05617-87f9-4fb3-b425-694579287ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168877689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1168877689
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1190538379
Short name T246
Test name
Test status
Simulation time 622298454855 ps
CPU time 525.29 seconds
Started Jun 10 06:26:28 PM PDT 24
Finished Jun 10 06:35:14 PM PDT 24
Peak memory 191272 kb
Host smart-697a3747-1f49-473d-b9d7-ce6d84ce6c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190538379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1190538379
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2811414743
Short name T444
Test name
Test status
Simulation time 52318075 ps
CPU time 0.54 seconds
Started Jun 10 06:26:27 PM PDT 24
Finished Jun 10 06:26:28 PM PDT 24
Peak memory 182824 kb
Host smart-88563fb5-89a0-4614-9048-0bd622767f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811414743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2811414743
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2640347359
Short name T34
Test name
Test status
Simulation time 19168671621 ps
CPU time 144.32 seconds
Started Jun 10 06:26:28 PM PDT 24
Finished Jun 10 06:28:52 PM PDT 24
Peak memory 197700 kb
Host smart-79d51443-a198-4e2e-9c52-2b8dfc0ed3da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640347359 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2640347359
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.4239072651
Short name T343
Test name
Test status
Simulation time 546654572661 ps
CPU time 320.43 seconds
Started Jun 10 06:26:30 PM PDT 24
Finished Jun 10 06:31:51 PM PDT 24
Peak memory 183056 kb
Host smart-e62aa919-a54a-4e81-917e-4069d9012aef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239072651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.4239072651
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3821949192
Short name T435
Test name
Test status
Simulation time 249030756365 ps
CPU time 107.42 seconds
Started Jun 10 06:26:31 PM PDT 24
Finished Jun 10 06:28:18 PM PDT 24
Peak memory 183144 kb
Host smart-d1ae9663-f1a1-4091-a10e-b420f1f2d279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821949192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3821949192
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1573733045
Short name T67
Test name
Test status
Simulation time 3744573166 ps
CPU time 3.96 seconds
Started Jun 10 06:26:30 PM PDT 24
Finished Jun 10 06:26:35 PM PDT 24
Peak memory 183084 kb
Host smart-a6e8270c-0a69-41f2-a013-a4e2e7995d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573733045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1573733045
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2553606522
Short name T359
Test name
Test status
Simulation time 19864836 ps
CPU time 0.54 seconds
Started Jun 10 06:26:31 PM PDT 24
Finished Jun 10 06:26:32 PM PDT 24
Peak memory 182848 kb
Host smart-d856bc96-63b4-4112-ad08-ae0fecaf62ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553606522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2553606522
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3068056282
Short name T225
Test name
Test status
Simulation time 2433921039288 ps
CPU time 846.68 seconds
Started Jun 10 06:26:31 PM PDT 24
Finished Jun 10 06:40:38 PM PDT 24
Peak memory 195752 kb
Host smart-cd18a50f-72dc-41b3-a9a0-219329287f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068056282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3068056282
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1806640606
Short name T6
Test name
Test status
Simulation time 1079757322385 ps
CPU time 659.8 seconds
Started Jun 10 06:26:35 PM PDT 24
Finished Jun 10 06:37:35 PM PDT 24
Peak memory 183072 kb
Host smart-f4e7d04e-fcfb-44f5-840f-3ce7ec093bce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806640606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1806640606
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2090024796
Short name T45
Test name
Test status
Simulation time 45481501074 ps
CPU time 66.42 seconds
Started Jun 10 06:26:31 PM PDT 24
Finished Jun 10 06:27:38 PM PDT 24
Peak memory 183052 kb
Host smart-d3be9ab7-09c3-45ac-b9ac-a9c7b81859be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090024796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2090024796
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1447666205
Short name T7
Test name
Test status
Simulation time 154892082507 ps
CPU time 117.48 seconds
Started Jun 10 06:26:31 PM PDT 24
Finished Jun 10 06:28:29 PM PDT 24
Peak memory 183084 kb
Host smart-8c1de117-28a2-457c-8d1e-978835dcca2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447666205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1447666205
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3293052740
Short name T315
Test name
Test status
Simulation time 319897950131 ps
CPU time 196.51 seconds
Started Jun 10 06:26:35 PM PDT 24
Finished Jun 10 06:29:52 PM PDT 24
Peak memory 191304 kb
Host smart-c32017fa-5554-4285-8947-b05765288aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293052740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3293052740
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.1788982174
Short name T350
Test name
Test status
Simulation time 25021677552 ps
CPU time 57.51 seconds
Started Jun 10 06:26:36 PM PDT 24
Finished Jun 10 06:27:34 PM PDT 24
Peak memory 197724 kb
Host smart-9e87fa61-0cd7-4a04-a6a5-51841f59ab28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788982174 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.1788982174
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1634883930
Short name T273
Test name
Test status
Simulation time 1039934061359 ps
CPU time 337.55 seconds
Started Jun 10 06:26:40 PM PDT 24
Finished Jun 10 06:32:18 PM PDT 24
Peak memory 183104 kb
Host smart-f98449c0-9a02-4774-8811-bd59224b3b25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634883930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1634883930
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1959489479
Short name T410
Test name
Test status
Simulation time 540477024183 ps
CPU time 189.19 seconds
Started Jun 10 06:26:40 PM PDT 24
Finished Jun 10 06:29:50 PM PDT 24
Peak memory 182944 kb
Host smart-9ccbd274-4c33-4586-8934-c06e35b5f1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959489479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1959489479
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3024181633
Short name T183
Test name
Test status
Simulation time 145247403345 ps
CPU time 420.93 seconds
Started Jun 10 06:26:40 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 191272 kb
Host smart-5aaed934-f7f1-44c8-8587-ed17c1b60c65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024181633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3024181633
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3113285481
Short name T88
Test name
Test status
Simulation time 152425588867 ps
CPU time 382.14 seconds
Started Jun 10 06:26:40 PM PDT 24
Finished Jun 10 06:33:02 PM PDT 24
Peak memory 191256 kb
Host smart-3fa19201-2d78-45f7-9974-4a5de7cb66f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113285481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3113285481
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1092978464
Short name T47
Test name
Test status
Simulation time 1084542835938 ps
CPU time 449.34 seconds
Started Jun 10 06:26:45 PM PDT 24
Finished Jun 10 06:34:14 PM PDT 24
Peak memory 191308 kb
Host smart-cd2238c8-cf0e-454a-a36f-c175bf6cd41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092978464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1092978464
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2224355915
Short name T36
Test name
Test status
Simulation time 42910694320 ps
CPU time 463.03 seconds
Started Jun 10 06:26:40 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 205872 kb
Host smart-114f20a5-3c99-43d5-ad3b-e33c3ddd720c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224355915 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2224355915
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2260956873
Short name T416
Test name
Test status
Simulation time 2495547358 ps
CPU time 5 seconds
Started Jun 10 06:26:45 PM PDT 24
Finished Jun 10 06:26:50 PM PDT 24
Peak memory 183072 kb
Host smart-78d7eeab-0c8a-4e6b-919d-3f0e4240fdb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260956873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2260956873
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.179483127
Short name T393
Test name
Test status
Simulation time 144213944183 ps
CPU time 95.67 seconds
Started Jun 10 06:26:43 PM PDT 24
Finished Jun 10 06:28:18 PM PDT 24
Peak memory 183056 kb
Host smart-31beaa24-2d0e-4cee-9e47-fef87f5afce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179483127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.179483127
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1822856338
Short name T397
Test name
Test status
Simulation time 14331313 ps
CPU time 0.53 seconds
Started Jun 10 06:26:44 PM PDT 24
Finished Jun 10 06:26:45 PM PDT 24
Peak memory 182792 kb
Host smart-61053132-3462-41ce-88a9-dd0140028913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822856338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1822856338
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3944217991
Short name T35
Test name
Test status
Simulation time 29851024137 ps
CPU time 257.11 seconds
Started Jun 10 06:26:44 PM PDT 24
Finished Jun 10 06:31:01 PM PDT 24
Peak memory 205936 kb
Host smart-4dbd343d-86af-44f4-bdb0-6a78ae43d4e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944217991 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3944217991
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1761137570
Short name T277
Test name
Test status
Simulation time 94343272220 ps
CPU time 46.56 seconds
Started Jun 10 06:26:48 PM PDT 24
Finished Jun 10 06:27:35 PM PDT 24
Peak memory 183032 kb
Host smart-2f4b62d6-7a86-4a7c-8a5f-4b81417d047d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761137570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1761137570
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2787782117
Short name T451
Test name
Test status
Simulation time 265338834653 ps
CPU time 103.64 seconds
Started Jun 10 06:26:43 PM PDT 24
Finished Jun 10 06:28:27 PM PDT 24
Peak memory 183056 kb
Host smart-55e3b445-b378-4b7b-9fae-735dfb9e2d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787782117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2787782117
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1106208326
Short name T133
Test name
Test status
Simulation time 10782343553 ps
CPU time 98.76 seconds
Started Jun 10 06:26:46 PM PDT 24
Finished Jun 10 06:28:25 PM PDT 24
Peak memory 183056 kb
Host smart-b743e34a-65db-4bdb-a6cd-cefec5a7a54f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106208326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1106208326
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1274662285
Short name T355
Test name
Test status
Simulation time 6903875034 ps
CPU time 29.58 seconds
Started Jun 10 06:26:48 PM PDT 24
Finished Jun 10 06:27:17 PM PDT 24
Peak memory 183036 kb
Host smart-f8862fec-9dee-4f72-a5e6-0df59f9ba471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274662285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1274662285
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3594196183
Short name T299
Test name
Test status
Simulation time 746093856352 ps
CPU time 408 seconds
Started Jun 10 06:26:54 PM PDT 24
Finished Jun 10 06:33:43 PM PDT 24
Peak memory 191276 kb
Host smart-55e658ff-79a3-4b71-9580-f6f66c46211c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594196183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3594196183
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1408139458
Short name T208
Test name
Test status
Simulation time 57501534230 ps
CPU time 92.43 seconds
Started Jun 10 06:26:52 PM PDT 24
Finished Jun 10 06:28:25 PM PDT 24
Peak memory 183044 kb
Host smart-8e046925-6679-40fb-b265-170211b5bf50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408139458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1408139458
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2180412039
Short name T90
Test name
Test status
Simulation time 165795174417 ps
CPU time 264.4 seconds
Started Jun 10 06:26:51 PM PDT 24
Finished Jun 10 06:31:16 PM PDT 24
Peak memory 182992 kb
Host smart-2ac383bf-28ec-416b-b2e9-7d5f56467a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180412039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2180412039
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2312555885
Short name T70
Test name
Test status
Simulation time 685977930943 ps
CPU time 244.62 seconds
Started Jun 10 06:26:54 PM PDT 24
Finished Jun 10 06:30:59 PM PDT 24
Peak memory 191264 kb
Host smart-a7940c07-3008-44f9-9364-75ee5c61a431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312555885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2312555885
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2322292542
Short name T331
Test name
Test status
Simulation time 76739294570 ps
CPU time 87.81 seconds
Started Jun 10 06:26:53 PM PDT 24
Finished Jun 10 06:28:21 PM PDT 24
Peak memory 191096 kb
Host smart-89a0c0ce-e8f4-4818-a863-411381365f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322292542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2322292542
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1824585432
Short name T266
Test name
Test status
Simulation time 6811458914 ps
CPU time 3.3 seconds
Started Jun 10 06:26:52 PM PDT 24
Finished Jun 10 06:26:56 PM PDT 24
Peak memory 191192 kb
Host smart-3ede6af5-d4df-4c66-a51e-9250a708d4b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824585432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1824585432
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2675207897
Short name T22
Test name
Test status
Simulation time 290816000394 ps
CPU time 509.62 seconds
Started Jun 10 06:23:28 PM PDT 24
Finished Jun 10 06:31:58 PM PDT 24
Peak memory 183004 kb
Host smart-7b3d598f-31ac-4dc6-9112-1dc42903f97c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675207897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2675207897
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1147103503
Short name T362
Test name
Test status
Simulation time 9137860801 ps
CPU time 14.97 seconds
Started Jun 10 06:23:26 PM PDT 24
Finished Jun 10 06:23:41 PM PDT 24
Peak memory 183020 kb
Host smart-bbb70e87-bafc-4a8a-96f8-d73751e681ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147103503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1147103503
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2844030110
Short name T430
Test name
Test status
Simulation time 96802694692 ps
CPU time 116.06 seconds
Started Jun 10 06:23:27 PM PDT 24
Finished Jun 10 06:25:23 PM PDT 24
Peak memory 183044 kb
Host smart-1a0c61ee-b513-4dea-be00-f7831c76abc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844030110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2844030110
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3499147719
Short name T62
Test name
Test status
Simulation time 148355834246 ps
CPU time 189.39 seconds
Started Jun 10 06:23:28 PM PDT 24
Finished Jun 10 06:26:38 PM PDT 24
Peak memory 183104 kb
Host smart-533fc359-28e8-4668-9a91-d36a3e7270ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499147719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3499147719
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1290074192
Short name T14
Test name
Test status
Simulation time 40480909726 ps
CPU time 175.99 seconds
Started Jun 10 06:23:33 PM PDT 24
Finished Jun 10 06:26:30 PM PDT 24
Peak memory 205840 kb
Host smart-b3d8c345-46dc-4898-ad32-ce47d8c4614a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290074192 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1290074192
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.rv_timer_random.1583863124
Short name T382
Test name
Test status
Simulation time 438207046545 ps
CPU time 108.08 seconds
Started Jun 10 06:26:57 PM PDT 24
Finished Jun 10 06:28:45 PM PDT 24
Peak memory 183176 kb
Host smart-b05e18d6-14a1-4feb-83a7-b128b95563a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583863124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1583863124
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.799122359
Short name T219
Test name
Test status
Simulation time 23325765998 ps
CPU time 46.56 seconds
Started Jun 10 06:26:56 PM PDT 24
Finished Jun 10 06:27:43 PM PDT 24
Peak memory 191172 kb
Host smart-8300c7e2-e90c-4452-83f6-0e4f18d8d842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799122359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.799122359
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2013582711
Short name T442
Test name
Test status
Simulation time 54078092992 ps
CPU time 239.08 seconds
Started Jun 10 06:26:56 PM PDT 24
Finished Jun 10 06:30:55 PM PDT 24
Peak memory 183068 kb
Host smart-57f63097-8b62-4255-afb7-cbecfc09da09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013582711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2013582711
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2643233837
Short name T168
Test name
Test status
Simulation time 132184168053 ps
CPU time 536.18 seconds
Started Jun 10 06:27:00 PM PDT 24
Finished Jun 10 06:35:57 PM PDT 24
Peak memory 191288 kb
Host smart-35aff78a-6000-4a70-8c70-1727267862c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643233837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2643233837
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.613258251
Short name T46
Test name
Test status
Simulation time 706807972601 ps
CPU time 344.68 seconds
Started Jun 10 06:27:02 PM PDT 24
Finished Jun 10 06:32:47 PM PDT 24
Peak memory 191224 kb
Host smart-67878e94-8c78-495a-8415-1c4c9a36d6f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613258251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.613258251
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3690278775
Short name T152
Test name
Test status
Simulation time 114109982065 ps
CPU time 130.65 seconds
Started Jun 10 06:27:00 PM PDT 24
Finished Jun 10 06:29:10 PM PDT 24
Peak memory 191276 kb
Host smart-83c4d09d-31c3-4865-8c4d-2cb3921d351f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690278775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3690278775
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2287356320
Short name T247
Test name
Test status
Simulation time 367174536678 ps
CPU time 439.55 seconds
Started Jun 10 06:27:01 PM PDT 24
Finished Jun 10 06:34:21 PM PDT 24
Peak memory 191284 kb
Host smart-4f8b5594-8406-4fa1-bcba-5f891a6c3cef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287356320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2287356320
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.55844544
Short name T319
Test name
Test status
Simulation time 40610037727 ps
CPU time 340.46 seconds
Started Jun 10 06:27:01 PM PDT 24
Finished Jun 10 06:32:41 PM PDT 24
Peak memory 183080 kb
Host smart-0d49d595-94bc-461b-8d45-25a41d12d3fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55844544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.55844544
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4126371912
Short name T198
Test name
Test status
Simulation time 172846538357 ps
CPU time 270.05 seconds
Started Jun 10 06:23:33 PM PDT 24
Finished Jun 10 06:28:03 PM PDT 24
Peak memory 183056 kb
Host smart-6c69d7a1-0e2f-4f7c-a34b-cfa9ee58ebc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126371912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4126371912
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1274371653
Short name T357
Test name
Test status
Simulation time 384593781742 ps
CPU time 307.23 seconds
Started Jun 10 06:23:34 PM PDT 24
Finished Jun 10 06:28:41 PM PDT 24
Peak memory 182888 kb
Host smart-9e47a5a8-92c3-487c-85d7-942e5813cb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274371653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1274371653
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1492218542
Short name T148
Test name
Test status
Simulation time 16319775708 ps
CPU time 16.23 seconds
Started Jun 10 06:23:31 PM PDT 24
Finished Jun 10 06:23:47 PM PDT 24
Peak memory 183088 kb
Host smart-43c41a10-b229-4676-a1e6-d0e200a46f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492218542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1492218542
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3460375138
Short name T349
Test name
Test status
Simulation time 64097603538 ps
CPU time 116.96 seconds
Started Jun 10 06:27:02 PM PDT 24
Finished Jun 10 06:28:59 PM PDT 24
Peak memory 193612 kb
Host smart-bd187505-d413-4bb8-9e9c-3ce4e59e6f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460375138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3460375138
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.636453946
Short name T304
Test name
Test status
Simulation time 223165018322 ps
CPU time 218.83 seconds
Started Jun 10 06:27:06 PM PDT 24
Finished Jun 10 06:30:45 PM PDT 24
Peak memory 191220 kb
Host smart-29869617-45ff-472e-abd2-930856c2ed78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636453946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.636453946
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.917463046
Short name T449
Test name
Test status
Simulation time 401074642982 ps
CPU time 236.29 seconds
Started Jun 10 06:27:04 PM PDT 24
Finished Jun 10 06:31:01 PM PDT 24
Peak memory 191252 kb
Host smart-8dd0da99-089b-4568-a294-b11ef807766e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917463046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.917463046
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1926114449
Short name T239
Test name
Test status
Simulation time 445548090718 ps
CPU time 423.75 seconds
Started Jun 10 06:27:05 PM PDT 24
Finished Jun 10 06:34:09 PM PDT 24
Peak memory 191232 kb
Host smart-0000d21e-08ed-4059-9e4a-6f22fa94f752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926114449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1926114449
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2324189772
Short name T84
Test name
Test status
Simulation time 70987688201 ps
CPU time 125.97 seconds
Started Jun 10 06:27:05 PM PDT 24
Finished Jun 10 06:29:12 PM PDT 24
Peak memory 191276 kb
Host smart-3977b668-0818-400e-8ccf-23bc583a616f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324189772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2324189772
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.950556991
Short name T194
Test name
Test status
Simulation time 130297166965 ps
CPU time 1483.08 seconds
Started Jun 10 06:27:05 PM PDT 24
Finished Jun 10 06:51:49 PM PDT 24
Peak memory 191276 kb
Host smart-27329bb5-e577-45bd-81e3-5acc1fcf79a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950556991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.950556991
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3274535225
Short name T423
Test name
Test status
Simulation time 38783861868 ps
CPU time 61.94 seconds
Started Jun 10 06:27:05 PM PDT 24
Finished Jun 10 06:28:07 PM PDT 24
Peak memory 183080 kb
Host smart-8f6660e8-0811-4fe7-a09b-639cd5f0ebc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274535225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3274535225
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2345306291
Short name T197
Test name
Test status
Simulation time 119281277346 ps
CPU time 202.37 seconds
Started Jun 10 06:27:09 PM PDT 24
Finished Jun 10 06:30:32 PM PDT 24
Peak memory 193384 kb
Host smart-c6d6e7a7-ec16-4592-a0df-53dfe8eb6699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345306291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2345306291
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.129554068
Short name T154
Test name
Test status
Simulation time 91497806488 ps
CPU time 113.63 seconds
Started Jun 10 06:27:09 PM PDT 24
Finished Jun 10 06:29:03 PM PDT 24
Peak memory 183028 kb
Host smart-93a66716-f6cb-4dbf-9a13-f9b9a535500a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129554068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.129554068
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2414735230
Short name T286
Test name
Test status
Simulation time 14274595225 ps
CPU time 27.88 seconds
Started Jun 10 06:23:35 PM PDT 24
Finished Jun 10 06:24:03 PM PDT 24
Peak memory 183016 kb
Host smart-d0f8c292-af81-4dc9-bce4-2d5da6c6da29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414735230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2414735230
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2026806886
Short name T69
Test name
Test status
Simulation time 217384615841 ps
CPU time 151.5 seconds
Started Jun 10 06:23:37 PM PDT 24
Finished Jun 10 06:26:08 PM PDT 24
Peak memory 183056 kb
Host smart-dcc6ba28-be50-4269-b936-3b9cbf366a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026806886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2026806886
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2166478581
Short name T341
Test name
Test status
Simulation time 22369778018 ps
CPU time 37.47 seconds
Started Jun 10 06:23:33 PM PDT 24
Finished Jun 10 06:24:11 PM PDT 24
Peak memory 183000 kb
Host smart-8c9a6ea2-9cc1-4f14-8509-4252c39e07ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166478581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2166478581
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.246288682
Short name T414
Test name
Test status
Simulation time 112785045406 ps
CPU time 177.51 seconds
Started Jun 10 06:27:10 PM PDT 24
Finished Jun 10 06:30:08 PM PDT 24
Peak memory 191252 kb
Host smart-ba06ae14-0421-4166-a60e-a01d9b1754e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246288682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.246288682
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.552548590
Short name T396
Test name
Test status
Simulation time 159498944059 ps
CPU time 67.25 seconds
Started Jun 10 06:27:14 PM PDT 24
Finished Jun 10 06:28:22 PM PDT 24
Peak memory 183096 kb
Host smart-d1f689cb-f64d-448f-91bf-cec233d6d1ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552548590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.552548590
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2805768767
Short name T222
Test name
Test status
Simulation time 347228110299 ps
CPU time 579.65 seconds
Started Jun 10 06:27:14 PM PDT 24
Finished Jun 10 06:36:54 PM PDT 24
Peak memory 191284 kb
Host smart-013dae21-94cb-4b12-9854-7f6a62c81624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805768767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2805768767
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.739590469
Short name T73
Test name
Test status
Simulation time 111115862278 ps
CPU time 96 seconds
Started Jun 10 06:27:13 PM PDT 24
Finished Jun 10 06:28:50 PM PDT 24
Peak memory 183044 kb
Host smart-6f79c24e-f73c-4676-b026-48029b14db59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739590469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.739590469
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1835898275
Short name T89
Test name
Test status
Simulation time 84366345128 ps
CPU time 197.35 seconds
Started Jun 10 06:27:16 PM PDT 24
Finished Jun 10 06:30:33 PM PDT 24
Peak memory 191272 kb
Host smart-2b770200-7f8d-4d09-a6a7-391863020430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835898275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1835898275
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1670183935
Short name T27
Test name
Test status
Simulation time 708406777718 ps
CPU time 924.3 seconds
Started Jun 10 06:27:14 PM PDT 24
Finished Jun 10 06:42:39 PM PDT 24
Peak memory 191268 kb
Host smart-cd409f03-5869-45b8-a2d1-999bebf95106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670183935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1670183935
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1573210396
Short name T131
Test name
Test status
Simulation time 97670720900 ps
CPU time 1393.85 seconds
Started Jun 10 06:27:13 PM PDT 24
Finished Jun 10 06:50:28 PM PDT 24
Peak memory 191244 kb
Host smart-8265ca7e-76c6-4709-bf3e-4691adc9c4ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573210396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1573210396
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1201568956
Short name T347
Test name
Test status
Simulation time 9029250836 ps
CPU time 12.74 seconds
Started Jun 10 06:27:21 PM PDT 24
Finished Jun 10 06:27:35 PM PDT 24
Peak memory 182960 kb
Host smart-c575a54b-ecc5-40d5-b81a-eaf5f5edcb8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201568956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1201568956
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3727577191
Short name T233
Test name
Test status
Simulation time 118635321480 ps
CPU time 327.8 seconds
Started Jun 10 06:27:20 PM PDT 24
Finished Jun 10 06:32:48 PM PDT 24
Peak memory 191292 kb
Host smart-ebeaec61-1173-43b5-8214-418d528021ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727577191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3727577191
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.943093474
Short name T336
Test name
Test status
Simulation time 815156430748 ps
CPU time 470.66 seconds
Started Jun 10 06:27:20 PM PDT 24
Finished Jun 10 06:35:11 PM PDT 24
Peak memory 191256 kb
Host smart-dba9c6d1-1ba5-4817-8ceb-3cb14023869d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943093474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.943093474
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3142514630
Short name T334
Test name
Test status
Simulation time 368200959660 ps
CPU time 581.22 seconds
Started Jun 10 06:23:36 PM PDT 24
Finished Jun 10 06:33:18 PM PDT 24
Peak memory 183072 kb
Host smart-d20d06a5-f37b-451c-a8e4-d497f7b67f70
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142514630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3142514630
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1216803811
Short name T380
Test name
Test status
Simulation time 330082406839 ps
CPU time 133.91 seconds
Started Jun 10 06:23:36 PM PDT 24
Finished Jun 10 06:25:50 PM PDT 24
Peak memory 183040 kb
Host smart-a39b5725-3075-4388-80b0-dbd64ab19966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216803811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1216803811
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3093479234
Short name T210
Test name
Test status
Simulation time 214489317885 ps
CPU time 206.17 seconds
Started Jun 10 06:23:37 PM PDT 24
Finished Jun 10 06:27:03 PM PDT 24
Peak memory 191264 kb
Host smart-0847e011-6bd6-499f-abcc-66ae2936be96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093479234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3093479234
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.4260679566
Short name T142
Test name
Test status
Simulation time 376967320899 ps
CPU time 259.34 seconds
Started Jun 10 06:23:35 PM PDT 24
Finished Jun 10 06:27:54 PM PDT 24
Peak memory 182972 kb
Host smart-966cab05-bbb6-4c59-ae54-24870fca0764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260679566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.4260679566
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.175252156
Short name T38
Test name
Test status
Simulation time 47313706947 ps
CPU time 175.96 seconds
Started Jun 10 06:23:35 PM PDT 24
Finished Jun 10 06:26:31 PM PDT 24
Peak memory 197712 kb
Host smart-c51f8692-0019-4ca2-84b2-9bb5765f3d46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175252156 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.175252156
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.594156825
Short name T431
Test name
Test status
Simulation time 121790129875 ps
CPU time 137.28 seconds
Started Jun 10 06:27:21 PM PDT 24
Finished Jun 10 06:29:39 PM PDT 24
Peak memory 191212 kb
Host smart-33914f8a-8130-43de-a8e0-20efc83f86b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594156825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.594156825
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.814638584
Short name T174
Test name
Test status
Simulation time 475313654475 ps
CPU time 346.19 seconds
Started Jun 10 06:27:20 PM PDT 24
Finished Jun 10 06:33:07 PM PDT 24
Peak memory 191224 kb
Host smart-bddccb64-acaa-4917-b925-fc91a3d58948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814638584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.814638584
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3396980006
Short name T268
Test name
Test status
Simulation time 28992235658 ps
CPU time 15.08 seconds
Started Jun 10 06:27:18 PM PDT 24
Finished Jun 10 06:27:33 PM PDT 24
Peak memory 183020 kb
Host smart-5ef47037-2ee6-4517-9287-585d04fdb100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396980006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3396980006
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3762237587
Short name T310
Test name
Test status
Simulation time 28802445703 ps
CPU time 53 seconds
Started Jun 10 06:27:22 PM PDT 24
Finished Jun 10 06:28:15 PM PDT 24
Peak memory 183040 kb
Host smart-8e2a8590-9e8a-4a5e-a4c6-66e81d1164d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762237587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3762237587
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2253133291
Short name T176
Test name
Test status
Simulation time 195447453993 ps
CPU time 1185.11 seconds
Started Jun 10 06:27:20 PM PDT 24
Finished Jun 10 06:47:05 PM PDT 24
Peak memory 191268 kb
Host smart-7f66ce38-b682-4047-8d49-fb93c479f226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253133291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2253133291
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1987510582
Short name T434
Test name
Test status
Simulation time 36796303662 ps
CPU time 17.9 seconds
Started Jun 10 06:27:21 PM PDT 24
Finished Jun 10 06:27:39 PM PDT 24
Peak memory 183084 kb
Host smart-a5930d67-7c80-4435-acda-6092062db83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987510582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1987510582
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.306893763
Short name T138
Test name
Test status
Simulation time 272598201761 ps
CPU time 143.7 seconds
Started Jun 10 06:27:23 PM PDT 24
Finished Jun 10 06:29:47 PM PDT 24
Peak memory 191276 kb
Host smart-84b0d32a-e42c-4d0a-a420-7f8ef7f492c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306893763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.306893763
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2303335175
Short name T241
Test name
Test status
Simulation time 161731237661 ps
CPU time 554.72 seconds
Started Jun 10 06:27:23 PM PDT 24
Finished Jun 10 06:36:38 PM PDT 24
Peak memory 191268 kb
Host smart-e040fe20-c7e5-44fc-8133-5db2132b89df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303335175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2303335175
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3612547717
Short name T253
Test name
Test status
Simulation time 174077787158 ps
CPU time 331.33 seconds
Started Jun 10 06:27:21 PM PDT 24
Finished Jun 10 06:32:53 PM PDT 24
Peak memory 193260 kb
Host smart-b84ab898-9ebe-42ab-91b1-f7ddcf25257f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612547717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3612547717
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1919558803
Short name T283
Test name
Test status
Simulation time 126663295159 ps
CPU time 194.6 seconds
Started Jun 10 06:23:42 PM PDT 24
Finished Jun 10 06:26:57 PM PDT 24
Peak memory 183056 kb
Host smart-bd46f32f-b37e-4f13-8945-7a33e40e5a3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919558803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1919558803
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.139451391
Short name T376
Test name
Test status
Simulation time 106521297640 ps
CPU time 155.92 seconds
Started Jun 10 06:23:42 PM PDT 24
Finished Jun 10 06:26:18 PM PDT 24
Peak memory 183048 kb
Host smart-a808ab43-7c5f-4a63-84d2-e73bc7367b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139451391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.139451391
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4160922161
Short name T276
Test name
Test status
Simulation time 26948803024 ps
CPU time 226.25 seconds
Started Jun 10 06:23:41 PM PDT 24
Finished Jun 10 06:27:27 PM PDT 24
Peak memory 183104 kb
Host smart-14b070f5-10bd-4e90-b12a-e41e77cab90d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160922161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4160922161
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3230367680
Short name T391
Test name
Test status
Simulation time 7993048570 ps
CPU time 68.39 seconds
Started Jun 10 06:23:40 PM PDT 24
Finished Jun 10 06:24:49 PM PDT 24
Peak memory 183060 kb
Host smart-aece5844-0ac3-4aab-b452-a6d64eec12d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230367680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3230367680
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.948633383
Short name T206
Test name
Test status
Simulation time 570259675617 ps
CPU time 396.19 seconds
Started Jun 10 06:23:41 PM PDT 24
Finished Jun 10 06:30:18 PM PDT 24
Peak memory 191260 kb
Host smart-15a5e5f6-ef61-4c6c-9bc2-8e60b11827a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948633383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.948633383
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.2187494120
Short name T261
Test name
Test status
Simulation time 158184215191 ps
CPU time 587.26 seconds
Started Jun 10 06:27:27 PM PDT 24
Finished Jun 10 06:37:15 PM PDT 24
Peak memory 191300 kb
Host smart-66f053bf-30eb-4915-b793-00bd0dcbafe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187494120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2187494120
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.333431010
Short name T425
Test name
Test status
Simulation time 64346339260 ps
CPU time 88.52 seconds
Started Jun 10 06:27:26 PM PDT 24
Finished Jun 10 06:28:55 PM PDT 24
Peak memory 191276 kb
Host smart-f54308df-e8ce-4114-a5b2-00a6fd65abf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333431010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.333431010
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1322734075
Short name T295
Test name
Test status
Simulation time 217996279115 ps
CPU time 613.56 seconds
Started Jun 10 06:27:29 PM PDT 24
Finished Jun 10 06:37:43 PM PDT 24
Peak memory 191196 kb
Host smart-6d2151de-8b0e-4366-8e06-d60e9abd1611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322734075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1322734075
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2410156829
Short name T196
Test name
Test status
Simulation time 97861474709 ps
CPU time 217.23 seconds
Started Jun 10 06:27:26 PM PDT 24
Finished Jun 10 06:31:03 PM PDT 24
Peak memory 191268 kb
Host smart-36e82f91-cdbe-4a5d-9b55-833eb9e22529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410156829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2410156829
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1482278803
Short name T5
Test name
Test status
Simulation time 123495721575 ps
CPU time 108.55 seconds
Started Jun 10 06:27:27 PM PDT 24
Finished Jun 10 06:29:15 PM PDT 24
Peak memory 191284 kb
Host smart-9bba5704-bfdb-4349-a12b-66d36d051536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482278803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1482278803
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1615222321
Short name T300
Test name
Test status
Simulation time 114590600712 ps
CPU time 269.46 seconds
Started Jun 10 06:27:31 PM PDT 24
Finished Jun 10 06:32:00 PM PDT 24
Peak memory 191260 kb
Host smart-9ddfbadc-ff56-41d9-865b-d512be56d276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615222321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1615222321
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.996410339
Short name T153
Test name
Test status
Simulation time 76535492103 ps
CPU time 304.85 seconds
Started Jun 10 06:27:30 PM PDT 24
Finished Jun 10 06:32:36 PM PDT 24
Peak memory 182952 kb
Host smart-c18a8d46-cccf-47e4-bc46-69cfbaee69fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996410339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.996410339
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2193986483
Short name T139
Test name
Test status
Simulation time 55171502830 ps
CPU time 85.4 seconds
Started Jun 10 06:27:31 PM PDT 24
Finished Jun 10 06:28:57 PM PDT 24
Peak memory 191256 kb
Host smart-6cc93c94-6fcb-4a22-9971-215f9ade855f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193986483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2193986483
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2626202384
Short name T10
Test name
Test status
Simulation time 29332887369 ps
CPU time 13.71 seconds
Started Jun 10 06:27:30 PM PDT 24
Finished Jun 10 06:27:44 PM PDT 24
Peak memory 183028 kb
Host smart-b47af9b6-41c5-4be6-84e4-8f60a3814fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626202384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2626202384
Directory /workspace/99.rv_timer_random/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%