Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 585
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T512 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2755855074 Jun 11 12:22:56 PM PDT 24 Jun 11 12:23:00 PM PDT 24 32345037 ps
T513 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2875109154 Jun 11 12:22:09 PM PDT 24 Jun 11 12:22:12 PM PDT 24 30493797 ps
T514 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2918892098 Jun 11 12:18:53 PM PDT 24 Jun 11 12:18:54 PM PDT 24 47786606 ps
T515 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.124312873 Jun 11 12:17:10 PM PDT 24 Jun 11 12:17:12 PM PDT 24 36245145 ps
T516 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1902147610 Jun 11 12:22:51 PM PDT 24 Jun 11 12:22:53 PM PDT 24 16753169 ps
T517 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1475327387 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:34 PM PDT 24 38595198 ps
T518 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4118096368 Jun 11 12:22:28 PM PDT 24 Jun 11 12:22:31 PM PDT 24 15312230 ps
T89 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.520944187 Jun 11 12:22:28 PM PDT 24 Jun 11 12:22:31 PM PDT 24 15216131 ps
T519 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2495005595 Jun 11 12:19:51 PM PDT 24 Jun 11 12:19:53 PM PDT 24 27882146 ps
T520 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1167956139 Jun 11 12:22:29 PM PDT 24 Jun 11 12:22:35 PM PDT 24 67324373 ps
T521 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3915075124 Jun 11 12:23:07 PM PDT 24 Jun 11 12:23:09 PM PDT 24 55127019 ps
T90 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.647721890 Jun 11 12:22:50 PM PDT 24 Jun 11 12:22:53 PM PDT 24 12561361 ps
T522 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.85061887 Jun 11 12:22:31 PM PDT 24 Jun 11 12:22:35 PM PDT 24 35199487 ps
T523 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1391500608 Jun 11 12:19:27 PM PDT 24 Jun 11 12:19:28 PM PDT 24 24818604 ps
T524 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3175541005 Jun 11 12:19:26 PM PDT 24 Jun 11 12:19:27 PM PDT 24 15489975 ps
T105 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.474185622 Jun 11 12:22:28 PM PDT 24 Jun 11 12:22:32 PM PDT 24 290637570 ps
T107 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1789749696 Jun 11 12:22:42 PM PDT 24 Jun 11 12:22:46 PM PDT 24 127961134 ps
T525 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.64082744 Jun 11 12:19:52 PM PDT 24 Jun 11 12:19:54 PM PDT 24 43613503 ps
T91 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3277085577 Jun 11 12:22:28 PM PDT 24 Jun 11 12:22:32 PM PDT 24 14499971 ps
T526 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.548063941 Jun 11 12:20:42 PM PDT 24 Jun 11 12:20:44 PM PDT 24 37550179 ps
T527 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2968909047 Jun 11 12:22:57 PM PDT 24 Jun 11 12:23:02 PM PDT 24 113414243 ps
T528 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2987386572 Jun 11 12:22:27 PM PDT 24 Jun 11 12:22:30 PM PDT 24 30630089 ps
T529 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1333296149 Jun 11 12:22:40 PM PDT 24 Jun 11 12:22:43 PM PDT 24 620066213 ps
T530 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3520596302 Jun 11 12:20:50 PM PDT 24 Jun 11 12:20:52 PM PDT 24 34581476 ps
T531 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2555423722 Jun 11 12:19:52 PM PDT 24 Jun 11 12:19:55 PM PDT 24 41288098 ps
T92 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1748852602 Jun 11 12:22:32 PM PDT 24 Jun 11 12:22:37 PM PDT 24 31083930 ps
T532 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1877383327 Jun 11 12:22:56 PM PDT 24 Jun 11 12:23:01 PM PDT 24 37339658 ps
T93 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1073522948 Jun 11 12:22:29 PM PDT 24 Jun 11 12:22:33 PM PDT 24 53404633 ps
T533 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.139665411 Jun 11 12:22:28 PM PDT 24 Jun 11 12:22:31 PM PDT 24 25227193 ps
T534 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3705991349 Jun 11 12:22:08 PM PDT 24 Jun 11 12:22:10 PM PDT 24 20219707 ps
T535 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1490213140 Jun 11 12:22:49 PM PDT 24 Jun 11 12:22:53 PM PDT 24 140332516 ps
T536 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.4039736857 Jun 11 12:23:36 PM PDT 24 Jun 11 12:23:40 PM PDT 24 43998668 ps
T537 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1969080587 Jun 11 12:22:08 PM PDT 24 Jun 11 12:22:10 PM PDT 24 47454556 ps
T538 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1043787620 Jun 11 12:22:53 PM PDT 24 Jun 11 12:22:56 PM PDT 24 11702548 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2814705807 Jun 11 12:17:23 PM PDT 24 Jun 11 12:17:26 PM PDT 24 630858009 ps
T540 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1199434518 Jun 11 12:22:53 PM PDT 24 Jun 11 12:22:55 PM PDT 24 60301143 ps
T541 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3623659970 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:34 PM PDT 24 13041770 ps
T542 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.919078718 Jun 11 12:22:23 PM PDT 24 Jun 11 12:22:26 PM PDT 24 799459141 ps
T543 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2463768239 Jun 11 12:19:38 PM PDT 24 Jun 11 12:19:39 PM PDT 24 59451094 ps
T544 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1325231689 Jun 11 12:22:06 PM PDT 24 Jun 11 12:22:10 PM PDT 24 103862194 ps
T545 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3626781586 Jun 11 12:22:30 PM PDT 24 Jun 11 12:22:34 PM PDT 24 34484615 ps
T546 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2318121502 Jun 11 12:17:27 PM PDT 24 Jun 11 12:17:30 PM PDT 24 564437854 ps
T94 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.771118754 Jun 11 12:20:12 PM PDT 24 Jun 11 12:20:13 PM PDT 24 17169943 ps
T547 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.796611281 Jun 11 12:20:48 PM PDT 24 Jun 11 12:20:49 PM PDT 24 58969373 ps
T95 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2976148813 Jun 11 12:22:42 PM PDT 24 Jun 11 12:22:45 PM PDT 24 129061864 ps
T548 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1724137886 Jun 11 12:22:57 PM PDT 24 Jun 11 12:23:02 PM PDT 24 110186995 ps
T549 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4152179891 Jun 11 12:22:48 PM PDT 24 Jun 11 12:22:51 PM PDT 24 14583451 ps
T550 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3097286005 Jun 11 12:22:32 PM PDT 24 Jun 11 12:22:37 PM PDT 24 143949874 ps
T551 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2568099936 Jun 11 12:20:06 PM PDT 24 Jun 11 12:20:07 PM PDT 24 25268145 ps
T552 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1603333230 Jun 11 12:22:43 PM PDT 24 Jun 11 12:22:46 PM PDT 24 55843429 ps
T553 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2643411436 Jun 11 12:17:14 PM PDT 24 Jun 11 12:17:17 PM PDT 24 849001048 ps
T554 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2028990609 Jun 11 12:18:13 PM PDT 24 Jun 11 12:18:14 PM PDT 24 14622543 ps
T555 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3744351493 Jun 11 12:22:06 PM PDT 24 Jun 11 12:22:11 PM PDT 24 205663690 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1389798284 Jun 11 12:17:08 PM PDT 24 Jun 11 12:17:10 PM PDT 24 186556320 ps
T557 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4131633622 Jun 11 12:22:48 PM PDT 24 Jun 11 12:22:51 PM PDT 24 40492005 ps
T97 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.877089885 Jun 11 12:22:40 PM PDT 24 Jun 11 12:22:42 PM PDT 24 25737824 ps
T558 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.722973232 Jun 11 12:22:07 PM PDT 24 Jun 11 12:22:10 PM PDT 24 418031414 ps
T559 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2829133796 Jun 11 12:17:54 PM PDT 24 Jun 11 12:17:55 PM PDT 24 13970506 ps
T560 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2264657379 Jun 11 12:22:34 PM PDT 24 Jun 11 12:22:40 PM PDT 24 207524197 ps
T561 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3122857663 Jun 11 12:19:52 PM PDT 24 Jun 11 12:19:55 PM PDT 24 16997642 ps
T562 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.959547222 Jun 11 12:23:17 PM PDT 24 Jun 11 12:23:18 PM PDT 24 164385730 ps
T563 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.972515066 Jun 11 12:19:52 PM PDT 24 Jun 11 12:19:54 PM PDT 24 22122792 ps
T564 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3997675551 Jun 11 12:23:22 PM PDT 24 Jun 11 12:23:26 PM PDT 24 66803745 ps
T565 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1739055550 Jun 11 12:22:54 PM PDT 24 Jun 11 12:22:58 PM PDT 24 625548232 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1751237807 Jun 11 12:22:07 PM PDT 24 Jun 11 12:22:09 PM PDT 24 38564785 ps
T567 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1561077502 Jun 11 12:22:09 PM PDT 24 Jun 11 12:22:12 PM PDT 24 13175087 ps
T568 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1898010371 Jun 11 12:22:07 PM PDT 24 Jun 11 12:22:10 PM PDT 24 168623759 ps
T569 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3260673413 Jun 11 12:22:56 PM PDT 24 Jun 11 12:23:01 PM PDT 24 35329375 ps
T570 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1586826897 Jun 11 12:17:09 PM PDT 24 Jun 11 12:17:11 PM PDT 24 154003141 ps
T571 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4234977512 Jun 11 12:17:55 PM PDT 24 Jun 11 12:17:56 PM PDT 24 235105677 ps
T572 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1096611516 Jun 11 12:19:08 PM PDT 24 Jun 11 12:19:09 PM PDT 24 12879643 ps
T573 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4011549904 Jun 11 12:22:58 PM PDT 24 Jun 11 12:23:03 PM PDT 24 12298102 ps
T96 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2412247151 Jun 11 12:21:33 PM PDT 24 Jun 11 12:21:34 PM PDT 24 65222327 ps
T574 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.155169675 Jun 11 12:18:00 PM PDT 24 Jun 11 12:18:01 PM PDT 24 48851393 ps
T575 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1806150481 Jun 11 12:18:04 PM PDT 24 Jun 11 12:18:05 PM PDT 24 15727160 ps
T576 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1841471164 Jun 11 12:22:41 PM PDT 24 Jun 11 12:22:46 PM PDT 24 1870719955 ps
T577 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2502919489 Jun 11 12:22:34 PM PDT 24 Jun 11 12:22:38 PM PDT 24 46690224 ps
T578 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4197104573 Jun 11 12:22:38 PM PDT 24 Jun 11 12:22:42 PM PDT 24 33983585 ps
T579 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2537420755 Jun 11 12:22:31 PM PDT 24 Jun 11 12:22:36 PM PDT 24 30190367 ps
T580 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2185728969 Jun 11 12:23:25 PM PDT 24 Jun 11 12:23:29 PM PDT 24 52802769 ps
T581 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1761481902 Jun 11 12:22:34 PM PDT 24 Jun 11 12:22:38 PM PDT 24 14355325 ps
T582 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1643353213 Jun 11 12:20:44 PM PDT 24 Jun 11 12:20:46 PM PDT 24 68099852 ps
T583 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4264972907 Jun 11 12:19:11 PM PDT 24 Jun 11 12:19:12 PM PDT 24 27450172 ps
T584 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2703546908 Jun 11 12:22:09 PM PDT 24 Jun 11 12:22:12 PM PDT 24 165658050 ps
T585 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2122820091 Jun 11 12:19:50 PM PDT 24 Jun 11 12:19:52 PM PDT 24 13694370 ps

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2291027360
Short name T9
Test name
Test status
Simulation time 95794640091 ps
CPU time 851.56 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:36:53 PM PDT 24
Peak memory 204904 kb
Host smart-1aeea039-05cb-4c73-86d7-456792124bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291027360 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2291027360
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.171539139
Short name T2
Test name
Test status
Simulation time 2803710457506 ps
CPU time 4245.66 seconds
Started Jun 11 12:18:50 PM PDT 24
Finished Jun 11 01:29:36 PM PDT 24
Peak memory 195776 kb
Host smart-404fcb16-5f7e-486f-843a-680436887592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171539139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
171539139
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3362379894
Short name T133
Test name
Test status
Simulation time 1538724353010 ps
CPU time 2870.59 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 01:10:25 PM PDT 24
Peak memory 190784 kb
Host smart-723e0209-09a8-4fe0-9560-ac8f890f5fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362379894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3362379894
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.465006243
Short name T16
Test name
Test status
Simulation time 137429117 ps
CPU time 0.73 seconds
Started Jun 11 12:20:07 PM PDT 24
Finished Jun 11 12:20:09 PM PDT 24
Peak memory 213188 kb
Host smart-b443760e-2c1a-4be1-88be-95054661d678
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465006243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.465006243
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.332586149
Short name T172
Test name
Test status
Simulation time 2997916951141 ps
CPU time 2295.52 seconds
Started Jun 11 12:22:58 PM PDT 24
Finished Jun 11 01:01:18 PM PDT 24
Peak memory 196384 kb
Host smart-2f0679e2-28a0-42bd-bb55-2dca196d5d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332586149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
332586149
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2010795265
Short name T158
Test name
Test status
Simulation time 5585249024877 ps
CPU time 4066.15 seconds
Started Jun 11 12:20:22 PM PDT 24
Finished Jun 11 01:28:09 PM PDT 24
Peak memory 191088 kb
Host smart-85edafc5-3e24-4f46-b202-9341f7a39438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010795265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2010795265
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3899280014
Short name T125
Test name
Test status
Simulation time 634106797140 ps
CPU time 1691.08 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:50:48 PM PDT 24
Peak memory 190800 kb
Host smart-bce37ff5-446c-4c23-aaaf-2fedfa67a6a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899280014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3899280014
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3277716663
Short name T27
Test name
Test status
Simulation time 537659150 ps
CPU time 1.05 seconds
Started Jun 11 12:22:44 PM PDT 24
Finished Jun 11 12:22:48 PM PDT 24
Peak memory 193068 kb
Host smart-765d39bf-0919-4159-8633-2b21c34e5230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277716663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3277716663
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3201819453
Short name T181
Test name
Test status
Simulation time 1416249647628 ps
CPU time 2945.15 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 01:12:09 PM PDT 24
Peak memory 195456 kb
Host smart-e63d1bf9-3620-4ba2-b141-7a382605c3fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201819453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3201819453
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2354848747
Short name T80
Test name
Test status
Simulation time 64619422 ps
CPU time 2.42 seconds
Started Jun 11 12:17:14 PM PDT 24
Finished Jun 11 12:17:18 PM PDT 24
Peak memory 193628 kb
Host smart-e11db4a3-f702-4de4-9025-8de0c136c83b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354848747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2354848747
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1913922139
Short name T230
Test name
Test status
Simulation time 976735220554 ps
CPU time 1403.44 seconds
Started Jun 11 12:22:13 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 194916 kb
Host smart-d50d41cc-f2d1-4f9a-a9f4-e1db6e76f5bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913922139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1913922139
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2128237413
Short name T67
Test name
Test status
Simulation time 638418803359 ps
CPU time 1277.41 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 190752 kb
Host smart-39addc7c-13d0-4b69-b9fe-41d1611b40de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128237413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2128237413
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/96.rv_timer_random.613796824
Short name T5
Test name
Test status
Simulation time 123871280777 ps
CPU time 299.85 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:27:11 PM PDT 24
Peak memory 191024 kb
Host smart-be987205-f3a2-4a82-8a67-0368d9f69862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613796824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.613796824
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3468092743
Short name T122
Test name
Test status
Simulation time 984735309432 ps
CPU time 433.26 seconds
Started Jun 11 12:23:06 PM PDT 24
Finished Jun 11 12:30:21 PM PDT 24
Peak memory 191056 kb
Host smart-39e7cc72-bd6e-46b5-a51b-905551fc834b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468092743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3468092743
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3770519684
Short name T160
Test name
Test status
Simulation time 2744172201225 ps
CPU time 1605.87 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:49:45 PM PDT 24
Peak memory 190812 kb
Host smart-f32ff452-3fbe-4e50-8272-45d49c531334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770519684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3770519684
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_random.1143660703
Short name T177
Test name
Test status
Simulation time 137817166878 ps
CPU time 325.57 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 194292 kb
Host smart-9e7dc9a7-bb76-43a4-ae57-f7c6581cf76f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143660703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1143660703
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3707482378
Short name T250
Test name
Test status
Simulation time 226798528184 ps
CPU time 1341.37 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:45:03 PM PDT 24
Peak memory 193936 kb
Host smart-16dbb977-ad22-4124-9a98-c64ba7d3e774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707482378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3707482378
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/108.rv_timer_random.891813694
Short name T19
Test name
Test status
Simulation time 162156400744 ps
CPU time 1738 seconds
Started Jun 11 12:22:22 PM PDT 24
Finished Jun 11 12:51:21 PM PDT 24
Peak memory 191020 kb
Host smart-9818abe2-cd26-4820-ac78-30b4af755d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891813694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.891813694
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3870981495
Short name T281
Test name
Test status
Simulation time 3211154544343 ps
CPU time 2404.76 seconds
Started Jun 11 12:22:48 PM PDT 24
Finished Jun 11 01:02:55 PM PDT 24
Peak memory 190708 kb
Host smart-92ed2b38-1383-4eda-b8e0-b2930db0dbbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870981495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3870981495
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.2064755965
Short name T198
Test name
Test status
Simulation time 385140961627 ps
CPU time 382.51 seconds
Started Jun 11 12:23:10 PM PDT 24
Finished Jun 11 12:29:33 PM PDT 24
Peak memory 191064 kb
Host smart-c07c18fd-0db7-466c-9e32-d915a0b541ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064755965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2064755965
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2231378548
Short name T277
Test name
Test status
Simulation time 397685661979 ps
CPU time 553.59 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:31:46 PM PDT 24
Peak memory 190768 kb
Host smart-063d6022-04e1-4c46-adac-761720ca3dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231378548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2231378548
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/68.rv_timer_random.3787932156
Short name T108
Test name
Test status
Simulation time 647615092313 ps
CPU time 519.88 seconds
Started Jun 11 12:23:21 PM PDT 24
Finished Jun 11 12:32:03 PM PDT 24
Peak memory 190892 kb
Host smart-a73aa1e9-2e91-4b27-97da-b3127d161732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787932156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3787932156
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1141786618
Short name T114
Test name
Test status
Simulation time 292428894108 ps
CPU time 1281.69 seconds
Started Jun 11 12:23:06 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 190932 kb
Host smart-720ed5a6-d47a-460a-ad9a-216b30a83c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141786618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1141786618
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1901682374
Short name T200
Test name
Test status
Simulation time 864420080019 ps
CPU time 2213 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:59:05 PM PDT 24
Peak memory 190960 kb
Host smart-41f58109-9ef9-4f10-9312-d376acc41d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901682374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1901682374
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.3280272950
Short name T109
Test name
Test status
Simulation time 767138007118 ps
CPU time 1925.05 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:55:05 PM PDT 24
Peak memory 190984 kb
Host smart-11d00350-000c-4b6d-8ef1-ffbb27cbec1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280272950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3280272950
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2421517387
Short name T63
Test name
Test status
Simulation time 391031106018 ps
CPU time 821.32 seconds
Started Jun 11 12:21:04 PM PDT 24
Finished Jun 11 12:34:46 PM PDT 24
Peak memory 191064 kb
Host smart-f1c3068c-940f-4a2c-a03c-df0ab175eeb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421517387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2421517387
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/145.rv_timer_random.920930065
Short name T120
Test name
Test status
Simulation time 852144274636 ps
CPU time 417.32 seconds
Started Jun 11 12:23:02 PM PDT 24
Finished Jun 11 12:30:03 PM PDT 24
Peak memory 191036 kb
Host smart-04e4b1d3-cd52-43e1-be4c-2db9ff5bd002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920930065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.920930065
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2143113784
Short name T186
Test name
Test status
Simulation time 1883944918884 ps
CPU time 1516.17 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:47:49 PM PDT 24
Peak memory 189740 kb
Host smart-63767b5f-ce77-4d56-88a7-5641f7b87674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143113784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2143113784
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2545429905
Short name T187
Test name
Test status
Simulation time 307976941700 ps
CPU time 644.25 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:33:10 PM PDT 24
Peak memory 190776 kb
Host smart-f6e95b79-13bd-4ff2-81b6-6f5a1025c7c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545429905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2545429905
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1990544955
Short name T211
Test name
Test status
Simulation time 2478711087513 ps
CPU time 2118.77 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:57:44 PM PDT 24
Peak memory 195832 kb
Host smart-e8954261-5c71-4299-8ea5-03f2f59ff0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990544955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1990544955
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2203789681
Short name T145
Test name
Test status
Simulation time 358711302572 ps
CPU time 175.58 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:25:29 PM PDT 24
Peak memory 182528 kb
Host smart-50f628a8-a02c-4f9c-b6ef-d1b6763e4ebd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203789681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2203789681
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.4294739141
Short name T260
Test name
Test status
Simulation time 316028127649 ps
CPU time 335.22 seconds
Started Jun 11 12:22:25 PM PDT 24
Finished Jun 11 12:28:02 PM PDT 24
Peak memory 191080 kb
Host smart-fe323d83-39e1-471c-958b-0384f70f91f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294739141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4294739141
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3729918971
Short name T290
Test name
Test status
Simulation time 116347570463 ps
CPU time 971.69 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:39:11 PM PDT 24
Peak memory 193296 kb
Host smart-f6bb0241-c0e5-4f20-a719-d6857cbc011c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729918971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3729918971
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3615662263
Short name T341
Test name
Test status
Simulation time 350507772549 ps
CPU time 631.49 seconds
Started Jun 11 12:20:10 PM PDT 24
Finished Jun 11 12:30:42 PM PDT 24
Peak memory 182876 kb
Host smart-5afdc84c-1e41-449e-afd9-6f5a16a10b16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615662263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3615662263
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3710664726
Short name T319
Test name
Test status
Simulation time 222809064780 ps
CPU time 360.72 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:28:49 PM PDT 24
Peak memory 182448 kb
Host smart-09c2badc-aa2b-4de0-a8a0-6702b0f56e92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710664726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3710664726
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4235949710
Short name T33
Test name
Test status
Simulation time 1942588612667 ps
CPU time 1060.7 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 190788 kb
Host smart-ac8f645b-205b-4bd9-b11d-05e1ff020597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235949710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4235949710
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1278033956
Short name T152
Test name
Test status
Simulation time 169441718806 ps
CPU time 277.68 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:28:23 PM PDT 24
Peak memory 191048 kb
Host smart-213234a9-864e-4d25-af70-54b4f3ea1b35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278033956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1278033956
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3390051625
Short name T151
Test name
Test status
Simulation time 2797058180140 ps
CPU time 585.29 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:32:29 PM PDT 24
Peak memory 182132 kb
Host smart-b7c38de1-8fb4-4f12-bf01-7324832be933
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390051625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3390051625
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/78.rv_timer_random.618158141
Short name T217
Test name
Test status
Simulation time 207152478003 ps
CPU time 843.85 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:37:33 PM PDT 24
Peak memory 191040 kb
Host smart-c75d1a8b-369f-485d-bb4b-71af13f0c387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618158141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.618158141
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2437367343
Short name T326
Test name
Test status
Simulation time 223596369257 ps
CPU time 277.67 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:27:04 PM PDT 24
Peak memory 189916 kb
Host smart-8a9c6d1a-806b-43b4-98c1-adc29909d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437367343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2437367343
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/117.rv_timer_random.1896573796
Short name T46
Test name
Test status
Simulation time 96175606071 ps
CPU time 1449.2 seconds
Started Jun 11 12:22:46 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 191028 kb
Host smart-5d1f43ed-f367-4f15-b8ff-e20dbbb2ec6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896573796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1896573796
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3797370372
Short name T324
Test name
Test status
Simulation time 305561265532 ps
CPU time 554.25 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:33:00 PM PDT 24
Peak memory 182848 kb
Host smart-d07da997-4cff-4c7c-aa0c-40d0781a5450
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797370372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3797370372
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.98150785
Short name T141
Test name
Test status
Simulation time 391973567291 ps
CPU time 716.2 seconds
Started Jun 11 12:23:38 PM PDT 24
Finished Jun 11 12:35:38 PM PDT 24
Peak memory 194952 kb
Host smart-0b7068ba-3fbd-4a3e-a541-a2e0b1219b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98150785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.98150785
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/152.rv_timer_random.2480820545
Short name T191
Test name
Test status
Simulation time 784774537961 ps
CPU time 259.63 seconds
Started Jun 11 12:23:03 PM PDT 24
Finished Jun 11 12:27:25 PM PDT 24
Peak memory 190988 kb
Host smart-c527496b-e5ff-468c-91a3-8e26ca6cf2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480820545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2480820545
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.2509491962
Short name T128
Test name
Test status
Simulation time 700411168911 ps
CPU time 803.96 seconds
Started Jun 11 12:22:08 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 189040 kb
Host smart-535697cb-a6d2-4c08-8e12-fe7e36b1f810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509491962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2509491962
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1128529925
Short name T297
Test name
Test status
Simulation time 80939018334 ps
CPU time 129.56 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:25:30 PM PDT 24
Peak memory 190992 kb
Host smart-0550ac2d-5fbb-42da-8866-9276a3ec2647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128529925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1128529925
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2515654063
Short name T220
Test name
Test status
Simulation time 1870388401906 ps
CPU time 586.38 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:33:20 PM PDT 24
Peak memory 191084 kb
Host smart-0033def9-1380-4b8b-a735-8f89e9de4dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515654063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2515654063
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2756160833
Short name T199
Test name
Test status
Simulation time 257008499558 ps
CPU time 339.6 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:29:00 PM PDT 24
Peak memory 191076 kb
Host smart-9587b9d1-d15c-4885-9e24-5657287094a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756160833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2756160833
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.3213888931
Short name T240
Test name
Test status
Simulation time 224680363121 ps
CPU time 623.44 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:33:23 PM PDT 24
Peak memory 190824 kb
Host smart-e5f5eb48-900d-4745-8210-5c9b398cd9eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213888931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3213888931
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.1843849202
Short name T174
Test name
Test status
Simulation time 293389733892 ps
CPU time 535 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:31:57 PM PDT 24
Peak memory 190980 kb
Host smart-7d051574-b86d-44c4-8b6a-678faf9bb4d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843849202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1843849202
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.663480056
Short name T273
Test name
Test status
Simulation time 458743495574 ps
CPU time 435.31 seconds
Started Jun 11 12:18:40 PM PDT 24
Finished Jun 11 12:25:56 PM PDT 24
Peak memory 191076 kb
Host smart-f0ee44d1-4417-44f1-acd2-20eb88a3a742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663480056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.663480056
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.2778908720
Short name T168
Test name
Test status
Simulation time 663448325804 ps
CPU time 366.16 seconds
Started Jun 11 12:20:33 PM PDT 24
Finished Jun 11 12:26:40 PM PDT 24
Peak memory 191444 kb
Host smart-8c74a775-20fa-4db4-b7a5-6fe195309b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778908720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2778908720
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.735715417
Short name T214
Test name
Test status
Simulation time 88995337036 ps
CPU time 252.44 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:27:33 PM PDT 24
Peak memory 190744 kb
Host smart-547313a4-724d-4e87-8574-c6c0bcee0b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735715417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.735715417
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1631101322
Short name T18
Test name
Test status
Simulation time 54462675894 ps
CPU time 89.18 seconds
Started Jun 11 12:22:08 PM PDT 24
Finished Jun 11 12:23:40 PM PDT 24
Peak memory 190968 kb
Host smart-2441e9bb-baa1-4eb9-baa0-65ebb60a1f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631101322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1631101322
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1740201467
Short name T86
Test name
Test status
Simulation time 10732993 ps
CPU time 0.57 seconds
Started Jun 11 12:18:51 PM PDT 24
Finished Jun 11 12:18:52 PM PDT 24
Peak memory 182140 kb
Host smart-cb9f80d0-e90c-4837-81d8-50dc967d2cc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740201467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1740201467
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.883260431
Short name T101
Test name
Test status
Simulation time 18391765 ps
CPU time 0.82 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:22:30 PM PDT 24
Peak memory 191164 kb
Host smart-2a39c378-2019-42bb-ab95-c2ea05b57ff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883260431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.883260431
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/103.rv_timer_random.1227402981
Short name T236
Test name
Test status
Simulation time 119681966417 ps
CPU time 347.32 seconds
Started Jun 11 12:23:10 PM PDT 24
Finished Jun 11 12:28:58 PM PDT 24
Peak memory 194496 kb
Host smart-33b59f30-e4a4-48c4-80f3-f7f6a273896c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227402981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1227402981
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2928073772
Short name T163
Test name
Test status
Simulation time 49994545376 ps
CPU time 508.95 seconds
Started Jun 11 12:22:23 PM PDT 24
Finished Jun 11 12:30:53 PM PDT 24
Peak memory 191120 kb
Host smart-82476765-8360-4a9f-973a-a8acf64f8edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928073772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2928073772
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.75836688
Short name T59
Test name
Test status
Simulation time 4066842349 ps
CPU time 7.83 seconds
Started Jun 11 12:19:29 PM PDT 24
Finished Jun 11 12:19:37 PM PDT 24
Peak memory 191440 kb
Host smart-479d1688-f201-4b99-bdb9-64c7c8fbea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75836688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.75836688
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/113.rv_timer_random.2922819631
Short name T180
Test name
Test status
Simulation time 597393742219 ps
CPU time 345.12 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:28:49 PM PDT 24
Peak memory 191012 kb
Host smart-d54bab34-5df3-4275-b9a0-fdcfe72f939c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922819631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2922819631
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.655132301
Short name T333
Test name
Test status
Simulation time 345190538630 ps
CPU time 1486.67 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:47:50 PM PDT 24
Peak memory 182804 kb
Host smart-36110a82-4cd0-4c91-98df-285bdc5f91f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655132301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.655132301
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3056156802
Short name T204
Test name
Test status
Simulation time 413527427664 ps
CPU time 433.58 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:30:58 PM PDT 24
Peak memory 191048 kb
Host smart-f590a8fe-8795-415e-b780-e89994b0da68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056156802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3056156802
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1993588273
Short name T272
Test name
Test status
Simulation time 817994813762 ps
CPU time 413.62 seconds
Started Jun 11 12:23:08 PM PDT 24
Finished Jun 11 12:30:03 PM PDT 24
Peak memory 190976 kb
Host smart-4b45acbe-e69a-4eca-b513-dcf4bfea87db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993588273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1993588273
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3531151457
Short name T20
Test name
Test status
Simulation time 374021468549 ps
CPU time 205.87 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:27:00 PM PDT 24
Peak memory 191140 kb
Host smart-b02e81c8-66b2-4fd9-a139-05d06b79da89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531151457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3531151457
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2015464877
Short name T210
Test name
Test status
Simulation time 382220162941 ps
CPU time 507.83 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:32:08 PM PDT 24
Peak memory 193192 kb
Host smart-2cb2eac3-23a2-49d2-8570-52c2dfa01e16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015464877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2015464877
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.590782193
Short name T368
Test name
Test status
Simulation time 978297740472 ps
CPU time 396.47 seconds
Started Jun 11 12:19:54 PM PDT 24
Finished Jun 11 12:26:32 PM PDT 24
Peak memory 190804 kb
Host smart-9d1fcef7-40d1-4721-bb5a-9424a9b2cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590782193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.590782193
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1829724460
Short name T162
Test name
Test status
Simulation time 469364043453 ps
CPU time 291.39 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:28:23 PM PDT 24
Peak memory 192984 kb
Host smart-3a775dcd-1b2f-4751-b2f7-7db7aac89abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829724460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1829724460
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_random.2518339039
Short name T237
Test name
Test status
Simulation time 130941985826 ps
CPU time 270.15 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:27:33 PM PDT 24
Peak memory 194288 kb
Host smart-9cf88e31-8f9d-440c-ae7a-4f0efb3054ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518339039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2518339039
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1611532991
Short name T331
Test name
Test status
Simulation time 177569354760 ps
CPU time 127.4 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:24:39 PM PDT 24
Peak memory 193144 kb
Host smart-b810ac77-7e3a-4026-aa32-1a0e8d5a227a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611532991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1611532991
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1389798284
Short name T556
Test name
Test status
Simulation time 186556320 ps
CPU time 1.37 seconds
Started Jun 11 12:17:08 PM PDT 24
Finished Jun 11 12:17:10 PM PDT 24
Peak memory 194900 kb
Host smart-40df4497-880d-49cd-876b-740e6aa40049
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389798284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1389798284
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1434409858
Short name T26
Test name
Test status
Simulation time 918981257 ps
CPU time 1.4 seconds
Started Jun 11 12:19:29 PM PDT 24
Finished Jun 11 12:19:31 PM PDT 24
Peak memory 194944 kb
Host smart-6728509d-472d-4225-a94f-dc45400c4835
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434409858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1434409858
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/101.rv_timer_random.2282522721
Short name T149
Test name
Test status
Simulation time 118323137485 ps
CPU time 338.32 seconds
Started Jun 11 12:22:49 PM PDT 24
Finished Jun 11 12:28:29 PM PDT 24
Peak memory 190992 kb
Host smart-821089c5-36bb-47ea-ad7f-23478fe59c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282522721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2282522721
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3751237520
Short name T153
Test name
Test status
Simulation time 646313463526 ps
CPU time 234.87 seconds
Started Jun 11 12:19:52 PM PDT 24
Finished Jun 11 12:23:49 PM PDT 24
Peak memory 181792 kb
Host smart-11ff14ff-6b58-49b2-ab1c-e2105911f5fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751237520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3751237520
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3926024405
Short name T161
Test name
Test status
Simulation time 3310200156768 ps
CPU time 1602.9 seconds
Started Jun 11 12:22:52 PM PDT 24
Finished Jun 11 12:49:37 PM PDT 24
Peak memory 190940 kb
Host smart-c7241272-985c-4fac-9581-4c3841f3e6ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926024405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3926024405
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.3063588327
Short name T242
Test name
Test status
Simulation time 121937432488 ps
CPU time 389.27 seconds
Started Jun 11 12:22:37 PM PDT 24
Finished Jun 11 12:29:08 PM PDT 24
Peak memory 191032 kb
Host smart-d32b7969-865e-4af9-852d-cfbc07344361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063588327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3063588327
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.60970083
Short name T286
Test name
Test status
Simulation time 1492655048764 ps
CPU time 745.9 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 191080 kb
Host smart-85c3ed66-d65c-45da-a3b1-c9d5c877eac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60970083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.60970083
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1457753354
Short name T265
Test name
Test status
Simulation time 243046431860 ps
CPU time 750.59 seconds
Started Jun 11 12:22:34 PM PDT 24
Finished Jun 11 12:35:08 PM PDT 24
Peak memory 193320 kb
Host smart-0272f2b3-0a3c-4e45-a7a0-736a39622a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457753354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1457753354
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.992561846
Short name T249
Test name
Test status
Simulation time 194912813688 ps
CPU time 175.43 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:25:58 PM PDT 24
Peak memory 191012 kb
Host smart-caddabf3-694e-43c6-bf1e-d0ebf0d4f884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992561846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.992561846
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3417646934
Short name T110
Test name
Test status
Simulation time 274764719033 ps
CPU time 256.52 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:27:15 PM PDT 24
Peak memory 191120 kb
Host smart-3f35830f-ee94-4d8c-96e2-cef9a0bcbcce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417646934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3417646934
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.913408642
Short name T189
Test name
Test status
Simulation time 146803286673 ps
CPU time 503.63 seconds
Started Jun 11 12:23:00 PM PDT 24
Finished Jun 11 12:31:28 PM PDT 24
Peak memory 191004 kb
Host smart-d103893e-8f88-43e5-bbc2-01cb00bbf251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913408642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.913408642
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2732243142
Short name T346
Test name
Test status
Simulation time 709635392185 ps
CPU time 298.96 seconds
Started Jun 11 12:23:10 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 193560 kb
Host smart-348d4f82-f7ed-4061-a436-67303afc52ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732243142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2732243142
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.770968454
Short name T175
Test name
Test status
Simulation time 96344971911 ps
CPU time 362.75 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:29:07 PM PDT 24
Peak memory 191036 kb
Host smart-8f15036c-0433-41bf-9657-88bc4d0efc45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770968454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.770968454
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1209146457
Short name T136
Test name
Test status
Simulation time 604643687034 ps
CPU time 397.18 seconds
Started Jun 11 12:23:06 PM PDT 24
Finished Jun 11 12:29:44 PM PDT 24
Peak memory 190980 kb
Host smart-634d0cc8-a5fa-458f-8fdf-f38919841c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209146457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1209146457
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.332471601
Short name T68
Test name
Test status
Simulation time 599814508862 ps
CPU time 554.17 seconds
Started Jun 11 12:23:08 PM PDT 24
Finished Jun 11 12:32:23 PM PDT 24
Peak memory 190968 kb
Host smart-1bbe7d6d-4194-45d3-9002-ef19997126ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332471601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.332471601
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2247651607
Short name T365
Test name
Test status
Simulation time 188164872541 ps
CPU time 475.18 seconds
Started Jun 11 12:23:22 PM PDT 24
Finished Jun 11 12:31:19 PM PDT 24
Peak memory 190960 kb
Host smart-939cc23b-1b8b-4449-a474-22a3a1d931e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247651607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2247651607
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1692205904
Short name T282
Test name
Test status
Simulation time 97040120461 ps
CPU time 88.03 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:25:02 PM PDT 24
Peak memory 182912 kb
Host smart-0b77b8b1-0ace-46ca-a3ae-b391a1a49fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692205904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1692205904
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3099878236
Short name T239
Test name
Test status
Simulation time 380817072201 ps
CPU time 303.67 seconds
Started Jun 11 12:23:22 PM PDT 24
Finished Jun 11 12:28:28 PM PDT 24
Peak memory 192128 kb
Host smart-e7087ffd-b828-496e-90d1-a9431fd1ab4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099878236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3099878236
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2463543926
Short name T156
Test name
Test status
Simulation time 323078784995 ps
CPU time 129.99 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:24:52 PM PDT 24
Peak memory 182464 kb
Host smart-ceb1f7e3-e34a-4a04-b288-b59286e866fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463543926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2463543926
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.23821155
Short name T371
Test name
Test status
Simulation time 2410097899543 ps
CPU time 741.93 seconds
Started Jun 11 12:19:28 PM PDT 24
Finished Jun 11 12:31:51 PM PDT 24
Peak memory 191440 kb
Host smart-481371a0-e9ac-4e49-9c87-46d0cdb3a891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23821155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.23821155
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.900492217
Short name T327
Test name
Test status
Simulation time 141519377991 ps
CPU time 173.33 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:26:24 PM PDT 24
Peak memory 190988 kb
Host smart-5c6a353f-1b80-4c8e-80a4-f8b33bf5d942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900492217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.900492217
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3390497813
Short name T184
Test name
Test status
Simulation time 275287779512 ps
CPU time 436.72 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:30:45 PM PDT 24
Peak memory 194588 kb
Host smart-9d7bdecb-d494-4d2c-9d9b-a31c58d8e91a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390497813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3390497813
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.1920504143
Short name T195
Test name
Test status
Simulation time 148705104840 ps
CPU time 1510.17 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:48:50 PM PDT 24
Peak memory 190700 kb
Host smart-89d79e0a-9215-4741-83cd-2c49418f7871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920504143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1920504143
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1457305492
Short name T213
Test name
Test status
Simulation time 332123459345 ps
CPU time 544 seconds
Started Jun 11 12:23:21 PM PDT 24
Finished Jun 11 12:32:27 PM PDT 24
Peak memory 190904 kb
Host smart-9168fcdb-b1de-4d45-94be-883986af68c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457305492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1457305492
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.990665935
Short name T45
Test name
Test status
Simulation time 11779557414 ps
CPU time 6.37 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:22:19 PM PDT 24
Peak memory 182596 kb
Host smart-f60aeab7-496c-4792-b0a1-d677b3e420c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990665935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.990665935
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3641117079
Short name T347
Test name
Test status
Simulation time 384820084202 ps
CPU time 618.36 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:33:18 PM PDT 24
Peak memory 182548 kb
Host smart-5213a3c1-e0a1-40c7-add3-d3aa618b09ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641117079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3641117079
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.853562160
Short name T243
Test name
Test status
Simulation time 750178384333 ps
CPU time 458.98 seconds
Started Jun 11 12:22:11 PM PDT 24
Finished Jun 11 12:29:52 PM PDT 24
Peak memory 182308 kb
Host smart-f37a0c6b-f552-482b-ba05-7bbdeff235ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853562160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.853562160
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3764584062
Short name T246
Test name
Test status
Simulation time 217347043742 ps
CPU time 675.11 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:34:03 PM PDT 24
Peak memory 190656 kb
Host smart-c72373d9-9577-4d02-ab6c-663a140757f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764584062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3764584062
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.1955980084
Short name T235
Test name
Test status
Simulation time 419680838237 ps
CPU time 323.26 seconds
Started Jun 11 12:22:52 PM PDT 24
Finished Jun 11 12:28:17 PM PDT 24
Peak memory 192036 kb
Host smart-eb883d9b-bc1f-4e7f-9bc3-e43af815875b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955980084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1955980084
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3418176664
Short name T57
Test name
Test status
Simulation time 333198732860 ps
CPU time 370.44 seconds
Started Jun 11 12:23:20 PM PDT 24
Finished Jun 11 12:29:34 PM PDT 24
Peak memory 190980 kb
Host smart-f763459a-0e6d-402f-986f-8142255c5069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418176664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3418176664
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1887507792
Short name T78
Test name
Test status
Simulation time 496692808 ps
CPU time 0.81 seconds
Started Jun 11 12:17:14 PM PDT 24
Finished Jun 11 12:17:16 PM PDT 24
Peak memory 191484 kb
Host smart-c3b210b1-4da7-4c85-895f-4385fff6e973
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887507792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1887507792
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.29998886
Short name T83
Test name
Test status
Simulation time 50129993 ps
CPU time 0.6 seconds
Started Jun 11 12:17:14 PM PDT 24
Finished Jun 11 12:17:16 PM PDT 24
Peak memory 182460 kb
Host smart-c2cad6a3-a22b-4d3c-9c83-50e9ca1bf54c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29998886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_res
et.29998886
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.124312873
Short name T515
Test name
Test status
Simulation time 36245145 ps
CPU time 0.88 seconds
Started Jun 11 12:17:10 PM PDT 24
Finished Jun 11 12:17:12 PM PDT 24
Peak memory 195772 kb
Host smart-3ee6e675-aa68-4a06-9879-63b42c2da0ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124312873 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.124312873
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3386436578
Short name T474
Test name
Test status
Simulation time 21054810 ps
CPU time 0.53 seconds
Started Jun 11 12:22:25 PM PDT 24
Finished Jun 11 12:22:27 PM PDT 24
Peak memory 181216 kb
Host smart-ba8ae774-6474-4bb7-bf14-bdca395940b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386436578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3386436578
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1603333230
Short name T552
Test name
Test status
Simulation time 55843429 ps
CPU time 0.74 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:22:46 PM PDT 24
Peak memory 192524 kb
Host smart-be1e1839-4163-4c0d-bb17-a49cdb8ee815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603333230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1603333230
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1877383327
Short name T532
Test name
Test status
Simulation time 37339658 ps
CPU time 1.14 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 196796 kb
Host smart-c5c67eec-af75-45a0-8ad0-e9c00a899b13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877383327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1877383327
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1586826897
Short name T570
Test name
Test status
Simulation time 154003141 ps
CPU time 0.85 seconds
Started Jun 11 12:17:09 PM PDT 24
Finished Jun 11 12:17:11 PM PDT 24
Peak memory 181304 kb
Host smart-2d2442ed-7261-4c26-9c27-53eef838ed84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586826897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1586826897
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3626781586
Short name T545
Test name
Test status
Simulation time 34484615 ps
CPU time 0.79 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 191524 kb
Host smart-96cee77c-a6c9-463c-9970-318f40d6e31f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626781586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3626781586
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1169948573
Short name T51
Test name
Test status
Simulation time 151868561 ps
CPU time 1.5 seconds
Started Jun 11 12:22:25 PM PDT 24
Finished Jun 11 12:22:28 PM PDT 24
Peak memory 190264 kb
Host smart-e8480fbb-4241-44cf-bdda-229693c06799
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169948573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1169948573
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4234977512
Short name T571
Test name
Test status
Simulation time 235105677 ps
CPU time 0.6 seconds
Started Jun 11 12:17:55 PM PDT 24
Finished Jun 11 12:17:56 PM PDT 24
Peak memory 182092 kb
Host smart-5f50cfa9-fca5-4a6e-96fc-fd8cd281569c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234977512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4234977512
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2672885055
Short name T489
Test name
Test status
Simulation time 32051555 ps
CPU time 0.75 seconds
Started Jun 11 12:22:34 PM PDT 24
Finished Jun 11 12:22:38 PM PDT 24
Peak memory 191264 kb
Host smart-48d6eaff-0dae-4d0e-8269-d091f33b7d69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672885055 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2672885055
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1761481902
Short name T581
Test name
Test status
Simulation time 14355325 ps
CPU time 0.61 seconds
Started Jun 11 12:22:34 PM PDT 24
Finished Jun 11 12:22:38 PM PDT 24
Peak memory 180472 kb
Host smart-63ac1655-c663-48e2-89fb-6f69d3a1d4bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761481902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1761481902
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2829133796
Short name T559
Test name
Test status
Simulation time 13970506 ps
CPU time 0.57 seconds
Started Jun 11 12:17:54 PM PDT 24
Finished Jun 11 12:17:55 PM PDT 24
Peak memory 181656 kb
Host smart-1a55cf61-24e0-41bd-9528-2fa3aba44b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829133796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2829133796
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4214221249
Short name T497
Test name
Test status
Simulation time 20848285 ps
CPU time 0.69 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:22:26 PM PDT 24
Peak memory 189728 kb
Host smart-629cb26a-57e9-488a-9ce9-8cc05f7f83d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214221249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4214221249
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2643411436
Short name T553
Test name
Test status
Simulation time 849001048 ps
CPU time 2.53 seconds
Started Jun 11 12:17:14 PM PDT 24
Finished Jun 11 12:17:17 PM PDT 24
Peak memory 196584 kb
Host smart-b6e8ba1e-938c-4faf-b3ea-3618a01a04c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643411436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2643411436
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.693377132
Short name T504
Test name
Test status
Simulation time 38255014 ps
CPU time 1.56 seconds
Started Jun 11 12:20:10 PM PDT 24
Finished Jun 11 12:20:12 PM PDT 24
Peak memory 194704 kb
Host smart-ea49440a-abaf-4256-94d6-3793567b46d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693377132 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.693377132
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2463768239
Short name T543
Test name
Test status
Simulation time 59451094 ps
CPU time 0.53 seconds
Started Jun 11 12:19:38 PM PDT 24
Finished Jun 11 12:19:39 PM PDT 24
Peak memory 181968 kb
Host smart-d3a54a09-145a-483d-8bcc-c85ed71f512a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463768239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2463768239
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1199434518
Short name T540
Test name
Test status
Simulation time 60301143 ps
CPU time 0.54 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:22:55 PM PDT 24
Peak memory 181524 kb
Host smart-52b29df5-cac4-4489-9d2e-7f6808d809f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199434518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1199434518
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.64082744
Short name T525
Test name
Test status
Simulation time 43613503 ps
CPU time 0.59 seconds
Started Jun 11 12:19:52 PM PDT 24
Finished Jun 11 12:19:54 PM PDT 24
Peak memory 191208 kb
Host smart-41b4b211-3a75-44e8-9bc2-814fe973f85c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64082744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_tim
er_same_csr_outstanding.64082744
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.352006897
Short name T62
Test name
Test status
Simulation time 199454597 ps
CPU time 1.13 seconds
Started Jun 11 12:19:50 PM PDT 24
Finished Jun 11 12:19:53 PM PDT 24
Peak memory 194680 kb
Host smart-f87773e9-528a-4641-9e37-c8363c91627e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352006897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.352006897
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.474185622
Short name T105
Test name
Test status
Simulation time 290637570 ps
CPU time 1 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:22:32 PM PDT 24
Peak memory 182476 kb
Host smart-98dae8b0-19bb-4c38-b67b-b0f6e61cf3a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474185622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.474185622
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.83463263
Short name T500
Test name
Test status
Simulation time 19004634 ps
CPU time 0.92 seconds
Started Jun 11 12:22:08 PM PDT 24
Finished Jun 11 12:22:11 PM PDT 24
Peak memory 196388 kb
Host smart-9d41cce6-a499-4fa9-9f4a-7f2852690a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83463263 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.83463263
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2568099936
Short name T551
Test name
Test status
Simulation time 25268145 ps
CPU time 0.59 seconds
Started Jun 11 12:20:06 PM PDT 24
Finished Jun 11 12:20:07 PM PDT 24
Peak memory 182084 kb
Host smart-c0c173f7-ddb3-494d-a920-7a1b2d355305
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568099936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2568099936
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2452493093
Short name T488
Test name
Test status
Simulation time 15312455 ps
CPU time 0.55 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:22:30 PM PDT 24
Peak memory 181524 kb
Host smart-0e699efe-a637-4811-b702-20850529eab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452493093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2452493093
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3962421048
Short name T503
Test name
Test status
Simulation time 48085173 ps
CPU time 2.16 seconds
Started Jun 11 12:19:50 PM PDT 24
Finished Jun 11 12:19:54 PM PDT 24
Peak memory 194812 kb
Host smart-63d9cb1d-4e4e-45d8-a33e-a8c60e29220d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962421048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3962421048
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.919078718
Short name T542
Test name
Test status
Simulation time 799459141 ps
CPU time 0.9 seconds
Started Jun 11 12:22:23 PM PDT 24
Finished Jun 11 12:22:26 PM PDT 24
Peak memory 180320 kb
Host smart-a0cf409a-81b0-428f-97fb-5032c76b7208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919078718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.919078718
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3794090379
Short name T502
Test name
Test status
Simulation time 164031861 ps
CPU time 0.75 seconds
Started Jun 11 12:21:04 PM PDT 24
Finished Jun 11 12:21:05 PM PDT 24
Peak memory 195072 kb
Host smart-1f2f06b9-6606-404d-98ed-8d4816e5e9c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794090379 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3794090379
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1561077502
Short name T567
Test name
Test status
Simulation time 13175087 ps
CPU time 0.57 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:22:12 PM PDT 24
Peak memory 180772 kb
Host smart-b5269c44-92e1-42d6-a139-29cd82d0cf4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561077502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1561077502
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3133007714
Short name T463
Test name
Test status
Simulation time 28070267 ps
CPU time 0.61 seconds
Started Jun 11 12:18:59 PM PDT 24
Finished Jun 11 12:19:00 PM PDT 24
Peak memory 182404 kb
Host smart-d92d890c-356c-466d-91ab-7a910e07979b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133007714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3133007714
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3705991349
Short name T534
Test name
Test status
Simulation time 20219707 ps
CPU time 0.6 seconds
Started Jun 11 12:22:08 PM PDT 24
Finished Jun 11 12:22:10 PM PDT 24
Peak memory 190408 kb
Host smart-02d7406e-6d07-4fed-a8c5-d9bdf43bd034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705991349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3705991349
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.760314849
Short name T467
Test name
Test status
Simulation time 46010507 ps
CPU time 2.01 seconds
Started Jun 11 12:19:50 PM PDT 24
Finished Jun 11 12:19:54 PM PDT 24
Peak memory 194912 kb
Host smart-fa0f1d64-6de8-4678-b264-90af7dcc275d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760314849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.760314849
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2703546908
Short name T584
Test name
Test status
Simulation time 165658050 ps
CPU time 0.78 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:22:12 PM PDT 24
Peak memory 180812 kb
Host smart-a6e842b5-50d5-4cb8-b7b0-19d7db62a8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703546908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2703546908
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3179973550
Short name T476
Test name
Test status
Simulation time 117373429 ps
CPU time 1.37 seconds
Started Jun 11 12:20:07 PM PDT 24
Finished Jun 11 12:20:09 PM PDT 24
Peak memory 197440 kb
Host smart-278559e3-8af8-4631-885a-201ca12b8395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179973550 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3179973550
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1751237807
Short name T566
Test name
Test status
Simulation time 38564785 ps
CPU time 0.53 seconds
Started Jun 11 12:22:07 PM PDT 24
Finished Jun 11 12:22:09 PM PDT 24
Peak memory 181736 kb
Host smart-e74c1621-712d-40f6-87f7-cdeb1f7f48ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751237807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1751237807
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2918892098
Short name T514
Test name
Test status
Simulation time 47786606 ps
CPU time 0.54 seconds
Started Jun 11 12:18:53 PM PDT 24
Finished Jun 11 12:18:54 PM PDT 24
Peak memory 182076 kb
Host smart-cc198ffa-0764-4c65-92ce-e0905b684c25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918892098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2918892098
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2828088825
Short name T85
Test name
Test status
Simulation time 117365896 ps
CPU time 0.71 seconds
Started Jun 11 12:22:07 PM PDT 24
Finished Jun 11 12:22:09 PM PDT 24
Peak memory 190704 kb
Host smart-732bc329-9487-4065-a69c-1f61f2ec8dfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828088825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2828088825
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3457548500
Short name T464
Test name
Test status
Simulation time 236803873 ps
CPU time 3.15 seconds
Started Jun 11 12:18:50 PM PDT 24
Finished Jun 11 12:18:54 PM PDT 24
Peak memory 197048 kb
Host smart-0e1fa75e-bd57-4dff-b2a0-47871fc02d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457548500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3457548500
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3520596302
Short name T530
Test name
Test status
Simulation time 34581476 ps
CPU time 0.86 seconds
Started Jun 11 12:20:50 PM PDT 24
Finished Jun 11 12:20:52 PM PDT 24
Peak memory 196680 kb
Host smart-67a3bebd-4c24-47f1-9763-21a74d35ec6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520596302 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3520596302
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2038814256
Short name T87
Test name
Test status
Simulation time 40094265 ps
CPU time 0.59 seconds
Started Jun 11 12:19:39 PM PDT 24
Finished Jun 11 12:19:40 PM PDT 24
Peak memory 182152 kb
Host smart-e7a49591-1434-4335-9883-53e1d813806b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038814256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2038814256
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4118096368
Short name T518
Test name
Test status
Simulation time 15312230 ps
CPU time 0.54 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:22:31 PM PDT 24
Peak memory 181712 kb
Host smart-ec9d1eb5-cd57-481e-83a5-a50209042001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118096368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4118096368
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.397313384
Short name T81
Test name
Test status
Simulation time 38312584 ps
CPU time 0.82 seconds
Started Jun 11 12:22:23 PM PDT 24
Finished Jun 11 12:22:26 PM PDT 24
Peak memory 189376 kb
Host smart-1a94c3aa-e6dd-4eaf-a3d7-7a766d17cb4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397313384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.397313384
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.908865068
Short name T473
Test name
Test status
Simulation time 187156128 ps
CPU time 3.58 seconds
Started Jun 11 12:19:44 PM PDT 24
Finished Jun 11 12:19:48 PM PDT 24
Peak memory 197420 kb
Host smart-b44847c3-2817-4f92-841f-f2b01e0bb4ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908865068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.908865068
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3027094865
Short name T104
Test name
Test status
Simulation time 113387645 ps
CPU time 1.36 seconds
Started Jun 11 12:22:06 PM PDT 24
Finished Jun 11 12:22:10 PM PDT 24
Peak memory 180692 kb
Host smart-87a64bb4-1e0d-458a-98ad-130bb24a1390
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027094865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3027094865
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2182510676
Short name T493
Test name
Test status
Simulation time 63015149 ps
CPU time 0.71 seconds
Started Jun 11 12:19:39 PM PDT 24
Finished Jun 11 12:19:41 PM PDT 24
Peak memory 194172 kb
Host smart-c44cc87c-b6aa-407f-9bf6-dfffb95a8dd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182510676 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2182510676
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4264972907
Short name T583
Test name
Test status
Simulation time 27450172 ps
CPU time 0.62 seconds
Started Jun 11 12:19:11 PM PDT 24
Finished Jun 11 12:19:12 PM PDT 24
Peak memory 182524 kb
Host smart-725ae731-b7fe-4633-b7e8-08acff78a1a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264972907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4264972907
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1969080587
Short name T537
Test name
Test status
Simulation time 47454556 ps
CPU time 0.52 seconds
Started Jun 11 12:22:08 PM PDT 24
Finished Jun 11 12:22:10 PM PDT 24
Peak memory 181180 kb
Host smart-c504b448-37ba-457a-b205-698619e10c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969080587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1969080587
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.139665411
Short name T533
Test name
Test status
Simulation time 25227193 ps
CPU time 0.64 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:22:31 PM PDT 24
Peak memory 189084 kb
Host smart-3d733750-5647-410f-a375-06ff22313f96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139665411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.139665411
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1898010371
Short name T568
Test name
Test status
Simulation time 168623759 ps
CPU time 1.38 seconds
Started Jun 11 12:22:07 PM PDT 24
Finished Jun 11 12:22:10 PM PDT 24
Peak memory 195940 kb
Host smart-6d1126b0-cda3-4e4a-a45d-8373d8d5a2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898010371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1898010371
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3270442692
Short name T28
Test name
Test status
Simulation time 268676229 ps
CPU time 1.03 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:22:14 PM PDT 24
Peak memory 193948 kb
Host smart-eb27f246-83c7-489a-bf80-816f6e34eccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270442692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3270442692
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.972515066
Short name T563
Test name
Test status
Simulation time 22122792 ps
CPU time 0.87 seconds
Started Jun 11 12:19:52 PM PDT 24
Finished Jun 11 12:19:54 PM PDT 24
Peak memory 196460 kb
Host smart-f01915e1-60e7-4309-98c1-1078252f837d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972515066 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.972515066
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3277085577
Short name T91
Test name
Test status
Simulation time 14499971 ps
CPU time 0.58 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:22:32 PM PDT 24
Peak memory 181820 kb
Host smart-403f1084-73f3-4fcd-a28e-a5dc8832f49b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277085577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3277085577
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2875109154
Short name T513
Test name
Test status
Simulation time 30493797 ps
CPU time 0.56 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:22:12 PM PDT 24
Peak memory 180136 kb
Host smart-c60febe0-d7c6-4a9d-9da8-00b6b048e646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875109154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2875109154
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2495005595
Short name T519
Test name
Test status
Simulation time 27882146 ps
CPU time 0.71 seconds
Started Jun 11 12:19:51 PM PDT 24
Finished Jun 11 12:19:53 PM PDT 24
Peak memory 191360 kb
Host smart-c44460ba-cc49-4b9d-96dd-6e97bf3ce8bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495005595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2495005595
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2326066624
Short name T61
Test name
Test status
Simulation time 115109208 ps
CPU time 1.22 seconds
Started Jun 11 12:18:49 PM PDT 24
Finished Jun 11 12:18:51 PM PDT 24
Peak memory 197048 kb
Host smart-2c21fc22-ed22-4735-990a-c642d996a67a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326066624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2326066624
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.722973232
Short name T558
Test name
Test status
Simulation time 418031414 ps
CPU time 1.32 seconds
Started Jun 11 12:22:07 PM PDT 24
Finished Jun 11 12:22:10 PM PDT 24
Peak memory 194664 kb
Host smart-71fcb2fa-f5a2-41b8-9f50-518f374a2ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722973232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.722973232
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1665177184
Short name T511
Test name
Test status
Simulation time 84319445 ps
CPU time 0.76 seconds
Started Jun 11 12:22:39 PM PDT 24
Finished Jun 11 12:22:42 PM PDT 24
Peak memory 192984 kb
Host smart-115747ae-72a5-41d7-8edf-7c3000cdab7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665177184 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1665177184
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.262467271
Short name T501
Test name
Test status
Simulation time 18511987 ps
CPU time 0.56 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:22:33 PM PDT 24
Peak memory 181816 kb
Host smart-ffe80ece-e77a-4722-942c-f0402ad03960
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262467271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.262467271
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1997878362
Short name T492
Test name
Test status
Simulation time 27353665 ps
CPU time 0.55 seconds
Started Jun 11 12:22:06 PM PDT 24
Finished Jun 11 12:22:09 PM PDT 24
Peak memory 179508 kb
Host smart-78593cd3-1f6d-46e8-afd5-9024c1edf83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997878362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1997878362
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2648551679
Short name T100
Test name
Test status
Simulation time 43488832 ps
CPU time 0.66 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:22:36 PM PDT 24
Peak memory 192184 kb
Host smart-0262811d-a09b-4bdc-b889-c9a4a875336f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648551679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2648551679
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1825355964
Short name T471
Test name
Test status
Simulation time 80157383 ps
CPU time 1.03 seconds
Started Jun 11 12:21:14 PM PDT 24
Finished Jun 11 12:21:15 PM PDT 24
Peak memory 196676 kb
Host smart-d2465d0c-b0c3-49e9-8894-42f4681e040b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825355964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1825355964
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3697471696
Short name T487
Test name
Test status
Simulation time 192227616 ps
CPU time 0.78 seconds
Started Jun 11 12:22:44 PM PDT 24
Finished Jun 11 12:22:48 PM PDT 24
Peak memory 191532 kb
Host smart-844e67a2-629b-4199-9302-8f0a3a30a4a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697471696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3697471696
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1525572781
Short name T468
Test name
Test status
Simulation time 22575511 ps
CPU time 0.96 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:03 PM PDT 24
Peak memory 196764 kb
Host smart-716c1348-a819-4f03-bb32-e617cd65a3af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525572781 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1525572781
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1073522948
Short name T93
Test name
Test status
Simulation time 53404633 ps
CPU time 0.57 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:22:33 PM PDT 24
Peak memory 180964 kb
Host smart-a5155e81-fe39-4981-944c-66068cb3bd2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073522948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1073522948
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.789449241
Short name T507
Test name
Test status
Simulation time 18438025 ps
CPU time 0.61 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:44 PM PDT 24
Peak memory 181244 kb
Host smart-021cdaab-74af-468a-b0b6-fcdc6131c989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789449241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.789449241
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1724137886
Short name T548
Test name
Test status
Simulation time 110186995 ps
CPU time 0.72 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:02 PM PDT 24
Peak memory 192696 kb
Host smart-d6b2aca3-0466-43d6-bba4-a11a313702df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724137886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1724137886
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3744351493
Short name T555
Test name
Test status
Simulation time 205663690 ps
CPU time 2.51 seconds
Started Jun 11 12:22:06 PM PDT 24
Finished Jun 11 12:22:11 PM PDT 24
Peak memory 195040 kb
Host smart-6c8eba96-7a6b-455d-8231-0441a9c0290a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744351493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3744351493
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1041097887
Short name T496
Test name
Test status
Simulation time 45390281 ps
CPU time 1.03 seconds
Started Jun 11 12:22:11 PM PDT 24
Finished Jun 11 12:22:13 PM PDT 24
Peak memory 196448 kb
Host smart-9661bdf6-6e13-47b9-96a7-6879f9186ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041097887 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1041097887
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.647721890
Short name T90
Test name
Test status
Simulation time 12561361 ps
CPU time 0.55 seconds
Started Jun 11 12:22:50 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 181688 kb
Host smart-e3124ec1-9345-4d8f-ae4f-21541865d7a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647721890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.647721890
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2560490812
Short name T499
Test name
Test status
Simulation time 16607498 ps
CPU time 0.59 seconds
Started Jun 11 12:20:27 PM PDT 24
Finished Jun 11 12:20:28 PM PDT 24
Peak memory 182068 kb
Host smart-14e7782e-d887-4264-99d5-2d0eb500733f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560490812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2560490812
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.393258931
Short name T84
Test name
Test status
Simulation time 37749426 ps
CPU time 0.66 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:22:56 PM PDT 24
Peak memory 190040 kb
Host smart-1266982d-c2ed-4342-a9bb-591becafbd1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393258931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.393258931
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1490213140
Short name T535
Test name
Test status
Simulation time 140332516 ps
CPU time 1.7 seconds
Started Jun 11 12:22:49 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 189272 kb
Host smart-4939a6c4-d717-4c21-a695-4c65c14da69e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490213140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1490213140
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1789749696
Short name T107
Test name
Test status
Simulation time 127961134 ps
CPU time 0.82 seconds
Started Jun 11 12:22:42 PM PDT 24
Finished Jun 11 12:22:46 PM PDT 24
Peak memory 181668 kb
Host smart-47e39300-1087-4c61-8d84-c2ff48615644
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789749696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1789749696
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.125893101
Short name T88
Test name
Test status
Simulation time 17534873 ps
CPU time 0.77 seconds
Started Jun 11 12:22:34 PM PDT 24
Finished Jun 11 12:22:38 PM PDT 24
Peak memory 190836 kb
Host smart-730b10c9-d441-4062-96c3-046b18a13f37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125893101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.125893101
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4105654220
Short name T31
Test name
Test status
Simulation time 895605712 ps
CPU time 2.27 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 190532 kb
Host smart-14065685-23fa-4fd0-87ea-8a1ef67d3c9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105654220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4105654220
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2502919489
Short name T577
Test name
Test status
Simulation time 46690224 ps
CPU time 0.61 seconds
Started Jun 11 12:22:34 PM PDT 24
Finished Jun 11 12:22:38 PM PDT 24
Peak memory 179436 kb
Host smart-7313a25e-dc8b-4f64-9aef-1492235517ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502919489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2502919489
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2755855074
Short name T512
Test name
Test status
Simulation time 32345037 ps
CPU time 0.8 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 195984 kb
Host smart-89253994-a683-44ff-bd6a-6cd30f47b9bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755855074 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2755855074
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2571254768
Short name T79
Test name
Test status
Simulation time 15871148 ps
CPU time 0.57 seconds
Started Jun 11 12:19:05 PM PDT 24
Finished Jun 11 12:19:06 PM PDT 24
Peak memory 181940 kb
Host smart-e34bd5b2-98ad-45b9-abaf-76edcc7b5b93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571254768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2571254768
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3260673413
Short name T569
Test name
Test status
Simulation time 35329375 ps
CPU time 0.53 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 181860 kb
Host smart-7d5f6acc-d788-44f7-90b0-5ced8df9fb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260673413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3260673413
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2537420755
Short name T579
Test name
Test status
Simulation time 30190367 ps
CPU time 0.75 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:36 PM PDT 24
Peak memory 192692 kb
Host smart-961d461a-12bc-4448-a5b2-e36c3762d8f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537420755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2537420755
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2264657379
Short name T560
Test name
Test status
Simulation time 207524197 ps
CPU time 2.22 seconds
Started Jun 11 12:22:34 PM PDT 24
Finished Jun 11 12:22:40 PM PDT 24
Peak memory 195320 kb
Host smart-700c2acd-a31f-429a-be26-892735cfcbd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264657379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2264657379
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2968909047
Short name T527
Test name
Test status
Simulation time 113414243 ps
CPU time 1.3 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:02 PM PDT 24
Peak memory 194588 kb
Host smart-1bb4b93a-8b8a-428b-8b8c-e67204d0459e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968909047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2968909047
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.959547222
Short name T562
Test name
Test status
Simulation time 164385730 ps
CPU time 0.56 seconds
Started Jun 11 12:23:17 PM PDT 24
Finished Jun 11 12:23:18 PM PDT 24
Peak memory 182024 kb
Host smart-31d4aac3-bbc6-4651-b931-4feeea167142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959547222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.959547222
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3915075124
Short name T521
Test name
Test status
Simulation time 55127019 ps
CPU time 0.55 seconds
Started Jun 11 12:23:07 PM PDT 24
Finished Jun 11 12:23:09 PM PDT 24
Peak memory 182048 kb
Host smart-c5896bef-2d2d-447d-aa29-be206c88713a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915075124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3915075124
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2829256721
Short name T495
Test name
Test status
Simulation time 34463956 ps
CPU time 0.57 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:22:13 PM PDT 24
Peak memory 180320 kb
Host smart-b432956e-dc58-434b-b5c3-c8e71d052779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829256721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2829256721
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.199150289
Short name T505
Test name
Test status
Simulation time 27139966 ps
CPU time 0.62 seconds
Started Jun 11 12:23:01 PM PDT 24
Finished Jun 11 12:23:06 PM PDT 24
Peak memory 181148 kb
Host smart-2d00b2b0-2ba9-4df6-986b-0344570393eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199150289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.199150289
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.85061887
Short name T522
Test name
Test status
Simulation time 35199487 ps
CPU time 0.52 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 181532 kb
Host smart-e2b25066-124a-42cb-aa1c-4d5678f608cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85061887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.85061887
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.459652938
Short name T508
Test name
Test status
Simulation time 13824856 ps
CPU time 0.55 seconds
Started Jun 11 12:23:12 PM PDT 24
Finished Jun 11 12:23:14 PM PDT 24
Peak memory 181660 kb
Host smart-6c794c42-f87d-4557-a732-f0990082a058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459652938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.459652938
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1043787620
Short name T538
Test name
Test status
Simulation time 11702548 ps
CPU time 0.57 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:22:56 PM PDT 24
Peak memory 179884 kb
Host smart-27e19753-ef43-4168-9626-dd4c7eb2afe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043787620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1043787620
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.155169675
Short name T574
Test name
Test status
Simulation time 48851393 ps
CPU time 0.61 seconds
Started Jun 11 12:18:00 PM PDT 24
Finished Jun 11 12:18:01 PM PDT 24
Peak memory 182484 kb
Host smart-45f7598b-1d32-437e-8b0d-d723ddeb4d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155169675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.155169675
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2185728969
Short name T580
Test name
Test status
Simulation time 52802769 ps
CPU time 0.53 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:23:29 PM PDT 24
Peak memory 181868 kb
Host smart-43d7c9e0-5b5b-49c8-a7a9-7e373fa57ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185728969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2185728969
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4011549904
Short name T573
Test name
Test status
Simulation time 12298102 ps
CPU time 0.52 seconds
Started Jun 11 12:22:58 PM PDT 24
Finished Jun 11 12:23:03 PM PDT 24
Peak memory 181356 kb
Host smart-c66e7d07-996f-4f7e-a8ad-b177f28664c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011549904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4011549904
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3250908511
Short name T52
Test name
Test status
Simulation time 37654653 ps
CPU time 0.62 seconds
Started Jun 11 12:19:50 PM PDT 24
Finished Jun 11 12:19:52 PM PDT 24
Peak memory 182096 kb
Host smart-8d633849-7aac-481c-866a-7ce8e1df2bae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250908511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3250908511
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1794898719
Short name T82
Test name
Test status
Simulation time 63075146 ps
CPU time 2.32 seconds
Started Jun 11 12:18:44 PM PDT 24
Finished Jun 11 12:18:47 PM PDT 24
Peak memory 191580 kb
Host smart-2c5d41a4-e696-4ce3-a067-d4f03dd6e82d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794898719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1794898719
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1121922842
Short name T30
Test name
Test status
Simulation time 78069903 ps
CPU time 0.55 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 190936 kb
Host smart-e7c3601d-5b80-4f07-bc07-6ef887fc10f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121922842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1121922842
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2987386572
Short name T528
Test name
Test status
Simulation time 30630089 ps
CPU time 0.63 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:22:30 PM PDT 24
Peak memory 193380 kb
Host smart-eef8b26c-0db5-4103-aad3-976cbef74985
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987386572 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2987386572
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1748852602
Short name T92
Test name
Test status
Simulation time 31083930 ps
CPU time 0.53 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:22:37 PM PDT 24
Peak memory 181524 kb
Host smart-2269f151-bc30-4853-a0fe-4a0796dfd6a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748852602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1748852602
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3623659970
Short name T541
Test name
Test status
Simulation time 13041770 ps
CPU time 0.5 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 181056 kb
Host smart-38b15b2d-d9fa-4861-ae22-cc0055911221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623659970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3623659970
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4264206041
Short name T48
Test name
Test status
Simulation time 91558704 ps
CPU time 0.69 seconds
Started Jun 11 12:21:34 PM PDT 24
Finished Jun 11 12:21:36 PM PDT 24
Peak memory 191732 kb
Host smart-78e2afb9-b593-4ebd-bdc6-9a0cf5f19b3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264206041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4264206041
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1167956139
Short name T520
Test name
Test status
Simulation time 67324373 ps
CPU time 1.56 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 196488 kb
Host smart-5bbfeba6-ac26-4f33-8dea-313f5451a296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167956139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1167956139
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1798756876
Short name T486
Test name
Test status
Simulation time 463881568 ps
CPU time 0.99 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:01 PM PDT 24
Peak memory 182896 kb
Host smart-3807a415-31c1-4b48-bd9b-575527374442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798756876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1798756876
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3957671008
Short name T472
Test name
Test status
Simulation time 44953873 ps
CPU time 0.53 seconds
Started Jun 11 12:22:49 PM PDT 24
Finished Jun 11 12:22:52 PM PDT 24
Peak memory 182008 kb
Host smart-168c8a3f-5b92-4955-b263-f77caf671af3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957671008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3957671008
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3122857663
Short name T561
Test name
Test status
Simulation time 16997642 ps
CPU time 0.54 seconds
Started Jun 11 12:19:52 PM PDT 24
Finished Jun 11 12:19:55 PM PDT 24
Peak memory 181672 kb
Host smart-7ab3c8b1-0979-4a52-8514-edf6fab5038d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122857663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3122857663
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.264875102
Short name T510
Test name
Test status
Simulation time 16520240 ps
CPU time 0.53 seconds
Started Jun 11 12:22:47 PM PDT 24
Finished Jun 11 12:22:50 PM PDT 24
Peak memory 181632 kb
Host smart-02d6521c-ed05-47c7-81dd-48596c90a8b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264875102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.264875102
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4131633622
Short name T557
Test name
Test status
Simulation time 40492005 ps
CPU time 0.5 seconds
Started Jun 11 12:22:48 PM PDT 24
Finished Jun 11 12:22:51 PM PDT 24
Peak memory 181648 kb
Host smart-bb89696d-cfd6-4de3-8032-1e1543833208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131633622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.4131633622
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4152179891
Short name T549
Test name
Test status
Simulation time 14583451 ps
CPU time 0.53 seconds
Started Jun 11 12:22:48 PM PDT 24
Finished Jun 11 12:22:51 PM PDT 24
Peak memory 181728 kb
Host smart-ec156ce9-5c11-41e3-a5b3-ff6fa288e39f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152179891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4152179891
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1902147610
Short name T516
Test name
Test status
Simulation time 16753169 ps
CPU time 0.52 seconds
Started Jun 11 12:22:51 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 181704 kb
Host smart-e2451d40-4fd7-4290-92e9-d7621d8d68dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902147610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1902147610
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.368848665
Short name T466
Test name
Test status
Simulation time 93836519 ps
CPU time 0.52 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:45 PM PDT 24
Peak memory 182100 kb
Host smart-c22ff42b-2087-4918-a09a-1685be1fd633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368848665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.368848665
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.211568143
Short name T482
Test name
Test status
Simulation time 18760556 ps
CPU time 0.53 seconds
Started Jun 11 12:23:41 PM PDT 24
Finished Jun 11 12:23:44 PM PDT 24
Peak memory 182044 kb
Host smart-9f8e10a4-47ba-4145-98f6-fc8778912703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211568143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.211568143
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1371838725
Short name T491
Test name
Test status
Simulation time 32981020 ps
CPU time 0.51 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:46 PM PDT 24
Peak memory 181956 kb
Host smart-49ab89ff-b9b1-404e-b35d-f344216f9c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371838725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1371838725
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3715185661
Short name T469
Test name
Test status
Simulation time 17370649 ps
CPU time 0.54 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:23:42 PM PDT 24
Peak memory 182072 kb
Host smart-f2a5a8be-fd2f-430b-9447-8faaa9a334f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715185661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3715185661
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2976148813
Short name T95
Test name
Test status
Simulation time 129061864 ps
CPU time 0.8 seconds
Started Jun 11 12:22:42 PM PDT 24
Finished Jun 11 12:22:45 PM PDT 24
Peak memory 189448 kb
Host smart-40b15b17-576b-4a4f-a8d8-5aa28d317df3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976148813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2976148813
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1841471164
Short name T576
Test name
Test status
Simulation time 1870719955 ps
CPU time 3.51 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:22:46 PM PDT 24
Peak memory 190260 kb
Host smart-3db2db0d-eea7-4b6b-bb51-97842996307f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841471164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1841471164
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2412247151
Short name T96
Test name
Test status
Simulation time 65222327 ps
CPU time 0.55 seconds
Started Jun 11 12:21:33 PM PDT 24
Finished Jun 11 12:21:34 PM PDT 24
Peak memory 182148 kb
Host smart-b71ff43d-7386-43e3-8560-64ccfbec3507
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412247151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2412247151
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.548063941
Short name T526
Test name
Test status
Simulation time 37550179 ps
CPU time 0.87 seconds
Started Jun 11 12:20:42 PM PDT 24
Finished Jun 11 12:20:44 PM PDT 24
Peak memory 196472 kb
Host smart-560a256d-b8d2-41cd-adce-380a6690db62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548063941 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.548063941
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.877089885
Short name T97
Test name
Test status
Simulation time 25737824 ps
CPU time 0.53 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:42 PM PDT 24
Peak memory 181628 kb
Host smart-4e62fff5-abba-4a8d-b8f0-9fd5295f0202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877089885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.877089885
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1096611516
Short name T572
Test name
Test status
Simulation time 12879643 ps
CPU time 0.54 seconds
Started Jun 11 12:19:08 PM PDT 24
Finished Jun 11 12:19:09 PM PDT 24
Peak memory 182060 kb
Host smart-6c57ed92-5f26-4793-91c2-ae4be21760bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096611516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1096611516
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.806676901
Short name T99
Test name
Test status
Simulation time 26132377 ps
CPU time 0.59 seconds
Started Jun 11 12:22:44 PM PDT 24
Finished Jun 11 12:22:48 PM PDT 24
Peak memory 191144 kb
Host smart-e704d027-79b1-4301-b472-76f2871de6c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806676901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.806676901
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1643353213
Short name T582
Test name
Test status
Simulation time 68099852 ps
CPU time 0.94 seconds
Started Jun 11 12:20:44 PM PDT 24
Finished Jun 11 12:20:46 PM PDT 24
Peak memory 196704 kb
Host smart-916e3be3-e479-4e5a-b3f4-20af93cfd9a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643353213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1643353213
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2204738739
Short name T478
Test name
Test status
Simulation time 1944407789 ps
CPU time 1.04 seconds
Started Jun 11 12:18:19 PM PDT 24
Finished Jun 11 12:18:21 PM PDT 24
Peak memory 182496 kb
Host smart-e87733de-c0fa-446f-b28d-27aaf36393d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204738739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2204738739
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3997675551
Short name T564
Test name
Test status
Simulation time 66803745 ps
CPU time 0.62 seconds
Started Jun 11 12:23:22 PM PDT 24
Finished Jun 11 12:23:26 PM PDT 24
Peak memory 180820 kb
Host smart-0db3ce51-f6d7-455a-ba91-14b9f0ae8336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997675551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3997675551
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2302125573
Short name T490
Test name
Test status
Simulation time 56510666 ps
CPU time 0.65 seconds
Started Jun 11 12:23:23 PM PDT 24
Finished Jun 11 12:23:27 PM PDT 24
Peak memory 179580 kb
Host smart-c9bb7b40-85da-4431-b534-c76ae9276b47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302125573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2302125573
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.4039736857
Short name T536
Test name
Test status
Simulation time 43998668 ps
CPU time 0.5 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:23:40 PM PDT 24
Peak memory 181148 kb
Host smart-0445f5a3-4a23-455e-bf7f-62f166398678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039736857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.4039736857
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2122820091
Short name T585
Test name
Test status
Simulation time 13694370 ps
CPU time 0.58 seconds
Started Jun 11 12:19:50 PM PDT 24
Finished Jun 11 12:19:52 PM PDT 24
Peak memory 179384 kb
Host smart-56c0506b-9e6e-4db8-b4f8-100470fcae4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122820091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2122820091
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2300792647
Short name T465
Test name
Test status
Simulation time 76683258 ps
CPU time 0.56 seconds
Started Jun 11 12:19:51 PM PDT 24
Finished Jun 11 12:19:53 PM PDT 24
Peak memory 181804 kb
Host smart-400cfe1f-9763-4bfa-8bf8-9465eff172f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300792647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2300792647
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2555423722
Short name T531
Test name
Test status
Simulation time 41288098 ps
CPU time 0.57 seconds
Started Jun 11 12:19:52 PM PDT 24
Finished Jun 11 12:19:55 PM PDT 24
Peak memory 181964 kb
Host smart-d74222c5-dcbb-49b9-a87a-0f5550576978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555423722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2555423722
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2028990609
Short name T554
Test name
Test status
Simulation time 14622543 ps
CPU time 0.62 seconds
Started Jun 11 12:18:13 PM PDT 24
Finished Jun 11 12:18:14 PM PDT 24
Peak memory 182084 kb
Host smart-38e3a278-a764-4751-9b09-399ced99c900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028990609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2028990609
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2815857356
Short name T470
Test name
Test status
Simulation time 84459420 ps
CPU time 0.52 seconds
Started Jun 11 12:23:46 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 181940 kb
Host smart-6b18772e-0ad7-41ab-8d03-0edd17a80a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815857356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2815857356
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1806150481
Short name T575
Test name
Test status
Simulation time 15727160 ps
CPU time 0.58 seconds
Started Jun 11 12:18:04 PM PDT 24
Finished Jun 11 12:18:05 PM PDT 24
Peak memory 181524 kb
Host smart-9e5805da-e85b-4007-8c67-dd84db328424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806150481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1806150481
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1965096768
Short name T506
Test name
Test status
Simulation time 25533940 ps
CPU time 0.52 seconds
Started Jun 11 12:19:52 PM PDT 24
Finished Jun 11 12:19:54 PM PDT 24
Peak memory 181620 kb
Host smart-639e63e8-c3dc-4b44-af03-511f297efd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965096768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1965096768
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1842785061
Short name T485
Test name
Test status
Simulation time 52519391 ps
CPU time 0.61 seconds
Started Jun 11 12:19:55 PM PDT 24
Finished Jun 11 12:19:57 PM PDT 24
Peak memory 192564 kb
Host smart-71c9b7ae-2351-44db-8afa-39d26c3fb87b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842785061 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1842785061
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1435489235
Short name T49
Test name
Test status
Simulation time 58896027 ps
CPU time 0.55 seconds
Started Jun 11 12:22:39 PM PDT 24
Finished Jun 11 12:22:41 PM PDT 24
Peak memory 181724 kb
Host smart-05704a00-26d1-49d9-9832-9722f46301f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435489235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1435489235
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1734539032
Short name T484
Test name
Test status
Simulation time 16930346 ps
CPU time 0.58 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 181808 kb
Host smart-43359dce-c9c5-49a0-848a-5ee027e6d23c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734539032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1734539032
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.4245938199
Short name T32
Test name
Test status
Simulation time 44822160 ps
CPU time 0.65 seconds
Started Jun 11 12:22:39 PM PDT 24
Finished Jun 11 12:22:41 PM PDT 24
Peak memory 192236 kb
Host smart-be224d71-c33e-4c6c-9bff-413ce1154601
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245938199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.4245938199
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3463061604
Short name T494
Test name
Test status
Simulation time 48007519 ps
CPU time 2.15 seconds
Started Jun 11 12:17:14 PM PDT 24
Finished Jun 11 12:17:17 PM PDT 24
Peak memory 196528 kb
Host smart-754c6384-5c51-4a55-90bf-213e8595c0be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463061604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3463061604
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1333296149
Short name T529
Test name
Test status
Simulation time 620066213 ps
CPU time 1.36 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:43 PM PDT 24
Peak memory 194516 kb
Host smart-ca667358-d043-4f18-baa8-43d8b98ef6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333296149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1333296149
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1787062019
Short name T477
Test name
Test status
Simulation time 48902698 ps
CPU time 1.14 seconds
Started Jun 11 12:17:57 PM PDT 24
Finished Jun 11 12:17:59 PM PDT 24
Peak memory 197416 kb
Host smart-0d6562c6-0c80-4509-b56d-5d5578457da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787062019 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1787062019
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1475327387
Short name T517
Test name
Test status
Simulation time 38595198 ps
CPU time 0.61 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:34 PM PDT 24
Peak memory 180840 kb
Host smart-490da7f7-46c2-474a-a5c7-ecb1cd609a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475327387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1475327387
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2041261869
Short name T481
Test name
Test status
Simulation time 11457555 ps
CPU time 0.51 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 181900 kb
Host smart-204de55f-ba4c-45a0-ad83-129763481d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041261869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2041261869
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2463276868
Short name T509
Test name
Test status
Simulation time 21038945 ps
CPU time 0.66 seconds
Started Jun 11 12:18:43 PM PDT 24
Finished Jun 11 12:18:45 PM PDT 24
Peak memory 191884 kb
Host smart-5fefb563-7720-427c-9712-7c6bc35b9e95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463276868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2463276868
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4197104573
Short name T578
Test name
Test status
Simulation time 33983585 ps
CPU time 1.58 seconds
Started Jun 11 12:22:38 PM PDT 24
Finished Jun 11 12:22:42 PM PDT 24
Peak memory 196068 kb
Host smart-e764ab5f-536c-4e1c-80ce-c539ec9bce07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197104573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4197104573
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.283786569
Short name T498
Test name
Test status
Simulation time 180268687 ps
CPU time 1.22 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 194196 kb
Host smart-a4045e8d-af9c-41e7-a89c-d380a364febd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283786569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.283786569
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1391500608
Short name T523
Test name
Test status
Simulation time 24818604 ps
CPU time 0.76 seconds
Started Jun 11 12:19:27 PM PDT 24
Finished Jun 11 12:19:28 PM PDT 24
Peak memory 194748 kb
Host smart-ec778676-1a3f-43ee-b290-38be2376da0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391500608 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1391500608
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.520944187
Short name T89
Test name
Test status
Simulation time 15216131 ps
CPU time 0.58 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:22:31 PM PDT 24
Peak memory 181828 kb
Host smart-ddac991a-cd17-48ba-98b9-9aeeaaf27f47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520944187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.520944187
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3175541005
Short name T524
Test name
Test status
Simulation time 15489975 ps
CPU time 0.55 seconds
Started Jun 11 12:19:26 PM PDT 24
Finished Jun 11 12:19:27 PM PDT 24
Peak memory 181876 kb
Host smart-ac539530-51d7-48ee-b888-95326f99f5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175541005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3175541005
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.4071325727
Short name T77
Test name
Test status
Simulation time 28516638 ps
CPU time 0.72 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:22:31 PM PDT 24
Peak memory 190824 kb
Host smart-f6a31643-3dd3-4e8f-856e-ed67bcbfbb2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071325727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.4071325727
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2318121502
Short name T546
Test name
Test status
Simulation time 564437854 ps
CPU time 2.52 seconds
Started Jun 11 12:17:27 PM PDT 24
Finished Jun 11 12:17:30 PM PDT 24
Peak memory 197416 kb
Host smart-244f113c-22d0-47b3-80d9-4c9763869415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318121502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2318121502
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1739055550
Short name T565
Test name
Test status
Simulation time 625548232 ps
CPU time 1.3 seconds
Started Jun 11 12:22:54 PM PDT 24
Finished Jun 11 12:22:58 PM PDT 24
Peak memory 182392 kb
Host smart-99498a3b-63b8-4625-9b0b-455b3ff89575
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739055550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1739055550
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2745892454
Short name T50
Test name
Test status
Simulation time 89780548 ps
CPU time 0.78 seconds
Started Jun 11 12:18:25 PM PDT 24
Finished Jun 11 12:18:26 PM PDT 24
Peak memory 194824 kb
Host smart-60dea86c-6174-4634-8d73-309828a863ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745892454 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2745892454
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1453822948
Short name T475
Test name
Test status
Simulation time 142169312 ps
CPU time 0.56 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:22:31 PM PDT 24
Peak memory 181676 kb
Host smart-726fd2b7-0fe6-4799-b8a1-525b6645b349
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453822948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1453822948
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1265120490
Short name T480
Test name
Test status
Simulation time 25936521 ps
CPU time 0.55 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:22:12 PM PDT 24
Peak memory 180744 kb
Host smart-97aec645-137b-44ca-8e19-70411d79d18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265120490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1265120490
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1886802425
Short name T98
Test name
Test status
Simulation time 131899350 ps
CPU time 0.75 seconds
Started Jun 11 12:19:51 PM PDT 24
Finished Jun 11 12:19:53 PM PDT 24
Peak memory 192476 kb
Host smart-a638aa91-6ed5-4074-ad89-3bfeb4e09180
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886802425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1886802425
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2814705807
Short name T539
Test name
Test status
Simulation time 630858009 ps
CPU time 2.77 seconds
Started Jun 11 12:17:23 PM PDT 24
Finished Jun 11 12:17:26 PM PDT 24
Peak memory 196972 kb
Host smart-fbbda19f-5da7-4294-baea-a21aa2f7ac8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814705807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2814705807
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1325231689
Short name T544
Test name
Test status
Simulation time 103862194 ps
CPU time 1.34 seconds
Started Jun 11 12:22:06 PM PDT 24
Finished Jun 11 12:22:10 PM PDT 24
Peak memory 180584 kb
Host smart-f9a9e0ea-0a8d-4c20-b808-d985250cb957
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325231689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1325231689
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.793870688
Short name T479
Test name
Test status
Simulation time 32256499 ps
CPU time 0.73 seconds
Started Jun 11 12:20:48 PM PDT 24
Finished Jun 11 12:20:49 PM PDT 24
Peak memory 194708 kb
Host smart-c0043b7b-3854-412c-a2d1-06a8617130e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793870688 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.793870688
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.771118754
Short name T94
Test name
Test status
Simulation time 17169943 ps
CPU time 0.57 seconds
Started Jun 11 12:20:12 PM PDT 24
Finished Jun 11 12:20:13 PM PDT 24
Peak memory 181876 kb
Host smart-b9d5ba74-57df-4dd9-8c21-bd8425536f51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771118754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.771118754
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.796611281
Short name T547
Test name
Test status
Simulation time 58969373 ps
CPU time 0.57 seconds
Started Jun 11 12:20:48 PM PDT 24
Finished Jun 11 12:20:49 PM PDT 24
Peak memory 182512 kb
Host smart-86ad5106-75c9-4acb-bff1-f52f3c970825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796611281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.796611281
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3097286005
Short name T550
Test name
Test status
Simulation time 143949874 ps
CPU time 0.8 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:22:37 PM PDT 24
Peak memory 190812 kb
Host smart-f3443e48-2434-4c38-b488-7701bb597883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097286005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3097286005
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1760149349
Short name T483
Test name
Test status
Simulation time 1414387697 ps
CPU time 1.89 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:22:57 PM PDT 24
Peak memory 196104 kb
Host smart-d99e56a1-deb5-4c4c-8ec3-fe48946094e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760149349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1760149349
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.402538297
Short name T106
Test name
Test status
Simulation time 417868497 ps
CPU time 1.34 seconds
Started Jun 11 12:19:26 PM PDT 24
Finished Jun 11 12:19:28 PM PDT 24
Peak memory 194756 kb
Host smart-64d94c16-65f0-4bb1-8041-da3816fd7ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402538297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.402538297
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1662965017
Short name T252
Test name
Test status
Simulation time 6934570673406 ps
CPU time 1577.74 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 182844 kb
Host smart-129786a6-6fee-4c17-86d4-c60e4411abdf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662965017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1662965017
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3827020423
Short name T411
Test name
Test status
Simulation time 108567895838 ps
CPU time 154.12 seconds
Started Jun 11 12:19:54 PM PDT 24
Finished Jun 11 12:22:30 PM PDT 24
Peak memory 182864 kb
Host smart-baa64b5d-755b-4367-a5c0-8841d2bb61a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827020423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3827020423
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3303693492
Short name T254
Test name
Test status
Simulation time 797335313243 ps
CPU time 303.26 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:27:35 PM PDT 24
Peak memory 189932 kb
Host smart-27a5fab9-4f06-4789-8b5e-07bbf432fc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303693492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3303693492
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3744778884
Short name T407
Test name
Test status
Simulation time 126475217 ps
CPU time 0.54 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 182624 kb
Host smart-ce37a2bf-dc2d-48da-92b4-4f6c36b0bcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744778884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3744778884
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.11542777
Short name T64
Test name
Test status
Simulation time 49265078855 ps
CPU time 68.19 seconds
Started Jun 11 12:17:56 PM PDT 24
Finished Jun 11 12:19:05 PM PDT 24
Peak memory 183244 kb
Host smart-ada086aa-e7a6-4d77-b009-194d07760cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11542777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.11542777
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2731175504
Short name T72
Test name
Test status
Simulation time 280378918435 ps
CPU time 233.99 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:26:20 PM PDT 24
Peak memory 182568 kb
Host smart-d2bcc6db-a27e-4f49-b258-0bc6d5fa9c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731175504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2731175504
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.532067721
Short name T205
Test name
Test status
Simulation time 593864901411 ps
CPU time 295.29 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:27:31 PM PDT 24
Peak memory 190820 kb
Host smart-0cb69bc4-4ddc-4350-be3c-77ba3bdd4348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532067721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.532067721
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2512462520
Short name T14
Test name
Test status
Simulation time 449074572 ps
CPU time 0.72 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:22:37 PM PDT 24
Peak memory 212968 kb
Host smart-1394d601-88b0-45fb-90fa-ecdebcd94d22
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512462520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2512462520
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3573201631
Short name T129
Test name
Test status
Simulation time 606641883679 ps
CPU time 379.21 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:29:39 PM PDT 24
Peak memory 182824 kb
Host smart-1b303851-a92f-4de4-901d-b0222b547cc0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573201631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3573201631
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2493403069
Short name T432
Test name
Test status
Simulation time 44871967557 ps
CPU time 61.31 seconds
Started Jun 11 12:23:12 PM PDT 24
Finished Jun 11 12:24:14 PM PDT 24
Peak memory 181976 kb
Host smart-4e33e36f-1fa6-48be-b355-33e99d4627f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493403069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2493403069
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2353923332
Short name T140
Test name
Test status
Simulation time 139125810490 ps
CPU time 320.08 seconds
Started Jun 11 12:23:18 PM PDT 24
Finished Jun 11 12:28:39 PM PDT 24
Peak memory 191012 kb
Host smart-3dbb06d1-07ca-46d8-b645-89d6435a55ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353923332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2353923332
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2495468156
Short name T157
Test name
Test status
Simulation time 74213077350 ps
CPU time 410.13 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:29:46 PM PDT 24
Peak memory 180712 kb
Host smart-258f27c2-4b3a-457f-9609-a197c2419289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495468156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2495468156
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.1693788547
Short name T221
Test name
Test status
Simulation time 233531977076 ps
CPU time 263.89 seconds
Started Jun 11 12:23:08 PM PDT 24
Finished Jun 11 12:27:33 PM PDT 24
Peak memory 194336 kb
Host smart-49a36ae0-dde7-49c2-a2aa-09b76c63037a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693788547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1693788547
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2446899877
Short name T248
Test name
Test status
Simulation time 23704295114 ps
CPU time 35.58 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:23:06 PM PDT 24
Peak memory 194332 kb
Host smart-38b1b87f-a1e5-44b4-be08-c71bbf7b7f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446899877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2446899877
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1066705924
Short name T119
Test name
Test status
Simulation time 92115681048 ps
CPU time 297.16 seconds
Started Jun 11 12:23:10 PM PDT 24
Finished Jun 11 12:28:08 PM PDT 24
Peak memory 191056 kb
Host smart-be52c0b5-f07c-42a4-97eb-641a0a72ab35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066705924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1066705924
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3664726552
Short name T130
Test name
Test status
Simulation time 15884146127 ps
CPU time 18.03 seconds
Started Jun 11 12:23:08 PM PDT 24
Finished Jun 11 12:23:27 PM PDT 24
Peak memory 182748 kb
Host smart-6ec1ca3e-0621-4737-bc8a-4b28bf4b94cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664726552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3664726552
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1953428926
Short name T76
Test name
Test status
Simulation time 42063513960 ps
CPU time 93.77 seconds
Started Jun 11 12:22:37 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 193980 kb
Host smart-1f22506f-bb0e-4433-b751-594444a63f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953428926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1953428926
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3086292325
Short name T382
Test name
Test status
Simulation time 87402918661 ps
CPU time 139.77 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:25:06 PM PDT 24
Peak memory 180980 kb
Host smart-8fe5047a-146b-4b73-beb1-7c818d15a7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086292325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3086292325
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1118232425
Short name T338
Test name
Test status
Simulation time 140833902680 ps
CPU time 238.19 seconds
Started Jun 11 12:22:52 PM PDT 24
Finished Jun 11 12:26:52 PM PDT 24
Peak memory 190928 kb
Host smart-6887be6c-735b-4117-97c8-ec83eb4e308a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118232425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1118232425
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.73714859
Short name T35
Test name
Test status
Simulation time 8419585642 ps
CPU time 62.12 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:24:33 PM PDT 24
Peak memory 194504 kb
Host smart-36537770-7bbd-4204-a132-4ce2b7a9f12a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73714859 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.73714859
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1406781304
Short name T284
Test name
Test status
Simulation time 780474043149 ps
CPU time 357.7 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:29:01 PM PDT 24
Peak memory 191020 kb
Host smart-68e162ca-5415-407b-9a88-5912776754f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406781304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1406781304
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2130023118
Short name T293
Test name
Test status
Simulation time 185378454401 ps
CPU time 155.14 seconds
Started Jun 11 12:22:36 PM PDT 24
Finished Jun 11 12:25:14 PM PDT 24
Peak memory 191036 kb
Host smart-6135bcbb-e13f-43af-9f79-eb81be0be73e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130023118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2130023118
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.124025150
Short name T298
Test name
Test status
Simulation time 85738086169 ps
CPU time 421.52 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:29:50 PM PDT 24
Peak memory 191452 kb
Host smart-a1ab1c2b-65e7-4e06-90f2-5fdd7eeca15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124025150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.124025150
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3136850909
Short name T400
Test name
Test status
Simulation time 96084173731 ps
CPU time 128.61 seconds
Started Jun 11 12:20:06 PM PDT 24
Finished Jun 11 12:22:16 PM PDT 24
Peak memory 182872 kb
Host smart-c760ef51-5f0d-4fb9-ae20-00ab5ad1678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136850909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3136850909
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1380881118
Short name T29
Test name
Test status
Simulation time 48853465572 ps
CPU time 78.71 seconds
Started Jun 11 12:22:51 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 190792 kb
Host smart-166d8970-2ad0-4946-8df0-d3ee1f89287b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380881118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1380881118
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3578123237
Short name T447
Test name
Test status
Simulation time 622721623 ps
CPU time 1.56 seconds
Started Jun 11 12:22:44 PM PDT 24
Finished Jun 11 12:22:48 PM PDT 24
Peak memory 182624 kb
Host smart-52a65b76-066c-4221-8f17-7206a6fb3f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578123237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3578123237
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.640125011
Short name T126
Test name
Test status
Simulation time 24971862824 ps
CPU time 37.56 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:23:40 PM PDT 24
Peak memory 191012 kb
Host smart-5cceb304-0bb8-4ba8-872d-4e056406248c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640125011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.640125011
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3225671659
Short name T356
Test name
Test status
Simulation time 49809377777 ps
CPU time 88.42 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:25:13 PM PDT 24
Peak memory 182848 kb
Host smart-fbfe2201-6f62-4c59-9146-dc34d5be75d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225671659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3225671659
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.4061925248
Short name T296
Test name
Test status
Simulation time 292366363373 ps
CPU time 39.23 seconds
Started Jun 11 12:23:00 PM PDT 24
Finished Jun 11 12:23:43 PM PDT 24
Peak memory 182812 kb
Host smart-1792c4cf-7519-4266-b42e-a743cf5aeeb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061925248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.4061925248
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1922492478
Short name T241
Test name
Test status
Simulation time 177099606834 ps
CPU time 204.89 seconds
Started Jun 11 12:23:03 PM PDT 24
Finished Jun 11 12:26:31 PM PDT 24
Peak memory 191048 kb
Host smart-4083d34a-8db5-4374-86dd-138fda1f18b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922492478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1922492478
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.353148248
Short name T245
Test name
Test status
Simulation time 99608979889 ps
CPU time 45.85 seconds
Started Jun 11 12:23:06 PM PDT 24
Finished Jun 11 12:23:53 PM PDT 24
Peak memory 182832 kb
Host smart-798446e3-e88b-43c9-a5fd-41712c4ce5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353148248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.353148248
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1145087096
Short name T21
Test name
Test status
Simulation time 62869059031 ps
CPU time 128.41 seconds
Started Jun 11 12:23:05 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 191048 kb
Host smart-0d5662e1-92e3-4e4c-827f-ca52782d1c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145087096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1145087096
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3157631239
Short name T132
Test name
Test status
Simulation time 235138743074 ps
CPU time 406.84 seconds
Started Jun 11 12:22:44 PM PDT 24
Finished Jun 11 12:29:33 PM PDT 24
Peak memory 182704 kb
Host smart-bdf1a464-eff1-4468-b06c-08a66ae568a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157631239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3157631239
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1585782014
Short name T58
Test name
Test status
Simulation time 417951007279 ps
CPU time 183.35 seconds
Started Jun 11 12:23:39 PM PDT 24
Finished Jun 11 12:26:45 PM PDT 24
Peak memory 182828 kb
Host smart-9798d702-40d7-46d1-88ff-301f5e21270c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585782014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1585782014
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.3305743646
Short name T299
Test name
Test status
Simulation time 24437210585 ps
CPU time 42.06 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:23:28 PM PDT 24
Peak memory 182628 kb
Host smart-d8759a59-d4f8-4bd6-99ec-269823c64005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305743646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3305743646
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3992746902
Short name T406
Test name
Test status
Simulation time 25686114265 ps
CPU time 15.16 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:23:47 PM PDT 24
Peak memory 192756 kb
Host smart-02604694-b46c-4391-9716-eef811b1bab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992746902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3992746902
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.999345781
Short name T435
Test name
Test status
Simulation time 19434425 ps
CPU time 0.53 seconds
Started Jun 11 12:23:38 PM PDT 24
Finished Jun 11 12:23:42 PM PDT 24
Peak memory 182028 kb
Host smart-506fa6de-dcf1-4bda-9818-e8df8e02e614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999345781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
999345781
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2492906424
Short name T103
Test name
Test status
Simulation time 40169629417 ps
CPU time 363.09 seconds
Started Jun 11 12:23:23 PM PDT 24
Finished Jun 11 12:29:29 PM PDT 24
Peak memory 194804 kb
Host smart-983a5161-1527-4068-97f8-bd7c53651b8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492906424 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2492906424
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.4170567403
Short name T362
Test name
Test status
Simulation time 112228799015 ps
CPU time 55.97 seconds
Started Jun 11 12:23:00 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 182836 kb
Host smart-4526c0f1-e8f7-41b6-a5b5-962174876e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170567403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.4170567403
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1739291340
Short name T159
Test name
Test status
Simulation time 77742431606 ps
CPU time 117.14 seconds
Started Jun 11 12:23:03 PM PDT 24
Finished Jun 11 12:25:03 PM PDT 24
Peak memory 190996 kb
Host smart-70e3badf-6484-40e6-b5c4-c642364f33fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739291340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1739291340
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.711107616
Short name T121
Test name
Test status
Simulation time 36170023617 ps
CPU time 55.5 seconds
Started Jun 11 12:23:00 PM PDT 24
Finished Jun 11 12:24:00 PM PDT 24
Peak memory 182812 kb
Host smart-11328abd-0220-4346-8722-9a7c98e9a770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711107616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.711107616
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3885600040
Short name T370
Test name
Test status
Simulation time 75309841375 ps
CPU time 1307.33 seconds
Started Jun 11 12:23:02 PM PDT 24
Finished Jun 11 12:44:53 PM PDT 24
Peak memory 191044 kb
Host smart-514ba5fc-c24b-434d-bc44-4fb97583496c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885600040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3885600040
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1989814897
Short name T194
Test name
Test status
Simulation time 146801116000 ps
CPU time 291.27 seconds
Started Jun 11 12:23:06 PM PDT 24
Finished Jun 11 12:27:58 PM PDT 24
Peak memory 190916 kb
Host smart-53be5820-0429-4f89-bf05-d72a889d9267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989814897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1989814897
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.58715580
Short name T173
Test name
Test status
Simulation time 383211914185 ps
CPU time 281.39 seconds
Started Jun 11 12:23:06 PM PDT 24
Finished Jun 11 12:27:49 PM PDT 24
Peak memory 191044 kb
Host smart-9581aeb4-22f9-4799-804f-2abedc6ab2b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58715580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.58715580
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1156588171
Short name T302
Test name
Test status
Simulation time 567215174995 ps
CPU time 974.34 seconds
Started Jun 11 12:23:02 PM PDT 24
Finished Jun 11 12:39:19 PM PDT 24
Peak memory 190984 kb
Host smart-0d54e9eb-1d25-43f1-8edc-2d5f3018789b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156588171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1156588171
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1708763106
Short name T216
Test name
Test status
Simulation time 418202607749 ps
CPU time 236.7 seconds
Started Jun 11 12:23:02 PM PDT 24
Finished Jun 11 12:27:02 PM PDT 24
Peak memory 190992 kb
Host smart-4823f0f1-6fae-4334-a961-33e87d235fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708763106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1708763106
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.495633044
Short name T287
Test name
Test status
Simulation time 62887702442 ps
CPU time 30.75 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:23:13 PM PDT 24
Peak memory 182512 kb
Host smart-5d94cc74-d5fe-4043-a05b-20459fbf7597
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495633044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.495633044
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3752547614
Short name T405
Test name
Test status
Simulation time 158946787768 ps
CPU time 264.72 seconds
Started Jun 11 12:22:44 PM PDT 24
Finished Jun 11 12:27:12 PM PDT 24
Peak memory 181492 kb
Host smart-a372aa7b-50ba-4b80-a0ab-64da6fdb1c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752547614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3752547614
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.4186911790
Short name T232
Test name
Test status
Simulation time 238768321110 ps
CPU time 100.14 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:24:23 PM PDT 24
Peak memory 189788 kb
Host smart-ab5e22f5-7e29-4766-8c80-f0a1b6f2e111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186911790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.4186911790
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3298650412
Short name T357
Test name
Test status
Simulation time 115927107012 ps
CPU time 53.22 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:23:26 PM PDT 24
Peak memory 190596 kb
Host smart-59cf115e-98d7-4a42-b64d-12536de5d5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298650412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3298650412
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.2742168805
Short name T438
Test name
Test status
Simulation time 369745118935 ps
CPU time 417.85 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:30:01 PM PDT 24
Peak memory 182848 kb
Host smart-29665332-05f7-4a33-af54-0ad7e68a98b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742168805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2742168805
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.320636817
Short name T322
Test name
Test status
Simulation time 334030032674 ps
CPU time 495.87 seconds
Started Jun 11 12:23:03 PM PDT 24
Finished Jun 11 12:31:22 PM PDT 24
Peak memory 190984 kb
Host smart-25e499b6-191a-44a9-8506-3dc04a11964a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320636817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.320636817
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3747928034
Short name T369
Test name
Test status
Simulation time 66228631766 ps
CPU time 69.48 seconds
Started Jun 11 12:23:03 PM PDT 24
Finished Jun 11 12:24:15 PM PDT 24
Peak memory 191048 kb
Host smart-a5535bbf-c33d-420a-b9d6-49f3b270719a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747928034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3747928034
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2851189056
Short name T328
Test name
Test status
Simulation time 116780677729 ps
CPU time 457.2 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:30:41 PM PDT 24
Peak memory 191044 kb
Host smart-a6c03187-f14f-4cc5-9fd3-ec88c0c61618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851189056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2851189056
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.4111414425
Short name T329
Test name
Test status
Simulation time 112372286255 ps
CPU time 75.36 seconds
Started Jun 11 12:23:02 PM PDT 24
Finished Jun 11 12:24:21 PM PDT 24
Peak memory 182844 kb
Host smart-75ced6c2-38d0-4dac-837c-59be150aff3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111414425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4111414425
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3713007878
Short name T344
Test name
Test status
Simulation time 17458485908 ps
CPU time 156.65 seconds
Started Jun 11 12:23:02 PM PDT 24
Finished Jun 11 12:25:42 PM PDT 24
Peak memory 182788 kb
Host smart-0e884c02-9833-4a0d-ad56-d4d4614887bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713007878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3713007878
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1832060433
Short name T307
Test name
Test status
Simulation time 43945733988 ps
CPU time 15.91 seconds
Started Jun 11 12:23:01 PM PDT 24
Finished Jun 11 12:23:21 PM PDT 24
Peak memory 182844 kb
Host smart-5f54ad20-57f6-4851-af91-97d37a4869a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832060433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1832060433
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2173271175
Short name T454
Test name
Test status
Simulation time 4874914666 ps
CPU time 3.16 seconds
Started Jun 11 12:20:33 PM PDT 24
Finished Jun 11 12:20:36 PM PDT 24
Peak memory 182920 kb
Host smart-de6ac313-9e48-4523-bbe2-a8b349df7634
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173271175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2173271175
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2380479659
Short name T22
Test name
Test status
Simulation time 233881809146 ps
CPU time 373.11 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:28:56 PM PDT 24
Peak memory 182420 kb
Host smart-7733eb2c-d7a0-4fd8-b2ef-abff2b8bc57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380479659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2380479659
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1921234495
Short name T131
Test name
Test status
Simulation time 34094922046 ps
CPU time 50.98 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:23:24 PM PDT 24
Peak memory 182276 kb
Host smart-3823a622-7325-4967-b509-500186abd6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921234495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1921234495
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1404165684
Short name T118
Test name
Test status
Simulation time 86025549677 ps
CPU time 175.72 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:25:30 PM PDT 24
Peak memory 190736 kb
Host smart-1d82a165-bc6b-4ef5-b925-cf36c56bc0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404165684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1404165684
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3519759498
Short name T334
Test name
Test status
Simulation time 92191012271 ps
CPU time 205.67 seconds
Started Jun 11 12:22:58 PM PDT 24
Finished Jun 11 12:26:28 PM PDT 24
Peak memory 205612 kb
Host smart-94bdf375-0214-4aef-a437-7927b4cfc315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519759498 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3519759498
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.4023859624
Short name T349
Test name
Test status
Simulation time 20307503376 ps
CPU time 10.8 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:23:58 PM PDT 24
Peak memory 182844 kb
Host smart-2c0178e9-af34-44bd-8f8f-1261c22d8eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023859624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4023859624
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.929464714
Short name T303
Test name
Test status
Simulation time 381463227632 ps
CPU time 132.04 seconds
Started Jun 11 12:23:08 PM PDT 24
Finished Jun 11 12:25:21 PM PDT 24
Peak memory 190960 kb
Host smart-27bac7e1-d2a1-4ea7-aa9b-1cecdbca9d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929464714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.929464714
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1992938597
Short name T413
Test name
Test status
Simulation time 29109365371 ps
CPU time 33.1 seconds
Started Jun 11 12:23:08 PM PDT 24
Finished Jun 11 12:23:42 PM PDT 24
Peak memory 182804 kb
Host smart-ad7a7e43-0cb9-4309-bb2b-f68151127379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992938597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1992938597
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.406715956
Short name T268
Test name
Test status
Simulation time 261250530000 ps
CPU time 327.07 seconds
Started Jun 11 12:23:05 PM PDT 24
Finished Jun 11 12:28:34 PM PDT 24
Peak memory 190964 kb
Host smart-cd480210-cb37-41b1-95d8-217130cb31d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406715956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.406715956
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.922418930
Short name T343
Test name
Test status
Simulation time 253457842141 ps
CPU time 94.45 seconds
Started Jun 11 12:23:10 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 191056 kb
Host smart-88b003a4-f5ce-4567-83fe-aa7717da17b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922418930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.922418930
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.865923191
Short name T261
Test name
Test status
Simulation time 65851649212 ps
CPU time 254.87 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:28:00 PM PDT 24
Peak memory 182832 kb
Host smart-d0555e9f-8543-416f-ad89-89e2a38bdbf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865923191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.865923191
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3629982370
Short name T188
Test name
Test status
Simulation time 32779924809 ps
CPU time 74.18 seconds
Started Jun 11 12:23:10 PM PDT 24
Finished Jun 11 12:24:25 PM PDT 24
Peak memory 191060 kb
Host smart-6d30395d-58fd-4411-88f6-2ac013be44c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629982370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3629982370
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2226830155
Short name T233
Test name
Test status
Simulation time 604829881233 ps
CPU time 562.44 seconds
Started Jun 11 12:22:50 PM PDT 24
Finished Jun 11 12:32:14 PM PDT 24
Peak memory 182460 kb
Host smart-95a1b4b5-95f3-4086-93bf-454dbd4f07fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226830155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2226830155
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.469487030
Short name T394
Test name
Test status
Simulation time 492405302534 ps
CPU time 202.16 seconds
Started Jun 11 12:19:39 PM PDT 24
Finished Jun 11 12:23:02 PM PDT 24
Peak memory 182860 kb
Host smart-4352f5c1-d910-4c1b-8180-f5d33b756e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469487030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.469487030
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.253117762
Short name T358
Test name
Test status
Simulation time 30889628122 ps
CPU time 92.14 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:24:07 PM PDT 24
Peak memory 190764 kb
Host smart-ccc43ec4-520c-4142-8ce6-d7a0ca799864
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253117762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.253117762
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2010167826
Short name T443
Test name
Test status
Simulation time 458763642 ps
CPU time 4.99 seconds
Started Jun 11 12:22:49 PM PDT 24
Finished Jun 11 12:22:56 PM PDT 24
Peak memory 189520 kb
Host smart-153e6502-17fa-40fa-ab9a-b276997a7690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010167826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2010167826
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.468344610
Short name T446
Test name
Test status
Simulation time 82659900 ps
CPU time 0.57 seconds
Started Jun 11 12:22:54 PM PDT 24
Finished Jun 11 12:22:57 PM PDT 24
Peak memory 182416 kb
Host smart-8447433d-5af0-4f7b-b2a1-0af5d0957724
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468344610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
468344610
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/163.rv_timer_random.348185386
Short name T462
Test name
Test status
Simulation time 100910130611 ps
CPU time 105.78 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:25:15 PM PDT 24
Peak memory 182780 kb
Host smart-f1731cb3-3c07-47f6-ba8b-e50a7a713f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348185386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.348185386
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1713847626
Short name T142
Test name
Test status
Simulation time 615046563065 ps
CPU time 330.04 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:29:04 PM PDT 24
Peak memory 190988 kb
Host smart-80ebeab5-da69-4f41-8982-b06ead2ee5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713847626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1713847626
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.868426939
Short name T361
Test name
Test status
Simulation time 42973427921 ps
CPU time 313.04 seconds
Started Jun 11 12:23:31 PM PDT 24
Finished Jun 11 12:28:48 PM PDT 24
Peak memory 182780 kb
Host smart-f1a5793c-be75-49b9-90fe-9f0fac6f5e7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868426939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.868426939
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.320514338
Short name T70
Test name
Test status
Simulation time 250921599587 ps
CPU time 327.85 seconds
Started Jun 11 12:23:22 PM PDT 24
Finished Jun 11 12:28:52 PM PDT 24
Peak memory 190948 kb
Host smart-76bad805-a95f-4324-a28d-e607e9d5034b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320514338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.320514338
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.183389353
Short name T4
Test name
Test status
Simulation time 484094244229 ps
CPU time 169.94 seconds
Started Jun 11 12:23:18 PM PDT 24
Finished Jun 11 12:26:09 PM PDT 24
Peak memory 182820 kb
Host smart-63874ce3-0238-424d-b0ec-069b63a4b246
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183389353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.183389353
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.4082863232
Short name T422
Test name
Test status
Simulation time 181689140253 ps
CPU time 254.67 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:26:26 PM PDT 24
Peak memory 182516 kb
Host smart-c5ad7681-1937-467b-9815-c44ec2074cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082863232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.4082863232
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.397714149
Short name T388
Test name
Test status
Simulation time 125198354 ps
CPU time 0.7 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:36 PM PDT 24
Peak memory 182244 kb
Host smart-aef76532-239b-4c1a-b5a4-083cecd46807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397714149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.397714149
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4140929371
Short name T451
Test name
Test status
Simulation time 937156203026 ps
CPU time 830.08 seconds
Started Jun 11 12:23:12 PM PDT 24
Finished Jun 11 12:37:04 PM PDT 24
Peak memory 190752 kb
Host smart-c6b16078-8e0d-43c3-b07e-3d6954f27c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140929371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4140929371
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1507194509
Short name T40
Test name
Test status
Simulation time 86607117154 ps
CPU time 662.12 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:34:06 PM PDT 24
Peak memory 207940 kb
Host smart-2c4096d6-a648-4a9e-ae03-26be9eea4035
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507194509 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1507194509
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.329235969
Short name T373
Test name
Test status
Simulation time 522385747287 ps
CPU time 211.3 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:27:02 PM PDT 24
Peak memory 191056 kb
Host smart-f5b37d17-c029-47c1-911e-be801f4ee3f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329235969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.329235969
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1560044512
Short name T291
Test name
Test status
Simulation time 93599297522 ps
CPU time 83.53 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:24:57 PM PDT 24
Peak memory 191104 kb
Host smart-637c4305-2ca0-4188-8f98-d1a72263cb19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560044512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1560044512
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1278164818
Short name T6
Test name
Test status
Simulation time 68401680116 ps
CPU time 32.31 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:24:04 PM PDT 24
Peak memory 182704 kb
Host smart-b7c687bc-283e-43e0-af0f-ae99cad82203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278164818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1278164818
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.327508363
Short name T229
Test name
Test status
Simulation time 136591390899 ps
CPU time 420.86 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:30:34 PM PDT 24
Peak memory 194396 kb
Host smart-a9a68445-9f80-4e95-a068-50b5b17f712b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327508363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.327508363
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.4238573735
Short name T147
Test name
Test status
Simulation time 337313106860 ps
CPU time 93.33 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:25:04 PM PDT 24
Peak memory 191020 kb
Host smart-4944ecd6-f2ec-4140-8cf3-651aa7774150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238573735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4238573735
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4286258386
Short name T208
Test name
Test status
Simulation time 65386711591 ps
CPU time 189.1 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:26:43 PM PDT 24
Peak memory 193660 kb
Host smart-9f52ce12-3f2a-4730-8bd7-5aec0b0ec8a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286258386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4286258386
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1324225053
Short name T385
Test name
Test status
Simulation time 47352892493 ps
CPU time 63.47 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:23:47 PM PDT 24
Peak memory 182564 kb
Host smart-bc5f63e0-fa79-43b8-b8e5-ec9098d4feb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324225053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1324225053
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2282673314
Short name T458
Test name
Test status
Simulation time 60432264536 ps
CPU time 54.26 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:24:25 PM PDT 24
Peak memory 182852 kb
Host smart-21ee7041-05f2-4e33-8911-6fd9dc5ea7ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282673314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2282673314
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3210759153
Short name T431
Test name
Test status
Simulation time 53935215 ps
CPU time 0.57 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:22:47 PM PDT 24
Peak memory 180772 kb
Host smart-f9f707b3-53bf-4b53-bb23-405f7f84baaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210759153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3210759153
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1781754809
Short name T166
Test name
Test status
Simulation time 381510818364 ps
CPU time 366.69 seconds
Started Jun 11 12:23:28 PM PDT 24
Finished Jun 11 12:29:40 PM PDT 24
Peak memory 194444 kb
Host smart-dd4ac6c1-5658-46bc-a2c3-b0c7cb75fac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781754809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1781754809
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2869995612
Short name T225
Test name
Test status
Simulation time 400290793671 ps
CPU time 814.24 seconds
Started Jun 11 12:23:29 PM PDT 24
Finished Jun 11 12:37:08 PM PDT 24
Peak memory 191104 kb
Host smart-f0050f8b-c29d-4874-ad30-2a7b7d6e0219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869995612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2869995612
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1835661095
Short name T176
Test name
Test status
Simulation time 58034476743 ps
CPU time 77.39 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 182796 kb
Host smart-747b0074-e060-44b1-9d2b-81258e98c492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835661095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1835661095
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1827143269
Short name T340
Test name
Test status
Simulation time 77816278280 ps
CPU time 840.69 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:37:31 PM PDT 24
Peak memory 191044 kb
Host smart-afb9d611-adea-4310-9f3a-4a9d8cb83582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827143269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1827143269
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.4140628307
Short name T348
Test name
Test status
Simulation time 69093757594 ps
CPU time 191.28 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:26:41 PM PDT 24
Peak memory 190976 kb
Host smart-9b0c1fc8-bc98-4bfa-8aef-41affc0ba402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140628307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.4140628307
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.972947293
Short name T308
Test name
Test status
Simulation time 107494393600 ps
CPU time 88.26 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:25:00 PM PDT 24
Peak memory 190912 kb
Host smart-2c76a8bb-2d66-48d5-93fc-bddaf827aacd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972947293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.972947293
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1606954844
Short name T144
Test name
Test status
Simulation time 288906683727 ps
CPU time 292.91 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:28:24 PM PDT 24
Peak memory 191060 kb
Host smart-7a3b7040-fee1-4667-adce-c065aaf26dff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606954844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1606954844
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3132288717
Short name T203
Test name
Test status
Simulation time 52731169507 ps
CPU time 87.76 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:24:48 PM PDT 24
Peak memory 182896 kb
Host smart-ff3a0ae9-e23f-4660-9160-286b2b07d871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132288717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3132288717
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1104241380
Short name T314
Test name
Test status
Simulation time 36788662540 ps
CPU time 73.6 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:24:45 PM PDT 24
Peak memory 190712 kb
Host smart-9744052b-24bb-400c-8857-d46e44f4ed4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104241380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1104241380
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2931179776
Short name T218
Test name
Test status
Simulation time 238338095294 ps
CPU time 133.14 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:25:44 PM PDT 24
Peak memory 191052 kb
Host smart-a285cac0-b443-4582-b60a-63b68154f94f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931179776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2931179776
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3529980486
Short name T75
Test name
Test status
Simulation time 956472470602 ps
CPU time 286.51 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:27:45 PM PDT 24
Peak memory 181820 kb
Host smart-4f81777d-36ec-449d-81df-45935f5c8f83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529980486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3529980486
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1597810101
Short name T43
Test name
Test status
Simulation time 377826911241 ps
CPU time 174.1 seconds
Started Jun 11 12:19:52 PM PDT 24
Finished Jun 11 12:22:48 PM PDT 24
Peak memory 182464 kb
Host smart-8e91b132-c2b9-46b6-8f0b-adcc38b9f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597810101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1597810101
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3591071442
Short name T278
Test name
Test status
Simulation time 71838875081 ps
CPU time 119.04 seconds
Started Jun 11 12:23:42 PM PDT 24
Finished Jun 11 12:25:44 PM PDT 24
Peak memory 190984 kb
Host smart-a8fc2178-3ff6-4e4d-8fe6-40911002609b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591071442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3591071442
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3872077685
Short name T459
Test name
Test status
Simulation time 32097058493 ps
CPU time 252.13 seconds
Started Jun 11 12:22:47 PM PDT 24
Finished Jun 11 12:27:02 PM PDT 24
Peak memory 195872 kb
Host smart-927e99d1-3511-4aef-8383-e7aff46168dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872077685 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3872077685
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/192.rv_timer_random.2705841588
Short name T137
Test name
Test status
Simulation time 445197935244 ps
CPU time 200.53 seconds
Started Jun 11 12:23:22 PM PDT 24
Finished Jun 11 12:26:45 PM PDT 24
Peak memory 190908 kb
Host smart-ad3b054e-774c-445e-ada5-4fc27983e1e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705841588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2705841588
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3427849532
Short name T415
Test name
Test status
Simulation time 227945769873 ps
CPU time 304.45 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:28:36 PM PDT 24
Peak memory 191044 kb
Host smart-966524f3-28bb-4793-beb2-61f1f49d363a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427849532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3427849532
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3380518123
Short name T316
Test name
Test status
Simulation time 238835591174 ps
CPU time 586.26 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:33:18 PM PDT 24
Peak memory 190712 kb
Host smart-a81bdc36-d77a-46e1-a3ce-2c0c49fc3377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380518123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3380518123
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2864218645
Short name T300
Test name
Test status
Simulation time 273927094615 ps
CPU time 143.08 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:26:03 PM PDT 24
Peak memory 191128 kb
Host smart-29ff71f6-1264-4448-8a2f-57872493465c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864218645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2864218645
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4213834384
Short name T315
Test name
Test status
Simulation time 12465165148 ps
CPU time 25.42 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:23:55 PM PDT 24
Peak memory 182776 kb
Host smart-fe126ebb-80f9-4b4b-b3c3-ba927f9b1c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213834384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4213834384
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3185057701
Short name T337
Test name
Test status
Simulation time 48163407359 ps
CPU time 78.65 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:24:50 PM PDT 24
Peak memory 194648 kb
Host smart-2585c039-78e8-458d-9117-28c140e73914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185057701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3185057701
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3122269571
Short name T364
Test name
Test status
Simulation time 444878560497 ps
CPU time 720.67 seconds
Started Jun 11 12:21:33 PM PDT 24
Finished Jun 11 12:33:34 PM PDT 24
Peak memory 182836 kb
Host smart-ff2d19c4-9fd6-4e12-9b16-625d13c772a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122269571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3122269571
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2968635515
Short name T403
Test name
Test status
Simulation time 191482894748 ps
CPU time 90.74 seconds
Started Jun 11 12:22:25 PM PDT 24
Finished Jun 11 12:23:57 PM PDT 24
Peak memory 181992 kb
Host smart-f0cc0319-fc15-4f3f-b187-f47c1376460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968635515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2968635515
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.87726863
Short name T115
Test name
Test status
Simulation time 197534676068 ps
CPU time 184.65 seconds
Started Jun 11 12:20:41 PM PDT 24
Finished Jun 11 12:23:47 PM PDT 24
Peak memory 191024 kb
Host smart-4e4ce0c5-95af-414b-9d23-085995d835f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87726863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.87726863
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2417998657
Short name T449
Test name
Test status
Simulation time 112292552580 ps
CPU time 144.72 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:25:07 PM PDT 24
Peak memory 193948 kb
Host smart-e02dddf0-51ed-4cb5-b2ad-d033b5935527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417998657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2417998657
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4116582448
Short name T17
Test name
Test status
Simulation time 98333388 ps
CPU time 0.83 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:22:59 PM PDT 24
Peak memory 213224 kb
Host smart-d5a86c78-52be-4b82-869c-27c71a34b65a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116582448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4116582448
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.910173243
Short name T410
Test name
Test status
Simulation time 43951986838 ps
CPU time 37.48 seconds
Started Jun 11 12:18:46 PM PDT 24
Finished Jun 11 12:19:24 PM PDT 24
Peak memory 182780 kb
Host smart-34671555-6b8b-4134-a59f-4f70cf81d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910173243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.910173243
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1384526968
Short name T231
Test name
Test status
Simulation time 143472037452 ps
CPU time 171.5 seconds
Started Jun 11 12:22:52 PM PDT 24
Finished Jun 11 12:25:45 PM PDT 24
Peak memory 190912 kb
Host smart-730b013d-94b9-4630-be10-2d3006fb8f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384526968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1384526968
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2965811470
Short name T419
Test name
Test status
Simulation time 755221821 ps
CPU time 1.3 seconds
Started Jun 11 12:23:38 PM PDT 24
Finished Jun 11 12:23:43 PM PDT 24
Peak memory 193884 kb
Host smart-fc6ded68-fcfd-41cb-9247-e3a63a10c740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965811470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2965811470
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.212872002
Short name T387
Test name
Test status
Simulation time 129839626864 ps
CPU time 192.16 seconds
Started Jun 11 12:23:27 PM PDT 24
Finished Jun 11 12:26:44 PM PDT 24
Peak memory 189940 kb
Host smart-b12ef7dd-76ee-4705-8128-1f420dee80b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212872002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
212872002
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1927949884
Short name T259
Test name
Test status
Simulation time 1338229373532 ps
CPU time 637.91 seconds
Started Jun 11 12:23:36 PM PDT 24
Finished Jun 11 12:34:18 PM PDT 24
Peak memory 182512 kb
Host smart-1bc2bebf-95cc-411a-8920-52bfceb69e01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927949884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1927949884
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1141945366
Short name T390
Test name
Test status
Simulation time 8402583112 ps
CPU time 9.37 seconds
Started Jun 11 12:23:37 PM PDT 24
Finished Jun 11 12:23:50 PM PDT 24
Peak memory 182660 kb
Host smart-ea8f9e35-62bb-40f9-811b-c3f25411eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141945366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1141945366
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1646226386
Short name T150
Test name
Test status
Simulation time 67432183755 ps
CPU time 108.6 seconds
Started Jun 11 12:19:50 PM PDT 24
Finished Jun 11 12:21:40 PM PDT 24
Peak memory 188936 kb
Host smart-1444c1e8-0ce6-4099-ae9c-ae0805252bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646226386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1646226386
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3097057422
Short name T310
Test name
Test status
Simulation time 369022319545 ps
CPU time 550.3 seconds
Started Jun 11 12:22:42 PM PDT 24
Finished Jun 11 12:31:54 PM PDT 24
Peak memory 182556 kb
Host smart-990e8c07-588c-4deb-801e-ecce05cd1c48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097057422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3097057422
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2552765787
Short name T412
Test name
Test status
Simulation time 74828537778 ps
CPU time 96.53 seconds
Started Jun 11 12:19:19 PM PDT 24
Finished Jun 11 12:20:57 PM PDT 24
Peak memory 182852 kb
Host smart-d7bf2575-c3c2-46be-a0f9-29e6ce528b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552765787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2552765787
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2926323115
Short name T317
Test name
Test status
Simulation time 10421590325 ps
CPU time 22.82 seconds
Started Jun 11 12:20:26 PM PDT 24
Finished Jun 11 12:20:50 PM PDT 24
Peak memory 182884 kb
Host smart-c9429848-9ee2-4c61-827b-dcf993d22f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926323115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2926323115
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1348469130
Short name T421
Test name
Test status
Simulation time 1580776789 ps
CPU time 3.79 seconds
Started Jun 11 12:22:42 PM PDT 24
Finished Jun 11 12:22:48 PM PDT 24
Peak memory 190832 kb
Host smart-0d0b2506-12fb-49e9-98e0-6790a5dd18fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348469130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1348469130
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1592196731
Short name T201
Test name
Test status
Simulation time 202089536632 ps
CPU time 374.15 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:29:09 PM PDT 24
Peak memory 194064 kb
Host smart-0ce85cd9-204a-4e9d-8f69-ebbb12808394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592196731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1592196731
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1832762461
Short name T8
Test name
Test status
Simulation time 162797531100 ps
CPU time 256.05 seconds
Started Jun 11 12:22:41 PM PDT 24
Finished Jun 11 12:26:59 PM PDT 24
Peak memory 182452 kb
Host smart-d9508ae5-b87a-4d7b-97b0-1b19d7223e82
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832762461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1832762461
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2680031923
Short name T24
Test name
Test status
Simulation time 142670167548 ps
CPU time 211.16 seconds
Started Jun 11 12:18:25 PM PDT 24
Finished Jun 11 12:21:57 PM PDT 24
Peak memory 182780 kb
Host smart-e5a9b672-3693-4463-b914-421df5de00fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680031923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2680031923
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.499716132
Short name T69
Test name
Test status
Simulation time 50819008096 ps
CPU time 82.66 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:24:08 PM PDT 24
Peak memory 182640 kb
Host smart-b1110b27-08bf-4231-9031-fc6a949e6d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499716132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.499716132
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2808265167
Short name T179
Test name
Test status
Simulation time 262697490345 ps
CPU time 139.89 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:24:53 PM PDT 24
Peak memory 181668 kb
Host smart-ac63b8fb-757c-47c8-9fe9-c9e591d6869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808265167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2808265167
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.765904211
Short name T367
Test name
Test status
Simulation time 301308459031 ps
CPU time 126.41 seconds
Started Jun 11 12:17:39 PM PDT 24
Finished Jun 11 12:19:46 PM PDT 24
Peak memory 194856 kb
Host smart-5c94b95a-b8bd-4fd5-9509-12ec10d5d984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765904211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
765904211
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.334217554
Short name T39
Test name
Test status
Simulation time 30784786650 ps
CPU time 240.93 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:26:37 PM PDT 24
Peak memory 197260 kb
Host smart-42036f25-3c4d-4687-bbdf-ab9271e773a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334217554 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.334217554
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1217733236
Short name T253
Test name
Test status
Simulation time 177304614919 ps
CPU time 192.46 seconds
Started Jun 11 12:22:49 PM PDT 24
Finished Jun 11 12:26:04 PM PDT 24
Peak memory 181492 kb
Host smart-64983de8-d521-40e6-b439-a8c066a157ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217733236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1217733236
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.626242302
Short name T384
Test name
Test status
Simulation time 281431083690 ps
CPU time 194.07 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:25:47 PM PDT 24
Peak memory 181416 kb
Host smart-6ba03ac2-74c9-44a3-b5bc-d8380975d057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626242302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.626242302
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.956545645
Short name T381
Test name
Test status
Simulation time 13095315798 ps
CPU time 38.13 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:22:50 PM PDT 24
Peak memory 190760 kb
Host smart-e97346ab-881d-4692-9f0e-f97245c3b97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956545645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.956545645
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2557611571
Short name T309
Test name
Test status
Simulation time 224144865732 ps
CPU time 1094.51 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:41:54 PM PDT 24
Peak memory 190724 kb
Host smart-ef5426cd-9cb6-4164-ae58-270bb7a38bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557611571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2557611571
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2679244581
Short name T445
Test name
Test status
Simulation time 289911316211 ps
CPU time 197.34 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:25:29 PM PDT 24
Peak memory 182552 kb
Host smart-856b1a47-aae0-4ae4-abb8-643d220da41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679244581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2679244581
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1850742932
Short name T56
Test name
Test status
Simulation time 3485944488 ps
CPU time 9.22 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:09 PM PDT 24
Peak memory 191952 kb
Host smart-d4064697-366f-4e9a-a492-e4f38b46b3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850742932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1850742932
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1280960222
Short name T323
Test name
Test status
Simulation time 351606398770 ps
CPU time 906.96 seconds
Started Jun 11 12:17:57 PM PDT 24
Finished Jun 11 12:33:05 PM PDT 24
Peak memory 195852 kb
Host smart-60dd9cfa-4446-4e26-abe0-24c9c67ab468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280960222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1280960222
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3221068281
Short name T12
Test name
Test status
Simulation time 19967611283 ps
CPU time 134.06 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:24:25 PM PDT 24
Peak memory 196360 kb
Host smart-627d42b8-ecb7-4e2c-9a37-b2fc5dd6ce3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221068281 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3221068281
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3458390108
Short name T262
Test name
Test status
Simulation time 539188948297 ps
CPU time 307.77 seconds
Started Jun 11 12:20:42 PM PDT 24
Finished Jun 11 12:25:50 PM PDT 24
Peak memory 182836 kb
Host smart-f37a7e1b-94de-4883-be4a-1f406de71749
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458390108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3458390108
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2612028216
Short name T430
Test name
Test status
Simulation time 35725258091 ps
CPU time 60.68 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:23:26 PM PDT 24
Peak memory 181284 kb
Host smart-ba66e6a0-f880-45de-b87c-bcab590e6fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612028216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2612028216
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1071589093
Short name T10
Test name
Test status
Simulation time 93999513878 ps
CPU time 165.4 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:25:20 PM PDT 24
Peak memory 190652 kb
Host smart-3050139e-a5a3-46c4-8498-877bb4bb1e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071589093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1071589093
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1357306384
Short name T74
Test name
Test status
Simulation time 626698440357 ps
CPU time 1147.79 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:41:54 PM PDT 24
Peak memory 190964 kb
Host smart-fb8a7e50-8d46-403e-837e-6049132552fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357306384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1357306384
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1606631052
Short name T36
Test name
Test status
Simulation time 79374484098 ps
CPU time 582.58 seconds
Started Jun 11 12:20:42 PM PDT 24
Finished Jun 11 12:30:25 PM PDT 24
Peak memory 205676 kb
Host smart-95cd1cb4-8bf3-4247-aa11-9181b640f294
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606631052 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1606631052
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1903246574
Short name T355
Test name
Test status
Simulation time 736400849740 ps
CPU time 409.11 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:29:44 PM PDT 24
Peak memory 181856 kb
Host smart-b0c69db4-aec5-44f2-8cdd-46f9b1ab5ad5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903246574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1903246574
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2637638359
Short name T386
Test name
Test status
Simulation time 146766218405 ps
CPU time 242.35 seconds
Started Jun 11 12:19:21 PM PDT 24
Finished Jun 11 12:23:24 PM PDT 24
Peak memory 182780 kb
Host smart-5983d749-b897-4afd-befa-ce4240883a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637638359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2637638359
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3564532307
Short name T332
Test name
Test status
Simulation time 99149059757 ps
CPU time 1748.99 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:52:04 PM PDT 24
Peak memory 193488 kb
Host smart-b604a428-030c-45f5-bc1e-9196ddebaba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564532307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3564532307
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1416196360
Short name T47
Test name
Test status
Simulation time 68506384161 ps
CPU time 310.97 seconds
Started Jun 11 12:20:25 PM PDT 24
Finished Jun 11 12:25:36 PM PDT 24
Peak memory 191440 kb
Host smart-7c422966-7785-4b1f-8dbb-f217a975421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416196360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1416196360
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1038946499
Short name T183
Test name
Test status
Simulation time 482306943926 ps
CPU time 656.94 seconds
Started Jun 11 12:20:10 PM PDT 24
Finished Jun 11 12:31:08 PM PDT 24
Peak memory 178996 kb
Host smart-1b552991-b02b-4fbd-a326-c3a6dd3372e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038946499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1038946499
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1801578456
Short name T434
Test name
Test status
Simulation time 111661103807 ps
CPU time 182.65 seconds
Started Jun 11 12:20:43 PM PDT 24
Finished Jun 11 12:23:47 PM PDT 24
Peak memory 182776 kb
Host smart-af7c7bba-2e45-4315-818b-dbe8860c1401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801578456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1801578456
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2399401131
Short name T271
Test name
Test status
Simulation time 33665120809 ps
CPU time 42.29 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:23:08 PM PDT 24
Peak memory 182096 kb
Host smart-408441ae-68b1-48c6-b340-5df228b33924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399401131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2399401131
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.172648937
Short name T123
Test name
Test status
Simulation time 164372575458 ps
CPU time 814.45 seconds
Started Jun 11 12:20:10 PM PDT 24
Finished Jun 11 12:33:45 PM PDT 24
Peak memory 188696 kb
Host smart-776ea595-9aa5-43a1-b997-fb595f3dac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172648937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.172648937
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1136648320
Short name T219
Test name
Test status
Simulation time 187951216524 ps
CPU time 458.85 seconds
Started Jun 11 12:21:27 PM PDT 24
Finished Jun 11 12:29:07 PM PDT 24
Peak memory 194952 kb
Host smart-6161ed46-5902-4d1c-b7e7-bb37fe64e31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136648320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1136648320
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.720145688
Short name T428
Test name
Test status
Simulation time 541478063854 ps
CPU time 271.61 seconds
Started Jun 11 12:19:02 PM PDT 24
Finished Jun 11 12:23:34 PM PDT 24
Peak memory 183240 kb
Host smart-efecea4f-bc1d-4079-9d5b-3db40666d7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720145688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.720145688
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.56288408
Short name T311
Test name
Test status
Simulation time 56031879540 ps
CPU time 506.23 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:31:25 PM PDT 24
Peak memory 190224 kb
Host smart-9fe2724d-a669-4151-b25e-e66023fcb4de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56288408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.56288408
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1026112999
Short name T363
Test name
Test status
Simulation time 97725523068 ps
CPU time 604.5 seconds
Started Jun 11 12:19:00 PM PDT 24
Finished Jun 11 12:29:05 PM PDT 24
Peak memory 194408 kb
Host smart-8d5dac25-1f4a-448d-bd79-cdb2f31eb9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026112999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1026112999
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.515264239
Short name T456
Test name
Test status
Simulation time 718521830668 ps
CPU time 379.75 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:29:22 PM PDT 24
Peak memory 182348 kb
Host smart-4ba08bbe-a50d-44c6-88bc-def390b5c1ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515264239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.515264239
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1458467892
Short name T71
Test name
Test status
Simulation time 325447107462 ps
CPU time 234.72 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:26:40 PM PDT 24
Peak memory 181980 kb
Host smart-387edf29-a0be-4920-9021-f7af8fd1cdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458467892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1458467892
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1282879773
Short name T127
Test name
Test status
Simulation time 101302433539 ps
CPU time 161.18 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:25:23 PM PDT 24
Peak memory 189520 kb
Host smart-330310de-ca14-49b1-a4a5-0eb31d2a5a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282879773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1282879773
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2359600744
Short name T442
Test name
Test status
Simulation time 19592459631 ps
CPU time 36.08 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 189128 kb
Host smart-d392f743-8d80-4c9e-9070-0c93e503f19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359600744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2359600744
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3609287190
Short name T13
Test name
Test status
Simulation time 352425285 ps
CPU time 0.88 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:43 PM PDT 24
Peak memory 213948 kb
Host smart-0f7b8c2d-d77b-4c2b-aab8-4a2765d587b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609287190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3609287190
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2589095193
Short name T193
Test name
Test status
Simulation time 1869038713008 ps
CPU time 944.08 seconds
Started Jun 11 12:20:36 PM PDT 24
Finished Jun 11 12:36:21 PM PDT 24
Peak memory 191432 kb
Host smart-08a1c15d-d7cd-4431-9cb4-9fef210c3bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589095193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2589095193
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2886840896
Short name T425
Test name
Test status
Simulation time 855329096685 ps
CPU time 118.67 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:25:38 PM PDT 24
Peak memory 182492 kb
Host smart-a065b1d1-801d-44ba-a3cf-3ddabb3ee037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886840896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2886840896
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.4190665373
Short name T182
Test name
Test status
Simulation time 314719730245 ps
CPU time 444.07 seconds
Started Jun 11 12:20:51 PM PDT 24
Finished Jun 11 12:28:16 PM PDT 24
Peak memory 191436 kb
Host smart-5384e3d7-e471-4457-82c7-e72689123402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190665373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4190665373
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.534619332
Short name T350
Test name
Test status
Simulation time 200635545491 ps
CPU time 51.53 seconds
Started Jun 11 12:23:13 PM PDT 24
Finished Jun 11 12:24:06 PM PDT 24
Peak memory 182580 kb
Host smart-83c1462b-c044-4bad-9a48-57a2a92c12c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534619332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.534619332
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1865432055
Short name T34
Test name
Test status
Simulation time 123046341643 ps
CPU time 477.33 seconds
Started Jun 11 12:21:29 PM PDT 24
Finished Jun 11 12:29:27 PM PDT 24
Peak memory 197444 kb
Host smart-fce59088-a45c-4f03-ada3-41374ead574d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865432055 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1865432055
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2716101378
Short name T247
Test name
Test status
Simulation time 220641492846 ps
CPU time 111.02 seconds
Started Jun 11 12:20:10 PM PDT 24
Finished Jun 11 12:22:02 PM PDT 24
Peak memory 181248 kb
Host smart-e2c7bbb3-db64-448a-bcbe-b3fd3013ef8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716101378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2716101378
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.726004456
Short name T409
Test name
Test status
Simulation time 239399928141 ps
CPU time 209.75 seconds
Started Jun 11 12:18:47 PM PDT 24
Finished Jun 11 12:22:18 PM PDT 24
Peak memory 182872 kb
Host smart-1f42598c-84d1-4827-b254-e25616505ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726004456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.726004456
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2948948312
Short name T25
Test name
Test status
Simulation time 52680549542 ps
CPU time 60.26 seconds
Started Jun 11 12:23:11 PM PDT 24
Finished Jun 11 12:24:13 PM PDT 24
Peak memory 181436 kb
Host smart-80b1fb13-90a8-4c5a-bd64-d26a03e99529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948948312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2948948312
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3789499382
Short name T135
Test name
Test status
Simulation time 234115516717 ps
CPU time 226.08 seconds
Started Jun 11 12:20:06 PM PDT 24
Finished Jun 11 12:23:52 PM PDT 24
Peak memory 190988 kb
Host smart-a6e11623-a308-4fa2-9a91-0a5d0338f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789499382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3789499382
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2875969336
Short name T402
Test name
Test status
Simulation time 443113772465 ps
CPU time 181.11 seconds
Started Jun 11 12:20:12 PM PDT 24
Finished Jun 11 12:23:14 PM PDT 24
Peak memory 194296 kb
Host smart-81b7e85f-f51c-4e9d-96a0-699ec0a1f674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875969336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2875969336
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1544727779
Short name T267
Test name
Test status
Simulation time 530088596213 ps
CPU time 699.22 seconds
Started Jun 11 12:20:12 PM PDT 24
Finished Jun 11 12:31:52 PM PDT 24
Peak memory 182600 kb
Host smart-bc0e617a-6be4-41ee-b895-2459b90305d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544727779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1544727779
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2413173332
Short name T395
Test name
Test status
Simulation time 246343029398 ps
CPU time 173.56 seconds
Started Jun 11 12:23:11 PM PDT 24
Finished Jun 11 12:26:06 PM PDT 24
Peak memory 181148 kb
Host smart-e9331e40-78e7-468e-a779-f6f6b312d832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413173332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2413173332
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1110770020
Short name T170
Test name
Test status
Simulation time 99418514912 ps
CPU time 154.55 seconds
Started Jun 11 12:20:10 PM PDT 24
Finished Jun 11 12:22:45 PM PDT 24
Peak memory 191188 kb
Host smart-89ad2229-fce2-4ca3-bc4d-0d703612d0dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110770020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1110770020
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2673843918
Short name T375
Test name
Test status
Simulation time 969610960 ps
CPU time 1.33 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:22:26 PM PDT 24
Peak memory 191856 kb
Host smart-434721c3-45fa-4ac1-94f9-ed1b141e8040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673843918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2673843918
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3501027401
Short name T197
Test name
Test status
Simulation time 1995827529908 ps
CPU time 736.75 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:34:42 PM PDT 24
Peak memory 190652 kb
Host smart-43434a3a-3602-4202-b345-1edbaeebc195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501027401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3501027401
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2066478803
Short name T427
Test name
Test status
Simulation time 38849493828 ps
CPU time 394.03 seconds
Started Jun 11 12:22:23 PM PDT 24
Finished Jun 11 12:28:59 PM PDT 24
Peak memory 203668 kb
Host smart-8c6dd25f-d94f-4ae3-ae2d-a38beabbe56c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066478803 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2066478803
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3243871378
Short name T55
Test name
Test status
Simulation time 57524493112 ps
CPU time 16.24 seconds
Started Jun 11 12:22:26 PM PDT 24
Finished Jun 11 12:22:43 PM PDT 24
Peak memory 182768 kb
Host smart-416972e4-4c09-4677-ac04-e01db970ec72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243871378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3243871378
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.2628309905
Short name T320
Test name
Test status
Simulation time 277511764629 ps
CPU time 1057.12 seconds
Started Jun 11 12:20:10 PM PDT 24
Finished Jun 11 12:37:48 PM PDT 24
Peak memory 188960 kb
Host smart-06610251-4e9f-4615-a56a-535c41702ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628309905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2628309905
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2156936533
Short name T117
Test name
Test status
Simulation time 356119622733 ps
CPU time 196.93 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:25:42 PM PDT 24
Peak memory 194676 kb
Host smart-b60b12f2-84bb-43f8-820c-fb13fad437ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156936533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2156936533
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3997298000
Short name T336
Test name
Test status
Simulation time 3755458414598 ps
CPU time 1247.3 seconds
Started Jun 11 12:23:13 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 182616 kb
Host smart-92b124bf-3818-4603-a251-c9a8d13efe1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997298000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3997298000
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.78034789
Short name T423
Test name
Test status
Simulation time 287042606427 ps
CPU time 229.89 seconds
Started Jun 11 12:20:12 PM PDT 24
Finished Jun 11 12:24:02 PM PDT 24
Peak memory 182592 kb
Host smart-7ef4154d-c334-45fa-96d3-3495a019fbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78034789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.78034789
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1352533289
Short name T124
Test name
Test status
Simulation time 71267554316 ps
CPU time 68.32 seconds
Started Jun 11 12:19:05 PM PDT 24
Finished Jun 11 12:20:14 PM PDT 24
Peak memory 195000 kb
Host smart-7ebc00cb-f18f-4630-b172-3c913415c970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352533289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1352533289
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3841217490
Short name T339
Test name
Test status
Simulation time 14789326780 ps
CPU time 23.97 seconds
Started Jun 11 12:22:11 PM PDT 24
Finished Jun 11 12:22:37 PM PDT 24
Peak memory 182368 kb
Host smart-c485916e-d877-4d65-9dce-2807a649848d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841217490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3841217490
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1581999263
Short name T178
Test name
Test status
Simulation time 1545042689495 ps
CPU time 4286.96 seconds
Started Jun 11 12:19:14 PM PDT 24
Finished Jun 11 01:30:42 PM PDT 24
Peak memory 191084 kb
Host smart-a0304193-a6d7-483e-8395-1c9655ef1fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581999263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1581999263
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1071101157
Short name T276
Test name
Test status
Simulation time 246476054549 ps
CPU time 422.56 seconds
Started Jun 11 12:22:39 PM PDT 24
Finished Jun 11 12:29:44 PM PDT 24
Peak memory 181224 kb
Host smart-0a338c32-8241-43fb-882f-4cc0841012ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071101157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1071101157
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.802237783
Short name T393
Test name
Test status
Simulation time 590030038615 ps
CPU time 211.53 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:26:13 PM PDT 24
Peak memory 182356 kb
Host smart-f4a5d04e-f7d4-4125-a98b-6bf74c6c1b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802237783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.802237783
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2054726069
Short name T288
Test name
Test status
Simulation time 418639639717 ps
CPU time 1541.33 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:49:10 PM PDT 24
Peak memory 190932 kb
Host smart-ffe51dac-1b64-4ae5-8e0c-70bb0b52206c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054726069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2054726069
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1080767826
Short name T209
Test name
Test status
Simulation time 158554236557 ps
CPU time 207.27 seconds
Started Jun 11 12:19:25 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 195196 kb
Host smart-57e5bf99-de82-4327-b4c8-d9fb4e320c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080767826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1080767826
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1937380303
Short name T196
Test name
Test status
Simulation time 1318317876421 ps
CPU time 886 seconds
Started Jun 11 12:22:39 PM PDT 24
Finished Jun 11 12:37:27 PM PDT 24
Peak memory 181356 kb
Host smart-9d427d3d-4b8c-42c9-82d4-f845b1d228ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937380303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1937380303
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1091960029
Short name T102
Test name
Test status
Simulation time 52498400278 ps
CPU time 400.82 seconds
Started Jun 11 12:23:23 PM PDT 24
Finished Jun 11 12:30:07 PM PDT 24
Peak memory 203432 kb
Host smart-9b7975b8-0369-433d-8897-982a3cb4e706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091960029 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1091960029
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2859775792
Short name T1
Test name
Test status
Simulation time 337725611810 ps
CPU time 547.72 seconds
Started Jun 11 12:19:24 PM PDT 24
Finished Jun 11 12:28:33 PM PDT 24
Peak memory 183236 kb
Host smart-6eaac1e5-216c-446f-bebe-8f7eafaa800e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859775792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2859775792
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.652009544
Short name T399
Test name
Test status
Simulation time 87012218035 ps
CPU time 125.26 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:24:47 PM PDT 24
Peak memory 182432 kb
Host smart-e3e7b7f5-87b8-4dd8-9ab5-c7165eb19d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652009544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.652009544
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1852558905
Short name T264
Test name
Test status
Simulation time 338874741035 ps
CPU time 173.08 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:25:48 PM PDT 24
Peak memory 190900 kb
Host smart-f96139a5-4550-4b52-9401-11e086c9c3b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852558905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1852558905
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3037140706
Short name T441
Test name
Test status
Simulation time 20744471 ps
CPU time 0.51 seconds
Started Jun 11 12:22:43 PM PDT 24
Finished Jun 11 12:22:47 PM PDT 24
Peak memory 182288 kb
Host smart-3f33064b-c099-4eaa-81dd-2363ecef5f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037140706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3037140706
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2170731572
Short name T408
Test name
Test status
Simulation time 43290700 ps
CPU time 0.64 seconds
Started Jun 11 12:19:36 PM PDT 24
Finished Jun 11 12:19:37 PM PDT 24
Peak memory 183032 kb
Host smart-0117bea8-e897-40f6-8260-0f337af5203f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170731572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2170731572
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2782450425
Short name T353
Test name
Test status
Simulation time 1145028904635 ps
CPU time 309.21 seconds
Started Jun 11 12:23:17 PM PDT 24
Finished Jun 11 12:28:27 PM PDT 24
Peak memory 182776 kb
Host smart-c10c2feb-e36f-4e24-93d6-d7e04b104720
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782450425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2782450425
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2339304761
Short name T437
Test name
Test status
Simulation time 332011401208 ps
CPU time 279.15 seconds
Started Jun 11 12:19:42 PM PDT 24
Finished Jun 11 12:24:22 PM PDT 24
Peak memory 183240 kb
Host smart-ec2a37ee-895e-4b26-8313-01ac58330bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339304761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2339304761
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1423363438
Short name T134
Test name
Test status
Simulation time 92775845456 ps
CPU time 286.48 seconds
Started Jun 11 12:19:47 PM PDT 24
Finished Jun 11 12:24:34 PM PDT 24
Peak memory 192472 kb
Host smart-230e9175-462c-46c0-bd3f-7203fd94901e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423363438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1423363438
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2233575407
Short name T215
Test name
Test status
Simulation time 64307938375 ps
CPU time 57.11 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:23:26 PM PDT 24
Peak memory 180868 kb
Host smart-a02d0013-cda5-4c1e-a081-c52845f5d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233575407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2233575407
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1801675251
Short name T65
Test name
Test status
Simulation time 1082693767882 ps
CPU time 416.48 seconds
Started Jun 11 12:19:55 PM PDT 24
Finished Jun 11 12:26:53 PM PDT 24
Peak memory 191064 kb
Host smart-5b9ed4b5-6b4c-44ea-987a-cd00b35329f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801675251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1801675251
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.909903096
Short name T244
Test name
Test status
Simulation time 98479803813 ps
CPU time 162.81 seconds
Started Jun 11 12:20:10 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 183236 kb
Host smart-25c58ef9-dc60-4807-a71e-5926cc8225e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909903096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.909903096
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2877446527
Short name T398
Test name
Test status
Simulation time 143517299173 ps
CPU time 221.55 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:26:11 PM PDT 24
Peak memory 181068 kb
Host smart-fa4ae42b-79a0-45df-8e73-e19d9750a9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877446527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2877446527
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1545100890
Short name T202
Test name
Test status
Simulation time 247406816621 ps
CPU time 147.64 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:24:57 PM PDT 24
Peak memory 182460 kb
Host smart-8b209560-d2da-404f-bf5f-e0dedebf6b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545100890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1545100890
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.65691351
Short name T270
Test name
Test status
Simulation time 165963443147 ps
CPU time 187.53 seconds
Started Jun 11 12:19:41 PM PDT 24
Finished Jun 11 12:22:50 PM PDT 24
Peak memory 191428 kb
Host smart-f78bb74a-7b37-4223-b982-6502bf167e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65691351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.65691351
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3454709224
Short name T66
Test name
Test status
Simulation time 1024832562962 ps
CPU time 405.34 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:29:43 PM PDT 24
Peak memory 190752 kb
Host smart-046354aa-1cbd-4375-855a-9a08379f8d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454709224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3454709224
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2711382150
Short name T171
Test name
Test status
Simulation time 2663683695 ps
CPU time 2.86 seconds
Started Jun 11 12:19:48 PM PDT 24
Finished Jun 11 12:19:52 PM PDT 24
Peak memory 183240 kb
Host smart-fbeeb77e-fba2-4b0e-be6c-39ea2d2e8c0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711382150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2711382150
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.499224653
Short name T378
Test name
Test status
Simulation time 200805682992 ps
CPU time 309.37 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:28:10 PM PDT 24
Peak memory 182652 kb
Host smart-9c8c4d63-d08c-4b16-aa76-a06af9ab0a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499224653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.499224653
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2111366038
Short name T155
Test name
Test status
Simulation time 728317237573 ps
CPU time 500.19 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:31:21 PM PDT 24
Peak memory 194360 kb
Host smart-f92086bb-8ac8-4e66-b586-b3064e1d8cc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111366038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2111366038
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3595640507
Short name T453
Test name
Test status
Simulation time 570347588538 ps
CPU time 384.52 seconds
Started Jun 11 12:23:18 PM PDT 24
Finished Jun 11 12:29:43 PM PDT 24
Peak memory 195524 kb
Host smart-b021f68b-cd0b-4d25-b127-85a738b470ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595640507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3595640507
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.161011066
Short name T37
Test name
Test status
Simulation time 21229252437 ps
CPU time 144.96 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:25:23 PM PDT 24
Peak memory 197220 kb
Host smart-2fa802ca-7c3d-4d57-959f-83230c71d657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161011066 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.161011066
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1340961080
Short name T207
Test name
Test status
Simulation time 15107587962 ps
CPU time 24.96 seconds
Started Jun 11 12:20:41 PM PDT 24
Finished Jun 11 12:21:07 PM PDT 24
Peak memory 182836 kb
Host smart-47e850b8-f0d7-4ce5-88d2-96bd336c5b84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340961080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1340961080
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3276212476
Short name T376
Test name
Test status
Simulation time 558232261599 ps
CPU time 226.91 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:26:46 PM PDT 24
Peak memory 182480 kb
Host smart-a7106a3f-af67-44ff-b9a5-f76f5443f331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276212476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3276212476
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.219054680
Short name T139
Test name
Test status
Simulation time 45233829495 ps
CPU time 645.16 seconds
Started Jun 11 12:22:58 PM PDT 24
Finished Jun 11 12:33:47 PM PDT 24
Peak memory 190840 kb
Host smart-8aaa18df-7614-47e2-abfa-10d44967e4c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219054680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.219054680
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.742087740
Short name T429
Test name
Test status
Simulation time 59674614497 ps
CPU time 60.46 seconds
Started Jun 11 12:18:42 PM PDT 24
Finished Jun 11 12:19:43 PM PDT 24
Peak memory 191072 kb
Host smart-bea82c78-18b2-4c8f-ad77-177aa3417160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742087740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.742087740
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.214327981
Short name T15
Test name
Test status
Simulation time 155777818 ps
CPU time 0.89 seconds
Started Jun 11 12:22:40 PM PDT 24
Finished Jun 11 12:22:43 PM PDT 24
Peak memory 214136 kb
Host smart-9a8fdf16-d194-43c2-990a-167a81614f42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214327981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.214327981
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.253624728
Short name T164
Test name
Test status
Simulation time 392756863073 ps
CPU time 1347.54 seconds
Started Jun 11 12:22:58 PM PDT 24
Finished Jun 11 12:45:29 PM PDT 24
Peak memory 190500 kb
Host smart-db4d1697-efe0-464c-9fab-44efe3162fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253624728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.253624728
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1379056031
Short name T38
Test name
Test status
Simulation time 25330353523 ps
CPU time 176.48 seconds
Started Jun 11 12:20:41 PM PDT 24
Finished Jun 11 12:23:39 PM PDT 24
Peak memory 205672 kb
Host smart-8187da66-338a-4032-93bf-36b9c1bff653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379056031 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1379056031
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.343792196
Short name T185
Test name
Test status
Simulation time 131889291787 ps
CPU time 231.77 seconds
Started Jun 11 12:23:18 PM PDT 24
Finished Jun 11 12:27:11 PM PDT 24
Peak memory 182820 kb
Host smart-a20421bc-6242-48a1-8d2b-d59a879082d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343792196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.343792196
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.506871914
Short name T42
Test name
Test status
Simulation time 209269579182 ps
CPU time 252.39 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:27:11 PM PDT 24
Peak memory 182820 kb
Host smart-849b69bf-c966-4b9c-a7f2-9fb401991122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506871914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.506871914
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3102768118
Short name T366
Test name
Test status
Simulation time 139368941941 ps
CPU time 284.46 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:27:32 PM PDT 24
Peak memory 190232 kb
Host smart-b7355acb-63ad-4369-a804-b9b7bf6e62f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102768118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3102768118
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.178238514
Short name T60
Test name
Test status
Simulation time 51149724408 ps
CPU time 89.96 seconds
Started Jun 11 12:19:54 PM PDT 24
Finished Jun 11 12:21:26 PM PDT 24
Peak memory 195048 kb
Host smart-ed9e635d-4033-443b-aa11-3cae9056f72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178238514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.178238514
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1089910258
Short name T392
Test name
Test status
Simulation time 128992040684 ps
CPU time 197.37 seconds
Started Jun 11 12:22:24 PM PDT 24
Finished Jun 11 12:25:42 PM PDT 24
Peak memory 181632 kb
Host smart-6fe4b50d-9427-4e5d-b8bd-e79832318d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089910258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1089910258
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2119402896
Short name T426
Test name
Test status
Simulation time 82035266489 ps
CPU time 386.36 seconds
Started Jun 11 12:20:16 PM PDT 24
Finished Jun 11 12:26:43 PM PDT 24
Peak memory 191452 kb
Host smart-8560b4d3-80c7-4690-ac98-c5aaa0818936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119402896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2119402896
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1447060695
Short name T379
Test name
Test status
Simulation time 114946845 ps
CPU time 0.58 seconds
Started Jun 11 12:22:53 PM PDT 24
Finished Jun 11 12:22:56 PM PDT 24
Peak memory 180852 kb
Host smart-2d989586-0f2f-452b-a44f-be0b6c264410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447060695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1447060695
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2485697715
Short name T212
Test name
Test status
Simulation time 143949195256 ps
CPU time 176.77 seconds
Started Jun 11 12:20:17 PM PDT 24
Finished Jun 11 12:23:15 PM PDT 24
Peak memory 191448 kb
Host smart-25e0ba3e-99b8-43af-b9de-9acc90437c58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485697715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2485697715
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.2449427076
Short name T11
Test name
Test status
Simulation time 199337615096 ps
CPU time 398.73 seconds
Started Jun 11 12:23:17 PM PDT 24
Finished Jun 11 12:29:57 PM PDT 24
Peak memory 204680 kb
Host smart-a22104ff-3257-4517-b38c-7881ba1e00fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449427076 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.2449427076
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3349768467
Short name T418
Test name
Test status
Simulation time 82382106529 ps
CPU time 127.57 seconds
Started Jun 11 12:23:07 PM PDT 24
Finished Jun 11 12:25:16 PM PDT 24
Peak memory 182764 kb
Host smart-59ff55ec-5295-467f-b580-41137f6cf84c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349768467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3349768467
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.628567143
Short name T404
Test name
Test status
Simulation time 126544883114 ps
CPU time 217.67 seconds
Started Jun 11 12:20:25 PM PDT 24
Finished Jun 11 12:24:03 PM PDT 24
Peak memory 183240 kb
Host smart-a1edc76c-cef0-4fd1-b1ea-f50267c4f622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628567143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.628567143
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3574242416
Short name T222
Test name
Test status
Simulation time 30811532936 ps
CPU time 170.82 seconds
Started Jun 11 12:22:58 PM PDT 24
Finished Jun 11 12:25:53 PM PDT 24
Peak memory 182660 kb
Host smart-79f29110-16ae-4405-8428-ee6f1e980973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574242416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3574242416
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.333658721
Short name T275
Test name
Test status
Simulation time 62785283525 ps
CPU time 70.29 seconds
Started Jun 11 12:21:49 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 183212 kb
Host smart-e1d5df6c-4315-48a7-8361-f87fc063a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333658721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.333658721
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3090270067
Short name T417
Test name
Test status
Simulation time 733029781211 ps
CPU time 376.32 seconds
Started Jun 11 12:23:13 PM PDT 24
Finished Jun 11 12:29:30 PM PDT 24
Peak memory 182784 kb
Host smart-80499bb9-ff4d-480c-a5b8-89b9974ac176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090270067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3090270067
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2146205432
Short name T283
Test name
Test status
Simulation time 114795131196 ps
CPU time 165.67 seconds
Started Jun 11 12:20:39 PM PDT 24
Finished Jun 11 12:23:25 PM PDT 24
Peak memory 191028 kb
Host smart-1abfa53c-afbc-4eeb-9552-17e853839202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146205432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2146205432
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.838954856
Short name T285
Test name
Test status
Simulation time 47124665196 ps
CPU time 66.08 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:24:07 PM PDT 24
Peak memory 182704 kb
Host smart-56e07b4b-17fb-4f5a-b4d4-ef4c65c64817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838954856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.838954856
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2094163203
Short name T439
Test name
Test status
Simulation time 527766103706 ps
CPU time 216.44 seconds
Started Jun 11 12:22:48 PM PDT 24
Finished Jun 11 12:26:27 PM PDT 24
Peak memory 182644 kb
Host smart-0e70bfcd-c8f8-488e-bfc6-f504e6023d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094163203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2094163203
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.4292517621
Short name T444
Test name
Test status
Simulation time 47217657035 ps
CPU time 88.88 seconds
Started Jun 11 12:20:45 PM PDT 24
Finished Jun 11 12:22:15 PM PDT 24
Peak memory 182916 kb
Host smart-2277b432-444d-4737-972b-b2c557385c33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292517621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.4292517621
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2081946901
Short name T414
Test name
Test status
Simulation time 14949089163 ps
CPU time 20.28 seconds
Started Jun 11 12:22:46 PM PDT 24
Finished Jun 11 12:23:09 PM PDT 24
Peak memory 182424 kb
Host smart-29a7e89d-069b-4514-8328-ad2ab9b9e192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081946901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2081946901
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.4124225919
Short name T251
Test name
Test status
Simulation time 305083664509 ps
CPU time 157.72 seconds
Started Jun 11 12:20:42 PM PDT 24
Finished Jun 11 12:23:21 PM PDT 24
Peak memory 190992 kb
Host smart-7523561d-01b6-42a8-a554-7b80fbeb475b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124225919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4124225919
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3603416926
Short name T3
Test name
Test status
Simulation time 464880289 ps
CPU time 0.66 seconds
Started Jun 11 12:22:56 PM PDT 24
Finished Jun 11 12:23:00 PM PDT 24
Peak memory 182288 kb
Host smart-486e57a3-5b40-4107-b380-b0c77ce884d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603416926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3603416926
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3676660280
Short name T280
Test name
Test status
Simulation time 523517686328 ps
CPU time 832.58 seconds
Started Jun 11 12:20:36 PM PDT 24
Finished Jun 11 12:34:29 PM PDT 24
Peak memory 191088 kb
Host smart-35d7a194-0f32-4cbe-9f60-de20e883db83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676660280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3676660280
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.375686723
Short name T23
Test name
Test status
Simulation time 19948346792 ps
CPU time 33.09 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:23:22 PM PDT 24
Peak memory 182448 kb
Host smart-90c4b1f6-6225-4f98-8e97-08c4aad6002d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375686723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.375686723
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3673820091
Short name T420
Test name
Test status
Simulation time 27420499836 ps
CPU time 38.63 seconds
Started Jun 11 12:20:49 PM PDT 24
Finished Jun 11 12:21:29 PM PDT 24
Peak memory 182744 kb
Host smart-a931b591-9e45-4c42-a606-ab9e9b443a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673820091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3673820091
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.532784863
Short name T351
Test name
Test status
Simulation time 22871605949 ps
CPU time 40.45 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:23:28 PM PDT 24
Peak memory 181572 kb
Host smart-3e0c135c-62fa-40a4-aa49-d578c3e9cb91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532784863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.532784863
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3947523933
Short name T416
Test name
Test status
Simulation time 9335495881 ps
CPU time 29.39 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:23:04 PM PDT 24
Peak memory 181688 kb
Host smart-a486fd99-746b-42e9-95d5-ceca7b02eb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947523933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3947523933
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.3510466347
Short name T440
Test name
Test status
Simulation time 359505205294 ps
CPU time 724.15 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:35:08 PM PDT 24
Peak memory 209092 kb
Host smart-dcba832f-3184-4386-856b-cd7d45e4ed11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510466347 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.3510466347
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.538139400
Short name T255
Test name
Test status
Simulation time 90710708334 ps
CPU time 51.22 seconds
Started Jun 11 12:20:46 PM PDT 24
Finished Jun 11 12:21:38 PM PDT 24
Peak memory 182900 kb
Host smart-07a62a1e-7ed9-4557-88c1-b3e2eba95edb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538139400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.538139400
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1942609824
Short name T389
Test name
Test status
Simulation time 1074077037 ps
CPU time 2.38 seconds
Started Jun 11 12:20:47 PM PDT 24
Finished Jun 11 12:20:50 PM PDT 24
Peak memory 182680 kb
Host smart-2a36e2a5-e21a-4b00-99b5-ead19a74a334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942609824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1942609824
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.532810998
Short name T374
Test name
Test status
Simulation time 55877343336 ps
CPU time 138.82 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:25:23 PM PDT 24
Peak memory 190964 kb
Host smart-29b85e2d-6d30-443b-9cfd-e85c064796d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532810998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.532810998
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2394841574
Short name T154
Test name
Test status
Simulation time 331352724114 ps
CPU time 156.21 seconds
Started Jun 11 12:22:46 PM PDT 24
Finished Jun 11 12:25:25 PM PDT 24
Peak memory 182460 kb
Host smart-c2ff3c23-d317-4c5b-be3a-b0ebf432ef5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394841574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2394841574
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1996476896
Short name T436
Test name
Test status
Simulation time 26428942560 ps
CPU time 45.87 seconds
Started Jun 11 12:21:48 PM PDT 24
Finished Jun 11 12:22:35 PM PDT 24
Peak memory 182876 kb
Host smart-8cd9e4b4-5d0f-442b-a844-d853f1d5718f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996476896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1996476896
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2963357641
Short name T460
Test name
Test status
Simulation time 433767061499 ps
CPU time 132.04 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:24:43 PM PDT 24
Peak memory 182524 kb
Host smart-46034442-958f-498f-b2ef-8b3672d7a861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963357641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2963357641
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3073749223
Short name T257
Test name
Test status
Simulation time 388307549166 ps
CPU time 803.39 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:36:11 PM PDT 24
Peak memory 190148 kb
Host smart-f1d610c3-54b6-4aa3-ac30-bb5166f11238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073749223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3073749223
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3699899079
Short name T292
Test name
Test status
Simulation time 46540255523 ps
CPU time 74.64 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:23:46 PM PDT 24
Peak memory 190728 kb
Host smart-cec1e525-dc54-4a1b-a090-04750e33139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699899079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3699899079
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.823626104
Short name T396
Test name
Test status
Simulation time 287162412475 ps
CPU time 210.52 seconds
Started Jun 11 12:22:46 PM PDT 24
Finished Jun 11 12:26:19 PM PDT 24
Peak memory 182468 kb
Host smart-17943476-c76d-4a9f-b8ef-3ec13f3e83cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823626104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
823626104
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3453155509
Short name T256
Test name
Test status
Simulation time 439984473212 ps
CPU time 440.19 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:30:08 PM PDT 24
Peak memory 181684 kb
Host smart-66419dc6-a015-4978-9ed7-bddc6e6b8a31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453155509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3453155509
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.962173962
Short name T424
Test name
Test status
Simulation time 133912637041 ps
CPU time 106.83 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:25:26 PM PDT 24
Peak memory 182488 kb
Host smart-5453f28f-6dca-4f59-9d4c-5834c2f18d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962173962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.962173962
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.313125028
Short name T450
Test name
Test status
Simulation time 14272914263 ps
CPU time 56.01 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:23:44 PM PDT 24
Peak memory 181820 kb
Host smart-49a5b62f-271a-4146-811e-924b7613c677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313125028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.313125028
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2540076459
Short name T312
Test name
Test status
Simulation time 32405355109 ps
CPU time 51.08 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:24:22 PM PDT 24
Peak memory 181572 kb
Host smart-3e420d9a-af65-484e-9186-dd185bc47933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540076459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2540076459
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1097647753
Short name T448
Test name
Test status
Simulation time 4451456636574 ps
CPU time 1044.9 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:40:01 PM PDT 24
Peak memory 182556 kb
Host smart-d8f3ce83-cf1a-4d1a-8b7e-a05a9021148d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097647753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1097647753
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2486825386
Short name T401
Test name
Test status
Simulation time 9113733065 ps
CPU time 3.32 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:39 PM PDT 24
Peak memory 182524 kb
Host smart-16a2e046-10c0-47ff-bea4-fc31772ccce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486825386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2486825386
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.4193290083
Short name T234
Test name
Test status
Simulation time 11448733930 ps
CPU time 20.07 seconds
Started Jun 11 12:22:45 PM PDT 24
Finished Jun 11 12:23:09 PM PDT 24
Peak memory 182416 kb
Host smart-fcb8892b-92ee-4754-9e0d-c49b9e65a57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193290083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4193290083
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1986642711
Short name T165
Test name
Test status
Simulation time 802964891323 ps
CPU time 667.35 seconds
Started Jun 11 12:21:35 PM PDT 24
Finished Jun 11 12:32:44 PM PDT 24
Peak memory 194944 kb
Host smart-a6d45a60-d9bb-4096-9816-490311fc3b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986642711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1986642711
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3467154820
Short name T360
Test name
Test status
Simulation time 24455080971 ps
CPU time 12.89 seconds
Started Jun 11 12:23:21 PM PDT 24
Finished Jun 11 12:23:36 PM PDT 24
Peak memory 182780 kb
Host smart-22c9f137-a505-41f6-9a9a-60be622d1e40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467154820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3467154820
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2009628024
Short name T452
Test name
Test status
Simulation time 104639288257 ps
CPU time 162.93 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:25:12 PM PDT 24
Peak memory 181680 kb
Host smart-66273621-eda2-4df9-92f1-97a6cd60f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009628024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2009628024
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.4078868902
Short name T306
Test name
Test status
Simulation time 120173059408 ps
CPU time 83.07 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:23:54 PM PDT 24
Peak memory 182568 kb
Host smart-212a599a-2cd3-475a-8755-baf765b4569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078868902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4078868902
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3442564311
Short name T192
Test name
Test status
Simulation time 126459168094 ps
CPU time 225.36 seconds
Started Jun 11 12:21:37 PM PDT 24
Finished Jun 11 12:25:23 PM PDT 24
Peak memory 191076 kb
Host smart-f56872cd-71c8-4120-83a9-43f21fc49048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442564311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3442564311
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1583308736
Short name T148
Test name
Test status
Simulation time 2662078910 ps
CPU time 4.99 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:22:40 PM PDT 24
Peak memory 182428 kb
Host smart-725ede50-0973-49de-a88c-ee8049ac8a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583308736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1583308736
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3641521259
Short name T143
Test name
Test status
Simulation time 66420354149 ps
CPU time 95.7 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:24:06 PM PDT 24
Peak memory 189676 kb
Host smart-00ec5a1d-da36-4bd4-aadb-9b867fa6fe2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641521259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3641521259
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3266706035
Short name T325
Test name
Test status
Simulation time 105670325835 ps
CPU time 273.01 seconds
Started Jun 11 12:22:23 PM PDT 24
Finished Jun 11 12:26:58 PM PDT 24
Peak memory 189044 kb
Host smart-ebfe4295-14c8-480f-9745-e36018ab0f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266706035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3266706035
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.223679408
Short name T345
Test name
Test status
Simulation time 147040616899 ps
CPU time 514.6 seconds
Started Jun 11 12:21:08 PM PDT 24
Finished Jun 11 12:29:43 PM PDT 24
Peak memory 191016 kb
Host smart-112e9849-53f2-4886-839b-6c6bfd702c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223679408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.223679408
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.837148153
Short name T44
Test name
Test status
Simulation time 62791988230 ps
CPU time 113.27 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:24:25 PM PDT 24
Peak memory 182536 kb
Host smart-9932a8a4-39d4-4122-a488-e38d368a21df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837148153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.837148153
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1698025863
Short name T461
Test name
Test status
Simulation time 38325129128 ps
CPU time 66.66 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:23:19 PM PDT 24
Peak memory 182420 kb
Host smart-d2b6f459-4d96-4afd-80b9-a605961e27b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698025863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1698025863
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2174420500
Short name T41
Test name
Test status
Simulation time 108401765402 ps
CPU time 66.18 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:23:18 PM PDT 24
Peak memory 182508 kb
Host smart-f0cdc7d9-1433-4f6e-ac08-035616aae06b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174420500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2174420500
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.316863368
Short name T321
Test name
Test status
Simulation time 47635655799 ps
CPU time 80.72 seconds
Started Jun 11 12:22:08 PM PDT 24
Finished Jun 11 12:23:32 PM PDT 24
Peak memory 189024 kb
Host smart-da0431a1-9dfb-470f-93c6-0768230dd9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316863368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.316863368
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2402322593
Short name T54
Test name
Test status
Simulation time 21777277218 ps
CPU time 36.77 seconds
Started Jun 11 12:21:14 PM PDT 24
Finished Jun 11 12:21:52 PM PDT 24
Peak memory 182856 kb
Host smart-d98ba0ef-7a98-44eb-ba64-8f863eb0ced8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402322593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2402322593
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.501995948
Short name T380
Test name
Test status
Simulation time 47351156561 ps
CPU time 68.49 seconds
Started Jun 11 12:19:51 PM PDT 24
Finished Jun 11 12:21:02 PM PDT 24
Peak memory 182568 kb
Host smart-aa409e03-6f27-432a-8923-cdb5ae2e2a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501995948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.501995948
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.180746635
Short name T433
Test name
Test status
Simulation time 91342546 ps
CPU time 0.61 seconds
Started Jun 11 12:19:50 PM PDT 24
Finished Jun 11 12:19:53 PM PDT 24
Peak memory 180328 kb
Host smart-72b5086d-5061-4500-8c86-7dd3bba23881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180746635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.180746635
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1484144913
Short name T169
Test name
Test status
Simulation time 2002709156643 ps
CPU time 793.74 seconds
Started Jun 11 12:18:27 PM PDT 24
Finished Jun 11 12:31:42 PM PDT 24
Peak memory 191032 kb
Host smart-eebe1c8c-ab16-42d9-b08c-0f3631c6955f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484144913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1484144913
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.1055349470
Short name T457
Test name
Test status
Simulation time 120738769068 ps
CPU time 240.48 seconds
Started Jun 11 12:22:27 PM PDT 24
Finished Jun 11 12:26:30 PM PDT 24
Peak memory 204596 kb
Host smart-887b6a70-5ba8-4fa7-9139-7a53ea28a20f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055349470 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.1055349470
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1509953326
Short name T455
Test name
Test status
Simulation time 26461688751 ps
CPU time 100.93 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:24:13 PM PDT 24
Peak memory 190740 kb
Host smart-8934dcfd-b885-4242-8987-cd5a78c51b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509953326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1509953326
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1472113970
Short name T206
Test name
Test status
Simulation time 173329766608 ps
CPU time 97.41 seconds
Started Jun 11 12:22:31 PM PDT 24
Finished Jun 11 12:24:12 PM PDT 24
Peak memory 182396 kb
Host smart-294b964b-36d0-4d2a-aabc-412dcfd505ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472113970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1472113970
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3985860528
Short name T279
Test name
Test status
Simulation time 3826162800 ps
CPU time 30.68 seconds
Started Jun 11 12:21:22 PM PDT 24
Finished Jun 11 12:21:53 PM PDT 24
Peak memory 182828 kb
Host smart-84324d83-2f18-4af2-bc51-c97838ca34c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985860528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3985860528
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2152738868
Short name T228
Test name
Test status
Simulation time 1408919782886 ps
CPU time 478.94 seconds
Started Jun 11 12:22:30 PM PDT 24
Finished Jun 11 12:30:32 PM PDT 24
Peak memory 190616 kb
Host smart-20541f42-c5e2-467e-9ee4-5c9b97a3f4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152738868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2152738868
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2504162530
Short name T269
Test name
Test status
Simulation time 103973730318 ps
CPU time 322.72 seconds
Started Jun 11 12:21:22 PM PDT 24
Finished Jun 11 12:26:46 PM PDT 24
Peak memory 191020 kb
Host smart-fb4615c8-907c-4c15-92b6-d72bc4967856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504162530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2504162530
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.184722794
Short name T294
Test name
Test status
Simulation time 527401067329 ps
CPU time 128.09 seconds
Started Jun 11 12:21:33 PM PDT 24
Finished Jun 11 12:23:42 PM PDT 24
Peak memory 182832 kb
Host smart-809615e3-3893-4912-8e68-0bd4b2ac9af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184722794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.184722794
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.689774421
Short name T305
Test name
Test status
Simulation time 346454135682 ps
CPU time 323.16 seconds
Started Jun 11 12:23:21 PM PDT 24
Finished Jun 11 12:28:46 PM PDT 24
Peak memory 190880 kb
Host smart-769b925b-ab95-495d-9f1f-80b1209b9681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689774421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.689774421
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.528257612
Short name T295
Test name
Test status
Simulation time 542685385498 ps
CPU time 458.06 seconds
Started Jun 11 12:21:28 PM PDT 24
Finished Jun 11 12:29:07 PM PDT 24
Peak memory 194272 kb
Host smart-2e5970d7-4542-43b7-beec-07ee117cd7e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528257612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.528257612
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2560542104
Short name T53
Test name
Test status
Simulation time 41743327852 ps
CPU time 68.52 seconds
Started Jun 11 12:23:20 PM PDT 24
Finished Jun 11 12:24:31 PM PDT 24
Peak memory 182684 kb
Host smart-30084b6b-a534-4085-b347-751e33fd98bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560542104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2560542104
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3119475345
Short name T238
Test name
Test status
Simulation time 1528511995428 ps
CPU time 525.34 seconds
Started Jun 11 12:22:29 PM PDT 24
Finished Jun 11 12:31:18 PM PDT 24
Peak memory 181492 kb
Host smart-5e536186-a850-4d46-a849-0c51eb6c92d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119475345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3119475345
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1068599001
Short name T73
Test name
Test status
Simulation time 25256453020 ps
CPU time 36.77 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:24:08 PM PDT 24
Peak memory 181364 kb
Host smart-ba657377-60d7-4208-8253-05e72e9b3bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068599001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1068599001
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3902777232
Short name T266
Test name
Test status
Simulation time 135114433772 ps
CPU time 535.35 seconds
Started Jun 11 12:19:51 PM PDT 24
Finished Jun 11 12:28:48 PM PDT 24
Peak memory 181400 kb
Host smart-31acc8e5-612f-4d50-afd3-4dd4f3dd7961
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902777232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3902777232
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.589771816
Short name T391
Test name
Test status
Simulation time 563386870 ps
CPU time 0.85 seconds
Started Jun 11 12:22:28 PM PDT 24
Finished Jun 11 12:22:32 PM PDT 24
Peak memory 182352 kb
Host smart-ea554691-bc8a-42ef-a6e3-5dd8255aa240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589771816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.589771816
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.4145111499
Short name T190
Test name
Test status
Simulation time 682549181883 ps
CPU time 894.32 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:38:25 PM PDT 24
Peak memory 191044 kb
Host smart-9e7f0947-3946-409d-a2ce-b19e64d65a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145111499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4145111499
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.893097835
Short name T224
Test name
Test status
Simulation time 67884316813 ps
CPU time 232.79 seconds
Started Jun 11 12:23:10 PM PDT 24
Finished Jun 11 12:27:04 PM PDT 24
Peak memory 190216 kb
Host smart-c1598770-9113-4f3e-967b-281d65366eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893097835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.893097835
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1891965739
Short name T138
Test name
Test status
Simulation time 158268420490 ps
CPU time 598.85 seconds
Started Jun 11 12:23:26 PM PDT 24
Finished Jun 11 12:33:30 PM PDT 24
Peak memory 191052 kb
Host smart-e70235fe-da31-40e8-b580-dec1e3a4e783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891965739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1891965739
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4110838514
Short name T113
Test name
Test status
Simulation time 1096929813947 ps
CPU time 177.87 seconds
Started Jun 11 12:23:25 PM PDT 24
Finished Jun 11 12:26:26 PM PDT 24
Peak memory 190920 kb
Host smart-45b12d1c-bbb7-48f8-943d-4d7757345b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110838514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4110838514
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2347466087
Short name T146
Test name
Test status
Simulation time 323365366754 ps
CPU time 65.78 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:24:26 PM PDT 24
Peak memory 193280 kb
Host smart-8431981e-b5dd-434c-9089-1e9d52f5e7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347466087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2347466087
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4002891569
Short name T111
Test name
Test status
Simulation time 227785103536 ps
CPU time 236.75 seconds
Started Jun 11 12:21:28 PM PDT 24
Finished Jun 11 12:25:25 PM PDT 24
Peak memory 193616 kb
Host smart-17766980-2d65-4ae6-b970-2476a3c9926a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002891569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4002891569
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1109854504
Short name T167
Test name
Test status
Simulation time 35323785592 ps
CPU time 30.38 seconds
Started Jun 11 12:23:19 PM PDT 24
Finished Jun 11 12:23:51 PM PDT 24
Peak memory 182532 kb
Host smart-f643416d-5330-4a2e-aac1-924ce0ffc583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109854504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1109854504
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2358618146
Short name T342
Test name
Test status
Simulation time 50864988372 ps
CPU time 91.62 seconds
Started Jun 11 12:23:03 PM PDT 24
Finished Jun 11 12:24:38 PM PDT 24
Peak memory 182804 kb
Host smart-97e41d1c-8211-4393-ae9f-e0c3b2ea2377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358618146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2358618146
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3068935620
Short name T263
Test name
Test status
Simulation time 106819413313 ps
CPU time 166.2 seconds
Started Jun 11 12:22:32 PM PDT 24
Finished Jun 11 12:25:22 PM PDT 24
Peak memory 182612 kb
Host smart-7baac8b4-548a-4f57-8d1e-17b6a5665658
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068935620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3068935620
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3702065299
Short name T383
Test name
Test status
Simulation time 456665250574 ps
CPU time 169.24 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:25:51 PM PDT 24
Peak memory 182812 kb
Host smart-256f2dbf-8338-4243-8d7e-c654dbfc2008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702065299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3702065299
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.819368996
Short name T289
Test name
Test status
Simulation time 110485144309 ps
CPU time 104.66 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:24:46 PM PDT 24
Peak memory 191052 kb
Host smart-7d24bf8e-46a7-4115-8ae8-30c6c086a17b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819368996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.819368996
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.691745963
Short name T318
Test name
Test status
Simulation time 190031962822 ps
CPU time 112.58 seconds
Started Jun 11 12:22:59 PM PDT 24
Finished Jun 11 12:24:56 PM PDT 24
Peak memory 194296 kb
Host smart-01efb4f8-ea73-42be-998e-24feaf7fd4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691745963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.691745963
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.97985225
Short name T330
Test name
Test status
Simulation time 318905813070 ps
CPU time 280.31 seconds
Started Jun 11 12:23:03 PM PDT 24
Finished Jun 11 12:27:46 PM PDT 24
Peak memory 190788 kb
Host smart-6cf54d5c-efe6-44ac-91d0-024bbeef1283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97985225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.97985225
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3821801960
Short name T304
Test name
Test status
Simulation time 263774059239 ps
CPU time 714.69 seconds
Started Jun 11 12:22:47 PM PDT 24
Finished Jun 11 12:34:44 PM PDT 24
Peak memory 190232 kb
Host smart-9b246451-a6bb-4711-9563-4e51d2e67d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821801960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3821801960
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.893385724
Short name T359
Test name
Test status
Simulation time 989674288 ps
CPU time 2.07 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:03 PM PDT 24
Peak memory 182484 kb
Host smart-80732bff-7c4e-4b0f-8091-1e103a84f2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893385724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.893385724
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2260122885
Short name T227
Test name
Test status
Simulation time 120303387763 ps
CPU time 413.12 seconds
Started Jun 11 12:22:49 PM PDT 24
Finished Jun 11 12:29:45 PM PDT 24
Peak memory 190656 kb
Host smart-d2d8df67-31a3-4f26-9633-a00d52a95dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260122885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2260122885
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2881281381
Short name T354
Test name
Test status
Simulation time 25233014106 ps
CPU time 22.91 seconds
Started Jun 11 12:22:57 PM PDT 24
Finished Jun 11 12:23:23 PM PDT 24
Peak memory 182668 kb
Host smart-e9f324f0-bc10-4d3a-884c-08f52115425d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881281381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2881281381
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.867448185
Short name T335
Test name
Test status
Simulation time 120701252807 ps
CPU time 548.26 seconds
Started Jun 11 12:22:55 PM PDT 24
Finished Jun 11 12:32:07 PM PDT 24
Peak memory 190028 kb
Host smart-d3a1d6d1-8b1c-4c5e-ac9d-708d1807f2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867448185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.867448185
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1723326526
Short name T274
Test name
Test status
Simulation time 2464891816657 ps
CPU time 576.63 seconds
Started Jun 11 12:23:03 PM PDT 24
Finished Jun 11 12:32:43 PM PDT 24
Peak memory 190796 kb
Host smart-2d69f91a-8af8-4f5b-8c34-9d9a44ae4b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723326526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1723326526
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3559282701
Short name T258
Test name
Test status
Simulation time 435383511050 ps
CPU time 130.66 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:25:50 PM PDT 24
Peak memory 194280 kb
Host smart-1caec3dc-e720-4fba-bd5f-6fcf25aee2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559282701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3559282701
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3274062847
Short name T7
Test name
Test status
Simulation time 337146908566 ps
CPU time 625.64 seconds
Started Jun 11 12:23:18 PM PDT 24
Finished Jun 11 12:33:45 PM PDT 24
Peak memory 182812 kb
Host smart-f707c283-a0d3-40cc-b9ba-b320ae3f039f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274062847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3274062847
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1530789030
Short name T397
Test name
Test status
Simulation time 144099976043 ps
CPU time 202.61 seconds
Started Jun 11 12:20:54 PM PDT 24
Finished Jun 11 12:24:18 PM PDT 24
Peak memory 183240 kb
Host smart-7f630899-986d-4a9f-978c-ddfdcd69c253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530789030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1530789030
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2405551897
Short name T372
Test name
Test status
Simulation time 58833681488 ps
CPU time 444.51 seconds
Started Jun 11 12:23:07 PM PDT 24
Finished Jun 11 12:30:33 PM PDT 24
Peak memory 190876 kb
Host smart-952b67d6-0999-4a7e-a1b3-e5eb5442d313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405551897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2405551897
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1731692800
Short name T377
Test name
Test status
Simulation time 27666724 ps
CPU time 0.6 seconds
Started Jun 11 12:22:10 PM PDT 24
Finished Jun 11 12:22:13 PM PDT 24
Peak memory 180964 kb
Host smart-0505b174-dd96-45c4-8ea2-d31b4c53ac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731692800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1731692800
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2621383534
Short name T301
Test name
Test status
Simulation time 41836926728 ps
CPU time 150.34 seconds
Started Jun 11 12:21:47 PM PDT 24
Finished Jun 11 12:24:19 PM PDT 24
Peak memory 182836 kb
Host smart-3a7ec54a-c1ad-4b01-839f-4382d925f506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621383534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2621383534
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2439596591
Short name T313
Test name
Test status
Simulation time 118319907046 ps
CPU time 55.75 seconds
Started Jun 11 12:21:48 PM PDT 24
Finished Jun 11 12:22:44 PM PDT 24
Peak memory 182876 kb
Host smart-98308787-452a-4c7b-8668-df105eaea0b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439596591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2439596591
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2615642260
Short name T112
Test name
Test status
Simulation time 114920483520 ps
CPU time 659.38 seconds
Started Jun 11 12:21:58 PM PDT 24
Finished Jun 11 12:32:58 PM PDT 24
Peak memory 191120 kb
Host smart-2dae710e-1c66-4326-bff4-fa95da7464c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615642260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2615642260
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3431224203
Short name T223
Test name
Test status
Simulation time 32876585201 ps
CPU time 50.71 seconds
Started Jun 11 12:22:02 PM PDT 24
Finished Jun 11 12:22:53 PM PDT 24
Peak memory 183244 kb
Host smart-9739348b-978e-4bd2-bf5a-69492a3a431f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431224203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3431224203
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.359027213
Short name T352
Test name
Test status
Simulation time 178806042455 ps
CPU time 407.73 seconds
Started Jun 11 12:23:35 PM PDT 24
Finished Jun 11 12:30:27 PM PDT 24
Peak memory 194152 kb
Host smart-8240f478-802a-467d-9d94-b0812740aad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359027213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.359027213
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1456607275
Short name T116
Test name
Test status
Simulation time 225604100529 ps
CPU time 164.44 seconds
Started Jun 11 12:23:34 PM PDT 24
Finished Jun 11 12:26:23 PM PDT 24
Peak memory 190712 kb
Host smart-a4991064-48e1-4089-ba62-472248852607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456607275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1456607275
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2671132941
Short name T226
Test name
Test status
Simulation time 484005370238 ps
CPU time 504.63 seconds
Started Jun 11 12:22:09 PM PDT 24
Finished Jun 11 12:30:36 PM PDT 24
Peak memory 191112 kb
Host smart-c2d47ce5-6db3-437c-a67b-de037215652e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671132941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2671132941
Directory /workspace/98.rv_timer_random/latest
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