Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2258626113 Jun 13 12:49:04 PM PDT 24 Jun 13 12:49:06 PM PDT 24 207010436 ps
T510 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3842646593 Jun 13 12:49:32 PM PDT 24 Jun 13 12:49:34 PM PDT 24 13241646 ps
T511 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1252881627 Jun 13 12:49:07 PM PDT 24 Jun 13 12:49:08 PM PDT 24 35161005 ps
T512 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1758519846 Jun 13 12:49:37 PM PDT 24 Jun 13 12:49:39 PM PDT 24 10769766 ps
T98 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3361139277 Jun 13 12:49:25 PM PDT 24 Jun 13 12:49:27 PM PDT 24 351101264 ps
T513 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2305163607 Jun 13 12:49:39 PM PDT 24 Jun 13 12:49:41 PM PDT 24 11926932 ps
T514 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.458974620 Jun 13 12:49:40 PM PDT 24 Jun 13 12:49:42 PM PDT 24 116542561 ps
T515 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.937336316 Jun 13 12:49:05 PM PDT 24 Jun 13 12:49:06 PM PDT 24 34705796 ps
T516 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.598772564 Jun 13 12:49:14 PM PDT 24 Jun 13 12:49:15 PM PDT 24 87452910 ps
T517 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1870840684 Jun 13 12:49:33 PM PDT 24 Jun 13 12:49:35 PM PDT 24 14013607 ps
T518 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.707594314 Jun 13 12:49:05 PM PDT 24 Jun 13 12:49:06 PM PDT 24 30114445 ps
T519 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1967634550 Jun 13 12:49:41 PM PDT 24 Jun 13 12:49:43 PM PDT 24 26455917 ps
T520 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3986029865 Jun 13 12:49:25 PM PDT 24 Jun 13 12:49:26 PM PDT 24 51369158 ps
T521 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1999532866 Jun 13 12:49:40 PM PDT 24 Jun 13 12:49:43 PM PDT 24 21949592 ps
T522 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2287503001 Jun 13 12:49:23 PM PDT 24 Jun 13 12:49:24 PM PDT 24 46228308 ps
T523 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.727286309 Jun 13 12:49:07 PM PDT 24 Jun 13 12:49:10 PM PDT 24 561238914 ps
T524 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.843747782 Jun 13 12:49:04 PM PDT 24 Jun 13 12:49:06 PM PDT 24 28952764 ps
T525 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2025113686 Jun 13 12:48:59 PM PDT 24 Jun 13 12:49:01 PM PDT 24 148306266 ps
T526 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3799061364 Jun 13 12:49:41 PM PDT 24 Jun 13 12:49:43 PM PDT 24 16019426 ps
T527 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.723492614 Jun 13 12:49:14 PM PDT 24 Jun 13 12:49:16 PM PDT 24 33746894 ps
T528 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3110776406 Jun 13 12:49:07 PM PDT 24 Jun 13 12:49:08 PM PDT 24 14068952 ps
T529 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2290655388 Jun 13 12:48:58 PM PDT 24 Jun 13 12:48:59 PM PDT 24 37373681 ps
T530 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1040598346 Jun 13 12:49:25 PM PDT 24 Jun 13 12:49:26 PM PDT 24 139547724 ps
T531 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2148714367 Jun 13 12:49:32 PM PDT 24 Jun 13 12:49:35 PM PDT 24 100767376 ps
T532 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1985098007 Jun 13 12:49:30 PM PDT 24 Jun 13 12:49:32 PM PDT 24 146858990 ps
T533 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.595858735 Jun 13 12:48:52 PM PDT 24 Jun 13 12:48:54 PM PDT 24 145615503 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2302115570 Jun 13 12:49:19 PM PDT 24 Jun 13 12:49:20 PM PDT 24 19440008 ps
T535 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1806326862 Jun 13 12:48:58 PM PDT 24 Jun 13 12:49:01 PM PDT 24 783778401 ps
T536 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.986487384 Jun 13 12:48:58 PM PDT 24 Jun 13 12:48:59 PM PDT 24 83004121 ps
T537 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3782635297 Jun 13 12:49:07 PM PDT 24 Jun 13 12:49:09 PM PDT 24 25525675 ps
T538 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4077270522 Jun 13 12:49:41 PM PDT 24 Jun 13 12:49:43 PM PDT 24 45738190 ps
T99 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1278669031 Jun 13 12:49:13 PM PDT 24 Jun 13 12:49:14 PM PDT 24 66519334 ps
T539 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1858169155 Jun 13 12:49:12 PM PDT 24 Jun 13 12:49:13 PM PDT 24 133295940 ps
T540 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3211715058 Jun 13 12:49:38 PM PDT 24 Jun 13 12:49:39 PM PDT 24 16797251 ps
T541 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1939762687 Jun 13 12:49:27 PM PDT 24 Jun 13 12:49:29 PM PDT 24 41901365 ps
T542 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.250456029 Jun 13 12:49:40 PM PDT 24 Jun 13 12:49:42 PM PDT 24 217708721 ps
T543 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1734782449 Jun 13 12:49:00 PM PDT 24 Jun 13 12:49:01 PM PDT 24 18896691 ps
T544 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2037320565 Jun 13 12:49:19 PM PDT 24 Jun 13 12:49:21 PM PDT 24 65875997 ps
T545 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.980587818 Jun 13 12:48:59 PM PDT 24 Jun 13 12:49:00 PM PDT 24 58395188 ps
T546 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.421098652 Jun 13 12:49:31 PM PDT 24 Jun 13 12:49:33 PM PDT 24 24348864 ps
T547 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2139713912 Jun 13 12:49:16 PM PDT 24 Jun 13 12:49:17 PM PDT 24 44898812 ps
T548 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.303245127 Jun 13 12:49:20 PM PDT 24 Jun 13 12:49:21 PM PDT 24 38771149 ps
T549 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.647279986 Jun 13 12:49:32 PM PDT 24 Jun 13 12:49:34 PM PDT 24 18984943 ps
T81 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1016294478 Jun 13 12:49:00 PM PDT 24 Jun 13 12:49:01 PM PDT 24 221560038 ps
T550 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1201324181 Jun 13 12:49:05 PM PDT 24 Jun 13 12:49:07 PM PDT 24 19493581 ps
T551 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1956962383 Jun 13 12:48:58 PM PDT 24 Jun 13 12:49:00 PM PDT 24 54154464 ps
T552 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2300590999 Jun 13 12:49:07 PM PDT 24 Jun 13 12:49:09 PM PDT 24 37906478 ps
T553 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.807609507 Jun 13 12:48:58 PM PDT 24 Jun 13 12:49:01 PM PDT 24 34634164 ps
T554 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.105755874 Jun 13 12:49:40 PM PDT 24 Jun 13 12:49:43 PM PDT 24 13916832 ps
T555 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3834113728 Jun 13 12:49:40 PM PDT 24 Jun 13 12:49:42 PM PDT 24 25873573 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3771039055 Jun 13 12:48:58 PM PDT 24 Jun 13 12:48:59 PM PDT 24 31266844 ps
T82 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2893955402 Jun 13 12:49:28 PM PDT 24 Jun 13 12:49:29 PM PDT 24 17131891 ps
T557 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.947612507 Jun 13 12:49:06 PM PDT 24 Jun 13 12:49:09 PM PDT 24 136182445 ps
T558 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2821034905 Jun 13 12:49:11 PM PDT 24 Jun 13 12:49:12 PM PDT 24 22383933 ps
T559 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2418556896 Jun 13 12:49:14 PM PDT 24 Jun 13 12:49:16 PM PDT 24 113994798 ps
T560 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.627417708 Jun 13 12:49:11 PM PDT 24 Jun 13 12:49:13 PM PDT 24 37312600 ps
T561 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3467777231 Jun 13 12:49:14 PM PDT 24 Jun 13 12:49:16 PM PDT 24 87245498 ps
T562 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3900386437 Jun 13 12:49:35 PM PDT 24 Jun 13 12:49:37 PM PDT 24 345697034 ps
T563 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2889718668 Jun 13 12:49:39 PM PDT 24 Jun 13 12:49:41 PM PDT 24 13384000 ps
T564 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.689567845 Jun 13 12:49:32 PM PDT 24 Jun 13 12:49:35 PM PDT 24 47788245 ps
T565 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2684224228 Jun 13 12:48:58 PM PDT 24 Jun 13 12:49:00 PM PDT 24 133905610 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2086199338 Jun 13 12:48:58 PM PDT 24 Jun 13 12:49:00 PM PDT 24 91722232 ps
T567 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1817820237 Jun 13 12:49:26 PM PDT 24 Jun 13 12:49:28 PM PDT 24 30017950 ps
T83 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2104681435 Jun 13 12:49:32 PM PDT 24 Jun 13 12:49:33 PM PDT 24 84987274 ps
T568 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.792163927 Jun 13 12:49:27 PM PDT 24 Jun 13 12:49:29 PM PDT 24 86198660 ps
T85 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1549306900 Jun 13 12:49:17 PM PDT 24 Jun 13 12:49:18 PM PDT 24 17414960 ps
T569 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4012176691 Jun 13 12:49:26 PM PDT 24 Jun 13 12:49:27 PM PDT 24 510854176 ps
T570 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1884994147 Jun 13 12:49:24 PM PDT 24 Jun 13 12:49:27 PM PDT 24 212641624 ps
T571 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1617326191 Jun 13 12:49:45 PM PDT 24 Jun 13 12:49:47 PM PDT 24 20875094 ps
T84 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2705871512 Jun 13 12:49:15 PM PDT 24 Jun 13 12:49:16 PM PDT 24 41971930 ps
T572 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1633363216 Jun 13 12:49:40 PM PDT 24 Jun 13 12:49:43 PM PDT 24 45833215 ps
T573 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2410887025 Jun 13 12:49:07 PM PDT 24 Jun 13 12:49:10 PM PDT 24 348928812 ps
T574 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1112645873 Jun 13 12:49:38 PM PDT 24 Jun 13 12:49:40 PM PDT 24 33832950 ps
T575 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1070603758 Jun 13 12:49:27 PM PDT 24 Jun 13 12:49:30 PM PDT 24 87195705 ps
T576 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.506076337 Jun 13 12:49:37 PM PDT 24 Jun 13 12:49:38 PM PDT 24 14527322 ps
T577 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1853460802 Jun 13 12:49:45 PM PDT 24 Jun 13 12:49:47 PM PDT 24 18321930 ps
T578 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3064014400 Jun 13 12:49:05 PM PDT 24 Jun 13 12:49:06 PM PDT 24 82478325 ps
T579 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.318117420 Jun 13 12:48:52 PM PDT 24 Jun 13 12:48:54 PM PDT 24 279859920 ps
T580 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3210770857 Jun 13 12:49:04 PM PDT 24 Jun 13 12:49:05 PM PDT 24 21138128 ps
T581 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2406276721 Jun 13 12:49:13 PM PDT 24 Jun 13 12:49:14 PM PDT 24 127344380 ps
T86 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1470128644 Jun 13 12:49:04 PM PDT 24 Jun 13 12:49:05 PM PDT 24 39529090 ps

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2379977926
Short name T4
Test name
Test status
Simulation time 11462590080 ps
CPU time 120.62 seconds
Started Jun 13 12:51:45 PM PDT 24
Finished Jun 13 12:53:46 PM PDT 24
Peak memory 196812 kb
Host smart-136df82c-29f5-405f-bd3e-a20c48bf2899
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379977926 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2379977926
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/115.rv_timer_random.558126519
Short name T43
Test name
Test status
Simulation time 68351355451 ps
CPU time 368.4 seconds
Started Jun 13 12:53:34 PM PDT 24
Finished Jun 13 12:59:43 PM PDT 24
Peak memory 191176 kb
Host smart-b0df716f-43e4-4242-a890-f9a7af74aeb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558126519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.558126519
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.501251989
Short name T34
Test name
Test status
Simulation time 1094607803308 ps
CPU time 1058.58 seconds
Started Jun 13 12:50:03 PM PDT 24
Finished Jun 13 01:07:45 PM PDT 24
Peak memory 191156 kb
Host smart-4d4c2578-faa3-4d23-8420-0d71e6e03f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501251989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
501251989
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.4135552480
Short name T151
Test name
Test status
Simulation time 4389637824424 ps
CPU time 4138.18 seconds
Started Jun 13 12:50:24 PM PDT 24
Finished Jun 13 01:59:24 PM PDT 24
Peak memory 191172 kb
Host smart-74a3f492-46e3-41eb-9705-974df7d79d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135552480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.4135552480
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3650903720
Short name T27
Test name
Test status
Simulation time 251234936 ps
CPU time 0.79 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 193396 kb
Host smart-00866bd2-35e0-407a-809f-3f496022de33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650903720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3650903720
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1183448732
Short name T109
Test name
Test status
Simulation time 1488003278989 ps
CPU time 1514.68 seconds
Started Jun 13 12:50:04 PM PDT 24
Finished Jun 13 01:15:22 PM PDT 24
Peak memory 191120 kb
Host smart-ac82a72f-d29a-43d5-a9ea-21dfbbbd42a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183448732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1183448732
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3206389617
Short name T103
Test name
Test status
Simulation time 482198258959 ps
CPU time 2201.86 seconds
Started Jun 13 12:49:44 PM PDT 24
Finished Jun 13 01:26:27 PM PDT 24
Peak memory 191160 kb
Host smart-11006c2d-587b-41e5-bf93-09099cc1470d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206389617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3206389617
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1190836131
Short name T47
Test name
Test status
Simulation time 39766740 ps
CPU time 0.58 seconds
Started Jun 13 12:49:06 PM PDT 24
Finished Jun 13 12:49:07 PM PDT 24
Peak memory 182588 kb
Host smart-ac4698ad-2420-42ba-aff9-0d6566b10ce8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190836131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1190836131
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.413903229
Short name T210
Test name
Test status
Simulation time 1988292095698 ps
CPU time 1969.88 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 01:22:52 PM PDT 24
Peak memory 195112 kb
Host smart-5710380e-f954-4328-b13c-ebcb67c7195c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413903229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.413903229
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4049685343
Short name T149
Test name
Test status
Simulation time 698262287620 ps
CPU time 4163.82 seconds
Started Jun 13 12:51:25 PM PDT 24
Finished Jun 13 02:00:50 PM PDT 24
Peak memory 191276 kb
Host smart-e79de118-72ee-4661-9453-7adc35511974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049685343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4049685343
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1539146236
Short name T9
Test name
Test status
Simulation time 69409128986 ps
CPU time 115.42 seconds
Started Jun 13 12:49:41 PM PDT 24
Finished Jun 13 12:51:38 PM PDT 24
Peak memory 182960 kb
Host smart-62a3d00a-452e-48dc-90a6-20090b2427ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539146236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1539146236
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3919664085
Short name T190
Test name
Test status
Simulation time 488031447143 ps
CPU time 4702.94 seconds
Started Jun 13 12:52:26 PM PDT 24
Finished Jun 13 02:10:50 PM PDT 24
Peak memory 191064 kb
Host smart-a33832e1-eb45-4299-bea3-5b6a87e672b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919664085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3919664085
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3039194941
Short name T100
Test name
Test status
Simulation time 281308723301 ps
CPU time 2084.95 seconds
Started Jun 13 12:51:59 PM PDT 24
Finished Jun 13 01:26:45 PM PDT 24
Peak memory 191068 kb
Host smart-6979fdbb-fe9a-46e9-ab22-b65c67719061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039194941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3039194941
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3938423243
Short name T298
Test name
Test status
Simulation time 2697795359444 ps
CPU time 2137.27 seconds
Started Jun 13 12:51:46 PM PDT 24
Finished Jun 13 01:27:24 PM PDT 24
Peak memory 191028 kb
Host smart-bb4e79b4-dee6-423b-a1a4-bc179da7fcbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938423243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3938423243
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.578130860
Short name T15
Test name
Test status
Simulation time 57036564 ps
CPU time 0.86 seconds
Started Jun 13 12:49:46 PM PDT 24
Finished Jun 13 12:49:48 PM PDT 24
Peak memory 213260 kb
Host smart-d69368b5-8d80-4e12-8b52-2b0a664dc632
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578130860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.578130860
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2668681176
Short name T33
Test name
Test status
Simulation time 372766019330 ps
CPU time 847.2 seconds
Started Jun 13 12:52:09 PM PDT 24
Finished Jun 13 01:06:18 PM PDT 24
Peak memory 191168 kb
Host smart-7d9466c7-752f-47fa-a943-4582d40751a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668681176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2668681176
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/194.rv_timer_random.2266821123
Short name T94
Test name
Test status
Simulation time 436605047141 ps
CPU time 215.08 seconds
Started Jun 13 12:54:49 PM PDT 24
Finished Jun 13 12:58:25 PM PDT 24
Peak memory 194620 kb
Host smart-22fee1a0-7a31-4952-a1cf-f207e85f2491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266821123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2266821123
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.701388835
Short name T245
Test name
Test status
Simulation time 214432137579 ps
CPU time 1350.74 seconds
Started Jun 13 12:49:41 PM PDT 24
Finished Jun 13 01:12:14 PM PDT 24
Peak memory 191156 kb
Host smart-1b8f24d8-7089-44ff-904e-a7101c9ec130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701388835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.701388835
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.445135049
Short name T250
Test name
Test status
Simulation time 1127956124172 ps
CPU time 2338.89 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 01:29:23 PM PDT 24
Peak memory 195664 kb
Host smart-cae463dd-03b1-4b5a-a075-44876c23c7f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445135049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
445135049
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.4221849060
Short name T240
Test name
Test status
Simulation time 526050729540 ps
CPU time 226.09 seconds
Started Jun 13 12:51:47 PM PDT 24
Finished Jun 13 12:55:34 PM PDT 24
Peak memory 191160 kb
Host smart-e912ec96-c37a-4fc8-95ff-3a891d19cb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221849060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4221849060
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3491231456
Short name T205
Test name
Test status
Simulation time 320301705023 ps
CPU time 1766.81 seconds
Started Jun 13 12:50:00 PM PDT 24
Finished Jun 13 01:19:30 PM PDT 24
Peak memory 196760 kb
Host smart-81826729-b905-476a-9a21-9b84c87ba0cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491231456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3491231456
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random.4233495152
Short name T248
Test name
Test status
Simulation time 765079368469 ps
CPU time 717.64 seconds
Started Jun 13 12:49:44 PM PDT 24
Finished Jun 13 01:01:42 PM PDT 24
Peak memory 191140 kb
Host smart-e340f19c-e56b-49ea-84b0-517ffdc1d8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233495152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.4233495152
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2755640627
Short name T22
Test name
Test status
Simulation time 166388217786 ps
CPU time 321.46 seconds
Started Jun 13 12:54:22 PM PDT 24
Finished Jun 13 12:59:44 PM PDT 24
Peak memory 191156 kb
Host smart-2ff25b10-c3c0-4676-8911-683d0754f6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755640627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2755640627
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2955969232
Short name T59
Test name
Test status
Simulation time 182859627387 ps
CPU time 691.96 seconds
Started Jun 13 12:53:27 PM PDT 24
Finished Jun 13 01:04:59 PM PDT 24
Peak memory 191172 kb
Host smart-3021d02a-fba3-4eee-bea3-c5904a00c1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955969232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2955969232
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4269441977
Short name T266
Test name
Test status
Simulation time 247505084892 ps
CPU time 195.48 seconds
Started Jun 13 12:53:54 PM PDT 24
Finished Jun 13 12:57:10 PM PDT 24
Peak memory 191124 kb
Host smart-9b3149aa-a8b5-425e-a1e4-2cf9cf55e6b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269441977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4269441977
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.715648928
Short name T352
Test name
Test status
Simulation time 2324195858241 ps
CPU time 1552.11 seconds
Started Jun 13 12:53:59 PM PDT 24
Finished Jun 13 01:19:51 PM PDT 24
Peak memory 193636 kb
Host smart-019f443d-4932-46c8-983f-72a9bd76a8ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715648928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.715648928
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.428992914
Short name T63
Test name
Test status
Simulation time 331442387259 ps
CPU time 786.94 seconds
Started Jun 13 12:51:41 PM PDT 24
Finished Jun 13 01:04:48 PM PDT 24
Peak memory 191184 kb
Host smart-438f6a27-802a-441d-a09d-0c38c33f7918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428992914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
428992914
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3429971461
Short name T225
Test name
Test status
Simulation time 458520923412 ps
CPU time 2340.73 seconds
Started Jun 13 12:52:21 PM PDT 24
Finished Jun 13 01:31:23 PM PDT 24
Peak memory 191112 kb
Host smart-8b62f43b-7f92-4b94-b0ba-2e84711c567d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429971461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3429971461
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.1849538664
Short name T236
Test name
Test status
Simulation time 52715015289 ps
CPU time 143.07 seconds
Started Jun 13 12:53:39 PM PDT 24
Finished Jun 13 12:56:03 PM PDT 24
Peak memory 191144 kb
Host smart-65c51efe-5cb8-41ab-8248-9f07974ff401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849538664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1849538664
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3524306563
Short name T342
Test name
Test status
Simulation time 159270678162 ps
CPU time 1027.22 seconds
Started Jun 13 12:54:28 PM PDT 24
Finished Jun 13 01:11:36 PM PDT 24
Peak memory 191164 kb
Host smart-15a3816d-f80a-493f-bb4c-8f1c4aa8278b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524306563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3524306563
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.856738595
Short name T132
Test name
Test status
Simulation time 500701752063 ps
CPU time 298.84 seconds
Started Jun 13 12:53:11 PM PDT 24
Finished Jun 13 12:58:11 PM PDT 24
Peak memory 191152 kb
Host smart-aeb8e8bb-a573-4737-99b3-cbc01b288219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856738595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.856738595
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2961376083
Short name T116
Test name
Test status
Simulation time 266721011392 ps
CPU time 266.27 seconds
Started Jun 13 12:53:19 PM PDT 24
Finished Jun 13 12:57:46 PM PDT 24
Peak memory 191156 kb
Host smart-d759ead7-7add-465a-bb29-a9c8e2fcd7ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961376083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2961376083
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2332282240
Short name T78
Test name
Test status
Simulation time 13629080 ps
CPU time 0.62 seconds
Started Jun 13 12:49:18 PM PDT 24
Finished Jun 13 12:49:19 PM PDT 24
Peak memory 182616 kb
Host smart-03a9b40e-833c-41d9-9aaa-31ec94954307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332282240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2332282240
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/111.rv_timer_random.2032562135
Short name T420
Test name
Test status
Simulation time 87051230496 ps
CPU time 127.57 seconds
Started Jun 13 12:53:28 PM PDT 24
Finished Jun 13 12:55:36 PM PDT 24
Peak memory 191024 kb
Host smart-b165c40f-7b29-43fa-8d80-7acb9d21b0cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032562135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2032562135
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4125053013
Short name T155
Test name
Test status
Simulation time 1764184475259 ps
CPU time 749.19 seconds
Started Jun 13 12:54:24 PM PDT 24
Finished Jun 13 01:06:54 PM PDT 24
Peak memory 191164 kb
Host smart-dbb367a3-0eab-4c04-b5bc-9ae6c3de1aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125053013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4125053013
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.609684199
Short name T170
Test name
Test status
Simulation time 129290556165 ps
CPU time 395.02 seconds
Started Jun 13 12:50:08 PM PDT 24
Finished Jun 13 12:56:45 PM PDT 24
Peak memory 191140 kb
Host smart-8f2b14e3-51d3-4f9c-93e2-c10bfcedf5cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609684199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.609684199
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1340978429
Short name T360
Test name
Test status
Simulation time 278584230467 ps
CPU time 439.42 seconds
Started Jun 13 12:52:58 PM PDT 24
Finished Jun 13 01:00:18 PM PDT 24
Peak memory 191160 kb
Host smart-0fdf3e9d-01a6-4b60-9c7e-0a86eb345ed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340978429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1340978429
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.588696274
Short name T135
Test name
Test status
Simulation time 143477020361 ps
CPU time 428.81 seconds
Started Jun 13 12:53:19 PM PDT 24
Finished Jun 13 01:00:28 PM PDT 24
Peak memory 191176 kb
Host smart-b66cf913-81ec-4012-a72a-82b3ec0b4935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588696274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.588696274
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.2608840278
Short name T283
Test name
Test status
Simulation time 155526748082 ps
CPU time 282.69 seconds
Started Jun 13 12:50:00 PM PDT 24
Finished Jun 13 12:54:46 PM PDT 24
Peak memory 191036 kb
Host smart-bebb1e12-d024-45b4-9d9c-79e20cc2d857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608840278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2608840278
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.544540471
Short name T252
Test name
Test status
Simulation time 112565448217 ps
CPU time 95.05 seconds
Started Jun 13 12:53:33 PM PDT 24
Finished Jun 13 12:55:09 PM PDT 24
Peak memory 193852 kb
Host smart-1b50ff80-b033-4f7a-b01b-6b99b7b1206e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544540471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.544540471
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2688246035
Short name T188
Test name
Test status
Simulation time 336053715113 ps
CPU time 889.46 seconds
Started Jun 13 12:53:53 PM PDT 24
Finished Jun 13 01:08:44 PM PDT 24
Peak memory 191148 kb
Host smart-f5beb089-1772-4c8c-a681-ea342987dee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688246035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2688246035
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2160715258
Short name T169
Test name
Test status
Simulation time 130570928685 ps
CPU time 411.34 seconds
Started Jun 13 12:54:01 PM PDT 24
Finished Jun 13 01:00:53 PM PDT 24
Peak memory 194352 kb
Host smart-67affb05-1269-4237-8552-958dbc00838f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160715258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2160715258
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.2035371710
Short name T447
Test name
Test status
Simulation time 95005937540 ps
CPU time 461.16 seconds
Started Jun 13 12:50:29 PM PDT 24
Finished Jun 13 12:58:12 PM PDT 24
Peak memory 191196 kb
Host smart-dd89d910-9be6-4802-843a-34ceb11793c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035371710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2035371710
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.506846735
Short name T260
Test name
Test status
Simulation time 299003855227 ps
CPU time 498.53 seconds
Started Jun 13 12:51:15 PM PDT 24
Finished Jun 13 12:59:34 PM PDT 24
Peak memory 182944 kb
Host smart-3741512e-fc80-448c-9629-85968b55c0d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506846735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.506846735
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.3005493368
Short name T241
Test name
Test status
Simulation time 554219245396 ps
CPU time 1477.97 seconds
Started Jun 13 12:51:25 PM PDT 24
Finished Jun 13 01:16:03 PM PDT 24
Peak memory 193204 kb
Host smart-f9893484-43af-4a03-8b2b-c1afd4c9fc98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005493368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3005493368
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2879133585
Short name T186
Test name
Test status
Simulation time 70740553818 ps
CPU time 222.19 seconds
Started Jun 13 12:52:43 PM PDT 24
Finished Jun 13 12:56:26 PM PDT 24
Peak memory 191156 kb
Host smart-44c135da-b5d9-46ba-8765-5f1ac31c9f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879133585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2879133585
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3894016023
Short name T106
Test name
Test status
Simulation time 121420189703 ps
CPU time 461.01 seconds
Started Jun 13 12:53:45 PM PDT 24
Finished Jun 13 01:01:27 PM PDT 24
Peak memory 192936 kb
Host smart-e2f3c6a5-7b5c-43ac-a255-ef118bd8d14b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894016023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3894016023
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3077060924
Short name T208
Test name
Test status
Simulation time 386247331279 ps
CPU time 529.21 seconds
Started Jun 13 12:53:53 PM PDT 24
Finished Jun 13 01:02:43 PM PDT 24
Peak memory 191168 kb
Host smart-542a95cd-2640-4868-9560-5518134dc41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077060924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3077060924
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4212749648
Short name T291
Test name
Test status
Simulation time 1737930422305 ps
CPU time 992.45 seconds
Started Jun 13 12:50:10 PM PDT 24
Finished Jun 13 01:06:44 PM PDT 24
Peak memory 195456 kb
Host smart-2761a542-3eb3-42dd-9fd2-864e77ccd7e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212749648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4212749648
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.116188675
Short name T278
Test name
Test status
Simulation time 783965513176 ps
CPU time 767.56 seconds
Started Jun 13 12:50:11 PM PDT 24
Finished Jun 13 01:03:01 PM PDT 24
Peak memory 182948 kb
Host smart-24b41679-ab21-493b-a33a-02f0a4e89588
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116188675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.116188675
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3398970532
Short name T176
Test name
Test status
Simulation time 1609280175895 ps
CPU time 1312.01 seconds
Started Jun 13 12:50:32 PM PDT 24
Finished Jun 13 01:12:26 PM PDT 24
Peak memory 182904 kb
Host smart-c2e7bf38-73d2-4cfb-a979-f20684e92ffd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398970532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3398970532
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.414153693
Short name T123
Test name
Test status
Simulation time 384814227592 ps
CPU time 88.86 seconds
Started Jun 13 12:50:40 PM PDT 24
Finished Jun 13 12:52:09 PM PDT 24
Peak memory 182960 kb
Host smart-a50c7720-1ba9-4325-bdd7-5df591f42611
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414153693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.414153693
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2894171360
Short name T162
Test name
Test status
Simulation time 331569779213 ps
CPU time 2201.99 seconds
Started Jun 13 12:50:55 PM PDT 24
Finished Jun 13 01:27:37 PM PDT 24
Peak memory 191116 kb
Host smart-9f472c80-2361-47f0-a6ab-cf8ca677a7b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894171360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2894171360
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1925095392
Short name T319
Test name
Test status
Simulation time 46282482030 ps
CPU time 42.11 seconds
Started Jun 13 12:51:39 PM PDT 24
Finished Jun 13 12:52:22 PM PDT 24
Peak memory 193852 kb
Host smart-62544492-d177-425d-b46c-f8cabebf82e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925095392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1925095392
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_random.3649338116
Short name T306
Test name
Test status
Simulation time 310515374430 ps
CPU time 263.13 seconds
Started Jun 13 12:49:52 PM PDT 24
Finished Jun 13 12:54:18 PM PDT 24
Peak memory 194548 kb
Host smart-d5fa88ef-9c28-4041-9229-1603401b0371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649338116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3649338116
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.81139923
Short name T97
Test name
Test status
Simulation time 113810084 ps
CPU time 1.33 seconds
Started Jun 13 12:49:28 PM PDT 24
Finished Jun 13 12:49:30 PM PDT 24
Peak memory 195164 kb
Host smart-5714651d-3442-4c8a-9ce0-1f4740df9445
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81139923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_int
g_err.81139923
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/106.rv_timer_random.3298867893
Short name T111
Test name
Test status
Simulation time 195568158703 ps
CPU time 315.53 seconds
Started Jun 13 12:53:28 PM PDT 24
Finished Jun 13 12:58:44 PM PDT 24
Peak memory 191144 kb
Host smart-ed303330-0feb-4fbc-8043-07ad843ffcc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298867893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3298867893
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.695679529
Short name T3
Test name
Test status
Simulation time 112335966396 ps
CPU time 1447.45 seconds
Started Jun 13 12:53:26 PM PDT 24
Finished Jun 13 01:17:35 PM PDT 24
Peak memory 191072 kb
Host smart-24dbf055-2c24-4df6-99a7-97b6e4e4a95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695679529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.695679529
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2555421824
Short name T194
Test name
Test status
Simulation time 93579561947 ps
CPU time 231.1 seconds
Started Jun 13 12:53:54 PM PDT 24
Finished Jun 13 12:57:46 PM PDT 24
Peak memory 191036 kb
Host smart-6161d403-11c0-43d7-88e5-d75e2c9c4ec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555421824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2555421824
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2184945817
Short name T216
Test name
Test status
Simulation time 1131049272629 ps
CPU time 516.93 seconds
Started Jun 13 12:50:09 PM PDT 24
Finished Jun 13 12:58:48 PM PDT 24
Peak memory 182964 kb
Host smart-22c505ce-25b3-4b32-8524-cc670412aa12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184945817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2184945817
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/156.rv_timer_random.1281687923
Short name T203
Test name
Test status
Simulation time 877366593345 ps
CPU time 242.16 seconds
Started Jun 13 12:54:00 PM PDT 24
Finished Jun 13 12:58:03 PM PDT 24
Peak memory 191020 kb
Host smart-5a9f7192-d244-42ce-b301-1d82c7583330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281687923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1281687923
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3026426687
Short name T269
Test name
Test status
Simulation time 1042791529677 ps
CPU time 287.35 seconds
Started Jun 13 12:50:12 PM PDT 24
Finished Jun 13 12:55:01 PM PDT 24
Peak memory 182104 kb
Host smart-fb0869cc-1084-4fd6-9142-12527368cdcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026426687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3026426687
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/165.rv_timer_random.3256554761
Short name T217
Test name
Test status
Simulation time 107468313402 ps
CPU time 200.55 seconds
Started Jun 13 12:54:08 PM PDT 24
Finished Jun 13 12:57:29 PM PDT 24
Peak memory 191104 kb
Host smart-5316ab95-97df-4ae0-ba00-7d17425c562a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256554761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3256554761
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1077361357
Short name T131
Test name
Test status
Simulation time 82609260448 ps
CPU time 63.08 seconds
Started Jun 13 12:54:21 PM PDT 24
Finished Jun 13 12:55:25 PM PDT 24
Peak memory 191168 kb
Host smart-58385659-735f-42f3-a696-b97bf071a8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077361357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1077361357
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.2302392829
Short name T146
Test name
Test status
Simulation time 866132875013 ps
CPU time 391.47 seconds
Started Jun 13 12:54:22 PM PDT 24
Finished Jun 13 01:00:54 PM PDT 24
Peak memory 194524 kb
Host smart-b2d49427-8652-4ac1-a98b-4d9d67e2c9a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302392829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2302392829
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.4116089052
Short name T158
Test name
Test status
Simulation time 154569843354 ps
CPU time 232.49 seconds
Started Jun 13 12:54:34 PM PDT 24
Finished Jun 13 12:58:27 PM PDT 24
Peak memory 191136 kb
Host smart-de325d31-c0bc-4c03-81b8-2b5e7274aed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116089052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4116089052
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.419871896
Short name T351
Test name
Test status
Simulation time 269994346333 ps
CPU time 1096.13 seconds
Started Jun 13 12:50:09 PM PDT 24
Finished Jun 13 01:08:28 PM PDT 24
Peak memory 182964 kb
Host smart-9b8a8b3a-dec2-497d-91e4-09b85494e1e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419871896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.419871896
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2435763686
Short name T344
Test name
Test status
Simulation time 45477683003 ps
CPU time 120.74 seconds
Started Jun 13 12:49:46 PM PDT 24
Finished Jun 13 12:51:48 PM PDT 24
Peak memory 191156 kb
Host smart-cc91c680-67cd-4391-91e2-11e23f54c27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435763686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2435763686
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_random.3068370398
Short name T110
Test name
Test status
Simulation time 29044485423 ps
CPU time 200.13 seconds
Started Jun 13 12:50:17 PM PDT 24
Finished Jun 13 12:53:39 PM PDT 24
Peak memory 191156 kb
Host smart-46970629-918c-4106-a48a-fd7f8e64f4df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068370398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3068370398
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.27180004
Short name T309
Test name
Test status
Simulation time 1189673742 ps
CPU time 2.51 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 12:50:05 PM PDT 24
Peak memory 182692 kb
Host smart-c01f76f3-898f-47f0-865c-aeba973afbc0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27180004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
rv_timer_cfg_update_on_fly.27180004
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3679910924
Short name T112
Test name
Test status
Simulation time 218065619360 ps
CPU time 631.44 seconds
Started Jun 13 12:49:46 PM PDT 24
Finished Jun 13 01:00:19 PM PDT 24
Peak memory 193488 kb
Host smart-d9b65bbd-f03d-4959-8cdc-5a02d067b2cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679910924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3679910924
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1450335977
Short name T145
Test name
Test status
Simulation time 889659069901 ps
CPU time 1423.22 seconds
Started Jun 13 12:51:53 PM PDT 24
Finished Jun 13 01:15:37 PM PDT 24
Peak memory 191140 kb
Host smart-2ce916db-e76d-4237-a360-5a0f0386b553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450335977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1450335977
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.4186594175
Short name T286
Test name
Test status
Simulation time 1451503754723 ps
CPU time 1196.18 seconds
Started Jun 13 12:51:59 PM PDT 24
Finished Jun 13 01:11:56 PM PDT 24
Peak memory 191072 kb
Host smart-e82f5b7e-e0c8-42e3-85ef-5d8ee0a57a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186594175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.4186594175
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1494928540
Short name T270
Test name
Test status
Simulation time 171919089058 ps
CPU time 566.74 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 12:59:30 PM PDT 24
Peak memory 195020 kb
Host smart-c1377a68-332c-4e68-afda-19e8edeb42d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494928540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1494928540
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.3490630704
Short name T263
Test name
Test status
Simulation time 262255158173 ps
CPU time 517.28 seconds
Started Jun 13 12:53:19 PM PDT 24
Finished Jun 13 01:01:57 PM PDT 24
Peak memory 192172 kb
Host smart-4c20fd02-6d07-4819-93ce-fd149a26855e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490630704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3490630704
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3170106982
Short name T255
Test name
Test status
Simulation time 150511572287 ps
CPU time 129.19 seconds
Started Jun 13 12:53:19 PM PDT 24
Finished Jun 13 12:55:29 PM PDT 24
Peak memory 191112 kb
Host smart-926a58b3-ef66-4f9d-b6f3-cd3c5a46c7f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170106982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3170106982
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2772665892
Short name T292
Test name
Test status
Simulation time 49189898472 ps
CPU time 117.93 seconds
Started Jun 13 12:49:58 PM PDT 24
Finished Jun 13 12:51:59 PM PDT 24
Peak memory 191120 kb
Host smart-cabfd688-f741-415c-bcd9-deae896c0d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772665892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2772665892
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.1206666929
Short name T281
Test name
Test status
Simulation time 465305540456 ps
CPU time 391.69 seconds
Started Jun 13 12:53:26 PM PDT 24
Finished Jun 13 12:59:58 PM PDT 24
Peak memory 191192 kb
Host smart-ddc4effb-e84f-4d7d-b173-f0c568e32968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206666929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1206666929
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.2472618747
Short name T69
Test name
Test status
Simulation time 72310307414 ps
CPU time 41.68 seconds
Started Jun 13 12:50:02 PM PDT 24
Finished Jun 13 12:50:48 PM PDT 24
Peak memory 182964 kb
Host smart-a4eb193b-5b02-4503-ac89-5d3412706fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472618747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2472618747
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1203310367
Short name T299
Test name
Test status
Simulation time 313304327242 ps
CPU time 244.89 seconds
Started Jun 13 12:50:02 PM PDT 24
Finished Jun 13 12:54:11 PM PDT 24
Peak memory 191152 kb
Host smart-38891119-a33b-4257-a5dd-39668413da24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203310367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1203310367
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.336686315
Short name T336
Test name
Test status
Simulation time 117354935101 ps
CPU time 355.6 seconds
Started Jun 13 12:53:45 PM PDT 24
Finished Jun 13 12:59:41 PM PDT 24
Peak memory 191164 kb
Host smart-7d1b26a0-51cb-42f0-aaa0-b9ff876f0cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336686315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.336686315
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3773887886
Short name T212
Test name
Test status
Simulation time 428058261029 ps
CPU time 365.71 seconds
Started Jun 13 12:53:46 PM PDT 24
Finished Jun 13 12:59:53 PM PDT 24
Peak memory 191152 kb
Host smart-c64192f6-60bc-45b1-9adb-8b7f212b7a13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773887886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3773887886
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1029031913
Short name T229
Test name
Test status
Simulation time 116773794737 ps
CPU time 401.8 seconds
Started Jun 13 12:53:59 PM PDT 24
Finished Jun 13 01:00:42 PM PDT 24
Peak memory 191164 kb
Host smart-a6c01b71-5046-4324-b39a-46f1902ab949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029031913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1029031913
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2636194879
Short name T72
Test name
Test status
Simulation time 255340142264 ps
CPU time 361.8 seconds
Started Jun 13 12:53:59 PM PDT 24
Finished Jun 13 01:00:01 PM PDT 24
Peak memory 191164 kb
Host smart-fa0d7ad0-1186-4f89-b197-fd4e9c34de76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636194879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2636194879
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3356430766
Short name T288
Test name
Test status
Simulation time 148425744920 ps
CPU time 147.13 seconds
Started Jun 13 12:53:55 PM PDT 24
Finished Jun 13 12:56:22 PM PDT 24
Peak memory 191212 kb
Host smart-d220956f-8425-4e15-9dd3-7b5f310422a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356430766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3356430766
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.120259517
Short name T271
Test name
Test status
Simulation time 334425963814 ps
CPU time 153.57 seconds
Started Jun 13 12:50:04 PM PDT 24
Finished Jun 13 12:52:41 PM PDT 24
Peak memory 191176 kb
Host smart-2e8e0dcc-a6a5-4ed9-8c4f-58196b6b3c4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120259517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.120259517
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1718324528
Short name T147
Test name
Test status
Simulation time 217656233199 ps
CPU time 1210.15 seconds
Started Jun 13 12:53:54 PM PDT 24
Finished Jun 13 01:14:05 PM PDT 24
Peak memory 191160 kb
Host smart-203e3fe3-83e2-41a0-82d8-39de7ae7be37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718324528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1718324528
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1513521136
Short name T200
Test name
Test status
Simulation time 250814049578 ps
CPU time 123.2 seconds
Started Jun 13 12:54:01 PM PDT 24
Finished Jun 13 12:56:05 PM PDT 24
Peak memory 191164 kb
Host smart-e6c25bd1-0645-475f-a264-9df2d5ad6e82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513521136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1513521136
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1858917389
Short name T172
Test name
Test status
Simulation time 80033434685 ps
CPU time 120.95 seconds
Started Jun 13 12:54:00 PM PDT 24
Finished Jun 13 12:56:01 PM PDT 24
Peak memory 191124 kb
Host smart-c1233ab6-1522-4b45-bc99-e25b87c629d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858917389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1858917389
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.412964523
Short name T160
Test name
Test status
Simulation time 268387990682 ps
CPU time 763.36 seconds
Started Jun 13 12:54:18 PM PDT 24
Finished Jun 13 01:07:02 PM PDT 24
Peak memory 191156 kb
Host smart-cd323019-8f70-4691-a411-4455898f70ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412964523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.412964523
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3798082786
Short name T353
Test name
Test status
Simulation time 47880427661 ps
CPU time 252.98 seconds
Started Jun 13 12:54:15 PM PDT 24
Finished Jun 13 12:58:29 PM PDT 24
Peak memory 191168 kb
Host smart-020da718-49c4-441d-8d16-4ad85728120e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798082786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3798082786
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3729336018
Short name T195
Test name
Test status
Simulation time 416874582177 ps
CPU time 536.61 seconds
Started Jun 13 12:54:29 PM PDT 24
Finished Jun 13 01:03:26 PM PDT 24
Peak memory 194392 kb
Host smart-7d539a99-eb97-417e-b7a2-30355855518e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729336018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3729336018
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1473104419
Short name T277
Test name
Test status
Simulation time 97078459573 ps
CPU time 101.18 seconds
Started Jun 13 12:54:28 PM PDT 24
Finished Jun 13 12:56:09 PM PDT 24
Peak memory 182876 kb
Host smart-7a487532-d9c6-4e21-a8a5-eeaf85c41388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473104419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1473104419
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1196453578
Short name T181
Test name
Test status
Simulation time 74024455112 ps
CPU time 128.58 seconds
Started Jun 13 12:50:17 PM PDT 24
Finished Jun 13 12:52:28 PM PDT 24
Peak memory 182916 kb
Host smart-08d0dc38-1411-4918-a23c-7ee0b153404e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196453578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1196453578
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/197.rv_timer_random.2325162508
Short name T119
Test name
Test status
Simulation time 58793723234 ps
CPU time 107.12 seconds
Started Jun 13 12:54:40 PM PDT 24
Finished Jun 13 12:56:28 PM PDT 24
Peak memory 191160 kb
Host smart-7c703cd8-b206-40e0-8719-51affc685d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325162508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2325162508
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3315923528
Short name T191
Test name
Test status
Simulation time 783214320405 ps
CPU time 119.14 seconds
Started Jun 13 12:54:40 PM PDT 24
Finished Jun 13 12:56:40 PM PDT 24
Peak memory 182952 kb
Host smart-5f03521b-0593-4b89-8a71-77b13d70a123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315923528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3315923528
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.240017472
Short name T174
Test name
Test status
Simulation time 84291398341 ps
CPU time 175.41 seconds
Started Jun 13 12:50:14 PM PDT 24
Finished Jun 13 12:53:11 PM PDT 24
Peak memory 193108 kb
Host smart-173106c6-710c-4f61-a9ef-950ffb388286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240017472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.240017472
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1435872513
Short name T224
Test name
Test status
Simulation time 345331913783 ps
CPU time 193.02 seconds
Started Jun 13 12:50:16 PM PDT 24
Finished Jun 13 12:53:31 PM PDT 24
Peak memory 191188 kb
Host smart-b855cbc6-e74d-442f-9b52-6fbba9995c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435872513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1435872513
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1854497944
Short name T185
Test name
Test status
Simulation time 145900794383 ps
CPU time 121.32 seconds
Started Jun 13 12:50:18 PM PDT 24
Finished Jun 13 12:52:21 PM PDT 24
Peak memory 191084 kb
Host smart-e84981b7-b4a4-4844-978a-16129f7c9fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854497944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1854497944
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2983538117
Short name T256
Test name
Test status
Simulation time 135635395639 ps
CPU time 1127.19 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 01:09:11 PM PDT 24
Peak memory 182976 kb
Host smart-809046c7-0997-433a-b265-a3e7a8249fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983538117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2983538117
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_random.3463818904
Short name T316
Test name
Test status
Simulation time 329371829899 ps
CPU time 146.38 seconds
Started Jun 13 12:50:40 PM PDT 24
Finished Jun 13 12:53:07 PM PDT 24
Peak memory 192288 kb
Host smart-7b7e92a0-a146-4d13-b0d1-e6d9b0585631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463818904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3463818904
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.3931996675
Short name T199
Test name
Test status
Simulation time 132068503810 ps
CPU time 219.43 seconds
Started Jun 13 12:50:43 PM PDT 24
Finished Jun 13 12:54:23 PM PDT 24
Peak memory 191148 kb
Host smart-e1896c7e-6b00-4e33-8494-9d512b209628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931996675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3931996675
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2079094088
Short name T138
Test name
Test status
Simulation time 670216677493 ps
CPU time 593.12 seconds
Started Jun 13 12:52:05 PM PDT 24
Finished Jun 13 01:01:58 PM PDT 24
Peak memory 182900 kb
Host smart-6a21df35-5bfa-4827-a408-51449d5e04f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079094088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2079094088
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/81.rv_timer_random.235865349
Short name T105
Test name
Test status
Simulation time 138137796601 ps
CPU time 283.29 seconds
Started Jun 13 12:53:05 PM PDT 24
Finished Jun 13 12:57:49 PM PDT 24
Peak memory 191152 kb
Host smart-f81d4a9c-6f33-4d76-a735-bc02e60b9e62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235865349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.235865349
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1239679453
Short name T231
Test name
Test status
Simulation time 113471653339 ps
CPU time 1240.62 seconds
Started Jun 13 12:53:14 PM PDT 24
Finished Jun 13 01:13:55 PM PDT 24
Peak memory 193540 kb
Host smart-95489bf0-a2a5-40fe-ae9e-b95f5d269dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239679453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1239679453
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1083424145
Short name T354
Test name
Test status
Simulation time 99869472 ps
CPU time 2.85 seconds
Started Jun 13 12:53:18 PM PDT 24
Finished Jun 13 12:53:22 PM PDT 24
Peak memory 182916 kb
Host smart-81b6f68e-f35c-45b7-b38f-9941e400721e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083424145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1083424145
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1016294478
Short name T81
Test name
Test status
Simulation time 221560038 ps
CPU time 0.81 seconds
Started Jun 13 12:49:00 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 192432 kb
Host smart-ca80cea6-431a-4161-a9b9-62c4a92b0488
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016294478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1016294478
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.595858735
Short name T533
Test name
Test status
Simulation time 145615503 ps
CPU time 1.58 seconds
Started Jun 13 12:48:52 PM PDT 24
Finished Jun 13 12:48:54 PM PDT 24
Peak memory 182828 kb
Host smart-9a029aa7-66bf-4698-a95e-09bd7e01d43c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595858735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.595858735
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1734782449
Short name T543
Test name
Test status
Simulation time 18896691 ps
CPU time 0.6 seconds
Started Jun 13 12:49:00 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 182660 kb
Host smart-ec8af102-0ef9-46ac-b000-88a6e7371bb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734782449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1734782449
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.807609507
Short name T553
Test name
Test status
Simulation time 34634164 ps
CPU time 1.64 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 197540 kb
Host smart-c50e7b53-a330-4f3e-bced-48fb0c79b198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807609507 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.807609507
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.207844442
Short name T459
Test name
Test status
Simulation time 17797899 ps
CPU time 0.6 seconds
Started Jun 13 12:48:53 PM PDT 24
Finished Jun 13 12:48:54 PM PDT 24
Peak memory 182624 kb
Host smart-cfc3b4c5-5264-458a-9868-f999282898e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207844442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.207844442
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1488839896
Short name T498
Test name
Test status
Simulation time 43263611 ps
CPU time 0.54 seconds
Started Jun 13 12:49:00 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 182000 kb
Host smart-d3f028cb-28b9-4b4e-8d9f-1ed80ff0a11e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488839896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1488839896
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3968784338
Short name T89
Test name
Test status
Simulation time 15464777 ps
CPU time 0.73 seconds
Started Jun 13 12:48:53 PM PDT 24
Finished Jun 13 12:48:54 PM PDT 24
Peak memory 193268 kb
Host smart-1f2da243-bbd3-4803-8fde-6a2d8c84a628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968784338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3968784338
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3427719527
Short name T456
Test name
Test status
Simulation time 119924232 ps
CPU time 1.42 seconds
Started Jun 13 12:49:00 PM PDT 24
Finished Jun 13 12:49:02 PM PDT 24
Peak memory 197512 kb
Host smart-9c8c7e33-543a-459f-bc5a-18086c568c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427719527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3427719527
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.318117420
Short name T579
Test name
Test status
Simulation time 279859920 ps
CPU time 1.11 seconds
Started Jun 13 12:48:52 PM PDT 24
Finished Jun 13 12:48:54 PM PDT 24
Peak memory 194092 kb
Host smart-0ac2b882-3e4d-4c74-98f0-82910e09ebfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318117420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.318117420
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.980587818
Short name T545
Test name
Test status
Simulation time 58395188 ps
CPU time 0.7 seconds
Started Jun 13 12:48:59 PM PDT 24
Finished Jun 13 12:49:00 PM PDT 24
Peak memory 182648 kb
Host smart-ba33e28d-0250-4a71-af02-e6ae634c3ba2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980587818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.980587818
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1940750231
Short name T463
Test name
Test status
Simulation time 571881997 ps
CPU time 3.64 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:49:02 PM PDT 24
Peak memory 193824 kb
Host smart-6d3509e7-0de7-41d8-8d30-3c97168616f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940750231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1940750231
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1956962383
Short name T551
Test name
Test status
Simulation time 54154464 ps
CPU time 0.58 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:49:00 PM PDT 24
Peak memory 191868 kb
Host smart-8d677dd7-4de5-44d4-a764-ba49bc10d754
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956962383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1956962383
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3771039055
Short name T556
Test name
Test status
Simulation time 31266844 ps
CPU time 0.87 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:48:59 PM PDT 24
Peak memory 196236 kb
Host smart-ed117b01-b255-4b3b-b638-21eb35c9bc9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771039055 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3771039055
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.758425850
Short name T77
Test name
Test status
Simulation time 32563723 ps
CPU time 0.56 seconds
Started Jun 13 12:48:57 PM PDT 24
Finished Jun 13 12:48:58 PM PDT 24
Peak memory 182536 kb
Host smart-371c719b-83b1-4702-9453-71628cb6ca94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758425850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.758425850
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2028358859
Short name T464
Test name
Test status
Simulation time 15708806 ps
CPU time 0.56 seconds
Started Jun 13 12:49:01 PM PDT 24
Finished Jun 13 12:49:02 PM PDT 24
Peak memory 182116 kb
Host smart-4b4577e1-98fa-4dc2-8312-746b71bdcdc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028358859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2028358859
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2290655388
Short name T529
Test name
Test status
Simulation time 37373681 ps
CPU time 0.78 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:48:59 PM PDT 24
Peak memory 193260 kb
Host smart-47037d2d-e407-437e-88e0-bda149ed206b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290655388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2290655388
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2086199338
Short name T566
Test name
Test status
Simulation time 91722232 ps
CPU time 1.83 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:49:00 PM PDT 24
Peak memory 197512 kb
Host smart-6a3a58a7-5b9c-4688-8b5e-384df4c77c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086199338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2086199338
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.986487384
Short name T536
Test name
Test status
Simulation time 83004121 ps
CPU time 0.82 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:48:59 PM PDT 24
Peak memory 193540 kb
Host smart-8c3438c4-ddb5-4c9b-8aa0-313d63812a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986487384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.986487384
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3523342934
Short name T492
Test name
Test status
Simulation time 28609845 ps
CPU time 1.19 seconds
Started Jun 13 12:49:19 PM PDT 24
Finished Jun 13 12:49:21 PM PDT 24
Peak memory 197460 kb
Host smart-5764f184-5a05-431b-820b-c16ff14d6871
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523342934 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3523342934
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3330732565
Short name T488
Test name
Test status
Simulation time 13832429 ps
CPU time 0.61 seconds
Started Jun 13 12:49:20 PM PDT 24
Finished Jun 13 12:49:22 PM PDT 24
Peak memory 182636 kb
Host smart-f818250c-0c6c-4612-b084-0d16a178d7aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330732565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3330732565
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.303245127
Short name T548
Test name
Test status
Simulation time 38771149 ps
CPU time 0.57 seconds
Started Jun 13 12:49:20 PM PDT 24
Finished Jun 13 12:49:21 PM PDT 24
Peak memory 182456 kb
Host smart-12c9e3a5-e219-4155-8457-0dac0a50c753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303245127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.303245127
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1789196585
Short name T499
Test name
Test status
Simulation time 34882158 ps
CPU time 0.86 seconds
Started Jun 13 12:49:18 PM PDT 24
Finished Jun 13 12:49:19 PM PDT 24
Peak memory 193376 kb
Host smart-37ab641b-7d98-4db8-b22f-1bafae389e46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789196585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1789196585
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2037320565
Short name T544
Test name
Test status
Simulation time 65875997 ps
CPU time 1.46 seconds
Started Jun 13 12:49:19 PM PDT 24
Finished Jun 13 12:49:21 PM PDT 24
Peak memory 197520 kb
Host smart-99d6f2e7-c5ee-4855-bb64-6ab62fb60aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037320565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2037320565
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3361139277
Short name T98
Test name
Test status
Simulation time 351101264 ps
CPU time 1.12 seconds
Started Jun 13 12:49:25 PM PDT 24
Finished Jun 13 12:49:27 PM PDT 24
Peak memory 183164 kb
Host smart-63af32a6-aa1b-421d-a725-9cb0f1e37848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361139277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3361139277
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.691133398
Short name T45
Test name
Test status
Simulation time 49102276 ps
CPU time 0.76 seconds
Started Jun 13 12:49:19 PM PDT 24
Finished Jun 13 12:49:20 PM PDT 24
Peak memory 195200 kb
Host smart-dc5d93a3-cb16-4d5c-99c7-0c0fdc26a5f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691133398 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.691133398
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4125343166
Short name T31
Test name
Test status
Simulation time 82795632 ps
CPU time 0.6 seconds
Started Jun 13 12:49:22 PM PDT 24
Finished Jun 13 12:49:23 PM PDT 24
Peak memory 182660 kb
Host smart-63268e0a-a799-4477-bd20-7b845fd043df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125343166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4125343166
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2907178004
Short name T508
Test name
Test status
Simulation time 44439304 ps
CPU time 0.58 seconds
Started Jun 13 12:49:18 PM PDT 24
Finished Jun 13 12:49:20 PM PDT 24
Peak memory 182128 kb
Host smart-cdff8a7e-57da-45fb-9c2d-6db1edfd71ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907178004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2907178004
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2302115570
Short name T534
Test name
Test status
Simulation time 19440008 ps
CPU time 0.62 seconds
Started Jun 13 12:49:19 PM PDT 24
Finished Jun 13 12:49:20 PM PDT 24
Peak memory 191916 kb
Host smart-a2785bdc-86ef-4ff7-aaca-0fbc8d0a24e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302115570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2302115570
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1884994147
Short name T570
Test name
Test status
Simulation time 212641624 ps
CPU time 3.13 seconds
Started Jun 13 12:49:24 PM PDT 24
Finished Jun 13 12:49:27 PM PDT 24
Peak memory 197456 kb
Host smart-6fe97697-04a8-4f22-b57d-3bc696e59f91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884994147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1884994147
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3324303694
Short name T28
Test name
Test status
Simulation time 48411477 ps
CPU time 0.82 seconds
Started Jun 13 12:49:18 PM PDT 24
Finished Jun 13 12:49:20 PM PDT 24
Peak memory 193420 kb
Host smart-5a155605-3c5b-4b26-8c26-e92aec85953e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324303694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3324303694
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2842349013
Short name T507
Test name
Test status
Simulation time 139762868 ps
CPU time 0.85 seconds
Started Jun 13 12:49:20 PM PDT 24
Finished Jun 13 12:49:21 PM PDT 24
Peak memory 197260 kb
Host smart-cdc7c303-cebf-409b-8411-53c1a5d09cfa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842349013 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2842349013
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.839381544
Short name T489
Test name
Test status
Simulation time 15778826 ps
CPU time 0.58 seconds
Started Jun 13 12:49:21 PM PDT 24
Finished Jun 13 12:49:22 PM PDT 24
Peak memory 182616 kb
Host smart-8f125504-b8c1-446e-aec8-82723074dfc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839381544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.839381544
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1197816052
Short name T90
Test name
Test status
Simulation time 16649448 ps
CPU time 0.6 seconds
Started Jun 13 12:49:20 PM PDT 24
Finished Jun 13 12:49:21 PM PDT 24
Peak memory 191220 kb
Host smart-99790974-7762-4755-a4ce-b0b72df361fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197816052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1197816052
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.237230423
Short name T46
Test name
Test status
Simulation time 138278483 ps
CPU time 2.45 seconds
Started Jun 13 12:49:20 PM PDT 24
Finished Jun 13 12:49:23 PM PDT 24
Peak memory 197512 kb
Host smart-81a4b409-a037-4d92-b910-faab993a81c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237230423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.237230423
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1346498442
Short name T482
Test name
Test status
Simulation time 95408809 ps
CPU time 0.86 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:28 PM PDT 24
Peak memory 193580 kb
Host smart-460af25c-f1da-45b1-bfa3-95b7bd17ebb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346498442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1346498442
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2287503001
Short name T522
Test name
Test status
Simulation time 46228308 ps
CPU time 1.05 seconds
Started Jun 13 12:49:23 PM PDT 24
Finished Jun 13 12:49:24 PM PDT 24
Peak memory 197476 kb
Host smart-92894102-3b8a-4133-a167-77548edc0bc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287503001 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2287503001
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2893955402
Short name T82
Test name
Test status
Simulation time 17131891 ps
CPU time 0.59 seconds
Started Jun 13 12:49:28 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 182648 kb
Host smart-a285d725-b117-46cd-996d-d6e3332b2a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893955402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2893955402
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.147966916
Short name T457
Test name
Test status
Simulation time 24187714 ps
CPU time 0.54 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:28 PM PDT 24
Peak memory 182184 kb
Host smart-fc533671-21ab-4830-aec7-04629f48e230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147966916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.147966916
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.308565145
Short name T496
Test name
Test status
Simulation time 23804628 ps
CPU time 0.68 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:27 PM PDT 24
Peak memory 192076 kb
Host smart-efecbc48-0cb3-4749-9047-bbdd68c1091e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308565145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.308565145
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2627184176
Short name T474
Test name
Test status
Simulation time 80485815 ps
CPU time 1.17 seconds
Started Jun 13 12:49:19 PM PDT 24
Finished Jun 13 12:49:21 PM PDT 24
Peak memory 197492 kb
Host smart-447e8db8-602e-4dc0-86c5-4748d18f0135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627184176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2627184176
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.792163927
Short name T568
Test name
Test status
Simulation time 86198660 ps
CPU time 1.12 seconds
Started Jun 13 12:49:27 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 197492 kb
Host smart-6ad03731-8d6f-442e-9214-8424c7610d13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792163927 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.792163927
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1161842368
Short name T32
Test name
Test status
Simulation time 25718237 ps
CPU time 0.58 seconds
Started Jun 13 12:49:27 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 191880 kb
Host smart-7df9e2c3-3d94-47de-9320-0f8e2b2ee3fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161842368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1161842368
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.151154096
Short name T477
Test name
Test status
Simulation time 18845000 ps
CPU time 0.53 seconds
Started Jun 13 12:49:24 PM PDT 24
Finished Jun 13 12:49:24 PM PDT 24
Peak memory 182196 kb
Host smart-9dd3669f-cbe9-415d-95ab-d7f10c6734eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151154096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.151154096
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3444430699
Short name T87
Test name
Test status
Simulation time 13980607 ps
CPU time 0.61 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:28 PM PDT 24
Peak memory 191852 kb
Host smart-201f5d1c-61eb-42c4-9019-b537445b63ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444430699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3444430699
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1941980895
Short name T461
Test name
Test status
Simulation time 103908464 ps
CPU time 1.35 seconds
Started Jun 13 12:49:25 PM PDT 24
Finished Jun 13 12:49:26 PM PDT 24
Peak memory 197292 kb
Host smart-94eba027-88b9-4886-8f82-bd4045923b98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941980895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1941980895
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4012176691
Short name T569
Test name
Test status
Simulation time 510854176 ps
CPU time 1.33 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:27 PM PDT 24
Peak memory 194428 kb
Host smart-7065c067-bc26-4289-b135-c2f77cb8862c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012176691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4012176691
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1040598346
Short name T530
Test name
Test status
Simulation time 139547724 ps
CPU time 0.99 seconds
Started Jun 13 12:49:25 PM PDT 24
Finished Jun 13 12:49:26 PM PDT 24
Peak memory 196840 kb
Host smart-6e27f453-378f-4d38-ae3f-a9e6b771ed27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040598346 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1040598346
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3977490322
Short name T75
Test name
Test status
Simulation time 10349562 ps
CPU time 0.52 seconds
Started Jun 13 12:49:28 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 182324 kb
Host smart-ff2b337f-d4b7-48f1-8154-451cf8acb13f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977490322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3977490322
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3986029865
Short name T520
Test name
Test status
Simulation time 51369158 ps
CPU time 0.58 seconds
Started Jun 13 12:49:25 PM PDT 24
Finished Jun 13 12:49:26 PM PDT 24
Peak memory 182580 kb
Host smart-514a6781-acc9-43a8-b3c4-2c0fb7f756c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986029865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3986029865
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.734130481
Short name T91
Test name
Test status
Simulation time 16871219 ps
CPU time 0.62 seconds
Started Jun 13 12:49:28 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 192068 kb
Host smart-9c5c61e7-36f6-4a43-8cae-94d9bcfe2bbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734130481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.734130481
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4011794331
Short name T469
Test name
Test status
Simulation time 46675672 ps
CPU time 2.32 seconds
Started Jun 13 12:49:28 PM PDT 24
Finished Jun 13 12:49:31 PM PDT 24
Peak memory 197444 kb
Host smart-f7576021-f27f-4221-831b-69b8a4a30199
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011794331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4011794331
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.214161613
Short name T29
Test name
Test status
Simulation time 94646796 ps
CPU time 1.13 seconds
Started Jun 13 12:49:25 PM PDT 24
Finished Jun 13 12:49:26 PM PDT 24
Peak memory 195004 kb
Host smart-607adefb-ec5a-4165-b569-647de31b0105
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214161613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.214161613
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.298806020
Short name T458
Test name
Test status
Simulation time 21318789 ps
CPU time 0.94 seconds
Started Jun 13 12:49:30 PM PDT 24
Finished Jun 13 12:49:31 PM PDT 24
Peak memory 197360 kb
Host smart-95a19c2d-efd4-49b7-a0d4-c2a25cac8f07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298806020 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.298806020
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3465363826
Short name T50
Test name
Test status
Simulation time 49683050 ps
CPU time 0.62 seconds
Started Jun 13 12:49:27 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 182600 kb
Host smart-9ba09da5-41ae-4bd8-8245-edaf788ecfdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465363826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3465363826
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.736486523
Short name T503
Test name
Test status
Simulation time 21909389 ps
CPU time 0.55 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:28 PM PDT 24
Peak memory 182584 kb
Host smart-d92bead1-8ac5-4d7c-a2aa-b7944bd19ef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736486523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.736486523
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1817820237
Short name T567
Test name
Test status
Simulation time 30017950 ps
CPU time 0.74 seconds
Started Jun 13 12:49:26 PM PDT 24
Finished Jun 13 12:49:28 PM PDT 24
Peak memory 192948 kb
Host smart-0a45aaa3-4375-4f24-bb58-d031cd6540ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817820237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1817820237
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3510230726
Short name T470
Test name
Test status
Simulation time 113240631 ps
CPU time 3.12 seconds
Started Jun 13 12:49:27 PM PDT 24
Finished Jun 13 12:49:31 PM PDT 24
Peak memory 197444 kb
Host smart-6037f9f1-ef28-40ac-9017-0fbde6b8c107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510230726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3510230726
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3900386437
Short name T562
Test name
Test status
Simulation time 345697034 ps
CPU time 0.81 seconds
Started Jun 13 12:49:35 PM PDT 24
Finished Jun 13 12:49:37 PM PDT 24
Peak memory 194740 kb
Host smart-3f6ff1de-d3b0-403e-b26d-aa1d709f64af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900386437 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3900386437
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2104681435
Short name T83
Test name
Test status
Simulation time 84987274 ps
CPU time 0.54 seconds
Started Jun 13 12:49:32 PM PDT 24
Finished Jun 13 12:49:33 PM PDT 24
Peak memory 182280 kb
Host smart-37142c07-7fe5-45ef-be60-65877d575735
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104681435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2104681435
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1985098007
Short name T532
Test name
Test status
Simulation time 146858990 ps
CPU time 0.54 seconds
Started Jun 13 12:49:30 PM PDT 24
Finished Jun 13 12:49:32 PM PDT 24
Peak memory 182004 kb
Host smart-030b5c9b-eddf-4bf2-a479-f88c5a761954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985098007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1985098007
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3970970562
Short name T30
Test name
Test status
Simulation time 19887184 ps
CPU time 0.77 seconds
Started Jun 13 12:49:33 PM PDT 24
Finished Jun 13 12:49:35 PM PDT 24
Peak memory 193324 kb
Host smart-2d74c7f6-476a-4c82-8318-66123d059266
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970970562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3970970562
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1070603758
Short name T575
Test name
Test status
Simulation time 87195705 ps
CPU time 1.67 seconds
Started Jun 13 12:49:27 PM PDT 24
Finished Jun 13 12:49:30 PM PDT 24
Peak memory 197556 kb
Host smart-e294c732-f61e-4959-b399-b3f5c9599e95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070603758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1070603758
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1939762687
Short name T541
Test name
Test status
Simulation time 41901365 ps
CPU time 0.83 seconds
Started Jun 13 12:49:27 PM PDT 24
Finished Jun 13 12:49:29 PM PDT 24
Peak memory 183280 kb
Host smart-9df5d1e0-c46f-48c2-9a64-9957526437d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939762687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1939762687
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1225312740
Short name T471
Test name
Test status
Simulation time 28932611 ps
CPU time 1.22 seconds
Started Jun 13 12:49:32 PM PDT 24
Finished Jun 13 12:49:34 PM PDT 24
Peak memory 197516 kb
Host smart-d79336ea-e3c8-4f85-a1b4-f35e5e342015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225312740 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1225312740
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.421098652
Short name T546
Test name
Test status
Simulation time 24348864 ps
CPU time 0.64 seconds
Started Jun 13 12:49:31 PM PDT 24
Finished Jun 13 12:49:33 PM PDT 24
Peak memory 182644 kb
Host smart-1d440671-e03d-4b26-8785-4da8a51eec93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421098652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.421098652
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3842646593
Short name T510
Test name
Test status
Simulation time 13241646 ps
CPU time 0.59 seconds
Started Jun 13 12:49:32 PM PDT 24
Finished Jun 13 12:49:34 PM PDT 24
Peak memory 182516 kb
Host smart-a8e6699f-3792-431d-b9b2-64aeaa795572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842646593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3842646593
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.647279986
Short name T549
Test name
Test status
Simulation time 18984943 ps
CPU time 0.69 seconds
Started Jun 13 12:49:32 PM PDT 24
Finished Jun 13 12:49:34 PM PDT 24
Peak memory 191612 kb
Host smart-7d6d6e34-e727-4b6d-b53f-0b8110034fe2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647279986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.647279986
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.689567845
Short name T564
Test name
Test status
Simulation time 47788245 ps
CPU time 2.38 seconds
Started Jun 13 12:49:32 PM PDT 24
Finished Jun 13 12:49:35 PM PDT 24
Peak memory 197512 kb
Host smart-60644f74-8d33-4832-a957-8c11f763f963
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689567845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.689567845
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1727771923
Short name T479
Test name
Test status
Simulation time 184850953 ps
CPU time 1.39 seconds
Started Jun 13 12:49:30 PM PDT 24
Finished Jun 13 12:49:31 PM PDT 24
Peak memory 195220 kb
Host smart-f89f18d8-19fa-487b-bcce-ce9239c40861
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727771923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1727771923
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3418781028
Short name T500
Test name
Test status
Simulation time 20811592 ps
CPU time 0.96 seconds
Started Jun 13 12:49:34 PM PDT 24
Finished Jun 13 12:49:36 PM PDT 24
Peak memory 196048 kb
Host smart-b75d0974-a993-46ce-aed9-a3b007833597
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418781028 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3418781028
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1301634256
Short name T462
Test name
Test status
Simulation time 39610400 ps
CPU time 0.5 seconds
Started Jun 13 12:49:29 PM PDT 24
Finished Jun 13 12:49:30 PM PDT 24
Peak memory 182292 kb
Host smart-dc45f7ec-4372-46a9-abd1-734e3dbb2284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301634256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1301634256
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1413511062
Short name T452
Test name
Test status
Simulation time 16999639 ps
CPU time 0.53 seconds
Started Jun 13 12:49:32 PM PDT 24
Finished Jun 13 12:49:33 PM PDT 24
Peak memory 181980 kb
Host smart-c72f31cb-f21f-49f0-af84-baacaacc9678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413511062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1413511062
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2420874765
Short name T506
Test name
Test status
Simulation time 14280036 ps
CPU time 0.62 seconds
Started Jun 13 12:49:35 PM PDT 24
Finished Jun 13 12:49:36 PM PDT 24
Peak memory 191380 kb
Host smart-5e91130a-4158-4ca6-ae4e-e155e0777522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420874765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2420874765
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1399784313
Short name T478
Test name
Test status
Simulation time 1752837675 ps
CPU time 2.66 seconds
Started Jun 13 12:49:31 PM PDT 24
Finished Jun 13 12:49:35 PM PDT 24
Peak memory 197500 kb
Host smart-844110a9-b80f-43d1-ae5e-1985a06180ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399784313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1399784313
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2148714367
Short name T531
Test name
Test status
Simulation time 100767376 ps
CPU time 1.39 seconds
Started Jun 13 12:49:32 PM PDT 24
Finished Jun 13 12:49:35 PM PDT 24
Peak memory 183332 kb
Host smart-6780f898-2787-424d-8f64-d260d027fdab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148714367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2148714367
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3468941974
Short name T48
Test name
Test status
Simulation time 37606891 ps
CPU time 0.83 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:49:00 PM PDT 24
Peak memory 190804 kb
Host smart-55c2917e-4899-4a3f-b187-c39845019060
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468941974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3468941974
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2684224228
Short name T565
Test name
Test status
Simulation time 133905610 ps
CPU time 1.43 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:49:00 PM PDT 24
Peak memory 191032 kb
Host smart-57c85c71-5c64-4a38-8d8c-50bb5720b619
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684224228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2684224228
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.19683921
Short name T76
Test name
Test status
Simulation time 41051788 ps
CPU time 0.55 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:48:59 PM PDT 24
Peak memory 182588 kb
Host smart-a2be9527-e0fd-4360-9a9d-c55593e05271
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19683921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_res
et.19683921
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2025113686
Short name T525
Test name
Test status
Simulation time 148306266 ps
CPU time 1.81 seconds
Started Jun 13 12:48:59 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 197408 kb
Host smart-d96cf0d9-e559-42f6-82f6-8ca8595cdec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025113686 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2025113686
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2123883660
Short name T494
Test name
Test status
Simulation time 90902655 ps
CPU time 0.6 seconds
Started Jun 13 12:49:00 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 182640 kb
Host smart-917e5144-60cf-477a-a83a-f715127d1d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123883660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2123883660
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3038078570
Short name T483
Test name
Test status
Simulation time 38366441 ps
CPU time 0.57 seconds
Started Jun 13 12:48:57 PM PDT 24
Finished Jun 13 12:48:58 PM PDT 24
Peak memory 182488 kb
Host smart-b8dcded3-8333-49ca-a11d-f78d9be9f9a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038078570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3038078570
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1188325186
Short name T88
Test name
Test status
Simulation time 114617139 ps
CPU time 0.83 seconds
Started Jun 13 12:48:59 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 193428 kb
Host smart-8e95f95e-d92f-4570-9e8f-657c93a83382
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188325186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1188325186
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1806326862
Short name T535
Test name
Test status
Simulation time 783778401 ps
CPU time 2.8 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:49:01 PM PDT 24
Peak memory 197492 kb
Host smart-25f83a35-b160-46b1-94ce-db8ee9bc9c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806326862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1806326862
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.297163564
Short name T491
Test name
Test status
Simulation time 40715108 ps
CPU time 0.86 seconds
Started Jun 13 12:48:58 PM PDT 24
Finished Jun 13 12:48:59 PM PDT 24
Peak memory 193364 kb
Host smart-139a1b6f-f804-4269-8db8-ac08c022902d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297163564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.297163564
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3180617902
Short name T454
Test name
Test status
Simulation time 12361104 ps
CPU time 0.58 seconds
Started Jun 13 12:49:31 PM PDT 24
Finished Jun 13 12:49:32 PM PDT 24
Peak memory 182540 kb
Host smart-4fee1e45-00e7-4360-8150-8d6473acf303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180617902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3180617902
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1870840684
Short name T517
Test name
Test status
Simulation time 14013607 ps
CPU time 0.55 seconds
Started Jun 13 12:49:33 PM PDT 24
Finished Jun 13 12:49:35 PM PDT 24
Peak memory 182540 kb
Host smart-7cdb96b8-1415-4485-bd3b-ad9f7eb77b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870840684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1870840684
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3714407652
Short name T467
Test name
Test status
Simulation time 12184227 ps
CPU time 0.59 seconds
Started Jun 13 12:49:34 PM PDT 24
Finished Jun 13 12:49:35 PM PDT 24
Peak memory 182588 kb
Host smart-7e88b50e-1885-499d-aec9-858e0f078395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714407652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3714407652
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1112645873
Short name T574
Test name
Test status
Simulation time 33832950 ps
CPU time 0.56 seconds
Started Jun 13 12:49:38 PM PDT 24
Finished Jun 13 12:49:40 PM PDT 24
Peak memory 182524 kb
Host smart-a89fbe2b-b572-448b-b4d1-b1aaacf72fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112645873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1112645873
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2305163607
Short name T513
Test name
Test status
Simulation time 11926932 ps
CPU time 0.58 seconds
Started Jun 13 12:49:39 PM PDT 24
Finished Jun 13 12:49:41 PM PDT 24
Peak memory 182504 kb
Host smart-ac27a1d0-fa6f-4e87-9791-8deb66670d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305163607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2305163607
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1937964542
Short name T476
Test name
Test status
Simulation time 13410236 ps
CPU time 0.54 seconds
Started Jun 13 12:49:37 PM PDT 24
Finished Jun 13 12:49:39 PM PDT 24
Peak memory 181940 kb
Host smart-99d10fbb-03eb-42dc-b7e0-579142864427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937964542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1937964542
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.298229685
Short name T480
Test name
Test status
Simulation time 33359751 ps
CPU time 0.52 seconds
Started Jun 13 12:49:38 PM PDT 24
Finished Jun 13 12:49:41 PM PDT 24
Peak memory 181936 kb
Host smart-e33e48ec-7012-47f6-82c9-f3f255c58679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298229685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.298229685
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1758519846
Short name T512
Test name
Test status
Simulation time 10769766 ps
CPU time 0.52 seconds
Started Jun 13 12:49:37 PM PDT 24
Finished Jun 13 12:49:39 PM PDT 24
Peak memory 182004 kb
Host smart-1ce9b353-c62e-466f-bce9-fac2f4ff4426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758519846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1758519846
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2413223420
Short name T455
Test name
Test status
Simulation time 27390881 ps
CPU time 0.53 seconds
Started Jun 13 12:49:43 PM PDT 24
Finished Jun 13 12:49:45 PM PDT 24
Peak memory 182008 kb
Host smart-46c3d358-610f-4ad6-9543-2f95f762847e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413223420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2413223420
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2520284658
Short name T502
Test name
Test status
Simulation time 56286580 ps
CPU time 0.6 seconds
Started Jun 13 12:49:38 PM PDT 24
Finished Jun 13 12:49:40 PM PDT 24
Peak memory 182564 kb
Host smart-d50b2cc3-7493-4ba9-aa75-5bf89175131b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520284658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2520284658
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1252881627
Short name T511
Test name
Test status
Simulation time 35161005 ps
CPU time 0.64 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:08 PM PDT 24
Peak memory 182652 kb
Host smart-a8a94043-4eed-4765-90a0-780b2b8f6650
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252881627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1252881627
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.947612507
Short name T557
Test name
Test status
Simulation time 136182445 ps
CPU time 2.43 seconds
Started Jun 13 12:49:06 PM PDT 24
Finished Jun 13 12:49:09 PM PDT 24
Peak memory 192216 kb
Host smart-5c479057-45b7-47cb-8909-7b021ecd7d02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947612507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.947612507
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4186260977
Short name T497
Test name
Test status
Simulation time 38391561 ps
CPU time 0.61 seconds
Started Jun 13 12:49:05 PM PDT 24
Finished Jun 13 12:49:06 PM PDT 24
Peak memory 182644 kb
Host smart-bcf1d32b-f121-4253-9545-6995ba30edde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186260977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4186260977
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.937336316
Short name T515
Test name
Test status
Simulation time 34705796 ps
CPU time 0.96 seconds
Started Jun 13 12:49:05 PM PDT 24
Finished Jun 13 12:49:06 PM PDT 24
Peak memory 197348 kb
Host smart-a5876d73-a3cf-4cfc-897a-eefc8c18d83a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937336316 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.937336316
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1470128644
Short name T86
Test name
Test status
Simulation time 39529090 ps
CPU time 0.54 seconds
Started Jun 13 12:49:04 PM PDT 24
Finished Jun 13 12:49:05 PM PDT 24
Peak memory 182468 kb
Host smart-5ac89379-3769-4c8c-b804-2f36935cea47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470128644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1470128644
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.707594314
Short name T518
Test name
Test status
Simulation time 30114445 ps
CPU time 0.56 seconds
Started Jun 13 12:49:05 PM PDT 24
Finished Jun 13 12:49:06 PM PDT 24
Peak memory 182188 kb
Host smart-6190509a-efad-4807-a0f3-ec6cc656c2d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707594314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.707594314
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1618109813
Short name T481
Test name
Test status
Simulation time 21133359 ps
CPU time 0.8 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:08 PM PDT 24
Peak memory 191664 kb
Host smart-6483bfec-5eb1-493c-8f6d-56970ead4ed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618109813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1618109813
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3900660854
Short name T460
Test name
Test status
Simulation time 137823614 ps
CPU time 0.97 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:08 PM PDT 24
Peak memory 196680 kb
Host smart-955de7d2-3710-43d7-95cf-391895da35bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900660854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3900660854
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2258626113
Short name T509
Test name
Test status
Simulation time 207010436 ps
CPU time 1.36 seconds
Started Jun 13 12:49:04 PM PDT 24
Finished Jun 13 12:49:06 PM PDT 24
Peak memory 183140 kb
Host smart-a098f309-37c7-402c-a669-1e0e80338a81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258626113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2258626113
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.620235264
Short name T465
Test name
Test status
Simulation time 51456311 ps
CPU time 0.57 seconds
Started Jun 13 12:49:38 PM PDT 24
Finished Jun 13 12:49:41 PM PDT 24
Peak memory 182536 kb
Host smart-8ec9058e-8da3-4cab-bfde-025f3d30eedf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620235264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.620235264
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.506076337
Short name T576
Test name
Test status
Simulation time 14527322 ps
CPU time 0.6 seconds
Started Jun 13 12:49:37 PM PDT 24
Finished Jun 13 12:49:38 PM PDT 24
Peak memory 182416 kb
Host smart-3be2af19-c892-43ff-a0e2-d551bdbe44a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506076337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.506076337
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3211715058
Short name T540
Test name
Test status
Simulation time 16797251 ps
CPU time 0.55 seconds
Started Jun 13 12:49:38 PM PDT 24
Finished Jun 13 12:49:39 PM PDT 24
Peak memory 182424 kb
Host smart-a69df3f4-0b3c-4c63-8a6f-7177673a84de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211715058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3211715058
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1617326191
Short name T571
Test name
Test status
Simulation time 20875094 ps
CPU time 0.52 seconds
Started Jun 13 12:49:45 PM PDT 24
Finished Jun 13 12:49:47 PM PDT 24
Peak memory 181976 kb
Host smart-8207f85d-6348-40e0-adba-36664785bc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617326191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1617326191
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.458974620
Short name T514
Test name
Test status
Simulation time 116542561 ps
CPU time 0.57 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:49:42 PM PDT 24
Peak memory 182492 kb
Host smart-1bcad8a1-8644-4b22-83a2-f16b9e4eb10b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458974620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.458974620
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3570609264
Short name T501
Test name
Test status
Simulation time 23191998 ps
CPU time 0.55 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:49:42 PM PDT 24
Peak memory 181988 kb
Host smart-5416f8f3-807b-4183-b36b-4ff0e5b8eafb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570609264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3570609264
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2556476118
Short name T468
Test name
Test status
Simulation time 30663360 ps
CPU time 0.56 seconds
Started Jun 13 12:49:39 PM PDT 24
Finished Jun 13 12:49:41 PM PDT 24
Peak memory 182508 kb
Host smart-b006886a-f497-4e0e-b53c-6ca5f9afb7fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556476118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2556476118
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1633363216
Short name T572
Test name
Test status
Simulation time 45833215 ps
CPU time 0.59 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:49:43 PM PDT 24
Peak memory 181988 kb
Host smart-44fabc43-ce6e-4b9a-8c2c-2ea575989069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633363216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1633363216
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.105755874
Short name T554
Test name
Test status
Simulation time 13916832 ps
CPU time 0.51 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:49:43 PM PDT 24
Peak memory 181968 kb
Host smart-033aa0d4-9d58-43e9-b4b7-7bbed7c14e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105755874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.105755874
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4077270522
Short name T538
Test name
Test status
Simulation time 45738190 ps
CPU time 0.57 seconds
Started Jun 13 12:49:41 PM PDT 24
Finished Jun 13 12:49:43 PM PDT 24
Peak memory 182512 kb
Host smart-dd5ac1d2-f378-4775-8e8c-31392049dc7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077270522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4077270522
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2742569503
Short name T80
Test name
Test status
Simulation time 50460356 ps
CPU time 0.8 seconds
Started Jun 13 12:49:04 PM PDT 24
Finished Jun 13 12:49:05 PM PDT 24
Peak memory 192056 kb
Host smart-39506714-73f7-40f3-9a7d-aba10a8c2a5b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742569503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2742569503
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.727286309
Short name T523
Test name
Test status
Simulation time 561238914 ps
CPU time 1.62 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:10 PM PDT 24
Peak memory 193648 kb
Host smart-09e3d6ff-f396-4fb7-98ce-99b06c057f58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727286309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.727286309
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3210770857
Short name T580
Test name
Test status
Simulation time 21138128 ps
CPU time 0.61 seconds
Started Jun 13 12:49:04 PM PDT 24
Finished Jun 13 12:49:05 PM PDT 24
Peak memory 182636 kb
Host smart-70b366f6-0b9c-4425-8cf8-9cbae4c7c08c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210770857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3210770857
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3782635297
Short name T537
Test name
Test status
Simulation time 25525675 ps
CPU time 0.75 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:09 PM PDT 24
Peak memory 195820 kb
Host smart-87d2623c-dcbe-4123-a2ba-9b73e4e9a298
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782635297 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3782635297
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1201324181
Short name T550
Test name
Test status
Simulation time 19493581 ps
CPU time 0.6 seconds
Started Jun 13 12:49:05 PM PDT 24
Finished Jun 13 12:49:07 PM PDT 24
Peak memory 182596 kb
Host smart-227c9dec-0e5d-442a-9cf4-48787285cb94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201324181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1201324181
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3165872894
Short name T484
Test name
Test status
Simulation time 49936594 ps
CPU time 0.63 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:08 PM PDT 24
Peak memory 191892 kb
Host smart-fb267e78-218f-4034-9df1-aa31dbb4ecf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165872894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3165872894
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.103605812
Short name T505
Test name
Test status
Simulation time 375076421 ps
CPU time 2.2 seconds
Started Jun 13 12:49:05 PM PDT 24
Finished Jun 13 12:49:08 PM PDT 24
Peak memory 197492 kb
Host smart-8b12d8b4-7680-4f20-88b5-9a019b118e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103605812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.103605812
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3064014400
Short name T578
Test name
Test status
Simulation time 82478325 ps
CPU time 1.11 seconds
Started Jun 13 12:49:05 PM PDT 24
Finished Jun 13 12:49:06 PM PDT 24
Peak memory 183368 kb
Host smart-d98338d3-7c5e-4bf4-9101-ff8932fe4f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064014400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3064014400
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4252094395
Short name T453
Test name
Test status
Simulation time 53479058 ps
CPU time 0.6 seconds
Started Jun 13 12:49:39 PM PDT 24
Finished Jun 13 12:49:41 PM PDT 24
Peak memory 182580 kb
Host smart-fb382c9a-ce6b-4fc0-8a25-f0aa04c3b992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252094395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4252094395
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3834113728
Short name T555
Test name
Test status
Simulation time 25873573 ps
CPU time 0.58 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:49:42 PM PDT 24
Peak memory 182532 kb
Host smart-17ca0376-1a3d-4b4c-a1b5-cbe3bfb89e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834113728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3834113728
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1967634550
Short name T519
Test name
Test status
Simulation time 26455917 ps
CPU time 0.58 seconds
Started Jun 13 12:49:41 PM PDT 24
Finished Jun 13 12:49:43 PM PDT 24
Peak memory 182560 kb
Host smart-4b555353-ab5c-4389-b413-b3ee95ca9266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967634550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1967634550
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.250456029
Short name T542
Test name
Test status
Simulation time 217708721 ps
CPU time 0.55 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:49:42 PM PDT 24
Peak memory 182204 kb
Host smart-73380e9d-4b39-44fd-a805-d27f494dd7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250456029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.250456029
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1999532866
Short name T521
Test name
Test status
Simulation time 21949592 ps
CPU time 0.57 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:49:43 PM PDT 24
Peak memory 182576 kb
Host smart-ca7ff454-3057-40d3-8dc8-a38e0cfdbd2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999532866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1999532866
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2889718668
Short name T563
Test name
Test status
Simulation time 13384000 ps
CPU time 0.54 seconds
Started Jun 13 12:49:39 PM PDT 24
Finished Jun 13 12:49:41 PM PDT 24
Peak memory 181988 kb
Host smart-d4f7b0cd-ec26-4701-ac82-fbc03943a500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889718668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2889718668
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1853460802
Short name T577
Test name
Test status
Simulation time 18321930 ps
CPU time 0.57 seconds
Started Jun 13 12:49:45 PM PDT 24
Finished Jun 13 12:49:47 PM PDT 24
Peak memory 182572 kb
Host smart-39ea8b41-2394-41f0-a92c-13beea274735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853460802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1853460802
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3007933177
Short name T487
Test name
Test status
Simulation time 12882345 ps
CPU time 0.51 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:49:42 PM PDT 24
Peak memory 182004 kb
Host smart-da837b68-a90b-4339-b4a2-f7f1ee67cf3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007933177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3007933177
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1551107079
Short name T473
Test name
Test status
Simulation time 14731005 ps
CPU time 0.54 seconds
Started Jun 13 12:49:38 PM PDT 24
Finished Jun 13 12:49:41 PM PDT 24
Peak memory 181968 kb
Host smart-fbf32f0b-ff57-40d6-8305-9a1f91e7ddad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551107079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1551107079
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3799061364
Short name T526
Test name
Test status
Simulation time 16019426 ps
CPU time 0.59 seconds
Started Jun 13 12:49:41 PM PDT 24
Finished Jun 13 12:49:43 PM PDT 24
Peak memory 182508 kb
Host smart-a94e3207-f851-45f1-b084-b08ab7cfb681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799061364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3799061364
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.252265438
Short name T49
Test name
Test status
Simulation time 288734302 ps
CPU time 0.79 seconds
Started Jun 13 12:49:04 PM PDT 24
Finished Jun 13 12:49:05 PM PDT 24
Peak memory 195656 kb
Host smart-cebc7848-6471-43a2-b2d9-158da3be455b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252265438 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.252265438
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1605495257
Short name T486
Test name
Test status
Simulation time 11621142 ps
CPU time 0.57 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:08 PM PDT 24
Peak memory 182656 kb
Host smart-6f72f11a-3451-4f24-a2b0-90a4cdfd79b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605495257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1605495257
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3110776406
Short name T528
Test name
Test status
Simulation time 14068952 ps
CPU time 0.54 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:08 PM PDT 24
Peak memory 181988 kb
Host smart-76a076b7-8034-4ae9-a6df-ab758adba417
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110776406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3110776406
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2300590999
Short name T552
Test name
Test status
Simulation time 37906478 ps
CPU time 0.79 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:09 PM PDT 24
Peak memory 193244 kb
Host smart-2a13d810-680d-4bad-81fa-adfab5562af7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300590999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2300590999
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.843747782
Short name T524
Test name
Test status
Simulation time 28952764 ps
CPU time 1.54 seconds
Started Jun 13 12:49:04 PM PDT 24
Finished Jun 13 12:49:06 PM PDT 24
Peak memory 197512 kb
Host smart-fdd8908b-9734-4111-ae23-1698325539fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843747782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.843747782
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.820836741
Short name T490
Test name
Test status
Simulation time 435853303 ps
CPU time 1.37 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:09 PM PDT 24
Peak memory 195368 kb
Host smart-eedc0870-d5f1-45ee-b95b-5bc7227e21bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820836741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.820836741
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3477090449
Short name T466
Test name
Test status
Simulation time 38074852 ps
CPU time 1.71 seconds
Started Jun 13 12:49:14 PM PDT 24
Finished Jun 13 12:49:17 PM PDT 24
Peak memory 197488 kb
Host smart-b6d682f9-1860-47c4-b5b6-3d5e70a5c1aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477090449 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3477090449
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3207860351
Short name T495
Test name
Test status
Simulation time 15069438 ps
CPU time 0.59 seconds
Started Jun 13 12:49:11 PM PDT 24
Finished Jun 13 12:49:12 PM PDT 24
Peak memory 182544 kb
Host smart-278a29f9-86cb-4adf-9733-3e37c899bddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207860351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3207860351
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.955599288
Short name T493
Test name
Test status
Simulation time 14772803 ps
CPU time 0.57 seconds
Started Jun 13 12:49:13 PM PDT 24
Finished Jun 13 12:49:14 PM PDT 24
Peak memory 182644 kb
Host smart-a32ab357-5381-4e7e-b444-8096fa665ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955599288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.955599288
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.598772564
Short name T516
Test name
Test status
Simulation time 87452910 ps
CPU time 0.82 seconds
Started Jun 13 12:49:14 PM PDT 24
Finished Jun 13 12:49:15 PM PDT 24
Peak memory 193332 kb
Host smart-2f8cfe5b-b6af-4a3b-8556-00d72eee4066
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598772564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.598772564
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2410887025
Short name T573
Test name
Test status
Simulation time 348928812 ps
CPU time 2.3 seconds
Started Jun 13 12:49:07 PM PDT 24
Finished Jun 13 12:49:10 PM PDT 24
Peak memory 197552 kb
Host smart-4d72b60d-e5d2-4502-9194-be50f3c861c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410887025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2410887025
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1278669031
Short name T99
Test name
Test status
Simulation time 66519334 ps
CPU time 0.84 seconds
Started Jun 13 12:49:13 PM PDT 24
Finished Jun 13 12:49:14 PM PDT 24
Peak memory 193676 kb
Host smart-ad067a04-854a-40a1-a143-8bab0a1d7826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278669031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1278669031
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.723492614
Short name T527
Test name
Test status
Simulation time 33746894 ps
CPU time 1.43 seconds
Started Jun 13 12:49:14 PM PDT 24
Finished Jun 13 12:49:16 PM PDT 24
Peak memory 197500 kb
Host smart-1ebd0d87-43db-433d-bc11-d02988dd4a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723492614 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.723492614
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4272134156
Short name T79
Test name
Test status
Simulation time 55847667 ps
CPU time 0.59 seconds
Started Jun 13 12:49:11 PM PDT 24
Finished Jun 13 12:49:13 PM PDT 24
Peak memory 182648 kb
Host smart-8682ef15-c1d8-49d9-99ad-84d73a297884
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272134156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.4272134156
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2821034905
Short name T558
Test name
Test status
Simulation time 22383933 ps
CPU time 0.56 seconds
Started Jun 13 12:49:11 PM PDT 24
Finished Jun 13 12:49:12 PM PDT 24
Peak memory 182156 kb
Host smart-2db50fe1-bd55-4a5e-9e08-a00886b53458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821034905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2821034905
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1858169155
Short name T539
Test name
Test status
Simulation time 133295940 ps
CPU time 0.76 seconds
Started Jun 13 12:49:12 PM PDT 24
Finished Jun 13 12:49:13 PM PDT 24
Peak memory 193268 kb
Host smart-f8d26a44-95ab-4217-a46d-cfbf551067c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858169155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1858169155
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3467777231
Short name T561
Test name
Test status
Simulation time 87245498 ps
CPU time 1.34 seconds
Started Jun 13 12:49:14 PM PDT 24
Finished Jun 13 12:49:16 PM PDT 24
Peak memory 197552 kb
Host smart-7155a973-e065-4d64-bf42-951eb934b0c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467777231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3467777231
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4029458161
Short name T504
Test name
Test status
Simulation time 232781535 ps
CPU time 1.39 seconds
Started Jun 13 12:49:13 PM PDT 24
Finished Jun 13 12:49:15 PM PDT 24
Peak memory 195140 kb
Host smart-7d815305-206f-43e4-a760-3ace9dea71ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029458161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.4029458161
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2406276721
Short name T581
Test name
Test status
Simulation time 127344380 ps
CPU time 0.83 seconds
Started Jun 13 12:49:13 PM PDT 24
Finished Jun 13 12:49:14 PM PDT 24
Peak memory 196560 kb
Host smart-bbda5431-7e8e-406f-a4f3-306149ced9e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406276721 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2406276721
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2705871512
Short name T84
Test name
Test status
Simulation time 41971930 ps
CPU time 0.56 seconds
Started Jun 13 12:49:15 PM PDT 24
Finished Jun 13 12:49:16 PM PDT 24
Peak memory 182640 kb
Host smart-1e8878ef-3752-49d0-b98c-5dd29a90688e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705871512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2705871512
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2796980057
Short name T450
Test name
Test status
Simulation time 15555297 ps
CPU time 0.56 seconds
Started Jun 13 12:49:12 PM PDT 24
Finished Jun 13 12:49:13 PM PDT 24
Peak memory 181916 kb
Host smart-43851c68-f896-4d94-9031-9481db96ab93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796980057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2796980057
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1719008411
Short name T485
Test name
Test status
Simulation time 57806387 ps
CPU time 0.78 seconds
Started Jun 13 12:49:16 PM PDT 24
Finished Jun 13 12:49:18 PM PDT 24
Peak memory 191632 kb
Host smart-a0a9dbac-93cc-4937-8182-de7e7511c866
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719008411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1719008411
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2613274360
Short name T472
Test name
Test status
Simulation time 335577473 ps
CPU time 1.23 seconds
Started Jun 13 12:49:13 PM PDT 24
Finished Jun 13 12:49:14 PM PDT 24
Peak memory 197740 kb
Host smart-49e30425-df2f-42f3-a083-5f177a19591d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613274360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2613274360
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2418556896
Short name T559
Test name
Test status
Simulation time 113994798 ps
CPU time 1.49 seconds
Started Jun 13 12:49:14 PM PDT 24
Finished Jun 13 12:49:16 PM PDT 24
Peak memory 183164 kb
Host smart-0283923f-f3f7-45b3-be74-a7e33e6f378a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418556896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2418556896
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2139713912
Short name T547
Test name
Test status
Simulation time 44898812 ps
CPU time 0.75 seconds
Started Jun 13 12:49:16 PM PDT 24
Finished Jun 13 12:49:17 PM PDT 24
Peak memory 195080 kb
Host smart-b74adb70-c0fa-425b-9940-97c316a6c330
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139713912 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2139713912
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1549306900
Short name T85
Test name
Test status
Simulation time 17414960 ps
CPU time 0.59 seconds
Started Jun 13 12:49:17 PM PDT 24
Finished Jun 13 12:49:18 PM PDT 24
Peak memory 182624 kb
Host smart-8ac7727b-0808-4c73-8744-6524a84dc4dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549306900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1549306900
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3977960796
Short name T475
Test name
Test status
Simulation time 50526296 ps
CPU time 0.58 seconds
Started Jun 13 12:49:16 PM PDT 24
Finished Jun 13 12:49:17 PM PDT 24
Peak memory 182576 kb
Host smart-ae4b4299-7100-47c0-9d6a-7845dbdd6abf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977960796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3977960796
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.627417708
Short name T560
Test name
Test status
Simulation time 37312600 ps
CPU time 0.84 seconds
Started Jun 13 12:49:11 PM PDT 24
Finished Jun 13 12:49:13 PM PDT 24
Peak memory 193468 kb
Host smart-e9547af2-e2ef-40e0-b19d-7461f278cb6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627417708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.627417708
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1945602330
Short name T451
Test name
Test status
Simulation time 39940606 ps
CPU time 1.01 seconds
Started Jun 13 12:49:16 PM PDT 24
Finished Jun 13 12:49:17 PM PDT 24
Peak memory 195592 kb
Host smart-adbc2869-3c99-4204-af6d-e5b7019e9a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945602330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1945602330
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2375718511
Short name T96
Test name
Test status
Simulation time 206326489 ps
CPU time 1.12 seconds
Started Jun 13 12:49:13 PM PDT 24
Finished Jun 13 12:49:15 PM PDT 24
Peak memory 194216 kb
Host smart-5a229681-e59f-4773-a3eb-0d253a2c312a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375718511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2375718511
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1532338864
Short name T383
Test name
Test status
Simulation time 392745305948 ps
CPU time 143.11 seconds
Started Jun 13 12:49:40 PM PDT 24
Finished Jun 13 12:52:05 PM PDT 24
Peak memory 182960 kb
Host smart-89adcbf8-815c-4662-b007-e8702e44afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532338864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1532338864
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1767479639
Short name T139
Test name
Test status
Simulation time 192059601958 ps
CPU time 94.08 seconds
Started Jun 13 12:49:45 PM PDT 24
Finished Jun 13 12:51:20 PM PDT 24
Peak memory 182924 kb
Host smart-9e1cc8e5-02bd-4c61-b809-dd2598287a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767479639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1767479639
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2496665885
Short name T361
Test name
Test status
Simulation time 700900782285 ps
CPU time 423.53 seconds
Started Jun 13 12:49:43 PM PDT 24
Finished Jun 13 12:56:48 PM PDT 24
Peak memory 182972 kb
Host smart-8495277f-bca6-4d2a-85c6-49253e0a334f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496665885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2496665885
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1035367024
Short name T388
Test name
Test status
Simulation time 50480854316 ps
CPU time 74.34 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 12:51:17 PM PDT 24
Peak memory 182960 kb
Host smart-21b91e6c-84d8-41e9-9f9b-b954e3b5e7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035367024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1035367024
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2348095320
Short name T315
Test name
Test status
Simulation time 148431597741 ps
CPU time 623.62 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 01:00:26 PM PDT 24
Peak memory 190552 kb
Host smart-3ec7bd2e-4291-43e9-b298-c04f7434a535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348095320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2348095320
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.62577300
Short name T16
Test name
Test status
Simulation time 121231039 ps
CPU time 0.74 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 12:50:03 PM PDT 24
Peak memory 213428 kb
Host smart-e2284b84-667d-4897-8930-5b571af3b026
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62577300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.62577300
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3936884491
Short name T184
Test name
Test status
Simulation time 97594533211 ps
CPU time 452.67 seconds
Started Jun 13 12:49:46 PM PDT 24
Finished Jun 13 12:57:19 PM PDT 24
Peak memory 191168 kb
Host smart-40a59402-782a-4ea9-a6da-f84f6965d0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936884491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3936884491
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1028396580
Short name T2
Test name
Test status
Simulation time 305745339491 ps
CPU time 292.2 seconds
Started Jun 13 12:49:58 PM PDT 24
Finished Jun 13 12:54:53 PM PDT 24
Peak memory 182924 kb
Host smart-0e5d39e2-7782-4679-9d9b-ec8c3c3708ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028396580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1028396580
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3358497332
Short name T56
Test name
Test status
Simulation time 4269156703 ps
CPU time 6.45 seconds
Started Jun 13 12:49:58 PM PDT 24
Finished Jun 13 12:50:08 PM PDT 24
Peak memory 182780 kb
Host smart-05a14cb2-b3c1-489d-967e-1785fbd15e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358497332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3358497332
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2488851712
Short name T446
Test name
Test status
Simulation time 516270362866 ps
CPU time 231.76 seconds
Started Jun 13 12:50:01 PM PDT 24
Finished Jun 13 12:53:56 PM PDT 24
Peak memory 191188 kb
Host smart-33b9b977-5503-4c29-8279-5bf818e4b1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488851712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2488851712
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2717017360
Short name T60
Test name
Test status
Simulation time 134219409651 ps
CPU time 51.65 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 12:50:55 PM PDT 24
Peak memory 192940 kb
Host smart-f2679bae-8db0-439c-b5ce-cd9eff8695db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717017360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2717017360
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.2165207792
Short name T258
Test name
Test status
Simulation time 354094677315 ps
CPU time 295.63 seconds
Started Jun 13 12:53:20 PM PDT 24
Finished Jun 13 12:58:16 PM PDT 24
Peak memory 191156 kb
Host smart-0b88fe4b-9cbd-4030-8a80-25a82d55d9fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165207792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2165207792
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.4219748741
Short name T124
Test name
Test status
Simulation time 889910220646 ps
CPU time 295.27 seconds
Started Jun 13 12:53:18 PM PDT 24
Finished Jun 13 12:58:13 PM PDT 24
Peak memory 191152 kb
Host smart-9d58102d-dc6d-44f1-8743-f62a3566e9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219748741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.4219748741
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.863486034
Short name T178
Test name
Test status
Simulation time 86722501507 ps
CPU time 567.76 seconds
Started Jun 13 12:53:18 PM PDT 24
Finished Jun 13 01:02:47 PM PDT 24
Peak memory 191180 kb
Host smart-74ef4294-3a66-4641-9d54-afda7eb73fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863486034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.863486034
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2179083245
Short name T102
Test name
Test status
Simulation time 89922627724 ps
CPU time 151.22 seconds
Started Jun 13 12:53:18 PM PDT 24
Finished Jun 13 12:55:50 PM PDT 24
Peak memory 191152 kb
Host smart-56bf993a-e152-46d1-8054-d2ab7238c56b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179083245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2179083245
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.363005067
Short name T6
Test name
Test status
Simulation time 294732151993 ps
CPU time 583.12 seconds
Started Jun 13 12:53:26 PM PDT 24
Finished Jun 13 01:03:09 PM PDT 24
Peak memory 191148 kb
Host smart-e91a8457-4489-4d29-9314-b60725e72c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363005067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.363005067
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.230548397
Short name T323
Test name
Test status
Simulation time 117449404556 ps
CPU time 62.35 seconds
Started Jun 13 12:53:26 PM PDT 24
Finished Jun 13 12:54:29 PM PDT 24
Peak memory 182912 kb
Host smart-601820aa-34e5-4b7f-be86-db9ab34b2329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230548397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.230548397
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.921133789
Short name T289
Test name
Test status
Simulation time 979569955996 ps
CPU time 553.62 seconds
Started Jun 13 12:50:03 PM PDT 24
Finished Jun 13 12:59:20 PM PDT 24
Peak memory 182944 kb
Host smart-55a85940-935f-4d00-813a-d3d39b0fadd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921133789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.921133789
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2443153761
Short name T389
Test name
Test status
Simulation time 19244858370 ps
CPU time 25.61 seconds
Started Jun 13 12:49:58 PM PDT 24
Finished Jun 13 12:50:27 PM PDT 24
Peak memory 182920 kb
Host smart-1abe3d94-dff7-40b8-a03c-b64bef5f1100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443153761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2443153761
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.487341170
Short name T140
Test name
Test status
Simulation time 217006325388 ps
CPU time 1130.88 seconds
Started Jun 13 12:50:36 PM PDT 24
Finished Jun 13 01:09:27 PM PDT 24
Peak memory 190692 kb
Host smart-6282fec2-6881-4307-afb7-837caf9b5ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487341170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.487341170
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.1467114988
Short name T211
Test name
Test status
Simulation time 287480854554 ps
CPU time 98.9 seconds
Started Jun 13 12:53:29 PM PDT 24
Finished Jun 13 12:55:08 PM PDT 24
Peak memory 182964 kb
Host smart-abb0c382-89bf-4226-a284-166f73786d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467114988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1467114988
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4088411308
Short name T359
Test name
Test status
Simulation time 337484076213 ps
CPU time 175.96 seconds
Started Jun 13 12:53:32 PM PDT 24
Finished Jun 13 12:56:28 PM PDT 24
Peak memory 191120 kb
Host smart-0645d547-d398-4698-961c-31e258a5839f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088411308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4088411308
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1369311561
Short name T356
Test name
Test status
Simulation time 373152575459 ps
CPU time 564.34 seconds
Started Jun 13 12:53:43 PM PDT 24
Finished Jun 13 01:03:08 PM PDT 24
Peak memory 182960 kb
Host smart-04ac3bae-079c-4d3b-a7cf-5b634b9da2f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369311561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1369311561
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2124519981
Short name T318
Test name
Test status
Simulation time 155963093250 ps
CPU time 234.84 seconds
Started Jun 13 12:50:03 PM PDT 24
Finished Jun 13 12:54:01 PM PDT 24
Peak memory 182952 kb
Host smart-d2696a0d-123c-4897-88a3-4f92ad05b554
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124519981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2124519981
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.217476521
Short name T417
Test name
Test status
Simulation time 347878511093 ps
CPU time 280.36 seconds
Started Jun 13 12:50:02 PM PDT 24
Finished Jun 13 12:54:46 PM PDT 24
Peak memory 182960 kb
Host smart-70c5e04d-7037-4272-b4ad-6d1a7e51a66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217476521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.217476521
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3726093333
Short name T332
Test name
Test status
Simulation time 165817138425 ps
CPU time 78.53 seconds
Started Jun 13 12:50:02 PM PDT 24
Finished Jun 13 12:51:24 PM PDT 24
Peak memory 191184 kb
Host smart-ca6c2062-6a4f-4e40-8070-9746bba1d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726093333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3726093333
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3354149847
Short name T268
Test name
Test status
Simulation time 199766250030 ps
CPU time 187.18 seconds
Started Jun 13 12:53:40 PM PDT 24
Finished Jun 13 12:56:47 PM PDT 24
Peak memory 191168 kb
Host smart-1caf13c6-323d-4106-9823-fc749584b550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354149847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3354149847
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3902550152
Short name T343
Test name
Test status
Simulation time 155679752388 ps
CPU time 197.28 seconds
Started Jun 13 12:53:43 PM PDT 24
Finished Jun 13 12:57:01 PM PDT 24
Peak memory 191164 kb
Host smart-81012bcb-52b8-4322-8464-a23801ad9448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902550152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3902550152
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2255764477
Short name T114
Test name
Test status
Simulation time 237625422152 ps
CPU time 209.54 seconds
Started Jun 13 12:53:39 PM PDT 24
Finished Jun 13 12:57:09 PM PDT 24
Peak memory 191076 kb
Host smart-8797d8a1-79bb-47aa-86e2-55883b341e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255764477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2255764477
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.4059811350
Short name T141
Test name
Test status
Simulation time 106795569467 ps
CPU time 73.05 seconds
Started Jun 13 12:53:40 PM PDT 24
Finished Jun 13 12:54:53 PM PDT 24
Peak memory 191168 kb
Host smart-4ee84540-083c-4345-b24f-e0ea1bfa4432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059811350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4059811350
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.686601527
Short name T287
Test name
Test status
Simulation time 414353431096 ps
CPU time 182.16 seconds
Started Jun 13 12:53:39 PM PDT 24
Finished Jun 13 12:56:42 PM PDT 24
Peak memory 191116 kb
Host smart-a8ef5d4e-a781-4c0a-a064-c0f696879375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686601527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.686601527
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2653251844
Short name T133
Test name
Test status
Simulation time 437615597829 ps
CPU time 2141.49 seconds
Started Jun 13 12:53:49 PM PDT 24
Finished Jun 13 01:29:31 PM PDT 24
Peak memory 191144 kb
Host smart-a5ab45c2-2e47-4576-85c5-07cbb68a4b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653251844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2653251844
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2156984522
Short name T182
Test name
Test status
Simulation time 113566433923 ps
CPU time 690.28 seconds
Started Jun 13 12:53:46 PM PDT 24
Finished Jun 13 01:05:17 PM PDT 24
Peak memory 191164 kb
Host smart-3a5a7898-dfb5-48b7-a56d-0badb57df76b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156984522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2156984522
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3828260445
Short name T296
Test name
Test status
Simulation time 130914690926 ps
CPU time 207.09 seconds
Started Jun 13 12:53:47 PM PDT 24
Finished Jun 13 12:57:14 PM PDT 24
Peak memory 194364 kb
Host smart-e0fbbe9f-d5c2-4467-865c-65bcfa065a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828260445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3828260445
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.886287722
Short name T444
Test name
Test status
Simulation time 15993710284 ps
CPU time 124.88 seconds
Started Jun 13 12:53:47 PM PDT 24
Finished Jun 13 12:55:53 PM PDT 24
Peak memory 182956 kb
Host smart-9312cfec-d71b-4578-ae7c-51f3fb499d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886287722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.886287722
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1997152739
Short name T242
Test name
Test status
Simulation time 319167839382 ps
CPU time 503.08 seconds
Started Jun 13 12:53:47 PM PDT 24
Finished Jun 13 01:02:10 PM PDT 24
Peak memory 191156 kb
Host smart-51bfc286-90b1-410e-b1f5-c0cc78e7bfb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997152739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1997152739
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1536544646
Short name T357
Test name
Test status
Simulation time 295051363782 ps
CPU time 245.48 seconds
Started Jun 13 12:50:04 PM PDT 24
Finished Jun 13 12:54:13 PM PDT 24
Peak memory 182984 kb
Host smart-e46f1496-c519-4098-a720-071f607f4cb2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536544646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1536544646
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2668622441
Short name T408
Test name
Test status
Simulation time 301182656053 ps
CPU time 214.6 seconds
Started Jun 13 12:50:05 PM PDT 24
Finished Jun 13 12:53:43 PM PDT 24
Peak memory 182936 kb
Host smart-880de973-848d-4907-915e-612324d97133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668622441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2668622441
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.3664300734
Short name T164
Test name
Test status
Simulation time 309692530374 ps
CPU time 3074.56 seconds
Started Jun 13 12:50:03 PM PDT 24
Finished Jun 13 01:41:22 PM PDT 24
Peak memory 191156 kb
Host smart-37708519-ecbc-4e22-924f-b39d5c5a67a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664300734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3664300734
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3623812212
Short name T148
Test name
Test status
Simulation time 236647093557 ps
CPU time 182 seconds
Started Jun 13 12:50:04 PM PDT 24
Finished Jun 13 12:53:10 PM PDT 24
Peak memory 193504 kb
Host smart-315adcca-44f1-4f84-baf9-40aa32adca5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623812212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3623812212
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2157582551
Short name T326
Test name
Test status
Simulation time 168091626251 ps
CPU time 301.71 seconds
Started Jun 13 12:53:46 PM PDT 24
Finished Jun 13 12:58:49 PM PDT 24
Peak memory 191132 kb
Host smart-da95886a-129d-45e0-b24f-85d3a5f5464f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157582551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2157582551
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.597288672
Short name T334
Test name
Test status
Simulation time 8853044755 ps
CPU time 11.95 seconds
Started Jun 13 12:53:48 PM PDT 24
Finished Jun 13 12:54:00 PM PDT 24
Peak memory 183032 kb
Host smart-9c92612d-3cdc-4804-a424-44c7f9065ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597288672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.597288672
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3377696326
Short name T413
Test name
Test status
Simulation time 32640295823 ps
CPU time 589.29 seconds
Started Jun 13 12:54:01 PM PDT 24
Finished Jun 13 01:03:50 PM PDT 24
Peak memory 182964 kb
Host smart-7ac07a3e-8924-4f79-a445-b9dbf1837d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377696326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3377696326
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1446871898
Short name T355
Test name
Test status
Simulation time 11529350867 ps
CPU time 20.39 seconds
Started Jun 13 12:50:03 PM PDT 24
Finished Jun 13 12:50:27 PM PDT 24
Peak memory 182952 kb
Host smart-de5e3ef3-5318-426b-95a8-9883eb73d902
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446871898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1446871898
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2255609599
Short name T387
Test name
Test status
Simulation time 129156706042 ps
CPU time 88.13 seconds
Started Jun 13 12:50:06 PM PDT 24
Finished Jun 13 12:51:37 PM PDT 24
Peak memory 182860 kb
Host smart-2f564e3d-3133-4e05-9cf7-6c8c74e78191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255609599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2255609599
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2736956442
Short name T10
Test name
Test status
Simulation time 25120919011 ps
CPU time 39.97 seconds
Started Jun 13 12:50:04 PM PDT 24
Finished Jun 13 12:50:47 PM PDT 24
Peak memory 191048 kb
Host smart-f809da84-0b53-4008-8a26-823cbcce4d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736956442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2736956442
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.401284731
Short name T44
Test name
Test status
Simulation time 71513558536 ps
CPU time 518.74 seconds
Started Jun 13 12:50:10 PM PDT 24
Finished Jun 13 12:58:52 PM PDT 24
Peak memory 207828 kb
Host smart-2bdcff72-beea-468c-b271-55125d6e1671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401284731 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.401284731
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.326067629
Short name T127
Test name
Test status
Simulation time 856193922582 ps
CPU time 3178.15 seconds
Started Jun 13 12:53:59 PM PDT 24
Finished Jun 13 01:46:58 PM PDT 24
Peak memory 191168 kb
Host smart-df0a64c1-1d8f-41bc-9441-adabe36eed43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326067629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.326067629
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.4197293209
Short name T179
Test name
Test status
Simulation time 156468701385 ps
CPU time 241.66 seconds
Started Jun 13 12:53:53 PM PDT 24
Finished Jun 13 12:57:55 PM PDT 24
Peak memory 191168 kb
Host smart-b046bb39-0f97-4279-8c7f-2bfdb4841d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197293209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4197293209
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3233614692
Short name T125
Test name
Test status
Simulation time 146605935504 ps
CPU time 176.51 seconds
Started Jun 13 12:53:54 PM PDT 24
Finished Jun 13 12:56:51 PM PDT 24
Peak memory 191152 kb
Host smart-49685d08-1dc1-440d-9b32-288dd0709dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233614692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3233614692
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.172267922
Short name T251
Test name
Test status
Simulation time 110187118164 ps
CPU time 190.08 seconds
Started Jun 13 12:53:53 PM PDT 24
Finished Jun 13 12:57:03 PM PDT 24
Peak memory 191164 kb
Host smart-1be4d21b-0816-49f5-bfc5-69698c210aa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172267922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.172267922
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3588124002
Short name T25
Test name
Test status
Simulation time 590716028906 ps
CPU time 281.42 seconds
Started Jun 13 12:53:59 PM PDT 24
Finished Jun 13 12:58:41 PM PDT 24
Peak memory 191164 kb
Host smart-aedf56b8-0e65-43bf-b47d-25c79d9569a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588124002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3588124002
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2758233704
Short name T386
Test name
Test status
Simulation time 50740020366 ps
CPU time 76.18 seconds
Started Jun 13 12:50:08 PM PDT 24
Finished Jun 13 12:51:26 PM PDT 24
Peak memory 182816 kb
Host smart-12ed5049-ac04-4fdf-a128-6c64aa19788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758233704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2758233704
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3679791261
Short name T317
Test name
Test status
Simulation time 128667238395 ps
CPU time 212.78 seconds
Started Jun 13 12:50:11 PM PDT 24
Finished Jun 13 12:53:46 PM PDT 24
Peak memory 191112 kb
Host smart-c2abf35d-7f9d-43d9-a257-ed151393ba15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679791261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3679791261
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.468745514
Short name T104
Test name
Test status
Simulation time 80845395842 ps
CPU time 52.03 seconds
Started Jun 13 12:50:12 PM PDT 24
Finished Jun 13 12:51:06 PM PDT 24
Peak memory 182172 kb
Host smart-9b0b4f72-cc54-42ab-9f72-50a8a93ca4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468745514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.468745514
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3672704872
Short name T165
Test name
Test status
Simulation time 777629790099 ps
CPU time 1473.13 seconds
Started Jun 13 12:50:09 PM PDT 24
Finished Jun 13 01:14:44 PM PDT 24
Peak memory 191156 kb
Host smart-551cb650-c254-4c4a-bde1-c79516c98fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672704872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3672704872
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.562665646
Short name T448
Test name
Test status
Simulation time 111245080909 ps
CPU time 99.72 seconds
Started Jun 13 12:54:02 PM PDT 24
Finished Jun 13 12:55:42 PM PDT 24
Peak memory 191156 kb
Host smart-0febf13e-96f2-4bf5-a3c9-b1bd1328cfda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562665646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.562665646
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2610542099
Short name T321
Test name
Test status
Simulation time 43223188763 ps
CPU time 30.76 seconds
Started Jun 13 12:53:59 PM PDT 24
Finished Jun 13 12:54:30 PM PDT 24
Peak memory 182792 kb
Host smart-e090c4a3-5235-41e7-bfcd-68a47f33452f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610542099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2610542099
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.16887541
Short name T237
Test name
Test status
Simulation time 732156567730 ps
CPU time 609.45 seconds
Started Jun 13 12:54:14 PM PDT 24
Finished Jun 13 01:04:24 PM PDT 24
Peak memory 191168 kb
Host smart-b4f6f0f6-7264-4415-8830-1281c86c345a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16887541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.16887541
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3030329409
Short name T275
Test name
Test status
Simulation time 140503833943 ps
CPU time 240.9 seconds
Started Jun 13 12:54:02 PM PDT 24
Finished Jun 13 12:58:03 PM PDT 24
Peak memory 191160 kb
Host smart-d21c1bf2-c5ec-41e8-98fc-df883d0cb898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030329409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3030329409
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2784841444
Short name T348
Test name
Test status
Simulation time 781974152153 ps
CPU time 503.1 seconds
Started Jun 13 12:54:01 PM PDT 24
Finished Jun 13 01:02:25 PM PDT 24
Peak memory 191152 kb
Host smart-5b3d9af7-9f08-49f7-b09d-0a933f8c4983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784841444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2784841444
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1912695671
Short name T41
Test name
Test status
Simulation time 101809560460 ps
CPU time 112.25 seconds
Started Jun 13 12:54:07 PM PDT 24
Finished Jun 13 12:56:00 PM PDT 24
Peak memory 182912 kb
Host smart-1dae0e7d-e2d0-49ea-827e-125b983b4c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912695671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1912695671
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.4225387498
Short name T439
Test name
Test status
Simulation time 199923900757 ps
CPU time 303.46 seconds
Started Jun 13 12:50:10 PM PDT 24
Finished Jun 13 12:55:15 PM PDT 24
Peak memory 182912 kb
Host smart-ec741c3a-9789-4440-8c6c-8ae0aa8c6270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225387498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.4225387498
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3588460983
Short name T238
Test name
Test status
Simulation time 692980332656 ps
CPU time 644.95 seconds
Started Jun 13 12:50:10 PM PDT 24
Finished Jun 13 01:00:57 PM PDT 24
Peak memory 191172 kb
Host smart-e62dd3ce-864b-4fc1-afba-c7b92ac5fb69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588460983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3588460983
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1657078927
Short name T443
Test name
Test status
Simulation time 100037723 ps
CPU time 0.58 seconds
Started Jun 13 12:50:12 PM PDT 24
Finished Jun 13 12:50:14 PM PDT 24
Peak memory 182756 kb
Host smart-946efcec-8d33-43c0-87ca-0c05b6b7e9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657078927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1657078927
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1766198501
Short name T394
Test name
Test status
Simulation time 67707120931 ps
CPU time 47.27 seconds
Started Jun 13 12:50:14 PM PDT 24
Finished Jun 13 12:51:03 PM PDT 24
Peak memory 194636 kb
Host smart-9bbfc3eb-1edc-4221-ae6a-f3b47dcf6e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766198501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1766198501
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.4256963658
Short name T303
Test name
Test status
Simulation time 177811900476 ps
CPU time 364.42 seconds
Started Jun 13 12:54:08 PM PDT 24
Finished Jun 13 01:00:13 PM PDT 24
Peak memory 182952 kb
Host smart-6d4bb315-5fc3-47ca-9ff8-d8a1dbd8386f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256963658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4256963658
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.797444392
Short name T272
Test name
Test status
Simulation time 1264333190366 ps
CPU time 213.26 seconds
Started Jun 13 12:54:07 PM PDT 24
Finished Jun 13 12:57:41 PM PDT 24
Peak memory 191184 kb
Host smart-4091f0da-df35-4cfd-8a60-51969788e4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797444392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.797444392
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2873384311
Short name T122
Test name
Test status
Simulation time 85113407587 ps
CPU time 134.41 seconds
Started Jun 13 12:54:09 PM PDT 24
Finished Jun 13 12:56:23 PM PDT 24
Peak memory 191068 kb
Host smart-648fec47-43d5-40f2-9cc9-a52d5eac9540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873384311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2873384311
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.425495120
Short name T206
Test name
Test status
Simulation time 439038613940 ps
CPU time 302.99 seconds
Started Jun 13 12:54:09 PM PDT 24
Finished Jun 13 12:59:12 PM PDT 24
Peak memory 191120 kb
Host smart-5ea6a018-9020-428e-b7ea-df4d721f23b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425495120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.425495120
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.628164374
Short name T426
Test name
Test status
Simulation time 137549961667 ps
CPU time 74.26 seconds
Started Jun 13 12:54:06 PM PDT 24
Finished Jun 13 12:55:21 PM PDT 24
Peak memory 182924 kb
Host smart-c0c64626-27f4-4bb3-b873-fd501d7b9a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628164374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.628164374
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1405694379
Short name T346
Test name
Test status
Simulation time 170166421525 ps
CPU time 1930.49 seconds
Started Jun 13 12:54:18 PM PDT 24
Finished Jun 13 01:26:29 PM PDT 24
Peak memory 182952 kb
Host smart-90029a4c-45ff-44a3-b249-4db8bc483f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405694379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1405694379
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4267884574
Short name T202
Test name
Test status
Simulation time 175526662897 ps
CPU time 69.04 seconds
Started Jun 13 12:54:15 PM PDT 24
Finished Jun 13 12:55:25 PM PDT 24
Peak memory 191184 kb
Host smart-011f3c07-68a1-4a3a-b2f1-db284073cc46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267884574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4267884574
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.109676566
Short name T273
Test name
Test status
Simulation time 236211685936 ps
CPU time 208.7 seconds
Started Jun 13 12:54:15 PM PDT 24
Finished Jun 13 12:57:44 PM PDT 24
Peak memory 191064 kb
Host smart-ee2324c1-5f47-4128-823e-b89438047581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109676566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.109676566
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.919811923
Short name T377
Test name
Test status
Simulation time 161719208995 ps
CPU time 246.36 seconds
Started Jun 13 12:50:11 PM PDT 24
Finished Jun 13 12:54:20 PM PDT 24
Peak memory 182916 kb
Host smart-4a77b8ef-fa50-449b-8939-66cf2831e4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919811923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.919811923
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1922717200
Short name T257
Test name
Test status
Simulation time 491934917821 ps
CPU time 826.15 seconds
Started Jun 13 12:50:09 PM PDT 24
Finished Jun 13 01:03:57 PM PDT 24
Peak memory 191172 kb
Host smart-f1a2ccd5-8e35-4c5c-aecd-55964ee14c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922717200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1922717200
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2067121115
Short name T391
Test name
Test status
Simulation time 407936363919 ps
CPU time 131.1 seconds
Started Jun 13 12:50:14 PM PDT 24
Finished Jun 13 12:52:27 PM PDT 24
Peak memory 194744 kb
Host smart-fcafe9ea-6f1e-4a9e-971c-172be644d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067121115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2067121115
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2272360539
Short name T402
Test name
Test status
Simulation time 94073334 ps
CPU time 0.59 seconds
Started Jun 13 12:50:09 PM PDT 24
Finished Jun 13 12:50:11 PM PDT 24
Peak memory 182680 kb
Host smart-2a01fab4-09fd-47e1-be86-f72949235586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272360539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2272360539
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.259864690
Short name T438
Test name
Test status
Simulation time 176352783691 ps
CPU time 662.38 seconds
Started Jun 13 12:54:15 PM PDT 24
Finished Jun 13 01:05:18 PM PDT 24
Peak memory 182880 kb
Host smart-ba266837-32b7-4ee5-b4e8-c8b8d7563bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259864690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.259864690
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2451922098
Short name T347
Test name
Test status
Simulation time 25230764439 ps
CPU time 44.07 seconds
Started Jun 13 12:54:13 PM PDT 24
Finished Jun 13 12:54:58 PM PDT 24
Peak memory 182908 kb
Host smart-14e37b3b-4901-440c-a8a6-b013facfca9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451922098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2451922098
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3814589014
Short name T442
Test name
Test status
Simulation time 43359093349 ps
CPU time 68.79 seconds
Started Jun 13 12:54:15 PM PDT 24
Finished Jun 13 12:55:25 PM PDT 24
Peak memory 191112 kb
Host smart-9a6daccf-52b0-453e-b0c4-40b25bef2054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814589014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3814589014
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2015384131
Short name T337
Test name
Test status
Simulation time 72513482137 ps
CPU time 2000.21 seconds
Started Jun 13 12:54:21 PM PDT 24
Finished Jun 13 01:27:42 PM PDT 24
Peak memory 191156 kb
Host smart-0dce1101-aa88-4db3-b485-aa263b9fc563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015384131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2015384131
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2476729042
Short name T220
Test name
Test status
Simulation time 90623980452 ps
CPU time 42.3 seconds
Started Jun 13 12:54:23 PM PDT 24
Finished Jun 13 12:55:06 PM PDT 24
Peak memory 182868 kb
Host smart-e96926c5-f9d1-47db-aeb1-4a72a713c8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476729042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2476729042
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1583263150
Short name T247
Test name
Test status
Simulation time 110117813024 ps
CPU time 374.75 seconds
Started Jun 13 12:54:22 PM PDT 24
Finished Jun 13 01:00:38 PM PDT 24
Peak memory 191160 kb
Host smart-c2f711ee-11da-433f-9f4a-36c22a070b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583263150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1583263150
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.876852868
Short name T74
Test name
Test status
Simulation time 213884107476 ps
CPU time 337.18 seconds
Started Jun 13 12:50:09 PM PDT 24
Finished Jun 13 12:55:49 PM PDT 24
Peak memory 182956 kb
Host smart-a2a10130-4fb5-4336-a441-8db50e203178
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876852868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.876852868
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2553949807
Short name T364
Test name
Test status
Simulation time 321924120334 ps
CPU time 81.58 seconds
Started Jun 13 12:50:11 PM PDT 24
Finished Jun 13 12:51:35 PM PDT 24
Peak memory 182904 kb
Host smart-fe880d0d-5a07-4021-92bb-859d0d3bd10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553949807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2553949807
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3473261468
Short name T261
Test name
Test status
Simulation time 122529352032 ps
CPU time 71.85 seconds
Started Jun 13 12:50:10 PM PDT 24
Finished Jun 13 12:51:25 PM PDT 24
Peak memory 191168 kb
Host smart-135f1ba6-3575-4211-9d8f-8ac490183ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473261468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3473261468
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.662812664
Short name T434
Test name
Test status
Simulation time 701072723701 ps
CPU time 253.03 seconds
Started Jun 13 12:50:10 PM PDT 24
Finished Jun 13 12:54:26 PM PDT 24
Peak memory 182992 kb
Host smart-2789dec3-df45-40db-bbf6-c59a12104a44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662812664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.
662812664
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.2202913792
Short name T320
Test name
Test status
Simulation time 34763523190 ps
CPU time 52.07 seconds
Started Jun 13 12:54:23 PM PDT 24
Finished Jun 13 12:55:16 PM PDT 24
Peak memory 191112 kb
Host smart-27cc52b4-e486-4766-93bd-826f0c8b0d44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202913792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2202913792
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3698450842
Short name T445
Test name
Test status
Simulation time 52520146900 ps
CPU time 85.65 seconds
Started Jun 13 12:54:22 PM PDT 24
Finished Jun 13 12:55:49 PM PDT 24
Peak memory 191176 kb
Host smart-17469328-c892-4a9e-9d77-815a83f97703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698450842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3698450842
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1876669858
Short name T197
Test name
Test status
Simulation time 622230325633 ps
CPU time 946.62 seconds
Started Jun 13 12:54:28 PM PDT 24
Finished Jun 13 01:10:16 PM PDT 24
Peak memory 193500 kb
Host smart-8013093a-74c1-4e48-8b6a-a6563a78e398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876669858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1876669858
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1089227480
Short name T350
Test name
Test status
Simulation time 701710091597 ps
CPU time 145.04 seconds
Started Jun 13 12:54:28 PM PDT 24
Finished Jun 13 12:56:54 PM PDT 24
Peak memory 191148 kb
Host smart-7eed8876-5593-44db-8fe2-d30cd5189d69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089227480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1089227480
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1139267959
Short name T222
Test name
Test status
Simulation time 234704534075 ps
CPU time 160.94 seconds
Started Jun 13 12:54:29 PM PDT 24
Finished Jun 13 12:57:11 PM PDT 24
Peak memory 191108 kb
Host smart-d3af71a5-38d1-4f6c-9b39-0f6c9f697b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139267959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1139267959
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1792153121
Short name T369
Test name
Test status
Simulation time 278083644072 ps
CPU time 176.14 seconds
Started Jun 13 12:50:16 PM PDT 24
Finished Jun 13 12:53:13 PM PDT 24
Peak memory 182960 kb
Host smart-735e9410-464e-495d-b6ac-0f9d28f2adfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792153121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1792153121
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1691420301
Short name T285
Test name
Test status
Simulation time 52221618687 ps
CPU time 37.51 seconds
Started Jun 13 12:50:17 PM PDT 24
Finished Jun 13 12:50:56 PM PDT 24
Peak memory 182932 kb
Host smart-14a299b5-903b-4c5f-9367-79a3c71c9e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691420301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1691420301
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1889835520
Short name T143
Test name
Test status
Simulation time 270420959972 ps
CPU time 421.71 seconds
Started Jun 13 12:50:17 PM PDT 24
Finished Jun 13 12:57:21 PM PDT 24
Peak memory 194804 kb
Host smart-50099eb1-f6c5-4ac4-8598-0a2d9cd82720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889835520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1889835520
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.3123509856
Short name T213
Test name
Test status
Simulation time 173321143208 ps
CPU time 551.46 seconds
Started Jun 13 12:54:35 PM PDT 24
Finished Jun 13 01:03:47 PM PDT 24
Peak memory 191076 kb
Host smart-c9ff1b52-ee7f-4c71-8905-c2dd1cb66942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123509856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3123509856
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3270555110
Short name T134
Test name
Test status
Simulation time 190171549011 ps
CPU time 93.62 seconds
Started Jun 13 12:54:36 PM PDT 24
Finished Jun 13 12:56:11 PM PDT 24
Peak memory 182868 kb
Host smart-9f2314b6-2a6e-4c3f-b2d9-7943117d43c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270555110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3270555110
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.657178852
Short name T330
Test name
Test status
Simulation time 75564752619 ps
CPU time 125 seconds
Started Jun 13 12:54:39 PM PDT 24
Finished Jun 13 12:56:44 PM PDT 24
Peak memory 191176 kb
Host smart-02b014dc-afbe-4a2a-a657-8a6add98a8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657178852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.657178852
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.570720746
Short name T227
Test name
Test status
Simulation time 354633010429 ps
CPU time 419.2 seconds
Started Jun 13 12:54:42 PM PDT 24
Finished Jun 13 01:01:41 PM PDT 24
Peak memory 191080 kb
Host smart-63540db9-92bc-43bb-a5b4-3dab0979de57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570720746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.570720746
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.4147747488
Short name T166
Test name
Test status
Simulation time 399334013093 ps
CPU time 99.31 seconds
Started Jun 13 12:54:45 PM PDT 24
Finished Jun 13 12:56:25 PM PDT 24
Peak memory 193468 kb
Host smart-cba26699-4ee6-4717-aa54-883c694ffbf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147747488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4147747488
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2223112221
Short name T73
Test name
Test status
Simulation time 394012033875 ps
CPU time 300.36 seconds
Started Jun 13 12:54:42 PM PDT 24
Finished Jun 13 12:59:43 PM PDT 24
Peak memory 191016 kb
Host smart-8360394b-4033-400c-b575-4d4fdfdcb1e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223112221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2223112221
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3651158675
Short name T130
Test name
Test status
Simulation time 528339029723 ps
CPU time 244.09 seconds
Started Jun 13 12:54:41 PM PDT 24
Finished Jun 13 12:58:45 PM PDT 24
Peak memory 191172 kb
Host smart-9afcd0d3-692d-4b51-baca-0890e2904bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651158675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3651158675
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2064377513
Short name T246
Test name
Test status
Simulation time 92378111792 ps
CPU time 143.35 seconds
Started Jun 13 12:49:45 PM PDT 24
Finished Jun 13 12:52:10 PM PDT 24
Peak memory 182948 kb
Host smart-40168528-6641-4502-99ab-2daff6464050
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064377513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2064377513
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3246735183
Short name T362
Test name
Test status
Simulation time 50579452930 ps
CPU time 78.72 seconds
Started Jun 13 12:49:58 PM PDT 24
Finished Jun 13 12:51:21 PM PDT 24
Peak memory 182960 kb
Host smart-96a2fa10-97d4-474f-85d9-485b29dbf177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246735183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3246735183
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3968744340
Short name T280
Test name
Test status
Simulation time 67490984679 ps
CPU time 54.55 seconds
Started Jun 13 12:49:46 PM PDT 24
Finished Jun 13 12:50:42 PM PDT 24
Peak memory 182772 kb
Host smart-a956970b-7ca4-440f-90b1-979bc24a997e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968744340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3968744340
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4202976333
Short name T14
Test name
Test status
Simulation time 119021437 ps
CPU time 0.9 seconds
Started Jun 13 12:49:46 PM PDT 24
Finished Jun 13 12:49:48 PM PDT 24
Peak memory 213168 kb
Host smart-75f29ee0-56c0-40b3-bd96-472c3224010d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202976333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4202976333
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.81840472
Short name T42
Test name
Test status
Simulation time 1789657809897 ps
CPU time 549.86 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 12:59:12 PM PDT 24
Peak memory 191152 kb
Host smart-ceade125-0621-4cea-9ee2-1848b52dd808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81840472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.81840472
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.4135664746
Short name T128
Test name
Test status
Simulation time 190011037792 ps
CPU time 308.27 seconds
Started Jun 13 12:50:18 PM PDT 24
Finished Jun 13 12:55:28 PM PDT 24
Peak memory 182948 kb
Host smart-72812df5-6001-465c-bbc6-5f6e855ecd50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135664746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.4135664746
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4266247673
Short name T366
Test name
Test status
Simulation time 329917874219 ps
CPU time 218.01 seconds
Started Jun 13 12:50:18 PM PDT 24
Finished Jun 13 12:53:58 PM PDT 24
Peak memory 182964 kb
Host smart-fc207f08-f757-400f-9c6e-2b58ab4d2a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266247673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4266247673
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1843862593
Short name T427
Test name
Test status
Simulation time 60777830147 ps
CPU time 78.84 seconds
Started Jun 13 12:50:17 PM PDT 24
Finished Jun 13 12:51:37 PM PDT 24
Peak memory 182980 kb
Host smart-f537caa9-b1d1-479c-9eff-6f76dd957d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843862593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1843862593
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3722491534
Short name T39
Test name
Test status
Simulation time 132205771954 ps
CPU time 274.85 seconds
Started Jun 13 12:50:18 PM PDT 24
Finished Jun 13 12:54:55 PM PDT 24
Peak memory 205868 kb
Host smart-f98eb6ae-579d-4282-8d5a-b0b5ca0c6be7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722491534 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3722491534
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1800917475
Short name T300
Test name
Test status
Simulation time 686229853924 ps
CPU time 619.87 seconds
Started Jun 13 12:50:17 PM PDT 24
Finished Jun 13 01:00:39 PM PDT 24
Peak memory 182952 kb
Host smart-d78b1c23-c353-48b5-857e-858c1ca61349
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800917475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1800917475
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2898224336
Short name T385
Test name
Test status
Simulation time 113363512109 ps
CPU time 167.35 seconds
Started Jun 13 12:50:19 PM PDT 24
Finished Jun 13 12:53:07 PM PDT 24
Peak memory 182944 kb
Host smart-acb95c7c-1113-43cc-bcaa-a3dab972776e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898224336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2898224336
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2684596618
Short name T313
Test name
Test status
Simulation time 81360926422 ps
CPU time 34.83 seconds
Started Jun 13 12:50:17 PM PDT 24
Finished Jun 13 12:50:54 PM PDT 24
Peak memory 191148 kb
Host smart-a978c65e-b42f-481e-a57f-79a02dd7b608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684596618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2684596618
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2214546723
Short name T373
Test name
Test status
Simulation time 155077707160 ps
CPU time 106.67 seconds
Started Jun 13 12:50:16 PM PDT 24
Finished Jun 13 12:52:04 PM PDT 24
Peak memory 182952 kb
Host smart-79a6e3e3-03ba-49a1-a4de-558eecad669d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214546723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2214546723
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1886048189
Short name T218
Test name
Test status
Simulation time 309957698898 ps
CPU time 457.31 seconds
Started Jun 13 12:50:16 PM PDT 24
Finished Jun 13 12:57:55 PM PDT 24
Peak memory 182948 kb
Host smart-09b63ee1-be55-4e48-8819-c18ffbc170a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886048189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1886048189
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.4187288595
Short name T20
Test name
Test status
Simulation time 783687396718 ps
CPU time 174.57 seconds
Started Jun 13 12:50:15 PM PDT 24
Finished Jun 13 12:53:12 PM PDT 24
Peak memory 182960 kb
Host smart-83b9904f-9969-4d5a-a69f-7b7c7c2a64b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187288595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.4187288595
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1466723605
Short name T363
Test name
Test status
Simulation time 385281200 ps
CPU time 1.02 seconds
Started Jun 13 12:50:14 PM PDT 24
Finished Jun 13 12:50:17 PM PDT 24
Peak memory 192648 kb
Host smart-a2bcb3a7-0c35-49d4-ac47-e76d2a7487cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466723605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1466723605
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2621141406
Short name T284
Test name
Test status
Simulation time 1036355127451 ps
CPU time 1156.34 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 01:09:41 PM PDT 24
Peak memory 195312 kb
Host smart-4cf391e8-2b69-4004-963f-39cf35b69a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621141406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2621141406
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4241315375
Short name T142
Test name
Test status
Simulation time 531046533158 ps
CPU time 200.92 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 12:53:45 PM PDT 24
Peak memory 182952 kb
Host smart-f041f6ec-a5be-4f70-a264-d748b6bcc053
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241315375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4241315375
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2294068752
Short name T428
Test name
Test status
Simulation time 350132639461 ps
CPU time 110.79 seconds
Started Jun 13 12:50:22 PM PDT 24
Finished Jun 13 12:52:14 PM PDT 24
Peak memory 182952 kb
Host smart-2ab0d976-b752-4693-a96c-bb7c7dd86f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294068752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2294068752
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1462554123
Short name T171
Test name
Test status
Simulation time 275130979981 ps
CPU time 861.95 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 01:04:47 PM PDT 24
Peak memory 191176 kb
Host smart-a1e69eaf-6b4a-4e4b-b99a-ba32310000e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462554123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1462554123
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2479548856
Short name T36
Test name
Test status
Simulation time 30391597161 ps
CPU time 330.48 seconds
Started Jun 13 12:50:22 PM PDT 24
Finished Jun 13 12:55:53 PM PDT 24
Peak memory 197648 kb
Host smart-9b686a0d-4f69-4877-83de-c8c2a74a2437
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479548856 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2479548856
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3043508650
Short name T52
Test name
Test status
Simulation time 1410185809483 ps
CPU time 1049.05 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 01:07:54 PM PDT 24
Peak memory 182920 kb
Host smart-fd9872d5-14bc-49a3-8cd6-5417dbaabde7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043508650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3043508650
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.359252464
Short name T392
Test name
Test status
Simulation time 62103966148 ps
CPU time 85.06 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 12:51:49 PM PDT 24
Peak memory 182920 kb
Host smart-a67a8ba8-f7c6-4cb7-a062-19c280a62a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359252464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.359252464
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.286382180
Short name T301
Test name
Test status
Simulation time 37953889941 ps
CPU time 295.21 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 12:55:19 PM PDT 24
Peak memory 182840 kb
Host smart-63c9d85b-8126-47a2-92fe-a88936693f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286382180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.286382180
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.497291635
Short name T55
Test name
Test status
Simulation time 44475595966 ps
CPU time 81.02 seconds
Started Jun 13 12:50:22 PM PDT 24
Finished Jun 13 12:51:44 PM PDT 24
Peak memory 195500 kb
Host smart-78f05351-18bc-4f1c-9d1c-d68c97d7f68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497291635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.497291635
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2597964952
Short name T340
Test name
Test status
Simulation time 22685203478 ps
CPU time 18.84 seconds
Started Jun 13 12:50:25 PM PDT 24
Finished Jun 13 12:50:44 PM PDT 24
Peak memory 182948 kb
Host smart-ac9fa80e-d92c-4bcb-8800-ba99fa95fc39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597964952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2597964952
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.2847744976
Short name T163
Test name
Test status
Simulation time 296365696932 ps
CPU time 811.7 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 01:03:56 PM PDT 24
Peak memory 191152 kb
Host smart-b1ac88a8-57b0-43dd-8475-e5ef38feb6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847744976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2847744976
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2343079318
Short name T19
Test name
Test status
Simulation time 115934105 ps
CPU time 1.18 seconds
Started Jun 13 12:50:22 PM PDT 24
Finished Jun 13 12:50:24 PM PDT 24
Peak memory 182912 kb
Host smart-a40c688a-f91c-4e1a-aad1-c8748e1c92e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343079318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2343079318
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1354979559
Short name T381
Test name
Test status
Simulation time 1001259051143 ps
CPU time 176.68 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 12:53:20 PM PDT 24
Peak memory 194488 kb
Host smart-3eab0cdb-3191-47e9-a36d-0c31a565e671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354979559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1354979559
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2586896048
Short name T239
Test name
Test status
Simulation time 234442145195 ps
CPU time 139 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 12:52:42 PM PDT 24
Peak memory 182972 kb
Host smart-78a97dc4-1503-4dfc-ba63-c1601a3412fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586896048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2586896048
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.13259752
Short name T376
Test name
Test status
Simulation time 219475937154 ps
CPU time 230.88 seconds
Started Jun 13 12:50:22 PM PDT 24
Finished Jun 13 12:54:13 PM PDT 24
Peak memory 182916 kb
Host smart-acc958e2-fcb8-429d-8d46-65aecfb3559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13259752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.13259752
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3473040206
Short name T137
Test name
Test status
Simulation time 1948732178090 ps
CPU time 1216.68 seconds
Started Jun 13 12:50:22 PM PDT 24
Finished Jun 13 01:10:40 PM PDT 24
Peak memory 191080 kb
Host smart-43df2820-dadb-49cf-9d32-6e336e60c89b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473040206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3473040206
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2880479562
Short name T67
Test name
Test status
Simulation time 27111343620 ps
CPU time 545.58 seconds
Started Jun 13 12:50:23 PM PDT 24
Finished Jun 13 12:59:29 PM PDT 24
Peak memory 182900 kb
Host smart-faa71130-0262-4eba-83f2-5c6ad7f81adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880479562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2880479562
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3172880739
Short name T429
Test name
Test status
Simulation time 814917257107 ps
CPU time 309.95 seconds
Started Jun 13 12:50:30 PM PDT 24
Finished Jun 13 12:55:42 PM PDT 24
Peak memory 182964 kb
Host smart-fe19746a-f610-48b1-8222-b0b296e70024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172880739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3172880739
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.49955465
Short name T35
Test name
Test status
Simulation time 152696986574 ps
CPU time 426.86 seconds
Started Jun 13 12:50:24 PM PDT 24
Finished Jun 13 12:57:32 PM PDT 24
Peak memory 205904 kb
Host smart-cc1ec88e-c262-4106-9c2d-37b7b4fbf1b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49955465 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.49955465
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.693270333
Short name T368
Test name
Test status
Simulation time 150329432836 ps
CPU time 211.59 seconds
Started Jun 13 12:50:29 PM PDT 24
Finished Jun 13 12:54:02 PM PDT 24
Peak memory 182940 kb
Host smart-58aa267d-2169-4c3a-91bc-d52c6cd5f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693270333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.693270333
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1856326257
Short name T399
Test name
Test status
Simulation time 15546798118 ps
CPU time 6.98 seconds
Started Jun 13 12:50:29 PM PDT 24
Finished Jun 13 12:50:38 PM PDT 24
Peak memory 191180 kb
Host smart-d3dcfebb-6a61-46d8-b87d-ce5d0ef83107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856326257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1856326257
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2911330790
Short name T393
Test name
Test status
Simulation time 125926906198 ps
CPU time 92.83 seconds
Started Jun 13 12:50:39 PM PDT 24
Finished Jun 13 12:52:12 PM PDT 24
Peak memory 182968 kb
Host smart-fe331f7a-e697-44e1-ba96-154b390264f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911330790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2911330790
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3333857621
Short name T380
Test name
Test status
Simulation time 593805680123 ps
CPU time 157.58 seconds
Started Jun 13 12:50:37 PM PDT 24
Finished Jun 13 12:53:15 PM PDT 24
Peak memory 182916 kb
Host smart-5bf1c7ab-a295-47a9-bd46-e1324b01bdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333857621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3333857621
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3676713819
Short name T93
Test name
Test status
Simulation time 10572388422 ps
CPU time 16.86 seconds
Started Jun 13 12:50:42 PM PDT 24
Finished Jun 13 12:51:00 PM PDT 24
Peak memory 182976 kb
Host smart-7eff7219-9e1e-4fee-9775-e5ff4eeab33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676713819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3676713819
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4065308921
Short name T421
Test name
Test status
Simulation time 175862617300 ps
CPU time 189.01 seconds
Started Jun 13 12:50:41 PM PDT 24
Finished Jun 13 12:53:51 PM PDT 24
Peak memory 191176 kb
Host smart-c692fec5-82b0-4787-8601-69ea20abc40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065308921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4065308921
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.88153171
Short name T249
Test name
Test status
Simulation time 268580148386 ps
CPU time 424.12 seconds
Started Jun 13 12:50:43 PM PDT 24
Finished Jun 13 12:57:47 PM PDT 24
Peak memory 182960 kb
Host smart-60a453f2-1dcd-4094-9b11-8266782c1230
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88153171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.rv_timer_cfg_update_on_fly.88153171
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1719022500
Short name T435
Test name
Test status
Simulation time 136426439512 ps
CPU time 198.29 seconds
Started Jun 13 12:50:43 PM PDT 24
Finished Jun 13 12:54:02 PM PDT 24
Peak memory 182952 kb
Host smart-956e4282-3cd7-4502-b0eb-47901cbe6ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719022500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1719022500
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3045042142
Short name T293
Test name
Test status
Simulation time 514213045391 ps
CPU time 115.08 seconds
Started Jun 13 12:50:41 PM PDT 24
Finished Jun 13 12:52:37 PM PDT 24
Peak memory 182968 kb
Host smart-b79d96a7-a2b0-4aff-b581-f2a002d97c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045042142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3045042142
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1147887764
Short name T26
Test name
Test status
Simulation time 82354636108 ps
CPU time 28.05 seconds
Started Jun 13 12:50:50 PM PDT 24
Finished Jun 13 12:51:19 PM PDT 24
Peak memory 182912 kb
Host smart-59540176-0037-4a76-bcb7-f8722c141b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147887764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1147887764
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1538270909
Short name T415
Test name
Test status
Simulation time 197177522468 ps
CPU time 81.08 seconds
Started Jun 13 12:49:44 PM PDT 24
Finished Jun 13 12:51:06 PM PDT 24
Peak memory 182952 kb
Host smart-111b83c7-7670-40be-b39c-558262c6657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538270909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1538270909
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.681512455
Short name T314
Test name
Test status
Simulation time 995018112 ps
CPU time 1.24 seconds
Started Jun 13 12:49:46 PM PDT 24
Finished Jun 13 12:49:48 PM PDT 24
Peak memory 182708 kb
Host smart-a7283625-b111-4b62-96f9-46147434851c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681512455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.681512455
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1201421578
Short name T312
Test name
Test status
Simulation time 993326083 ps
CPU time 0.99 seconds
Started Jun 13 12:49:58 PM PDT 24
Finished Jun 13 12:50:03 PM PDT 24
Peak memory 192724 kb
Host smart-a94888bd-74ee-410d-8109-14929e33775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201421578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1201421578
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3971636673
Short name T13
Test name
Test status
Simulation time 212010547 ps
CPU time 0.8 seconds
Started Jun 13 12:49:44 PM PDT 24
Finished Jun 13 12:49:46 PM PDT 24
Peak memory 213772 kb
Host smart-44f75b4e-4952-4ae2-8516-463aa253e0f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971636673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3971636673
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.467770307
Short name T57
Test name
Test status
Simulation time 5870342338 ps
CPU time 5.3 seconds
Started Jun 13 12:50:50 PM PDT 24
Finished Jun 13 12:50:56 PM PDT 24
Peak memory 182972 kb
Host smart-41e648bf-0fcf-48ff-8cdb-da7b1e8b9d89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467770307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.467770307
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1249107608
Short name T367
Test name
Test status
Simulation time 101347034448 ps
CPU time 156.95 seconds
Started Jun 13 12:50:49 PM PDT 24
Finished Jun 13 12:53:27 PM PDT 24
Peak memory 182908 kb
Host smart-23312219-6a55-40ea-bedc-e062a5e07712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249107608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1249107608
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.311417482
Short name T267
Test name
Test status
Simulation time 310788304229 ps
CPU time 634.61 seconds
Started Jun 13 12:50:48 PM PDT 24
Finished Jun 13 01:01:24 PM PDT 24
Peak memory 194232 kb
Host smart-2c6596dd-45c8-4137-ad23-26eb4855a550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311417482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.311417482
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2239926383
Short name T297
Test name
Test status
Simulation time 51429221420 ps
CPU time 66.41 seconds
Started Jun 13 12:50:53 PM PDT 24
Finished Jun 13 12:52:00 PM PDT 24
Peak memory 193796 kb
Host smart-caec6e80-6c5e-4529-b93d-bf66f7911856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239926383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2239926383
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2735403071
Short name T262
Test name
Test status
Simulation time 11583506315 ps
CPU time 18.71 seconds
Started Jun 13 12:51:02 PM PDT 24
Finished Jun 13 12:51:21 PM PDT 24
Peak memory 182944 kb
Host smart-e5c80e6c-8503-4f68-a6b0-1679b6eb3008
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735403071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2735403071
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.812947578
Short name T401
Test name
Test status
Simulation time 494313756474 ps
CPU time 192.3 seconds
Started Jun 13 12:50:55 PM PDT 24
Finished Jun 13 12:54:08 PM PDT 24
Peak memory 182952 kb
Host smart-c4b584eb-d77f-4782-b33d-54d8a3b774c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812947578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.812947578
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.798235897
Short name T201
Test name
Test status
Simulation time 97198099083 ps
CPU time 322.76 seconds
Started Jun 13 12:50:55 PM PDT 24
Finished Jun 13 12:56:18 PM PDT 24
Peak memory 182956 kb
Host smart-4fb46ee7-2d3f-4502-8385-9e4db96015e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798235897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.798235897
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2272724115
Short name T406
Test name
Test status
Simulation time 117026757 ps
CPU time 0.62 seconds
Started Jun 13 12:51:03 PM PDT 24
Finished Jun 13 12:51:03 PM PDT 24
Peak memory 182716 kb
Host smart-5a5178e2-1ec3-4d17-972d-e9385e832b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272724115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2272724115
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2833422000
Short name T441
Test name
Test status
Simulation time 87409903 ps
CPU time 0.62 seconds
Started Jun 13 12:51:10 PM PDT 24
Finished Jun 13 12:51:11 PM PDT 24
Peak memory 182716 kb
Host smart-06135c9c-a4ed-4c12-87f0-97578546cf20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833422000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2833422000
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3887167064
Short name T183
Test name
Test status
Simulation time 300591372902 ps
CPU time 211.29 seconds
Started Jun 13 12:51:09 PM PDT 24
Finished Jun 13 12:54:40 PM PDT 24
Peak memory 182964 kb
Host smart-2bdf46a4-a364-42c2-8279-84518a4e5ee1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887167064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3887167064
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1244606036
Short name T390
Test name
Test status
Simulation time 70533440655 ps
CPU time 93.04 seconds
Started Jun 13 12:51:07 PM PDT 24
Finished Jun 13 12:52:41 PM PDT 24
Peak memory 182972 kb
Host smart-3473600f-933b-4065-a2a6-602dcefe4641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244606036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1244606036
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2952328458
Short name T161
Test name
Test status
Simulation time 63152511875 ps
CPU time 40.28 seconds
Started Jun 13 12:51:10 PM PDT 24
Finished Jun 13 12:51:51 PM PDT 24
Peak memory 182784 kb
Host smart-b9c45ea5-5774-4fe2-bfc4-39c422209272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952328458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2952328458
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2555754957
Short name T403
Test name
Test status
Simulation time 118718089 ps
CPU time 0.73 seconds
Started Jun 13 12:51:08 PM PDT 24
Finished Jun 13 12:51:10 PM PDT 24
Peak memory 182724 kb
Host smart-54eaeae7-3518-42b8-9768-613f8a9aa732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555754957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2555754957
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.39052785
Short name T156
Test name
Test status
Simulation time 426963894782 ps
CPU time 1945.48 seconds
Started Jun 13 12:51:07 PM PDT 24
Finished Jun 13 01:23:33 PM PDT 24
Peak memory 191152 kb
Host smart-5be53737-b2f3-466f-af9d-da48e66c32c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39052785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.39052785
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.4209182537
Short name T40
Test name
Test status
Simulation time 13033743593 ps
CPU time 96.17 seconds
Started Jun 13 12:51:08 PM PDT 24
Finished Jun 13 12:52:45 PM PDT 24
Peak memory 197604 kb
Host smart-aa7cc5f8-fc4f-43b4-bd37-e17f06a76e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209182537 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.4209182537
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.302025232
Short name T365
Test name
Test status
Simulation time 29501266055 ps
CPU time 44.13 seconds
Started Jun 13 12:51:16 PM PDT 24
Finished Jun 13 12:52:01 PM PDT 24
Peak memory 182992 kb
Host smart-58c57052-55af-4280-a844-4822f4abb561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302025232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.302025232
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3774641524
Short name T154
Test name
Test status
Simulation time 61329177061 ps
CPU time 426.05 seconds
Started Jun 13 12:51:08 PM PDT 24
Finished Jun 13 12:58:14 PM PDT 24
Peak memory 194684 kb
Host smart-322a64f2-7c91-46c3-8292-ceb538d1d2be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774641524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3774641524
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2700457585
Short name T121
Test name
Test status
Simulation time 178772740284 ps
CPU time 124.46 seconds
Started Jun 13 12:51:15 PM PDT 24
Finished Jun 13 12:53:20 PM PDT 24
Peak memory 194376 kb
Host smart-3b6dc071-0712-4d85-825c-19b2d784293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700457585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2700457585
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.219821629
Short name T418
Test name
Test status
Simulation time 234018429504 ps
CPU time 345.37 seconds
Started Jun 13 12:51:22 PM PDT 24
Finished Jun 13 12:57:07 PM PDT 24
Peak memory 191160 kb
Host smart-768bfd96-21f4-41a9-b3e8-5886e87c0a89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219821629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
219821629
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.292848481
Short name T18
Test name
Test status
Simulation time 102614795059 ps
CPU time 543.75 seconds
Started Jun 13 12:51:18 PM PDT 24
Finished Jun 13 01:00:22 PM PDT 24
Peak memory 205768 kb
Host smart-31d3be94-f957-48d2-9d6f-1efd8bc59ee7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292848481 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.292848481
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3455945229
Short name T327
Test name
Test status
Simulation time 2011535940960 ps
CPU time 815.14 seconds
Started Jun 13 12:51:23 PM PDT 24
Finished Jun 13 01:04:58 PM PDT 24
Peak memory 182972 kb
Host smart-649c9891-c224-4057-8c8f-b456c280c501
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455945229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3455945229
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.283402591
Short name T395
Test name
Test status
Simulation time 38281757037 ps
CPU time 56.08 seconds
Started Jun 13 12:51:26 PM PDT 24
Finished Jun 13 12:52:22 PM PDT 24
Peak memory 182956 kb
Host smart-5af5c4c4-060b-4160-b69b-308283a59064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283402591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.283402591
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1348142931
Short name T436
Test name
Test status
Simulation time 1009500758 ps
CPU time 1.51 seconds
Started Jun 13 12:51:27 PM PDT 24
Finished Jun 13 12:51:29 PM PDT 24
Peak memory 194380 kb
Host smart-f2e6427b-2b6f-4a16-bd40-b29dc21199f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348142931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1348142931
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.92961301
Short name T305
Test name
Test status
Simulation time 645505177131 ps
CPU time 161.98 seconds
Started Jun 13 12:51:25 PM PDT 24
Finished Jun 13 12:54:07 PM PDT 24
Peak memory 182868 kb
Host smart-16a7e23b-ac15-483a-9439-ebd60f4a5b69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92961301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.rv_timer_cfg_update_on_fly.92961301
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.4171891793
Short name T375
Test name
Test status
Simulation time 689542797571 ps
CPU time 279.99 seconds
Started Jun 13 12:51:23 PM PDT 24
Finished Jun 13 12:56:04 PM PDT 24
Peak memory 182920 kb
Host smart-d647e963-65af-4379-b245-177866b31e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171891793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4171891793
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3230929171
Short name T339
Test name
Test status
Simulation time 131039157398 ps
CPU time 195.7 seconds
Started Jun 13 12:51:24 PM PDT 24
Finished Jun 13 12:54:40 PM PDT 24
Peak memory 192348 kb
Host smart-08068fcb-8535-490a-bbbc-00a5ad313ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230929171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3230929171
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1955119172
Short name T228
Test name
Test status
Simulation time 62654454879 ps
CPU time 28.77 seconds
Started Jun 13 12:51:22 PM PDT 24
Finished Jun 13 12:51:51 PM PDT 24
Peak memory 191168 kb
Host smart-a1850701-4715-43e1-a0f9-96307c1df2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955119172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1955119172
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.84199586
Short name T370
Test name
Test status
Simulation time 590708861330 ps
CPU time 232.89 seconds
Started Jun 13 12:51:31 PM PDT 24
Finished Jun 13 12:55:25 PM PDT 24
Peak memory 183012 kb
Host smart-da99c8dc-7f5e-4d8e-a7fa-6c7e99b2350c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84199586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.84199586
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1660822412
Short name T311
Test name
Test status
Simulation time 198109190505 ps
CPU time 332.97 seconds
Started Jun 13 12:51:31 PM PDT 24
Finished Jun 13 12:57:04 PM PDT 24
Peak memory 182960 kb
Host smart-d1c6718f-4163-48b7-bf21-ef0de45aca4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660822412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1660822412
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1214508804
Short name T419
Test name
Test status
Simulation time 466804269579 ps
CPU time 194.97 seconds
Started Jun 13 12:51:30 PM PDT 24
Finished Jun 13 12:54:45 PM PDT 24
Peak memory 182952 kb
Host smart-b9c2660a-383a-4e89-8aa5-2aba8ed421b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214508804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1214508804
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1966340852
Short name T226
Test name
Test status
Simulation time 146839644819 ps
CPU time 374.26 seconds
Started Jun 13 12:51:31 PM PDT 24
Finished Jun 13 12:57:46 PM PDT 24
Peak memory 195076 kb
Host smart-90e6a9b4-ec1a-42e9-935b-183799c0c82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966340852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1966340852
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2572603400
Short name T153
Test name
Test status
Simulation time 126716822943 ps
CPU time 347.54 seconds
Started Jun 13 12:51:32 PM PDT 24
Finished Jun 13 12:57:20 PM PDT 24
Peak memory 182848 kb
Host smart-8fe7dfa4-142c-4f05-a075-b7cc8c723990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572603400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2572603400
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2717740083
Short name T279
Test name
Test status
Simulation time 83119528528 ps
CPU time 52.68 seconds
Started Jun 13 12:51:31 PM PDT 24
Finished Jun 13 12:52:25 PM PDT 24
Peak memory 192784 kb
Host smart-52e857ef-9094-419f-af43-8dc0776715e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717740083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2717740083
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3637618474
Short name T113
Test name
Test status
Simulation time 194635469555 ps
CPU time 210.44 seconds
Started Jun 13 12:51:39 PM PDT 24
Finished Jun 13 12:55:10 PM PDT 24
Peak memory 182900 kb
Host smart-e450ba3b-39d4-47f7-840a-2997fdf5436a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637618474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3637618474
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2955646584
Short name T404
Test name
Test status
Simulation time 170533747135 ps
CPU time 240.65 seconds
Started Jun 13 12:51:38 PM PDT 24
Finished Jun 13 12:55:39 PM PDT 24
Peak memory 182944 kb
Host smart-8497815a-655e-4190-8103-79738d0df08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955646584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2955646584
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3358944666
Short name T307
Test name
Test status
Simulation time 123284144044 ps
CPU time 74.93 seconds
Started Jun 13 12:51:31 PM PDT 24
Finished Jun 13 12:52:47 PM PDT 24
Peak memory 191196 kb
Host smart-0593f0e8-0e9e-4d03-95e5-c8e812ede719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358944666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3358944666
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4033790701
Short name T196
Test name
Test status
Simulation time 53758959694 ps
CPU time 49.44 seconds
Started Jun 13 12:51:39 PM PDT 24
Finished Jun 13 12:52:29 PM PDT 24
Peak memory 182960 kb
Host smart-571bbd1d-96f6-4717-8610-3a90dca128f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033790701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4033790701
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1878080445
Short name T1
Test name
Test status
Simulation time 159174913321 ps
CPU time 60 seconds
Started Jun 13 12:51:38 PM PDT 24
Finished Jun 13 12:52:39 PM PDT 24
Peak memory 182952 kb
Host smart-bff37f28-d642-420c-b250-25d2514b177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878080445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1878080445
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3898069782
Short name T335
Test name
Test status
Simulation time 669833813210 ps
CPU time 328.56 seconds
Started Jun 13 12:51:39 PM PDT 24
Finished Jun 13 12:57:09 PM PDT 24
Peak memory 182956 kb
Host smart-bc4d60b4-544c-4a65-8036-71a6d2eb18c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898069782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3898069782
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2180897607
Short name T58
Test name
Test status
Simulation time 68907563838 ps
CPU time 116.63 seconds
Started Jun 13 12:51:39 PM PDT 24
Finished Jun 13 12:53:37 PM PDT 24
Peak memory 194756 kb
Host smart-a9db9f79-75a9-47d8-99ab-58e6b6015dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180897607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2180897607
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1194450033
Short name T61
Test name
Test status
Simulation time 369284604112 ps
CPU time 280.22 seconds
Started Jun 13 12:51:39 PM PDT 24
Finished Jun 13 12:56:20 PM PDT 24
Peak memory 191140 kb
Host smart-76ad0b87-73f1-4ca4-9bff-6063fac70d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194450033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1194450033
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3017531381
Short name T328
Test name
Test status
Simulation time 1226207563231 ps
CPU time 654.89 seconds
Started Jun 13 12:51:45 PM PDT 24
Finished Jun 13 01:02:40 PM PDT 24
Peak memory 182940 kb
Host smart-c74d7cf0-7e5d-42af-aa89-d10f1b43cfd6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017531381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3017531381
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3487727359
Short name T8
Test name
Test status
Simulation time 113398638800 ps
CPU time 175.69 seconds
Started Jun 13 12:51:47 PM PDT 24
Finished Jun 13 12:54:43 PM PDT 24
Peak memory 182936 kb
Host smart-c43f56a7-092e-4c9c-ad8c-09e384e8b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487727359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3487727359
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.4082944900
Short name T304
Test name
Test status
Simulation time 509652218560 ps
CPU time 140.83 seconds
Started Jun 13 12:51:39 PM PDT 24
Finished Jun 13 12:54:01 PM PDT 24
Peak memory 191160 kb
Host smart-9abedd6e-9a3f-494e-ab23-0db607360318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082944900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4082944900
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2065331910
Short name T425
Test name
Test status
Simulation time 3852728612 ps
CPU time 3.39 seconds
Started Jun 13 12:51:45 PM PDT 24
Finished Jun 13 12:51:49 PM PDT 24
Peak memory 182796 kb
Host smart-3655294e-cecf-4a11-a2aa-65ceac2c697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065331910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2065331910
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3670484546
Short name T189
Test name
Test status
Simulation time 377026973908 ps
CPU time 348.57 seconds
Started Jun 13 12:49:52 PM PDT 24
Finished Jun 13 12:55:42 PM PDT 24
Peak memory 182984 kb
Host smart-f95ca92d-5a7e-4b6c-876f-2eb4f4e165d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670484546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3670484546
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1341979061
Short name T409
Test name
Test status
Simulation time 101881293839 ps
CPU time 137.18 seconds
Started Jun 13 12:49:52 PM PDT 24
Finished Jun 13 12:52:12 PM PDT 24
Peak memory 182956 kb
Host smart-43b96197-2a05-47fc-ba78-a5204cd647ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341979061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1341979061
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2266103261
Short name T223
Test name
Test status
Simulation time 625700678754 ps
CPU time 2022.01 seconds
Started Jun 13 12:49:45 PM PDT 24
Finished Jun 13 01:23:28 PM PDT 24
Peak memory 191072 kb
Host smart-9b1db90f-9422-4f03-9981-c037e22a7309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266103261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2266103261
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1792718991
Short name T310
Test name
Test status
Simulation time 219534602769 ps
CPU time 82.89 seconds
Started Jun 13 12:49:53 PM PDT 24
Finished Jun 13 12:51:18 PM PDT 24
Peak memory 192700 kb
Host smart-ce9a8492-7d5f-492a-bd68-4d739381571b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792718991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1792718991
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4092495425
Short name T17
Test name
Test status
Simulation time 55438848 ps
CPU time 0.81 seconds
Started Jun 13 12:49:51 PM PDT 24
Finished Jun 13 12:49:54 PM PDT 24
Peak memory 213772 kb
Host smart-6b455cee-aa61-493b-b737-2fdf916e6741
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092495425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4092495425
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.149828587
Short name T397
Test name
Test status
Simulation time 41950314 ps
CPU time 0.58 seconds
Started Jun 13 12:49:53 PM PDT 24
Finished Jun 13 12:49:56 PM PDT 24
Peak memory 182704 kb
Host smart-22bf9095-8a25-40ea-af5b-6b9222115b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149828587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.149828587
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2808337329
Short name T230
Test name
Test status
Simulation time 315366822638 ps
CPU time 512.23 seconds
Started Jun 13 12:51:45 PM PDT 24
Finished Jun 13 01:00:18 PM PDT 24
Peak memory 182932 kb
Host smart-94421ceb-ab46-4976-bb0d-fd891e637764
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808337329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2808337329
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.185727259
Short name T70
Test name
Test status
Simulation time 169813457291 ps
CPU time 111.45 seconds
Started Jun 13 12:51:47 PM PDT 24
Finished Jun 13 12:53:38 PM PDT 24
Peak memory 182876 kb
Host smart-9cfff384-dad7-411e-b1c2-0b38419bb33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185727259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.185727259
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1980771747
Short name T276
Test name
Test status
Simulation time 24024652343 ps
CPU time 35.33 seconds
Started Jun 13 12:51:46 PM PDT 24
Finished Jun 13 12:52:21 PM PDT 24
Peak memory 182960 kb
Host smart-1dfe01ad-49d3-4dae-8d0b-94d5dcc618f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980771747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1980771747
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3402198645
Short name T150
Test name
Test status
Simulation time 184214732532 ps
CPU time 260.15 seconds
Started Jun 13 12:52:02 PM PDT 24
Finished Jun 13 12:56:23 PM PDT 24
Peak memory 182948 kb
Host smart-0fb90c67-eb76-44cc-bd21-83b063d220fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402198645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3402198645
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.728546938
Short name T384
Test name
Test status
Simulation time 178511379627 ps
CPU time 253.36 seconds
Started Jun 13 12:51:53 PM PDT 24
Finished Jun 13 12:56:07 PM PDT 24
Peak memory 182944 kb
Host smart-3792f612-99c0-46f6-ab0a-da8f39e53187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728546938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.728546938
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.477274922
Short name T214
Test name
Test status
Simulation time 633487108272 ps
CPU time 346.59 seconds
Started Jun 13 12:51:52 PM PDT 24
Finished Jun 13 12:57:39 PM PDT 24
Peak memory 195008 kb
Host smart-a4ea7e06-aa64-449e-bac4-5ebb2fee14a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477274922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.477274922
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3370643213
Short name T412
Test name
Test status
Simulation time 59541926112 ps
CPU time 39.42 seconds
Started Jun 13 12:52:00 PM PDT 24
Finished Jun 13 12:52:40 PM PDT 24
Peak memory 194904 kb
Host smart-343f1545-f56e-4546-a38f-60620b17d840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370643213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3370643213
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2585861791
Short name T198
Test name
Test status
Simulation time 812484806056 ps
CPU time 438.09 seconds
Started Jun 13 12:51:59 PM PDT 24
Finished Jun 13 12:59:18 PM PDT 24
Peak memory 182948 kb
Host smart-5ae64ff8-37b8-4724-9852-0c9aa50cbc0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585861791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2585861791
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2066648125
Short name T407
Test name
Test status
Simulation time 28057534442 ps
CPU time 43.38 seconds
Started Jun 13 12:52:01 PM PDT 24
Finished Jun 13 12:52:45 PM PDT 24
Peak memory 182960 kb
Host smart-65441009-b0ff-490c-8202-c2441e25c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066648125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2066648125
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3525479971
Short name T108
Test name
Test status
Simulation time 998087528055 ps
CPU time 2367.39 seconds
Started Jun 13 12:51:59 PM PDT 24
Finished Jun 13 01:31:27 PM PDT 24
Peak memory 191156 kb
Host smart-36ace2e1-24dc-4035-8c90-0ba541973c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525479971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3525479971
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3215531625
Short name T358
Test name
Test status
Simulation time 125518604426 ps
CPU time 78.27 seconds
Started Jun 13 12:51:58 PM PDT 24
Finished Jun 13 12:53:17 PM PDT 24
Peak memory 182984 kb
Host smart-4708a7fb-1911-4ea6-a10c-ea2f10d51af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215531625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3215531625
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1753285923
Short name T232
Test name
Test status
Simulation time 8076688566 ps
CPU time 13.03 seconds
Started Jun 13 12:51:59 PM PDT 24
Finished Jun 13 12:52:13 PM PDT 24
Peak memory 182972 kb
Host smart-437c1adf-5b1d-49f4-93b5-b05ddcfeb98c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753285923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1753285923
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.944522242
Short name T396
Test name
Test status
Simulation time 335104349626 ps
CPU time 101.82 seconds
Started Jun 13 12:51:59 PM PDT 24
Finished Jun 13 12:53:42 PM PDT 24
Peak memory 182916 kb
Host smart-1414dbde-f6bd-476f-85ff-29a675c88cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944522242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.944522242
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1261440886
Short name T221
Test name
Test status
Simulation time 88843584759 ps
CPU time 2122.62 seconds
Started Jun 13 12:51:59 PM PDT 24
Finished Jun 13 01:27:23 PM PDT 24
Peak memory 191176 kb
Host smart-acb242ec-5d7d-411e-b4fd-11899d322b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261440886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1261440886
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.36572108
Short name T422
Test name
Test status
Simulation time 127729699 ps
CPU time 0.7 seconds
Started Jun 13 12:52:10 PM PDT 24
Finished Jun 13 12:52:11 PM PDT 24
Peak memory 182692 kb
Host smart-96f942fc-684b-4fdf-9bc2-a9b313e119e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36572108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.36572108
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3141926205
Short name T65
Test name
Test status
Simulation time 425456604549 ps
CPU time 253.27 seconds
Started Jun 13 12:52:11 PM PDT 24
Finished Jun 13 12:56:25 PM PDT 24
Peak memory 191164 kb
Host smart-2118238d-bf9a-4e31-b79c-efff856972cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141926205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3141926205
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2141862016
Short name T53
Test name
Test status
Simulation time 322668112429 ps
CPU time 134.05 seconds
Started Jun 13 12:52:10 PM PDT 24
Finished Jun 13 12:54:25 PM PDT 24
Peak memory 182960 kb
Host smart-892386ab-5100-4835-9e5f-614c8d702795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141862016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2141862016
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2416300553
Short name T5
Test name
Test status
Simulation time 10976560200 ps
CPU time 17.86 seconds
Started Jun 13 12:52:05 PM PDT 24
Finished Jun 13 12:52:24 PM PDT 24
Peak memory 182952 kb
Host smart-785776bc-cb8e-4d08-a989-04f5382a1d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416300553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2416300553
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2098090775
Short name T423
Test name
Test status
Simulation time 800879304 ps
CPU time 2.11 seconds
Started Jun 13 12:52:05 PM PDT 24
Finished Jun 13 12:52:07 PM PDT 24
Peak memory 193340 kb
Host smart-21d360d4-d38c-4dd3-8528-891a78039055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098090775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2098090775
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.4193931446
Short name T11
Test name
Test status
Simulation time 73444718350 ps
CPU time 265.45 seconds
Started Jun 13 12:52:05 PM PDT 24
Finished Jun 13 12:56:31 PM PDT 24
Peak memory 205904 kb
Host smart-8847df00-f29d-41ef-9100-96a195db11c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193931446 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.4193931446
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.275191801
Short name T187
Test name
Test status
Simulation time 268590407488 ps
CPU time 423.98 seconds
Started Jun 13 12:52:15 PM PDT 24
Finished Jun 13 12:59:19 PM PDT 24
Peak memory 182948 kb
Host smart-6acce7ad-e91f-4b87-b0f8-a3e58d28c4d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275191801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.275191801
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.990717103
Short name T440
Test name
Test status
Simulation time 123972834056 ps
CPU time 159.87 seconds
Started Jun 13 12:52:13 PM PDT 24
Finished Jun 13 12:54:54 PM PDT 24
Peak memory 182956 kb
Host smart-ec7980f1-5df6-4998-a589-2df7e6a6aae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990717103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.990717103
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2314757142
Short name T115
Test name
Test status
Simulation time 143596411175 ps
CPU time 755.48 seconds
Started Jun 13 12:52:10 PM PDT 24
Finished Jun 13 01:04:47 PM PDT 24
Peak memory 191032 kb
Host smart-82f4fb78-a48a-46f1-aba2-a7afc3f67d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314757142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2314757142
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3993598898
Short name T433
Test name
Test status
Simulation time 65592014 ps
CPU time 0.58 seconds
Started Jun 13 12:52:11 PM PDT 24
Finished Jun 13 12:52:13 PM PDT 24
Peak memory 182720 kb
Host smart-842fba06-d471-440a-9fcd-0c12514db791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993598898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3993598898
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2672972983
Short name T68
Test name
Test status
Simulation time 37166448217 ps
CPU time 18.13 seconds
Started Jun 13 12:52:19 PM PDT 24
Finished Jun 13 12:52:38 PM PDT 24
Peak memory 182972 kb
Host smart-4eaefc01-4d98-4b9e-bf1a-94d9c994feff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672972983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2672972983
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1168078365
Short name T449
Test name
Test status
Simulation time 266491026368 ps
CPU time 105.84 seconds
Started Jun 13 12:52:19 PM PDT 24
Finished Jun 13 12:54:06 PM PDT 24
Peak memory 182948 kb
Host smart-184ace1e-dbdb-4cb0-91a5-d5686f76e595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168078365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1168078365
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1938057955
Short name T107
Test name
Test status
Simulation time 2892182136791 ps
CPU time 459.13 seconds
Started Jun 13 12:52:19 PM PDT 24
Finished Jun 13 12:59:59 PM PDT 24
Peak memory 191036 kb
Host smart-f37ddae1-fa24-4469-ad25-90d879ab3823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938057955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1938057955
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.447548801
Short name T51
Test name
Test status
Simulation time 44556159091 ps
CPU time 145.73 seconds
Started Jun 13 12:52:18 PM PDT 24
Finished Jun 13 12:54:45 PM PDT 24
Peak memory 182960 kb
Host smart-2a095926-18ad-4e6e-a655-62c9ac1093f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447548801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.447548801
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2822108358
Short name T302
Test name
Test status
Simulation time 315724006638 ps
CPU time 303.05 seconds
Started Jun 13 12:52:26 PM PDT 24
Finished Jun 13 12:57:30 PM PDT 24
Peak memory 182964 kb
Host smart-9ec91d91-b511-48d1-b872-8e3a0c96026d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822108358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2822108358
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1517954040
Short name T414
Test name
Test status
Simulation time 120648291298 ps
CPU time 142.06 seconds
Started Jun 13 12:52:25 PM PDT 24
Finished Jun 13 12:54:48 PM PDT 24
Peak memory 182952 kb
Host smart-aafcb424-f161-42f6-80ba-1ca56cc6ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517954040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1517954040
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1930220208
Short name T430
Test name
Test status
Simulation time 215739572198 ps
CPU time 1535.06 seconds
Started Jun 13 12:52:26 PM PDT 24
Finished Jun 13 01:18:02 PM PDT 24
Peak memory 191124 kb
Host smart-9b4f3876-1856-4dfe-8dd6-a29f5a498238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930220208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1930220208
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2103314580
Short name T66
Test name
Test status
Simulation time 23653316214 ps
CPU time 42.92 seconds
Started Jun 13 12:52:25 PM PDT 24
Finished Jun 13 12:53:09 PM PDT 24
Peak memory 191220 kb
Host smart-7a5da404-25a3-414b-8638-1fdb3c10bb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103314580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2103314580
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2941028010
Short name T416
Test name
Test status
Simulation time 148536392984 ps
CPU time 205.87 seconds
Started Jun 13 12:52:32 PM PDT 24
Finished Jun 13 12:55:59 PM PDT 24
Peak memory 182924 kb
Host smart-d8630962-8c50-47ba-9f25-a7aeb90ed530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941028010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2941028010
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.1422898868
Short name T12
Test name
Test status
Simulation time 36985390400 ps
CPU time 268.75 seconds
Started Jun 13 12:52:26 PM PDT 24
Finished Jun 13 12:56:55 PM PDT 24
Peak memory 205920 kb
Host smart-270f766d-95b7-4c8b-b4ee-f8dda93e326b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422898868 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.1422898868
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.995582565
Short name T235
Test name
Test status
Simulation time 172350453787 ps
CPU time 70.41 seconds
Started Jun 13 12:52:31 PM PDT 24
Finished Jun 13 12:53:42 PM PDT 24
Peak memory 182960 kb
Host smart-471c5041-f9a0-4211-9471-1aa5e2f9b3fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995582565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.995582565
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3011409685
Short name T400
Test name
Test status
Simulation time 100488346439 ps
CPU time 71.59 seconds
Started Jun 13 12:52:33 PM PDT 24
Finished Jun 13 12:53:45 PM PDT 24
Peak memory 182952 kb
Host smart-626b4058-5ecf-4e1e-8f57-eb1a3de3876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011409685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3011409685
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3440143440
Short name T295
Test name
Test status
Simulation time 87129749566 ps
CPU time 139.2 seconds
Started Jun 13 12:52:34 PM PDT 24
Finished Jun 13 12:54:54 PM PDT 24
Peak memory 191148 kb
Host smart-261a86f4-24f5-4825-bad8-0b7b9f7301e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440143440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3440143440
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.4244469623
Short name T405
Test name
Test status
Simulation time 229950426 ps
CPU time 0.62 seconds
Started Jun 13 12:52:31 PM PDT 24
Finished Jun 13 12:52:32 PM PDT 24
Peak memory 182744 kb
Host smart-9e2a93f8-9110-4c89-bfd1-38cfec1aa2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244469623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4244469623
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3912530300
Short name T331
Test name
Test status
Simulation time 990803584564 ps
CPU time 546.09 seconds
Started Jun 13 12:52:31 PM PDT 24
Finished Jun 13 01:01:38 PM PDT 24
Peak memory 191156 kb
Host smart-11917984-e3f7-462e-9223-92085669299a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912530300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3912530300
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.545638179
Short name T254
Test name
Test status
Simulation time 219780202770 ps
CPU time 366.46 seconds
Started Jun 13 12:52:32 PM PDT 24
Finished Jun 13 12:58:39 PM PDT 24
Peak memory 182940 kb
Host smart-fe6b7a7d-5110-4dab-a8da-a041c24b9fa6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545638179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.545638179
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3659282127
Short name T410
Test name
Test status
Simulation time 252781678028 ps
CPU time 91.28 seconds
Started Jun 13 12:52:38 PM PDT 24
Finished Jun 13 12:54:10 PM PDT 24
Peak memory 182944 kb
Host smart-de4a0f87-a951-4545-a2fb-49e09c310449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659282127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3659282127
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.4225573939
Short name T308
Test name
Test status
Simulation time 155307265857 ps
CPU time 735.11 seconds
Started Jun 13 12:52:40 PM PDT 24
Finished Jun 13 01:04:56 PM PDT 24
Peak memory 191184 kb
Host smart-d44b28d9-250a-4ced-9ebb-5119c6dbc4c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225573939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.4225573939
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3092967077
Short name T325
Test name
Test status
Simulation time 50559166964 ps
CPU time 52.71 seconds
Started Jun 13 12:52:32 PM PDT 24
Finished Jun 13 12:53:25 PM PDT 24
Peak memory 191152 kb
Host smart-a0528fc5-c8d9-429b-880d-6d74ff54b259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092967077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3092967077
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2929437265
Short name T233
Test name
Test status
Simulation time 81029341050 ps
CPU time 135.47 seconds
Started Jun 13 12:52:37 PM PDT 24
Finished Jun 13 12:54:53 PM PDT 24
Peak memory 194568 kb
Host smart-917e18fc-6932-4f67-ac47-0eff0a7e797b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929437265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2929437265
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2810036637
Short name T95
Test name
Test status
Simulation time 75407707738 ps
CPU time 782.56 seconds
Started Jun 13 12:52:36 PM PDT 24
Finished Jun 13 01:05:39 PM PDT 24
Peak memory 207660 kb
Host smart-b4104d18-d2d4-4650-bc46-098950fae0a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810036637 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2810036637
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.214168119
Short name T437
Test name
Test status
Simulation time 553397289658 ps
CPU time 166.64 seconds
Started Jun 13 12:49:52 PM PDT 24
Finished Jun 13 12:52:41 PM PDT 24
Peak memory 182864 kb
Host smart-a2a853fc-5a7b-4f8d-a8e8-a1b7e750744e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214168119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.214168119
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.295852907
Short name T23
Test name
Test status
Simulation time 115638581323 ps
CPU time 47.8 seconds
Started Jun 13 12:49:54 PM PDT 24
Finished Jun 13 12:50:45 PM PDT 24
Peak memory 182968 kb
Host smart-4fda6000-a45e-4589-9ebb-377a53417e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295852907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.295852907
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.724038334
Short name T215
Test name
Test status
Simulation time 323604320170 ps
CPU time 282.43 seconds
Started Jun 13 12:49:52 PM PDT 24
Finished Jun 13 12:54:37 PM PDT 24
Peak memory 191124 kb
Host smart-92ff7979-3247-48d9-bcea-fba5d46f0702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724038334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.724038334
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2186539030
Short name T274
Test name
Test status
Simulation time 184619054665 ps
CPU time 79.32 seconds
Started Jun 13 12:49:52 PM PDT 24
Finished Jun 13 12:51:14 PM PDT 24
Peak memory 194916 kb
Host smart-d5fff685-b8a8-4cd7-8a4e-49a2a5c90d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186539030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2186539030
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.95899906
Short name T38
Test name
Test status
Simulation time 18652569576 ps
CPU time 158.72 seconds
Started Jun 13 12:49:51 PM PDT 24
Finished Jun 13 12:52:32 PM PDT 24
Peak memory 197600 kb
Host smart-eefb1c62-43c5-4ab7-afb1-076115ce43e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95899906 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.95899906
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3821628950
Short name T204
Test name
Test status
Simulation time 574177614162 ps
CPU time 789.53 seconds
Started Jun 13 12:52:39 PM PDT 24
Finished Jun 13 01:05:49 PM PDT 24
Peak memory 191176 kb
Host smart-0655cf00-97c7-451c-bb1c-eba0f2baf866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821628950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3821628950
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.437481099
Short name T219
Test name
Test status
Simulation time 423339630170 ps
CPU time 1952.45 seconds
Started Jun 13 12:52:39 PM PDT 24
Finished Jun 13 01:25:12 PM PDT 24
Peak memory 191108 kb
Host smart-b97e49bd-e81f-4097-a020-ea925d778375
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437481099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.437481099
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4087440075
Short name T333
Test name
Test status
Simulation time 110768340031 ps
CPU time 112 seconds
Started Jun 13 12:52:38 PM PDT 24
Finished Jun 13 12:54:30 PM PDT 24
Peak memory 182940 kb
Host smart-5fd762f9-1ef0-45a0-8a94-7ee9c7e77665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087440075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4087440075
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.305786013
Short name T54
Test name
Test status
Simulation time 231528602019 ps
CPU time 364.16 seconds
Started Jun 13 12:52:38 PM PDT 24
Finished Jun 13 12:58:43 PM PDT 24
Peak memory 191176 kb
Host smart-f431367c-06b1-4418-b3fe-6899577a8ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305786013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.305786013
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1261220497
Short name T338
Test name
Test status
Simulation time 29749414530 ps
CPU time 38.02 seconds
Started Jun 13 12:52:45 PM PDT 24
Finished Jun 13 12:53:25 PM PDT 24
Peak memory 182948 kb
Host smart-fae86fdf-b43d-45eb-8b91-fc46511cee37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261220497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1261220497
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.268035173
Short name T117
Test name
Test status
Simulation time 69122765827 ps
CPU time 161.48 seconds
Started Jun 13 12:52:45 PM PDT 24
Finished Jun 13 12:55:27 PM PDT 24
Peak memory 191180 kb
Host smart-30138b77-0b6e-466e-8ce8-ab389ae777d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268035173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.268035173
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.335171263
Short name T167
Test name
Test status
Simulation time 206290313353 ps
CPU time 188.09 seconds
Started Jun 13 12:52:46 PM PDT 24
Finished Jun 13 12:55:55 PM PDT 24
Peak memory 191176 kb
Host smart-e49cd735-ffbe-41dc-968f-c6b73fccb207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335171263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.335171263
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.498287543
Short name T243
Test name
Test status
Simulation time 134717649827 ps
CPU time 596.36 seconds
Started Jun 13 12:52:44 PM PDT 24
Finished Jun 13 01:02:41 PM PDT 24
Peak memory 191120 kb
Host smart-ab481646-f646-4eab-963d-aa23e31d9984
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498287543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.498287543
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2708481254
Short name T118
Test name
Test status
Simulation time 162101206506 ps
CPU time 351.3 seconds
Started Jun 13 12:52:44 PM PDT 24
Finished Jun 13 12:58:36 PM PDT 24
Peak memory 182944 kb
Host smart-5f33220e-2c36-46fe-9618-7b88991dfefd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708481254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2708481254
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4017938390
Short name T209
Test name
Test status
Simulation time 353936883478 ps
CPU time 544.33 seconds
Started Jun 13 12:49:52 PM PDT 24
Finished Jun 13 12:58:59 PM PDT 24
Peak memory 182868 kb
Host smart-8d9b13c8-db1c-445f-aab8-97e1c156bf6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017938390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4017938390
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.825011812
Short name T378
Test name
Test status
Simulation time 15334713423 ps
CPU time 6.06 seconds
Started Jun 13 12:50:00 PM PDT 24
Finished Jun 13 12:50:10 PM PDT 24
Peak memory 182960 kb
Host smart-25065e4e-a165-432f-bf54-dedecfcedaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825011812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.825011812
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.854931027
Short name T177
Test name
Test status
Simulation time 100196383342 ps
CPU time 370.26 seconds
Started Jun 13 12:49:55 PM PDT 24
Finished Jun 13 12:56:07 PM PDT 24
Peak memory 182968 kb
Host smart-13e4f926-fdae-4333-9d74-e6864629ea6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854931027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.854931027
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.616282917
Short name T264
Test name
Test status
Simulation time 4309203180 ps
CPU time 7.66 seconds
Started Jun 13 12:49:54 PM PDT 24
Finished Jun 13 12:50:04 PM PDT 24
Peak memory 182944 kb
Host smart-a4892572-5a29-4134-8e9c-94af0764f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616282917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.616282917
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.737461184
Short name T21
Test name
Test status
Simulation time 436585148638 ps
CPU time 609.67 seconds
Started Jun 13 12:49:52 PM PDT 24
Finished Jun 13 01:00:04 PM PDT 24
Peak memory 191036 kb
Host smart-02113798-5392-4998-aaf3-2f5d5ad62346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737461184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.737461184
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2107215064
Short name T432
Test name
Test status
Simulation time 58584081538 ps
CPU time 426.15 seconds
Started Jun 13 12:49:51 PM PDT 24
Finished Jun 13 12:56:58 PM PDT 24
Peak memory 197644 kb
Host smart-63b299a7-4b81-4c8d-97a8-0f40d92e5c94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107215064 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2107215064
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1605668041
Short name T265
Test name
Test status
Simulation time 304556574471 ps
CPU time 808.33 seconds
Started Jun 13 12:52:44 PM PDT 24
Finished Jun 13 01:06:13 PM PDT 24
Peak memory 191152 kb
Host smart-07a67163-55c5-47db-88c2-ece1930d694d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605668041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1605668041
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.402551699
Short name T175
Test name
Test status
Simulation time 99649110139 ps
CPU time 592.79 seconds
Started Jun 13 12:52:52 PM PDT 24
Finished Jun 13 01:02:45 PM PDT 24
Peak memory 191160 kb
Host smart-339f25c0-c2cf-455d-baeb-995cd2f9735d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402551699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.402551699
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.232942857
Short name T374
Test name
Test status
Simulation time 22855448898 ps
CPU time 35.54 seconds
Started Jun 13 12:52:52 PM PDT 24
Finished Jun 13 12:53:28 PM PDT 24
Peak memory 182916 kb
Host smart-5e48a6f4-b251-4423-b415-81f45702944c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232942857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.232942857
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1495074568
Short name T282
Test name
Test status
Simulation time 61718722342 ps
CPU time 74.81 seconds
Started Jun 13 12:52:52 PM PDT 24
Finished Jun 13 12:54:08 PM PDT 24
Peak memory 191160 kb
Host smart-1244ec90-1c32-4722-8423-be918e7e804e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495074568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1495074568
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.817494521
Short name T341
Test name
Test status
Simulation time 70875616601 ps
CPU time 217.19 seconds
Started Jun 13 12:52:50 PM PDT 24
Finished Jun 13 12:56:28 PM PDT 24
Peak memory 193312 kb
Host smart-654cee94-b0f3-4ee0-bec8-1f185a53ef8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817494521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.817494521
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2193728118
Short name T244
Test name
Test status
Simulation time 10165649499 ps
CPU time 20.35 seconds
Started Jun 13 12:52:51 PM PDT 24
Finished Jun 13 12:53:12 PM PDT 24
Peak memory 182956 kb
Host smart-bf0fdc73-2aa5-4d19-8d42-81222fe579f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193728118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2193728118
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.384605364
Short name T101
Test name
Test status
Simulation time 48386014140 ps
CPU time 68.75 seconds
Started Jun 13 12:52:52 PM PDT 24
Finished Jun 13 12:54:01 PM PDT 24
Peak memory 191164 kb
Host smart-9d74fb0e-6907-4959-942a-adc8f91bb9de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384605364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.384605364
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3069430583
Short name T120
Test name
Test status
Simulation time 365145343722 ps
CPU time 1687.22 seconds
Started Jun 13 12:52:53 PM PDT 24
Finished Jun 13 01:21:01 PM PDT 24
Peak memory 191120 kb
Host smart-3f15e22a-7aba-437c-aa62-052869e33cd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069430583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3069430583
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.334521953
Short name T398
Test name
Test status
Simulation time 56312986050 ps
CPU time 51.68 seconds
Started Jun 13 12:52:58 PM PDT 24
Finished Jun 13 12:53:50 PM PDT 24
Peak memory 182864 kb
Host smart-39a2307a-8ad7-43fa-b17e-526b698662a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334521953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.334521953
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.875476006
Short name T431
Test name
Test status
Simulation time 1479270682711 ps
CPU time 382.93 seconds
Started Jun 13 12:50:00 PM PDT 24
Finished Jun 13 12:56:27 PM PDT 24
Peak memory 181580 kb
Host smart-dbf0bbf7-aae2-4ee6-8c1c-b32377ccadb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875476006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.875476006
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3810737124
Short name T372
Test name
Test status
Simulation time 25561173229 ps
CPU time 34.5 seconds
Started Jun 13 12:49:54 PM PDT 24
Finished Jun 13 12:50:31 PM PDT 24
Peak memory 182876 kb
Host smart-3133a01c-2d70-4eba-baa4-5fef6400e9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810737124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3810737124
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1156415642
Short name T62
Test name
Test status
Simulation time 336309191519 ps
CPU time 519.04 seconds
Started Jun 13 12:49:58 PM PDT 24
Finished Jun 13 12:58:41 PM PDT 24
Peak memory 194664 kb
Host smart-69aad46f-3d15-4724-bd9c-a3f63eaff572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156415642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1156415642
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3971363502
Short name T152
Test name
Test status
Simulation time 139765983964 ps
CPU time 612.94 seconds
Started Jun 13 12:52:57 PM PDT 24
Finished Jun 13 01:03:11 PM PDT 24
Peak memory 191072 kb
Host smart-6df4b220-39a9-495a-8d43-09526bfd5431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971363502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3971363502
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3491215312
Short name T411
Test name
Test status
Simulation time 104377975669 ps
CPU time 394.47 seconds
Started Jun 13 12:53:00 PM PDT 24
Finished Jun 13 12:59:36 PM PDT 24
Peak memory 191176 kb
Host smart-b8c88b62-93f1-4ed0-8a01-f0c729db4377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491215312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3491215312
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3860847197
Short name T180
Test name
Test status
Simulation time 66720621699 ps
CPU time 128.53 seconds
Started Jun 13 12:52:56 PM PDT 24
Finished Jun 13 12:55:05 PM PDT 24
Peak memory 194684 kb
Host smart-aca52ebc-f45f-4e85-b4ab-87022d19c881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860847197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3860847197
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1637643027
Short name T329
Test name
Test status
Simulation time 10412603020 ps
CPU time 30.87 seconds
Started Jun 13 12:53:00 PM PDT 24
Finished Jun 13 12:53:32 PM PDT 24
Peak memory 182976 kb
Host smart-20558d59-2b8e-4206-9bfb-4ed13f305057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637643027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1637643027
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1923770095
Short name T126
Test name
Test status
Simulation time 81560699062 ps
CPU time 132.21 seconds
Started Jun 13 12:52:59 PM PDT 24
Finished Jun 13 12:55:12 PM PDT 24
Peak memory 191164 kb
Host smart-b303413c-7dee-43a3-8d45-62f4f20fcaf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923770095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1923770095
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1269150043
Short name T173
Test name
Test status
Simulation time 468933679968 ps
CPU time 1742.71 seconds
Started Jun 13 12:53:05 PM PDT 24
Finished Jun 13 01:22:08 PM PDT 24
Peak memory 191128 kb
Host smart-8b8c878f-3afb-4804-aa35-abc27fcf6715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269150043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1269150043
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1634007713
Short name T71
Test name
Test status
Simulation time 316907807467 ps
CPU time 684.47 seconds
Started Jun 13 12:53:05 PM PDT 24
Finished Jun 13 01:04:31 PM PDT 24
Peak memory 191156 kb
Host smart-5c839511-b8e3-444d-83ef-2cd8cbb4e18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634007713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1634007713
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2978559710
Short name T379
Test name
Test status
Simulation time 35278524403 ps
CPU time 62.1 seconds
Started Jun 13 12:53:05 PM PDT 24
Finished Jun 13 12:54:08 PM PDT 24
Peak memory 182976 kb
Host smart-ea752e86-6ccb-45f5-b32a-707023e51e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978559710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2978559710
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3993878799
Short name T259
Test name
Test status
Simulation time 155629405867 ps
CPU time 1232.52 seconds
Started Jun 13 12:53:04 PM PDT 24
Finished Jun 13 01:13:38 PM PDT 24
Peak memory 191040 kb
Host smart-c1deeb8a-da12-46e1-b9b9-3745a503c94b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993878799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3993878799
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1332946477
Short name T322
Test name
Test status
Simulation time 367881749642 ps
CPU time 135.3 seconds
Started Jun 13 12:53:03 PM PDT 24
Finished Jun 13 12:55:19 PM PDT 24
Peak memory 191164 kb
Host smart-cf157d10-6e79-43bc-a762-b0fcf26b244e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332946477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1332946477
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1268754172
Short name T290
Test name
Test status
Simulation time 185728765786 ps
CPU time 315.06 seconds
Started Jun 13 12:49:58 PM PDT 24
Finished Jun 13 12:55:17 PM PDT 24
Peak memory 182952 kb
Host smart-f41c98ee-6c3e-4393-ad35-c0ee0495a256
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268754172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1268754172
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2058696558
Short name T382
Test name
Test status
Simulation time 722349354269 ps
CPU time 139.72 seconds
Started Jun 13 12:50:00 PM PDT 24
Finished Jun 13 12:52:23 PM PDT 24
Peak memory 181484 kb
Host smart-3e5bdc70-a50d-41fc-b67d-36620a07cc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058696558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2058696558
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.891644881
Short name T129
Test name
Test status
Simulation time 127143075978 ps
CPU time 286.32 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 12:54:49 PM PDT 24
Peak memory 193408 kb
Host smart-a9407d11-6d90-40dc-94f1-4ea0146f1c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891644881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.891644881
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.901021940
Short name T7
Test name
Test status
Simulation time 158647330 ps
CPU time 0.73 seconds
Started Jun 13 12:50:01 PM PDT 24
Finished Jun 13 12:50:05 PM PDT 24
Peak memory 182692 kb
Host smart-1cbb3f59-1fce-4dae-bba4-9fbeb1c35ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901021940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.901021940
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.4234595331
Short name T349
Test name
Test status
Simulation time 133196166014 ps
CPU time 110.8 seconds
Started Jun 13 12:53:06 PM PDT 24
Finished Jun 13 12:54:57 PM PDT 24
Peak memory 191168 kb
Host smart-d8f01e6f-70bd-4b3b-b828-189cf673b46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234595331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4234595331
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1911837039
Short name T324
Test name
Test status
Simulation time 178885571972 ps
CPU time 259.71 seconds
Started Jun 13 12:53:05 PM PDT 24
Finished Jun 13 12:57:25 PM PDT 24
Peak memory 191080 kb
Host smart-5cfcad40-2fd3-41ca-89eb-c145102fbe9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911837039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1911837039
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1106416412
Short name T253
Test name
Test status
Simulation time 663922773937 ps
CPU time 661.45 seconds
Started Jun 13 12:53:04 PM PDT 24
Finished Jun 13 01:04:06 PM PDT 24
Peak memory 191080 kb
Host smart-f9b8bf2c-a6a8-4cf7-aca7-ed29bc354182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106416412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1106416412
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3810178588
Short name T157
Test name
Test status
Simulation time 73438434901 ps
CPU time 111.78 seconds
Started Jun 13 12:53:11 PM PDT 24
Finished Jun 13 12:55:04 PM PDT 24
Peak memory 191080 kb
Host smart-cdad186a-66bd-4a21-8ed1-b6a48af26d42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810178588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3810178588
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.28717439
Short name T207
Test name
Test status
Simulation time 247458752958 ps
CPU time 335.2 seconds
Started Jun 13 12:53:12 PM PDT 24
Finished Jun 13 12:58:48 PM PDT 24
Peak memory 191168 kb
Host smart-e057aa32-8489-42df-afd9-45a92f233e1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28717439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.28717439
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.916610099
Short name T424
Test name
Test status
Simulation time 6238144305 ps
CPU time 6.13 seconds
Started Jun 13 12:53:12 PM PDT 24
Finished Jun 13 12:53:19 PM PDT 24
Peak memory 182968 kb
Host smart-45708f58-bdc7-41b9-947d-6eb4fc3be39e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916610099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.916610099
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.274027198
Short name T92
Test name
Test status
Simulation time 109037728430 ps
CPU time 63.96 seconds
Started Jun 13 12:53:12 PM PDT 24
Finished Jun 13 12:54:17 PM PDT 24
Peak memory 182916 kb
Host smart-8fce913a-32aa-4b64-a806-e8dc1e66ecff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274027198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.274027198
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4161204520
Short name T294
Test name
Test status
Simulation time 597209126095 ps
CPU time 321.13 seconds
Started Jun 13 12:50:01 PM PDT 24
Finished Jun 13 12:55:25 PM PDT 24
Peak memory 182960 kb
Host smart-09bfef23-bfbd-4351-8afc-e21c1979af8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161204520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4161204520
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3384901740
Short name T371
Test name
Test status
Simulation time 32949125514 ps
CPU time 12.02 seconds
Started Jun 13 12:50:00 PM PDT 24
Finished Jun 13 12:50:15 PM PDT 24
Peak memory 182972 kb
Host smart-1f43a43e-e22c-4a8d-845a-d95aaa7d4d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384901740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3384901740
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.914177300
Short name T136
Test name
Test status
Simulation time 17146700389 ps
CPU time 46.6 seconds
Started Jun 13 12:49:59 PM PDT 24
Finished Jun 13 12:50:50 PM PDT 24
Peak memory 191132 kb
Host smart-59f2952e-7b8a-45ef-ac72-d30ddc6cd7db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914177300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.914177300
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1627155473
Short name T168
Test name
Test status
Simulation time 12159435407 ps
CPU time 69.9 seconds
Started Jun 13 12:50:00 PM PDT 24
Finished Jun 13 12:51:13 PM PDT 24
Peak memory 182964 kb
Host smart-17d4e12e-56d3-4d7e-95f8-8d29d73fb168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627155473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1627155473
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2533715812
Short name T64
Test name
Test status
Simulation time 1816452515223 ps
CPU time 1081.97 seconds
Started Jun 13 12:50:02 PM PDT 24
Finished Jun 13 01:08:07 PM PDT 24
Peak memory 197016 kb
Host smart-aa879ea0-a788-46e5-96f4-b8a19d8e3801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533715812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2533715812
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1411061517
Short name T37
Test name
Test status
Simulation time 93271565022 ps
CPU time 287.83 seconds
Started Jun 13 12:50:00 PM PDT 24
Finished Jun 13 12:54:51 PM PDT 24
Peak memory 205848 kb
Host smart-0248109e-ebfb-4162-ac0c-dfbc81eee072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411061517 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1411061517
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2442634735
Short name T24
Test name
Test status
Simulation time 138076073832 ps
CPU time 73.86 seconds
Started Jun 13 12:53:10 PM PDT 24
Finished Jun 13 12:54:24 PM PDT 24
Peak memory 182972 kb
Host smart-b2617400-4271-4989-9049-4ba1719be178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442634735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2442634735
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1790070238
Short name T192
Test name
Test status
Simulation time 121375807769 ps
CPU time 506.35 seconds
Started Jun 13 12:53:18 PM PDT 24
Finished Jun 13 01:01:45 PM PDT 24
Peak memory 191080 kb
Host smart-c0c47066-1314-450e-be88-11e2ce3b1032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790070238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1790070238
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.977937137
Short name T193
Test name
Test status
Simulation time 28770720704 ps
CPU time 44 seconds
Started Jun 13 12:53:18 PM PDT 24
Finished Jun 13 12:54:03 PM PDT 24
Peak memory 182880 kb
Host smart-5dc39f34-482f-4443-9452-19c7c27a82f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977937137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.977937137
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.822300483
Short name T345
Test name
Test status
Simulation time 146218925589 ps
CPU time 355.97 seconds
Started Jun 13 12:53:19 PM PDT 24
Finished Jun 13 12:59:15 PM PDT 24
Peak memory 191176 kb
Host smart-0a4cfafd-b1d9-41c7-9acc-88e47c54de22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822300483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.822300483
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3506727087
Short name T234
Test name
Test status
Simulation time 1319690111893 ps
CPU time 579.64 seconds
Started Jun 13 12:53:18 PM PDT 24
Finished Jun 13 01:02:58 PM PDT 24
Peak memory 191124 kb
Host smart-432e996b-5d78-4183-b35c-579ae4eb575f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506727087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3506727087
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2819549143
Short name T144
Test name
Test status
Simulation time 317191647375 ps
CPU time 156.52 seconds
Started Jun 13 12:53:20 PM PDT 24
Finished Jun 13 12:55:57 PM PDT 24
Peak memory 191176 kb
Host smart-80772ddb-7701-49ff-b51a-fee6bbbf0f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819549143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2819549143
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.353224159
Short name T159
Test name
Test status
Simulation time 260318721654 ps
CPU time 254.74 seconds
Started Jun 13 12:53:18 PM PDT 24
Finished Jun 13 12:57:33 PM PDT 24
Peak memory 191176 kb
Host smart-651074d4-e519-479c-954e-6750766a7b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353224159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.353224159
Directory /workspace/99.rv_timer_random/latest
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