Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1837038393 Jun 21 05:09:13 PM PDT 24 Jun 21 05:09:18 PM PDT 24 664760032 ps
T98 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2558415593 Jun 21 05:09:14 PM PDT 24 Jun 21 05:09:18 PM PDT 24 23447170 ps
T510 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.683302574 Jun 21 05:09:33 PM PDT 24 Jun 21 05:09:37 PM PDT 24 101025900 ps
T511 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.742426443 Jun 21 05:09:32 PM PDT 24 Jun 21 05:09:37 PM PDT 24 48745221 ps
T512 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2292094199 Jun 21 05:09:26 PM PDT 24 Jun 21 05:09:30 PM PDT 24 145434489 ps
T513 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1094625347 Jun 21 05:09:14 PM PDT 24 Jun 21 05:09:18 PM PDT 24 61267082 ps
T514 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.337249885 Jun 21 05:09:13 PM PDT 24 Jun 21 05:09:17 PM PDT 24 383498533 ps
T515 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4243941674 Jun 21 05:09:26 PM PDT 24 Jun 21 05:09:29 PM PDT 24 13400936 ps
T105 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1262833421 Jun 21 05:09:38 PM PDT 24 Jun 21 05:09:43 PM PDT 24 382497097 ps
T516 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1851749739 Jun 21 05:09:43 PM PDT 24 Jun 21 05:09:46 PM PDT 24 16005387 ps
T517 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1382127344 Jun 21 05:09:37 PM PDT 24 Jun 21 05:09:42 PM PDT 24 38500106 ps
T518 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2093744012 Jun 21 05:09:13 PM PDT 24 Jun 21 05:09:19 PM PDT 24 559378295 ps
T519 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2068070799 Jun 21 05:09:48 PM PDT 24 Jun 21 05:09:51 PM PDT 24 31596844 ps
T520 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.489058493 Jun 21 05:09:26 PM PDT 24 Jun 21 05:09:30 PM PDT 24 244406826 ps
T83 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.647703934 Jun 21 05:09:40 PM PDT 24 Jun 21 05:09:44 PM PDT 24 26809696 ps
T521 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.138353190 Jun 21 05:09:43 PM PDT 24 Jun 21 05:09:47 PM PDT 24 29081603 ps
T522 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3210426879 Jun 21 05:09:27 PM PDT 24 Jun 21 05:09:30 PM PDT 24 13643441 ps
T523 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2478633276 Jun 21 05:09:14 PM PDT 24 Jun 21 05:09:18 PM PDT 24 44586790 ps
T524 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1523878888 Jun 21 05:09:27 PM PDT 24 Jun 21 05:09:32 PM PDT 24 172082247 ps
T525 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1732100154 Jun 21 05:09:40 PM PDT 24 Jun 21 05:09:43 PM PDT 24 38017783 ps
T526 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2991347495 Jun 21 05:09:26 PM PDT 24 Jun 21 05:09:30 PM PDT 24 721826080 ps
T527 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3391028801 Jun 21 05:09:40 PM PDT 24 Jun 21 05:09:44 PM PDT 24 11623297 ps
T528 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2868472078 Jun 21 05:09:27 PM PDT 24 Jun 21 05:09:30 PM PDT 24 37558925 ps
T86 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2981566436 Jun 21 05:09:11 PM PDT 24 Jun 21 05:09:16 PM PDT 24 834146955 ps
T529 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1056499454 Jun 21 05:09:11 PM PDT 24 Jun 21 05:09:13 PM PDT 24 150224241 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.154976557 Jun 21 05:09:12 PM PDT 24 Jun 21 05:09:15 PM PDT 24 31570660 ps
T531 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2379674770 Jun 21 05:09:14 PM PDT 24 Jun 21 05:09:18 PM PDT 24 12744355 ps
T532 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3711720371 Jun 21 05:09:44 PM PDT 24 Jun 21 05:09:47 PM PDT 24 53777124 ps
T533 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.470985766 Jun 21 05:09:33 PM PDT 24 Jun 21 05:09:38 PM PDT 24 259842314 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3114507698 Jun 21 05:09:13 PM PDT 24 Jun 21 05:09:17 PM PDT 24 14589470 ps
T535 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1910473117 Jun 21 05:09:34 PM PDT 24 Jun 21 05:09:39 PM PDT 24 21297789 ps
T536 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2255469179 Jun 21 05:09:15 PM PDT 24 Jun 21 05:09:20 PM PDT 24 31269713 ps
T537 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.744969730 Jun 21 05:09:34 PM PDT 24 Jun 21 05:09:39 PM PDT 24 16779318 ps
T538 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1864921681 Jun 21 05:09:12 PM PDT 24 Jun 21 05:09:14 PM PDT 24 17270511 ps
T539 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2231885251 Jun 21 05:09:37 PM PDT 24 Jun 21 05:09:41 PM PDT 24 24348920 ps
T540 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1985294736 Jun 21 05:09:30 PM PDT 24 Jun 21 05:09:34 PM PDT 24 18779809 ps
T541 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.77093980 Jun 21 05:09:11 PM PDT 24 Jun 21 05:09:12 PM PDT 24 11870107 ps
T542 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3818436320 Jun 21 05:09:28 PM PDT 24 Jun 21 05:09:33 PM PDT 24 223682469 ps
T543 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3777878391 Jun 21 05:09:16 PM PDT 24 Jun 21 05:09:20 PM PDT 24 32196302 ps
T544 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3576975342 Jun 21 05:09:27 PM PDT 24 Jun 21 05:09:32 PM PDT 24 12776456 ps
T84 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.147305491 Jun 21 05:09:15 PM PDT 24 Jun 21 05:09:20 PM PDT 24 60514070 ps
T88 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1892811389 Jun 21 05:09:12 PM PDT 24 Jun 21 05:09:15 PM PDT 24 132824768 ps
T106 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3755187145 Jun 21 05:09:29 PM PDT 24 Jun 21 05:09:34 PM PDT 24 89799368 ps
T545 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2602945018 Jun 21 05:09:34 PM PDT 24 Jun 21 05:09:38 PM PDT 24 110202469 ps
T546 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3140100792 Jun 21 05:09:36 PM PDT 24 Jun 21 05:09:41 PM PDT 24 13108093 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1189152597 Jun 21 05:09:28 PM PDT 24 Jun 21 05:09:33 PM PDT 24 17821836 ps
T548 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3668359872 Jun 21 05:09:23 PM PDT 24 Jun 21 05:09:25 PM PDT 24 20287342 ps
T549 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3507953242 Jun 21 05:09:28 PM PDT 24 Jun 21 05:09:34 PM PDT 24 265910931 ps
T550 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1046554060 Jun 21 05:09:14 PM PDT 24 Jun 21 05:09:18 PM PDT 24 94691319 ps
T551 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1224731034 Jun 21 05:09:11 PM PDT 24 Jun 21 05:09:15 PM PDT 24 53736860 ps
T552 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.512544564 Jun 21 05:09:46 PM PDT 24 Jun 21 05:09:50 PM PDT 24 13411492 ps
T553 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.777021795 Jun 21 05:09:25 PM PDT 24 Jun 21 05:09:28 PM PDT 24 868310432 ps
T554 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.548260728 Jun 21 05:09:38 PM PDT 24 Jun 21 05:09:42 PM PDT 24 73500526 ps
T555 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4265527069 Jun 21 05:09:34 PM PDT 24 Jun 21 05:09:39 PM PDT 24 106892483 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2357461999 Jun 21 05:09:16 PM PDT 24 Jun 21 05:09:20 PM PDT 24 17270103 ps
T557 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1329428120 Jun 21 05:09:28 PM PDT 24 Jun 21 05:09:33 PM PDT 24 67602499 ps
T558 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2110424419 Jun 21 05:09:27 PM PDT 24 Jun 21 05:09:32 PM PDT 24 119208477 ps
T559 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1151521166 Jun 21 05:09:28 PM PDT 24 Jun 21 05:09:33 PM PDT 24 459194449 ps
T560 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1686544799 Jun 21 05:09:27 PM PDT 24 Jun 21 05:09:31 PM PDT 24 47862685 ps
T561 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2898153953 Jun 21 05:09:21 PM PDT 24 Jun 21 05:09:23 PM PDT 24 392827213 ps
T562 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1999164197 Jun 21 05:09:32 PM PDT 24 Jun 21 05:09:37 PM PDT 24 42768129 ps
T563 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.533708876 Jun 21 05:09:44 PM PDT 24 Jun 21 05:09:47 PM PDT 24 26899732 ps
T564 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3552978341 Jun 21 05:09:31 PM PDT 24 Jun 21 05:09:38 PM PDT 24 48267695 ps
T565 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2323815267 Jun 21 05:09:15 PM PDT 24 Jun 21 05:09:21 PM PDT 24 704888832 ps
T87 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.911314848 Jun 21 05:09:16 PM PDT 24 Jun 21 05:09:21 PM PDT 24 52562312 ps
T566 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.899575286 Jun 21 05:09:11 PM PDT 24 Jun 21 05:09:14 PM PDT 24 257110373 ps
T567 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3612879231 Jun 21 05:09:48 PM PDT 24 Jun 21 05:09:51 PM PDT 24 93363593 ps
T568 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.486293134 Jun 21 05:09:41 PM PDT 24 Jun 21 05:09:45 PM PDT 24 30188032 ps
T569 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2467568034 Jun 21 05:09:31 PM PDT 24 Jun 21 05:09:36 PM PDT 24 217638290 ps
T570 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4242663508 Jun 21 05:09:49 PM PDT 24 Jun 21 05:09:52 PM PDT 24 11902647 ps
T571 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2483729616 Jun 21 05:09:37 PM PDT 24 Jun 21 05:09:42 PM PDT 24 67434542 ps
T572 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3618571222 Jun 21 05:09:28 PM PDT 24 Jun 21 05:09:33 PM PDT 24 46996095 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.628604306 Jun 21 05:09:12 PM PDT 24 Jun 21 05:09:16 PM PDT 24 338145567 ps
T574 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1589440818 Jun 21 05:09:38 PM PDT 24 Jun 21 05:09:43 PM PDT 24 16792247 ps
T575 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3107967784 Jun 21 05:09:29 PM PDT 24 Jun 21 05:09:34 PM PDT 24 26866757 ps
T576 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.290310753 Jun 21 05:09:15 PM PDT 24 Jun 21 05:09:21 PM PDT 24 102231942 ps
T577 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4264722268 Jun 21 05:09:12 PM PDT 24 Jun 21 05:09:15 PM PDT 24 87819702 ps
T578 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.403750292 Jun 21 05:09:40 PM PDT 24 Jun 21 05:09:46 PM PDT 24 47492760 ps
T579 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3171398706 Jun 21 05:09:36 PM PDT 24 Jun 21 05:09:41 PM PDT 24 17827127 ps
T580 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2546051671 Jun 21 05:09:54 PM PDT 24 Jun 21 05:09:56 PM PDT 24 36466789 ps
T581 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1899782539 Jun 21 05:09:13 PM PDT 24 Jun 21 05:09:18 PM PDT 24 144193570 ps
T582 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3514554175 Jun 21 05:09:13 PM PDT 24 Jun 21 05:09:17 PM PDT 24 26729715 ps

Test location /workspace/coverage/default/19.rv_timer_stress_all.4203383333
Short name T3
Test name
Test status
Simulation time 363747379205 ps
CPU time 369.78 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:16:10 PM PDT 24
Peak memory 191124 kb
Host smart-91acd38f-0809-47e7-868b-6ac13688e058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203383333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4203383333
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.2440248337
Short name T15
Test name
Test status
Simulation time 219313795856 ps
CPU time 647.91 seconds
Started Jun 21 05:10:21 PM PDT 24
Finished Jun 21 05:21:13 PM PDT 24
Peak memory 205872 kb
Host smart-d9af25c5-a347-470a-966a-f6718de6c62d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440248337 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.2440248337
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.4289603983
Short name T12
Test name
Test status
Simulation time 1751915068891 ps
CPU time 730.23 seconds
Started Jun 21 05:10:19 PM PDT 24
Finished Jun 21 05:22:33 PM PDT 24
Peak memory 191156 kb
Host smart-acbd718a-fa4d-4cdd-8fac-b0b2e2b48677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289603983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.4289603983
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1990830969
Short name T28
Test name
Test status
Simulation time 519895875 ps
CPU time 1.3 seconds
Started Jun 21 05:09:25 PM PDT 24
Finished Jun 21 05:09:28 PM PDT 24
Peak memory 194988 kb
Host smart-aad26ea8-96a8-46ca-b7ba-db28d297b59d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990830969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1990830969
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.595416082
Short name T176
Test name
Test status
Simulation time 2418127478644 ps
CPU time 1912.25 seconds
Started Jun 21 05:10:22 PM PDT 24
Finished Jun 21 05:42:18 PM PDT 24
Peak memory 196400 kb
Host smart-9613af4d-e4d8-4cb6-9663-465a2e0672a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595416082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
595416082
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1837438246
Short name T26
Test name
Test status
Simulation time 2042342926249 ps
CPU time 1296.27 seconds
Started Jun 21 05:10:03 PM PDT 24
Finished Jun 21 05:31:41 PM PDT 24
Peak memory 191132 kb
Host smart-33fd2b18-b761-4593-9b88-49172921c610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837438246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1837438246
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.117641108
Short name T117
Test name
Test status
Simulation time 5204438168515 ps
CPU time 4803.27 seconds
Started Jun 21 05:09:41 PM PDT 24
Finished Jun 21 06:29:48 PM PDT 24
Peak memory 191028 kb
Host smart-ccba2699-babd-42e9-ae0c-abe809888189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117641108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.117641108
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.866344275
Short name T170
Test name
Test status
Simulation time 3739018791473 ps
CPU time 3285.68 seconds
Started Jun 21 05:09:41 PM PDT 24
Finished Jun 21 06:04:30 PM PDT 24
Peak memory 191284 kb
Host smart-dbdd5c3a-50c4-4a54-94e4-fa2b498fd092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866344275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.866344275
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.289489247
Short name T57
Test name
Test status
Simulation time 1135792445801 ps
CPU time 1573.35 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:36:32 PM PDT 24
Peak memory 191160 kb
Host smart-285484aa-7fc4-4cf6-ba01-3e2dbc81c60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289489247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
289489247
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3732599526
Short name T144
Test name
Test status
Simulation time 4021307339316 ps
CPU time 4356.73 seconds
Started Jun 21 05:10:21 PM PDT 24
Finished Jun 21 06:23:02 PM PDT 24
Peak memory 191076 kb
Host smart-38e66dfb-4093-4993-a338-9093695f7ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732599526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3732599526
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4041480930
Short name T184
Test name
Test status
Simulation time 594603173594 ps
CPU time 887.43 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:24:55 PM PDT 24
Peak memory 191152 kb
Host smart-77db85b9-f41c-4198-b268-6261c9b9c153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041480930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4041480930
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_random.2442090505
Short name T10
Test name
Test status
Simulation time 1005184592783 ps
CPU time 567.99 seconds
Started Jun 21 05:10:28 PM PDT 24
Finished Jun 21 05:19:58 PM PDT 24
Peak memory 191068 kb
Host smart-0cf7bf06-3cb9-4e15-b5da-f6553547be5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442090505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2442090505
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1539177407
Short name T16
Test name
Test status
Simulation time 131882497 ps
CPU time 0.77 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:09:47 PM PDT 24
Peak memory 213704 kb
Host smart-a00bf386-c18b-4d57-80dd-2a98629b3545
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539177407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1539177407
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/114.rv_timer_random.124238418
Short name T111
Test name
Test status
Simulation time 420645041426 ps
CPU time 769.62 seconds
Started Jun 21 05:10:36 PM PDT 24
Finished Jun 21 05:23:26 PM PDT 24
Peak memory 191140 kb
Host smart-ab292dad-1154-47b8-8c20-55009ad78278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124238418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.124238418
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4275142013
Short name T277
Test name
Test status
Simulation time 3145626210938 ps
CPU time 833.42 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:23:53 PM PDT 24
Peak memory 195968 kb
Host smart-c93e249b-112a-4e28-b868-df78682a6218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275142013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4275142013
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3131274275
Short name T156
Test name
Test status
Simulation time 854659715591 ps
CPU time 1413.77 seconds
Started Jun 21 05:10:10 PM PDT 24
Finished Jun 21 05:33:45 PM PDT 24
Peak memory 191076 kb
Host smart-df9f289f-2244-4b1b-8323-03be338b2b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131274275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3131274275
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.4276498426
Short name T127
Test name
Test status
Simulation time 218540406235 ps
CPU time 467.7 seconds
Started Jun 21 05:09:51 PM PDT 24
Finished Jun 21 05:17:41 PM PDT 24
Peak memory 192596 kb
Host smart-877e1754-c8e8-4f60-86bf-4654954be55b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276498426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.4276498426
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1707692154
Short name T267
Test name
Test status
Simulation time 977705911010 ps
CPU time 1239.03 seconds
Started Jun 21 05:10:04 PM PDT 24
Finished Jun 21 05:30:45 PM PDT 24
Peak memory 191296 kb
Host smart-c0ea3b83-d0b5-4546-bf09-4d8c8cefdd3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707692154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1707692154
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1622400873
Short name T145
Test name
Test status
Simulation time 2188736979605 ps
CPU time 1491.86 seconds
Started Jun 21 05:09:55 PM PDT 24
Finished Jun 21 05:34:48 PM PDT 24
Peak memory 191144 kb
Host smart-3123eb0c-2274-4f9b-9832-658a829e622e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622400873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1622400873
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/94.rv_timer_random.46425431
Short name T109
Test name
Test status
Simulation time 407798393838 ps
CPU time 341.87 seconds
Started Jun 21 05:10:33 PM PDT 24
Finished Jun 21 05:16:16 PM PDT 24
Peak memory 191160 kb
Host smart-dac9f41b-0ed7-41d0-945f-d91c40477481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46425431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.46425431
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.975454659
Short name T21
Test name
Test status
Simulation time 645306375281 ps
CPU time 2093.69 seconds
Started Jun 21 05:10:37 PM PDT 24
Finished Jun 21 05:45:32 PM PDT 24
Peak memory 191068 kb
Host smart-1a22ae49-48e9-4805-a045-bb4f88107ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975454659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.975454659
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2575604040
Short name T253
Test name
Test status
Simulation time 796584841991 ps
CPU time 332.09 seconds
Started Jun 21 05:10:58 PM PDT 24
Finished Jun 21 05:16:31 PM PDT 24
Peak memory 191064 kb
Host smart-43704843-8d3c-433e-8c4b-26d716a957a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575604040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2575604040
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3135241873
Short name T27
Test name
Test status
Simulation time 631726356720 ps
CPU time 259.68 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:14:47 PM PDT 24
Peak memory 191152 kb
Host smart-db1be2bd-af5b-4b20-8e06-084a447c13f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135241873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3135241873
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1929963712
Short name T77
Test name
Test status
Simulation time 11888723 ps
CPU time 0.57 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:17 PM PDT 24
Peak memory 182656 kb
Host smart-86b44c68-8e13-492b-a3f9-907dbb5272f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929963712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1929963712
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/63.rv_timer_random.1323378221
Short name T213
Test name
Test status
Simulation time 749369462006 ps
CPU time 835.89 seconds
Started Jun 21 05:10:21 PM PDT 24
Finished Jun 21 05:24:21 PM PDT 24
Peak memory 191044 kb
Host smart-328e4210-6e7d-47af-a121-453579c7b335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323378221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1323378221
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4293237385
Short name T224
Test name
Test status
Simulation time 194537197412 ps
CPU time 479.8 seconds
Started Jun 21 05:10:22 PM PDT 24
Finished Jun 21 05:18:26 PM PDT 24
Peak memory 191040 kb
Host smart-3e7cb0c3-a1a5-4a0d-8272-128d93e55cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293237385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4293237385
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.4152782029
Short name T316
Test name
Test status
Simulation time 397348082813 ps
CPU time 2164.28 seconds
Started Jun 21 05:10:32 PM PDT 24
Finished Jun 21 05:46:38 PM PDT 24
Peak memory 191076 kb
Host smart-cf1ab194-8742-408d-9adb-852208acdfaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152782029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4152782029
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.3120710621
Short name T165
Test name
Test status
Simulation time 145860433110 ps
CPU time 219.99 seconds
Started Jun 21 05:10:38 PM PDT 24
Finished Jun 21 05:14:18 PM PDT 24
Peak memory 191072 kb
Host smart-5cf1b423-d1b8-4deb-a38e-dfd9264b98d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120710621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3120710621
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2178062130
Short name T183
Test name
Test status
Simulation time 111504140513 ps
CPU time 387.63 seconds
Started Jun 21 05:11:12 PM PDT 24
Finished Jun 21 05:17:41 PM PDT 24
Peak memory 191280 kb
Host smart-9585c72d-adbd-4f30-8e4b-dbf9c5d2723a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178062130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2178062130
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2182852121
Short name T274
Test name
Test status
Simulation time 287848010329 ps
CPU time 978.32 seconds
Started Jun 21 05:11:13 PM PDT 24
Finished Jun 21 05:27:32 PM PDT 24
Peak memory 191048 kb
Host smart-ca4793b6-3aa5-42eb-a1d8-4b4f6b7a6109
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182852121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2182852121
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1051101963
Short name T143
Test name
Test status
Simulation time 284740763452 ps
CPU time 472.27 seconds
Started Jun 21 05:10:32 PM PDT 24
Finished Jun 21 05:18:26 PM PDT 24
Peak memory 191072 kb
Host smart-bc73eccf-3b74-4d36-9e9a-5deeb484ea2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051101963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1051101963
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.191629473
Short name T178
Test name
Test status
Simulation time 91317235772 ps
CPU time 351.43 seconds
Started Jun 21 05:10:35 PM PDT 24
Finished Jun 21 05:16:27 PM PDT 24
Peak memory 191020 kb
Host smart-00fe8e11-e038-44f6-a376-dbb0338f3913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191629473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.191629473
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3323704531
Short name T247
Test name
Test status
Simulation time 109712876382 ps
CPU time 210.91 seconds
Started Jun 21 05:10:40 PM PDT 24
Finished Jun 21 05:14:12 PM PDT 24
Peak memory 191120 kb
Host smart-f06b1a6d-c12b-4a69-a43c-dcce95edfd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323704531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3323704531
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.1142886663
Short name T151
Test name
Test status
Simulation time 1016144452297 ps
CPU time 298.63 seconds
Started Jun 21 05:10:52 PM PDT 24
Finished Jun 21 05:15:51 PM PDT 24
Peak memory 191152 kb
Host smart-402ff2a8-40a2-42e0-84da-d4b7556198dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142886663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1142886663
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random.2242555751
Short name T164
Test name
Test status
Simulation time 128996608909 ps
CPU time 637.49 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:21:01 PM PDT 24
Peak memory 191164 kb
Host smart-5038772a-7d81-4241-9b50-1c619d6af329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242555751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2242555751
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1504766966
Short name T59
Test name
Test status
Simulation time 220197785471 ps
CPU time 694.69 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:21:59 PM PDT 24
Peak memory 191132 kb
Host smart-d58bc29b-9838-4165-8c37-a717f1cc9a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504766966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1504766966
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.318973620
Short name T284
Test name
Test status
Simulation time 318634783521 ps
CPU time 858.92 seconds
Started Jun 21 05:10:32 PM PDT 24
Finished Jun 21 05:24:52 PM PDT 24
Peak memory 191076 kb
Host smart-2a06408f-502b-4255-9521-56f99136a745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318973620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.318973620
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3902144770
Short name T180
Test name
Test status
Simulation time 153092077645 ps
CPU time 447.32 seconds
Started Jun 21 05:10:42 PM PDT 24
Finished Jun 21 05:18:10 PM PDT 24
Peak memory 191148 kb
Host smart-5e889486-3b42-4970-8b18-fa0b1fc1eb28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902144770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3902144770
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1994887971
Short name T233
Test name
Test status
Simulation time 1000780318754 ps
CPU time 839.55 seconds
Started Jun 21 05:10:51 PM PDT 24
Finished Jun 21 05:24:51 PM PDT 24
Peak memory 191072 kb
Host smart-4910644e-0294-4170-9ee7-62738ce396e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994887971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1994887971
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.735390875
Short name T210
Test name
Test status
Simulation time 565572334058 ps
CPU time 407.01 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:16:48 PM PDT 24
Peak memory 191148 kb
Host smart-d1b98972-3945-49e7-8188-b2b86464e2b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735390875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.735390875
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2763523044
Short name T8
Test name
Test status
Simulation time 167798593917 ps
CPU time 238.89 seconds
Started Jun 21 05:09:56 PM PDT 24
Finished Jun 21 05:13:56 PM PDT 24
Peak memory 182956 kb
Host smart-b08a336f-c893-433c-a3d3-da1a7ff12bde
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763523044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2763523044
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_random.1131755183
Short name T135
Test name
Test status
Simulation time 224149770914 ps
CPU time 873.33 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:24:20 PM PDT 24
Peak memory 191164 kb
Host smart-cf5b6308-f8b0-4a4e-958f-a82eb60adf21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131755183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1131755183
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1835242093
Short name T199
Test name
Test status
Simulation time 507140646884 ps
CPU time 2346.04 seconds
Started Jun 21 05:10:02 PM PDT 24
Finished Jun 21 05:49:10 PM PDT 24
Peak memory 195540 kb
Host smart-ef5af5cf-7d12-4bb4-80e4-47cb0643234d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835242093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1835242093
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_random.1678050889
Short name T171
Test name
Test status
Simulation time 2043433863458 ps
CPU time 872.97 seconds
Started Jun 21 05:10:15 PM PDT 24
Finished Jun 21 05:24:52 PM PDT 24
Peak memory 191140 kb
Host smart-774335af-5e31-4c95-8a62-f5c17d12f914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678050889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1678050889
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.741729018
Short name T262
Test name
Test status
Simulation time 109697582000 ps
CPU time 199.52 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:13:46 PM PDT 24
Peak memory 191160 kb
Host smart-bea8b6cf-648e-4118-a262-8728b06b604c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741729018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.741729018
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3281796196
Short name T138
Test name
Test status
Simulation time 843730009456 ps
CPU time 494.79 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:18:07 PM PDT 24
Peak memory 191068 kb
Host smart-c443222c-73bc-409b-8d04-03ddbcbbcce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281796196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3281796196
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.2106768358
Short name T195
Test name
Test status
Simulation time 265457453079 ps
CPU time 414.41 seconds
Started Jun 21 05:10:38 PM PDT 24
Finished Jun 21 05:17:33 PM PDT 24
Peak memory 193280 kb
Host smart-43597be2-82cf-476b-9fe7-51aa7bbf8283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106768358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2106768358
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1353347166
Short name T152
Test name
Test status
Simulation time 367476355838 ps
CPU time 717.74 seconds
Started Jun 21 05:09:52 PM PDT 24
Finished Jun 21 05:21:52 PM PDT 24
Peak memory 195984 kb
Host smart-f78948fa-ca0a-4ee8-a914-fcccd4f7a5a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353347166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1353347166
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/136.rv_timer_random.2689088991
Short name T442
Test name
Test status
Simulation time 798519989755 ps
CPU time 1581.43 seconds
Started Jun 21 05:10:33 PM PDT 24
Finished Jun 21 05:36:55 PM PDT 24
Peak memory 191144 kb
Host smart-8007e97a-4308-43e9-ab32-66ec40cc3812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689088991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2689088991
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1179139029
Short name T157
Test name
Test status
Simulation time 803951720643 ps
CPU time 635.81 seconds
Started Jun 21 05:10:43 PM PDT 24
Finished Jun 21 05:21:20 PM PDT 24
Peak memory 191008 kb
Host smart-eda0d488-1f45-4c43-aba3-6345ea487cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179139029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1179139029
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3946783362
Short name T7
Test name
Test status
Simulation time 86899659543 ps
CPU time 195.47 seconds
Started Jun 21 05:10:58 PM PDT 24
Finished Jun 21 05:14:14 PM PDT 24
Peak memory 191136 kb
Host smart-e6f82605-f96a-4db8-b2ac-02de1ba518f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946783362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3946783362
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1126627692
Short name T319
Test name
Test status
Simulation time 536625320141 ps
CPU time 441.21 seconds
Started Jun 21 05:10:04 PM PDT 24
Finished Jun 21 05:17:27 PM PDT 24
Peak memory 191160 kb
Host smart-ebbf3175-5dee-4de4-981d-05c0ee8bd9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126627692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1126627692
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_random.2303106319
Short name T136
Test name
Test status
Simulation time 128922366028 ps
CPU time 172.48 seconds
Started Jun 21 05:09:47 PM PDT 24
Finished Jun 21 05:12:42 PM PDT 24
Peak memory 191052 kb
Host smart-4b52fcdf-7df3-4578-a975-e58174ef0c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303106319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2303106319
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3706286302
Short name T211
Test name
Test status
Simulation time 687652055336 ps
CPU time 2023.19 seconds
Started Jun 21 05:09:45 PM PDT 24
Finished Jun 21 05:43:31 PM PDT 24
Peak memory 191056 kb
Host smart-b3331fc8-e2ad-484c-817e-2de0a15d1862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706286302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3706286302
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/95.rv_timer_random.1935441167
Short name T215
Test name
Test status
Simulation time 82550197005 ps
CPU time 231.66 seconds
Started Jun 21 05:10:34 PM PDT 24
Finished Jun 21 05:14:27 PM PDT 24
Peak memory 191120 kb
Host smart-61326dbe-b3f3-434b-a251-73cf057ad4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935441167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1935441167
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.628604306
Short name T573
Test name
Test status
Simulation time 338145567 ps
CPU time 1.1 seconds
Started Jun 21 05:09:12 PM PDT 24
Finished Jun 21 05:09:16 PM PDT 24
Peak memory 195100 kb
Host smart-70a1fac6-9538-4756-b3bf-2037ef2784e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628604306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.628604306
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.323157965
Short name T295
Test name
Test status
Simulation time 607185841215 ps
CPU time 1047.1 seconds
Started Jun 21 05:09:43 PM PDT 24
Finished Jun 21 05:27:13 PM PDT 24
Peak memory 182840 kb
Host smart-87615a93-af55-48e2-a07b-793f393c746e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323157965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.323157965
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3668706693
Short name T134
Test name
Test status
Simulation time 434182004032 ps
CPU time 1259.15 seconds
Started Jun 21 05:09:47 PM PDT 24
Finished Jun 21 05:30:49 PM PDT 24
Peak memory 191136 kb
Host smart-56c4ddb9-ca54-4abb-9caf-39a454aef79a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668706693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3668706693
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.2288063022
Short name T192
Test name
Test status
Simulation time 35051657647 ps
CPU time 40.16 seconds
Started Jun 21 05:10:30 PM PDT 24
Finished Jun 21 05:11:12 PM PDT 24
Peak memory 182952 kb
Host smart-0ed7159e-9945-40a8-86b1-cbfe552b2259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288063022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2288063022
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1169537523
Short name T167
Test name
Test status
Simulation time 244742275042 ps
CPU time 982.34 seconds
Started Jun 21 05:09:56 PM PDT 24
Finished Jun 21 05:26:20 PM PDT 24
Peak memory 195336 kb
Host smart-3a1f4d5b-8938-4171-a44b-be0c07161cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169537523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1169537523
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/124.rv_timer_random.1171051379
Short name T290
Test name
Test status
Simulation time 256153839707 ps
CPU time 292.61 seconds
Started Jun 21 05:10:40 PM PDT 24
Finished Jun 21 05:15:34 PM PDT 24
Peak memory 191124 kb
Host smart-1f75ac97-4fc7-4782-aa94-f1b38e07c205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171051379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1171051379
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4039668455
Short name T235
Test name
Test status
Simulation time 77668222838 ps
CPU time 36.14 seconds
Started Jun 21 05:10:40 PM PDT 24
Finished Jun 21 05:11:18 PM PDT 24
Peak memory 194748 kb
Host smart-5bbebec2-cb36-45a4-9142-eec5d58fedb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039668455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4039668455
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3397828782
Short name T334
Test name
Test status
Simulation time 64139836359 ps
CPU time 121.83 seconds
Started Jun 21 05:10:50 PM PDT 24
Finished Jun 21 05:12:53 PM PDT 24
Peak memory 191156 kb
Host smart-ca45e5ba-317c-4da5-b83e-3ec4774b0540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397828782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3397828782
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.914923303
Short name T280
Test name
Test status
Simulation time 174559459875 ps
CPU time 82.59 seconds
Started Jun 21 05:11:01 PM PDT 24
Finished Jun 21 05:12:25 PM PDT 24
Peak memory 182852 kb
Host smart-d4d9b498-0ab5-41ff-bd02-b55ba0657b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914923303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.914923303
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3313007159
Short name T11
Test name
Test status
Simulation time 57980111931 ps
CPU time 41.18 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:10:49 PM PDT 24
Peak memory 182964 kb
Host smart-05884dae-b1a6-4ae4-b65f-ac2d8477bd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313007159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3313007159
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/194.rv_timer_random.1007137602
Short name T243
Test name
Test status
Simulation time 144056327626 ps
CPU time 220.21 seconds
Started Jun 21 05:11:09 PM PDT 24
Finished Jun 21 05:14:50 PM PDT 24
Peak memory 191136 kb
Host smart-6ac736e3-9c5b-486d-8586-9cb31c6a0ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007137602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1007137602
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3309072535
Short name T148
Test name
Test status
Simulation time 726278264779 ps
CPU time 316.57 seconds
Started Jun 21 05:11:13 PM PDT 24
Finished Jun 21 05:16:30 PM PDT 24
Peak memory 191040 kb
Host smart-5c5dcb4f-a337-4180-9b60-3bc57eed4746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309072535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3309072535
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3852582976
Short name T288
Test name
Test status
Simulation time 79641225755 ps
CPU time 438.33 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:17:25 PM PDT 24
Peak memory 191120 kb
Host smart-0f498983-8660-4495-a4be-5eef72cfde5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852582976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3852582976
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.12659460
Short name T119
Test name
Test status
Simulation time 139748285463 ps
CPU time 200.71 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:13:22 PM PDT 24
Peak memory 191084 kb
Host smart-ca5db641-b2ad-472a-9c07-70703a02a61a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12659460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.12659460
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2544606696
Short name T55
Test name
Test status
Simulation time 800379497374 ps
CPU time 163.23 seconds
Started Jun 21 05:10:32 PM PDT 24
Finished Jun 21 05:13:16 PM PDT 24
Peak memory 194556 kb
Host smart-0d868541-e2e9-4019-ae40-18a7a2b228f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544606696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2544606696
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.2719778284
Short name T71
Test name
Test status
Simulation time 85100632786 ps
CPU time 153.18 seconds
Started Jun 21 05:10:36 PM PDT 24
Finished Jun 21 05:13:10 PM PDT 24
Peak memory 191128 kb
Host smart-87faa846-47df-499f-8ab6-5eeb1c3a6204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719778284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2719778284
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.971265043
Short name T185
Test name
Test status
Simulation time 46795034261 ps
CPU time 81.44 seconds
Started Jun 21 05:10:36 PM PDT 24
Finished Jun 21 05:11:58 PM PDT 24
Peak memory 191140 kb
Host smart-0292a472-7dbc-419f-a7aa-5b1a173ce477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971265043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.971265043
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.832248009
Short name T276
Test name
Test status
Simulation time 390552496497 ps
CPU time 601.44 seconds
Started Jun 21 05:09:36 PM PDT 24
Finished Jun 21 05:19:41 PM PDT 24
Peak memory 182952 kb
Host smart-753708ca-dcd0-440f-823f-03f0983a09d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832248009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.832248009
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random.3866958102
Short name T301
Test name
Test status
Simulation time 360380471146 ps
CPU time 410.61 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:16:37 PM PDT 24
Peak memory 190956 kb
Host smart-4d8aec96-e9e3-4356-880c-5026e7573139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866958102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3866958102
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.1342848387
Short name T113
Test name
Test status
Simulation time 237760873998 ps
CPU time 186.75 seconds
Started Jun 21 05:09:48 PM PDT 24
Finished Jun 21 05:13:02 PM PDT 24
Peak memory 190956 kb
Host smart-397474fe-31b3-4ef7-bc59-70d6db4cd73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342848387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1342848387
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3871329008
Short name T303
Test name
Test status
Simulation time 259929852045 ps
CPU time 406.04 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:16:53 PM PDT 24
Peak memory 182960 kb
Host smart-7e6eb449-9155-4ef7-a81b-6ca6d18714fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871329008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3871329008
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/102.rv_timer_random.2183366013
Short name T166
Test name
Test status
Simulation time 392235653224 ps
CPU time 219.12 seconds
Started Jun 21 05:10:27 PM PDT 24
Finished Jun 21 05:14:08 PM PDT 24
Peak memory 194520 kb
Host smart-c941e2a8-f493-465e-96af-46bd6f4079ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183366013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2183366013
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2299417249
Short name T299
Test name
Test status
Simulation time 80466245731 ps
CPU time 686.02 seconds
Started Jun 21 05:10:36 PM PDT 24
Finished Jun 21 05:22:03 PM PDT 24
Peak memory 191124 kb
Host smart-eb71c32c-06fb-4a7b-ae0b-2cc4740be1f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299417249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2299417249
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2601847089
Short name T346
Test name
Test status
Simulation time 82884502572 ps
CPU time 121.59 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:11:54 PM PDT 24
Peak memory 182928 kb
Host smart-c7889750-6248-49dd-88b3-0dd429ba45d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601847089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2601847089
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_random.3597510845
Short name T177
Test name
Test status
Simulation time 543218787285 ps
CPU time 451.63 seconds
Started Jun 21 05:09:57 PM PDT 24
Finished Jun 21 05:17:30 PM PDT 24
Peak memory 191152 kb
Host smart-53167ff3-504c-4c24-bdd2-915a0fe1128b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597510845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3597510845
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2519566503
Short name T133
Test name
Test status
Simulation time 131494749817 ps
CPU time 76.92 seconds
Started Jun 21 05:10:39 PM PDT 24
Finished Jun 21 05:11:57 PM PDT 24
Peak memory 191072 kb
Host smart-7e2c9e2c-eb96-496a-92cb-4422de4b5861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519566503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2519566503
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.284004897
Short name T326
Test name
Test status
Simulation time 42876810060 ps
CPU time 82.31 seconds
Started Jun 21 05:10:39 PM PDT 24
Finished Jun 21 05:12:02 PM PDT 24
Peak memory 191068 kb
Host smart-7015a929-be2d-4e3b-9301-3e215d2d7757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284004897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.284004897
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1377866605
Short name T296
Test name
Test status
Simulation time 60559031745 ps
CPU time 82.17 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:11:23 PM PDT 24
Peak memory 182980 kb
Host smart-ca71a10e-84d9-493d-9153-c503e1a95b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377866605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1377866605
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/139.rv_timer_random.4105788295
Short name T236
Test name
Test status
Simulation time 148459959293 ps
CPU time 1685.29 seconds
Started Jun 21 05:10:42 PM PDT 24
Finished Jun 21 05:38:48 PM PDT 24
Peak memory 191140 kb
Host smart-b15d26fb-c727-44b7-bd85-19115cd77e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105788295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4105788295
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3111471017
Short name T25
Test name
Test status
Simulation time 1139262852330 ps
CPU time 380.44 seconds
Started Jun 21 05:10:43 PM PDT 24
Finished Jun 21 05:17:04 PM PDT 24
Peak memory 191148 kb
Host smart-3947da41-ea56-4e67-a6ff-f57459b1bf57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111471017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3111471017
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1539624216
Short name T250
Test name
Test status
Simulation time 184331621370 ps
CPU time 1579.34 seconds
Started Jun 21 05:10:42 PM PDT 24
Finished Jun 21 05:37:03 PM PDT 24
Peak memory 191148 kb
Host smart-5b84a5f9-5ed8-4c8d-821d-2c9be5df6dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539624216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1539624216
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.2731963612
Short name T9
Test name
Test status
Simulation time 21207769090 ps
CPU time 72.45 seconds
Started Jun 21 05:10:43 PM PDT 24
Finished Jun 21 05:11:56 PM PDT 24
Peak memory 182948 kb
Host smart-879bcfc8-a409-4d13-a982-141f378a5f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731963612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2731963612
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2505401736
Short name T329
Test name
Test status
Simulation time 53511005231 ps
CPU time 84.22 seconds
Started Jun 21 05:10:50 PM PDT 24
Finished Jun 21 05:12:15 PM PDT 24
Peak memory 191072 kb
Host smart-7360d347-d4ed-47ae-a690-b66dd9d61a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505401736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2505401736
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3629916713
Short name T256
Test name
Test status
Simulation time 88531932770 ps
CPU time 659.86 seconds
Started Jun 21 05:10:58 PM PDT 24
Finished Jun 21 05:21:59 PM PDT 24
Peak memory 191188 kb
Host smart-6b21b728-138c-4dbf-a778-5aecb5500d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629916713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3629916713
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1791293586
Short name T120
Test name
Test status
Simulation time 227373407867 ps
CPU time 576.78 seconds
Started Jun 21 05:10:57 PM PDT 24
Finished Jun 21 05:20:35 PM PDT 24
Peak memory 191060 kb
Host smart-d80e25b7-2b57-4344-b193-fdc44deea25c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791293586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1791293586
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3224246247
Short name T181
Test name
Test status
Simulation time 1368116111421 ps
CPU time 286.06 seconds
Started Jun 21 05:10:58 PM PDT 24
Finished Jun 21 05:15:45 PM PDT 24
Peak memory 191156 kb
Host smart-31bf0079-00e1-4a02-b823-e35158bbc5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224246247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3224246247
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3300848161
Short name T163
Test name
Test status
Simulation time 68224095099 ps
CPU time 241.14 seconds
Started Jun 21 05:10:59 PM PDT 24
Finished Jun 21 05:15:01 PM PDT 24
Peak memory 191168 kb
Host smart-8a2518b1-30e6-4d71-a05c-65f3830b9f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300848161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3300848161
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.631099039
Short name T1
Test name
Test status
Simulation time 265187806340 ps
CPU time 128.72 seconds
Started Jun 21 05:10:58 PM PDT 24
Finished Jun 21 05:13:08 PM PDT 24
Peak memory 191012 kb
Host smart-979c1fa9-2964-4b5f-99a7-3b3f358f85cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631099039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.631099039
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1792889887
Short name T48
Test name
Test status
Simulation time 297354495309 ps
CPU time 131.84 seconds
Started Jun 21 05:10:59 PM PDT 24
Finished Jun 21 05:13:12 PM PDT 24
Peak memory 191164 kb
Host smart-85117dc7-76f3-458c-8171-d2afb2da7c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792889887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1792889887
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2217523508
Short name T269
Test name
Test status
Simulation time 247648598860 ps
CPU time 426.35 seconds
Started Jun 21 05:11:09 PM PDT 24
Finished Jun 21 05:18:17 PM PDT 24
Peak memory 191148 kb
Host smart-90b68e3b-c000-40a7-b6bb-3ddaee828a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217523508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2217523508
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.4052701476
Short name T259
Test name
Test status
Simulation time 467834616757 ps
CPU time 226.24 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:13:47 PM PDT 24
Peak memory 182956 kb
Host smart-415f371c-3d10-4b52-a13a-1650be5b67c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052701476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.4052701476
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3810999988
Short name T97
Test name
Test status
Simulation time 27817165120 ps
CPU time 25.68 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:10:32 PM PDT 24
Peak memory 182960 kb
Host smart-cbd5b70b-3fe3-4172-b60b-7ed2da3bae96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810999988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3810999988
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.3991195699
Short name T188
Test name
Test status
Simulation time 105836325642 ps
CPU time 53.78 seconds
Started Jun 21 05:10:16 PM PDT 24
Finished Jun 21 05:11:15 PM PDT 24
Peak memory 182876 kb
Host smart-7366654d-def2-4fb8-aa00-cf91a00e3870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991195699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3991195699
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1138888893
Short name T257
Test name
Test status
Simulation time 981038292200 ps
CPU time 530.93 seconds
Started Jun 21 05:10:03 PM PDT 24
Finished Jun 21 05:18:55 PM PDT 24
Peak memory 182860 kb
Host smart-eb5c3fa8-d7eb-4fbc-82f4-12181bb4e096
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138888893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1138888893
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1980409472
Short name T115
Test name
Test status
Simulation time 52119974973 ps
CPU time 27.75 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:10:27 PM PDT 24
Peak memory 182956 kb
Host smart-4deafcfa-e763-4364-ab5b-b837119e5675
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980409472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1980409472
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2490578471
Short name T187
Test name
Test status
Simulation time 138972181928 ps
CPU time 107.17 seconds
Started Jun 21 05:10:07 PM PDT 24
Finished Jun 21 05:11:55 PM PDT 24
Peak memory 191152 kb
Host smart-f36ddb83-0ba5-41a0-bff8-18a89aee545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490578471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2490578471
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_random.2181312872
Short name T175
Test name
Test status
Simulation time 913116700138 ps
CPU time 428.03 seconds
Started Jun 21 05:10:19 PM PDT 24
Finished Jun 21 05:17:31 PM PDT 24
Peak memory 191076 kb
Host smart-7618e98f-c000-4c7c-b0cb-aa690a144bb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181312872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2181312872
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3776269562
Short name T298
Test name
Test status
Simulation time 1103958094087 ps
CPU time 1196.53 seconds
Started Jun 21 05:10:12 PM PDT 24
Finished Jun 21 05:30:10 PM PDT 24
Peak memory 191044 kb
Host smart-68779285-01ce-4be7-8a67-c86e04bd31ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776269562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3776269562
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.954130018
Short name T294
Test name
Test status
Simulation time 4279958838 ps
CPU time 42.04 seconds
Started Jun 21 05:10:25 PM PDT 24
Finished Jun 21 05:11:10 PM PDT 24
Peak memory 191284 kb
Host smart-f6106a0f-9dc8-43b4-9080-718ca73fb1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954130018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.954130018
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4085718927
Short name T114
Test name
Test status
Simulation time 2122831810945 ps
CPU time 3284.45 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 06:05:02 PM PDT 24
Peak memory 195916 kb
Host smart-2868fbef-d7dc-46c0-bd8e-3c59ef5ef09e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085718927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4085718927
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3010482197
Short name T140
Test name
Test status
Simulation time 139397987519 ps
CPU time 128.99 seconds
Started Jun 21 05:10:31 PM PDT 24
Finished Jun 21 05:12:41 PM PDT 24
Peak memory 182948 kb
Host smart-dfddfd12-4922-4de7-8797-07e22645b7d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010482197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3010482197
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1964494221
Short name T169
Test name
Test status
Simulation time 434758272726 ps
CPU time 641.48 seconds
Started Jun 21 05:10:33 PM PDT 24
Finished Jun 21 05:21:16 PM PDT 24
Peak memory 191156 kb
Host smart-82a37d94-19f0-47f0-924c-145ec600cc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964494221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1964494221
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.2151400045
Short name T146
Test name
Test status
Simulation time 188007297131 ps
CPU time 77.71 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:11:44 PM PDT 24
Peak memory 191156 kb
Host smart-250a13c8-02fd-4334-b4cc-580bc7ccf565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151400045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2151400045
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1892811389
Short name T88
Test name
Test status
Simulation time 132824768 ps
CPU time 0.71 seconds
Started Jun 21 05:09:12 PM PDT 24
Finished Jun 21 05:09:15 PM PDT 24
Peak memory 192164 kb
Host smart-85e17b02-a504-4986-92e0-58dfebb17638
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892811389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1892811389
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2981566436
Short name T86
Test name
Test status
Simulation time 834146955 ps
CPU time 3.63 seconds
Started Jun 21 05:09:11 PM PDT 24
Finished Jun 21 05:09:16 PM PDT 24
Peak memory 190992 kb
Host smart-fa44dc62-e0e8-4b11-a58f-3d8e51ffa86c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981566436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2981566436
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1903851736
Short name T50
Test name
Test status
Simulation time 40376689 ps
CPU time 0.55 seconds
Started Jun 21 05:09:11 PM PDT 24
Finished Jun 21 05:09:13 PM PDT 24
Peak memory 182120 kb
Host smart-40d7cc61-53be-4f24-b795-21222d980a06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903851736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1903851736
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2651123817
Short name T456
Test name
Test status
Simulation time 69381948 ps
CPU time 0.64 seconds
Started Jun 21 05:09:12 PM PDT 24
Finished Jun 21 05:09:15 PM PDT 24
Peak memory 192904 kb
Host smart-aec5d711-23fb-4f66-9743-555685a959d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651123817 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2651123817
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.154976557
Short name T530
Test name
Test status
Simulation time 31570660 ps
CPU time 0.54 seconds
Started Jun 21 05:09:12 PM PDT 24
Finished Jun 21 05:09:15 PM PDT 24
Peak memory 182776 kb
Host smart-f211ea16-d96e-4715-a147-695695b3fcb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154976557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.154976557
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.77093980
Short name T541
Test name
Test status
Simulation time 11870107 ps
CPU time 0.52 seconds
Started Jun 21 05:09:11 PM PDT 24
Finished Jun 21 05:09:12 PM PDT 24
Peak memory 181948 kb
Host smart-56dcad00-96d8-40a8-861c-c58670749aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77093980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.77093980
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1025133452
Short name T101
Test name
Test status
Simulation time 20543806 ps
CPU time 0.74 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:16 PM PDT 24
Peak memory 193276 kb
Host smart-98e69714-449d-4edb-af07-8f95712ecf89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025133452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1025133452
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1224731034
Short name T551
Test name
Test status
Simulation time 53736860 ps
CPU time 2.64 seconds
Started Jun 21 05:09:11 PM PDT 24
Finished Jun 21 05:09:15 PM PDT 24
Peak memory 197496 kb
Host smart-7d4a196a-1113-4049-95cb-e5cde3788280
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224731034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1224731034
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1056499454
Short name T529
Test name
Test status
Simulation time 150224241 ps
CPU time 0.98 seconds
Started Jun 21 05:09:11 PM PDT 24
Finished Jun 21 05:09:13 PM PDT 24
Peak memory 193712 kb
Host smart-ac109c83-99c8-4d74-8f5b-2bc7f0b26663
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056499454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1056499454
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.911314848
Short name T87
Test name
Test status
Simulation time 52562312 ps
CPU time 0.72 seconds
Started Jun 21 05:09:16 PM PDT 24
Finished Jun 21 05:09:21 PM PDT 24
Peak memory 182592 kb
Host smart-a53f2fc7-8537-407e-b957-3e63f995be44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911314848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.911314848
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.290310753
Short name T576
Test name
Test status
Simulation time 102231942 ps
CPU time 1.6 seconds
Started Jun 21 05:09:15 PM PDT 24
Finished Jun 21 05:09:21 PM PDT 24
Peak memory 190992 kb
Host smart-884adcf7-3b55-412a-8aa2-ea2b0dd2aeaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290310753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.290310753
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1864921681
Short name T538
Test name
Test status
Simulation time 17270511 ps
CPU time 0.59 seconds
Started Jun 21 05:09:12 PM PDT 24
Finished Jun 21 05:09:14 PM PDT 24
Peak memory 182596 kb
Host smart-88a61a8e-824c-4cc3-8fe3-f06012e664d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864921681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1864921681
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3777878391
Short name T543
Test name
Test status
Simulation time 32196302 ps
CPU time 0.63 seconds
Started Jun 21 05:09:16 PM PDT 24
Finished Jun 21 05:09:20 PM PDT 24
Peak memory 192988 kb
Host smart-394460b9-b003-4b86-a336-c518446c71e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777878391 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3777878391
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4121430998
Short name T474
Test name
Test status
Simulation time 14170586 ps
CPU time 0.58 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:16 PM PDT 24
Peak memory 182548 kb
Host smart-aecc6fe1-f2c8-46b3-8529-b5126e642cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121430998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4121430998
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2357461999
Short name T556
Test name
Test status
Simulation time 17270103 ps
CPU time 0.65 seconds
Started Jun 21 05:09:16 PM PDT 24
Finished Jun 21 05:09:20 PM PDT 24
Peak memory 192124 kb
Host smart-5c74c973-f674-49be-af71-80dc1554365d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357461999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2357461999
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1837038393
Short name T509
Test name
Test status
Simulation time 664760032 ps
CPU time 2.76 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 197496 kb
Host smart-1c90c99f-1c6c-4bb0-af91-cd31b1d7a651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837038393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1837038393
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2625007685
Short name T463
Test name
Test status
Simulation time 34828743 ps
CPU time 1.64 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 197500 kb
Host smart-b088de3a-e630-46ac-91b8-c83897f27076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625007685 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2625007685
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1914597452
Short name T461
Test name
Test status
Simulation time 24197039 ps
CPU time 0.6 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 182420 kb
Host smart-b072fe41-c96f-4057-b3f0-57c33e46f6c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914597452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1914597452
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1189152597
Short name T547
Test name
Test status
Simulation time 17821836 ps
CPU time 0.57 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 182496 kb
Host smart-fb8492c6-0727-4143-9c73-5d4470e39786
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189152597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1189152597
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3308637099
Short name T78
Test name
Test status
Simulation time 14758384 ps
CPU time 0.7 seconds
Started Jun 21 05:09:30 PM PDT 24
Finished Jun 21 05:09:34 PM PDT 24
Peak memory 192056 kb
Host smart-1dc4788e-1e64-4bce-96c6-c804e5a2f759
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308637099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3308637099
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3507953242
Short name T549
Test name
Test status
Simulation time 265910931 ps
CPU time 1.7 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:34 PM PDT 24
Peak memory 197520 kb
Host smart-0f35eef9-d665-48b9-93fb-a866154cc201
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507953242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3507953242
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2991347495
Short name T526
Test name
Test status
Simulation time 721826080 ps
CPU time 1.3 seconds
Started Jun 21 05:09:26 PM PDT 24
Finished Jun 21 05:09:30 PM PDT 24
Peak memory 195432 kb
Host smart-019e8932-469c-4343-957f-b5ee8d25c432
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991347495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2991347495
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.876621539
Short name T465
Test name
Test status
Simulation time 113177617 ps
CPU time 1.17 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 197468 kb
Host smart-60e20423-1951-4579-b66e-c228a267f834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876621539 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.876621539
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1382127344
Short name T517
Test name
Test status
Simulation time 38500106 ps
CPU time 0.61 seconds
Started Jun 21 05:09:37 PM PDT 24
Finished Jun 21 05:09:42 PM PDT 24
Peak memory 182636 kb
Host smart-b341d12e-2448-4fd0-ab66-007bd94a480a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382127344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1382127344
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3856674643
Short name T469
Test name
Test status
Simulation time 12169970 ps
CPU time 0.55 seconds
Started Jun 21 05:09:36 PM PDT 24
Finished Jun 21 05:09:41 PM PDT 24
Peak memory 181844 kb
Host smart-bbcf7007-ed89-4e87-84a4-721cb18ba6dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856674643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3856674643
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3576975342
Short name T544
Test name
Test status
Simulation time 12776456 ps
CPU time 0.6 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:32 PM PDT 24
Peak memory 191144 kb
Host smart-b3c04e35-ab72-4d7c-9fae-ab4efc6b6c39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576975342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3576975342
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3196524783
Short name T475
Test name
Test status
Simulation time 35907808 ps
CPU time 0.95 seconds
Started Jun 21 05:09:25 PM PDT 24
Finished Jun 21 05:09:26 PM PDT 24
Peak memory 197184 kb
Host smart-631a0463-e774-4c6a-b0cd-36f8c3b39093
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196524783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3196524783
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1848227906
Short name T507
Test name
Test status
Simulation time 115216519 ps
CPU time 1.35 seconds
Started Jun 21 05:09:26 PM PDT 24
Finished Jun 21 05:09:30 PM PDT 24
Peak memory 194900 kb
Host smart-17caac82-17cb-428f-a8a6-d5a806e40427
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848227906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1848227906
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3791852540
Short name T476
Test name
Test status
Simulation time 32527981 ps
CPU time 1.35 seconds
Started Jun 21 05:09:29 PM PDT 24
Finished Jun 21 05:09:35 PM PDT 24
Peak memory 197524 kb
Host smart-fd2a3b3c-510f-49d9-a1f8-58492d5d607f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791852540 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3791852540
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2527307058
Short name T502
Test name
Test status
Simulation time 42711918 ps
CPU time 0.61 seconds
Started Jun 21 05:09:35 PM PDT 24
Finished Jun 21 05:09:40 PM PDT 24
Peak memory 182652 kb
Host smart-d97613e8-0615-434b-bea9-defa29d55217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527307058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2527307058
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1851749739
Short name T516
Test name
Test status
Simulation time 16005387 ps
CPU time 0.51 seconds
Started Jun 21 05:09:43 PM PDT 24
Finished Jun 21 05:09:46 PM PDT 24
Peak memory 181864 kb
Host smart-aa8dac3b-897f-4ac3-a331-d2c2cb18291d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851749739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1851749739
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4100452463
Short name T100
Test name
Test status
Simulation time 125519172 ps
CPU time 0.84 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 193372 kb
Host smart-80fb14a1-17d1-4f43-8843-d6d5e891a7af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100452463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4100452463
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4085696806
Short name T54
Test name
Test status
Simulation time 189598618 ps
CPU time 1.16 seconds
Started Jun 21 05:09:30 PM PDT 24
Finished Jun 21 05:09:35 PM PDT 24
Peak memory 197156 kb
Host smart-598cf05c-4c82-48a0-b084-3cce39a1c297
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085696806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4085696806
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3755187145
Short name T106
Test name
Test status
Simulation time 89799368 ps
CPU time 0.87 seconds
Started Jun 21 05:09:29 PM PDT 24
Finished Jun 21 05:09:34 PM PDT 24
Peak memory 193608 kb
Host smart-dadcdd1f-6b9d-4803-a2f4-f8c22a347c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755187145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3755187145
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3711720371
Short name T532
Test name
Test status
Simulation time 53777124 ps
CPU time 0.74 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:09:47 PM PDT 24
Peak memory 194904 kb
Host smart-a2dc128d-198b-4efe-bb18-e2c5e45be7b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711720371 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3711720371
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2184976335
Short name T500
Test name
Test status
Simulation time 17939078 ps
CPU time 0.6 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:09:47 PM PDT 24
Peak memory 191748 kb
Host smart-2864bff1-1e60-4a99-a45b-59088478a16d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184976335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2184976335
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1686544799
Short name T560
Test name
Test status
Simulation time 47862685 ps
CPU time 0.55 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:31 PM PDT 24
Peak memory 182492 kb
Host smart-513a5e1c-9005-4295-929b-107f3ec6c590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686544799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1686544799
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.192235366
Short name T53
Test name
Test status
Simulation time 205603580 ps
CPU time 0.75 seconds
Started Jun 21 05:09:42 PM PDT 24
Finished Jun 21 05:09:46 PM PDT 24
Peak memory 191680 kb
Host smart-99982010-7a99-4d2a-9fd0-1566a512b0fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192235366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.192235366
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2292094199
Short name T512
Test name
Test status
Simulation time 145434489 ps
CPU time 1.94 seconds
Started Jun 21 05:09:26 PM PDT 24
Finished Jun 21 05:09:30 PM PDT 24
Peak memory 191560 kb
Host smart-21615260-d9cc-459a-96b9-9219950b1eca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292094199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2292094199
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2170038782
Short name T30
Test name
Test status
Simulation time 71181875 ps
CPU time 1.16 seconds
Started Jun 21 05:09:30 PM PDT 24
Finished Jun 21 05:09:36 PM PDT 24
Peak memory 183180 kb
Host smart-96f2c07f-ff92-4f15-b294-2ff69ca34c91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170038782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2170038782
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2110424419
Short name T558
Test name
Test status
Simulation time 119208477 ps
CPU time 1.44 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:32 PM PDT 24
Peak memory 197524 kb
Host smart-b391aded-ca8c-4d74-a202-6f9dcc177bc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110424419 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2110424419
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.4053384893
Short name T81
Test name
Test status
Simulation time 26977323 ps
CPU time 0.6 seconds
Started Jun 21 05:09:32 PM PDT 24
Finished Jun 21 05:09:37 PM PDT 24
Peak memory 182604 kb
Host smart-e0a32c47-9179-4392-a3a8-fcf8adabf1b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053384893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.4053384893
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1959009059
Short name T490
Test name
Test status
Simulation time 22733278 ps
CPU time 0.51 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:09:53 PM PDT 24
Peak memory 182440 kb
Host smart-7cd99835-4f18-4aca-ac72-66f64d80c2b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959009059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1959009059
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1602684937
Short name T52
Test name
Test status
Simulation time 23677869 ps
CPU time 0.63 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 191612 kb
Host smart-18c99b54-5c9e-46f1-bf32-6cf9331f1d6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602684937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1602684937
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1463235311
Short name T468
Test name
Test status
Simulation time 103299353 ps
CPU time 1.25 seconds
Started Jun 21 05:09:30 PM PDT 24
Finished Jun 21 05:09:35 PM PDT 24
Peak memory 196232 kb
Host smart-152af5f3-6271-47d7-bdfa-850c64403bde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463235311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1463235311
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1151521166
Short name T559
Test name
Test status
Simulation time 459194449 ps
CPU time 1.09 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 194852 kb
Host smart-e26269e0-109f-45b1-9399-fdf2e3640d57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151521166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1151521166
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2467568034
Short name T569
Test name
Test status
Simulation time 217638290 ps
CPU time 0.91 seconds
Started Jun 21 05:09:31 PM PDT 24
Finished Jun 21 05:09:36 PM PDT 24
Peak memory 197036 kb
Host smart-7a8d7efc-42df-4738-96e2-9dbd72c6482e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467568034 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2467568034
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2005318681
Short name T79
Test name
Test status
Simulation time 14054585 ps
CPU time 0.57 seconds
Started Jun 21 05:09:42 PM PDT 24
Finished Jun 21 05:09:46 PM PDT 24
Peak memory 182528 kb
Host smart-e4f9797f-6d5e-4897-925e-9f53b1581485
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005318681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2005318681
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.486293134
Short name T568
Test name
Test status
Simulation time 30188032 ps
CPU time 0.52 seconds
Started Jun 21 05:09:41 PM PDT 24
Finished Jun 21 05:09:45 PM PDT 24
Peak memory 182384 kb
Host smart-e671fc87-eaa3-45d4-a63d-958815432089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486293134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.486293134
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3419473310
Short name T486
Test name
Test status
Simulation time 72273213 ps
CPU time 0.65 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:31 PM PDT 24
Peak memory 191948 kb
Host smart-5830db89-7d75-4750-af70-29b05c551b50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419473310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3419473310
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1523878888
Short name T524
Test name
Test status
Simulation time 172082247 ps
CPU time 1.97 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:32 PM PDT 24
Peak memory 197392 kb
Host smart-8f4815ac-4d98-496c-b593-9617a166a1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523878888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1523878888
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3216003375
Short name T103
Test name
Test status
Simulation time 44297989 ps
CPU time 0.83 seconds
Started Jun 21 05:09:31 PM PDT 24
Finished Jun 21 05:09:36 PM PDT 24
Peak memory 193660 kb
Host smart-ade861af-1402-4791-90a5-0d3dc957841e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216003375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3216003375
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.138353190
Short name T521
Test name
Test status
Simulation time 29081603 ps
CPU time 1.36 seconds
Started Jun 21 05:09:43 PM PDT 24
Finished Jun 21 05:09:47 PM PDT 24
Peak memory 197432 kb
Host smart-7913d554-aa84-4cd2-a832-da15e3c91d50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138353190 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.138353190
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2385453204
Short name T51
Test name
Test status
Simulation time 27473197 ps
CPU time 0.61 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:09:47 PM PDT 24
Peak memory 191748 kb
Host smart-47f5d579-abb6-43ae-a521-678bffae6a68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385453204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2385453204
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.742426443
Short name T511
Test name
Test status
Simulation time 48745221 ps
CPU time 0.56 seconds
Started Jun 21 05:09:32 PM PDT 24
Finished Jun 21 05:09:37 PM PDT 24
Peak memory 182444 kb
Host smart-6d52b306-3fd2-482e-a788-c8c99ec27557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742426443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.742426443
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3107967784
Short name T575
Test name
Test status
Simulation time 26866757 ps
CPU time 0.71 seconds
Started Jun 21 05:09:29 PM PDT 24
Finished Jun 21 05:09:34 PM PDT 24
Peak memory 191668 kb
Host smart-2260eb8c-7b10-49bc-bc04-4af388d386e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107967784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3107967784
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3552978341
Short name T564
Test name
Test status
Simulation time 48267695 ps
CPU time 2.38 seconds
Started Jun 21 05:09:31 PM PDT 24
Finished Jun 21 05:09:38 PM PDT 24
Peak memory 197492 kb
Host smart-498e89b9-190a-4b10-a43b-4962be095df1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552978341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3552978341
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2481251325
Short name T487
Test name
Test status
Simulation time 217972629 ps
CPU time 0.83 seconds
Started Jun 21 05:09:31 PM PDT 24
Finished Jun 21 05:09:36 PM PDT 24
Peak memory 193428 kb
Host smart-a5c78bf3-7486-439d-ba88-b264e86eb80e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481251325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2481251325
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2602945018
Short name T545
Test name
Test status
Simulation time 110202469 ps
CPU time 1.22 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:38 PM PDT 24
Peak memory 197472 kb
Host smart-3d00ba87-b779-4c7e-9708-c864a1eeda45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602945018 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2602945018
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.647703934
Short name T83
Test name
Test status
Simulation time 26809696 ps
CPU time 0.59 seconds
Started Jun 21 05:09:40 PM PDT 24
Finished Jun 21 05:09:44 PM PDT 24
Peak memory 182632 kb
Host smart-52b7e837-d905-4142-8470-58524d8699ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647703934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.647703934
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.735679631
Short name T455
Test name
Test status
Simulation time 13943140 ps
CPU time 0.54 seconds
Started Jun 21 05:09:31 PM PDT 24
Finished Jun 21 05:09:36 PM PDT 24
Peak memory 182024 kb
Host smart-47cca973-1144-4d2b-94c0-5c9b40809cc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735679631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.735679631
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.562249205
Short name T494
Test name
Test status
Simulation time 144599823 ps
CPU time 0.71 seconds
Started Jun 21 05:09:39 PM PDT 24
Finished Jun 21 05:09:43 PM PDT 24
Peak memory 191628 kb
Host smart-710caa4d-c26c-4254-8b59-36582067c564
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562249205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.562249205
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3845486573
Short name T466
Test name
Test status
Simulation time 147078220 ps
CPU time 1.87 seconds
Started Jun 21 05:09:46 PM PDT 24
Finished Jun 21 05:09:51 PM PDT 24
Peak memory 197544 kb
Host smart-86f13623-4e4d-406d-819c-e9d0641ae9fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845486573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3845486573
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.470985766
Short name T533
Test name
Test status
Simulation time 259842314 ps
CPU time 1.09 seconds
Started Jun 21 05:09:33 PM PDT 24
Finished Jun 21 05:09:38 PM PDT 24
Peak memory 195056 kb
Host smart-259498b7-d876-4a66-89c2-23d6050791b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470985766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.470985766
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4194358600
Short name T505
Test name
Test status
Simulation time 24506645 ps
CPU time 0.72 seconds
Started Jun 21 05:09:37 PM PDT 24
Finished Jun 21 05:09:41 PM PDT 24
Peak memory 195360 kb
Host smart-7116289e-4712-4b8d-a169-87f04fcb890c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194358600 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4194358600
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.512544564
Short name T552
Test name
Test status
Simulation time 13411492 ps
CPU time 0.61 seconds
Started Jun 21 05:09:46 PM PDT 24
Finished Jun 21 05:09:50 PM PDT 24
Peak memory 182332 kb
Host smart-730b222b-a27c-4d60-95cd-a0caf249c69f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512544564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.512544564
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.334698997
Short name T504
Test name
Test status
Simulation time 12199000 ps
CPU time 0.56 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:37 PM PDT 24
Peak memory 182500 kb
Host smart-47a91a3e-11ae-4b1f-b14d-b07d3c1a9ba7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334698997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.334698997
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.683302574
Short name T510
Test name
Test status
Simulation time 101025900 ps
CPU time 0.69 seconds
Started Jun 21 05:09:33 PM PDT 24
Finished Jun 21 05:09:37 PM PDT 24
Peak memory 193156 kb
Host smart-1a19310e-a941-42b4-8bb5-89aadc9bdb94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683302574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.683302574
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.403750292
Short name T578
Test name
Test status
Simulation time 47492760 ps
CPU time 2.39 seconds
Started Jun 21 05:09:40 PM PDT 24
Finished Jun 21 05:09:46 PM PDT 24
Peak memory 197496 kb
Host smart-a5863dda-486b-4177-b660-5491a7cc0e36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403750292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.403750292
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3660527702
Short name T104
Test name
Test status
Simulation time 166895760 ps
CPU time 1.11 seconds
Started Jun 21 05:09:37 PM PDT 24
Finished Jun 21 05:09:42 PM PDT 24
Peak memory 194760 kb
Host smart-93a8c698-3fd4-4aeb-957c-594c1119b87b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660527702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3660527702
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2216486735
Short name T495
Test name
Test status
Simulation time 38857781 ps
CPU time 0.79 seconds
Started Jun 21 05:09:41 PM PDT 24
Finished Jun 21 05:09:45 PM PDT 24
Peak memory 195744 kb
Host smart-c7054bfd-ccf4-4794-abf5-82b9ef72483f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216486735 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2216486735
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3508449617
Short name T82
Test name
Test status
Simulation time 33905067 ps
CPU time 0.6 seconds
Started Jun 21 05:09:40 PM PDT 24
Finished Jun 21 05:09:44 PM PDT 24
Peak memory 182660 kb
Host smart-6a7360de-2fce-4b2a-b5c1-00339926c61d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508449617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3508449617
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1263681654
Short name T478
Test name
Test status
Simulation time 30217252 ps
CPU time 0.58 seconds
Started Jun 21 05:09:39 PM PDT 24
Finished Jun 21 05:09:43 PM PDT 24
Peak memory 182496 kb
Host smart-d0a59cea-e444-43d3-b347-00a815ed0b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263681654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1263681654
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4265527069
Short name T555
Test name
Test status
Simulation time 106892483 ps
CPU time 0.71 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:39 PM PDT 24
Peak memory 192604 kb
Host smart-e8a780ff-cd45-485b-9e83-c21bfea159c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265527069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4265527069
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3542130167
Short name T462
Test name
Test status
Simulation time 171274830 ps
CPU time 1.85 seconds
Started Jun 21 05:09:47 PM PDT 24
Finished Jun 21 05:09:52 PM PDT 24
Peak memory 197520 kb
Host smart-8eb012e2-a90a-4fef-a6e7-1179255c68b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542130167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3542130167
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1262833421
Short name T105
Test name
Test status
Simulation time 382497097 ps
CPU time 1.37 seconds
Started Jun 21 05:09:38 PM PDT 24
Finished Jun 21 05:09:43 PM PDT 24
Peak memory 194432 kb
Host smart-807c525d-e428-4f31-a5b1-6f34ceca4cd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262833421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1262833421
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3514554175
Short name T582
Test name
Test status
Simulation time 26729715 ps
CPU time 0.73 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:17 PM PDT 24
Peak memory 182668 kb
Host smart-948baac0-3f97-45ab-981d-906b63378406
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514554175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3514554175
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.899575286
Short name T566
Test name
Test status
Simulation time 257110373 ps
CPU time 1.67 seconds
Started Jun 21 05:09:11 PM PDT 24
Finished Jun 21 05:09:14 PM PDT 24
Peak memory 192080 kb
Host smart-fab5b28e-46c7-494e-8a60-f67b96df17fd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899575286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.899575286
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1309559756
Short name T473
Test name
Test status
Simulation time 15455419 ps
CPU time 0.53 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:19 PM PDT 24
Peak memory 182596 kb
Host smart-08c23462-b2db-42f2-aa55-b5aea62c799e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309559756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1309559756
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1094625347
Short name T513
Test name
Test status
Simulation time 61267082 ps
CPU time 0.9 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 196420 kb
Host smart-1637c004-7207-407f-80d1-374ba3b51710
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094625347 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1094625347
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1046554060
Short name T550
Test name
Test status
Simulation time 94691319 ps
CPU time 0.56 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 182596 kb
Host smart-1846e152-8c9f-4602-804a-61b7a44e430a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046554060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1046554060
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2379674770
Short name T531
Test name
Test status
Simulation time 12744355 ps
CPU time 0.54 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 182428 kb
Host smart-b43bd076-7c35-4179-8163-ebd486f1b477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379674770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2379674770
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2255469179
Short name T536
Test name
Test status
Simulation time 31269713 ps
CPU time 0.73 seconds
Started Jun 21 05:09:15 PM PDT 24
Finished Jun 21 05:09:20 PM PDT 24
Peak memory 191972 kb
Host smart-c4feb6cd-c777-4770-a1ca-0c8c67eb352b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255469179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2255469179
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1140706838
Short name T501
Test name
Test status
Simulation time 134748329 ps
CPU time 2.63 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 197496 kb
Host smart-48ae7a5b-549e-408c-a3c1-fd80d7952f84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140706838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1140706838
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.337249885
Short name T514
Test name
Test status
Simulation time 383498533 ps
CPU time 1.39 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:17 PM PDT 24
Peak memory 195512 kb
Host smart-45608a49-03cf-440f-ac56-a47b0c7b5047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337249885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.337249885
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2231885251
Short name T539
Test name
Test status
Simulation time 24348920 ps
CPU time 0.51 seconds
Started Jun 21 05:09:37 PM PDT 24
Finished Jun 21 05:09:41 PM PDT 24
Peak memory 182008 kb
Host smart-e58517eb-6d7e-4123-99b2-38d5e31cf8fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231885251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2231885251
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.893139580
Short name T458
Test name
Test status
Simulation time 34153059 ps
CPU time 0.59 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:37 PM PDT 24
Peak memory 182528 kb
Host smart-20e82f75-ebf9-48fe-9b39-7f256b9832f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893139580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.893139580
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1910473117
Short name T535
Test name
Test status
Simulation time 21297789 ps
CPU time 0.55 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:39 PM PDT 24
Peak memory 182476 kb
Host smart-f5ea01ab-70a1-461c-ba77-9feb26c86466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910473117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1910473117
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3459395077
Short name T450
Test name
Test status
Simulation time 70141236 ps
CPU time 0.55 seconds
Started Jun 21 05:09:33 PM PDT 24
Finished Jun 21 05:09:38 PM PDT 24
Peak memory 182444 kb
Host smart-873a0554-5f10-4da3-958b-df738a1d4622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459395077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3459395077
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3393643473
Short name T452
Test name
Test status
Simulation time 24006136 ps
CPU time 0.58 seconds
Started Jun 21 05:09:35 PM PDT 24
Finished Jun 21 05:09:39 PM PDT 24
Peak memory 182520 kb
Host smart-bed5c236-0e37-4613-b74e-4da07128d4e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393643473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3393643473
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4154420653
Short name T498
Test name
Test status
Simulation time 31242079 ps
CPU time 0.57 seconds
Started Jun 21 05:09:47 PM PDT 24
Finished Jun 21 05:09:50 PM PDT 24
Peak memory 182544 kb
Host smart-569f54e7-9bd0-46ff-a513-8df7136f0e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154420653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4154420653
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.744969730
Short name T537
Test name
Test status
Simulation time 16779318 ps
CPU time 0.57 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:39 PM PDT 24
Peak memory 182524 kb
Host smart-600fc105-99c1-4be5-8f01-9fdd96ad0836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744969730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.744969730
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1274130051
Short name T451
Test name
Test status
Simulation time 25569678 ps
CPU time 0.54 seconds
Started Jun 21 05:09:32 PM PDT 24
Finished Jun 21 05:09:37 PM PDT 24
Peak memory 181912 kb
Host smart-f11ce783-ea13-4fa2-8a6c-ce2c49b8f394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274130051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1274130051
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3977822742
Short name T484
Test name
Test status
Simulation time 52617557 ps
CPU time 0.53 seconds
Started Jun 21 05:09:39 PM PDT 24
Finished Jun 21 05:09:43 PM PDT 24
Peak memory 181956 kb
Host smart-d75675f5-0e5f-4740-b8f3-7b56f2fd058b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977822742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3977822742
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2546051671
Short name T580
Test name
Test status
Simulation time 36466789 ps
CPU time 0.52 seconds
Started Jun 21 05:09:54 PM PDT 24
Finished Jun 21 05:09:56 PM PDT 24
Peak memory 182444 kb
Host smart-f313504c-c44e-4136-85a0-50c3fb1737a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546051671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2546051671
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.147305491
Short name T84
Test name
Test status
Simulation time 60514070 ps
CPU time 0.79 seconds
Started Jun 21 05:09:15 PM PDT 24
Finished Jun 21 05:09:20 PM PDT 24
Peak memory 182628 kb
Host smart-4cafbb74-f584-4258-9f2e-d3dbd504c4cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147305491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.147305491
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.517320032
Short name T496
Test name
Test status
Simulation time 93284113 ps
CPU time 3.26 seconds
Started Jun 21 05:09:17 PM PDT 24
Finished Jun 21 05:09:23 PM PDT 24
Peak memory 190972 kb
Host smart-091b5040-5e4d-4937-8583-393536c6f316
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517320032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.517320032
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2478633276
Short name T523
Test name
Test status
Simulation time 44586790 ps
CPU time 0.53 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 182544 kb
Host smart-1c7c3838-8f2f-4ccc-8dc9-89e28324e101
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478633276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2478633276
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3644507019
Short name T477
Test name
Test status
Simulation time 94266176 ps
CPU time 0.87 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:19 PM PDT 24
Peak memory 196868 kb
Host smart-2a87bd20-1bb4-46fd-9d49-5e3bb59c58cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644507019 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3644507019
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3114507698
Short name T534
Test name
Test status
Simulation time 14589470 ps
CPU time 0.59 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:17 PM PDT 24
Peak memory 182656 kb
Host smart-f062ddd3-5cac-4b11-9769-fb0121c299d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114507698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3114507698
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.56125779
Short name T482
Test name
Test status
Simulation time 32717353 ps
CPU time 0.54 seconds
Started Jun 21 05:09:16 PM PDT 24
Finished Jun 21 05:09:20 PM PDT 24
Peak memory 181928 kb
Host smart-a020c983-d09e-495a-9ab6-89896d7b2109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56125779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.56125779
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.685098722
Short name T503
Test name
Test status
Simulation time 65680655 ps
CPU time 0.62 seconds
Started Jun 21 05:09:15 PM PDT 24
Finished Jun 21 05:09:20 PM PDT 24
Peak memory 191836 kb
Host smart-6b75f739-a6b7-493f-bb0e-b748061a3815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685098722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.685098722
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1899782539
Short name T581
Test name
Test status
Simulation time 144193570 ps
CPU time 1.8 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 197308 kb
Host smart-157e9dc8-e760-4005-9a10-cdba4d87c75e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899782539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1899782539
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1927465624
Short name T493
Test name
Test status
Simulation time 46452887 ps
CPU time 0.89 seconds
Started Jun 21 05:09:15 PM PDT 24
Finished Jun 21 05:09:19 PM PDT 24
Peak memory 183064 kb
Host smart-f26a53d7-987c-4ff4-8ecb-293c27129d31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927465624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1927465624
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1553629832
Short name T459
Test name
Test status
Simulation time 81931896 ps
CPU time 0.56 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:39 PM PDT 24
Peak memory 182524 kb
Host smart-d132b75a-30c9-48c4-978a-ebeb5fb40cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553629832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1553629832
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4242663508
Short name T570
Test name
Test status
Simulation time 11902647 ps
CPU time 0.51 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:09:52 PM PDT 24
Peak memory 182380 kb
Host smart-3fd8d00b-40b1-44b3-aa4d-c2951311eba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242663508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4242663508
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.438483840
Short name T480
Test name
Test status
Simulation time 51983723 ps
CPU time 0.55 seconds
Started Jun 21 05:09:39 PM PDT 24
Finished Jun 21 05:09:43 PM PDT 24
Peak memory 182496 kb
Host smart-1c062510-e6d5-4105-aa55-7fb3b44a61ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438483840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.438483840
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.4279621760
Short name T506
Test name
Test status
Simulation time 33793309 ps
CPU time 0.59 seconds
Started Jun 21 05:09:36 PM PDT 24
Finished Jun 21 05:09:41 PM PDT 24
Peak memory 182596 kb
Host smart-f5f04cff-932c-4eed-8611-a9e94b601dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279621760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.4279621760
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2068070799
Short name T519
Test name
Test status
Simulation time 31596844 ps
CPU time 0.57 seconds
Started Jun 21 05:09:48 PM PDT 24
Finished Jun 21 05:09:51 PM PDT 24
Peak memory 182548 kb
Host smart-67654bf3-78be-4e79-9e46-6001849e404d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068070799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2068070799
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.548260728
Short name T554
Test name
Test status
Simulation time 73500526 ps
CPU time 0.56 seconds
Started Jun 21 05:09:38 PM PDT 24
Finished Jun 21 05:09:42 PM PDT 24
Peak memory 182512 kb
Host smart-bb02be5b-9616-4b8a-bda0-26855720a6df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548260728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.548260728
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2364238096
Short name T481
Test name
Test status
Simulation time 101525413 ps
CPU time 0.61 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:39 PM PDT 24
Peak memory 182544 kb
Host smart-78234eda-4f49-49a4-a0ae-880c51095834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364238096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2364238096
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3612879231
Short name T567
Test name
Test status
Simulation time 93363593 ps
CPU time 0.55 seconds
Started Jun 21 05:09:48 PM PDT 24
Finished Jun 21 05:09:51 PM PDT 24
Peak memory 182592 kb
Host smart-5dea08ec-745b-44e1-9ea7-428e212fa627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612879231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3612879231
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2220568216
Short name T488
Test name
Test status
Simulation time 46254357 ps
CPU time 0.6 seconds
Started Jun 21 05:09:47 PM PDT 24
Finished Jun 21 05:09:50 PM PDT 24
Peak memory 182440 kb
Host smart-0ae275d3-7c0c-4891-91e5-6e611a0d7a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220568216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2220568216
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1345620890
Short name T457
Test name
Test status
Simulation time 20558640 ps
CPU time 0.57 seconds
Started Jun 21 05:09:33 PM PDT 24
Finished Jun 21 05:09:38 PM PDT 24
Peak memory 181932 kb
Host smart-cd21b9b3-f935-450a-8714-0d6e7aea34a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345620890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1345620890
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2676361497
Short name T489
Test name
Test status
Simulation time 25474230 ps
CPU time 0.72 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:16 PM PDT 24
Peak memory 182652 kb
Host smart-f832edbb-457e-41fa-85db-7db0b6fb3c96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676361497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2676361497
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3533421066
Short name T483
Test name
Test status
Simulation time 66227788 ps
CPU time 2.32 seconds
Started Jun 21 05:09:15 PM PDT 24
Finished Jun 21 05:09:21 PM PDT 24
Peak memory 191060 kb
Host smart-52fbfec4-3e81-477c-9c75-16ac5c95e658
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533421066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3533421066
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1899028224
Short name T80
Test name
Test status
Simulation time 15532602 ps
CPU time 0.59 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 182596 kb
Host smart-e89892b9-a95b-4045-a83f-75f088af88d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899028224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1899028224
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.538501663
Short name T485
Test name
Test status
Simulation time 79080092 ps
CPU time 0.73 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 194680 kb
Host smart-a4a81b45-caf5-4d8e-816a-d0b2b167ac2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538501663 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.538501663
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2558415593
Short name T98
Test name
Test status
Simulation time 23447170 ps
CPU time 0.57 seconds
Started Jun 21 05:09:14 PM PDT 24
Finished Jun 21 05:09:18 PM PDT 24
Peak memory 182544 kb
Host smart-70fd8859-1c0d-4334-92fd-167874020a75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558415593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2558415593
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2934418149
Short name T499
Test name
Test status
Simulation time 144925734 ps
CPU time 0.53 seconds
Started Jun 21 05:09:15 PM PDT 24
Finished Jun 21 05:09:19 PM PDT 24
Peak memory 182552 kb
Host smart-7cfa2717-1118-40db-baf9-6b4ee0a8d195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934418149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2934418149
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.397791090
Short name T33
Test name
Test status
Simulation time 51958750 ps
CPU time 0.65 seconds
Started Jun 21 05:09:12 PM PDT 24
Finished Jun 21 05:09:15 PM PDT 24
Peak memory 192060 kb
Host smart-8b3656dd-a198-4993-a032-4f640ec11f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397791090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.397791090
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2323815267
Short name T565
Test name
Test status
Simulation time 704888832 ps
CPU time 2.21 seconds
Started Jun 21 05:09:15 PM PDT 24
Finished Jun 21 05:09:21 PM PDT 24
Peak memory 196472 kb
Host smart-320b3f20-5cd3-49b5-919a-19d11ec0bc36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323815267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2323815267
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4264722268
Short name T577
Test name
Test status
Simulation time 87819702 ps
CPU time 1.13 seconds
Started Jun 21 05:09:12 PM PDT 24
Finished Jun 21 05:09:15 PM PDT 24
Peak memory 195000 kb
Host smart-130f3d8f-0cec-42d5-84f8-ba59cb1aebc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264722268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4264722268
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2483729616
Short name T571
Test name
Test status
Simulation time 67434542 ps
CPU time 0.54 seconds
Started Jun 21 05:09:37 PM PDT 24
Finished Jun 21 05:09:42 PM PDT 24
Peak memory 181944 kb
Host smart-b64a3866-ef91-4517-abea-1fcaf7c7c1b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483729616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2483729616
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1152333858
Short name T454
Test name
Test status
Simulation time 47379690 ps
CPU time 0.58 seconds
Started Jun 21 05:09:37 PM PDT 24
Finished Jun 21 05:09:42 PM PDT 24
Peak memory 182628 kb
Host smart-fc164f13-bb57-42fc-aaa9-4956378950a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152333858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1152333858
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.4126771054
Short name T508
Test name
Test status
Simulation time 16114268 ps
CPU time 0.59 seconds
Started Jun 21 05:09:35 PM PDT 24
Finished Jun 21 05:09:40 PM PDT 24
Peak memory 182628 kb
Host smart-bc022226-0aa8-4853-9039-b3358034baa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126771054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.4126771054
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1589440818
Short name T574
Test name
Test status
Simulation time 16792247 ps
CPU time 0.57 seconds
Started Jun 21 05:09:38 PM PDT 24
Finished Jun 21 05:09:43 PM PDT 24
Peak memory 182576 kb
Host smart-6eddecbf-aaa8-4071-9641-454ca0b0e35f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589440818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1589440818
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1732100154
Short name T525
Test name
Test status
Simulation time 38017783 ps
CPU time 0.55 seconds
Started Jun 21 05:09:40 PM PDT 24
Finished Jun 21 05:09:43 PM PDT 24
Peak memory 182024 kb
Host smart-21ff81be-46c1-4165-8697-6bd004d96db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732100154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1732100154
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4216604594
Short name T453
Test name
Test status
Simulation time 19276438 ps
CPU time 0.57 seconds
Started Jun 21 05:09:46 PM PDT 24
Finished Jun 21 05:09:50 PM PDT 24
Peak memory 182496 kb
Host smart-20e62c42-f9a1-4232-ab10-e2fe7b546cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216604594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.4216604594
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3391028801
Short name T527
Test name
Test status
Simulation time 11623297 ps
CPU time 0.53 seconds
Started Jun 21 05:09:40 PM PDT 24
Finished Jun 21 05:09:44 PM PDT 24
Peak memory 181956 kb
Host smart-4872dc0b-1080-48c0-adb5-8aa173fc4381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391028801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3391028801
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.533708876
Short name T563
Test name
Test status
Simulation time 26899732 ps
CPU time 0.57 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:09:47 PM PDT 24
Peak memory 182600 kb
Host smart-0d7fcf58-4994-4fba-8cc6-ecbbb6fcbfb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533708876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.533708876
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4193614988
Short name T470
Test name
Test status
Simulation time 15099573 ps
CPU time 0.55 seconds
Started Jun 21 05:09:33 PM PDT 24
Finished Jun 21 05:09:37 PM PDT 24
Peak memory 182020 kb
Host smart-f6839f61-1858-495c-b36c-f86743b9ab5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193614988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4193614988
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3110869047
Short name T472
Test name
Test status
Simulation time 40885656 ps
CPU time 0.53 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:09:54 PM PDT 24
Peak memory 182008 kb
Host smart-f12971b2-4794-4961-a44d-81b1ae46452b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110869047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3110869047
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3668359872
Short name T548
Test name
Test status
Simulation time 20287342 ps
CPU time 0.71 seconds
Started Jun 21 05:09:23 PM PDT 24
Finished Jun 21 05:09:25 PM PDT 24
Peak memory 194708 kb
Host smart-4744616c-0303-41b4-962b-cfe7b5adde42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668359872 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3668359872
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3171398706
Short name T579
Test name
Test status
Simulation time 17827127 ps
CPU time 0.61 seconds
Started Jun 21 05:09:36 PM PDT 24
Finished Jun 21 05:09:41 PM PDT 24
Peak memory 191756 kb
Host smart-63547709-25c2-4964-9677-6f75726629d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171398706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3171398706
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2868472078
Short name T528
Test name
Test status
Simulation time 37558925 ps
CPU time 0.6 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:30 PM PDT 24
Peak memory 182520 kb
Host smart-4b657c21-2986-4247-a319-5d84253659c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868472078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2868472078
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1329428120
Short name T557
Test name
Test status
Simulation time 67602499 ps
CPU time 0.62 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 191676 kb
Host smart-2fa59ba5-7bd4-4b0c-876d-4b52b1912104
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329428120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1329428120
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2093744012
Short name T518
Test name
Test status
Simulation time 559378295 ps
CPU time 2.78 seconds
Started Jun 21 05:09:13 PM PDT 24
Finished Jun 21 05:09:19 PM PDT 24
Peak memory 197444 kb
Host smart-76eb4e89-4c9a-4735-a3e0-b89fd0246de6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093744012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2093744012
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.489058493
Short name T520
Test name
Test status
Simulation time 244406826 ps
CPU time 1.46 seconds
Started Jun 21 05:09:26 PM PDT 24
Finished Jun 21 05:09:30 PM PDT 24
Peak memory 183244 kb
Host smart-03b5ced6-56d0-46ba-b9d3-2770b8d1b254
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489058493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.489058493
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3424106404
Short name T31
Test name
Test status
Simulation time 31283313 ps
CPU time 0.61 seconds
Started Jun 21 05:09:25 PM PDT 24
Finished Jun 21 05:09:26 PM PDT 24
Peak memory 193544 kb
Host smart-c5ba4489-e6b7-4aef-84ef-472a24c99f60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424106404 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3424106404
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.334818921
Short name T85
Test name
Test status
Simulation time 18289064 ps
CPU time 0.58 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:30 PM PDT 24
Peak memory 182632 kb
Host smart-f9cedbf2-546e-447a-9e54-2df0197ff256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334818921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.334818921
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1045635183
Short name T464
Test name
Test status
Simulation time 14139568 ps
CPU time 0.58 seconds
Started Jun 21 05:09:20 PM PDT 24
Finished Jun 21 05:09:22 PM PDT 24
Peak memory 182460 kb
Host smart-022367c0-bff7-437e-948c-508d93df1733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045635183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1045635183
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.4250040426
Short name T497
Test name
Test status
Simulation time 68134538 ps
CPU time 0.63 seconds
Started Jun 21 05:09:26 PM PDT 24
Finished Jun 21 05:09:29 PM PDT 24
Peak memory 191376 kb
Host smart-0b38ce44-ab30-488b-8e4b-55d749bc2636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250040426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.4250040426
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1162678474
Short name T471
Test name
Test status
Simulation time 91508208 ps
CPU time 1.17 seconds
Started Jun 21 05:09:26 PM PDT 24
Finished Jun 21 05:09:29 PM PDT 24
Peak memory 197472 kb
Host smart-518f44b5-95c8-417d-858b-3cae762085d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162678474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1162678474
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3345493139
Short name T491
Test name
Test status
Simulation time 748337340 ps
CPU time 1.22 seconds
Started Jun 21 05:09:25 PM PDT 24
Finished Jun 21 05:09:28 PM PDT 24
Peak memory 183128 kb
Host smart-911e1d5d-0d09-4990-b375-666ac3ab2ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345493139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3345493139
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1411773856
Short name T32
Test name
Test status
Simulation time 35594512 ps
CPU time 1.49 seconds
Started Jun 21 05:09:26 PM PDT 24
Finished Jun 21 05:09:30 PM PDT 24
Peak memory 197496 kb
Host smart-82df4a3b-ecd0-4a41-a5dc-3df0575f1039
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411773856 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1411773856
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3140100792
Short name T546
Test name
Test status
Simulation time 13108093 ps
CPU time 0.55 seconds
Started Jun 21 05:09:36 PM PDT 24
Finished Jun 21 05:09:41 PM PDT 24
Peak memory 182296 kb
Host smart-a3677395-5ee8-4496-b632-c8fec11c9f77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140100792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3140100792
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.982333726
Short name T460
Test name
Test status
Simulation time 14332302 ps
CPU time 0.53 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 182592 kb
Host smart-7c6d1653-af9a-49a7-a821-59a252c7ee49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982333726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.982333726
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1999164197
Short name T562
Test name
Test status
Simulation time 42768129 ps
CPU time 0.61 seconds
Started Jun 21 05:09:32 PM PDT 24
Finished Jun 21 05:09:37 PM PDT 24
Peak memory 191348 kb
Host smart-be15cbc9-f104-44b3-89e1-8f7555cb0546
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999164197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1999164197
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3560255104
Short name T479
Test name
Test status
Simulation time 178542017 ps
CPU time 1.07 seconds
Started Jun 21 05:09:29 PM PDT 24
Finished Jun 21 05:09:35 PM PDT 24
Peak memory 197484 kb
Host smart-973eb46b-df97-4de5-8229-8776fea8e724
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560255104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3560255104
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3818436320
Short name T542
Test name
Test status
Simulation time 223682469 ps
CPU time 0.68 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 194188 kb
Host smart-7c687d60-15bc-4c12-a12b-fc2ca3c98e53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818436320 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3818436320
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1985294736
Short name T540
Test name
Test status
Simulation time 18779809 ps
CPU time 0.59 seconds
Started Jun 21 05:09:30 PM PDT 24
Finished Jun 21 05:09:34 PM PDT 24
Peak memory 182656 kb
Host smart-94c0349b-e629-4361-92c0-b32a80d2a14f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985294736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1985294736
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.322664544
Short name T467
Test name
Test status
Simulation time 38832057 ps
CPU time 0.54 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:31 PM PDT 24
Peak memory 182188 kb
Host smart-0098b134-5a0e-45f0-9702-5865f0270bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322664544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.322664544
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3482680179
Short name T99
Test name
Test status
Simulation time 46386914 ps
CPU time 0.69 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 191408 kb
Host smart-4085b387-cfb8-4300-8da5-750e30f45012
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482680179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3482680179
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3376267166
Short name T492
Test name
Test status
Simulation time 1679505226 ps
CPU time 2.57 seconds
Started Jun 21 05:09:34 PM PDT 24
Finished Jun 21 05:09:41 PM PDT 24
Peak memory 197524 kb
Host smart-9e8fa00d-8909-4544-9628-229eb9167c89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376267166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3376267166
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2898153953
Short name T561
Test name
Test status
Simulation time 392827213 ps
CPU time 1.6 seconds
Started Jun 21 05:09:21 PM PDT 24
Finished Jun 21 05:09:23 PM PDT 24
Peak memory 195068 kb
Host smart-777f8e80-5867-49b1-afe0-4aba9aaed7c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898153953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2898153953
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3618571222
Short name T572
Test name
Test status
Simulation time 46996095 ps
CPU time 0.75 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 196076 kb
Host smart-41f4b0de-dc22-48e5-b097-c80e57757d10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618571222 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3618571222
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3210426879
Short name T522
Test name
Test status
Simulation time 13643441 ps
CPU time 0.53 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:30 PM PDT 24
Peak memory 182496 kb
Host smart-cf4bd043-f36c-41d3-814c-9ca35025af03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210426879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3210426879
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4243941674
Short name T515
Test name
Test status
Simulation time 13400936 ps
CPU time 0.58 seconds
Started Jun 21 05:09:26 PM PDT 24
Finished Jun 21 05:09:29 PM PDT 24
Peak memory 182728 kb
Host smart-7caee024-61d2-4e5b-bb58-8c6934dd39d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243941674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4243941674
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4064057345
Short name T102
Test name
Test status
Simulation time 17192107 ps
CPU time 0.74 seconds
Started Jun 21 05:09:27 PM PDT 24
Finished Jun 21 05:09:31 PM PDT 24
Peak memory 191676 kb
Host smart-3c0aa302-c63c-4775-9eda-df27bcd53be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064057345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.4064057345
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.777021795
Short name T553
Test name
Test status
Simulation time 868310432 ps
CPU time 2.3 seconds
Started Jun 21 05:09:25 PM PDT 24
Finished Jun 21 05:09:28 PM PDT 24
Peak memory 197512 kb
Host smart-ba3b51ff-268c-4374-a1cc-2e8a02d7b1da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777021795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.777021795
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2874836425
Short name T29
Test name
Test status
Simulation time 79210619 ps
CPU time 1.08 seconds
Started Jun 21 05:09:28 PM PDT 24
Finished Jun 21 05:09:33 PM PDT 24
Peak memory 183136 kb
Host smart-6d4a167e-6873-4ad2-a270-a7a97e16e4c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874836425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2874836425
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1876657728
Short name T349
Test name
Test status
Simulation time 80785217017 ps
CPU time 31.32 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:10:18 PM PDT 24
Peak memory 182972 kb
Host smart-699bb836-625f-471d-aff4-d47588cc3177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876657728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1876657728
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3642259764
Short name T217
Test name
Test status
Simulation time 42338277538 ps
CPU time 153.96 seconds
Started Jun 21 05:09:48 PM PDT 24
Finished Jun 21 05:12:25 PM PDT 24
Peak memory 182768 kb
Host smart-19ff7047-e117-43f6-b521-6cac46de4c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642259764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3642259764
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.2651187714
Short name T76
Test name
Test status
Simulation time 279289029189 ps
CPU time 1424.56 seconds
Started Jun 21 05:09:37 PM PDT 24
Finished Jun 21 05:33:26 PM PDT 24
Peak memory 221428 kb
Host smart-63c088f9-1338-457e-ae81-b1ea54d2530e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651187714 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2651187714
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.243703054
Short name T423
Test name
Test status
Simulation time 81411705940 ps
CPU time 115.1 seconds
Started Jun 21 05:09:38 PM PDT 24
Finished Jun 21 05:11:37 PM PDT 24
Peak memory 182872 kb
Host smart-7ba8537b-3d84-436f-aa0c-3bdb546f1d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243703054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.243703054
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2593192003
Short name T411
Test name
Test status
Simulation time 189285845324 ps
CPU time 74.87 seconds
Started Jun 21 05:09:43 PM PDT 24
Finished Jun 21 05:11:01 PM PDT 24
Peak memory 182984 kb
Host smart-0c741e8f-7f59-4ee3-98b3-8339e906e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593192003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2593192003
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.870609601
Short name T19
Test name
Test status
Simulation time 57334279 ps
CPU time 0.84 seconds
Started Jun 21 05:09:47 PM PDT 24
Finished Jun 21 05:09:50 PM PDT 24
Peak memory 213216 kb
Host smart-f7615fe5-5045-4786-a7d1-3090e267d0ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870609601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.870609601
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1689627508
Short name T351
Test name
Test status
Simulation time 26653355852 ps
CPU time 37.07 seconds
Started Jun 21 05:09:48 PM PDT 24
Finished Jun 21 05:10:28 PM PDT 24
Peak memory 182952 kb
Host smart-fa66d91a-d5e9-49ce-90c7-5bea79648502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689627508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1689627508
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3048378479
Short name T162
Test name
Test status
Simulation time 121802595470 ps
CPU time 124.72 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:12:00 PM PDT 24
Peak memory 191140 kb
Host smart-e50a604f-bf67-4314-afd8-ea3bf6003331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048378479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3048378479
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3504977357
Short name T420
Test name
Test status
Simulation time 219106417394 ps
CPU time 85.58 seconds
Started Jun 21 05:09:55 PM PDT 24
Finished Jun 21 05:11:22 PM PDT 24
Peak memory 195500 kb
Host smart-5da81f59-98e2-4b84-a70c-cabf6af096b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504977357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3504977357
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3692214
Short name T402
Test name
Test status
Simulation time 632250824163 ps
CPU time 825.65 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:23:38 PM PDT 24
Peak memory 195660 kb
Host smart-9a0de4ec-fb18-47ac-9e12-560ad911c2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.3692214
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.1350910300
Short name T227
Test name
Test status
Simulation time 156816578618 ps
CPU time 882.63 seconds
Started Jun 21 05:10:31 PM PDT 24
Finished Jun 21 05:25:15 PM PDT 24
Peak memory 191152 kb
Host smart-e34ca21b-864f-4f31-ba75-170aa0ba0c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350910300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1350910300
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1139035503
Short name T45
Test name
Test status
Simulation time 676571848189 ps
CPU time 582.42 seconds
Started Jun 21 05:10:32 PM PDT 24
Finished Jun 21 05:20:15 PM PDT 24
Peak memory 191068 kb
Host smart-2d8580f1-c3ee-4c34-b20e-e977957da5cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139035503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1139035503
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1516204537
Short name T126
Test name
Test status
Simulation time 93729035430 ps
CPU time 43.39 seconds
Started Jun 21 05:10:40 PM PDT 24
Finished Jun 21 05:11:24 PM PDT 24
Peak memory 182872 kb
Host smart-d3c7554d-8e3c-464e-a81d-60c089c3c8df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516204537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1516204537
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2128719915
Short name T240
Test name
Test status
Simulation time 197627162103 ps
CPU time 115.03 seconds
Started Jun 21 05:10:40 PM PDT 24
Finished Jun 21 05:12:36 PM PDT 24
Peak memory 191072 kb
Host smart-655ef10b-2311-4c12-bc84-c9833931d2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128719915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2128719915
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.814712948
Short name T41
Test name
Test status
Simulation time 262362186377 ps
CPU time 569.13 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:20:00 PM PDT 24
Peak memory 191144 kb
Host smart-5f6ee1b2-257b-4160-9c3a-f78fe10ec9c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814712948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.814712948
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2137243546
Short name T377
Test name
Test status
Simulation time 12817403464 ps
CPU time 20.29 seconds
Started Jun 21 05:10:33 PM PDT 24
Finished Jun 21 05:10:54 PM PDT 24
Peak memory 182840 kb
Host smart-e3846a13-9286-42a7-9131-d38c08876931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137243546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2137243546
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.4098094581
Short name T73
Test name
Test status
Simulation time 32569612015 ps
CPU time 154.49 seconds
Started Jun 21 05:10:35 PM PDT 24
Finished Jun 21 05:13:10 PM PDT 24
Peak memory 191064 kb
Host smart-e37b858b-fc05-40eb-8290-3031577f07e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098094581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.4098094581
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2611824278
Short name T387
Test name
Test status
Simulation time 510247909213 ps
CPU time 194.93 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:13:10 PM PDT 24
Peak memory 182964 kb
Host smart-1e2e7a42-eff3-4e80-821d-db6fc121ebc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611824278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2611824278
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1521389054
Short name T222
Test name
Test status
Simulation time 170770307569 ps
CPU time 401.81 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:16:34 PM PDT 24
Peak memory 191168 kb
Host smart-f49deffb-0b28-463b-86bb-9d65233cd2e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521389054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1521389054
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.212883998
Short name T124
Test name
Test status
Simulation time 91193685415 ps
CPU time 127.46 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 191152 kb
Host smart-3c4e2b58-b796-44ac-8c59-3427c916ef15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212883998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.212883998
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.1852912571
Short name T391
Test name
Test status
Simulation time 188968188532 ps
CPU time 90 seconds
Started Jun 21 05:10:36 PM PDT 24
Finished Jun 21 05:12:07 PM PDT 24
Peak memory 182948 kb
Host smart-94fb0af5-388c-4a5a-8d99-90132304d5b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852912571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1852912571
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1532319219
Short name T446
Test name
Test status
Simulation time 544099592537 ps
CPU time 95.61 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:12:07 PM PDT 24
Peak memory 182964 kb
Host smart-95a2ced5-91bb-4fe9-a874-230ddeeb7576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532319219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1532319219
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.170139559
Short name T201
Test name
Test status
Simulation time 401330832908 ps
CPU time 214.67 seconds
Started Jun 21 05:10:28 PM PDT 24
Finished Jun 21 05:14:05 PM PDT 24
Peak memory 191152 kb
Host smart-615ea6b8-eeca-47e3-896e-8137595ca552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170139559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.170139559
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4098270430
Short name T131
Test name
Test status
Simulation time 310265617900 ps
CPU time 117.55 seconds
Started Jun 21 05:10:40 PM PDT 24
Finished Jun 21 05:12:39 PM PDT 24
Peak memory 193408 kb
Host smart-f9c9dcec-1456-41c0-b613-2e77cd269aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098270430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4098270430
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2594973311
Short name T323
Test name
Test status
Simulation time 38694499026 ps
CPU time 36 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:10:36 PM PDT 24
Peak memory 182856 kb
Host smart-5575c442-32d2-49bf-8baa-b1c02baa158c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594973311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2594973311
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.4023466496
Short name T348
Test name
Test status
Simulation time 46739092262 ps
CPU time 62.81 seconds
Started Jun 21 05:09:56 PM PDT 24
Finished Jun 21 05:11:00 PM PDT 24
Peak memory 182964 kb
Host smart-cd3a0cbf-d275-4d6e-aeed-8bc8c01fbc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023466496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.4023466496
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/120.rv_timer_random.996311364
Short name T69
Test name
Test status
Simulation time 138574600661 ps
CPU time 2898.61 seconds
Started Jun 21 05:10:38 PM PDT 24
Finished Jun 21 05:58:58 PM PDT 24
Peak memory 191168 kb
Host smart-45db2ae4-5b46-44a8-8243-c387c0579509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996311364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.996311364
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.467304165
Short name T254
Test name
Test status
Simulation time 193019473415 ps
CPU time 188.31 seconds
Started Jun 21 05:10:42 PM PDT 24
Finished Jun 21 05:13:51 PM PDT 24
Peak memory 191216 kb
Host smart-8f27ae27-dabe-4369-88db-2464e1baf3e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467304165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.467304165
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.4137776551
Short name T237
Test name
Test status
Simulation time 56136020127 ps
CPU time 83.21 seconds
Started Jun 21 05:10:34 PM PDT 24
Finished Jun 21 05:11:58 PM PDT 24
Peak memory 191152 kb
Host smart-d5ced5b8-5970-4d8f-b6a4-6b3d260148bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137776551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4137776551
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.790337954
Short name T324
Test name
Test status
Simulation time 154442740319 ps
CPU time 78.01 seconds
Started Jun 21 05:10:38 PM PDT 24
Finished Jun 21 05:11:57 PM PDT 24
Peak memory 182876 kb
Host smart-818fc13c-65bd-4ec1-9c7a-d5a2394770b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790337954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.790337954
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.157371947
Short name T137
Test name
Test status
Simulation time 120229872014 ps
CPU time 106.97 seconds
Started Jun 21 05:10:34 PM PDT 24
Finished Jun 21 05:12:22 PM PDT 24
Peak memory 191160 kb
Host smart-3f77007c-3673-4cec-b562-f2db21e7222b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157371947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.157371947
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.969771016
Short name T440
Test name
Test status
Simulation time 1354708593829 ps
CPU time 755.28 seconds
Started Jun 21 05:09:53 PM PDT 24
Finished Jun 21 05:22:30 PM PDT 24
Peak memory 182808 kb
Host smart-e4d897b7-6933-46ac-a351-280235f0b31f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969771016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.969771016
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3104603562
Short name T392
Test name
Test status
Simulation time 488078195221 ps
CPU time 181.78 seconds
Started Jun 21 05:09:52 PM PDT 24
Finished Jun 21 05:12:57 PM PDT 24
Peak memory 182888 kb
Host smart-c74e43f2-2b16-44b6-8209-0352c28589f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104603562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3104603562
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/130.rv_timer_random.3345233972
Short name T150
Test name
Test status
Simulation time 731132808541 ps
CPU time 1995.5 seconds
Started Jun 21 05:10:34 PM PDT 24
Finished Jun 21 05:43:51 PM PDT 24
Peak memory 193592 kb
Host smart-ebeb7fe0-4756-4dfb-b2a6-021eb55f4c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345233972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3345233972
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2343272405
Short name T249
Test name
Test status
Simulation time 201888736271 ps
CPU time 280.02 seconds
Started Jun 21 05:10:33 PM PDT 24
Finished Jun 21 05:15:14 PM PDT 24
Peak memory 191152 kb
Host smart-93f3d112-b52d-4d3d-8451-f04ce5560b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343272405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2343272405
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1683573445
Short name T311
Test name
Test status
Simulation time 100660662817 ps
CPU time 1717.74 seconds
Started Jun 21 05:10:40 PM PDT 24
Finished Jun 21 05:39:19 PM PDT 24
Peak memory 182740 kb
Host smart-39c5769f-10f1-4e45-970b-dc1ecbba99a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683573445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1683573445
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3907525832
Short name T155
Test name
Test status
Simulation time 379766705610 ps
CPU time 527.1 seconds
Started Jun 21 05:10:40 PM PDT 24
Finished Jun 21 05:19:28 PM PDT 24
Peak memory 190872 kb
Host smart-aebb03fb-67b9-4bce-8e92-6b56274788b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907525832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3907525832
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1017583919
Short name T336
Test name
Test status
Simulation time 505402804404 ps
CPU time 180.76 seconds
Started Jun 21 05:10:41 PM PDT 24
Finished Jun 21 05:13:43 PM PDT 24
Peak memory 193388 kb
Host smart-303b5bac-1f7c-4b45-b599-3791aa40482b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017583919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1017583919
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2712772030
Short name T231
Test name
Test status
Simulation time 53911607414 ps
CPU time 45.54 seconds
Started Jun 21 05:10:45 PM PDT 24
Finished Jun 21 05:11:32 PM PDT 24
Peak memory 191124 kb
Host smart-e8e51afe-bb61-44bf-ae09-db7cc2610817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712772030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2712772030
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.918790877
Short name T173
Test name
Test status
Simulation time 689446930234 ps
CPU time 196.87 seconds
Started Jun 21 05:09:51 PM PDT 24
Finished Jun 21 05:13:11 PM PDT 24
Peak memory 182948 kb
Host smart-ac7f160b-ea79-4be8-96ac-1caab8f4377f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918790877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.918790877
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3188038329
Short name T413
Test name
Test status
Simulation time 127376052531 ps
CPU time 99.54 seconds
Started Jun 21 05:09:56 PM PDT 24
Finished Jun 21 05:11:36 PM PDT 24
Peak memory 182956 kb
Host smart-72e65e76-2145-4e7d-9b17-00bd13f3f028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188038329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3188038329
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3949648507
Short name T47
Test name
Test status
Simulation time 423768574629 ps
CPU time 385.54 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:16:25 PM PDT 24
Peak memory 191144 kb
Host smart-f928ad7e-e522-459f-94b3-910fa2560933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949648507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3949648507
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1974499617
Short name T388
Test name
Test status
Simulation time 172442189 ps
CPU time 0.66 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:09:54 PM PDT 24
Peak memory 182588 kb
Host smart-5af88b3f-766b-4c19-93d9-22c704c53985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974499617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1974499617
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2114391565
Short name T118
Test name
Test status
Simulation time 356847927650 ps
CPU time 423.37 seconds
Started Jun 21 05:09:51 PM PDT 24
Finished Jun 21 05:16:57 PM PDT 24
Peak memory 195524 kb
Host smart-2a2a03b9-5607-4210-b623-6ac4b8e240d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114391565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2114391565
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.2863463579
Short name T225
Test name
Test status
Simulation time 19969771369 ps
CPU time 29.66 seconds
Started Jun 21 05:10:42 PM PDT 24
Finished Jun 21 05:11:13 PM PDT 24
Peak memory 182940 kb
Host smart-306a91ae-9e05-4d67-90e2-8084bb0737df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863463579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2863463579
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1864194353
Short name T208
Test name
Test status
Simulation time 245208627383 ps
CPU time 77.78 seconds
Started Jun 21 05:10:42 PM PDT 24
Finished Jun 21 05:12:01 PM PDT 24
Peak memory 182964 kb
Host smart-4f395d56-8f9a-4b70-b642-ac046d4117aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864194353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1864194353
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1099469549
Short name T441
Test name
Test status
Simulation time 104845497150 ps
CPU time 87.95 seconds
Started Jun 21 05:10:43 PM PDT 24
Finished Jun 21 05:12:12 PM PDT 24
Peak memory 182948 kb
Host smart-e5b04868-23a0-45bb-a5a2-ad88441bbe8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099469549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1099469549
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2834579626
Short name T447
Test name
Test status
Simulation time 78523080408 ps
CPU time 525.14 seconds
Started Jun 21 05:10:46 PM PDT 24
Finished Jun 21 05:19:32 PM PDT 24
Peak memory 194652 kb
Host smart-852e24d3-3d98-45e5-90bf-de7b377e1018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834579626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2834579626
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1571696953
Short name T244
Test name
Test status
Simulation time 197588190818 ps
CPU time 505.63 seconds
Started Jun 21 05:10:46 PM PDT 24
Finished Jun 21 05:19:12 PM PDT 24
Peak memory 191048 kb
Host smart-280f8f1f-94b6-4aca-96ac-f111e8d55252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571696953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1571696953
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2720102703
Short name T313
Test name
Test status
Simulation time 11678284872 ps
CPU time 19.42 seconds
Started Jun 21 05:10:42 PM PDT 24
Finished Jun 21 05:11:03 PM PDT 24
Peak memory 182924 kb
Host smart-861f9eba-f005-4bb3-8e6e-7ca8d6f8b410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720102703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2720102703
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3861981656
Short name T285
Test name
Test status
Simulation time 71235528804 ps
CPU time 33.27 seconds
Started Jun 21 05:10:41 PM PDT 24
Finished Jun 21 05:11:15 PM PDT 24
Peak memory 182948 kb
Host smart-d9cbed1a-47be-4cf5-af2c-6e9e22fd04ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861981656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3861981656
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3012221087
Short name T202
Test name
Test status
Simulation time 119434066634 ps
CPU time 52.3 seconds
Started Jun 21 05:09:53 PM PDT 24
Finished Jun 21 05:10:47 PM PDT 24
Peak memory 182804 kb
Host smart-12f980ce-da6c-42b9-9ce5-ff6a85f62a02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012221087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3012221087
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.4130665652
Short name T44
Test name
Test status
Simulation time 240322321846 ps
CPU time 88.43 seconds
Started Jun 21 05:09:52 PM PDT 24
Finished Jun 21 05:11:22 PM PDT 24
Peak memory 182968 kb
Host smart-1939c7b3-890d-43e9-8ef8-5e2c6d61e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130665652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.4130665652
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.4034439936
Short name T159
Test name
Test status
Simulation time 85549524361 ps
CPU time 128.47 seconds
Started Jun 21 05:09:52 PM PDT 24
Finished Jun 21 05:12:03 PM PDT 24
Peak memory 191076 kb
Host smart-fb9cddab-5de0-4ba8-96cf-199943ee40d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034439936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4034439936
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2707456757
Short name T412
Test name
Test status
Simulation time 203196170672 ps
CPU time 96.38 seconds
Started Jun 21 05:09:57 PM PDT 24
Finished Jun 21 05:11:35 PM PDT 24
Peak memory 191172 kb
Host smart-92ad7527-305f-4773-8723-0a461bc45d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707456757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2707456757
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3977106207
Short name T378
Test name
Test status
Simulation time 103793889242 ps
CPU time 147.67 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:12:28 PM PDT 24
Peak memory 182912 kb
Host smart-af31e7d6-1637-4626-87ea-14416ee6be08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977106207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3977106207
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.820929132
Short name T38
Test name
Test status
Simulation time 54193889538 ps
CPU time 386.54 seconds
Started Jun 21 05:09:53 PM PDT 24
Finished Jun 21 05:16:21 PM PDT 24
Peak memory 205856 kb
Host smart-0ca07f88-afa7-439a-a0ea-3fd3e8833b29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820929132 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.820929132
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.705211108
Short name T278
Test name
Test status
Simulation time 119273800922 ps
CPU time 86.6 seconds
Started Jun 21 05:10:49 PM PDT 24
Finished Jun 21 05:12:17 PM PDT 24
Peak memory 191160 kb
Host smart-eb867fd7-7ca7-4e1a-9be8-ca4fc062c8d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705211108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.705211108
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3916127516
Short name T405
Test name
Test status
Simulation time 32135969516 ps
CPU time 46.58 seconds
Started Jun 21 05:10:49 PM PDT 24
Finished Jun 21 05:11:36 PM PDT 24
Peak memory 182948 kb
Host smart-685ffcaf-8fb9-4074-bcc6-e0dd1aa061c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916127516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3916127516
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1535870626
Short name T141
Test name
Test status
Simulation time 338096489671 ps
CPU time 134.43 seconds
Started Jun 21 05:10:51 PM PDT 24
Finished Jun 21 05:13:07 PM PDT 24
Peak memory 183076 kb
Host smart-64d7a0fd-66b5-4e0b-9a21-ff882fd2c0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535870626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1535870626
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2249195019
Short name T214
Test name
Test status
Simulation time 107702686169 ps
CPU time 329.47 seconds
Started Jun 21 05:10:50 PM PDT 24
Finished Jun 21 05:16:20 PM PDT 24
Peak memory 191164 kb
Host smart-bf2d33a4-9e38-4e73-867e-e18729848dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249195019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2249195019
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2524282140
Short name T320
Test name
Test status
Simulation time 261371955577 ps
CPU time 196.14 seconds
Started Jun 21 05:10:52 PM PDT 24
Finished Jun 21 05:14:09 PM PDT 24
Peak memory 191136 kb
Host smart-0c4cdce2-2489-4aa2-a325-599997c6570a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524282140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2524282140
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1509628079
Short name T49
Test name
Test status
Simulation time 93859469987 ps
CPU time 105.62 seconds
Started Jun 21 05:10:50 PM PDT 24
Finished Jun 21 05:12:36 PM PDT 24
Peak memory 191072 kb
Host smart-89c05410-1f17-4d87-8143-276245d4300e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509628079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1509628079
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3996886707
Short name T174
Test name
Test status
Simulation time 461074325482 ps
CPU time 176.46 seconds
Started Jun 21 05:10:49 PM PDT 24
Finished Jun 21 05:13:46 PM PDT 24
Peak memory 191164 kb
Host smart-53ee2fa3-b887-48f0-8e57-38ee86b62c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996886707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3996886707
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2235798066
Short name T268
Test name
Test status
Simulation time 318655437839 ps
CPU time 949.99 seconds
Started Jun 21 05:10:51 PM PDT 24
Finished Jun 21 05:26:42 PM PDT 24
Peak memory 191076 kb
Host smart-ed66d137-3a7f-4d0a-8f12-4700ebfd7f3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235798066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2235798066
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4035542161
Short name T260
Test name
Test status
Simulation time 3375354407 ps
CPU time 2.25 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:10:01 PM PDT 24
Peak memory 183088 kb
Host smart-aa19340d-03d1-4b12-b5a3-5aebe6c05a3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035542161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4035542161
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2235576662
Short name T370
Test name
Test status
Simulation time 492246145144 ps
CPU time 159.78 seconds
Started Jun 21 05:09:56 PM PDT 24
Finished Jun 21 05:12:36 PM PDT 24
Peak memory 182976 kb
Host smart-c5293211-1165-4a96-ab13-6ed9963c4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235576662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2235576662
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.4054666201
Short name T197
Test name
Test status
Simulation time 352531639988 ps
CPU time 257.16 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:14:18 PM PDT 24
Peak memory 191068 kb
Host smart-c943010f-3c9e-4f5b-a846-3bf33c9b4144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054666201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4054666201
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.909579549
Short name T312
Test name
Test status
Simulation time 16349243734 ps
CPU time 11.52 seconds
Started Jun 21 05:09:57 PM PDT 24
Finished Jun 21 05:10:10 PM PDT 24
Peak memory 191168 kb
Host smart-f0678b76-3655-45b6-8cd6-426403c2e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909579549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.909579549
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2343712392
Short name T332
Test name
Test status
Simulation time 236009428092 ps
CPU time 2300.53 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:48:21 PM PDT 24
Peak memory 195016 kb
Host smart-41355cba-9db7-430c-b31d-0ee037d1ebde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343712392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2343712392
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.663152185
Short name T40
Test name
Test status
Simulation time 7190984859 ps
CPU time 59.06 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:10:58 PM PDT 24
Peak memory 197648 kb
Host smart-c0aec16b-1af4-479d-83e7-7df0c9381b47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663152185 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.663152185
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.3853742255
Short name T128
Test name
Test status
Simulation time 115269278429 ps
CPU time 458.09 seconds
Started Jun 21 05:10:50 PM PDT 24
Finished Jun 21 05:18:29 PM PDT 24
Peak memory 191104 kb
Host smart-88716121-8610-44d2-b00b-5f43b09ab9dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853742255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3853742255
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1634346322
Short name T436
Test name
Test status
Simulation time 275750703245 ps
CPU time 1761.42 seconds
Started Jun 21 05:10:51 PM PDT 24
Finished Jun 21 05:40:13 PM PDT 24
Peak memory 191072 kb
Host smart-87b498ec-e665-4106-b954-8d30d7cead83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634346322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1634346322
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.865883010
Short name T234
Test name
Test status
Simulation time 287185998766 ps
CPU time 123.37 seconds
Started Jun 21 05:10:48 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 191076 kb
Host smart-5c4c29c0-200e-49c1-85a3-709c9051161a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865883010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.865883010
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3336939031
Short name T191
Test name
Test status
Simulation time 126036021461 ps
CPU time 214.31 seconds
Started Jun 21 05:10:52 PM PDT 24
Finished Jun 21 05:14:27 PM PDT 24
Peak memory 192412 kb
Host smart-1c04d0cb-3bc0-461c-bdaa-810d185aa59a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336939031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3336939031
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.755315455
Short name T335
Test name
Test status
Simulation time 89569782458 ps
CPU time 133.6 seconds
Started Jun 21 05:10:51 PM PDT 24
Finished Jun 21 05:13:06 PM PDT 24
Peak memory 191288 kb
Host smart-a64eeeaa-9d3c-4a33-9700-beb143d1193e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755315455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.755315455
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.733789682
Short name T300
Test name
Test status
Simulation time 66442149565 ps
CPU time 53.52 seconds
Started Jun 21 05:10:58 PM PDT 24
Finished Jun 21 05:11:53 PM PDT 24
Peak memory 182952 kb
Host smart-1c52378b-8606-42fe-b41b-aa7a93f1a650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733789682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.733789682
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1590871235
Short name T325
Test name
Test status
Simulation time 98703607238 ps
CPU time 85.73 seconds
Started Jun 21 05:10:59 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 191160 kb
Host smart-4098e494-f9c9-4689-bda4-89f89d5e55af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590871235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1590871235
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.554837085
Short name T154
Test name
Test status
Simulation time 183425162138 ps
CPU time 164.23 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 183088 kb
Host smart-c2736298-84b7-4fd8-abdd-8a5c9b8ad435
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554837085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.554837085
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1571943946
Short name T433
Test name
Test status
Simulation time 577560471326 ps
CPU time 126.18 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:12:05 PM PDT 24
Peak memory 182864 kb
Host smart-f9ee7334-9658-4513-afcb-ddfe46482659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571943946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1571943946
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3398022706
Short name T432
Test name
Test status
Simulation time 812928311 ps
CPU time 1.13 seconds
Started Jun 21 05:09:58 PM PDT 24
Finished Jun 21 05:10:02 PM PDT 24
Peak memory 182716 kb
Host smart-11a77a12-54d7-4983-bffd-5dde6fe6a91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398022706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3398022706
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2682877707
Short name T39
Test name
Test status
Simulation time 79186431948 ps
CPU time 254.28 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:14:16 PM PDT 24
Peak memory 197664 kb
Host smart-2bb55a10-d6c9-43a5-87ca-4186beb144a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682877707 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2682877707
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2389983212
Short name T255
Test name
Test status
Simulation time 113454567245 ps
CPU time 231.98 seconds
Started Jun 21 05:10:57 PM PDT 24
Finished Jun 21 05:14:50 PM PDT 24
Peak memory 191140 kb
Host smart-a2889752-d35b-4ec8-ba35-71d6f65ba2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389983212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2389983212
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1678163954
Short name T61
Test name
Test status
Simulation time 673610160400 ps
CPU time 596.64 seconds
Started Jun 21 05:10:57 PM PDT 24
Finished Jun 21 05:20:55 PM PDT 24
Peak memory 191064 kb
Host smart-4c9e0fe3-882c-4143-8659-aeed4c300f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678163954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1678163954
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3904763440
Short name T186
Test name
Test status
Simulation time 18282067532 ps
CPU time 31.94 seconds
Started Jun 21 05:10:59 PM PDT 24
Finished Jun 21 05:11:32 PM PDT 24
Peak memory 182940 kb
Host smart-6b33d8b7-2653-4d10-965d-efbfe91a1b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904763440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3904763440
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1389023879
Short name T342
Test name
Test status
Simulation time 990837069831 ps
CPU time 2085.42 seconds
Started Jun 21 05:10:58 PM PDT 24
Finished Jun 21 05:45:44 PM PDT 24
Peak memory 191052 kb
Host smart-983b06fc-2e68-4bda-9aaa-17b26f24c47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389023879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1389023879
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.554789125
Short name T261
Test name
Test status
Simulation time 52384950775 ps
CPU time 17.83 seconds
Started Jun 21 05:11:00 PM PDT 24
Finished Jun 21 05:11:19 PM PDT 24
Peak memory 191520 kb
Host smart-8bebc173-9216-49d9-be08-c951f6c522b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554789125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.554789125
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1466559607
Short name T353
Test name
Test status
Simulation time 279650693157 ps
CPU time 115.31 seconds
Started Jun 21 05:09:57 PM PDT 24
Finished Jun 21 05:11:54 PM PDT 24
Peak memory 182964 kb
Host smart-bbeed8da-1a49-4c6b-890a-295ffc255b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466559607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1466559607
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2155658006
Short name T203
Test name
Test status
Simulation time 112079533782 ps
CPU time 93.19 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:11:34 PM PDT 24
Peak memory 191076 kb
Host smart-ba464c7a-dcc9-4718-a2ad-f566b76cb41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155658006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2155658006
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2521673377
Short name T218
Test name
Test status
Simulation time 502972387457 ps
CPU time 357.85 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:15:59 PM PDT 24
Peak memory 182960 kb
Host smart-84eb19ed-bb8b-4096-bd8f-10f7a494fa81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521673377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2521673377
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.194046721
Short name T431
Test name
Test status
Simulation time 58471964246 ps
CPU time 495.01 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:18:16 PM PDT 24
Peak memory 205840 kb
Host smart-a70d6069-5e92-449a-abeb-14a01cafea80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194046721 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.194046721
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.4030562312
Short name T90
Test name
Test status
Simulation time 39214996008 ps
CPU time 107.99 seconds
Started Jun 21 05:11:01 PM PDT 24
Finished Jun 21 05:12:49 PM PDT 24
Peak memory 192768 kb
Host smart-59b7e278-9f25-4292-bc80-a740642c81a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030562312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4030562312
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3885311679
Short name T345
Test name
Test status
Simulation time 654797048718 ps
CPU time 933.8 seconds
Started Jun 21 05:11:01 PM PDT 24
Finished Jun 21 05:26:36 PM PDT 24
Peak memory 191048 kb
Host smart-006cb7c7-d9bb-4723-95be-1fb1ee758bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885311679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3885311679
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1583638775
Short name T306
Test name
Test status
Simulation time 86592302700 ps
CPU time 641.51 seconds
Started Jun 21 05:11:11 PM PDT 24
Finished Jun 21 05:21:53 PM PDT 24
Peak memory 191064 kb
Host smart-fa6c7ce4-526d-406f-9e46-8fd0033edd98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583638775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1583638775
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3182169867
Short name T399
Test name
Test status
Simulation time 9110639650 ps
CPU time 4.3 seconds
Started Jun 21 05:11:12 PM PDT 24
Finished Jun 21 05:11:17 PM PDT 24
Peak memory 182948 kb
Host smart-881cf041-4ce1-401f-b97d-224460bf985a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182169867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3182169867
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2313629786
Short name T168
Test name
Test status
Simulation time 800524918154 ps
CPU time 312.91 seconds
Started Jun 21 05:11:10 PM PDT 24
Finished Jun 21 05:16:24 PM PDT 24
Peak memory 191148 kb
Host smart-c50b5d6f-652d-4e9e-9bd9-f9e0f86b2679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313629786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2313629786
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.215653478
Short name T238
Test name
Test status
Simulation time 8931858461 ps
CPU time 14.57 seconds
Started Jun 21 05:10:00 PM PDT 24
Finished Jun 21 05:10:16 PM PDT 24
Peak memory 182872 kb
Host smart-74fd72c2-4208-4f4c-be8c-355b3f2f5895
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215653478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.215653478
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.261905720
Short name T363
Test name
Test status
Simulation time 30461205402 ps
CPU time 20.42 seconds
Started Jun 21 05:09:57 PM PDT 24
Finished Jun 21 05:10:19 PM PDT 24
Peak memory 182876 kb
Host smart-5a8ad808-d9e4-4aa0-bfd2-4de416781b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261905720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.261905720
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2642671645
Short name T6
Test name
Test status
Simulation time 94554356303 ps
CPU time 77.95 seconds
Started Jun 21 05:09:57 PM PDT 24
Finished Jun 21 05:11:22 PM PDT 24
Peak memory 191152 kb
Host smart-e0da0f12-b3a4-439c-a0b2-a1380fe09198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642671645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2642671645
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3688173365
Short name T68
Test name
Test status
Simulation time 142371165090 ps
CPU time 429.82 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:17:10 PM PDT 24
Peak memory 191172 kb
Host smart-f1df0d65-7e72-4d99-89df-f7cece7d1889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688173365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3688173365
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.557269197
Short name T232
Test name
Test status
Simulation time 181316081187 ps
CPU time 458.05 seconds
Started Jun 21 05:11:10 PM PDT 24
Finished Jun 21 05:18:50 PM PDT 24
Peak memory 191164 kb
Host smart-77c854b6-8044-4892-9406-4bdbe09806ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557269197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.557269197
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.4225551575
Short name T60
Test name
Test status
Simulation time 262498854651 ps
CPU time 997.66 seconds
Started Jun 21 05:11:11 PM PDT 24
Finished Jun 21 05:27:49 PM PDT 24
Peak memory 191148 kb
Host smart-825a935e-cf3e-4baf-a72d-2687f4761d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225551575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.4225551575
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.69426506
Short name T314
Test name
Test status
Simulation time 40480965137 ps
CPU time 50 seconds
Started Jun 21 05:11:11 PM PDT 24
Finished Jun 21 05:12:03 PM PDT 24
Peak memory 182932 kb
Host smart-7e763f35-013f-41c7-a4ee-3a29c19a6cdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69426506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.69426506
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1379201114
Short name T282
Test name
Test status
Simulation time 100601270152 ps
CPU time 340.33 seconds
Started Jun 21 05:11:11 PM PDT 24
Finished Jun 21 05:16:52 PM PDT 24
Peak memory 191160 kb
Host smart-753313cb-a309-4f7a-9621-4ab8bf223581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379201114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1379201114
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.930446721
Short name T246
Test name
Test status
Simulation time 1412205268915 ps
CPU time 1461.57 seconds
Started Jun 21 05:11:10 PM PDT 24
Finished Jun 21 05:35:33 PM PDT 24
Peak memory 191164 kb
Host smart-5a13a8b9-dbdb-4085-9a4b-9a877783019e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930446721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.930446721
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1048356867
Short name T74
Test name
Test status
Simulation time 100775399112 ps
CPU time 866.89 seconds
Started Jun 21 05:11:10 PM PDT 24
Finished Jun 21 05:25:38 PM PDT 24
Peak memory 191124 kb
Host smart-44153b77-ebe7-44db-a153-9162edfe0dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048356867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1048356867
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3257390424
Short name T182
Test name
Test status
Simulation time 452662934735 ps
CPU time 402.53 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:16:35 PM PDT 24
Peak memory 182972 kb
Host smart-3e2d6534-57bb-4520-a874-52faa4e08529
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257390424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3257390424
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2839994708
Short name T444
Test name
Test status
Simulation time 105228469366 ps
CPU time 157.49 seconds
Started Jun 21 05:09:43 PM PDT 24
Finished Jun 21 05:12:23 PM PDT 24
Peak memory 182968 kb
Host smart-979f112a-373d-412f-8f4d-8fb10e3d181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839994708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2839994708
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1350076642
Short name T194
Test name
Test status
Simulation time 194157270088 ps
CPU time 341.74 seconds
Started Jun 21 05:09:43 PM PDT 24
Finished Jun 21 05:15:28 PM PDT 24
Peak memory 191152 kb
Host smart-eb6fd483-3cd5-4def-b889-231af7557c61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350076642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1350076642
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3432852793
Short name T355
Test name
Test status
Simulation time 62205430 ps
CPU time 0.64 seconds
Started Jun 21 05:09:42 PM PDT 24
Finished Jun 21 05:09:46 PM PDT 24
Peak memory 182700 kb
Host smart-d75e50fc-27c4-4e89-8cb1-3e73c5e6c4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432852793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3432852793
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2193306674
Short name T18
Test name
Test status
Simulation time 53340315 ps
CPU time 0.84 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:09:53 PM PDT 24
Peak memory 213148 kb
Host smart-d719b169-0519-49ea-8cf6-80b872c4d9ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193306674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2193306674
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2681374395
Short name T383
Test name
Test status
Simulation time 59347327662 ps
CPU time 26.42 seconds
Started Jun 21 05:10:02 PM PDT 24
Finished Jun 21 05:10:30 PM PDT 24
Peak memory 182864 kb
Host smart-6f5b9b86-c986-4a0c-b881-3b0e155456e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681374395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2681374395
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3756597326
Short name T322
Test name
Test status
Simulation time 847004080159 ps
CPU time 408.74 seconds
Started Jun 21 05:10:00 PM PDT 24
Finished Jun 21 05:16:51 PM PDT 24
Peak memory 192180 kb
Host smart-a7ca5f70-86a2-4e45-950e-d303b62d689f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756597326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3756597326
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.459561176
Short name T226
Test name
Test status
Simulation time 110687722078 ps
CPU time 197.36 seconds
Started Jun 21 05:10:04 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 191072 kb
Host smart-2178c749-2cb8-4e22-8f70-3d3668e613d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459561176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
459561176
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2240303984
Short name T271
Test name
Test status
Simulation time 2359662899341 ps
CPU time 662.61 seconds
Started Jun 21 05:10:00 PM PDT 24
Finished Jun 21 05:21:05 PM PDT 24
Peak memory 182808 kb
Host smart-c03d5cdc-7ac4-4aae-9db8-20c5e2d1b120
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240303984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2240303984
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3729083379
Short name T397
Test name
Test status
Simulation time 69662246297 ps
CPU time 91.05 seconds
Started Jun 21 05:10:00 PM PDT 24
Finished Jun 21 05:11:33 PM PDT 24
Peak memory 182976 kb
Host smart-104d702f-db6d-4f82-a90c-985a5baa3a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729083379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3729083379
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3130644356
Short name T309
Test name
Test status
Simulation time 32564258659 ps
CPU time 40.1 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:10:41 PM PDT 24
Peak memory 182776 kb
Host smart-82e30f94-1133-4c48-89da-88428be8dd1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130644356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3130644356
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1015095172
Short name T307
Test name
Test status
Simulation time 29365029987 ps
CPU time 239.16 seconds
Started Jun 21 05:10:03 PM PDT 24
Finished Jun 21 05:14:04 PM PDT 24
Peak memory 193284 kb
Host smart-4a463410-ff93-4dee-968b-bc341c2b50a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015095172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1015095172
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.549785485
Short name T58
Test name
Test status
Simulation time 950996373525 ps
CPU time 371.28 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:16:12 PM PDT 24
Peak memory 191116 kb
Host smart-b1749abd-6fb5-4262-a07e-c3e44a5dbbca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549785485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
549785485
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3487746295
Short name T371
Test name
Test status
Simulation time 362971320423 ps
CPU time 268.05 seconds
Started Jun 21 05:10:19 PM PDT 24
Finished Jun 21 05:14:51 PM PDT 24
Peak memory 182820 kb
Host smart-59ddcfb2-25d5-4497-b922-e28a60b5cfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487746295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3487746295
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1000845014
Short name T443
Test name
Test status
Simulation time 15456872885 ps
CPU time 500.45 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:18:22 PM PDT 24
Peak memory 191164 kb
Host smart-7e16f7da-eb30-4a6c-8453-0b1785f66046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000845014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1000845014
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1048134337
Short name T415
Test name
Test status
Simulation time 78418870 ps
CPU time 0.64 seconds
Started Jun 21 05:10:11 PM PDT 24
Finished Jun 21 05:10:14 PM PDT 24
Peak memory 182712 kb
Host smart-abb7fe39-f62a-4bf4-ad2a-cd06a857d715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048134337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1048134337
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1145400139
Short name T385
Test name
Test status
Simulation time 263607690020 ps
CPU time 420.28 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:17:18 PM PDT 24
Peak memory 195580 kb
Host smart-94ba50a4-e241-413b-a1d5-458453f08bd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145400139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1145400139
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3131246262
Short name T291
Test name
Test status
Simulation time 520256373147 ps
CPU time 302.07 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:15:18 PM PDT 24
Peak memory 182860 kb
Host smart-21dcbde4-d560-40f5-86d3-6aa38aa5de17
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131246262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3131246262
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1920334297
Short name T366
Test name
Test status
Simulation time 71911329268 ps
CPU time 54.95 seconds
Started Jun 21 05:10:02 PM PDT 24
Finished Jun 21 05:10:58 PM PDT 24
Peak memory 182912 kb
Host smart-74123ceb-9337-4371-9b62-1783a582e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920334297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1920334297
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2798828308
Short name T223
Test name
Test status
Simulation time 137027666088 ps
CPU time 60.06 seconds
Started Jun 21 05:10:02 PM PDT 24
Finished Jun 21 05:11:03 PM PDT 24
Peak memory 193368 kb
Host smart-1d1f80e3-53f0-45ae-9e75-a802268ff5d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798828308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2798828308
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.328686670
Short name T376
Test name
Test status
Simulation time 426056500 ps
CPU time 1.86 seconds
Started Jun 21 05:10:12 PM PDT 24
Finished Jun 21 05:10:15 PM PDT 24
Peak memory 182812 kb
Host smart-23eef3a9-a4a5-42ca-abd3-34b9d10606f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328686670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.328686670
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2128150139
Short name T439
Test name
Test status
Simulation time 1397144889052 ps
CPU time 588.15 seconds
Started Jun 21 05:10:21 PM PDT 24
Finished Jun 21 05:20:13 PM PDT 24
Peak memory 195504 kb
Host smart-48cc72d7-3624-4d69-b27d-84189d2cdd2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128150139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2128150139
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.4248827320
Short name T149
Test name
Test status
Simulation time 811992031175 ps
CPU time 440.46 seconds
Started Jun 21 05:10:01 PM PDT 24
Finished Jun 21 05:17:23 PM PDT 24
Peak memory 182948 kb
Host smart-49f1e28a-5cc4-4387-bc4c-ef10985936eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248827320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.4248827320
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2757167132
Short name T430
Test name
Test status
Simulation time 42171744746 ps
CPU time 56.32 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:11:13 PM PDT 24
Peak memory 182880 kb
Host smart-a31e4f96-5f2c-4ddf-a0eb-f3967338201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757167132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2757167132
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2640150710
Short name T350
Test name
Test status
Simulation time 147829204 ps
CPU time 1.27 seconds
Started Jun 21 05:10:12 PM PDT 24
Finished Jun 21 05:10:15 PM PDT 24
Peak memory 182836 kb
Host smart-bc4eb459-b946-4e98-ac33-97d0196ab357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640150710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2640150710
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.272346777
Short name T384
Test name
Test status
Simulation time 31179403 ps
CPU time 0.63 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:10:17 PM PDT 24
Peak memory 182620 kb
Host smart-5b5912f3-20ed-41dc-bb6f-e666e69e26eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272346777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
272346777
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2582732537
Short name T437
Test name
Test status
Simulation time 299758936675 ps
CPU time 851.08 seconds
Started Jun 21 05:10:18 PM PDT 24
Finished Jun 21 05:24:33 PM PDT 24
Peak memory 210068 kb
Host smart-8407aa68-2903-483e-af65-1c5635b04caf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582732537 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2582732537
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2456926097
Short name T179
Test name
Test status
Simulation time 883160264118 ps
CPU time 356.23 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:16:14 PM PDT 24
Peak memory 182960 kb
Host smart-ae4b86c7-d08d-48bb-a19e-ebcbcb4250ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456926097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2456926097
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3477721104
Short name T418
Test name
Test status
Simulation time 18576483155 ps
CPU time 28.03 seconds
Started Jun 21 05:10:19 PM PDT 24
Finished Jun 21 05:10:51 PM PDT 24
Peak memory 182976 kb
Host smart-a56a490c-52e6-4152-9445-f8690eaeb07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477721104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3477721104
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.4028290443
Short name T289
Test name
Test status
Simulation time 41187984973 ps
CPU time 54.08 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:11:01 PM PDT 24
Peak memory 182716 kb
Host smart-5a56b667-364e-4a83-b82e-40481e9282b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028290443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.4028290443
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2041332413
Short name T438
Test name
Test status
Simulation time 330213677085 ps
CPU time 467.37 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:17:54 PM PDT 24
Peak memory 194812 kb
Host smart-0d57aae1-fb88-414b-a7f5-920eb049b5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041332413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2041332413
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1685319261
Short name T352
Test name
Test status
Simulation time 151190025447 ps
CPU time 222.12 seconds
Started Jun 21 05:10:04 PM PDT 24
Finished Jun 21 05:13:47 PM PDT 24
Peak memory 182876 kb
Host smart-69a9155e-33e0-4046-80e9-95db40712732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685319261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1685319261
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1007275100
Short name T328
Test name
Test status
Simulation time 107422248023 ps
CPU time 389.44 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:16:36 PM PDT 24
Peak memory 191104 kb
Host smart-2918e307-96e2-4836-896f-a8132d172145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007275100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1007275100
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1451873189
Short name T333
Test name
Test status
Simulation time 24519138034 ps
CPU time 194.46 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:13:21 PM PDT 24
Peak memory 182884 kb
Host smart-115d5b97-a6de-4267-878f-3383e67751b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451873189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1451873189
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.840779687
Short name T302
Test name
Test status
Simulation time 2187936429436 ps
CPU time 1081.52 seconds
Started Jun 21 05:10:10 PM PDT 24
Finished Jun 21 05:28:13 PM PDT 24
Peak memory 182988 kb
Host smart-8d19e8dc-da61-44cf-ba18-d4d044176e82
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840779687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.840779687
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1659366067
Short name T393
Test name
Test status
Simulation time 66275729330 ps
CPU time 100.46 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:11:47 PM PDT 24
Peak memory 182972 kb
Host smart-d9f50275-24e9-457d-a9d1-6c38e9eb9c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659366067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1659366067
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2331019796
Short name T2
Test name
Test status
Simulation time 44579635227 ps
CPU time 34.76 seconds
Started Jun 21 05:10:04 PM PDT 24
Finished Jun 21 05:10:40 PM PDT 24
Peak memory 182776 kb
Host smart-acfabbff-9e0a-4a68-85c9-bcd6e8be0097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331019796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2331019796
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.618523358
Short name T445
Test name
Test status
Simulation time 8658441559 ps
CPU time 14.54 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:10:21 PM PDT 24
Peak memory 191184 kb
Host smart-4976ea80-b116-4e55-9c4e-d3673e8619da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618523358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.618523358
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3052276244
Short name T190
Test name
Test status
Simulation time 1058447528396 ps
CPU time 1459.36 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:34:26 PM PDT 24
Peak memory 191164 kb
Host smart-a3ff633f-a5de-4119-b1d9-5cee1ddb3522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052276244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3052276244
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.508335962
Short name T448
Test name
Test status
Simulation time 30505020903 ps
CPU time 28.19 seconds
Started Jun 21 05:10:10 PM PDT 24
Finished Jun 21 05:10:38 PM PDT 24
Peak memory 182988 kb
Host smart-a6771393-701c-4c0e-b3bd-d0f47786ce99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508335962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.508335962
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3989117670
Short name T379
Test name
Test status
Simulation time 14647117036 ps
CPU time 8.45 seconds
Started Jun 21 05:10:15 PM PDT 24
Finished Jun 21 05:10:28 PM PDT 24
Peak memory 182984 kb
Host smart-5778b9cc-12fe-4411-a572-cc3b5d512daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989117670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3989117670
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.4279683786
Short name T286
Test name
Test status
Simulation time 121961511434 ps
CPU time 599.34 seconds
Started Jun 21 05:10:16 PM PDT 24
Finished Jun 21 05:20:20 PM PDT 24
Peak memory 191196 kb
Host smart-e2104756-02d0-4a0c-b07f-19478fd8d3ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279683786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4279683786
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.118567982
Short name T408
Test name
Test status
Simulation time 125937041 ps
CPU time 1 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:10:28 PM PDT 24
Peak memory 182948 kb
Host smart-9c706a87-f85e-4db5-a23e-b33ba3cf714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118567982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.118567982
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2056249873
Short name T364
Test name
Test status
Simulation time 426156982361 ps
CPU time 92.51 seconds
Started Jun 21 05:10:10 PM PDT 24
Finished Jun 21 05:11:44 PM PDT 24
Peak memory 182808 kb
Host smart-def13f25-d6ab-4df8-9409-07aba266dc5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056249873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2056249873
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3652684507
Short name T354
Test name
Test status
Simulation time 425197409133 ps
CPU time 324.17 seconds
Started Jun 21 05:10:02 PM PDT 24
Finished Jun 21 05:15:28 PM PDT 24
Peak memory 182864 kb
Host smart-7df99d61-8e3f-4ac3-a32d-36778875669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652684507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3652684507
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2517475447
Short name T429
Test name
Test status
Simulation time 38929838142 ps
CPU time 67.87 seconds
Started Jun 21 05:10:00 PM PDT 24
Finished Jun 21 05:11:10 PM PDT 24
Peak memory 191108 kb
Host smart-f8345104-ee8d-4d6f-b3f2-b19f3c17a96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517475447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2517475447
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2353954120
Short name T160
Test name
Test status
Simulation time 127960553837 ps
CPU time 208.22 seconds
Started Jun 21 05:09:43 PM PDT 24
Finished Jun 21 05:13:14 PM PDT 24
Peak memory 182884 kb
Host smart-f014d405-8aeb-481e-8374-ca3784dbf2df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353954120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2353954120
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1279641831
Short name T396
Test name
Test status
Simulation time 79240646871 ps
CPU time 65.56 seconds
Started Jun 21 05:09:41 PM PDT 24
Finished Jun 21 05:10:50 PM PDT 24
Peak memory 182976 kb
Host smart-7ed9f593-25cd-4fbc-8329-aa90dd422dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279641831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1279641831
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.307657014
Short name T66
Test name
Test status
Simulation time 46969741061 ps
CPU time 67.52 seconds
Started Jun 21 05:09:47 PM PDT 24
Finished Jun 21 05:10:57 PM PDT 24
Peak memory 182872 kb
Host smart-19a825bf-5d44-4010-a529-86a049b19f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307657014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.307657014
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2373218346
Short name T17
Test name
Test status
Simulation time 104907814 ps
CPU time 0.96 seconds
Started Jun 21 05:09:41 PM PDT 24
Finished Jun 21 05:09:45 PM PDT 24
Peak memory 215520 kb
Host smart-57eb5ad9-60ca-410c-a7f9-ede8b7a3dd4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373218346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2373218346
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3932359636
Short name T422
Test name
Test status
Simulation time 124603612946 ps
CPU time 313.4 seconds
Started Jun 21 05:09:43 PM PDT 24
Finished Jun 21 05:15:00 PM PDT 24
Peak memory 191168 kb
Host smart-196bda23-ee41-4a46-81ca-8b5b5d955b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932359636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3932359636
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2324759887
Short name T121
Test name
Test status
Simulation time 667781589625 ps
CPU time 719.55 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:22:16 PM PDT 24
Peak memory 182812 kb
Host smart-f9ba126f-a7c0-4315-90eb-127a8b0a64fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324759887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2324759887
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1140939460
Short name T394
Test name
Test status
Simulation time 56442584180 ps
CPU time 85.69 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:11:26 PM PDT 24
Peak memory 182928 kb
Host smart-209b7908-d733-412c-b795-9f6aed220fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140939460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1140939460
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3984321541
Short name T46
Test name
Test status
Simulation time 66915460496 ps
CPU time 1423.36 seconds
Started Jun 21 05:09:59 PM PDT 24
Finished Jun 21 05:33:45 PM PDT 24
Peak memory 191144 kb
Host smart-ba1ca4f8-2d9a-480a-842a-1489261716e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984321541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3984321541
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1481017252
Short name T107
Test name
Test status
Simulation time 147580363835 ps
CPU time 126.27 seconds
Started Jun 21 05:10:22 PM PDT 24
Finished Jun 21 05:12:32 PM PDT 24
Peak memory 191028 kb
Host smart-383b103a-60bc-491c-9a97-edbad7adb0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481017252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1481017252
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2117294233
Short name T381
Test name
Test status
Simulation time 37748669 ps
CPU time 0.57 seconds
Started Jun 21 05:10:01 PM PDT 24
Finished Jun 21 05:10:04 PM PDT 24
Peak memory 182676 kb
Host smart-91480d9e-5038-42bc-9f89-05cdd37e31f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117294233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2117294233
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3218835146
Short name T142
Test name
Test status
Simulation time 833102346810 ps
CPU time 425.28 seconds
Started Jun 21 05:10:06 PM PDT 24
Finished Jun 21 05:17:13 PM PDT 24
Peak memory 182944 kb
Host smart-39baf358-c082-460d-b585-c638f06de03a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218835146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3218835146
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2195104363
Short name T386
Test name
Test status
Simulation time 472931269598 ps
CPU time 147.71 seconds
Started Jun 21 05:10:25 PM PDT 24
Finished Jun 21 05:12:55 PM PDT 24
Peak memory 182980 kb
Host smart-ca1d2bce-b549-4998-8df1-33c61be0a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195104363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2195104363
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1064773471
Short name T308
Test name
Test status
Simulation time 19355254361 ps
CPU time 30.35 seconds
Started Jun 21 05:10:17 PM PDT 24
Finished Jun 21 05:10:52 PM PDT 24
Peak memory 182864 kb
Host smart-c8ddac10-e16a-40cd-9100-34167567d838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064773471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1064773471
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.4182874395
Short name T130
Test name
Test status
Simulation time 60464740935 ps
CPU time 143.01 seconds
Started Jun 21 05:10:01 PM PDT 24
Finished Jun 21 05:12:26 PM PDT 24
Peak memory 191160 kb
Host smart-e45f7f49-8eb1-423e-a4a3-5fe10e6fcb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182874395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.4182874395
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.4200078069
Short name T264
Test name
Test status
Simulation time 374885281596 ps
CPU time 580.57 seconds
Started Jun 21 05:10:02 PM PDT 24
Finished Jun 21 05:19:44 PM PDT 24
Peak memory 182896 kb
Host smart-1b21abb3-b6e7-418a-816c-2cdaeee6a50c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200078069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.4200078069
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.665356442
Short name T380
Test name
Test status
Simulation time 148048576444 ps
CPU time 186.27 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:13:24 PM PDT 24
Peak memory 182964 kb
Host smart-9bc8cfac-45a8-47ab-a9e9-9f6e176911d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665356442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.665356442
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1168130647
Short name T305
Test name
Test status
Simulation time 176014810595 ps
CPU time 121.84 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 191144 kb
Host smart-8bf0754b-1c2f-412d-a5ef-5cc2703bea27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168130647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1168130647
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1384723610
Short name T272
Test name
Test status
Simulation time 79921452350 ps
CPU time 36.95 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:10:44 PM PDT 24
Peak memory 191072 kb
Host smart-706285d1-9207-4f5d-b1fb-b7c97353affb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384723610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1384723610
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2390349493
Short name T330
Test name
Test status
Simulation time 171140933821 ps
CPU time 242.69 seconds
Started Jun 21 05:10:28 PM PDT 24
Finished Jun 21 05:14:33 PM PDT 24
Peak memory 182964 kb
Host smart-e128fe7b-8b65-42ce-8e1b-5b0fd21207b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390349493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2390349493
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.541454387
Short name T414
Test name
Test status
Simulation time 99381034692 ps
CPU time 76.72 seconds
Started Jun 21 05:10:01 PM PDT 24
Finished Jun 21 05:11:20 PM PDT 24
Peak memory 182964 kb
Host smart-104f4df0-a9c6-425f-83e5-6844f24c2fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541454387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.541454387
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3991486933
Short name T94
Test name
Test status
Simulation time 73798358218 ps
CPU time 221.24 seconds
Started Jun 21 05:10:18 PM PDT 24
Finished Jun 21 05:14:03 PM PDT 24
Peak memory 191076 kb
Host smart-8ab02798-2041-4b5a-a612-f7d5e5e1cbbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991486933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3991486933
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.263126350
Short name T251
Test name
Test status
Simulation time 134172703522 ps
CPU time 323.59 seconds
Started Jun 21 05:10:10 PM PDT 24
Finished Jun 21 05:15:35 PM PDT 24
Peak memory 182892 kb
Host smart-36bff5cd-c6a0-4d39-9bae-73630a5b2116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263126350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.263126350
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.175317864
Short name T281
Test name
Test status
Simulation time 500424093809 ps
CPU time 648.5 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:20:56 PM PDT 24
Peak memory 195104 kb
Host smart-7bf5ccd7-ad6f-4f76-8c89-3bd73b00a881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175317864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
175317864
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3619105344
Short name T123
Test name
Test status
Simulation time 326220910862 ps
CPU time 522.28 seconds
Started Jun 21 05:10:06 PM PDT 24
Finished Jun 21 05:18:50 PM PDT 24
Peak memory 182960 kb
Host smart-a51769cb-b5b4-4737-821d-9d34422d1927
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619105344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3619105344
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2766339105
Short name T407
Test name
Test status
Simulation time 384926093581 ps
CPU time 121.02 seconds
Started Jun 21 05:10:04 PM PDT 24
Finished Jun 21 05:12:06 PM PDT 24
Peak memory 182952 kb
Host smart-e89ccad1-1523-45d6-be53-dbdfc2542a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766339105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2766339105
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2276895648
Short name T112
Test name
Test status
Simulation time 165841149387 ps
CPU time 96.61 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:11:53 PM PDT 24
Peak memory 191148 kb
Host smart-701e95c0-7142-463b-a8b2-630f30b98135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276895648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2276895648
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2296217268
Short name T75
Test name
Test status
Simulation time 272261071239 ps
CPU time 1736.14 seconds
Started Jun 21 05:10:12 PM PDT 24
Finished Jun 21 05:39:11 PM PDT 24
Peak memory 213640 kb
Host smart-c93f2da5-2a79-4340-b45d-5d8180c91a3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296217268 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2296217268
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.4285634151
Short name T434
Test name
Test status
Simulation time 355433558885 ps
CPU time 531.95 seconds
Started Jun 21 05:10:06 PM PDT 24
Finished Jun 21 05:19:00 PM PDT 24
Peak memory 182944 kb
Host smart-0f06bf1a-ade8-452b-856d-9db96552e166
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285634151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.4285634151
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3785170894
Short name T358
Test name
Test status
Simulation time 169953105471 ps
CPU time 67.48 seconds
Started Jun 21 05:10:18 PM PDT 24
Finished Jun 21 05:11:30 PM PDT 24
Peak memory 182968 kb
Host smart-15a849e7-131c-4fb6-8b03-06bf34d08035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785170894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3785170894
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.608545564
Short name T273
Test name
Test status
Simulation time 127233836913 ps
CPU time 58.4 seconds
Started Jun 21 05:10:05 PM PDT 24
Finished Jun 21 05:11:05 PM PDT 24
Peak memory 191160 kb
Host smart-84946cac-8098-4c3b-b684-bf71cf1dfebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608545564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.608545564
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1793715900
Short name T409
Test name
Test status
Simulation time 100900810111 ps
CPU time 46.88 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:11:03 PM PDT 24
Peak memory 193880 kb
Host smart-697e90a2-19a8-4b20-8140-5d8d0e2220d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793715900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1793715900
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1316637189
Short name T56
Test name
Test status
Simulation time 2041992113403 ps
CPU time 818.35 seconds
Started Jun 21 05:10:24 PM PDT 24
Finished Jun 21 05:24:06 PM PDT 24
Peak memory 195456 kb
Host smart-eb4f4c45-22eb-4ed8-83b9-5ec00474fa76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316637189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1316637189
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2757486083
Short name T252
Test name
Test status
Simulation time 139073445152 ps
CPU time 134.49 seconds
Started Jun 21 05:10:25 PM PDT 24
Finished Jun 21 05:12:42 PM PDT 24
Peak memory 182944 kb
Host smart-1dce3c46-f3b2-42d1-a086-2cdc8de9a1b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757486083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2757486083
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.983235700
Short name T400
Test name
Test status
Simulation time 259817957663 ps
CPU time 94.83 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:11:52 PM PDT 24
Peak memory 182964 kb
Host smart-f1a040af-b914-405e-8bfb-95eff042606f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983235700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.983235700
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.743989064
Short name T172
Test name
Test status
Simulation time 328748946003 ps
CPU time 277.03 seconds
Started Jun 21 05:10:04 PM PDT 24
Finished Jun 21 05:14:42 PM PDT 24
Peak memory 191152 kb
Host smart-6f05f063-d209-408a-99c1-3f3819d4c7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743989064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.743989064
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1993026972
Short name T248
Test name
Test status
Simulation time 75416482302 ps
CPU time 62.38 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:11:33 PM PDT 24
Peak memory 182972 kb
Host smart-48380a79-380b-4278-8b7f-1361b99d1cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993026972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1993026972
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1154597287
Short name T24
Test name
Test status
Simulation time 382369176222 ps
CPU time 297.9 seconds
Started Jun 21 05:10:16 PM PDT 24
Finished Jun 21 05:15:18 PM PDT 24
Peak memory 194836 kb
Host smart-f7e7a70a-7b4a-46a4-b6dc-50c90f246a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154597287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1154597287
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.676272059
Short name T34
Test name
Test status
Simulation time 34733554488 ps
CPU time 291.68 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:15:09 PM PDT 24
Peak memory 205852 kb
Host smart-298ad4b7-08f3-4dec-9a91-be86a651798a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676272059 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.676272059
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.196323792
Short name T245
Test name
Test status
Simulation time 407301737436 ps
CPU time 681.87 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:21:53 PM PDT 24
Peak memory 182944 kb
Host smart-f00594dc-04ad-47cc-b330-10771e7d7c21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196323792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.196323792
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1155196717
Short name T369
Test name
Test status
Simulation time 72807698380 ps
CPU time 108.19 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:12:07 PM PDT 24
Peak memory 182964 kb
Host smart-33b3d2ad-8035-4d6f-98f1-fa44335b8f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155196717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1155196717
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1360148435
Short name T62
Test name
Test status
Simulation time 153440207044 ps
CPU time 79.4 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:11:36 PM PDT 24
Peak memory 191152 kb
Host smart-3d71b913-0c09-443a-a009-a509febbcbaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360148435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1360148435
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2245068848
Short name T91
Test name
Test status
Simulation time 37621685687 ps
CPU time 69.03 seconds
Started Jun 21 05:10:18 PM PDT 24
Finished Jun 21 05:11:31 PM PDT 24
Peak memory 191088 kb
Host smart-7f9fecd9-aa53-4c96-910c-575fed2d26bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245068848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2245068848
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.41808509
Short name T382
Test name
Test status
Simulation time 84928941485 ps
CPU time 120.09 seconds
Started Jun 21 05:10:18 PM PDT 24
Finished Jun 21 05:12:22 PM PDT 24
Peak memory 182956 kb
Host smart-8dcf732c-3a88-4919-9dc7-a4de63d2ffb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41808509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.41808509
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3147996784
Short name T207
Test name
Test status
Simulation time 315017213864 ps
CPU time 123.47 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:12:20 PM PDT 24
Peak memory 182944 kb
Host smart-54ecc365-28e9-47f8-adf4-f8584b3ab977
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147996784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3147996784
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2042392775
Short name T424
Test name
Test status
Simulation time 51771752813 ps
CPU time 36.76 seconds
Started Jun 21 05:10:15 PM PDT 24
Finished Jun 21 05:10:57 PM PDT 24
Peak memory 182908 kb
Host smart-8424107c-637a-4f03-bb50-4ef6b784faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042392775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2042392775
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3743666116
Short name T161
Test name
Test status
Simulation time 249342274361 ps
CPU time 309.55 seconds
Started Jun 21 05:10:25 PM PDT 24
Finished Jun 21 05:15:38 PM PDT 24
Peak memory 191072 kb
Host smart-91cc54ac-b6a5-4d51-ad62-0ba180cc566a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743666116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3743666116
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2975932350
Short name T403
Test name
Test status
Simulation time 21214984 ps
CPU time 0.55 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:10:32 PM PDT 24
Peak memory 182676 kb
Host smart-209ffbfd-c764-417d-9021-182f0b394530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975932350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2975932350
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.430880251
Short name T5
Test name
Test status
Simulation time 949064487270 ps
CPU time 464.04 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:18:15 PM PDT 24
Peak memory 182944 kb
Host smart-1e53d2c6-4ac7-4e8b-aec9-d1e32a6b00b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430880251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.430880251
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.4123133594
Short name T389
Test name
Test status
Simulation time 123542252442 ps
CPU time 188.27 seconds
Started Jun 21 05:10:15 PM PDT 24
Finished Jun 21 05:13:27 PM PDT 24
Peak memory 182868 kb
Host smart-61f16f38-806c-4803-9eec-14760b7c3924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123133594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.4123133594
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1535255792
Short name T337
Test name
Test status
Simulation time 34783834684 ps
CPU time 314.56 seconds
Started Jun 21 05:10:17 PM PDT 24
Finished Jun 21 05:15:37 PM PDT 24
Peak memory 191160 kb
Host smart-a07ee461-324a-497f-be8d-82f58d2314c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535255792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1535255792
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.418499909
Short name T428
Test name
Test status
Simulation time 305413741 ps
CPU time 0.66 seconds
Started Jun 21 05:10:26 PM PDT 24
Finished Jun 21 05:10:29 PM PDT 24
Peak memory 182640 kb
Host smart-d31171b9-24dd-4c24-8513-7db745cb0585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418499909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.418499909
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.58628949
Short name T37
Test name
Test status
Simulation time 84598941701 ps
CPU time 393.37 seconds
Started Jun 21 05:10:25 PM PDT 24
Finished Jun 21 05:17:02 PM PDT 24
Peak memory 205860 kb
Host smart-6e606a15-9f23-4353-99ba-f0f1638babc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58628949 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.58628949
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.314031152
Short name T205
Test name
Test status
Simulation time 595075299905 ps
CPU time 246.7 seconds
Started Jun 21 05:09:45 PM PDT 24
Finished Jun 21 05:13:54 PM PDT 24
Peak memory 182944 kb
Host smart-77e6283a-4420-4b68-8157-0cdfb7214eae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314031152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.314031152
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.968313615
Short name T93
Test name
Test status
Simulation time 360761211920 ps
CPU time 150.88 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:12:22 PM PDT 24
Peak memory 182972 kb
Host smart-a4d61bbb-5566-482c-bdce-82cbfc30bf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968313615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.968313615
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2832016260
Short name T367
Test name
Test status
Simulation time 142948169 ps
CPU time 0.91 seconds
Started Jun 21 05:09:51 PM PDT 24
Finished Jun 21 05:09:54 PM PDT 24
Peak memory 191564 kb
Host smart-b7f28310-4dcd-4900-9001-8c548c1f80bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832016260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2832016260
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2870367000
Short name T20
Test name
Test status
Simulation time 94980753 ps
CPU time 0.89 seconds
Started Jun 21 05:09:51 PM PDT 24
Finished Jun 21 05:09:55 PM PDT 24
Peak memory 214384 kb
Host smart-0250d117-206f-49a7-b5a7-0b8efb414bf4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870367000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2870367000
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1704992829
Short name T42
Test name
Test status
Simulation time 3811324163 ps
CPU time 6.46 seconds
Started Jun 21 05:10:33 PM PDT 24
Finished Jun 21 05:10:41 PM PDT 24
Peak memory 182956 kb
Host smart-58fc5163-c199-4361-a9fa-e84274ecfdc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704992829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1704992829
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.533297954
Short name T359
Test name
Test status
Simulation time 97688091485 ps
CPU time 127.17 seconds
Started Jun 21 05:10:19 PM PDT 24
Finished Jun 21 05:12:30 PM PDT 24
Peak memory 182976 kb
Host smart-19bb9d7e-02bb-4c96-a551-ccdeef0da88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533297954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.533297954
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2295381847
Short name T228
Test name
Test status
Simulation time 389020765067 ps
CPU time 310.66 seconds
Started Jun 21 05:10:27 PM PDT 24
Finished Jun 21 05:15:40 PM PDT 24
Peak memory 193484 kb
Host smart-b5f1a9b0-198a-4281-b1b9-87d817c11a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295381847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2295381847
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.697835635
Short name T317
Test name
Test status
Simulation time 153448525324 ps
CPU time 63.03 seconds
Started Jun 21 05:10:24 PM PDT 24
Finished Jun 21 05:11:30 PM PDT 24
Peak memory 182700 kb
Host smart-a1b08ac6-6e11-4831-82ff-abfb33131d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697835635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.697835635
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3683377889
Short name T200
Test name
Test status
Simulation time 181341365690 ps
CPU time 757.97 seconds
Started Jun 21 05:10:31 PM PDT 24
Finished Jun 21 05:23:11 PM PDT 24
Peak memory 191148 kb
Host smart-4362f65e-6a6c-4b3a-af67-5c7f64441daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683377889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3683377889
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2677547971
Short name T4
Test name
Test status
Simulation time 1184697384393 ps
CPU time 513.35 seconds
Started Jun 21 05:10:27 PM PDT 24
Finished Jun 21 05:19:03 PM PDT 24
Peak memory 182872 kb
Host smart-ec877472-155d-420f-a3a1-7f5696a9ee2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677547971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2677547971
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2568699230
Short name T368
Test name
Test status
Simulation time 138405829 ps
CPU time 1.03 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:10:18 PM PDT 24
Peak memory 191120 kb
Host smart-9d394747-77e2-4191-9324-c987592ea426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568699230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2568699230
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3682248045
Short name T95
Test name
Test status
Simulation time 205322844905 ps
CPU time 519.02 seconds
Started Jun 21 05:10:27 PM PDT 24
Finished Jun 21 05:19:08 PM PDT 24
Peak memory 194832 kb
Host smart-04231dd7-b4cd-4618-8950-347a66a8eb4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682248045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3682248045
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.954559794
Short name T241
Test name
Test status
Simulation time 166938695212 ps
CPU time 128.85 seconds
Started Jun 21 05:10:19 PM PDT 24
Finished Jun 21 05:12:32 PM PDT 24
Peak memory 182868 kb
Host smart-06b10303-6115-4b0c-b779-658f342cb698
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954559794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.954559794
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.930015434
Short name T372
Test name
Test status
Simulation time 108853534110 ps
CPU time 35.71 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:10:54 PM PDT 24
Peak memory 182964 kb
Host smart-561f8b92-f2c6-4d97-a2e2-08ff41b611b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930015434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.930015434
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2946839071
Short name T220
Test name
Test status
Simulation time 141820260146 ps
CPU time 245.2 seconds
Started Jun 21 05:10:31 PM PDT 24
Finished Jun 21 05:14:38 PM PDT 24
Peak memory 194624 kb
Host smart-72dde9ce-46fe-4f18-b84f-90e87add346d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946839071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2946839071
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.927471680
Short name T426
Test name
Test status
Simulation time 24797873 ps
CPU time 0.51 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:10:31 PM PDT 24
Peak memory 182700 kb
Host smart-b31d9ad8-d832-4fd6-89ed-ea52fb33486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927471680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.927471680
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.772208145
Short name T13
Test name
Test status
Simulation time 55092959430 ps
CPU time 464.09 seconds
Started Jun 21 05:10:11 PM PDT 24
Finished Jun 21 05:17:57 PM PDT 24
Peak memory 205988 kb
Host smart-aeb0190f-d451-4a29-92f5-df9cbe3d7b08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772208145 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.772208145
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1998118793
Short name T92
Test name
Test status
Simulation time 8042679707 ps
CPU time 13.95 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:10:31 PM PDT 24
Peak memory 182924 kb
Host smart-27979902-652b-426e-820b-57d5eee1eb50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998118793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1998118793
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3358076657
Short name T89
Test name
Test status
Simulation time 193420640457 ps
CPU time 77.35 seconds
Started Jun 21 05:10:12 PM PDT 24
Finished Jun 21 05:11:30 PM PDT 24
Peak memory 182888 kb
Host smart-650984ae-c205-4bfa-a5ad-51b5be5f9b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358076657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3358076657
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2249540401
Short name T36
Test name
Test status
Simulation time 58751519640 ps
CPU time 302.82 seconds
Started Jun 21 05:10:25 PM PDT 24
Finished Jun 21 05:15:30 PM PDT 24
Peak memory 205860 kb
Host smart-93db9d37-5136-48bc-8770-11cea213fe02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249540401 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2249540401
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2404639633
Short name T340
Test name
Test status
Simulation time 1560418278794 ps
CPU time 884.29 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:25:15 PM PDT 24
Peak memory 182872 kb
Host smart-93fd9dd2-fd44-4b9e-beae-e7dbe7d089ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404639633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2404639633
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3736659423
Short name T357
Test name
Test status
Simulation time 310110726703 ps
CPU time 166.3 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:13:05 PM PDT 24
Peak memory 182964 kb
Host smart-2d56d86f-f1e7-49c1-836f-5c337b58cb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736659423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3736659423
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3931216222
Short name T265
Test name
Test status
Simulation time 168168408542 ps
CPU time 78.46 seconds
Started Jun 21 05:10:12 PM PDT 24
Finished Jun 21 05:11:32 PM PDT 24
Peak memory 182840 kb
Host smart-fed543b2-776d-40a6-8436-374b6da7b883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931216222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3931216222
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2700473207
Short name T360
Test name
Test status
Simulation time 5855488964 ps
CPU time 30.92 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:10:55 PM PDT 24
Peak memory 191016 kb
Host smart-ad67b768-ba2e-4428-ae0d-242f76e873d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700473207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2700473207
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3063086879
Short name T23
Test name
Test status
Simulation time 159313834433 ps
CPU time 259.16 seconds
Started Jun 21 05:10:16 PM PDT 24
Finished Jun 21 05:14:39 PM PDT 24
Peak memory 182748 kb
Host smart-577aa9b4-ac64-4dd0-9598-160c7fd5d7bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063086879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3063086879
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.4189767914
Short name T416
Test name
Test status
Simulation time 290574048004 ps
CPU time 111.91 seconds
Started Jun 21 05:10:13 PM PDT 24
Finished Jun 21 05:12:09 PM PDT 24
Peak memory 182964 kb
Host smart-d404926b-3057-40d5-9646-c9ec542dd17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189767914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.4189767914
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1633945207
Short name T132
Test name
Test status
Simulation time 622597805803 ps
CPU time 634.08 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:20:52 PM PDT 24
Peak memory 182968 kb
Host smart-93a172c2-d5cf-4672-8387-f93e0acb8173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633945207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1633945207
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1435938815
Short name T204
Test name
Test status
Simulation time 325701008064 ps
CPU time 320.11 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:15:44 PM PDT 24
Peak memory 191096 kb
Host smart-2d95f5e3-33df-4263-96ee-78928a02c53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435938815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1435938815
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1609821786
Short name T398
Test name
Test status
Simulation time 532338674547 ps
CPU time 228.6 seconds
Started Jun 21 05:10:14 PM PDT 24
Finished Jun 21 05:14:06 PM PDT 24
Peak memory 194704 kb
Host smart-4f264b90-3a0a-4b5d-ba34-04109dec128e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609821786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1609821786
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1381180192
Short name T410
Test name
Test status
Simulation time 96661577944 ps
CPU time 37.08 seconds
Started Jun 21 05:10:15 PM PDT 24
Finished Jun 21 05:10:56 PM PDT 24
Peak memory 182844 kb
Host smart-725ff60b-74b3-4f5a-8a3e-86647d8b39fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381180192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1381180192
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3968784492
Short name T375
Test name
Test status
Simulation time 100231763019 ps
CPU time 44.2 seconds
Started Jun 21 05:10:15 PM PDT 24
Finished Jun 21 05:11:04 PM PDT 24
Peak memory 182720 kb
Host smart-728e5351-e5ac-43b2-82ed-812fae517aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968784492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3968784492
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.4029832883
Short name T196
Test name
Test status
Simulation time 91626011127 ps
CPU time 220.25 seconds
Started Jun 21 05:10:35 PM PDT 24
Finished Jun 21 05:14:16 PM PDT 24
Peak memory 191076 kb
Host smart-68da845c-9fd1-45b8-9159-fff916bc4b7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029832883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4029832883
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3128560938
Short name T404
Test name
Test status
Simulation time 226058896 ps
CPU time 1.57 seconds
Started Jun 21 05:10:25 PM PDT 24
Finished Jun 21 05:10:29 PM PDT 24
Peak memory 191100 kb
Host smart-9e32dc34-d371-404c-8dcb-129f3c8f45d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128560938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3128560938
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3018105616
Short name T344
Test name
Test status
Simulation time 68514648361 ps
CPU time 119.15 seconds
Started Jun 21 05:10:38 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 182932 kb
Host smart-2fbb1675-b89a-4f71-af6f-0ed14be86c90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018105616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3018105616
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3699099738
Short name T22
Test name
Test status
Simulation time 191785319519 ps
CPU time 135.43 seconds
Started Jun 21 05:10:24 PM PDT 24
Finished Jun 21 05:12:43 PM PDT 24
Peak memory 182980 kb
Host smart-c7427a8b-d1f9-4198-9d2c-10aa91128282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699099738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3699099738
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2983774943
Short name T343
Test name
Test status
Simulation time 132073806066 ps
CPU time 137.65 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:12:49 PM PDT 24
Peak memory 191160 kb
Host smart-82c759f4-ab08-441c-a518-848770bafa3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983774943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2983774943
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1364876317
Short name T361
Test name
Test status
Simulation time 95463348404 ps
CPU time 39.26 seconds
Started Jun 21 05:10:31 PM PDT 24
Finished Jun 21 05:11:12 PM PDT 24
Peak memory 182964 kb
Host smart-ee449f24-e628-4b7e-9a7d-1be2cfaf7830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364876317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1364876317
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2641001620
Short name T331
Test name
Test status
Simulation time 155297489308 ps
CPU time 210.73 seconds
Started Jun 21 05:10:24 PM PDT 24
Finished Jun 21 05:13:58 PM PDT 24
Peak memory 191152 kb
Host smart-b7d73aad-3a63-4a1f-bb96-9fa2719fe5df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641001620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2641001620
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3870760999
Short name T275
Test name
Test status
Simulation time 13325591 ps
CPU time 0.53 seconds
Started Jun 21 05:10:19 PM PDT 24
Finished Jun 21 05:10:23 PM PDT 24
Peak memory 182624 kb
Host smart-d327cae7-5979-41b8-b2be-42c3255dce11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870760999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3870760999
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2146023909
Short name T263
Test name
Test status
Simulation time 231225926346 ps
CPU time 399.99 seconds
Started Jun 21 05:10:30 PM PDT 24
Finished Jun 21 05:17:12 PM PDT 24
Peak memory 182960 kb
Host smart-d65dfb08-d072-4b6e-8621-7a16f7f41ffa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146023909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2146023909
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3380997995
Short name T401
Test name
Test status
Simulation time 221306275425 ps
CPU time 165.4 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:13:09 PM PDT 24
Peak memory 182956 kb
Host smart-cd182540-7538-4214-aed4-1842b0c90195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380997995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3380997995
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.675763064
Short name T425
Test name
Test status
Simulation time 97824584414 ps
CPU time 38.08 seconds
Started Jun 21 05:10:22 PM PDT 24
Finished Jun 21 05:11:04 PM PDT 24
Peak memory 182816 kb
Host smart-8a443c25-545a-4935-8b41-13f676706e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675763064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.675763064
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3792935388
Short name T229
Test name
Test status
Simulation time 91647440826 ps
CPU time 118.2 seconds
Started Jun 21 05:10:35 PM PDT 24
Finished Jun 21 05:12:34 PM PDT 24
Peak memory 191164 kb
Host smart-fbcbb4a2-37f2-44c3-b251-8123647eecfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792935388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3792935388
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2682369853
Short name T35
Test name
Test status
Simulation time 64392322317 ps
CPU time 245.37 seconds
Started Jun 21 05:10:21 PM PDT 24
Finished Jun 21 05:14:31 PM PDT 24
Peak memory 205748 kb
Host smart-5966dae9-82b9-4a70-b09b-be59211b0be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682369853 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2682369853
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.703254458
Short name T293
Test name
Test status
Simulation time 22200875796 ps
CPU time 34.58 seconds
Started Jun 21 05:09:44 PM PDT 24
Finished Jun 21 05:10:21 PM PDT 24
Peak memory 182944 kb
Host smart-e9ef1b7c-7336-4eae-aba3-db184e7d08f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703254458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.703254458
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.545979886
Short name T395
Test name
Test status
Simulation time 331241663728 ps
CPU time 165.09 seconds
Started Jun 21 05:09:45 PM PDT 24
Finished Jun 21 05:12:32 PM PDT 24
Peak memory 182956 kb
Host smart-b3387ebc-c3f7-4589-97b0-e489f4f49d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545979886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.545979886
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1508896554
Short name T64
Test name
Test status
Simulation time 35990092243 ps
CPU time 106.66 seconds
Started Jun 21 05:09:46 PM PDT 24
Finished Jun 21 05:11:35 PM PDT 24
Peak memory 194492 kb
Host smart-09144689-cccf-4e72-b088-ccac2c708c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508896554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1508896554
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.65551395
Short name T219
Test name
Test status
Simulation time 166822146146 ps
CPU time 93.96 seconds
Started Jun 21 05:09:51 PM PDT 24
Finished Jun 21 05:11:28 PM PDT 24
Peak memory 191088 kb
Host smart-0cee383f-9328-4064-af4e-1d31c9aec4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65551395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.65551395
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1329286522
Short name T43
Test name
Test status
Simulation time 538347967949 ps
CPU time 188.33 seconds
Started Jun 21 05:09:47 PM PDT 24
Finished Jun 21 05:12:57 PM PDT 24
Peak memory 182948 kb
Host smart-76db0e35-0783-4ec1-bd29-6ade86661980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329286522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1329286522
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.2726504824
Short name T14
Test name
Test status
Simulation time 16625428929 ps
CPU time 130.22 seconds
Started Jun 21 05:09:48 PM PDT 24
Finished Jun 21 05:12:01 PM PDT 24
Peak memory 197696 kb
Host smart-9b42efe5-26ba-4019-9eb4-fb74237999a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726504824 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.2726504824
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2383489199
Short name T216
Test name
Test status
Simulation time 392626122691 ps
CPU time 297.15 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:15:28 PM PDT 24
Peak memory 191008 kb
Host smart-309cb325-ee82-490c-9dd2-f1fc414a19b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383489199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2383489199
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.342886996
Short name T65
Test name
Test status
Simulation time 16447181471 ps
CPU time 18.22 seconds
Started Jun 21 05:10:19 PM PDT 24
Finished Jun 21 05:10:41 PM PDT 24
Peak memory 182960 kb
Host smart-aac043f8-5726-46e4-88c5-f1436c5f748a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342886996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.342886996
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2364666046
Short name T266
Test name
Test status
Simulation time 583875243853 ps
CPU time 273.77 seconds
Started Jun 21 05:10:31 PM PDT 24
Finished Jun 21 05:15:06 PM PDT 24
Peak memory 191164 kb
Host smart-bf33c655-ea66-4e18-927a-057269b2b1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364666046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2364666046
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.846076822
Short name T63
Test name
Test status
Simulation time 38305862872 ps
CPU time 329.01 seconds
Started Jun 21 05:10:30 PM PDT 24
Finished Jun 21 05:16:01 PM PDT 24
Peak memory 182956 kb
Host smart-11a9d13f-155e-4b68-a972-f89c182c812f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846076822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.846076822
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1110072676
Short name T258
Test name
Test status
Simulation time 472467415162 ps
CPU time 185.11 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:13:32 PM PDT 24
Peak memory 192244 kb
Host smart-3dc0a3dd-e53b-4bc3-9e86-348076fca11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110072676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1110072676
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1010137477
Short name T189
Test name
Test status
Simulation time 186546150341 ps
CPU time 107.36 seconds
Started Jun 21 05:10:41 PM PDT 24
Finished Jun 21 05:12:29 PM PDT 24
Peak memory 182852 kb
Host smart-c324fb10-e375-47de-a439-0f6237011e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010137477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1010137477
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2080379899
Short name T242
Test name
Test status
Simulation time 4565959551 ps
CPU time 8.24 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:10:33 PM PDT 24
Peak memory 182964 kb
Host smart-bfb17960-fbe6-4139-adf7-9618c37b9e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080379899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2080379899
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1125862471
Short name T206
Test name
Test status
Simulation time 449581916241 ps
CPU time 532.28 seconds
Started Jun 21 05:10:30 PM PDT 24
Finished Jun 21 05:19:24 PM PDT 24
Peak memory 191164 kb
Host smart-0faced1d-b7ba-4f28-8d31-ef8ae70487fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125862471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1125862471
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3638152558
Short name T72
Test name
Test status
Simulation time 190222068397 ps
CPU time 65.85 seconds
Started Jun 21 05:10:34 PM PDT 24
Finished Jun 21 05:11:41 PM PDT 24
Peak memory 182952 kb
Host smart-992f260e-5c72-4f95-afb8-63baae87e3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638152558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3638152558
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.840296585
Short name T279
Test name
Test status
Simulation time 482998318771 ps
CPU time 787.39 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:22:59 PM PDT 24
Peak memory 182952 kb
Host smart-677f376f-3a25-43e6-8c91-ec69df3d5b07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840296585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.840296585
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.481933994
Short name T406
Test name
Test status
Simulation time 910542637647 ps
CPU time 357.41 seconds
Started Jun 21 05:09:42 PM PDT 24
Finished Jun 21 05:15:43 PM PDT 24
Peak memory 182824 kb
Host smart-cd591f0f-d65b-4c67-94a4-dfb2801cbe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481933994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.481933994
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1247973262
Short name T347
Test name
Test status
Simulation time 21444874393 ps
CPU time 35.37 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:10:27 PM PDT 24
Peak memory 182952 kb
Host smart-70df6905-b632-4399-a424-043e76d02458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247973262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1247973262
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2205330277
Short name T338
Test name
Test status
Simulation time 48062635807 ps
CPU time 438.53 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:17:10 PM PDT 24
Peak memory 182936 kb
Host smart-ac1d7a44-6a21-47b4-be0d-0577c70e617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205330277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2205330277
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1274921360
Short name T221
Test name
Test status
Simulation time 149715038538 ps
CPU time 571.12 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:19:56 PM PDT 24
Peak memory 191140 kb
Host smart-fa1f943a-a09f-485c-90f8-1251ec115589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274921360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1274921360
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3407490945
Short name T96
Test name
Test status
Simulation time 525900787898 ps
CPU time 1257.36 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:31:22 PM PDT 24
Peak memory 191144 kb
Host smart-9d12f3f3-c9ee-48ab-8efb-f1bff732edb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407490945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3407490945
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3580896718
Short name T270
Test name
Test status
Simulation time 318615866726 ps
CPU time 263.64 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:14:51 PM PDT 24
Peak memory 191112 kb
Host smart-405b3e1a-d58e-4ddf-83d6-7c69776ab1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580896718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3580896718
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2340744743
Short name T67
Test name
Test status
Simulation time 211734762081 ps
CPU time 415.2 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:17:19 PM PDT 24
Peak memory 191128 kb
Host smart-f53692b0-a7e6-40be-bea2-68b3ee2e53c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340744743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2340744743
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.4018395064
Short name T198
Test name
Test status
Simulation time 448454895850 ps
CPU time 259.94 seconds
Started Jun 21 05:10:22 PM PDT 24
Finished Jun 21 05:14:46 PM PDT 24
Peak memory 191052 kb
Host smart-be52f37d-3372-4467-884c-39fdf4c3f83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018395064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4018395064
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3951143888
Short name T158
Test name
Test status
Simulation time 198893704351 ps
CPU time 910.12 seconds
Started Jun 21 05:10:34 PM PDT 24
Finished Jun 21 05:25:45 PM PDT 24
Peak memory 193896 kb
Host smart-e9c40fc1-95a8-4cd8-920d-e2f79b3ed5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951143888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3951143888
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2418012353
Short name T139
Test name
Test status
Simulation time 115152996744 ps
CPU time 366.54 seconds
Started Jun 21 05:10:30 PM PDT 24
Finished Jun 21 05:16:38 PM PDT 24
Peak memory 191160 kb
Host smart-4250eb64-81eb-4c20-a688-1375c952bb6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418012353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2418012353
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1762522768
Short name T310
Test name
Test status
Simulation time 733145789279 ps
CPU time 339.81 seconds
Started Jun 21 05:10:21 PM PDT 24
Finished Jun 21 05:16:05 PM PDT 24
Peak memory 191172 kb
Host smart-a4d0bc38-23b2-4825-a158-3c9144a138dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762522768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1762522768
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3159221104
Short name T287
Test name
Test status
Simulation time 3041786673 ps
CPU time 2.83 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:09:58 PM PDT 24
Peak memory 182964 kb
Host smart-9abbf4aa-bea6-470f-a5bc-1fcba47a2eb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159221104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3159221104
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3846547716
Short name T419
Test name
Test status
Simulation time 104952848312 ps
CPU time 77.49 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:11:09 PM PDT 24
Peak memory 182944 kb
Host smart-943f8fe6-bb0e-45a1-b4c2-2df3b12af3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846547716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3846547716
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3370786291
Short name T209
Test name
Test status
Simulation time 54631998394 ps
CPU time 40.98 seconds
Started Jun 21 05:10:04 PM PDT 24
Finished Jun 21 05:10:46 PM PDT 24
Peak memory 182932 kb
Host smart-4abb239e-6e21-42aa-bcd2-53085ce56810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370786291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3370786291
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.30780389
Short name T362
Test name
Test status
Simulation time 590892183 ps
CPU time 1.33 seconds
Started Jun 21 05:09:52 PM PDT 24
Finished Jun 21 05:09:55 PM PDT 24
Peak memory 191112 kb
Host smart-177f590c-95ba-47e6-be42-ac4b001f02bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30780389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.30780389
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3421889006
Short name T147
Test name
Test status
Simulation time 399694697061 ps
CPU time 280.22 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:14:36 PM PDT 24
Peak memory 195528 kb
Host smart-0e107a83-06cd-40b3-a520-a0b96efad6ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421889006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3421889006
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.2763489929
Short name T318
Test name
Test status
Simulation time 26512397382 ps
CPU time 40.03 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:11:11 PM PDT 24
Peak memory 193976 kb
Host smart-ba7c14ac-0099-42ce-9540-7b1210bcf2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763489929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2763489929
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2978659473
Short name T315
Test name
Test status
Simulation time 273679194022 ps
CPU time 126.78 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:12:33 PM PDT 24
Peak memory 191164 kb
Host smart-37d78808-f671-4ad9-8815-69dad8313a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978659473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2978659473
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.4157877825
Short name T153
Test name
Test status
Simulation time 99217111266 ps
CPU time 176.46 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:13:23 PM PDT 24
Peak memory 191120 kb
Host smart-289bf344-09fd-435a-bbb6-a8913508494a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157877825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.4157877825
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2889132622
Short name T239
Test name
Test status
Simulation time 519951403801 ps
CPU time 1885.28 seconds
Started Jun 21 05:10:38 PM PDT 24
Finished Jun 21 05:42:04 PM PDT 24
Peak memory 191140 kb
Host smart-714828d0-310a-4c12-aa91-822434179223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889132622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2889132622
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2456915099
Short name T427
Test name
Test status
Simulation time 85335577533 ps
CPU time 39.96 seconds
Started Jun 21 05:10:22 PM PDT 24
Finished Jun 21 05:11:06 PM PDT 24
Peak memory 182964 kb
Host smart-609abf64-717b-4b9a-9735-7e735360a1d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456915099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2456915099
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.774280450
Short name T122
Test name
Test status
Simulation time 68464036734 ps
CPU time 257.77 seconds
Started Jun 21 05:10:18 PM PDT 24
Finished Jun 21 05:14:40 PM PDT 24
Peak memory 191152 kb
Host smart-cdc2e855-a822-4aea-9f4c-6ef47972f053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774280450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.774280450
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1805195653
Short name T116
Test name
Test status
Simulation time 202256061716 ps
CPU time 124.24 seconds
Started Jun 21 05:10:22 PM PDT 24
Finished Jun 21 05:12:30 PM PDT 24
Peak memory 191152 kb
Host smart-19f4f601-e109-470f-9518-6370b5b99696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805195653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1805195653
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.87453112
Short name T129
Test name
Test status
Simulation time 109475371094 ps
CPU time 147.85 seconds
Started Jun 21 05:10:20 PM PDT 24
Finished Jun 21 05:12:52 PM PDT 24
Peak memory 191160 kb
Host smart-4805f18c-245b-4500-93f4-b8b0cb01b1f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87453112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.87453112
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1780052478
Short name T292
Test name
Test status
Simulation time 664813212444 ps
CPU time 335.01 seconds
Started Jun 21 05:09:53 PM PDT 24
Finished Jun 21 05:15:30 PM PDT 24
Peak memory 182880 kb
Host smart-559ba118-3a9c-4282-a859-45f89c5c1e82
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780052478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1780052478
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3371628594
Short name T373
Test name
Test status
Simulation time 706800967681 ps
CPU time 221.59 seconds
Started Jun 21 05:09:56 PM PDT 24
Finished Jun 21 05:13:39 PM PDT 24
Peak memory 182864 kb
Host smart-db26a8c1-2f86-43d4-a2ad-8fc318717607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371628594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3371628594
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.869295659
Short name T341
Test name
Test status
Simulation time 78845104131 ps
CPU time 124.78 seconds
Started Jun 21 05:09:51 PM PDT 24
Finished Jun 21 05:11:58 PM PDT 24
Peak memory 191136 kb
Host smart-bfd42cac-1fee-4dc2-a355-29d9b2e63476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869295659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.869295659
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3040147755
Short name T365
Test name
Test status
Simulation time 244942581 ps
CPU time 3.71 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:09:55 PM PDT 24
Peak memory 182912 kb
Host smart-edd039f8-83c8-4d6a-bfc3-81cb6105c43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040147755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3040147755
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.2255900724
Short name T193
Test name
Test status
Simulation time 483112160393 ps
CPU time 235.64 seconds
Started Jun 21 05:10:35 PM PDT 24
Finished Jun 21 05:14:31 PM PDT 24
Peak memory 191160 kb
Host smart-2b841aa3-932b-4936-8cdb-bd906d4985f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255900724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2255900724
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2685092944
Short name T421
Test name
Test status
Simulation time 92818649817 ps
CPU time 60.75 seconds
Started Jun 21 05:10:35 PM PDT 24
Finished Jun 21 05:11:37 PM PDT 24
Peak memory 182956 kb
Host smart-1ea9648e-4cf0-431e-bd34-abcd4dcf899b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685092944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2685092944
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.423415518
Short name T327
Test name
Test status
Simulation time 10588305511 ps
CPU time 16.91 seconds
Started Jun 21 05:10:23 PM PDT 24
Finished Jun 21 05:10:44 PM PDT 24
Peak memory 182924 kb
Host smart-d7e4699c-bc00-4abb-8ca4-5c0e32857dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423415518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.423415518
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3274605959
Short name T108
Test name
Test status
Simulation time 380545950614 ps
CPU time 1404.16 seconds
Started Jun 21 05:10:42 PM PDT 24
Finished Jun 21 05:34:08 PM PDT 24
Peak memory 190956 kb
Host smart-8b836f63-7d8f-42c8-b2b5-9fd690cab12a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274605959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3274605959
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2493000928
Short name T417
Test name
Test status
Simulation time 103579387660 ps
CPU time 39.71 seconds
Started Jun 21 05:10:31 PM PDT 24
Finished Jun 21 05:11:12 PM PDT 24
Peak memory 182964 kb
Host smart-13ed8a57-0ba1-4a5c-97dc-e404006b6f23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493000928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2493000928
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3373474556
Short name T125
Test name
Test status
Simulation time 50310972244 ps
CPU time 1054.73 seconds
Started Jun 21 05:10:41 PM PDT 24
Finished Jun 21 05:28:17 PM PDT 24
Peak memory 191144 kb
Host smart-102909e9-32e8-40d4-b814-9440f904d705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373474556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3373474556
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1321878631
Short name T110
Test name
Test status
Simulation time 616009357491 ps
CPU time 308.83 seconds
Started Jun 21 05:10:33 PM PDT 24
Finished Jun 21 05:15:43 PM PDT 24
Peak memory 191164 kb
Host smart-ba9950ac-4c9a-45b5-b815-bb34527df1d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321878631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1321878631
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2184159684
Short name T449
Test name
Test status
Simulation time 263668554018 ps
CPU time 59.24 seconds
Started Jun 21 05:10:29 PM PDT 24
Finished Jun 21 05:11:30 PM PDT 24
Peak memory 182964 kb
Host smart-cb1f6e75-593d-4d45-8551-4d03b37736fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184159684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2184159684
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1371570468
Short name T70
Test name
Test status
Simulation time 276328761399 ps
CPU time 596.53 seconds
Started Jun 21 05:10:27 PM PDT 24
Finished Jun 21 05:20:26 PM PDT 24
Peak memory 194696 kb
Host smart-d044c267-5e79-4eec-acab-b757a5b6fb2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371570468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1371570468
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3519120105
Short name T297
Test name
Test status
Simulation time 182128710522 ps
CPU time 79.14 seconds
Started Jun 21 05:10:32 PM PDT 24
Finished Jun 21 05:11:52 PM PDT 24
Peak memory 191076 kb
Host smart-4b2cb556-e07b-4d89-8e8d-836fed9aa5d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519120105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3519120105
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3900469046
Short name T304
Test name
Test status
Simulation time 917286601494 ps
CPU time 661.95 seconds
Started Jun 21 05:09:49 PM PDT 24
Finished Jun 21 05:20:55 PM PDT 24
Peak memory 182924 kb
Host smart-dea0a601-4263-478b-b909-213956e70715
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900469046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3900469046
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3900396963
Short name T390
Test name
Test status
Simulation time 154885964884 ps
CPU time 242.95 seconds
Started Jun 21 05:09:51 PM PDT 24
Finished Jun 21 05:13:57 PM PDT 24
Peak memory 182964 kb
Host smart-aade79df-feb6-4491-8989-a52a8db45df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900396963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3900396963
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2808541741
Short name T339
Test name
Test status
Simulation time 78340647442 ps
CPU time 768.75 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:22:42 PM PDT 24
Peak memory 191148 kb
Host smart-67f9df71-516f-405f-bdf9-ddbea2d20c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808541741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2808541741
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.607292373
Short name T374
Test name
Test status
Simulation time 105193887 ps
CPU time 0.73 seconds
Started Jun 21 05:09:50 PM PDT 24
Finished Jun 21 05:09:53 PM PDT 24
Peak memory 182712 kb
Host smart-f6d54101-c6ce-45dc-84ba-c48d26f24455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607292373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.607292373
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.380878862
Short name T356
Test name
Test status
Simulation time 196073145166 ps
CPU time 75.74 seconds
Started Jun 21 05:09:52 PM PDT 24
Finished Jun 21 05:11:10 PM PDT 24
Peak memory 182904 kb
Host smart-00da7a09-553f-4282-853c-a505173dca7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380878862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.380878862
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/92.rv_timer_random.1826596368
Short name T230
Test name
Test status
Simulation time 103652622520 ps
CPU time 1936.58 seconds
Started Jun 21 05:10:31 PM PDT 24
Finished Jun 21 05:42:50 PM PDT 24
Peak memory 191156 kb
Host smart-6c66dc68-0d56-4e0d-a756-75052008c8a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826596368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1826596368
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1831670311
Short name T283
Test name
Test status
Simulation time 343309344033 ps
CPU time 155.39 seconds
Started Jun 21 05:10:34 PM PDT 24
Finished Jun 21 05:13:10 PM PDT 24
Peak memory 191052 kb
Host smart-3acecd9f-2fe3-42bd-b35e-d68dfb3ee866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831670311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1831670311
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1599429382
Short name T212
Test name
Test status
Simulation time 211499260464 ps
CPU time 113.42 seconds
Started Jun 21 05:10:44 PM PDT 24
Finished Jun 21 05:12:38 PM PDT 24
Peak memory 191052 kb
Host smart-10ef944b-ce10-4a24-9374-008943f53528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599429382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1599429382
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1835693141
Short name T435
Test name
Test status
Simulation time 20483874696 ps
CPU time 27.4 seconds
Started Jun 21 05:10:27 PM PDT 24
Finished Jun 21 05:10:56 PM PDT 24
Peak memory 182916 kb
Host smart-038bbcd1-4c0c-4a7c-984c-8022ae7e6edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835693141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1835693141
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.7172046
Short name T321
Test name
Test status
Simulation time 77192510120 ps
CPU time 82.26 seconds
Started Jun 21 05:10:28 PM PDT 24
Finished Jun 21 05:11:52 PM PDT 24
Peak memory 191168 kb
Host smart-2d2aa0bf-7d95-4cc7-9525-0c1bc3cdbd80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7172046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.7172046
Directory /workspace/99.rv_timer_random/latest
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