Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
114636423 |
1 |
|
T1 |
436064 |
|
T2 |
754046 |
|
T3 |
27628 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53352987 |
1 |
|
T1 |
48575 |
|
T2 |
348932 |
|
T3 |
15121 |
auto[1] |
61283436 |
1 |
|
T1 |
387489 |
|
T2 |
405114 |
|
T3 |
12507 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
114630954 |
1 |
|
T1 |
436056 |
|
T2 |
754034 |
|
T3 |
27620 |
auto[1] |
5469 |
1 |
|
T1 |
8 |
|
T2 |
12 |
|
T3 |
8 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
53350361 |
1 |
|
T1 |
48571 |
|
T2 |
348930 |
|
T3 |
15120 |
all_values[0] |
auto[0] |
auto[1] |
2626 |
1 |
|
T1 |
4 |
|
T2 |
2 |
|
T3 |
1 |
all_values[0] |
auto[1] |
auto[0] |
61280593 |
1 |
|
T1 |
387485 |
|
T2 |
405104 |
|
T3 |
12500 |
all_values[0] |
auto[1] |
auto[1] |
2843 |
1 |
|
T1 |
4 |
|
T2 |
10 |
|
T3 |
7 |