Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
1184 |
1 |
|
T3 |
4 |
|
T34 |
8 |
|
T35 |
35 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
613 |
1 |
|
T3 |
1 |
|
T34 |
3 |
|
T35 |
17 |
auto[1] |
571 |
1 |
|
T3 |
3 |
|
T34 |
5 |
|
T35 |
18 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
424 |
1 |
|
T3 |
1 |
|
T35 |
16 |
|
T106 |
10 |
auto[1] |
760 |
1 |
|
T3 |
3 |
|
T34 |
8 |
|
T35 |
19 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
660 |
1 |
|
T3 |
2 |
|
T34 |
3 |
|
T35 |
25 |
auto[1] |
524 |
1 |
|
T3 |
2 |
|
T34 |
5 |
|
T35 |
10 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
227 |
1 |
|
T35 |
9 |
|
T106 |
3 |
|
T12 |
1 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
108 |
1 |
|
T35 |
4 |
|
T106 |
1 |
|
T12 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
197 |
1 |
|
T3 |
1 |
|
T35 |
7 |
|
T106 |
7 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
128 |
1 |
|
T3 |
1 |
|
T34 |
3 |
|
T35 |
5 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
278 |
1 |
|
T3 |
1 |
|
T34 |
3 |
|
T35 |
4 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
246 |
1 |
|
T3 |
1 |
|
T34 |
2 |
|
T35 |
6 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |