Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.53 99.36 98.73 100.00 100.00 100.00 99.09


Total test records in report: 574
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.411496213 Jun 22 04:34:58 PM PDT 24 Jun 22 04:34:59 PM PDT 24 15061180 ps
T512 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1451237852 Jun 22 04:34:57 PM PDT 24 Jun 22 04:35:00 PM PDT 24 63557314 ps
T513 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.140653608 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:08 PM PDT 24 17381614 ps
T514 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.83192131 Jun 22 04:35:12 PM PDT 24 Jun 22 04:35:13 PM PDT 24 11609896 ps
T76 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.557858221 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:08 PM PDT 24 28651363 ps
T515 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3439849130 Jun 22 04:34:54 PM PDT 24 Jun 22 04:34:56 PM PDT 24 45209734 ps
T516 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.496748742 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:09 PM PDT 24 121916840 ps
T517 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1604046598 Jun 22 04:35:00 PM PDT 24 Jun 22 04:35:02 PM PDT 24 37960317 ps
T518 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2859535961 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:08 PM PDT 24 126826581 ps
T77 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2281848294 Jun 22 04:34:59 PM PDT 24 Jun 22 04:35:04 PM PDT 24 40312258 ps
T519 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1886419821 Jun 22 04:35:01 PM PDT 24 Jun 22 04:35:03 PM PDT 24 19333194 ps
T95 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3597791963 Jun 22 04:34:55 PM PDT 24 Jun 22 04:34:57 PM PDT 24 124262034 ps
T520 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2895673374 Jun 22 04:35:06 PM PDT 24 Jun 22 04:35:10 PM PDT 24 106026114 ps
T79 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3673651602 Jun 22 04:34:58 PM PDT 24 Jun 22 04:35:00 PM PDT 24 31891695 ps
T80 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2718579275 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:08 PM PDT 24 15269643 ps
T521 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2627397439 Jun 22 04:35:04 PM PDT 24 Jun 22 04:35:08 PM PDT 24 27450772 ps
T522 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.363675290 Jun 22 04:35:02 PM PDT 24 Jun 22 04:35:05 PM PDT 24 296168975 ps
T81 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1342329294 Jun 22 04:34:57 PM PDT 24 Jun 22 04:34:58 PM PDT 24 33696152 ps
T523 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3180531372 Jun 22 04:34:51 PM PDT 24 Jun 22 04:34:52 PM PDT 24 41639242 ps
T524 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.147952461 Jun 22 04:35:00 PM PDT 24 Jun 22 04:35:02 PM PDT 24 12231099 ps
T525 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.95859931 Jun 22 04:35:06 PM PDT 24 Jun 22 04:35:10 PM PDT 24 11003982 ps
T526 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.685542676 Jun 22 04:34:55 PM PDT 24 Jun 22 04:34:57 PM PDT 24 212569134 ps
T527 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2642486894 Jun 22 04:34:50 PM PDT 24 Jun 22 04:34:52 PM PDT 24 371160929 ps
T528 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1098440511 Jun 22 04:35:21 PM PDT 24 Jun 22 04:35:22 PM PDT 24 45540619 ps
T529 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1361868289 Jun 22 04:35:02 PM PDT 24 Jun 22 04:35:05 PM PDT 24 73403181 ps
T530 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1989290003 Jun 22 04:35:04 PM PDT 24 Jun 22 04:35:06 PM PDT 24 25266712 ps
T531 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.807148384 Jun 22 04:35:01 PM PDT 24 Jun 22 04:35:03 PM PDT 24 183180856 ps
T91 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.54403645 Jun 22 04:35:07 PM PDT 24 Jun 22 04:35:11 PM PDT 24 214486335 ps
T532 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.595938382 Jun 22 04:35:06 PM PDT 24 Jun 22 04:35:10 PM PDT 24 196502025 ps
T533 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2902685965 Jun 22 04:35:04 PM PDT 24 Jun 22 04:35:07 PM PDT 24 32498976 ps
T82 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2602984996 Jun 22 04:34:48 PM PDT 24 Jun 22 04:34:52 PM PDT 24 953241000 ps
T534 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3501858577 Jun 22 04:35:09 PM PDT 24 Jun 22 04:35:11 PM PDT 24 31755011 ps
T535 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2039183467 Jun 22 04:35:08 PM PDT 24 Jun 22 04:35:13 PM PDT 24 581337061 ps
T536 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2404237799 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:08 PM PDT 24 146907858 ps
T537 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4130749762 Jun 22 04:35:10 PM PDT 24 Jun 22 04:35:12 PM PDT 24 230235930 ps
T92 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3652684907 Jun 22 04:35:06 PM PDT 24 Jun 22 04:35:10 PM PDT 24 87029451 ps
T538 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.822664187 Jun 22 04:35:14 PM PDT 24 Jun 22 04:35:15 PM PDT 24 89999356 ps
T539 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3479690756 Jun 22 04:35:07 PM PDT 24 Jun 22 04:35:19 PM PDT 24 30470440 ps
T540 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4009550510 Jun 22 04:35:12 PM PDT 24 Jun 22 04:35:13 PM PDT 24 19377579 ps
T541 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.634775939 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:09 PM PDT 24 35511918 ps
T542 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2978073519 Jun 22 04:35:07 PM PDT 24 Jun 22 04:35:10 PM PDT 24 42249511 ps
T543 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1420400136 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:08 PM PDT 24 13278313 ps
T544 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3774558666 Jun 22 04:34:58 PM PDT 24 Jun 22 04:35:04 PM PDT 24 52968917 ps
T545 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1831239221 Jun 22 04:34:58 PM PDT 24 Jun 22 04:35:01 PM PDT 24 225562143 ps
T546 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.608351979 Jun 22 04:35:02 PM PDT 24 Jun 22 04:35:07 PM PDT 24 516555579 ps
T547 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.59230985 Jun 22 04:35:02 PM PDT 24 Jun 22 04:35:05 PM PDT 24 43495157 ps
T548 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.26766825 Jun 22 04:35:25 PM PDT 24 Jun 22 04:35:26 PM PDT 24 42275036 ps
T549 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1285474126 Jun 22 04:35:02 PM PDT 24 Jun 22 04:35:05 PM PDT 24 36194014 ps
T550 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2213298025 Jun 22 04:35:19 PM PDT 24 Jun 22 04:35:20 PM PDT 24 26538443 ps
T551 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1622085580 Jun 22 04:35:07 PM PDT 24 Jun 22 04:35:10 PM PDT 24 19638377 ps
T552 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2185838785 Jun 22 04:34:53 PM PDT 24 Jun 22 04:34:55 PM PDT 24 119447990 ps
T553 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3887213311 Jun 22 04:35:01 PM PDT 24 Jun 22 04:35:03 PM PDT 24 345983932 ps
T554 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2311558080 Jun 22 04:35:17 PM PDT 24 Jun 22 04:35:18 PM PDT 24 80015367 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3633927072 Jun 22 04:34:56 PM PDT 24 Jun 22 04:34:58 PM PDT 24 106321912 ps
T556 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.252426617 Jun 22 04:34:57 PM PDT 24 Jun 22 04:34:59 PM PDT 24 18926480 ps
T557 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2184743978 Jun 22 04:35:16 PM PDT 24 Jun 22 04:35:17 PM PDT 24 51521241 ps
T83 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2060480303 Jun 22 04:34:54 PM PDT 24 Jun 22 04:34:56 PM PDT 24 19064277 ps
T558 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1217419071 Jun 22 04:34:51 PM PDT 24 Jun 22 04:34:52 PM PDT 24 90326031 ps
T559 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3442770812 Jun 22 04:35:01 PM PDT 24 Jun 22 04:35:03 PM PDT 24 39451056 ps
T560 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2262737733 Jun 22 04:35:14 PM PDT 24 Jun 22 04:35:15 PM PDT 24 87899346 ps
T561 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3340647330 Jun 22 04:35:04 PM PDT 24 Jun 22 04:35:06 PM PDT 24 31375495 ps
T562 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.367700823 Jun 22 04:35:20 PM PDT 24 Jun 22 04:35:21 PM PDT 24 41374017 ps
T563 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2076737485 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:09 PM PDT 24 29082457 ps
T564 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.323953918 Jun 22 04:35:01 PM PDT 24 Jun 22 04:35:05 PM PDT 24 514176526 ps
T565 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2798301184 Jun 22 04:35:06 PM PDT 24 Jun 22 04:35:10 PM PDT 24 132141743 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3114035209 Jun 22 04:34:52 PM PDT 24 Jun 22 04:34:53 PM PDT 24 51687655 ps
T567 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2088469381 Jun 22 04:35:05 PM PDT 24 Jun 22 04:35:12 PM PDT 24 27402898 ps
T568 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1951643392 Jun 22 04:35:03 PM PDT 24 Jun 22 04:35:05 PM PDT 24 12287220 ps
T569 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2578362641 Jun 22 04:34:49 PM PDT 24 Jun 22 04:34:51 PM PDT 24 97752793 ps
T570 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2037121211 Jun 22 04:35:07 PM PDT 24 Jun 22 04:35:11 PM PDT 24 85565942 ps
T571 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.370426263 Jun 22 04:34:59 PM PDT 24 Jun 22 04:35:04 PM PDT 24 777404177 ps
T572 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1622633851 Jun 22 04:35:32 PM PDT 24 Jun 22 04:35:33 PM PDT 24 493319708 ps
T573 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3949558316 Jun 22 04:35:18 PM PDT 24 Jun 22 04:35:19 PM PDT 24 30776837 ps
T574 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2137615224 Jun 22 04:35:11 PM PDT 24 Jun 22 04:35:13 PM PDT 24 55190998 ps

Test location /workspace/coverage/default/54.rv_timer_random.1805579771
Short name T4
Test name
Test status
Simulation time 314404606800 ps
CPU time 269.39 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:46:29 PM PDT 24
Peak memory 193424 kb
Host smart-4b44e6fb-6249-4ef2-9261-e7e545ae6a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805579771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1805579771
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3838107600
Short name T13
Test name
Test status
Simulation time 310702251754 ps
CPU time 1195.6 seconds
Started Jun 22 04:41:13 PM PDT 24
Finished Jun 22 05:01:09 PM PDT 24
Peak memory 211360 kb
Host smart-3d055564-3e71-4e65-886e-bb5e71ca1214
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838107600 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.3838107600
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2621796829
Short name T34
Test name
Test status
Simulation time 611904514712 ps
CPU time 4016.21 seconds
Started Jun 22 04:41:31 PM PDT 24
Finished Jun 22 05:48:28 PM PDT 24
Peak memory 191092 kb
Host smart-74a1b7e2-045a-4d72-b1a8-f4e2e080cf7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621796829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2621796829
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.3318858889
Short name T2
Test name
Test status
Simulation time 217862083358 ps
CPU time 869.6 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:56:40 PM PDT 24
Peak memory 191188 kb
Host smart-f5b9c256-bdcc-4ea2-90da-9fe4af734116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318858889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3318858889
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1561834812
Short name T17
Test name
Test status
Simulation time 76969397 ps
CPU time 0.92 seconds
Started Jun 22 04:41:05 PM PDT 24
Finished Jun 22 04:41:07 PM PDT 24
Peak memory 213744 kb
Host smart-f1ae18ed-fdba-47bc-befc-ab100d2df63c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561834812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1561834812
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1555253981
Short name T106
Test name
Test status
Simulation time 4575180226475 ps
CPU time 2021.5 seconds
Started Jun 22 04:41:54 PM PDT 24
Finished Jun 22 05:15:37 PM PDT 24
Peak memory 191184 kb
Host smart-d54faf00-535f-465c-9b6b-dae25f796ad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555253981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1555253981
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1504415152
Short name T66
Test name
Test status
Simulation time 818202078394 ps
CPU time 794.49 seconds
Started Jun 22 04:41:47 PM PDT 24
Finished Jun 22 04:55:02 PM PDT 24
Peak memory 191084 kb
Host smart-777dc5d7-3e5c-49d0-b662-bf51fc3ce982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504415152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1504415152
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.534624833
Short name T138
Test name
Test status
Simulation time 439703085409 ps
CPU time 1811.15 seconds
Started Jun 22 04:42:00 PM PDT 24
Finished Jun 22 05:12:12 PM PDT 24
Peak memory 191084 kb
Host smart-240dd43c-647d-435e-b229-0a5c9dae17f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534624833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
534624833
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.993542444
Short name T100
Test name
Test status
Simulation time 1013738776252 ps
CPU time 1108.06 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:59:48 PM PDT 24
Peak memory 191028 kb
Host smart-2d1e1554-4248-4ca3-80f0-0456c601ac1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993542444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
993542444
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/74.rv_timer_random.3905628523
Short name T96
Test name
Test status
Simulation time 155971979809 ps
CPU time 645.26 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:52:44 PM PDT 24
Peak memory 191080 kb
Host smart-7372552c-d5f5-4611-80c6-173ac55030ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905628523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3905628523
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.771264947
Short name T299
Test name
Test status
Simulation time 655499767361 ps
CPU time 4002.06 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 05:48:04 PM PDT 24
Peak memory 191028 kb
Host smart-e2e0bc9b-2d2f-4090-b09e-5573e13f15b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771264947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.771264947
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3426674522
Short name T146
Test name
Test status
Simulation time 716252908830 ps
CPU time 2758.06 seconds
Started Jun 22 04:41:40 PM PDT 24
Finished Jun 22 05:27:39 PM PDT 24
Peak memory 191080 kb
Host smart-5869ab62-3c89-45b2-aa32-f0eaf7b24fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426674522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3426674522
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.2015507811
Short name T155
Test name
Test status
Simulation time 118026986419 ps
CPU time 187.11 seconds
Started Jun 22 04:42:09 PM PDT 24
Finished Jun 22 04:45:16 PM PDT 24
Peak memory 191080 kb
Host smart-f321ac52-ee1b-4123-8f36-749d42ab32fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015507811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2015507811
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.84754678
Short name T30
Test name
Test status
Simulation time 76850644 ps
CPU time 1.08 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:07 PM PDT 24
Peak memory 194996 kb
Host smart-b0d0cc5c-7d04-4725-9e9c-290aa89277bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84754678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_int
g_err.84754678
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1831737214
Short name T198
Test name
Test status
Simulation time 6036180277905 ps
CPU time 1345.19 seconds
Started Jun 22 04:41:58 PM PDT 24
Finished Jun 22 05:04:25 PM PDT 24
Peak memory 190996 kb
Host smart-e80c2240-8c8a-45d4-b763-103bd30e2758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831737214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1831737214
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2727421902
Short name T159
Test name
Test status
Simulation time 2007321431579 ps
CPU time 1361.95 seconds
Started Jun 22 04:41:14 PM PDT 24
Finished Jun 22 05:03:57 PM PDT 24
Peak memory 196920 kb
Host smart-c9d80905-dcaf-434a-90be-3f14c92e2182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727421902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2727421902
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.85926219
Short name T65
Test name
Test status
Simulation time 1317383363576 ps
CPU time 1029.21 seconds
Started Jun 22 04:41:35 PM PDT 24
Finished Jun 22 04:58:45 PM PDT 24
Peak memory 191184 kb
Host smart-793aa176-58f8-4182-9dfa-304448cbf2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85926219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.85926219
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3612192209
Short name T215
Test name
Test status
Simulation time 1906754700253 ps
CPU time 1514.57 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 05:06:32 PM PDT 24
Peak memory 195816 kb
Host smart-635ba392-23ab-471e-b93a-972037f3bf7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612192209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3612192209
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1602010145
Short name T281
Test name
Test status
Simulation time 567556240834 ps
CPU time 1892.02 seconds
Started Jun 22 04:41:52 PM PDT 24
Finished Jun 22 05:13:25 PM PDT 24
Peak memory 191080 kb
Host smart-5c69fe8e-d042-46b1-803a-56da4488168d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602010145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1602010145
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1342329294
Short name T81
Test name
Test status
Simulation time 33696152 ps
CPU time 0.61 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:34:58 PM PDT 24
Peak memory 182584 kb
Host smart-66291e0b-af56-45eb-b9c4-a97f316b922c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342329294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1342329294
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/66.rv_timer_random.3228650233
Short name T121
Test name
Test status
Simulation time 114701182888 ps
CPU time 187.35 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:45:13 PM PDT 24
Peak memory 191188 kb
Host smart-a25aa416-6bba-4045-a6db-1bead263fa5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228650233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3228650233
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1296711691
Short name T250
Test name
Test status
Simulation time 1429380210304 ps
CPU time 931.48 seconds
Started Jun 22 04:41:12 PM PDT 24
Finished Jun 22 04:56:44 PM PDT 24
Peak memory 191184 kb
Host smart-e0113e11-9610-4a88-aa6f-9f536a6f220a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296711691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1296711691
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1800465644
Short name T174
Test name
Test status
Simulation time 520738460198 ps
CPU time 730.96 seconds
Started Jun 22 04:41:47 PM PDT 24
Finished Jun 22 04:53:59 PM PDT 24
Peak memory 191064 kb
Host smart-9bffed64-f02b-4553-8b5c-01418d870bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800465644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1800465644
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.519980039
Short name T300
Test name
Test status
Simulation time 430574546626 ps
CPU time 1421.66 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 05:05:01 PM PDT 24
Peak memory 191392 kb
Host smart-fa148cf8-ae74-4fb1-bf82-1582daeaa6b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519980039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
519980039
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_random.3155610746
Short name T163
Test name
Test status
Simulation time 203239446009 ps
CPU time 528.7 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 04:50:13 PM PDT 24
Peak memory 191176 kb
Host smart-68448cc9-8003-4be2-a524-48fd4ed49791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155610746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3155610746
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.1154560169
Short name T221
Test name
Test status
Simulation time 1623318605989 ps
CPU time 519.36 seconds
Started Jun 22 04:41:31 PM PDT 24
Finished Jun 22 04:50:11 PM PDT 24
Peak memory 191168 kb
Host smart-c3c2313c-2937-422b-8fb7-e8968776fc6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154560169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1154560169
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1088362652
Short name T257
Test name
Test status
Simulation time 304055567301 ps
CPU time 126.83 seconds
Started Jun 22 04:41:32 PM PDT 24
Finished Jun 22 04:43:39 PM PDT 24
Peak memory 193888 kb
Host smart-8258f464-9f32-4e53-9497-116506d199a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088362652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1088362652
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/86.rv_timer_random.360899658
Short name T7
Test name
Test status
Simulation time 118696775895 ps
CPU time 443.54 seconds
Started Jun 22 04:42:09 PM PDT 24
Finished Jun 22 04:49:33 PM PDT 24
Peak memory 191080 kb
Host smart-2fbec619-3f27-4ebd-892e-b7011d7f31e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360899658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.360899658
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.508706885
Short name T31
Test name
Test status
Simulation time 58427802 ps
CPU time 0.69 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 191636 kb
Host smart-82e24d23-5f82-4acf-a4d1-350df6a6f212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508706885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.508706885
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/158.rv_timer_random.478051634
Short name T205
Test name
Test status
Simulation time 276619699534 ps
CPU time 237.86 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:46:09 PM PDT 24
Peak memory 191060 kb
Host smart-e7e6346c-48c5-486c-9047-cb9e9972e723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478051634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.478051634
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.2786104386
Short name T140
Test name
Test status
Simulation time 198106680429 ps
CPU time 1475.94 seconds
Started Jun 22 04:41:39 PM PDT 24
Finished Jun 22 05:06:15 PM PDT 24
Peak memory 191080 kb
Host smart-1fe1bc6f-828c-4e50-a1dc-9093d40f3ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786104386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2786104386
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.2911893509
Short name T177
Test name
Test status
Simulation time 171953735269 ps
CPU time 369.98 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:47:32 PM PDT 24
Peak memory 191156 kb
Host smart-43fe5b94-3899-4d2e-8c38-2f17078fe5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911893509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2911893509
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.4186938360
Short name T55
Test name
Test status
Simulation time 132244516916 ps
CPU time 139.9 seconds
Started Jun 22 04:41:49 PM PDT 24
Finished Jun 22 04:44:09 PM PDT 24
Peak memory 191088 kb
Host smart-ff50bc36-0811-4557-ac5b-20cc097f5673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186938360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4186938360
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.4245302718
Short name T160
Test name
Test status
Simulation time 677634587508 ps
CPU time 361.52 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:47:59 PM PDT 24
Peak memory 191176 kb
Host smart-70be2896-90e9-4b2d-913e-79f1fbb5237e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245302718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.4245302718
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2002406513
Short name T179
Test name
Test status
Simulation time 528787656971 ps
CPU time 1988.9 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 05:15:14 PM PDT 24
Peak memory 194152 kb
Host smart-be6765d2-9cfe-460f-bd85-61169667687a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002406513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2002406513
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.291602699
Short name T152
Test name
Test status
Simulation time 669232868405 ps
CPU time 494.58 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:50:25 PM PDT 24
Peak memory 191084 kb
Host smart-8613cc50-baa8-4494-b0a5-da68304df89a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291602699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.291602699
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.4128501584
Short name T252
Test name
Test status
Simulation time 338522845755 ps
CPU time 331.92 seconds
Started Jun 22 04:42:08 PM PDT 24
Finished Jun 22 04:47:41 PM PDT 24
Peak memory 191188 kb
Host smart-d5d719b3-f91d-47e0-a7e8-de74d5bd24fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128501584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.4128501584
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.564738724
Short name T108
Test name
Test status
Simulation time 431945316929 ps
CPU time 1038.28 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 04:59:09 PM PDT 24
Peak memory 191184 kb
Host smart-07fbd907-b49c-4457-aa3f-ec16a645689a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564738724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
564738724
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_random.418352869
Short name T279
Test name
Test status
Simulation time 853175803869 ps
CPU time 538.28 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:50:14 PM PDT 24
Peak memory 191192 kb
Host smart-819bf029-2efa-4f39-8b4c-326a88c620d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418352869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.418352869
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1245179840
Short name T6
Test name
Test status
Simulation time 77537522301 ps
CPU time 138.25 seconds
Started Jun 22 04:42:01 PM PDT 24
Finished Jun 22 04:44:19 PM PDT 24
Peak memory 193132 kb
Host smart-f1d104c2-1d74-433a-9f16-9c3ec71712c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245179840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1245179840
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3326745082
Short name T20
Test name
Test status
Simulation time 456535272024 ps
CPU time 1104.24 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 05:00:29 PM PDT 24
Peak memory 191088 kb
Host smart-5b43cee1-7ff0-413d-9345-d31fbe69e4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326745082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3326745082
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.4279524308
Short name T113
Test name
Test status
Simulation time 284797471887 ps
CPU time 379.98 seconds
Started Jun 22 04:41:17 PM PDT 24
Finished Jun 22 04:47:40 PM PDT 24
Peak memory 195688 kb
Host smart-5a3dedcf-bab6-42d9-9314-0ec619238df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279524308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.4279524308
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/134.rv_timer_random.2595455992
Short name T267
Test name
Test status
Simulation time 441434792402 ps
CPU time 309.73 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:47:17 PM PDT 24
Peak memory 191180 kb
Host smart-e6fa48bc-e7fa-43c3-ad51-2dd4245bf5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595455992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2595455992
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.118374081
Short name T207
Test name
Test status
Simulation time 407392947758 ps
CPU time 269.08 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:46:36 PM PDT 24
Peak memory 191180 kb
Host smart-155f123c-1cf1-40e0-95be-3a5fc32f50b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118374081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.118374081
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.197208050
Short name T206
Test name
Test status
Simulation time 717722323115 ps
CPU time 517.62 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:50:44 PM PDT 24
Peak memory 191172 kb
Host smart-05e62e67-d688-4ab4-8ebc-1d9dc9dd5ea3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197208050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.197208050
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.935782364
Short name T189
Test name
Test status
Simulation time 270910826806 ps
CPU time 620.69 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:52:32 PM PDT 24
Peak memory 191188 kb
Host smart-797a5a6e-0751-4570-b4cb-6c872ceab59b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935782364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.935782364
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3895976489
Short name T201
Test name
Test status
Simulation time 524373773174 ps
CPU time 884.03 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:56:06 PM PDT 24
Peak memory 182960 kb
Host smart-689149bd-cae4-442d-8445-b065f511a6fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895976489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3895976489
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.4162039514
Short name T61
Test name
Test status
Simulation time 806298515161 ps
CPU time 736.72 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:53:36 PM PDT 24
Peak memory 195476 kb
Host smart-12cd47b2-475b-4d6c-a066-d66b4843b6eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162039514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
4162039514
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3604700268
Short name T233
Test name
Test status
Simulation time 3404040063083 ps
CPU time 1541.8 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 05:07:33 PM PDT 24
Peak memory 191188 kb
Host smart-09d5cfbf-767b-41dd-be1f-9f2bf95d71e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604700268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3604700268
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2960367392
Short name T60
Test name
Test status
Simulation time 2549349586133 ps
CPU time 1341.83 seconds
Started Jun 22 04:41:54 PM PDT 24
Finished Jun 22 05:04:16 PM PDT 24
Peak memory 191184 kb
Host smart-429672b6-2a8b-47e5-b1a5-0d60524d7ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960367392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2960367392
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.1601286950
Short name T285
Test name
Test status
Simulation time 122218852543 ps
CPU time 343.2 seconds
Started Jun 22 04:41:54 PM PDT 24
Finished Jun 22 04:47:38 PM PDT 24
Peak memory 191088 kb
Host smart-a1d64e7d-53a5-4760-8e68-eaed8e980478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601286950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1601286950
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2861540637
Short name T181
Test name
Test status
Simulation time 330430353216 ps
CPU time 149.11 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 193500 kb
Host smart-eb7186f0-4a3e-4f6f-a7d9-ac8bddec540d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861540637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2861540637
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.850037936
Short name T361
Test name
Test status
Simulation time 103469938201 ps
CPU time 149.8 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:43:48 PM PDT 24
Peak memory 182884 kb
Host smart-30dc4395-c81c-453b-bc35-0671f5e708ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850037936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.850037936
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/112.rv_timer_random.3434450211
Short name T141
Test name
Test status
Simulation time 223182311052 ps
CPU time 630.07 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:52:33 PM PDT 24
Peak memory 191088 kb
Host smart-16ec210e-99b4-481f-afb8-6dbf829ee0ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434450211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3434450211
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1224790619
Short name T26
Test name
Test status
Simulation time 105433044547 ps
CPU time 228.25 seconds
Started Jun 22 04:41:19 PM PDT 24
Finished Jun 22 04:45:11 PM PDT 24
Peak memory 191084 kb
Host smart-5af91e7f-1e79-47fd-ae87-8cf468470872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224790619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1224790619
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3136033414
Short name T328
Test name
Test status
Simulation time 82095183755 ps
CPU time 416.05 seconds
Started Jun 22 04:42:26 PM PDT 24
Finished Jun 22 04:49:22 PM PDT 24
Peak memory 191092 kb
Host smart-9d6dd490-3390-434a-bdf2-38810ec53636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136033414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3136033414
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3131711256
Short name T8
Test name
Test status
Simulation time 181775715320 ps
CPU time 203.44 seconds
Started Jun 22 04:41:48 PM PDT 24
Finished Jun 22 04:45:12 PM PDT 24
Peak memory 191208 kb
Host smart-44caeb3a-6620-40e3-8a0b-68e0016f85c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131711256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3131711256
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.885318667
Short name T324
Test name
Test status
Simulation time 468233563024 ps
CPU time 262.41 seconds
Started Jun 22 04:41:52 PM PDT 24
Finished Jun 22 04:46:15 PM PDT 24
Peak memory 182880 kb
Host smart-9b70a8ac-f128-4ee4-9366-6533d60bd180
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885318667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.885318667
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2750757071
Short name T172
Test name
Test status
Simulation time 567751691295 ps
CPU time 1245.55 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 05:02:42 PM PDT 24
Peak memory 191192 kb
Host smart-9013fc6a-bbed-4037-9dbd-2a91bc4d5599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750757071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2750757071
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/67.rv_timer_random.3705084294
Short name T277
Test name
Test status
Simulation time 288873513069 ps
CPU time 195.89 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:45:14 PM PDT 24
Peak memory 193384 kb
Host smart-3b39c8b2-7819-42d4-83ad-83336e8b10a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705084294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3705084294
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.2449921346
Short name T292
Test name
Test status
Simulation time 434652638826 ps
CPU time 1514.3 seconds
Started Jun 22 04:41:07 PM PDT 24
Finished Jun 22 05:06:22 PM PDT 24
Peak memory 191112 kb
Host smart-db523832-35dd-4784-a939-0b03cb030dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449921346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2449921346
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.2486216680
Short name T149
Test name
Test status
Simulation time 92025708928 ps
CPU time 366.99 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:47:24 PM PDT 24
Peak memory 191180 kb
Host smart-9bd47343-0f21-43e4-b22b-47215c9fbf65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486216680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2486216680
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2421082204
Short name T237
Test name
Test status
Simulation time 341518428668 ps
CPU time 649.24 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:52:53 PM PDT 24
Peak memory 191176 kb
Host smart-fe43eb31-f39e-4fae-967f-e6958976f259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421082204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2421082204
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.975319047
Short name T350
Test name
Test status
Simulation time 153652112970 ps
CPU time 764.01 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:54:46 PM PDT 24
Peak memory 191076 kb
Host smart-d9a701da-01a5-4d75-845b-f7ad5c53e37b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975319047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.975319047
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.242804899
Short name T131
Test name
Test status
Simulation time 129789583372 ps
CPU time 210.89 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:45:36 PM PDT 24
Peak memory 191184 kb
Host smart-834b041f-5ce4-4cb5-991f-32f23907e804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242804899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.242804899
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2264300447
Short name T204
Test name
Test status
Simulation time 447074507030 ps
CPU time 251.61 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:46:17 PM PDT 24
Peak memory 191180 kb
Host smart-d7da90b3-9511-4571-a6bc-fd8738717851
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264300447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2264300447
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3235454899
Short name T104
Test name
Test status
Simulation time 189718609691 ps
CPU time 281.77 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:46:48 PM PDT 24
Peak memory 191172 kb
Host smart-ae1712c1-81f8-4930-bfed-489c37e6dc7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235454899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3235454899
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4083922829
Short name T227
Test name
Test status
Simulation time 1434689148597 ps
CPU time 1388.42 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 05:04:32 PM PDT 24
Peak memory 191088 kb
Host smart-972abc3e-9ffa-4bd1-8398-b88761be15c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083922829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4083922829
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/183.rv_timer_random.493390122
Short name T124
Test name
Test status
Simulation time 86590393725 ps
CPU time 138.51 seconds
Started Jun 22 04:42:18 PM PDT 24
Finished Jun 22 04:44:37 PM PDT 24
Peak memory 191176 kb
Host smart-34d5f492-d9a6-43cf-9f99-c714417493c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493390122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.493390122
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3705874622
Short name T153
Test name
Test status
Simulation time 3092419542 ps
CPU time 109.78 seconds
Started Jun 22 04:42:24 PM PDT 24
Finished Jun 22 04:44:14 PM PDT 24
Peak memory 182884 kb
Host smart-17c039f9-e0bd-4d6a-b085-11e94a3734ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705874622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3705874622
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.2817197387
Short name T288
Test name
Test status
Simulation time 63509755709 ps
CPU time 112.21 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:43:16 PM PDT 24
Peak memory 191180 kb
Host smart-79fd7036-6210-4b5c-a00e-a5b50461177c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817197387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2817197387
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.440978851
Short name T125
Test name
Test status
Simulation time 11054987420 ps
CPU time 63.78 seconds
Started Jun 22 04:41:36 PM PDT 24
Finished Jun 22 04:42:41 PM PDT 24
Peak memory 194504 kb
Host smart-3d1aeab8-0dfa-4f41-9d2e-db9c2664b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440978851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.440978851
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_random.1699011980
Short name T193
Test name
Test status
Simulation time 52436917610 ps
CPU time 77 seconds
Started Jun 22 04:41:41 PM PDT 24
Finished Jun 22 04:42:59 PM PDT 24
Peak memory 191180 kb
Host smart-48e97c26-5f41-4781-8e21-ed638fd13688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699011980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1699011980
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.1507626376
Short name T150
Test name
Test status
Simulation time 531265548689 ps
CPU time 510.14 seconds
Started Jun 22 04:41:53 PM PDT 24
Finished Jun 22 04:50:23 PM PDT 24
Peak memory 191132 kb
Host smart-76801038-f58b-4e39-8bca-b7eb92fc68a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507626376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1507626376
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.703148402
Short name T195
Test name
Test status
Simulation time 813364081785 ps
CPU time 869.15 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:56:27 PM PDT 24
Peak memory 191180 kb
Host smart-5cbd2751-f6ea-4d1c-88ad-08667df4b08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703148402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
703148402
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.633624140
Short name T23
Test name
Test status
Simulation time 210969193373 ps
CPU time 2667.71 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 05:26:27 PM PDT 24
Peak memory 191180 kb
Host smart-430ecf11-83e6-49e8-9fca-0b2430f107d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633624140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.633624140
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.4227116158
Short name T218
Test name
Test status
Simulation time 553444997736 ps
CPU time 474.4 seconds
Started Jun 22 04:41:55 PM PDT 24
Finished Jun 22 04:49:50 PM PDT 24
Peak memory 191100 kb
Host smart-30e20f8c-0cbb-4cb3-bd66-8adebdecfb58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227116158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.4227116158
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.3057433727
Short name T229
Test name
Test status
Simulation time 67121651192 ps
CPU time 100.25 seconds
Started Jun 22 04:42:00 PM PDT 24
Finished Jun 22 04:43:40 PM PDT 24
Peak memory 191020 kb
Host smart-1983887f-14e1-4b53-a682-587fb7c0052f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057433727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3057433727
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1824743607
Short name T171
Test name
Test status
Simulation time 202441698431 ps
CPU time 326.55 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:47:24 PM PDT 24
Peak memory 191180 kb
Host smart-e9fa1b62-5ec9-4d1e-9671-c70d83fd8a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824743607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1824743607
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3887213311
Short name T553
Test name
Test status
Simulation time 345983932 ps
CPU time 0.81 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:03 PM PDT 24
Peak memory 193680 kb
Host smart-fae8319b-9244-4be1-99bd-6dffad1eab54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887213311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3887213311
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1653842881
Short name T64
Test name
Test status
Simulation time 162263139649 ps
CPU time 223.87 seconds
Started Jun 22 04:41:07 PM PDT 24
Finished Jun 22 04:44:51 PM PDT 24
Peak memory 191184 kb
Host smart-c201def3-26a2-4e52-93a1-06ff64fa17f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653842881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1653842881
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.3994484626
Short name T255
Test name
Test status
Simulation time 702585289960 ps
CPU time 174.87 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:44:57 PM PDT 24
Peak memory 194328 kb
Host smart-441af9cc-dc6e-4b44-aec0-74ede4352b98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994484626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3994484626
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.737128832
Short name T310
Test name
Test status
Simulation time 453456514048 ps
CPU time 687.8 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:53:31 PM PDT 24
Peak memory 191088 kb
Host smart-445be2f5-fee3-4eaf-bb1d-c4818bcbefa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737128832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.737128832
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2034932053
Short name T97
Test name
Test status
Simulation time 169427116200 ps
CPU time 496.88 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:50:22 PM PDT 24
Peak memory 195028 kb
Host smart-8345ea0e-9030-4c69-9511-e8d11a75c3c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034932053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2034932053
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1751937339
Short name T228
Test name
Test status
Simulation time 1113974269521 ps
CPU time 609.98 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:52:16 PM PDT 24
Peak memory 191184 kb
Host smart-b1af3bd1-864d-48e2-906c-37d5822bd411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751937339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1751937339
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4126910336
Short name T147
Test name
Test status
Simulation time 186214867479 ps
CPU time 290.91 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 191088 kb
Host smart-f50aae98-294e-4fa8-b853-caf34cb78bcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126910336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4126910336
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2446573510
Short name T270
Test name
Test status
Simulation time 609738803012 ps
CPU time 166.33 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:44:53 PM PDT 24
Peak memory 191188 kb
Host smart-40fb7576-46d9-4d26-95a3-56d05732b6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446573510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2446573510
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1289342657
Short name T156
Test name
Test status
Simulation time 480946087370 ps
CPU time 372 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:48:23 PM PDT 24
Peak memory 190996 kb
Host smart-a379ae27-fce2-49e2-9e76-8abb3e73c734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289342657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1289342657
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2341033372
Short name T260
Test name
Test status
Simulation time 124562389938 ps
CPU time 161.01 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:44:52 PM PDT 24
Peak memory 191092 kb
Host smart-91f8ab7d-6dd5-47d7-9391-e05f278efa2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341033372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2341033372
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3983476885
Short name T325
Test name
Test status
Simulation time 274645554718 ps
CPU time 1276.38 seconds
Started Jun 22 04:42:11 PM PDT 24
Finished Jun 22 05:03:28 PM PDT 24
Peak memory 191188 kb
Host smart-95a18e93-28e1-429e-a931-748b1090fb08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983476885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3983476885
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.873969859
Short name T312
Test name
Test status
Simulation time 234463262674 ps
CPU time 115.55 seconds
Started Jun 22 04:42:09 PM PDT 24
Finished Jun 22 04:44:05 PM PDT 24
Peak memory 191088 kb
Host smart-d4b04329-6128-47de-b327-1602d17228c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873969859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.873969859
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3817644610
Short name T346
Test name
Test status
Simulation time 92659768596 ps
CPU time 259.85 seconds
Started Jun 22 04:41:19 PM PDT 24
Finished Jun 22 04:45:42 PM PDT 24
Peak memory 191116 kb
Host smart-ce8e3615-dbc5-457d-931e-2e86fe28c693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817644610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3817644610
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.597024803
Short name T123
Test name
Test status
Simulation time 279273278654 ps
CPU time 197.55 seconds
Started Jun 22 04:42:18 PM PDT 24
Finished Jun 22 04:45:36 PM PDT 24
Peak memory 191060 kb
Host smart-76fec4a8-66e0-4613-af8b-dfa4577458c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597024803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.597024803
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3971663186
Short name T362
Test name
Test status
Simulation time 59026641938 ps
CPU time 53.76 seconds
Started Jun 22 04:42:19 PM PDT 24
Finished Jun 22 04:43:13 PM PDT 24
Peak memory 191184 kb
Host smart-466acd2b-45b8-464a-817c-5ffbe217ac76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971663186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3971663186
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1962984865
Short name T210
Test name
Test status
Simulation time 64822819378 ps
CPU time 109.81 seconds
Started Jun 22 04:42:25 PM PDT 24
Finished Jun 22 04:44:15 PM PDT 24
Peak memory 191052 kb
Host smart-17b75e84-8068-4f60-98ab-a3c6c95f3d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962984865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1962984865
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3194099789
Short name T253
Test name
Test status
Simulation time 575933045884 ps
CPU time 298.32 seconds
Started Jun 22 04:42:24 PM PDT 24
Finished Jun 22 04:47:22 PM PDT 24
Peak memory 191052 kb
Host smart-f5d6e0f1-fc52-41c5-ac9c-84b4c34613b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194099789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3194099789
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.608941155
Short name T289
Test name
Test status
Simulation time 97095380510 ps
CPU time 605.09 seconds
Started Jun 22 04:42:18 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 191184 kb
Host smart-149f8642-a4d5-4825-91c3-1cf1c69f3b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608941155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.608941155
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3803929886
Short name T107
Test name
Test status
Simulation time 371071235738 ps
CPU time 290.83 seconds
Started Jun 22 04:41:29 PM PDT 24
Finished Jun 22 04:46:21 PM PDT 24
Peak memory 182980 kb
Host smart-2aa7857c-d369-46cd-84dd-43d64fc37e46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803929886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3803929886
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_random.3767695959
Short name T222
Test name
Test status
Simulation time 110304789293 ps
CPU time 378.95 seconds
Started Jun 22 04:41:28 PM PDT 24
Finished Jun 22 04:47:48 PM PDT 24
Peak memory 191092 kb
Host smart-b52d188e-6aee-4f9e-8e98-2346a42a4e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767695959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3767695959
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3387696334
Short name T135
Test name
Test status
Simulation time 32668424210 ps
CPU time 67.62 seconds
Started Jun 22 04:41:30 PM PDT 24
Finished Jun 22 04:42:38 PM PDT 24
Peak memory 191208 kb
Host smart-25eecf93-cbed-4f5c-bea2-49fb44ab9127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387696334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3387696334
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_random.1332263153
Short name T354
Test name
Test status
Simulation time 939521336265 ps
CPU time 286.06 seconds
Started Jun 22 04:41:39 PM PDT 24
Finished Jun 22 04:46:25 PM PDT 24
Peak memory 191052 kb
Host smart-b134cff2-9afd-402e-97cb-0af43843ae42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332263153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1332263153
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.374493991
Short name T99
Test name
Test status
Simulation time 301722876848 ps
CPU time 258.18 seconds
Started Jun 22 04:41:36 PM PDT 24
Finished Jun 22 04:45:55 PM PDT 24
Peak memory 182984 kb
Host smart-a14f47b0-402d-4a8d-add0-6860e07e7a6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374493991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.374493991
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random.2343321056
Short name T165
Test name
Test status
Simulation time 83765869295 ps
CPU time 183.26 seconds
Started Jun 22 04:41:37 PM PDT 24
Finished Jun 22 04:44:41 PM PDT 24
Peak memory 191188 kb
Host smart-c5ee781b-0ff1-40f0-8b14-f9f60aec074a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343321056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2343321056
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.89791071
Short name T356
Test name
Test status
Simulation time 615409028704 ps
CPU time 484.39 seconds
Started Jun 22 04:41:52 PM PDT 24
Finished Jun 22 04:49:57 PM PDT 24
Peak memory 191124 kb
Host smart-f8741a76-29bc-468c-990a-0cf05abde039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89791071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.89791071
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_random.390094276
Short name T134
Test name
Test status
Simulation time 141409501647 ps
CPU time 636.31 seconds
Started Jun 22 04:41:47 PM PDT 24
Finished Jun 22 04:52:24 PM PDT 24
Peak memory 191056 kb
Host smart-bca7de7f-ac24-44af-87d7-3ba2534d4a74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390094276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.390094276
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1463484336
Short name T296
Test name
Test status
Simulation time 303278808986 ps
CPU time 1292.53 seconds
Started Jun 22 04:41:53 PM PDT 24
Finished Jun 22 05:03:26 PM PDT 24
Peak memory 183004 kb
Host smart-4510f3ee-e1e8-4027-aedc-7463c2af51fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463484336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1463484336
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3367095869
Short name T122
Test name
Test status
Simulation time 330012117195 ps
CPU time 890.93 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:56:49 PM PDT 24
Peak memory 194984 kb
Host smart-3c2b45b9-3b15-4f22-9e83-7c27ff34857c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367095869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3367095869
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_random.3422076980
Short name T313
Test name
Test status
Simulation time 57406428944 ps
CPU time 179.96 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:44:56 PM PDT 24
Peak memory 182956 kb
Host smart-85e42796-2b5d-4535-8d21-abf355985e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422076980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3422076980
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1003707342
Short name T188
Test name
Test status
Simulation time 77192201361 ps
CPU time 140.78 seconds
Started Jun 22 04:41:58 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 191184 kb
Host smart-8c564b88-b92b-4231-9c31-860e6e22cf3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003707342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1003707342
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2407779853
Short name T358
Test name
Test status
Simulation time 97545236127 ps
CPU time 556.92 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:51:20 PM PDT 24
Peak memory 182976 kb
Host smart-6b430cdf-a361-413d-8687-59e33f1580cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407779853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2407779853
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2578362641
Short name T569
Test name
Test status
Simulation time 97752793 ps
CPU time 0.75 seconds
Started Jun 22 04:34:49 PM PDT 24
Finished Jun 22 04:34:51 PM PDT 24
Peak memory 192288 kb
Host smart-111f87e0-4ca1-4263-888d-eea6a6fe0075
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578362641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2578362641
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4158105253
Short name T78
Test name
Test status
Simulation time 424770491 ps
CPU time 3.1 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:35:01 PM PDT 24
Peak memory 192372 kb
Host smart-85abfca6-90d3-4047-9315-9e8218244767
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158105253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.4158105253
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1281424245
Short name T474
Test name
Test status
Simulation time 52303717 ps
CPU time 0.54 seconds
Started Jun 22 04:34:55 PM PDT 24
Finished Jun 22 04:34:56 PM PDT 24
Peak memory 182580 kb
Host smart-7a2307c7-2003-411b-9313-b95a6f296df6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281424245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1281424245
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3082076990
Short name T457
Test name
Test status
Simulation time 37873258 ps
CPU time 0.61 seconds
Started Jun 22 04:35:00 PM PDT 24
Finished Jun 22 04:35:02 PM PDT 24
Peak memory 192928 kb
Host smart-49bfb4e4-95aa-4632-ad5d-8cad696ee638
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082076990 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3082076990
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3442770812
Short name T559
Test name
Test status
Simulation time 39451056 ps
CPU time 0.55 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:03 PM PDT 24
Peak memory 182532 kb
Host smart-b433762b-d60a-45c6-9829-1c7a845a4fd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442770812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3442770812
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3089761439
Short name T509
Test name
Test status
Simulation time 19674987 ps
CPU time 0.58 seconds
Started Jun 22 04:34:50 PM PDT 24
Finished Jun 22 04:34:52 PM PDT 24
Peak memory 182464 kb
Host smart-c61d502c-2378-47e7-bb0f-e1f03a50a08d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089761439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3089761439
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3086058231
Short name T70
Test name
Test status
Simulation time 16733752 ps
CPU time 0.67 seconds
Started Jun 22 04:35:13 PM PDT 24
Finished Jun 22 04:35:14 PM PDT 24
Peak memory 193048 kb
Host smart-ef8e8900-06a2-4917-8d3f-14355d22949c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086058231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3086058231
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1831239221
Short name T545
Test name
Test status
Simulation time 225562143 ps
CPU time 1.72 seconds
Started Jun 22 04:34:58 PM PDT 24
Finished Jun 22 04:35:01 PM PDT 24
Peak memory 197468 kb
Host smart-aca1c921-c12e-4667-a7d7-0266090d69dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831239221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1831239221
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2602984996
Short name T82
Test name
Test status
Simulation time 953241000 ps
CPU time 2.81 seconds
Started Jun 22 04:34:48 PM PDT 24
Finished Jun 22 04:34:52 PM PDT 24
Peak memory 192388 kb
Host smart-c7623f01-b304-4b4f-a7a2-f1b16cb1accd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602984996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2602984996
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2275940202
Short name T478
Test name
Test status
Simulation time 47813291 ps
CPU time 0.55 seconds
Started Jun 22 04:34:51 PM PDT 24
Finished Jun 22 04:34:52 PM PDT 24
Peak memory 182580 kb
Host smart-8894f746-782c-4496-85b8-958f3f3dec55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275940202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2275940202
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.59230985
Short name T547
Test name
Test status
Simulation time 43495157 ps
CPU time 0.94 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 197264 kb
Host smart-39ed02a4-6d25-4889-b7c1-846bc9b24e2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59230985 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.59230985
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3921436462
Short name T459
Test name
Test status
Simulation time 19412168 ps
CPU time 0.55 seconds
Started Jun 22 04:34:54 PM PDT 24
Finished Jun 22 04:34:55 PM PDT 24
Peak memory 182536 kb
Host smart-e42376cf-66fd-441b-935c-cdfa193f88e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921436462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3921436462
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1951643392
Short name T568
Test name
Test status
Simulation time 12287220 ps
CPU time 0.51 seconds
Started Jun 22 04:35:03 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 181988 kb
Host smart-c7f9a911-6dbb-4b4f-ae2e-0b2f5a29bbde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951643392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1951643392
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.807148384
Short name T531
Test name
Test status
Simulation time 183180856 ps
CPU time 0.61 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:03 PM PDT 24
Peak memory 192272 kb
Host smart-63346c86-81b3-4bbe-9547-280787cd6705
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807148384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.807148384
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2185838785
Short name T552
Test name
Test status
Simulation time 119447990 ps
CPU time 1.53 seconds
Started Jun 22 04:34:53 PM PDT 24
Finished Jun 22 04:34:55 PM PDT 24
Peak memory 197384 kb
Host smart-f0bf86e9-73e6-4f67-bc6c-9ff1f12dd23c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185838785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2185838785
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3114035209
Short name T566
Test name
Test status
Simulation time 51687655 ps
CPU time 0.86 seconds
Started Jun 22 04:34:52 PM PDT 24
Finished Jun 22 04:34:53 PM PDT 24
Peak memory 193576 kb
Host smart-626b3d5c-4f58-40bd-995d-b4a3af680305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114035209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3114035209
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.118608674
Short name T48
Test name
Test status
Simulation time 20048833 ps
CPU time 0.64 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:07 PM PDT 24
Peak memory 193784 kb
Host smart-ac3e532a-1f39-4654-b218-7ee11dc3b1c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118608674 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.118608674
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1419346857
Short name T87
Test name
Test status
Simulation time 25505460 ps
CPU time 0.54 seconds
Started Jun 22 04:35:14 PM PDT 24
Finished Jun 22 04:35:15 PM PDT 24
Peak memory 182560 kb
Host smart-4f6dcc9a-f0a9-4c12-84a0-df7cf8f647cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419346857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1419346857
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1077183234
Short name T460
Test name
Test status
Simulation time 14946442 ps
CPU time 0.55 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 182464 kb
Host smart-874a29ff-aafb-4075-88a0-99384b7203eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077183234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1077183234
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.367700823
Short name T562
Test name
Test status
Simulation time 41374017 ps
CPU time 0.84 seconds
Started Jun 22 04:35:20 PM PDT 24
Finished Jun 22 04:35:21 PM PDT 24
Peak memory 193216 kb
Host smart-b918f945-3f49-4b5f-8870-d3aea44552f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367700823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.367700823
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.180277343
Short name T458
Test name
Test status
Simulation time 257992743 ps
CPU time 1.58 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 197464 kb
Host smart-5d10d13d-3356-450f-8eee-f8930c29e9a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180277343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.180277343
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.860162417
Short name T481
Test name
Test status
Simulation time 71930476 ps
CPU time 1.1 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:06 PM PDT 24
Peak memory 194912 kb
Host smart-0d3e6367-de91-4de9-aca3-7e820c21fa12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860162417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.860162417
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.27624410
Short name T487
Test name
Test status
Simulation time 167124316 ps
CPU time 0.9 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 196988 kb
Host smart-85b4a1e8-74ed-489e-81da-1ecb41c9196e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27624410 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.27624410
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1074413795
Short name T49
Test name
Test status
Simulation time 50536931 ps
CPU time 0.6 seconds
Started Jun 22 04:35:13 PM PDT 24
Finished Jun 22 04:35:14 PM PDT 24
Peak memory 182584 kb
Host smart-07fb24a8-cfb3-4a0b-8764-4171ad3a76cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074413795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1074413795
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2878233615
Short name T450
Test name
Test status
Simulation time 16987315 ps
CPU time 0.53 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 182556 kb
Host smart-25a06076-cf07-42cd-8ed3-62c4a021742d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878233615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2878233615
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2037121211
Short name T570
Test name
Test status
Simulation time 85565942 ps
CPU time 1.17 seconds
Started Jun 22 04:35:07 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 196884 kb
Host smart-eb0623a5-0d48-411c-b46a-5ba6a32a95f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037121211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2037121211
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2232761794
Short name T29
Test name
Test status
Simulation time 38616137 ps
CPU time 0.79 seconds
Started Jun 22 04:35:07 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 182980 kb
Host smart-d480887a-4102-43e6-9266-8bd3a1a1981c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232761794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2232761794
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2076737485
Short name T563
Test name
Test status
Simulation time 29082457 ps
CPU time 0.72 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 194980 kb
Host smart-b561ec42-73e2-4304-9213-c92a799b683c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076737485 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2076737485
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3171202562
Short name T495
Test name
Test status
Simulation time 17729923 ps
CPU time 0.59 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:07 PM PDT 24
Peak memory 182584 kb
Host smart-51431b04-90a8-42af-ba7f-32a18e6f5cf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171202562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3171202562
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1119337020
Short name T454
Test name
Test status
Simulation time 16486317 ps
CPU time 0.53 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:03 PM PDT 24
Peak memory 182440 kb
Host smart-27209cc2-d775-4c40-9804-95888211aefd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119337020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1119337020
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.822664187
Short name T538
Test name
Test status
Simulation time 89999356 ps
CPU time 0.63 seconds
Started Jun 22 04:35:14 PM PDT 24
Finished Jun 22 04:35:15 PM PDT 24
Peak memory 191876 kb
Host smart-37cab13c-24d0-4d17-9e71-191f050ee09e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822664187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.822664187
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3766935607
Short name T465
Test name
Test status
Simulation time 799831148 ps
CPU time 2.13 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 197500 kb
Host smart-d73c7c64-abdc-4507-bc77-5f18061c5644
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766935607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3766935607
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1622633851
Short name T572
Test name
Test status
Simulation time 493319708 ps
CPU time 1.34 seconds
Started Jun 22 04:35:32 PM PDT 24
Finished Jun 22 04:35:33 PM PDT 24
Peak memory 195276 kb
Host smart-aedad1a4-c67d-4311-89f1-7f0f09d4fd33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622633851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1622633851
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.363400160
Short name T477
Test name
Test status
Simulation time 36491264 ps
CPU time 1 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 197288 kb
Host smart-a65e7bcd-43f4-4340-b331-2de6c9033a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363400160 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.363400160
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.557858221
Short name T76
Test name
Test status
Simulation time 28651363 ps
CPU time 0.58 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 182584 kb
Host smart-bd3c8933-2f99-4f93-bd63-20c584df8f72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557858221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.557858221
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1082773629
Short name T451
Test name
Test status
Simulation time 34818957 ps
CPU time 0.53 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:04 PM PDT 24
Peak memory 181928 kb
Host smart-b61017fc-05d4-40e5-8adb-b5e830b6e902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082773629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1082773629
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1604046598
Short name T517
Test name
Test status
Simulation time 37960317 ps
CPU time 0.75 seconds
Started Jun 22 04:35:00 PM PDT 24
Finished Jun 22 04:35:02 PM PDT 24
Peak memory 193020 kb
Host smart-55139f89-1357-4d5b-a5b9-98139f2af674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604046598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1604046598
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1954407505
Short name T467
Test name
Test status
Simulation time 252086729 ps
CPU time 1.51 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 197444 kb
Host smart-274e1f0e-3284-49d3-b752-5431629abc6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954407505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1954407505
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3949558316
Short name T573
Test name
Test status
Simulation time 30776837 ps
CPU time 0.6 seconds
Started Jun 22 04:35:18 PM PDT 24
Finished Jun 22 04:35:19 PM PDT 24
Peak memory 193256 kb
Host smart-b63ad0ec-34d3-4f3f-9147-82171b3124c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949558316 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3949558316
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2856293216
Short name T74
Test name
Test status
Simulation time 232627466 ps
CPU time 0.54 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:04 PM PDT 24
Peak memory 182584 kb
Host smart-829df5be-272e-44db-8b11-179f0a8f5cee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856293216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2856293216
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3037469794
Short name T449
Test name
Test status
Simulation time 119127992 ps
CPU time 0.54 seconds
Started Jun 22 04:35:14 PM PDT 24
Finished Jun 22 04:35:20 PM PDT 24
Peak memory 181968 kb
Host smart-bf2564cb-62e7-4e50-83ee-34a6b989d71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037469794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3037469794
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.190468207
Short name T88
Test name
Test status
Simulation time 124957205 ps
CPU time 0.64 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 191884 kb
Host smart-599f6479-1818-470e-b75c-2b562217d9da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190468207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.190468207
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3394178653
Short name T489
Test name
Test status
Simulation time 171716159 ps
CPU time 2.63 seconds
Started Jun 22 04:35:31 PM PDT 24
Finished Jun 22 04:35:34 PM PDT 24
Peak memory 197716 kb
Host smart-28c5fe20-2bbe-4a58-aecc-5cdaf463f88c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394178653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3394178653
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4130749762
Short name T537
Test name
Test status
Simulation time 230235930 ps
CPU time 0.78 seconds
Started Jun 22 04:35:10 PM PDT 24
Finished Jun 22 04:35:12 PM PDT 24
Peak memory 182960 kb
Host smart-b053b3fd-204e-42cb-a69d-1187566ee2a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130749762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4130749762
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2491311581
Short name T500
Test name
Test status
Simulation time 247568272 ps
CPU time 0.89 seconds
Started Jun 22 04:34:52 PM PDT 24
Finished Jun 22 04:34:54 PM PDT 24
Peak memory 196908 kb
Host smart-d24a4a8e-9322-47da-898b-60c553682fdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491311581 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2491311581
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.760380613
Short name T71
Test name
Test status
Simulation time 45049347 ps
CPU time 0.56 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:06 PM PDT 24
Peak memory 182588 kb
Host smart-572098bf-fa7e-4514-b4b8-9703b269beb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760380613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.760380613
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1473612339
Short name T494
Test name
Test status
Simulation time 38435891 ps
CPU time 0.52 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 181936 kb
Host smart-8a9c82c1-d67e-4e1f-9f95-4141a937c1a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473612339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1473612339
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.147952461
Short name T524
Test name
Test status
Simulation time 12231099 ps
CPU time 0.58 seconds
Started Jun 22 04:35:00 PM PDT 24
Finished Jun 22 04:35:02 PM PDT 24
Peak memory 191252 kb
Host smart-3bc4d433-d81d-432a-9449-f816b5a96e24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147952461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.147952461
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3863001082
Short name T470
Test name
Test status
Simulation time 44137138 ps
CPU time 2.1 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 197532 kb
Host smart-66098014-01c6-443c-815d-b45b023080a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863001082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3863001082
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3652684907
Short name T92
Test name
Test status
Simulation time 87029451 ps
CPU time 1.12 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 195136 kb
Host smart-07ac7aad-631c-464a-bb67-0f11a0b17195
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652684907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3652684907
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2895673374
Short name T520
Test name
Test status
Simulation time 106026114 ps
CPU time 0.77 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 195136 kb
Host smart-60d2b31f-5bdd-4996-96c2-329ec02ac1dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895673374 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2895673374
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.604853681
Short name T480
Test name
Test status
Simulation time 12942262 ps
CPU time 0.53 seconds
Started Jun 22 04:35:07 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 182220 kb
Host smart-99f29700-91da-45d1-9e4e-edc335c922a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604853681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.604853681
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2184743978
Short name T557
Test name
Test status
Simulation time 51521241 ps
CPU time 0.56 seconds
Started Jun 22 04:35:16 PM PDT 24
Finished Jun 22 04:35:17 PM PDT 24
Peak memory 182496 kb
Host smart-2f6cb7ca-279a-4630-9097-c4bccd652839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184743978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2184743978
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.647709296
Short name T89
Test name
Test status
Simulation time 18984068 ps
CPU time 0.76 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 193224 kb
Host smart-3e887800-4f93-45df-999d-e7700c718b95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647709296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.647709296
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.476549075
Short name T471
Test name
Test status
Simulation time 106650728 ps
CPU time 1.24 seconds
Started Jun 22 04:35:12 PM PDT 24
Finished Jun 22 04:35:14 PM PDT 24
Peak memory 197396 kb
Host smart-5ec3360e-6976-45a8-83ee-9db015b7e698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476549075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.476549075
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.595938382
Short name T532
Test name
Test status
Simulation time 196502025 ps
CPU time 1.11 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 195196 kb
Host smart-e162e6fc-4fe6-4937-9228-13fafa6fd3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595938382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.595938382
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2627397439
Short name T521
Test name
Test status
Simulation time 27450772 ps
CPU time 1.16 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 197476 kb
Host smart-637ccf70-540b-446c-a781-01f240dc67cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627397439 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2627397439
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.784158206
Short name T466
Test name
Test status
Simulation time 34338094 ps
CPU time 0.53 seconds
Started Jun 22 04:35:13 PM PDT 24
Finished Jun 22 04:35:14 PM PDT 24
Peak memory 182584 kb
Host smart-8c8db430-b499-4fe0-ad14-d233ff7b974d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784158206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.784158206
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1098440511
Short name T528
Test name
Test status
Simulation time 45540619 ps
CPU time 0.51 seconds
Started Jun 22 04:35:21 PM PDT 24
Finished Jun 22 04:35:22 PM PDT 24
Peak memory 182444 kb
Host smart-0de5edb3-a388-4747-b727-f130b6e04dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098440511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1098440511
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.634775939
Short name T541
Test name
Test status
Simulation time 35511918 ps
CPU time 0.79 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 191612 kb
Host smart-a33e1994-f99c-4e0b-a009-f24f9ebf1fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634775939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.634775939
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2039183467
Short name T535
Test name
Test status
Simulation time 581337061 ps
CPU time 2.32 seconds
Started Jun 22 04:35:08 PM PDT 24
Finished Jun 22 04:35:13 PM PDT 24
Peak memory 197388 kb
Host smart-e7de6981-2714-4204-9bb0-a78668ca77b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039183467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2039183467
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.54403645
Short name T91
Test name
Test status
Simulation time 214486335 ps
CPU time 0.79 seconds
Started Jun 22 04:35:07 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 193416 kb
Host smart-6d389974-0bd5-43b1-a232-bbe8e35e5152
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54403645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_int
g_err.54403645
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.496748742
Short name T516
Test name
Test status
Simulation time 121916840 ps
CPU time 0.86 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 197240 kb
Host smart-e70c8142-b28b-4fe4-9ddf-d432e60fdb0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496748742 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.496748742
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.762817509
Short name T73
Test name
Test status
Simulation time 15275863 ps
CPU time 0.59 seconds
Started Jun 22 04:35:23 PM PDT 24
Finished Jun 22 04:35:24 PM PDT 24
Peak memory 191808 kb
Host smart-140d1854-d5f8-4934-9756-7ba5282264ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762817509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.762817509
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.197322749
Short name T463
Test name
Test status
Simulation time 56921421 ps
CPU time 0.58 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 182452 kb
Host smart-13e8a7c7-7ab9-48b2-bce0-3182a712f827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197322749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.197322749
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1622085580
Short name T551
Test name
Test status
Simulation time 19638377 ps
CPU time 0.64 seconds
Started Jun 22 04:35:07 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 192096 kb
Host smart-c3e4ed99-ca24-40a8-8c30-07f7c6624da6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622085580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1622085580
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4218703531
Short name T507
Test name
Test status
Simulation time 382916552 ps
CPU time 1.97 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 197444 kb
Host smart-8334a6d5-4743-41e3-8ba3-c728ca6e25b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218703531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4218703531
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3241645518
Short name T28
Test name
Test status
Simulation time 135574205 ps
CPU time 0.79 seconds
Started Jun 22 04:35:23 PM PDT 24
Finished Jun 22 04:35:24 PM PDT 24
Peak memory 193668 kb
Host smart-06d429f3-541d-4c74-a434-a615335a0021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241645518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3241645518
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3909388703
Short name T32
Test name
Test status
Simulation time 123308111 ps
CPU time 0.9 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 196344 kb
Host smart-e14cdb59-a0e2-47aa-a2ce-b83479f4ed03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909388703 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3909388703
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.718521991
Short name T50
Test name
Test status
Simulation time 18063476 ps
CPU time 0.58 seconds
Started Jun 22 04:35:14 PM PDT 24
Finished Jun 22 04:35:15 PM PDT 24
Peak memory 182512 kb
Host smart-3e791c7a-b510-4e91-aa24-6f34e1b47c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718521991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.718521991
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4117555370
Short name T488
Test name
Test status
Simulation time 65558060 ps
CPU time 0.57 seconds
Started Jun 22 04:35:13 PM PDT 24
Finished Jun 22 04:35:14 PM PDT 24
Peak memory 182416 kb
Host smart-26730549-e458-4ab6-9532-e6916d43e928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117555370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4117555370
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2404237799
Short name T536
Test name
Test status
Simulation time 146907858 ps
CPU time 0.81 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 193352 kb
Host smart-32632175-a0ea-496f-8cbd-0a3f79f813dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404237799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2404237799
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3497331869
Short name T59
Test name
Test status
Simulation time 482920606 ps
CPU time 2.2 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 197276 kb
Host smart-359b7d18-945f-44de-b1ca-c592d93d522b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497331869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3497331869
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2262737733
Short name T560
Test name
Test status
Simulation time 87899346 ps
CPU time 1.05 seconds
Started Jun 22 04:35:14 PM PDT 24
Finished Jun 22 04:35:15 PM PDT 24
Peak memory 194844 kb
Host smart-8a9930ce-d5f0-4e8e-844a-113233d68448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262737733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2262737733
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1917647746
Short name T508
Test name
Test status
Simulation time 85348095 ps
CPU time 0.64 seconds
Started Jun 22 04:34:48 PM PDT 24
Finished Jun 22 04:34:49 PM PDT 24
Peak memory 191804 kb
Host smart-53911384-4f94-439d-942d-4d4fba214d46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917647746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1917647746
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1451237852
Short name T512
Test name
Test status
Simulation time 63557314 ps
CPU time 2.13 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:35:00 PM PDT 24
Peak memory 193052 kb
Host smart-66270d37-3764-4c13-9a81-c243710cf0aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451237852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1451237852
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.411496213
Short name T511
Test name
Test status
Simulation time 15061180 ps
CPU time 0.55 seconds
Started Jun 22 04:34:58 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 182580 kb
Host smart-2d50b821-7222-4609-ac1a-b193a5245f5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411496213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.411496213
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1217419071
Short name T558
Test name
Test status
Simulation time 90326031 ps
CPU time 0.8 seconds
Started Jun 22 04:34:51 PM PDT 24
Finished Jun 22 04:34:52 PM PDT 24
Peak memory 195128 kb
Host smart-4c5415d9-6f1c-4612-bb88-af8c1c8ef10b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217419071 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1217419071
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3300018401
Short name T493
Test name
Test status
Simulation time 46136719 ps
CPU time 0.61 seconds
Started Jun 22 04:34:56 PM PDT 24
Finished Jun 22 04:34:58 PM PDT 24
Peak memory 182588 kb
Host smart-002aee72-9f81-404d-9263-32c5608cd0fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300018401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3300018401
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4257282936
Short name T473
Test name
Test status
Simulation time 14367629 ps
CPU time 0.52 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 182416 kb
Host smart-47bc28d7-9c0e-4930-87cf-b5e184a239cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257282936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.4257282936
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3712209006
Short name T69
Test name
Test status
Simulation time 41869474 ps
CPU time 0.55 seconds
Started Jun 22 04:34:59 PM PDT 24
Finished Jun 22 04:35:01 PM PDT 24
Peak memory 191260 kb
Host smart-f1940d5d-6563-4d38-97ac-04d1b62e377c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712209006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3712209006
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.608351979
Short name T546
Test name
Test status
Simulation time 516555579 ps
CPU time 2.1 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:07 PM PDT 24
Peak memory 197472 kb
Host smart-2fc0340d-d6d4-4a77-bd48-b6eacd80e534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608351979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.608351979
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4012967533
Short name T90
Test name
Test status
Simulation time 325668476 ps
CPU time 1.1 seconds
Started Jun 22 04:34:55 PM PDT 24
Finished Jun 22 04:34:57 PM PDT 24
Peak memory 194864 kb
Host smart-1be19a68-efad-45d4-8794-60b8c99ff098
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012967533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.4012967533
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2311558080
Short name T554
Test name
Test status
Simulation time 80015367 ps
CPU time 0.55 seconds
Started Jun 22 04:35:17 PM PDT 24
Finished Jun 22 04:35:18 PM PDT 24
Peak memory 182412 kb
Host smart-3ba4ff61-357b-4783-8485-6b3001a8fb85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311558080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2311558080
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.83192131
Short name T514
Test name
Test status
Simulation time 11609896 ps
CPU time 0.51 seconds
Started Jun 22 04:35:12 PM PDT 24
Finished Jun 22 04:35:13 PM PDT 24
Peak memory 182100 kb
Host smart-ad3c233d-90ca-49a4-bef2-590e8e5017b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83192131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.83192131
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3501858577
Short name T534
Test name
Test status
Simulation time 31755011 ps
CPU time 0.52 seconds
Started Jun 22 04:35:09 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 181876 kb
Host smart-e4e6fd0d-5d74-4628-8f35-63d27738be45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501858577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3501858577
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.14985909
Short name T469
Test name
Test status
Simulation time 16169709 ps
CPU time 0.56 seconds
Started Jun 22 04:35:25 PM PDT 24
Finished Jun 22 04:35:25 PM PDT 24
Peak memory 182528 kb
Host smart-01066f77-234c-4692-ac11-41aebc98e026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14985909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.14985909
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.59821668
Short name T503
Test name
Test status
Simulation time 58597756 ps
CPU time 0.56 seconds
Started Jun 22 04:35:00 PM PDT 24
Finished Jun 22 04:35:02 PM PDT 24
Peak memory 182476 kb
Host smart-0c4599a7-1348-4ff2-a9e6-1dc9c9c90c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59821668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.59821668
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3392988442
Short name T464
Test name
Test status
Simulation time 29775093 ps
CPU time 0.55 seconds
Started Jun 22 04:35:12 PM PDT 24
Finished Jun 22 04:35:13 PM PDT 24
Peak memory 182548 kb
Host smart-6a4b855a-df78-40c8-b770-8deee6eccb0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392988442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3392988442
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1534734483
Short name T483
Test name
Test status
Simulation time 38850432 ps
CPU time 0.52 seconds
Started Jun 22 04:35:09 PM PDT 24
Finished Jun 22 04:35:12 PM PDT 24
Peak memory 181936 kb
Host smart-cfb67d8e-9170-4cef-8904-90649ce1bbd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534734483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1534734483
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3625942071
Short name T479
Test name
Test status
Simulation time 40200963 ps
CPU time 0.53 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 181940 kb
Host smart-e906506b-1bd9-4d2b-8177-f04b509baaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625942071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3625942071
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.95859931
Short name T525
Test name
Test status
Simulation time 11003982 ps
CPU time 0.54 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 182096 kb
Host smart-7e42e73e-cfbf-45f6-8ce5-06e19af6468e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95859931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.95859931
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1989290003
Short name T530
Test name
Test status
Simulation time 25266712 ps
CPU time 0.51 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:06 PM PDT 24
Peak memory 181932 kb
Host smart-d6f3c3fe-3657-40d8-abca-bd1b59e3a15c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989290003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1989290003
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2011428642
Short name T499
Test name
Test status
Simulation time 59303687 ps
CPU time 0.81 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 192472 kb
Host smart-1c00794b-4316-4de4-821a-54322f529482
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011428642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2011428642
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.363211783
Short name T505
Test name
Test status
Simulation time 38560979 ps
CPU time 1.42 seconds
Started Jun 22 04:34:59 PM PDT 24
Finished Jun 22 04:35:02 PM PDT 24
Peak memory 192048 kb
Host smart-41092f45-a9ed-4e13-b38e-7d16e266b633
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363211783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.363211783
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1269693150
Short name T75
Test name
Test status
Simulation time 51965333 ps
CPU time 0.6 seconds
Started Jun 22 04:34:51 PM PDT 24
Finished Jun 22 04:34:52 PM PDT 24
Peak memory 182584 kb
Host smart-d4881281-0d4b-4bf4-b119-16a6ab01d00e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269693150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1269693150
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2462583482
Short name T453
Test name
Test status
Simulation time 49405150 ps
CPU time 0.62 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 193296 kb
Host smart-e85e45a6-e246-4aa5-85bb-928ee17f99f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462583482 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2462583482
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.535832071
Short name T462
Test name
Test status
Simulation time 51529136 ps
CPU time 0.53 seconds
Started Jun 22 04:34:58 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 182352 kb
Host smart-431fcdc9-0e72-4c6e-b5da-b5fb1c5c9781
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535832071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.535832071
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.464476032
Short name T502
Test name
Test status
Simulation time 83308964 ps
CPU time 0.6 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 182464 kb
Host smart-97a6b099-b635-4a78-bdf3-4e453d9b8264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464476032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.464476032
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3331120252
Short name T84
Test name
Test status
Simulation time 283298317 ps
CPU time 0.74 seconds
Started Jun 22 04:34:58 PM PDT 24
Finished Jun 22 04:35:00 PM PDT 24
Peak memory 193260 kb
Host smart-41d4d810-a438-42f5-a8ec-5d77e27a7c67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331120252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3331120252
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3498505233
Short name T476
Test name
Test status
Simulation time 515621316 ps
CPU time 2.32 seconds
Started Jun 22 04:34:48 PM PDT 24
Finished Jun 22 04:34:51 PM PDT 24
Peak memory 197468 kb
Host smart-5eae2aaf-aabb-4ef5-8ecb-c0fcde270a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498505233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3498505233
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3633927072
Short name T555
Test name
Test status
Simulation time 106321912 ps
CPU time 1.35 seconds
Started Jun 22 04:34:56 PM PDT 24
Finished Jun 22 04:34:58 PM PDT 24
Peak memory 183128 kb
Host smart-bca07363-97e6-41e2-b52e-74747f5c43fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633927072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3633927072
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2978073519
Short name T542
Test name
Test status
Simulation time 42249511 ps
CPU time 0.55 seconds
Started Jun 22 04:35:07 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 182448 kb
Host smart-fbed9bd1-d4bd-4773-8df7-e2c01e9d554c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978073519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2978073519
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1886419821
Short name T519
Test name
Test status
Simulation time 19333194 ps
CPU time 0.54 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:03 PM PDT 24
Peak memory 182460 kb
Host smart-ce647a1d-c5f4-4998-8b21-4cdecb16f14b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886419821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1886419821
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.684271726
Short name T491
Test name
Test status
Simulation time 39617005 ps
CPU time 0.55 seconds
Started Jun 22 04:35:13 PM PDT 24
Finished Jun 22 04:35:14 PM PDT 24
Peak memory 182356 kb
Host smart-2cdb5199-9e38-4be8-8638-9bbc97eef638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684271726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.684271726
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3978144508
Short name T498
Test name
Test status
Simulation time 11955623 ps
CPU time 0.55 seconds
Started Jun 22 04:35:20 PM PDT 24
Finished Jun 22 04:35:20 PM PDT 24
Peak memory 181952 kb
Host smart-28356257-e1c6-4476-bd38-094ba6a10f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978144508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3978144508
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2859535961
Short name T518
Test name
Test status
Simulation time 126826581 ps
CPU time 0.53 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 182460 kb
Host smart-6df2fb95-2355-48f6-b219-740663c06f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859535961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2859535961
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2541784605
Short name T501
Test name
Test status
Simulation time 13763484 ps
CPU time 0.52 seconds
Started Jun 22 04:35:09 PM PDT 24
Finished Jun 22 04:35:12 PM PDT 24
Peak memory 181860 kb
Host smart-75209530-44cb-41e3-86ea-118822ac94ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541784605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2541784605
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1990134933
Short name T468
Test name
Test status
Simulation time 13335678 ps
CPU time 0.55 seconds
Started Jun 22 04:35:09 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 182136 kb
Host smart-0eaedf4f-2639-4afa-8b6a-b2e3c4c8fe65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990134933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1990134933
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3479690756
Short name T539
Test name
Test status
Simulation time 30470440 ps
CPU time 0.5 seconds
Started Jun 22 04:35:07 PM PDT 24
Finished Jun 22 04:35:19 PM PDT 24
Peak memory 181856 kb
Host smart-60e09ed7-e2d5-4218-8444-e9bd033d57a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479690756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3479690756
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3945478271
Short name T492
Test name
Test status
Simulation time 38385238 ps
CPU time 0.53 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:07 PM PDT 24
Peak memory 182476 kb
Host smart-7a650742-8aba-449f-a152-a66fa7869a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945478271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3945478271
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1420400136
Short name T543
Test name
Test status
Simulation time 13278313 ps
CPU time 0.53 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 182532 kb
Host smart-30a2ff93-9c74-4177-a98d-e10b2a06d2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420400136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1420400136
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2060480303
Short name T83
Test name
Test status
Simulation time 19064277 ps
CPU time 0.85 seconds
Started Jun 22 04:34:54 PM PDT 24
Finished Jun 22 04:34:56 PM PDT 24
Peak memory 182588 kb
Host smart-886e53a9-6d4a-4874-a678-8096fb780bcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060480303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2060480303
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.370426263
Short name T571
Test name
Test status
Simulation time 777404177 ps
CPU time 2.34 seconds
Started Jun 22 04:34:59 PM PDT 24
Finished Jun 22 04:35:04 PM PDT 24
Peak memory 191996 kb
Host smart-4e300273-6991-4785-bd15-2510fa267c03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370426263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.370426263
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1323335150
Short name T52
Test name
Test status
Simulation time 26856313 ps
CPU time 0.57 seconds
Started Jun 22 04:35:03 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 182548 kb
Host smart-34ec0f6f-8422-47f9-a0e6-695e1da63454
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323335150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1323335150
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.557192549
Short name T482
Test name
Test status
Simulation time 109738668 ps
CPU time 1.36 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 197444 kb
Host smart-34f3a9fd-35a0-4479-a729-7101d49377eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557192549 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.557192549
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2718579275
Short name T80
Test name
Test status
Simulation time 15269643 ps
CPU time 0.57 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 182584 kb
Host smart-3f241a56-3906-48bd-9136-b437d8cd104c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718579275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2718579275
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3766264128
Short name T497
Test name
Test status
Simulation time 41714003 ps
CPU time 0.6 seconds
Started Jun 22 04:34:53 PM PDT 24
Finished Jun 22 04:34:54 PM PDT 24
Peak memory 182456 kb
Host smart-a4087e78-5e2a-46aa-9ca7-797650dcfcc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766264128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3766264128
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.252426617
Short name T556
Test name
Test status
Simulation time 18926480 ps
CPU time 0.75 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 191540 kb
Host smart-c71c855e-05b5-4853-ae67-bad906467b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252426617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.252426617
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.975511827
Short name T504
Test name
Test status
Simulation time 41501161 ps
CPU time 1.1 seconds
Started Jun 22 04:34:59 PM PDT 24
Finished Jun 22 04:35:01 PM PDT 24
Peak memory 197208 kb
Host smart-b8e97fff-f27f-4a14-89e0-e785ca36fe85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975511827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.975511827
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.363675290
Short name T522
Test name
Test status
Simulation time 296168975 ps
CPU time 0.82 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 193660 kb
Host smart-52569bf1-f3f6-4038-9918-dbeab5ee2510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363675290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.363675290
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1183643294
Short name T484
Test name
Test status
Simulation time 90581133 ps
CPU time 0.55 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 182504 kb
Host smart-2705d4b8-73b7-4649-94de-7ddcd36dbb84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183643294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1183643294
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.140653608
Short name T513
Test name
Test status
Simulation time 17381614 ps
CPU time 0.53 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:08 PM PDT 24
Peak memory 181972 kb
Host smart-89061b34-da97-4fda-ad16-991420042b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140653608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.140653608
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2213298025
Short name T550
Test name
Test status
Simulation time 26538443 ps
CPU time 0.56 seconds
Started Jun 22 04:35:19 PM PDT 24
Finished Jun 22 04:35:20 PM PDT 24
Peak memory 182560 kb
Host smart-5e80c7fa-0dbd-4754-950e-c2cf06bd7c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213298025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2213298025
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.26766825
Short name T548
Test name
Test status
Simulation time 42275036 ps
CPU time 0.58 seconds
Started Jun 22 04:35:25 PM PDT 24
Finished Jun 22 04:35:26 PM PDT 24
Peak memory 182728 kb
Host smart-c006fb43-acc1-45e5-b0cb-b85549cf192b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26766825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.26766825
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3340647330
Short name T561
Test name
Test status
Simulation time 31375495 ps
CPU time 0.56 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:06 PM PDT 24
Peak memory 182428 kb
Host smart-b1abdb83-579a-4a2d-a052-7120689a6a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340647330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3340647330
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.480258291
Short name T496
Test name
Test status
Simulation time 11551981 ps
CPU time 0.55 seconds
Started Jun 22 04:35:00 PM PDT 24
Finished Jun 22 04:35:02 PM PDT 24
Peak memory 182440 kb
Host smart-75ddc5df-448c-471e-a5c7-0463e3ef0fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480258291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.480258291
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2217082027
Short name T455
Test name
Test status
Simulation time 49523933 ps
CPU time 0.55 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:09 PM PDT 24
Peak memory 182124 kb
Host smart-b0fe73d8-2560-4268-bebb-5124176ac847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217082027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2217082027
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2902685965
Short name T533
Test name
Test status
Simulation time 32498976 ps
CPU time 0.53 seconds
Started Jun 22 04:35:04 PM PDT 24
Finished Jun 22 04:35:07 PM PDT 24
Peak memory 182440 kb
Host smart-6a164d64-3e57-4b54-9002-e9c97c782f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902685965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2902685965
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4009550510
Short name T540
Test name
Test status
Simulation time 19377579 ps
CPU time 0.53 seconds
Started Jun 22 04:35:12 PM PDT 24
Finished Jun 22 04:35:13 PM PDT 24
Peak memory 182120 kb
Host smart-2711abbe-4309-4f4f-88ca-cdb002a14664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009550510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4009550510
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2137615224
Short name T574
Test name
Test status
Simulation time 55190998 ps
CPU time 0.53 seconds
Started Jun 22 04:35:11 PM PDT 24
Finished Jun 22 04:35:13 PM PDT 24
Peak memory 182440 kb
Host smart-a0d889cd-8186-43bb-b852-f69b039855f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137615224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2137615224
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3809062681
Short name T51
Test name
Test status
Simulation time 323826148 ps
CPU time 0.82 seconds
Started Jun 22 04:35:03 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 196804 kb
Host smart-432d5751-22f0-4606-8f7b-67d436919506
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809062681 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3809062681
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2281848294
Short name T77
Test name
Test status
Simulation time 40312258 ps
CPU time 0.59 seconds
Started Jun 22 04:34:59 PM PDT 24
Finished Jun 22 04:35:04 PM PDT 24
Peak memory 182892 kb
Host smart-e59052f1-afe0-4e00-bb12-2992cc60962e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281848294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2281848294
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.146799097
Short name T486
Test name
Test status
Simulation time 12758093 ps
CPU time 0.52 seconds
Started Jun 22 04:34:59 PM PDT 24
Finished Jun 22 04:35:01 PM PDT 24
Peak memory 182512 kb
Host smart-d5e4fb54-cf1f-4a46-a1ba-58f6ed5d1f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146799097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.146799097
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3979653250
Short name T33
Test name
Test status
Simulation time 25854863 ps
CPU time 0.67 seconds
Started Jun 22 04:35:08 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 192996 kb
Host smart-4a3035ed-3027-4ec7-be16-d3ec3b9e3ed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979653250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3979653250
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2391251819
Short name T472
Test name
Test status
Simulation time 152529205 ps
CPU time 2.51 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:12 PM PDT 24
Peak memory 197408 kb
Host smart-56df509f-9ef8-4afd-bfdc-2df6342cac81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391251819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2391251819
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3967333541
Short name T93
Test name
Test status
Simulation time 219916811 ps
CPU time 0.83 seconds
Started Jun 22 04:34:56 PM PDT 24
Finished Jun 22 04:34:58 PM PDT 24
Peak memory 193412 kb
Host smart-6c1950ed-b9a7-4c99-9d0c-bcb743845c87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967333541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3967333541
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1285474126
Short name T549
Test name
Test status
Simulation time 36194014 ps
CPU time 0.73 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 194580 kb
Host smart-b361bde4-1e44-40ef-8785-29bd583c96c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285474126 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1285474126
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.174523224
Short name T506
Test name
Test status
Simulation time 14508150 ps
CPU time 0.53 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:03 PM PDT 24
Peak memory 182500 kb
Host smart-389455e3-a731-4b8a-aed7-8e4fc8f99199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174523224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.174523224
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3030923519
Short name T456
Test name
Test status
Simulation time 17166088 ps
CPU time 0.58 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 182504 kb
Host smart-79fa35a7-174c-4ac0-8c16-d4ca68f5c065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030923519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3030923519
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2798301184
Short name T565
Test name
Test status
Simulation time 132141743 ps
CPU time 0.76 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:10 PM PDT 24
Peak memory 193188 kb
Host smart-d834e634-6eb2-4e1c-a01e-d8706a8b1498
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798301184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2798301184
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3167911110
Short name T452
Test name
Test status
Simulation time 322339437 ps
CPU time 2.86 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 197428 kb
Host smart-ddbe92b0-949a-4ffd-9b00-dbcf56bbaca1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167911110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3167911110
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1541003418
Short name T94
Test name
Test status
Simulation time 598486245 ps
CPU time 1.37 seconds
Started Jun 22 04:35:06 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 195308 kb
Host smart-7497c531-1ce9-4fd0-8644-455591c875bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541003418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1541003418
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1361868289
Short name T529
Test name
Test status
Simulation time 73403181 ps
CPU time 1.06 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 197520 kb
Host smart-6758deab-2312-45d3-b2c4-fc6173ccc73b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361868289 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1361868289
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4203722603
Short name T72
Test name
Test status
Simulation time 17218077 ps
CPU time 0.57 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 182592 kb
Host smart-91543844-1ee7-444d-9f34-025800334863
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203722603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.4203722603
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3403171180
Short name T475
Test name
Test status
Simulation time 30267777 ps
CPU time 0.51 seconds
Started Jun 22 04:35:02 PM PDT 24
Finished Jun 22 04:35:04 PM PDT 24
Peak memory 182408 kb
Host smart-d4e93ff2-3518-4270-9e37-4719f08cdc85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403171180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3403171180
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1420290951
Short name T85
Test name
Test status
Simulation time 49602516 ps
CPU time 0.67 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 191636 kb
Host smart-8a506587-c84a-452c-9649-f273565e75b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420290951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1420290951
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2979755203
Short name T461
Test name
Test status
Simulation time 143015917 ps
CPU time 1.9 seconds
Started Jun 22 04:34:57 PM PDT 24
Finished Jun 22 04:35:00 PM PDT 24
Peak memory 197784 kb
Host smart-960874c5-b511-4a32-84c3-4414aae1f7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979755203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2979755203
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2642486894
Short name T527
Test name
Test status
Simulation time 371160929 ps
CPU time 1.1 seconds
Started Jun 22 04:34:50 PM PDT 24
Finished Jun 22 04:34:52 PM PDT 24
Peak memory 194600 kb
Host smart-ba8d3a81-48ff-4840-ba73-5a0b1de4ba6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642486894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2642486894
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3774558666
Short name T544
Test name
Test status
Simulation time 52968917 ps
CPU time 0.65 seconds
Started Jun 22 04:34:58 PM PDT 24
Finished Jun 22 04:35:04 PM PDT 24
Peak memory 194300 kb
Host smart-c110f1d9-e89c-4d48-b00a-767a92229cbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774558666 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3774558666
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3673651602
Short name T79
Test name
Test status
Simulation time 31891695 ps
CPU time 0.57 seconds
Started Jun 22 04:34:58 PM PDT 24
Finished Jun 22 04:35:00 PM PDT 24
Peak memory 182588 kb
Host smart-baf1ae61-4cd9-4612-83dd-c3a0ac08f854
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673651602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3673651602
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.191071047
Short name T490
Test name
Test status
Simulation time 31936661 ps
CPU time 0.53 seconds
Started Jun 22 04:34:58 PM PDT 24
Finished Jun 22 04:34:59 PM PDT 24
Peak memory 182252 kb
Host smart-e6910d2c-d33d-48f3-991c-946786d44973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191071047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.191071047
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.945466174
Short name T86
Test name
Test status
Simulation time 34648576 ps
CPU time 0.62 seconds
Started Jun 22 04:35:00 PM PDT 24
Finished Jun 22 04:35:02 PM PDT 24
Peak memory 191872 kb
Host smart-67e16c11-6253-49ae-a6e3-7f74c7f4f315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945466174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.945466174
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.323953918
Short name T564
Test name
Test status
Simulation time 514176526 ps
CPU time 2.37 seconds
Started Jun 22 04:35:01 PM PDT 24
Finished Jun 22 04:35:05 PM PDT 24
Peak memory 197432 kb
Host smart-abfe4ebe-f152-4191-ad46-3f9041000277
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323953918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.323953918
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.685542676
Short name T526
Test name
Test status
Simulation time 212569134 ps
CPU time 1.22 seconds
Started Jun 22 04:34:55 PM PDT 24
Finished Jun 22 04:34:57 PM PDT 24
Peak memory 194380 kb
Host smart-9a325ef0-dab7-4493-b7a1-8d9c7cc14805
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685542676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.685542676
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3439849130
Short name T515
Test name
Test status
Simulation time 45209734 ps
CPU time 0.92 seconds
Started Jun 22 04:34:54 PM PDT 24
Finished Jun 22 04:34:56 PM PDT 24
Peak memory 197036 kb
Host smart-2510fe81-e261-4146-aa93-4c6a3c4b6d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439849130 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3439849130
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3110504462
Short name T510
Test name
Test status
Simulation time 14717486 ps
CPU time 0.53 seconds
Started Jun 22 04:35:09 PM PDT 24
Finished Jun 22 04:35:11 PM PDT 24
Peak memory 182404 kb
Host smart-4cb5e673-d89b-423c-afd4-c15be302ea2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110504462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3110504462
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3180531372
Short name T523
Test name
Test status
Simulation time 41639242 ps
CPU time 0.54 seconds
Started Jun 22 04:34:51 PM PDT 24
Finished Jun 22 04:34:52 PM PDT 24
Peak memory 182460 kb
Host smart-b343a57c-02b5-4ab2-b362-b63c63686611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180531372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3180531372
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2088469381
Short name T567
Test name
Test status
Simulation time 27402898 ps
CPU time 0.59 seconds
Started Jun 22 04:35:05 PM PDT 24
Finished Jun 22 04:35:12 PM PDT 24
Peak memory 191236 kb
Host smart-03e1e420-f346-495a-b4b0-f755ac6ea172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088469381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2088469381
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3996126880
Short name T485
Test name
Test status
Simulation time 116041203 ps
CPU time 0.85 seconds
Started Jun 22 04:34:56 PM PDT 24
Finished Jun 22 04:34:58 PM PDT 24
Peak memory 190616 kb
Host smart-7e891530-df4b-4288-9d09-c0b573b4b447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996126880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3996126880
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3597791963
Short name T95
Test name
Test status
Simulation time 124262034 ps
CPU time 1.35 seconds
Started Jun 22 04:34:55 PM PDT 24
Finished Jun 22 04:34:57 PM PDT 24
Peak memory 195516 kb
Host smart-c44401e0-9955-418e-a700-14b48f534140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597791963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3597791963
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3720316195
Short name T379
Test name
Test status
Simulation time 81526513863 ps
CPU time 33.37 seconds
Started Jun 22 04:41:04 PM PDT 24
Finished Jun 22 04:41:38 PM PDT 24
Peak memory 182864 kb
Host smart-897e3e2f-5899-4eaf-8dfa-35021fe9a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720316195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3720316195
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.760460146
Short name T161
Test name
Test status
Simulation time 239866106475 ps
CPU time 110.61 seconds
Started Jun 22 04:41:14 PM PDT 24
Finished Jun 22 04:43:06 PM PDT 24
Peak memory 195244 kb
Host smart-4a425518-a6ad-4d6a-ad65-ab83bc0ee606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760460146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.760460146
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.1266317527
Short name T36
Test name
Test status
Simulation time 41598662318 ps
CPU time 329.72 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:46:52 PM PDT 24
Peak memory 197664 kb
Host smart-0714b94a-e268-4873-babc-d2707e188e7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266317527 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.1266317527
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1424360978
Short name T110
Test name
Test status
Simulation time 37331209560 ps
CPU time 19.47 seconds
Started Jun 22 04:41:17 PM PDT 24
Finished Jun 22 04:41:40 PM PDT 24
Peak memory 182884 kb
Host smart-54fcd461-9ddc-41e1-b3bd-6706bf02099d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424360978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1424360978
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.152137548
Short name T414
Test name
Test status
Simulation time 939427617819 ps
CPU time 147.57 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:43:46 PM PDT 24
Peak memory 182876 kb
Host smart-07b7670a-5217-428c-b3f1-27aafdb9bc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152137548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.152137548
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1232744178
Short name T249
Test name
Test status
Simulation time 31208385388 ps
CPU time 32.11 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:41:48 PM PDT 24
Peak memory 194356 kb
Host smart-8b86c299-c31f-4346-810b-bddacd6efa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232744178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1232744178
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.877739086
Short name T16
Test name
Test status
Simulation time 331821481 ps
CPU time 0.79 seconds
Started Jun 22 04:41:17 PM PDT 24
Finished Jun 22 04:41:22 PM PDT 24
Peak memory 213060 kb
Host smart-b0d68559-5e93-4259-af82-3b46e1436c81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877739086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.877739086
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.4180218841
Short name T263
Test name
Test status
Simulation time 165644740417 ps
CPU time 136.07 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:43:34 PM PDT 24
Peak memory 182876 kb
Host smart-18a4defc-f50e-44e6-8358-dcd2acb410a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180218841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.4180218841
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3417101710
Short name T372
Test name
Test status
Simulation time 196094610638 ps
CPU time 83 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:42:39 PM PDT 24
Peak memory 183004 kb
Host smart-368b8035-8a55-4a82-abea-8a9f42bb93d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417101710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3417101710
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2681104850
Short name T366
Test name
Test status
Simulation time 180521261 ps
CPU time 0.68 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:41:19 PM PDT 24
Peak memory 182628 kb
Host smart-c9c522c1-dbef-4d40-9849-6443d96b3f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681104850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2681104850
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.99186534
Short name T41
Test name
Test status
Simulation time 41779879680 ps
CPU time 326.79 seconds
Started Jun 22 04:41:19 PM PDT 24
Finished Jun 22 04:46:49 PM PDT 24
Peak memory 206172 kb
Host smart-3cb97153-a2f8-4d74-9263-c3a4395ac496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99186534 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.99186534
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.rv_timer_random.3482401475
Short name T334
Test name
Test status
Simulation time 5593114097 ps
CPU time 210.62 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:45:37 PM PDT 24
Peak memory 182880 kb
Host smart-0dd9a9e5-e5a3-4425-9f7a-09068d8c83d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482401475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3482401475
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1442493283
Short name T186
Test name
Test status
Simulation time 613626414738 ps
CPU time 250.23 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:46:15 PM PDT 24
Peak memory 191128 kb
Host smart-94ce33ca-1d17-4f9a-9e86-36e5a33cb643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442493283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1442493283
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1547263799
Short name T197
Test name
Test status
Simulation time 180616551859 ps
CPU time 498 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:50:21 PM PDT 24
Peak memory 191092 kb
Host smart-21f4c4bf-6210-417f-a0c7-d35b4a26d341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547263799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1547263799
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2371980645
Short name T148
Test name
Test status
Simulation time 45147653369 ps
CPU time 90.26 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:43:33 PM PDT 24
Peak memory 191188 kb
Host smart-1fc0cd1f-a32d-492f-be68-3d408b173b00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371980645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2371980645
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2281711568
Short name T47
Test name
Test status
Simulation time 46249374781 ps
CPU time 40.69 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:42:44 PM PDT 24
Peak memory 191424 kb
Host smart-a3ab5a83-22b7-42e3-af42-a5f37c52a055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281711568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2281711568
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3031954028
Short name T317
Test name
Test status
Simulation time 84123750507 ps
CPU time 135.83 seconds
Started Jun 22 04:41:20 PM PDT 24
Finished Jun 22 04:43:41 PM PDT 24
Peak memory 182880 kb
Host smart-f9fe4229-6f1a-42e8-99bb-cfc9b33e8721
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031954028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3031954028
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random.2132854152
Short name T44
Test name
Test status
Simulation time 230136128813 ps
CPU time 583.3 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:51:01 PM PDT 24
Peak memory 191156 kb
Host smart-4aa65902-a6e8-41ad-8c58-feb80f7f1fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132854152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2132854152
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1313417273
Short name T440
Test name
Test status
Simulation time 93223453 ps
CPU time 2.13 seconds
Started Jun 22 04:41:17 PM PDT 24
Finished Jun 22 04:41:23 PM PDT 24
Peak memory 182828 kb
Host smart-ff253391-de24-47fd-af70-e855cd805daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313417273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1313417273
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3574227122
Short name T403
Test name
Test status
Simulation time 1149893254934 ps
CPU time 763.36 seconds
Started Jun 22 04:41:13 PM PDT 24
Finished Jun 22 04:53:57 PM PDT 24
Peak memory 191188 kb
Host smart-0cf1be1b-579e-4e96-86c9-a5325c422c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574227122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3574227122
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.3304135854
Short name T337
Test name
Test status
Simulation time 251847871221 ps
CPU time 195 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:45:20 PM PDT 24
Peak memory 191168 kb
Host smart-4c6f402e-b37e-486c-849a-0af90186c87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304135854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3304135854
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2221163831
Short name T151
Test name
Test status
Simulation time 480491057884 ps
CPU time 335.64 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:47:43 PM PDT 24
Peak memory 192844 kb
Host smart-27664f2b-b1b9-43ef-a706-82dea9d38357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221163831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2221163831
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2142441819
Short name T137
Test name
Test status
Simulation time 1152303670846 ps
CPU time 1613.83 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 05:09:00 PM PDT 24
Peak memory 191176 kb
Host smart-e3afb5f5-de4d-4fa4-86b1-8521090eeb35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142441819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2142441819
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1310612610
Short name T112
Test name
Test status
Simulation time 164421011651 ps
CPU time 206.71 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:45:33 PM PDT 24
Peak memory 191176 kb
Host smart-f63aed92-b565-4b22-8d1a-9092cad32799
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310612610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1310612610
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3826880470
Short name T68
Test name
Test status
Simulation time 24891226461 ps
CPU time 9.37 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:42:14 PM PDT 24
Peak memory 182740 kb
Host smart-e02fe0ad-745d-493d-a3b5-7ef501d953b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826880470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3826880470
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1363825670
Short name T187
Test name
Test status
Simulation time 238377633631 ps
CPU time 361.42 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:47:19 PM PDT 24
Peak memory 182852 kb
Host smart-fecd2f3c-fc41-460a-9172-dbb1a3e410ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363825670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1363825670
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1779711608
Short name T416
Test name
Test status
Simulation time 8476784513 ps
CPU time 11.98 seconds
Started Jun 22 04:41:19 PM PDT 24
Finished Jun 22 04:41:34 PM PDT 24
Peak memory 182996 kb
Host smart-82f4f703-f385-4e3d-8f41-9611e80c348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779711608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1779711608
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4190033230
Short name T348
Test name
Test status
Simulation time 170452777552 ps
CPU time 80.84 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:42:39 PM PDT 24
Peak memory 182972 kb
Host smart-a329606e-12f9-4e58-b310-a68af3b8af16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190033230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4190033230
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2700295128
Short name T398
Test name
Test status
Simulation time 497062130 ps
CPU time 0.69 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:41:18 PM PDT 24
Peak memory 182756 kb
Host smart-0f5d056d-1d79-4e52-b2d3-8063ffafa5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700295128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2700295128
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.1536548277
Short name T42
Test name
Test status
Simulation time 89751137721 ps
CPU time 692.12 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:53:38 PM PDT 24
Peak memory 191188 kb
Host smart-37237fa0-7874-491c-ae86-8a95ff48b5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536548277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1536548277
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.391853962
Short name T315
Test name
Test status
Simulation time 237496766508 ps
CPU time 95.37 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:43:42 PM PDT 24
Peak memory 191184 kb
Host smart-18f1b360-cb65-4830-8589-975ec6055745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391853962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.391853962
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.4067017095
Short name T301
Test name
Test status
Simulation time 112962401462 ps
CPU time 237.43 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:46:02 PM PDT 24
Peak memory 191120 kb
Host smart-41eb647c-d187-4db5-b484-142a9d368bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067017095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4067017095
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2271306042
Short name T321
Test name
Test status
Simulation time 87389105854 ps
CPU time 290.69 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:46:56 PM PDT 24
Peak memory 191088 kb
Host smart-4bca18b4-0abf-4e15-83b8-b0de3f3f6b9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271306042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2271306042
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3238326510
Short name T242
Test name
Test status
Simulation time 2627486138001 ps
CPU time 948.37 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:57:54 PM PDT 24
Peak memory 191184 kb
Host smart-8230e02e-c193-42dc-8bd0-c93107aaa923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238326510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3238326510
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1287051731
Short name T118
Test name
Test status
Simulation time 214626327509 ps
CPU time 184.32 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:45:09 PM PDT 24
Peak memory 191188 kb
Host smart-be4c57c6-30ec-4a02-a42f-6a39b460654d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287051731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1287051731
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.425924104
Short name T102
Test name
Test status
Simulation time 156512434014 ps
CPU time 90.09 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:43:37 PM PDT 24
Peak memory 182984 kb
Host smart-768aa35c-eadf-4217-a4c7-40dab9e80c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425924104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.425924104
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.549370761
Short name T21
Test name
Test status
Simulation time 49790994110 ps
CPU time 514.79 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:50:37 PM PDT 24
Peak memory 191184 kb
Host smart-e0274821-690e-4401-a9a3-aecdc7e74456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549370761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.549370761
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2622463201
Short name T437
Test name
Test status
Simulation time 184254873256 ps
CPU time 320.12 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:46:38 PM PDT 24
Peak memory 183028 kb
Host smart-39032816-a195-42eb-9733-847645aa5bf9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622463201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2622463201
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2313135821
Short name T448
Test name
Test status
Simulation time 279811675451 ps
CPU time 53.02 seconds
Started Jun 22 04:41:14 PM PDT 24
Finished Jun 22 04:42:09 PM PDT 24
Peak memory 182820 kb
Host smart-98c51a21-23f6-4d9c-ad27-1b3577a3ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313135821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2313135821
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.109603977
Short name T157
Test name
Test status
Simulation time 172559053121 ps
CPU time 477.85 seconds
Started Jun 22 04:41:12 PM PDT 24
Finished Jun 22 04:49:11 PM PDT 24
Peak memory 191188 kb
Host smart-6b1a0415-7254-4101-aaa5-31683ef8d13a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109603977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.109603977
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3892886525
Short name T439
Test name
Test status
Simulation time 42848131276 ps
CPU time 403.22 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:48:00 PM PDT 24
Peak memory 182920 kb
Host smart-a3ab5164-3e9f-4a1b-b45d-19113edf507e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892886525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3892886525
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3637671900
Short name T173
Test name
Test status
Simulation time 1263567845151 ps
CPU time 390.43 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:48:36 PM PDT 24
Peak memory 191180 kb
Host smart-07ab39b4-fe2f-4048-94b9-5296b3e89c61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637671900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3637671900
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.530499818
Short name T302
Test name
Test status
Simulation time 501366558942 ps
CPU time 613.58 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:52:19 PM PDT 24
Peak memory 191188 kb
Host smart-8c14f676-b081-4bcf-bba6-0e9decf18771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530499818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.530499818
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4005778918
Short name T5
Test name
Test status
Simulation time 17584822798 ps
CPU time 72.09 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:43:19 PM PDT 24
Peak memory 191184 kb
Host smart-814b7a71-3c3c-400e-9035-e694685ac159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005778918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4005778918
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.43282351
Short name T330
Test name
Test status
Simulation time 270406920760 ps
CPU time 134.67 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 191176 kb
Host smart-4fd0afc5-0510-40c7-9023-411e782f464e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43282351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.43282351
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3573223518
Short name T322
Test name
Test status
Simulation time 326802787929 ps
CPU time 446.93 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:48:48 PM PDT 24
Peak memory 182980 kb
Host smart-6d3cbe52-bae0-4367-b822-536af8272249
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573223518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3573223518
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.4221305722
Short name T24
Test name
Test status
Simulation time 8257812558 ps
CPU time 6.52 seconds
Started Jun 22 04:41:17 PM PDT 24
Finished Jun 22 04:41:27 PM PDT 24
Peak memory 182904 kb
Host smart-3e88070e-19d9-441b-8a98-d484ae098f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221305722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4221305722
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3736588216
Short name T116
Test name
Test status
Simulation time 172736425458 ps
CPU time 155.09 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:43:57 PM PDT 24
Peak memory 191092 kb
Host smart-7dfa893b-bce1-44ce-8558-d5634ec81b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736588216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3736588216
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.459674223
Short name T341
Test name
Test status
Simulation time 54045947155 ps
CPU time 71.14 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:42:33 PM PDT 24
Peak memory 182976 kb
Host smart-4dd779ba-0024-4141-aa27-ded3354b6208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459674223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.459674223
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2992960659
Short name T391
Test name
Test status
Simulation time 2237948474111 ps
CPU time 301.63 seconds
Started Jun 22 04:41:17 PM PDT 24
Finished Jun 22 04:46:22 PM PDT 24
Peak memory 182960 kb
Host smart-b87f2576-1ebe-45a6-9af0-9dbb0081cb97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992960659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2992960659
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.2352936808
Short name T332
Test name
Test status
Simulation time 13290104927 ps
CPU time 21.77 seconds
Started Jun 22 04:42:08 PM PDT 24
Finished Jun 22 04:42:31 PM PDT 24
Peak memory 191104 kb
Host smart-6e90f571-5823-464b-8c7c-68d1a5e1b3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352936808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2352936808
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.346790756
Short name T238
Test name
Test status
Simulation time 640854198509 ps
CPU time 473.44 seconds
Started Jun 22 04:42:09 PM PDT 24
Finished Jun 22 04:50:03 PM PDT 24
Peak memory 191088 kb
Host smart-3c8113ab-d027-485c-b320-b414c05d22ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346790756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.346790756
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.834411275
Short name T306
Test name
Test status
Simulation time 381700558866 ps
CPU time 134.95 seconds
Started Jun 22 04:42:12 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 182988 kb
Host smart-833e65a4-594d-4f76-9c3d-a3f89e35014a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834411275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.834411275
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1490630134
Short name T421
Test name
Test status
Simulation time 225435329865 ps
CPU time 110.28 seconds
Started Jun 22 04:42:12 PM PDT 24
Finished Jun 22 04:44:03 PM PDT 24
Peak memory 191060 kb
Host smart-72bf52c8-be83-4b3c-aa59-e7460cc93af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490630134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1490630134
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3483350379
Short name T333
Test name
Test status
Simulation time 141526533137 ps
CPU time 218.79 seconds
Started Jun 22 04:42:17 PM PDT 24
Finished Jun 22 04:45:56 PM PDT 24
Peak memory 191084 kb
Host smart-e5134ae8-4f77-46fe-a521-f243e6c44990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483350379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3483350379
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3148752122
Short name T264
Test name
Test status
Simulation time 267769594677 ps
CPU time 210.07 seconds
Started Jun 22 04:42:09 PM PDT 24
Finished Jun 22 04:45:40 PM PDT 24
Peak memory 194756 kb
Host smart-9b84e2e8-dbca-4dfe-9fae-db4d5cdae104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148752122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3148752122
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1341404169
Short name T286
Test name
Test status
Simulation time 124634045210 ps
CPU time 174.49 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:44:13 PM PDT 24
Peak memory 182932 kb
Host smart-51b97036-0099-486f-bebf-82e121a0799b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341404169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1341404169
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.4139237781
Short name T363
Test name
Test status
Simulation time 921707191554 ps
CPU time 306.35 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:46:24 PM PDT 24
Peak memory 182916 kb
Host smart-a19b1a87-be7a-4ac4-8155-eed00d100c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139237781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.4139237781
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3058038473
Short name T351
Test name
Test status
Simulation time 109434220286 ps
CPU time 174.37 seconds
Started Jun 22 04:41:17 PM PDT 24
Finished Jun 22 04:44:15 PM PDT 24
Peak memory 191080 kb
Host smart-54f6ecad-7d07-4aed-a2bf-f875d57c9744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058038473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3058038473
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1951967983
Short name T276
Test name
Test status
Simulation time 17273012895 ps
CPU time 27.87 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:41:46 PM PDT 24
Peak memory 182908 kb
Host smart-06a704f7-d926-4bf5-b032-d1dca964aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951967983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1951967983
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/153.rv_timer_random.3978033345
Short name T56
Test name
Test status
Simulation time 205291381437 ps
CPU time 89.35 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:43:40 PM PDT 24
Peak memory 191088 kb
Host smart-53af040b-691b-4480-ac40-25daff80e449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978033345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3978033345
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3468937322
Short name T245
Test name
Test status
Simulation time 437435521066 ps
CPU time 263.6 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:46:34 PM PDT 24
Peak memory 191072 kb
Host smart-26d9714a-2b24-4b8c-946b-04fe31933ebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468937322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3468937322
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2426953885
Short name T436
Test name
Test status
Simulation time 142641311217 ps
CPU time 602.96 seconds
Started Jun 22 04:42:16 PM PDT 24
Finished Jun 22 04:52:20 PM PDT 24
Peak memory 182880 kb
Host smart-7dee509c-f639-408d-bda4-28f453cf564d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426953885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2426953885
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1517877109
Short name T259
Test name
Test status
Simulation time 16859804028 ps
CPU time 7.37 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:42:18 PM PDT 24
Peak memory 182980 kb
Host smart-1613eca8-1b9a-493f-b0e1-e89581735e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517877109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1517877109
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2903150052
Short name T336
Test name
Test status
Simulation time 112306009576 ps
CPU time 37.08 seconds
Started Jun 22 04:42:16 PM PDT 24
Finished Jun 22 04:42:54 PM PDT 24
Peak memory 182880 kb
Host smart-19d1ec89-6d2b-48ef-889b-b9b0619279b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903150052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2903150052
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3854272931
Short name T280
Test name
Test status
Simulation time 489203145513 ps
CPU time 658.7 seconds
Started Jun 22 04:41:28 PM PDT 24
Finished Jun 22 04:52:27 PM PDT 24
Peak memory 183192 kb
Host smart-2e9854cd-954d-48c9-bfaf-c0089d17e285
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854272931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3854272931
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1321336137
Short name T374
Test name
Test status
Simulation time 537935797531 ps
CPU time 183.04 seconds
Started Jun 22 04:41:26 PM PDT 24
Finished Jun 22 04:44:29 PM PDT 24
Peak memory 182948 kb
Host smart-53996753-5b9f-472c-933b-523620a15076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321336137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1321336137
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1023489374
Short name T344
Test name
Test status
Simulation time 31109490394 ps
CPU time 54.69 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 04:42:18 PM PDT 24
Peak memory 191128 kb
Host smart-be654cc5-946e-4f7c-9deb-a748b7491e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023489374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1023489374
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2282439997
Short name T309
Test name
Test status
Simulation time 672022891518 ps
CPU time 2525.2 seconds
Started Jun 22 04:41:19 PM PDT 24
Finished Jun 22 05:23:28 PM PDT 24
Peak memory 191080 kb
Host smart-bc4190d9-8073-4524-98e3-43ec29f3bee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282439997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2282439997
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1532302869
Short name T98
Test name
Test status
Simulation time 187320119550 ps
CPU time 428.06 seconds
Started Jun 22 04:42:08 PM PDT 24
Finished Jun 22 04:49:17 PM PDT 24
Peak memory 191184 kb
Host smart-bad0aab5-6606-4eba-b228-948d73d35321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532302869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1532302869
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.4292713615
Short name T111
Test name
Test status
Simulation time 141168843349 ps
CPU time 53.83 seconds
Started Jun 22 04:42:16 PM PDT 24
Finished Jun 22 04:43:11 PM PDT 24
Peak memory 182692 kb
Host smart-a6ddb587-84d6-470a-90a5-51a02b6d68cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292713615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4292713615
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.656324510
Short name T307
Test name
Test status
Simulation time 34124861975 ps
CPU time 151.24 seconds
Started Jun 22 04:42:09 PM PDT 24
Finished Jun 22 04:44:41 PM PDT 24
Peak memory 191100 kb
Host smart-2c098cea-4f4b-47ce-9a37-a858e3ee8c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656324510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.656324510
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2105933118
Short name T305
Test name
Test status
Simulation time 48072517909 ps
CPU time 64.79 seconds
Started Jun 22 04:42:17 PM PDT 24
Finished Jun 22 04:43:22 PM PDT 24
Peak memory 182684 kb
Host smart-882fb140-679b-4714-9bd9-288ebc76126c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105933118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2105933118
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1861100603
Short name T128
Test name
Test status
Simulation time 32549329487 ps
CPU time 54.7 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:43:06 PM PDT 24
Peak memory 191188 kb
Host smart-6b3eb925-de56-4bfa-b3f1-5a15bd8d6010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861100603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1861100603
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2186857108
Short name T271
Test name
Test status
Simulation time 60199120759 ps
CPU time 31.63 seconds
Started Jun 22 04:42:10 PM PDT 24
Finished Jun 22 04:42:42 PM PDT 24
Peak memory 182868 kb
Host smart-b14fdde7-e316-4d3d-ac90-fdff1eed8910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186857108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2186857108
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.237105162
Short name T216
Test name
Test status
Simulation time 118264329563 ps
CPU time 115.71 seconds
Started Jun 22 04:42:24 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 191060 kb
Host smart-b88bf4d9-3410-42f8-b8df-9fbd63557f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237105162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.237105162
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3735183365
Short name T335
Test name
Test status
Simulation time 326587716427 ps
CPU time 657.95 seconds
Started Jun 22 04:42:16 PM PDT 24
Finished Jun 22 04:53:15 PM PDT 24
Peak memory 191104 kb
Host smart-01a2ce05-8626-483e-82b2-29922d3d01a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735183365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3735183365
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3666051429
Short name T194
Test name
Test status
Simulation time 130900991189 ps
CPU time 187.94 seconds
Started Jun 22 04:41:34 PM PDT 24
Finished Jun 22 04:44:42 PM PDT 24
Peak memory 182872 kb
Host smart-8e5c25a0-83e8-4805-b2dd-191ea7e498f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666051429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3666051429
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1852225370
Short name T375
Test name
Test status
Simulation time 740364156609 ps
CPU time 298.11 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:46:22 PM PDT 24
Peak memory 182908 kb
Host smart-0401eee4-ade9-4932-b2f4-207665abe430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852225370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1852225370
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.810898469
Short name T282
Test name
Test status
Simulation time 60532371702 ps
CPU time 25.74 seconds
Started Jun 22 04:41:20 PM PDT 24
Finished Jun 22 04:41:49 PM PDT 24
Peak memory 182900 kb
Host smart-c1aa1b65-a4f3-429a-9d84-34eff470e010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810898469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.810898469
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3910045368
Short name T434
Test name
Test status
Simulation time 25464186993 ps
CPU time 48.6 seconds
Started Jun 22 04:41:34 PM PDT 24
Finished Jun 22 04:42:23 PM PDT 24
Peak memory 195256 kb
Host smart-efcbdf85-08c6-4ffa-99a3-c59fe0b61d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910045368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3910045368
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3688690362
Short name T427
Test name
Test status
Simulation time 324232383121 ps
CPU time 233.9 seconds
Started Jun 22 04:41:20 PM PDT 24
Finished Jun 22 04:45:17 PM PDT 24
Peak memory 182884 kb
Host smart-9f93866c-585a-439c-9fa9-a25a27216e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688690362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3688690362
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.1069370249
Short name T240
Test name
Test status
Simulation time 499267489916 ps
CPU time 545.06 seconds
Started Jun 22 04:42:18 PM PDT 24
Finished Jun 22 04:51:23 PM PDT 24
Peak memory 194644 kb
Host smart-a89c1f1c-8b42-4432-a1e2-5e441f1d8b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069370249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1069370249
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2797820368
Short name T433
Test name
Test status
Simulation time 39991720682 ps
CPU time 23.81 seconds
Started Jun 22 04:42:17 PM PDT 24
Finished Jun 22 04:42:41 PM PDT 24
Peak memory 182976 kb
Host smart-35b7c14c-e5c5-499a-83dc-49dee800e147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797820368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2797820368
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3688776664
Short name T192
Test name
Test status
Simulation time 263887981521 ps
CPU time 685.23 seconds
Started Jun 22 04:42:18 PM PDT 24
Finished Jun 22 04:53:44 PM PDT 24
Peak memory 191188 kb
Host smart-732fb4f7-e324-4e5d-8ab5-563edbb35746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688776664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3688776664
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3357829380
Short name T339
Test name
Test status
Simulation time 72427828927 ps
CPU time 724.58 seconds
Started Jun 22 04:42:18 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 191080 kb
Host smart-22971de0-58f4-426e-8f51-9f62c34aa4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357829380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3357829380
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3911270122
Short name T326
Test name
Test status
Simulation time 75260344053 ps
CPU time 685.23 seconds
Started Jun 22 04:42:25 PM PDT 24
Finished Jun 22 04:53:50 PM PDT 24
Peak memory 191060 kb
Host smart-1a9c037b-fed8-42a3-baed-998a80c55548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911270122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3911270122
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1435195614
Short name T425
Test name
Test status
Simulation time 248592295691 ps
CPU time 128.27 seconds
Started Jun 22 04:42:23 PM PDT 24
Finished Jun 22 04:44:32 PM PDT 24
Peak memory 191056 kb
Host smart-9aa745e9-2bc2-47d3-bf54-d98588ba76d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435195614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1435195614
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.883976998
Short name T347
Test name
Test status
Simulation time 118210837842 ps
CPU time 372.2 seconds
Started Jun 22 04:42:19 PM PDT 24
Finished Jun 22 04:48:32 PM PDT 24
Peak memory 191184 kb
Host smart-1741d0fa-a587-47fb-a681-efbaf0472fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883976998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.883976998
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3616038732
Short name T383
Test name
Test status
Simulation time 45646835473 ps
CPU time 65.51 seconds
Started Jun 22 04:42:20 PM PDT 24
Finished Jun 22 04:43:26 PM PDT 24
Peak memory 182820 kb
Host smart-9373784f-eaad-4e5e-bb7b-fd40fdf451f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616038732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3616038732
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2603416947
Short name T224
Test name
Test status
Simulation time 13110469883 ps
CPU time 10.79 seconds
Started Jun 22 04:41:20 PM PDT 24
Finished Jun 22 04:41:34 PM PDT 24
Peak memory 182892 kb
Host smart-70cc18f9-fa9e-4daa-9ad1-f752d51217b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603416947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2603416947
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.911223823
Short name T401
Test name
Test status
Simulation time 53898408350 ps
CPU time 70.3 seconds
Started Jun 22 04:41:25 PM PDT 24
Finished Jun 22 04:42:35 PM PDT 24
Peak memory 182896 kb
Host smart-42fa2daf-4948-4250-8f4d-9dc34851110d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911223823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.911223823
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.4017330149
Short name T316
Test name
Test status
Simulation time 46725270875 ps
CPU time 40.34 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 04:42:04 PM PDT 24
Peak memory 182752 kb
Host smart-88127475-24a0-44c3-a2de-57a6ca6a819b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017330149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4017330149
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2424630854
Short name T327
Test name
Test status
Simulation time 101085858055 ps
CPU time 730.24 seconds
Started Jun 22 04:41:20 PM PDT 24
Finished Jun 22 04:53:33 PM PDT 24
Peak memory 191200 kb
Host smart-d1e06d8c-0682-4e2e-b114-2fec61144445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424630854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2424630854
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.2509340716
Short name T132
Test name
Test status
Simulation time 34556928315 ps
CPU time 46.25 seconds
Started Jun 22 04:42:18 PM PDT 24
Finished Jun 22 04:43:04 PM PDT 24
Peak memory 182984 kb
Host smart-ceeac032-5534-4c95-95d6-ca72dd56dc7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509340716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2509340716
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3242398553
Short name T101
Test name
Test status
Simulation time 384561299851 ps
CPU time 1522.65 seconds
Started Jun 22 04:42:18 PM PDT 24
Finished Jun 22 05:07:41 PM PDT 24
Peak memory 191148 kb
Host smart-3900159f-1ec7-4083-9cb4-5268dd0ac935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242398553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3242398553
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3343515804
Short name T256
Test name
Test status
Simulation time 142434618321 ps
CPU time 403.31 seconds
Started Jun 22 04:42:19 PM PDT 24
Finished Jun 22 04:49:03 PM PDT 24
Peak memory 190704 kb
Host smart-7b677f0e-0dab-4dc4-986d-1c757248d204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343515804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3343515804
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1199664995
Short name T261
Test name
Test status
Simulation time 428076359519 ps
CPU time 162.48 seconds
Started Jun 22 04:42:16 PM PDT 24
Finished Jun 22 04:45:00 PM PDT 24
Peak memory 183224 kb
Host smart-1d8cad88-e0ca-49b2-852f-1d543b66d208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199664995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1199664995
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3088508106
Short name T167
Test name
Test status
Simulation time 75923156252 ps
CPU time 73.21 seconds
Started Jun 22 04:42:19 PM PDT 24
Finished Jun 22 04:43:33 PM PDT 24
Peak memory 190584 kb
Host smart-0c31f209-1ca8-47e1-8866-c43114b8fa0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088508106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3088508106
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.662898142
Short name T404
Test name
Test status
Simulation time 9730852337 ps
CPU time 16.3 seconds
Started Jun 22 04:42:26 PM PDT 24
Finished Jun 22 04:42:42 PM PDT 24
Peak memory 182884 kb
Host smart-fe7d4dc2-0512-40ae-804a-21c1dd760db7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662898142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.662898142
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2451693141
Short name T226
Test name
Test status
Simulation time 165401600228 ps
CPU time 339.99 seconds
Started Jun 22 04:42:26 PM PDT 24
Finished Jun 22 04:48:07 PM PDT 24
Peak memory 191180 kb
Host smart-43eedb39-c3ab-4e95-9044-32b48418c6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451693141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2451693141
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1764909013
Short name T241
Test name
Test status
Simulation time 925439089253 ps
CPU time 441.2 seconds
Started Jun 22 04:41:20 PM PDT 24
Finished Jun 22 04:48:44 PM PDT 24
Peak memory 182916 kb
Host smart-b01a9fdb-8089-4610-bac3-0bf8a6e54b7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764909013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1764909013
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3433387196
Short name T423
Test name
Test status
Simulation time 488175258728 ps
CPU time 194.83 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:44:39 PM PDT 24
Peak memory 182916 kb
Host smart-6613ad4e-2283-4507-b2df-47dc402f896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433387196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3433387196
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1086336970
Short name T417
Test name
Test status
Simulation time 236985952 ps
CPU time 0.63 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:41:25 PM PDT 24
Peak memory 182752 kb
Host smart-641f11e1-4741-4b99-9974-61ab6cc3b7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086336970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1086336970
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.837038573
Short name T213
Test name
Test status
Simulation time 209005255514 ps
CPU time 486.46 seconds
Started Jun 22 04:42:23 PM PDT 24
Finished Jun 22 04:50:29 PM PDT 24
Peak memory 191180 kb
Host smart-315f9489-16ff-434f-be25-2ff80f37fbc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837038573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.837038573
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1210599464
Short name T219
Test name
Test status
Simulation time 145716240184 ps
CPU time 252.42 seconds
Started Jun 22 04:42:24 PM PDT 24
Finished Jun 22 04:46:36 PM PDT 24
Peak memory 191188 kb
Host smart-ba3140e3-8d7d-457a-9268-632acccc4eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210599464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1210599464
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.668770825
Short name T232
Test name
Test status
Simulation time 47693857901 ps
CPU time 190.73 seconds
Started Jun 22 04:42:24 PM PDT 24
Finished Jun 22 04:45:36 PM PDT 24
Peak memory 182888 kb
Host smart-c5cd5339-b91a-44c6-9d3a-d834850cac52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668770825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.668770825
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2745839408
Short name T184
Test name
Test status
Simulation time 82823197964 ps
CPU time 273.34 seconds
Started Jun 22 04:42:24 PM PDT 24
Finished Jun 22 04:46:58 PM PDT 24
Peak memory 191188 kb
Host smart-17a21595-05f3-4692-84e5-21d6d718227d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745839408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2745839408
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.919777109
Short name T320
Test name
Test status
Simulation time 950050113345 ps
CPU time 232.79 seconds
Started Jun 22 04:42:25 PM PDT 24
Finished Jun 22 04:46:19 PM PDT 24
Peak memory 191132 kb
Host smart-efe1f9b2-6c26-46d0-b534-a6e2f9dcdf29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919777109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.919777109
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.359507318
Short name T154
Test name
Test status
Simulation time 111280298213 ps
CPU time 330.92 seconds
Started Jun 22 04:43:29 PM PDT 24
Finished Jun 22 04:49:01 PM PDT 24
Peak memory 191088 kb
Host smart-47e1d7ff-5dfe-4393-95ec-0271b21cfb93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359507318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.359507318
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.442392413
Short name T338
Test name
Test status
Simulation time 100429901156 ps
CPU time 163.71 seconds
Started Jun 22 04:42:26 PM PDT 24
Finished Jun 22 04:45:10 PM PDT 24
Peak memory 191188 kb
Host smart-761ae2b7-a91b-4de9-8199-bb7be7fc9d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442392413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.442392413
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1884665120
Short name T308
Test name
Test status
Simulation time 160250232998 ps
CPU time 88.54 seconds
Started Jun 22 04:42:30 PM PDT 24
Finished Jun 22 04:43:59 PM PDT 24
Peak memory 183224 kb
Host smart-64e88c5e-bc72-4d93-b1a9-aaf5d91b4046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884665120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1884665120
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1047057001
Short name T393
Test name
Test status
Simulation time 85685040470 ps
CPU time 128.15 seconds
Started Jun 22 04:41:13 PM PDT 24
Finished Jun 22 04:43:22 PM PDT 24
Peak memory 182996 kb
Host smart-dc06445e-d4dc-4163-8d82-c2b2971205fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047057001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1047057001
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.4127579180
Short name T145
Test name
Test status
Simulation time 139034484867 ps
CPU time 265.08 seconds
Started Jun 22 04:41:11 PM PDT 24
Finished Jun 22 04:45:36 PM PDT 24
Peak memory 191080 kb
Host smart-499c03a1-086d-4706-b336-4cd17084e791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127579180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4127579180
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3439472098
Short name T331
Test name
Test status
Simulation time 106572419102 ps
CPU time 53.03 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:42:11 PM PDT 24
Peak memory 194668 kb
Host smart-9bcde4bc-a28b-4005-8db0-0038dc2a3ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439472098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3439472098
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3982686092
Short name T15
Test name
Test status
Simulation time 35033739 ps
CPU time 0.77 seconds
Started Jun 22 04:41:06 PM PDT 24
Finished Jun 22 04:41:07 PM PDT 24
Peak memory 213136 kb
Host smart-b7c689f2-09c6-4c60-9721-ebe4346c4473
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982686092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3982686092
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1231961533
Short name T3
Test name
Test status
Simulation time 474524968457 ps
CPU time 194.48 seconds
Started Jun 22 04:41:05 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 191068 kb
Host smart-36943cce-a29e-4a3d-bb0a-d4d74afefa3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231961533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1231961533
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3088674808
Short name T266
Test name
Test status
Simulation time 394323967051 ps
CPU time 178.76 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:44:23 PM PDT 24
Peak memory 182860 kb
Host smart-e0ea2b67-7c35-42ea-953a-09b7d39d0746
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088674808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3088674808
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.787024453
Short name T377
Test name
Test status
Simulation time 74583480584 ps
CPU time 94.2 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 04:42:58 PM PDT 24
Peak memory 182904 kb
Host smart-d2f995da-38b2-4d4e-a0c9-312bd8386bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787024453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.787024453
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4180362951
Short name T168
Test name
Test status
Simulation time 3790956619 ps
CPU time 4.48 seconds
Started Jun 22 04:41:42 PM PDT 24
Finished Jun 22 04:41:48 PM PDT 24
Peak memory 183016 kb
Host smart-61c4b737-2527-4525-a518-c2dc0063c298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180362951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4180362951
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.529833647
Short name T384
Test name
Test status
Simulation time 137327991897 ps
CPU time 159.39 seconds
Started Jun 22 04:41:38 PM PDT 24
Finished Jun 22 04:44:18 PM PDT 24
Peak memory 182884 kb
Host smart-62abde90-b662-4723-9945-9180551c565c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529833647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
529833647
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2271512773
Short name T14
Test name
Test status
Simulation time 109005207127 ps
CPU time 1104.62 seconds
Started Jun 22 04:41:20 PM PDT 24
Finished Jun 22 04:59:48 PM PDT 24
Peak memory 212192 kb
Host smart-a6b62fde-89b0-45a4-8844-c12f3576314b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271512773 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2271512773
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3310262988
Short name T183
Test name
Test status
Simulation time 117004932174 ps
CPU time 86.61 seconds
Started Jun 22 04:41:23 PM PDT 24
Finished Jun 22 04:42:51 PM PDT 24
Peak memory 182872 kb
Host smart-a00edd42-2276-435a-90a1-8af759f66e02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310262988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3310262988
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1990559560
Short name T385
Test name
Test status
Simulation time 995977874488 ps
CPU time 312.99 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:46:37 PM PDT 24
Peak memory 182812 kb
Host smart-e143cc9e-dc1b-469c-b815-ec351722d851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990559560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1990559560
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.426776051
Short name T297
Test name
Test status
Simulation time 197242487444 ps
CPU time 177.32 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:44:21 PM PDT 24
Peak memory 191192 kb
Host smart-aaff74bc-18fc-4fec-bf12-811671effb97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426776051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.426776051
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1906146820
Short name T438
Test name
Test status
Simulation time 42754364138 ps
CPU time 311.16 seconds
Started Jun 22 04:41:22 PM PDT 24
Finished Jun 22 04:46:35 PM PDT 24
Peak memory 191420 kb
Host smart-5d3dcc89-282e-474f-b156-b057ade30d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906146820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1906146820
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1222026237
Short name T412
Test name
Test status
Simulation time 417220681875 ps
CPU time 526.8 seconds
Started Jun 22 04:41:20 PM PDT 24
Finished Jun 22 04:50:10 PM PDT 24
Peak memory 191092 kb
Host smart-85828c51-ff56-46ee-b126-cc84c2e01e86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222026237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1222026237
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.3701163058
Short name T37
Test name
Test status
Simulation time 38716260646 ps
CPU time 199.92 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 04:44:44 PM PDT 24
Peak memory 197592 kb
Host smart-c236a6e5-a485-4648-b197-e928129ac15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701163058 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.3701163058
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3268687085
Short name T136
Test name
Test status
Simulation time 899604187524 ps
CPU time 500.66 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 04:49:45 PM PDT 24
Peak memory 182948 kb
Host smart-d1a1f68c-d2a1-444e-bc3b-e18cefce4902
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268687085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3268687085
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3181704849
Short name T443
Test name
Test status
Simulation time 947182320162 ps
CPU time 256.8 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 04:45:40 PM PDT 24
Peak memory 182940 kb
Host smart-5e2a52c0-9b46-4899-9de1-1d5415696695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181704849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3181704849
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2338266887
Short name T311
Test name
Test status
Simulation time 73527135912 ps
CPU time 168 seconds
Started Jun 22 04:41:33 PM PDT 24
Finished Jun 22 04:44:21 PM PDT 24
Peak memory 191104 kb
Host smart-d4c2e7d2-8aef-45ab-b403-2ab51ce4a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338266887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2338266887
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2365750120
Short name T378
Test name
Test status
Simulation time 452008893031 ps
CPU time 169.15 seconds
Started Jun 22 04:41:36 PM PDT 24
Finished Jun 22 04:44:26 PM PDT 24
Peak memory 182984 kb
Host smart-a6de3e32-008a-497e-979c-9caded31adfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365750120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2365750120
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.685766181
Short name T235
Test name
Test status
Simulation time 22536238552 ps
CPU time 41.11 seconds
Started Jun 22 04:41:31 PM PDT 24
Finished Jun 22 04:42:12 PM PDT 24
Peak memory 191204 kb
Host smart-d5333ee6-06fb-4b24-ab7c-83785f7c7182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685766181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.685766181
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.419574727
Short name T230
Test name
Test status
Simulation time 130799509749 ps
CPU time 705.31 seconds
Started Jun 22 04:41:38 PM PDT 24
Finished Jun 22 04:53:24 PM PDT 24
Peak memory 191028 kb
Host smart-4bb64d57-c27e-4266-830d-1369d7eb63a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419574727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
419574727
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.4157543839
Short name T38
Test name
Test status
Simulation time 16904808546 ps
CPU time 117.78 seconds
Started Jun 22 04:41:38 PM PDT 24
Finished Jun 22 04:43:37 PM PDT 24
Peak memory 197668 kb
Host smart-7c26b0de-5168-4723-bf76-bca7817939cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157543839 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.4157543839
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.4229009536
Short name T117
Test name
Test status
Simulation time 291885757854 ps
CPU time 502.84 seconds
Started Jun 22 04:41:29 PM PDT 24
Finished Jun 22 04:49:52 PM PDT 24
Peak memory 182976 kb
Host smart-120db282-0a06-4479-a2aa-f06fd0f8d3eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229009536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.4229009536
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2308665755
Short name T396
Test name
Test status
Simulation time 93539420212 ps
CPU time 146.25 seconds
Started Jun 22 04:41:33 PM PDT 24
Finished Jun 22 04:44:00 PM PDT 24
Peak memory 182996 kb
Host smart-5c8c3439-fb5b-4ab1-abb6-020950485418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308665755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2308665755
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1106652426
Short name T248
Test name
Test status
Simulation time 118637115845 ps
CPU time 55.86 seconds
Started Jun 22 04:41:30 PM PDT 24
Finished Jun 22 04:42:27 PM PDT 24
Peak memory 182984 kb
Host smart-82a17b9e-5d1f-434b-8184-3d2162cef341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106652426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1106652426
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.601676432
Short name T411
Test name
Test status
Simulation time 432173533 ps
CPU time 0.71 seconds
Started Jun 22 04:41:29 PM PDT 24
Finished Jun 22 04:41:31 PM PDT 24
Peak memory 182652 kb
Host smart-9c4350c3-664c-46b6-b895-cf4d5057e5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601676432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.601676432
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1968516241
Short name T262
Test name
Test status
Simulation time 309928202820 ps
CPU time 112.78 seconds
Started Jun 22 04:41:27 PM PDT 24
Finished Jun 22 04:43:20 PM PDT 24
Peak memory 182964 kb
Host smart-5741fdeb-aff0-4720-81a8-60d5655f0481
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968516241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1968516241
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2505427212
Short name T376
Test name
Test status
Simulation time 62308948500 ps
CPU time 42.69 seconds
Started Jun 22 04:41:31 PM PDT 24
Finished Jun 22 04:42:14 PM PDT 24
Peak memory 182992 kb
Host smart-a663ed48-5f8a-4cb1-bd5c-393332f19b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505427212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2505427212
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1251274131
Short name T199
Test name
Test status
Simulation time 38696669069 ps
CPU time 62.67 seconds
Started Jun 22 04:41:37 PM PDT 24
Finished Jun 22 04:42:40 PM PDT 24
Peak memory 182832 kb
Host smart-93ab00ae-67dd-4002-820e-69a35bb86883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251274131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1251274131
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3951250418
Short name T413
Test name
Test status
Simulation time 749052858072 ps
CPU time 198.01 seconds
Started Jun 22 04:41:26 PM PDT 24
Finished Jun 22 04:44:45 PM PDT 24
Peak memory 194488 kb
Host smart-c45f88cb-9ea9-472c-aac1-26cd2fc415c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951250418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3951250418
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.53903119
Short name T114
Test name
Test status
Simulation time 813796433705 ps
CPU time 1011.64 seconds
Started Jun 22 04:41:32 PM PDT 24
Finished Jun 22 04:58:24 PM PDT 24
Peak memory 183108 kb
Host smart-346cd47f-5403-4642-8c24-908bc8a9f70e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53903119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.rv_timer_cfg_update_on_fly.53903119
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2048152613
Short name T25
Test name
Test status
Simulation time 145744361455 ps
CPU time 185.55 seconds
Started Jun 22 04:41:27 PM PDT 24
Finished Jun 22 04:44:33 PM PDT 24
Peak memory 182872 kb
Host smart-02f89f8c-b463-4646-b3e2-133af409ccf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048152613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2048152613
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.303882058
Short name T175
Test name
Test status
Simulation time 125443203117 ps
CPU time 186.86 seconds
Started Jun 22 04:41:30 PM PDT 24
Finished Jun 22 04:44:37 PM PDT 24
Peak memory 191172 kb
Host smart-125e1b00-7e37-47f4-ba69-3558e527089e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303882058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.303882058
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.64958610
Short name T349
Test name
Test status
Simulation time 518898939350 ps
CPU time 174.16 seconds
Started Jun 22 04:41:28 PM PDT 24
Finished Jun 22 04:44:23 PM PDT 24
Peak memory 182980 kb
Host smart-b7ea7cce-3769-4d39-9f9c-1e3ee7735b37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64958610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.rv_timer_cfg_update_on_fly.64958610
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1735003288
Short name T364
Test name
Test status
Simulation time 55646235527 ps
CPU time 73.49 seconds
Started Jun 22 04:41:35 PM PDT 24
Finished Jun 22 04:42:49 PM PDT 24
Peak memory 182896 kb
Host smart-06eb9192-cf22-4c3c-af11-42e9ee65d6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735003288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1735003288
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.826382623
Short name T129
Test name
Test status
Simulation time 286583588329 ps
CPU time 396.55 seconds
Started Jun 22 04:41:28 PM PDT 24
Finished Jun 22 04:48:05 PM PDT 24
Peak memory 182984 kb
Host smart-8d432d8c-778d-4d3d-9a3b-a8fae8076874
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826382623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.826382623
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.55073650
Short name T370
Test name
Test status
Simulation time 415406599097 ps
CPU time 161.58 seconds
Started Jun 22 04:41:38 PM PDT 24
Finished Jun 22 04:44:20 PM PDT 24
Peak memory 183004 kb
Host smart-9d835596-f07b-4d3d-92f3-ca2b5176db1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55073650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.55073650
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.68645403
Short name T225
Test name
Test status
Simulation time 205914997672 ps
CPU time 65.74 seconds
Started Jun 22 04:41:36 PM PDT 24
Finished Jun 22 04:42:43 PM PDT 24
Peak memory 191140 kb
Host smart-8b6f38e6-be44-4dd9-8288-1b964af46ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68645403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.68645403
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.740991368
Short name T67
Test name
Test status
Simulation time 512938606 ps
CPU time 0.64 seconds
Started Jun 22 04:41:31 PM PDT 24
Finished Jun 22 04:41:37 PM PDT 24
Peak memory 182712 kb
Host smart-f0c5a5b9-892e-47c5-bb5d-ad236142ba35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740991368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
740991368
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1467873977
Short name T265
Test name
Test status
Simulation time 308336201723 ps
CPU time 288.91 seconds
Started Jun 22 04:41:41 PM PDT 24
Finished Jun 22 04:46:31 PM PDT 24
Peak memory 182880 kb
Host smart-2b7964a4-b7be-4b96-8b77-677772778b75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467873977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1467873977
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.917395376
Short name T371
Test name
Test status
Simulation time 359104270513 ps
CPU time 147.71 seconds
Started Jun 22 04:41:30 PM PDT 24
Finished Jun 22 04:43:58 PM PDT 24
Peak memory 183000 kb
Host smart-23f96572-4a9a-4036-acbc-af3744719356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917395376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.917395376
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1478792817
Short name T278
Test name
Test status
Simulation time 89182774409 ps
CPU time 880.31 seconds
Started Jun 22 04:41:35 PM PDT 24
Finished Jun 22 04:56:16 PM PDT 24
Peak memory 191188 kb
Host smart-df71faa9-891c-40a0-a1d9-e0b4eee7efc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478792817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1478792817
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1299269168
Short name T447
Test name
Test status
Simulation time 78239838507 ps
CPU time 373.4 seconds
Started Jun 22 04:41:44 PM PDT 24
Finished Jun 22 04:47:58 PM PDT 24
Peak memory 182904 kb
Host smart-38f4b199-dc81-44df-92d5-33e245185768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299269168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1299269168
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.4072587764
Short name T445
Test name
Test status
Simulation time 22392198 ps
CPU time 0.59 seconds
Started Jun 22 04:41:38 PM PDT 24
Finished Jun 22 04:41:39 PM PDT 24
Peak memory 182960 kb
Host smart-b8bcf409-b8b0-46a7-b250-dbba91a81e49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072587764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.4072587764
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3743635438
Short name T57
Test name
Test status
Simulation time 20648310910 ps
CPU time 6.49 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:41:25 PM PDT 24
Peak memory 182884 kb
Host smart-e94e1518-0c94-4bf3-942a-ed9b4af342d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743635438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3743635438
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1653179374
Short name T382
Test name
Test status
Simulation time 68745895558 ps
CPU time 53.58 seconds
Started Jun 22 04:41:07 PM PDT 24
Finished Jun 22 04:42:01 PM PDT 24
Peak memory 182924 kb
Host smart-653e3f75-26f2-438c-bf9e-3826a0e493e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653179374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1653179374
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.703415403
Short name T428
Test name
Test status
Simulation time 454105597 ps
CPU time 1.28 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:41:20 PM PDT 24
Peak memory 182728 kb
Host smart-43a1897f-c218-4f84-a7f8-a100ebbd5d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703415403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.703415403
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.996514557
Short name T18
Test name
Test status
Simulation time 96271425 ps
CPU time 0.9 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:41:20 PM PDT 24
Peak memory 214260 kb
Host smart-aa800b90-19c6-414c-acfb-536e8b2e791a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996514557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.996514557
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2071841305
Short name T169
Test name
Test status
Simulation time 443431868511 ps
CPU time 1917.35 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 05:13:17 PM PDT 24
Peak memory 191132 kb
Host smart-b2f053d0-b0b6-460f-88d1-5c7ba387d0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071841305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2071841305
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.871086429
Short name T422
Test name
Test status
Simulation time 1545720352792 ps
CPU time 404.69 seconds
Started Jun 22 04:41:40 PM PDT 24
Finished Jun 22 04:48:26 PM PDT 24
Peak memory 182976 kb
Host smart-8b5bbb21-0ba9-485e-b9a0-d3ffb3ceffb2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871086429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.871086429
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2463749151
Short name T418
Test name
Test status
Simulation time 361066576415 ps
CPU time 125.29 seconds
Started Jun 22 04:41:41 PM PDT 24
Finished Jun 22 04:43:47 PM PDT 24
Peak memory 183000 kb
Host smart-7222cbcf-a95a-437d-9886-b23fd0286207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463749151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2463749151
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2639575859
Short name T435
Test name
Test status
Simulation time 95142332 ps
CPU time 1.03 seconds
Started Jun 22 04:41:34 PM PDT 24
Finished Jun 22 04:41:36 PM PDT 24
Peak memory 182916 kb
Host smart-366bb44b-30ce-4853-bd06-45c2d4d98793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639575859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2639575859
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1264980427
Short name T35
Test name
Test status
Simulation time 1386686043783 ps
CPU time 513.28 seconds
Started Jun 22 04:41:36 PM PDT 24
Finished Jun 22 04:50:10 PM PDT 24
Peak memory 191180 kb
Host smart-2e2fd790-e944-415c-bb82-9bf71f028052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264980427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1264980427
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3897844726
Short name T369
Test name
Test status
Simulation time 14240127511 ps
CPU time 11.9 seconds
Started Jun 22 04:41:41 PM PDT 24
Finished Jun 22 04:41:54 PM PDT 24
Peak memory 183004 kb
Host smart-b1883230-ff3b-4a97-9c52-d45e58c24a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897844726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3897844726
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2976890509
Short name T272
Test name
Test status
Simulation time 8478207085 ps
CPU time 14.16 seconds
Started Jun 22 04:41:43 PM PDT 24
Finished Jun 22 04:41:58 PM PDT 24
Peak memory 182856 kb
Host smart-8342aef0-cb08-431a-878d-11addc1ba65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976890509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2976890509
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2057737624
Short name T244
Test name
Test status
Simulation time 183234779816 ps
CPU time 61.66 seconds
Started Jun 22 04:41:44 PM PDT 24
Finished Jun 22 04:42:46 PM PDT 24
Peak memory 194916 kb
Host smart-89bcac9c-727b-4d4c-a39d-30ca374fd803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057737624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2057737624
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2031357922
Short name T268
Test name
Test status
Simulation time 690567062334 ps
CPU time 305.84 seconds
Started Jun 22 04:41:35 PM PDT 24
Finished Jun 22 04:46:41 PM PDT 24
Peak memory 182924 kb
Host smart-779636b6-2d03-4495-ab24-8155f11ae380
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031357922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2031357922
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.535142451
Short name T394
Test name
Test status
Simulation time 372271434342 ps
CPU time 128.67 seconds
Started Jun 22 04:41:34 PM PDT 24
Finished Jun 22 04:43:43 PM PDT 24
Peak memory 182896 kb
Host smart-57cb378f-e702-43e2-a14e-c56c0da3946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535142451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.535142451
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.239073398
Short name T119
Test name
Test status
Simulation time 46069726108 ps
CPU time 71.72 seconds
Started Jun 22 04:41:35 PM PDT 24
Finished Jun 22 04:42:47 PM PDT 24
Peak memory 191088 kb
Host smart-674be12e-ecc1-4058-b89e-9be3d641e5a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239073398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.239073398
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2929111870
Short name T11
Test name
Test status
Simulation time 8626491554 ps
CPU time 71.94 seconds
Started Jun 22 04:41:40 PM PDT 24
Finished Jun 22 04:42:52 PM PDT 24
Peak memory 182912 kb
Host smart-582839bb-7459-40b8-9765-f7bd8c83e422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929111870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2929111870
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3750073655
Short name T217
Test name
Test status
Simulation time 3612278723564 ps
CPU time 656.32 seconds
Started Jun 22 04:41:37 PM PDT 24
Finished Jun 22 04:52:34 PM PDT 24
Peak memory 191416 kb
Host smart-53715a19-3f2a-4788-bee2-7444234fd0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750073655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3750073655
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2334251733
Short name T304
Test name
Test status
Simulation time 1745906633302 ps
CPU time 745.3 seconds
Started Jun 22 04:41:51 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 182964 kb
Host smart-8e2f9cdc-4ef9-423f-b5a6-d219a335b58f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334251733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2334251733
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.3486783197
Short name T212
Test name
Test status
Simulation time 360283917238 ps
CPU time 160.57 seconds
Started Jun 22 04:41:52 PM PDT 24
Finished Jun 22 04:44:33 PM PDT 24
Peak memory 191088 kb
Host smart-2caa4f02-7084-4cd9-8db7-84733ac5f0f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486783197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3486783197
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.63280377
Short name T273
Test name
Test status
Simulation time 99905357144 ps
CPU time 168.18 seconds
Started Jun 22 04:41:48 PM PDT 24
Finished Jun 22 04:44:37 PM PDT 24
Peak memory 191092 kb
Host smart-5d814d4e-80dc-4978-a3c4-4b69f2111074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63280377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.63280377
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3869796791
Short name T303
Test name
Test status
Simulation time 46308707744 ps
CPU time 12.29 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 04:42:03 PM PDT 24
Peak memory 182880 kb
Host smart-7fe3ad76-bc0c-491b-ac17-c340bd265480
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869796791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3869796791
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3754586099
Short name T388
Test name
Test status
Simulation time 200766248382 ps
CPU time 66.4 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 04:42:57 PM PDT 24
Peak memory 183004 kb
Host smart-b9510c7a-6da9-4cb3-8e5f-e01297a6b4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754586099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3754586099
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.161931109
Short name T357
Test name
Test status
Simulation time 6147959258 ps
CPU time 10.94 seconds
Started Jun 22 04:41:52 PM PDT 24
Finished Jun 22 04:42:03 PM PDT 24
Peak memory 182928 kb
Host smart-5d1d38b0-c67f-47a9-92f9-101de29f3ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161931109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.161931109
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2201758025
Short name T164
Test name
Test status
Simulation time 149600362266 ps
CPU time 135.98 seconds
Started Jun 22 04:41:53 PM PDT 24
Finished Jun 22 04:44:09 PM PDT 24
Peak memory 182880 kb
Host smart-24f16a8f-23fb-4f1b-bf2e-41b8d4f9c2f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201758025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2201758025
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2952310416
Short name T27
Test name
Test status
Simulation time 115937429843 ps
CPU time 160.48 seconds
Started Jun 22 04:41:46 PM PDT 24
Finished Jun 22 04:44:27 PM PDT 24
Peak memory 182996 kb
Host smart-920b7961-a65f-4c77-9557-0738f75e6b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952310416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2952310416
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3824982906
Short name T231
Test name
Test status
Simulation time 166493463608 ps
CPU time 245.67 seconds
Started Jun 22 04:41:49 PM PDT 24
Finished Jun 22 04:45:56 PM PDT 24
Peak memory 195376 kb
Host smart-2c429634-8179-4cb8-a7c7-9cd85b973604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824982906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3824982906
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2406210019
Short name T399
Test name
Test status
Simulation time 304970052978 ps
CPU time 197.71 seconds
Started Jun 22 04:41:46 PM PDT 24
Finished Jun 22 04:45:05 PM PDT 24
Peak memory 182804 kb
Host smart-f31ae0a0-ee66-478e-bbec-9627e53f46f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406210019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2406210019
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3458053277
Short name T254
Test name
Test status
Simulation time 532395854018 ps
CPU time 269.56 seconds
Started Jun 22 04:41:49 PM PDT 24
Finished Jun 22 04:46:19 PM PDT 24
Peak memory 182972 kb
Host smart-dc3737a0-0dde-4ba2-8a98-ea755e961088
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458053277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3458053277
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3841450255
Short name T381
Test name
Test status
Simulation time 70322951050 ps
CPU time 51.19 seconds
Started Jun 22 04:41:48 PM PDT 24
Finished Jun 22 04:42:39 PM PDT 24
Peak memory 182876 kb
Host smart-4c5990a9-f1e0-43c3-b912-7703d8bde845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841450255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3841450255
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1785627440
Short name T143
Test name
Test status
Simulation time 1373796661840 ps
CPU time 595.02 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 196176 kb
Host smart-8a7454ad-5be0-4ac9-b94c-d61769174859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785627440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1785627440
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1403900187
Short name T275
Test name
Test status
Simulation time 95100843751 ps
CPU time 145.98 seconds
Started Jun 22 04:41:55 PM PDT 24
Finished Jun 22 04:44:22 PM PDT 24
Peak memory 182980 kb
Host smart-4972eb14-62b4-41f4-a6f4-beccd99e1ec0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403900187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1403900187
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1380734857
Short name T392
Test name
Test status
Simulation time 101133979986 ps
CPU time 127.13 seconds
Started Jun 22 04:41:52 PM PDT 24
Finished Jun 22 04:44:00 PM PDT 24
Peak memory 183004 kb
Host smart-ebc795d5-a00d-4ec2-8698-0720aacfeef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380734857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1380734857
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1115406704
Short name T162
Test name
Test status
Simulation time 457960278409 ps
CPU time 254.67 seconds
Started Jun 22 04:41:49 PM PDT 24
Finished Jun 22 04:46:04 PM PDT 24
Peak memory 191188 kb
Host smart-f76689d4-4aa5-4829-93a0-c9af8a6be5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115406704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1115406704
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1379756326
Short name T359
Test name
Test status
Simulation time 783634002920 ps
CPU time 242.03 seconds
Started Jun 22 04:41:46 PM PDT 24
Finished Jun 22 04:45:49 PM PDT 24
Peak memory 191172 kb
Host smart-609981c2-de82-4b5a-9b05-88f3d6d12bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379756326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1379756326
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4087780637
Short name T407
Test name
Test status
Simulation time 109180788657 ps
CPU time 178.27 seconds
Started Jun 22 04:41:48 PM PDT 24
Finished Jun 22 04:44:47 PM PDT 24
Peak memory 182904 kb
Host smart-2c0096c8-cb6f-4777-82b3-8ec85799796d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087780637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4087780637
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3021040032
Short name T365
Test name
Test status
Simulation time 502719360171 ps
CPU time 62.78 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 04:42:53 PM PDT 24
Peak memory 182904 kb
Host smart-847531dc-3fde-4aed-a445-1887c314b6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021040032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3021040032
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2936322321
Short name T408
Test name
Test status
Simulation time 831524679 ps
CPU time 1 seconds
Started Jun 22 04:41:49 PM PDT 24
Finished Jun 22 04:41:50 PM PDT 24
Peak memory 182664 kb
Host smart-31ce2b17-ed80-46b3-84d7-3d94fb01a3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936322321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2936322321
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3045942075
Short name T291
Test name
Test status
Simulation time 634091928939 ps
CPU time 246.68 seconds
Started Jun 22 04:41:49 PM PDT 24
Finished Jun 22 04:45:56 PM PDT 24
Peak memory 182880 kb
Host smart-152fd4bf-eecb-4b5e-acef-31faa38f631c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045942075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3045942075
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.905558270
Short name T446
Test name
Test status
Simulation time 846183059840 ps
CPU time 219.24 seconds
Started Jun 22 04:41:53 PM PDT 24
Finished Jun 22 04:45:33 PM PDT 24
Peak memory 183004 kb
Host smart-a791a818-d259-4292-a25d-ecfefb312acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905558270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.905558270
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2559140565
Short name T202
Test name
Test status
Simulation time 36586340992 ps
CPU time 107.24 seconds
Started Jun 22 04:41:49 PM PDT 24
Finished Jun 22 04:43:37 PM PDT 24
Peak memory 194692 kb
Host smart-d9b13efe-b8d3-49c7-9296-9160f12549e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559140565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2559140565
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.811131679
Short name T352
Test name
Test status
Simulation time 3846163168 ps
CPU time 6.99 seconds
Started Jun 22 04:41:49 PM PDT 24
Finished Jun 22 04:41:56 PM PDT 24
Peak memory 182908 kb
Host smart-35ab3087-593f-428f-8182-c49353b8b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811131679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.811131679
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3797961233
Short name T243
Test name
Test status
Simulation time 202938645633 ps
CPU time 485.42 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 04:49:56 PM PDT 24
Peak memory 191180 kb
Host smart-6f58b10d-8d81-485d-a060-ee31cc906f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797961233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3797961233
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.1463071555
Short name T39
Test name
Test status
Simulation time 26593075523 ps
CPU time 205.04 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 04:45:15 PM PDT 24
Peak memory 205788 kb
Host smart-94c6c159-5c83-4dbf-a5b4-81f49c0dbc52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463071555 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.1463071555
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4099095349
Short name T209
Test name
Test status
Simulation time 6268958003 ps
CPU time 5.16 seconds
Started Jun 22 04:41:19 PM PDT 24
Finished Jun 22 04:41:27 PM PDT 24
Peak memory 182348 kb
Host smart-e753cce5-4eb5-4614-a955-5b56a55fc50b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099095349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.4099095349
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2671217847
Short name T429
Test name
Test status
Simulation time 890075292049 ps
CPU time 264.01 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:45:41 PM PDT 24
Peak memory 182820 kb
Host smart-94d5b376-5255-41e6-bd47-95a6e1b83eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671217847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2671217847
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3605119651
Short name T314
Test name
Test status
Simulation time 47682262443 ps
CPU time 1740.3 seconds
Started Jun 22 04:41:13 PM PDT 24
Finished Jun 22 05:10:15 PM PDT 24
Peak memory 182984 kb
Host smart-e9032d78-a3a8-4f05-89c8-5cecd1f3a4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605119651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3605119651
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2389033387
Short name T409
Test name
Test status
Simulation time 928402132 ps
CPU time 1.73 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:41:23 PM PDT 24
Peak memory 182596 kb
Host smart-463e03f8-bc32-445e-a1e4-7c98ecc1143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389033387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2389033387
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2718711309
Short name T19
Test name
Test status
Simulation time 100479246 ps
CPU time 0.75 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:41:21 PM PDT 24
Peak memory 213112 kb
Host smart-85f09832-83a5-4767-b116-370b2fb6ca80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718711309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2718711309
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.649894521
Short name T400
Test name
Test status
Simulation time 55302478015 ps
CPU time 69.36 seconds
Started Jun 22 04:41:53 PM PDT 24
Finished Jun 22 04:43:02 PM PDT 24
Peak memory 182940 kb
Host smart-03293356-cc04-426f-9e55-bd97a63541ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649894521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.649894521
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2915889708
Short name T319
Test name
Test status
Simulation time 39211153597 ps
CPU time 52.3 seconds
Started Jun 22 04:41:50 PM PDT 24
Finished Jun 22 04:42:43 PM PDT 24
Peak memory 182516 kb
Host smart-966acd12-fe7c-4220-81d6-f6c435ce5f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915889708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2915889708
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.807363092
Short name T342
Test name
Test status
Simulation time 121019494525 ps
CPU time 171.59 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:44:50 PM PDT 24
Peak memory 182984 kb
Host smart-0a08aa30-8c37-4bbe-9de6-90d22a9fa204
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807363092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.807363092
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2833214417
Short name T387
Test name
Test status
Simulation time 6964984806 ps
CPU time 10.82 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:42:09 PM PDT 24
Peak memory 182816 kb
Host smart-ee738d7b-153d-4611-9a14-e7e69d45ae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833214417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2833214417
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2966422573
Short name T295
Test name
Test status
Simulation time 227139766669 ps
CPU time 148.69 seconds
Started Jun 22 04:41:48 PM PDT 24
Finished Jun 22 04:44:17 PM PDT 24
Peak memory 191176 kb
Host smart-c9e79bde-053b-4582-9b6e-8b0cb9971b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966422573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2966422573
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.62336459
Short name T390
Test name
Test status
Simulation time 65992748062 ps
CPU time 347.78 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:47:46 PM PDT 24
Peak memory 194480 kb
Host smart-1365a712-3e2b-400d-ab63-1d00263eff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62336459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.62336459
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.2879325205
Short name T12
Test name
Test status
Simulation time 34520027216 ps
CPU time 72.39 seconds
Started Jun 22 04:41:58 PM PDT 24
Finished Jun 22 04:43:11 PM PDT 24
Peak memory 197692 kb
Host smart-339d1505-9409-4ed2-b2e9-2f97e855f1f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879325205 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.2879325205
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1941851758
Short name T115
Test name
Test status
Simulation time 358811807935 ps
CPU time 520.79 seconds
Started Jun 22 04:41:54 PM PDT 24
Finished Jun 22 04:50:35 PM PDT 24
Peak memory 183212 kb
Host smart-e245b34d-9882-4cc3-9100-81d11009702e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941851758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1941851758
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2589638693
Short name T405
Test name
Test status
Simulation time 355468265049 ps
CPU time 148.01 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:44:28 PM PDT 24
Peak memory 182844 kb
Host smart-a3777809-14ac-441f-b05a-76044715e84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589638693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2589638693
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.886750053
Short name T45
Test name
Test status
Simulation time 60554453175 ps
CPU time 379.37 seconds
Started Jun 22 04:41:54 PM PDT 24
Finished Jun 22 04:48:14 PM PDT 24
Peak memory 191180 kb
Host smart-97801633-6c25-4252-ae87-d4e3ddd3d31e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886750053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.886750053
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.624326697
Short name T144
Test name
Test status
Simulation time 14035096511 ps
CPU time 93.31 seconds
Started Jun 22 04:42:01 PM PDT 24
Finished Jun 22 04:43:35 PM PDT 24
Peak memory 183008 kb
Host smart-b84363f2-15e2-4aad-8015-b3f7619838a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624326697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.624326697
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.318760754
Short name T178
Test name
Test status
Simulation time 151085720134 ps
CPU time 251.52 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:46:09 PM PDT 24
Peak memory 182980 kb
Host smart-25b98dde-fb59-4455-bf64-e523253a9b6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318760754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.318760754
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.237810820
Short name T46
Test name
Test status
Simulation time 28021898914 ps
CPU time 12.26 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:42:12 PM PDT 24
Peak memory 182992 kb
Host smart-030604e7-834e-4c92-9e72-dbb4eb04f470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237810820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.237810820
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1491444189
Short name T185
Test name
Test status
Simulation time 101049892387 ps
CPU time 197.48 seconds
Started Jun 22 04:41:54 PM PDT 24
Finished Jun 22 04:45:12 PM PDT 24
Peak memory 191132 kb
Host smart-96b1946d-fc68-48e9-8f11-f981dc64858f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491444189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1491444189
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1465925131
Short name T43
Test name
Test status
Simulation time 33232885321 ps
CPU time 30.58 seconds
Started Jun 22 04:41:55 PM PDT 24
Finished Jun 22 04:42:26 PM PDT 24
Peak memory 182908 kb
Host smart-103b0cbc-1fab-4cde-bf9e-dbd12d1eccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465925131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1465925131
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3120086506
Short name T191
Test name
Test status
Simulation time 158226394847 ps
CPU time 236.84 seconds
Started Jun 22 04:42:00 PM PDT 24
Finished Jun 22 04:45:57 PM PDT 24
Peak memory 182880 kb
Host smart-a1f4058b-0fcd-40cd-a843-9899785e326e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120086506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3120086506
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1019993196
Short name T368
Test name
Test status
Simulation time 93805233222 ps
CPU time 41.26 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:42:41 PM PDT 24
Peak memory 182968 kb
Host smart-00d45aca-50b4-475e-b4ec-3efbe4892dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019993196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1019993196
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1551702254
Short name T284
Test name
Test status
Simulation time 194297943218 ps
CPU time 279.52 seconds
Started Jun 22 04:41:55 PM PDT 24
Finished Jun 22 04:46:35 PM PDT 24
Peak memory 191188 kb
Host smart-4d8dde29-ce69-4111-8250-75f62657fb25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551702254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1551702254
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.4112667515
Short name T410
Test name
Test status
Simulation time 179222198648 ps
CPU time 338.17 seconds
Started Jun 22 04:41:55 PM PDT 24
Finished Jun 22 04:47:33 PM PDT 24
Peak memory 182920 kb
Host smart-17a5bb82-abbe-4b39-95f7-982ffb485d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112667515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4112667515
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1785333274
Short name T323
Test name
Test status
Simulation time 368933776540 ps
CPU time 205.67 seconds
Started Jun 22 04:41:55 PM PDT 24
Finished Jun 22 04:45:21 PM PDT 24
Peak memory 182880 kb
Host smart-329640d5-efb6-44eb-9d7b-de143131148d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785333274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1785333274
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.24615249
Short name T373
Test name
Test status
Simulation time 41512032515 ps
CPU time 65.78 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:43:04 PM PDT 24
Peak memory 183004 kb
Host smart-74138aef-93ad-46d5-9fd7-41965881f77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24615249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.24615249
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1293188061
Short name T360
Test name
Test status
Simulation time 16828276078 ps
CPU time 28.74 seconds
Started Jun 22 04:41:58 PM PDT 24
Finished Jun 22 04:42:28 PM PDT 24
Peak memory 194400 kb
Host smart-0ab99593-6eb4-4400-8a1a-6815033c3139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293188061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1293188061
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3760167510
Short name T442
Test name
Test status
Simulation time 41290603174 ps
CPU time 57.98 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:42:58 PM PDT 24
Peak memory 191184 kb
Host smart-721c0681-c721-48b0-b082-cc9e99488bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760167510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3760167510
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.4098552128
Short name T200
Test name
Test status
Simulation time 161884050607 ps
CPU time 535.44 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 191180 kb
Host smart-8b5499d5-76e0-4782-9e52-57ba6665fcb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098552128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.4098552128
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.32242011
Short name T58
Test name
Test status
Simulation time 77263979379 ps
CPU time 115.02 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:43:53 PM PDT 24
Peak memory 182984 kb
Host smart-ffd734b0-abce-4231-9cb2-04d4a8879ccb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32242011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.rv_timer_cfg_update_on_fly.32242011
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3151434980
Short name T367
Test name
Test status
Simulation time 119580043531 ps
CPU time 179.83 seconds
Started Jun 22 04:41:55 PM PDT 24
Finished Jun 22 04:44:56 PM PDT 24
Peak memory 182880 kb
Host smart-77f893ac-2797-4ffd-86ed-00711a33fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151434980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3151434980
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1160429216
Short name T444
Test name
Test status
Simulation time 191551060 ps
CPU time 0.84 seconds
Started Jun 22 04:41:53 PM PDT 24
Finished Jun 22 04:41:55 PM PDT 24
Peak memory 182676 kb
Host smart-143666fc-a9a5-4fb2-a8f5-d97591b49519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160429216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1160429216
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.710980181
Short name T40
Test name
Test status
Simulation time 14328118618 ps
CPU time 77.33 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:43:15 PM PDT 24
Peak memory 195376 kb
Host smart-c9bc30f9-d75d-44fb-a99a-9bb5a1b9b8b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710980181 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.710980181
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2000066499
Short name T211
Test name
Test status
Simulation time 220034320394 ps
CPU time 319.04 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:47:19 PM PDT 24
Peak memory 182816 kb
Host smart-21448af1-1615-417e-955b-7e175cc4ac1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000066499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2000066499
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.2345100078
Short name T158
Test name
Test status
Simulation time 125532824815 ps
CPU time 194.59 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:45:12 PM PDT 24
Peak memory 193340 kb
Host smart-09397050-734a-4ce1-a45c-ca180c39a48c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345100078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2345100078
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.785594502
Short name T353
Test name
Test status
Simulation time 198363802347 ps
CPU time 181.56 seconds
Started Jun 22 04:41:55 PM PDT 24
Finished Jun 22 04:44:57 PM PDT 24
Peak memory 183000 kb
Host smart-cf845e25-191b-46f2-95e3-e7fd80789667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785594502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.785594502
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3432879477
Short name T10
Test name
Test status
Simulation time 2246293273198 ps
CPU time 1145.63 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 05:01:02 PM PDT 24
Peak memory 182852 kb
Host smart-20e8b754-deff-426c-be61-f838918c3d0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432879477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3432879477
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.3287178383
Short name T293
Test name
Test status
Simulation time 141747434293 ps
CPU time 366.49 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:48:05 PM PDT 24
Peak memory 191184 kb
Host smart-0b1b53cd-7838-4a4a-a8ce-8e75cb62898c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287178383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3287178383
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2343240090
Short name T166
Test name
Test status
Simulation time 43257024834 ps
CPU time 87.25 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:43:24 PM PDT 24
Peak memory 194768 kb
Host smart-e0d7b29b-26bd-461f-b10b-9e7665228294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343240090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2343240090
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1570845482
Short name T424
Test name
Test status
Simulation time 732358859786 ps
CPU time 281.33 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:46:41 PM PDT 24
Peak memory 195616 kb
Host smart-0f63df2d-f8ea-458b-85da-fb236ae667b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570845482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1570845482
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2054175669
Short name T130
Test name
Test status
Simulation time 308486400923 ps
CPU time 518.57 seconds
Started Jun 22 04:41:58 PM PDT 24
Finished Jun 22 04:50:38 PM PDT 24
Peak memory 182980 kb
Host smart-ac4e2398-3a78-4352-aea7-a7f0e8abc300
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054175669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2054175669
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1640628150
Short name T395
Test name
Test status
Simulation time 68703315740 ps
CPU time 51.78 seconds
Started Jun 22 04:41:54 PM PDT 24
Finished Jun 22 04:42:46 PM PDT 24
Peak memory 182904 kb
Host smart-e75c738d-4fd5-4d8c-ab65-69e5f2632b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640628150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1640628150
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.531933920
Short name T214
Test name
Test status
Simulation time 21525685646 ps
CPU time 29.87 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:42:27 PM PDT 24
Peak memory 182872 kb
Host smart-5932101d-1bd6-4b17-aa65-a50b88a2df78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531933920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.531933920
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1620711447
Short name T402
Test name
Test status
Simulation time 46471428534 ps
CPU time 14.57 seconds
Started Jun 22 04:41:58 PM PDT 24
Finished Jun 22 04:42:14 PM PDT 24
Peak memory 183004 kb
Host smart-01dac6c9-3c75-4697-9480-9bed0b0355cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620711447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1620711447
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2422015508
Short name T340
Test name
Test status
Simulation time 15255946503 ps
CPU time 25.01 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:41:42 PM PDT 24
Peak memory 182860 kb
Host smart-d9661bc2-0a3f-46f5-88e3-0bc10cb3dfaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422015508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2422015508
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3889901644
Short name T406
Test name
Test status
Simulation time 839673539951 ps
CPU time 282.96 seconds
Started Jun 22 04:41:14 PM PDT 24
Finished Jun 22 04:45:58 PM PDT 24
Peak memory 183004 kb
Host smart-c8d2d1d4-33d2-4c88-9228-0710e51f5fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889901644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3889901644
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.886423287
Short name T1
Test name
Test status
Simulation time 202961338708 ps
CPU time 448.28 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:48:50 PM PDT 24
Peak memory 191180 kb
Host smart-c8173dca-4e4d-4fbf-917a-4c629db6e8a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886423287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.886423287
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1423253741
Short name T441
Test name
Test status
Simulation time 43081496 ps
CPU time 0.6 seconds
Started Jun 22 04:41:12 PM PDT 24
Finished Jun 22 04:41:13 PM PDT 24
Peak memory 182708 kb
Host smart-91f126c6-e536-4b44-8356-b0a72e2c3060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423253741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1423253741
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/51.rv_timer_random.3584467425
Short name T234
Test name
Test status
Simulation time 91384807852 ps
CPU time 134.84 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:44:12 PM PDT 24
Peak memory 191128 kb
Host smart-daa69ddd-a100-4a40-bf3c-cfe5350a61a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584467425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3584467425
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.720115242
Short name T53
Test name
Test status
Simulation time 135173588849 ps
CPU time 106.02 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:43:43 PM PDT 24
Peak memory 191156 kb
Host smart-f06862b2-80b2-4440-8d01-700bb6a208c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720115242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.720115242
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2569545571
Short name T105
Test name
Test status
Simulation time 130315959365 ps
CPU time 915.06 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:57:13 PM PDT 24
Peak memory 191188 kb
Host smart-b966287b-c5f5-4ae5-a48e-d7e0c3b76ca9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569545571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2569545571
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.673826567
Short name T54
Test name
Test status
Simulation time 23866380195 ps
CPU time 166.32 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:44:46 PM PDT 24
Peak memory 191160 kb
Host smart-8f3f8567-d4e1-4ab1-8e66-0250ea5babb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673826567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.673826567
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3486224543
Short name T133
Test name
Test status
Simulation time 217878710160 ps
CPU time 448.39 seconds
Started Jun 22 04:41:57 PM PDT 24
Finished Jun 22 04:49:27 PM PDT 24
Peak memory 193380 kb
Host smart-3924a3ba-7afc-491d-bbe8-68989a088702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486224543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3486224543
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4261899349
Short name T223
Test name
Test status
Simulation time 13985129849 ps
CPU time 20.71 seconds
Started Jun 22 04:41:16 PM PDT 24
Finished Jun 22 04:41:40 PM PDT 24
Peak memory 182984 kb
Host smart-e902fbb0-5f4b-4dab-89a6-c51b1569ddf4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261899349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4261899349
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.907816102
Short name T380
Test name
Test status
Simulation time 116258971273 ps
CPU time 160.54 seconds
Started Jun 22 04:41:12 PM PDT 24
Finished Jun 22 04:43:53 PM PDT 24
Peak memory 182880 kb
Host smart-bfb1be80-bfcf-4e88-95a9-919cca69e881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907816102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.907816102
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1446997091
Short name T127
Test name
Test status
Simulation time 100887277775 ps
CPU time 112.41 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:43:14 PM PDT 24
Peak memory 182984 kb
Host smart-168cacb9-1b79-4798-8657-ba656ead13ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446997091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1446997091
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.422246313
Short name T419
Test name
Test status
Simulation time 100503753611 ps
CPU time 83.24 seconds
Started Jun 22 04:41:14 PM PDT 24
Finished Jun 22 04:42:38 PM PDT 24
Peak memory 183008 kb
Host smart-802f3b75-1db6-4a7f-9816-e91858a5858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422246313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.422246313
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3431082702
Short name T251
Test name
Test status
Simulation time 439291625757 ps
CPU time 560.71 seconds
Started Jun 22 04:41:17 PM PDT 24
Finished Jun 22 04:50:42 PM PDT 24
Peak memory 191184 kb
Host smart-b993b502-ff11-426f-96f9-6c1eeb446870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431082702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3431082702
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.999415871
Short name T139
Test name
Test status
Simulation time 395413142738 ps
CPU time 556.88 seconds
Started Jun 22 04:41:58 PM PDT 24
Finished Jun 22 04:51:16 PM PDT 24
Peak memory 191172 kb
Host smart-05521e3a-d12f-4e6f-9642-bfe1bc2ace70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999415871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.999415871
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2816374603
Short name T22
Test name
Test status
Simulation time 33749271265 ps
CPU time 15.29 seconds
Started Jun 22 04:41:56 PM PDT 24
Finished Jun 22 04:42:13 PM PDT 24
Peak memory 182988 kb
Host smart-44d228cf-f7c0-4e2b-baa5-3130c305c562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816374603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2816374603
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3912133158
Short name T109
Test name
Test status
Simulation time 2806097773231 ps
CPU time 621.91 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:52:22 PM PDT 24
Peak memory 191180 kb
Host smart-e67c4904-4972-44e5-9788-7a126d5cd9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912133158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3912133158
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3949112109
Short name T247
Test name
Test status
Simulation time 134199737476 ps
CPU time 349.74 seconds
Started Jun 22 04:42:00 PM PDT 24
Finished Jun 22 04:47:50 PM PDT 24
Peak memory 191188 kb
Host smart-dd51f422-72a3-4822-9e07-01737fe08ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949112109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3949112109
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2220992706
Short name T415
Test name
Test status
Simulation time 16236673672 ps
CPU time 21.16 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:42:21 PM PDT 24
Peak memory 182792 kb
Host smart-6b9d4d36-e32c-4d52-8792-3d29c031d104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220992706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2220992706
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3488499468
Short name T182
Test name
Test status
Simulation time 260006541871 ps
CPU time 181.57 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:44:23 PM PDT 24
Peak memory 182996 kb
Host smart-e9aab198-6b10-41d9-81b7-59f5e7757ae9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488499468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3488499468
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3560434017
Short name T386
Test name
Test status
Simulation time 340574720254 ps
CPU time 132.84 seconds
Started Jun 22 04:41:13 PM PDT 24
Finished Jun 22 04:43:26 PM PDT 24
Peak memory 182904 kb
Host smart-c99b5ae5-ba5c-4546-a636-6b4d77b33fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560434017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3560434017
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2548023480
Short name T345
Test name
Test status
Simulation time 72641634559 ps
CPU time 32.98 seconds
Started Jun 22 04:41:09 PM PDT 24
Finished Jun 22 04:41:43 PM PDT 24
Peak memory 191132 kb
Host smart-6e91f80f-21bb-4ff1-a270-6df7bc9d2b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548023480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2548023480
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3431913149
Short name T431
Test name
Test status
Simulation time 155028572 ps
CPU time 0.78 seconds
Started Jun 22 04:41:21 PM PDT 24
Finished Jun 22 04:41:24 PM PDT 24
Peak memory 182756 kb
Host smart-f021140f-3281-4dfa-9268-9dd4f94adeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431913149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3431913149
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.4136237741
Short name T63
Test name
Test status
Simulation time 2655072781917 ps
CPU time 981.84 seconds
Started Jun 22 04:41:12 PM PDT 24
Finished Jun 22 04:57:35 PM PDT 24
Peak memory 191196 kb
Host smart-17d68602-6250-4b1b-a5e9-edc9b334ed01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136237741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
4136237741
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3885552604
Short name T294
Test name
Test status
Simulation time 605603617929 ps
CPU time 519.64 seconds
Started Jun 22 04:41:59 PM PDT 24
Finished Jun 22 04:50:39 PM PDT 24
Peak memory 191004 kb
Host smart-25130309-0578-4a57-95e3-016a33858eba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885552604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3885552604
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2187220253
Short name T180
Test name
Test status
Simulation time 9346839575 ps
CPU time 16.3 seconds
Started Jun 22 04:41:58 PM PDT 24
Finished Jun 22 04:42:16 PM PDT 24
Peak memory 191084 kb
Host smart-ea854915-d9a0-46b4-83e5-e963eb1a5896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187220253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2187220253
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3937594914
Short name T258
Test name
Test status
Simulation time 3097201230 ps
CPU time 3.37 seconds
Started Jun 22 04:42:00 PM PDT 24
Finished Jun 22 04:42:04 PM PDT 24
Peak memory 182988 kb
Host smart-1a15e08a-db4a-46e5-a146-e9a119bad9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937594914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3937594914
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3364148078
Short name T236
Test name
Test status
Simulation time 59941031046 ps
CPU time 216.21 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:45:40 PM PDT 24
Peak memory 191076 kb
Host smart-9eb2c464-3581-4e04-92e2-16bb5f68f642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364148078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3364148078
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3217507442
Short name T430
Test name
Test status
Simulation time 472467367639 ps
CPU time 262.38 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:46:27 PM PDT 24
Peak memory 191088 kb
Host smart-72d45e8a-88bc-466b-bef2-b505b162f9f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217507442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3217507442
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.782274351
Short name T274
Test name
Test status
Simulation time 106997344953 ps
CPU time 85.06 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:43:31 PM PDT 24
Peak memory 182980 kb
Host smart-fdea86a2-fe2d-41b0-9596-1a8ad8160909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782274351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.782274351
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.821552045
Short name T220
Test name
Test status
Simulation time 187316097129 ps
CPU time 353.49 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:47:57 PM PDT 24
Peak memory 191116 kb
Host smart-3e654437-e959-48fc-ac32-bad19eae8ece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821552045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.821552045
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3518251430
Short name T176
Test name
Test status
Simulation time 317739554680 ps
CPU time 793.39 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:55:17 PM PDT 24
Peak memory 191028 kb
Host smart-810290e7-f01c-4011-9ccc-769aa43fc3e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518251430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3518251430
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.173704046
Short name T269
Test name
Test status
Simulation time 287430209358 ps
CPU time 445.27 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:48:47 PM PDT 24
Peak memory 182860 kb
Host smart-b8f143dc-4b5e-4ae4-b282-61430cbca0bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173704046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.173704046
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3794138927
Short name T426
Test name
Test status
Simulation time 563762862448 ps
CPU time 229.06 seconds
Started Jun 22 04:41:12 PM PDT 24
Finished Jun 22 04:45:02 PM PDT 24
Peak memory 183004 kb
Host smart-d8892b46-0787-4431-be0b-53fa5adadb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794138927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3794138927
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2089612999
Short name T120
Test name
Test status
Simulation time 305938429296 ps
CPU time 378.01 seconds
Started Jun 22 04:41:14 PM PDT 24
Finished Jun 22 04:47:33 PM PDT 24
Peak memory 192660 kb
Host smart-cdf044fd-731a-4925-9d34-554c47394ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089612999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2089612999
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1814863715
Short name T389
Test name
Test status
Simulation time 1013706651 ps
CPU time 1.11 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:41:18 PM PDT 24
Peak memory 192440 kb
Host smart-3599bc37-97eb-4ce9-809a-b5862d594ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814863715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1814863715
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3665846195
Short name T318
Test name
Test status
Simulation time 250058371659 ps
CPU time 875.54 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:56:43 PM PDT 24
Peak memory 191088 kb
Host smart-7ef93c77-0093-49a0-95a5-374baf5e8fba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665846195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3665846195
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3856024325
Short name T283
Test name
Test status
Simulation time 284677199560 ps
CPU time 442.17 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:49:26 PM PDT 24
Peak memory 193120 kb
Host smart-1d4a47be-a1cf-4b2c-bee2-fbc38a8fe8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856024325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3856024325
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.542241689
Short name T290
Test name
Test status
Simulation time 576396465102 ps
CPU time 309.69 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:47:14 PM PDT 24
Peak memory 191172 kb
Host smart-6092465f-22fb-4632-adf2-174fab544551
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542241689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.542241689
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1434445043
Short name T239
Test name
Test status
Simulation time 56090179320 ps
CPU time 87.92 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 04:43:33 PM PDT 24
Peak memory 191132 kb
Host smart-f247c0f2-0efa-40ed-a1a0-c0c5916a2f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434445043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1434445043
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.191227642
Short name T246
Test name
Test status
Simulation time 25508845033 ps
CPU time 36.7 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:42:41 PM PDT 24
Peak memory 182880 kb
Host smart-35bc8a21-3b9c-4f46-99ae-449685cce0ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191227642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.191227642
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.732359209
Short name T355
Test name
Test status
Simulation time 324801041433 ps
CPU time 125.02 seconds
Started Jun 22 04:42:02 PM PDT 24
Finished Jun 22 04:44:07 PM PDT 24
Peak memory 191180 kb
Host smart-e6d5a5dc-3702-4078-999c-85c1bc55becd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732359209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.732359209
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1157742483
Short name T287
Test name
Test status
Simulation time 77375332953 ps
CPU time 68.8 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:43:13 PM PDT 24
Peak memory 182880 kb
Host smart-1b6642b4-82fa-403d-9e7d-33398edde3a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157742483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1157742483
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3231705737
Short name T329
Test name
Test status
Simulation time 317826375384 ps
CPU time 146.96 seconds
Started Jun 22 04:42:01 PM PDT 24
Finished Jun 22 04:44:28 PM PDT 24
Peak memory 191320 kb
Host smart-dceb3694-088e-4386-b300-f99448007b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231705737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3231705737
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1152083656
Short name T142
Test name
Test status
Simulation time 187781883342 ps
CPU time 104.8 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:43:49 PM PDT 24
Peak memory 182976 kb
Host smart-c7c6176a-1846-4d78-aa66-d45a4a8e7be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152083656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1152083656
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1261376774
Short name T298
Test name
Test status
Simulation time 30576968016 ps
CPU time 14.86 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:41:33 PM PDT 24
Peak memory 182988 kb
Host smart-d194c70b-d346-49f2-bf90-ab76b144ddd2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261376774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1261376774
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.51761298
Short name T397
Test name
Test status
Simulation time 69154807024 ps
CPU time 110.56 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:43:07 PM PDT 24
Peak memory 182912 kb
Host smart-d4ee37bb-928d-48db-9e7a-a01bc2d105b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51761298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.51761298
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2868021309
Short name T196
Test name
Test status
Simulation time 290862301067 ps
CPU time 527.31 seconds
Started Jun 22 04:41:18 PM PDT 24
Finished Jun 22 04:50:09 PM PDT 24
Peak memory 194560 kb
Host smart-1d884bd8-c62a-44d7-aab9-5a3b0a00a7b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868021309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2868021309
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1514668978
Short name T126
Test name
Test status
Simulation time 208154787608 ps
CPU time 43.45 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:42:01 PM PDT 24
Peak memory 182908 kb
Host smart-1c6f7f4a-df69-403f-bf7a-dd9891e1e501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514668978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1514668978
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.320003272
Short name T62
Test name
Test status
Simulation time 153727264983 ps
CPU time 220.39 seconds
Started Jun 22 04:41:15 PM PDT 24
Finished Jun 22 04:44:58 PM PDT 24
Peak memory 191188 kb
Host smart-9fa06f26-5546-49e2-96c7-b590541fefd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320003272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.320003272
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.3090139902
Short name T420
Test name
Test status
Simulation time 23145097929 ps
CPU time 42.69 seconds
Started Jun 22 04:42:01 PM PDT 24
Finished Jun 22 04:42:44 PM PDT 24
Peak memory 183200 kb
Host smart-ffdea994-2678-4963-a868-92938c278d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090139902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3090139902
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3194307535
Short name T432
Test name
Test status
Simulation time 274879376647 ps
CPU time 1512.8 seconds
Started Jun 22 04:42:04 PM PDT 24
Finished Jun 22 05:07:18 PM PDT 24
Peak memory 193556 kb
Host smart-86831a5e-8052-4131-94ae-87ab22ef2f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194307535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3194307535
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3669595557
Short name T170
Test name
Test status
Simulation time 133988865127 ps
CPU time 1606.15 seconds
Started Jun 22 04:42:01 PM PDT 24
Finished Jun 22 05:08:48 PM PDT 24
Peak memory 182912 kb
Host smart-bf4972ad-b7d0-45c2-bada-64f0d0e5404b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669595557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3669595557
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2867354024
Short name T190
Test name
Test status
Simulation time 178320550200 ps
CPU time 579.32 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:51:46 PM PDT 24
Peak memory 191132 kb
Host smart-6e26502b-db0b-4bfb-a05f-707ae03f5d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867354024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2867354024
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1865765240
Short name T203
Test name
Test status
Simulation time 479504189794 ps
CPU time 316.47 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:47:21 PM PDT 24
Peak memory 191100 kb
Host smart-480dd9d5-ddc3-4fda-be43-cd91771d3d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865765240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1865765240
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1739005787
Short name T9
Test name
Test status
Simulation time 42626270142 ps
CPU time 327.52 seconds
Started Jun 22 04:42:06 PM PDT 24
Finished Jun 22 04:47:34 PM PDT 24
Peak memory 182880 kb
Host smart-5f7373a8-19a5-4548-ae37-d544d348c8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739005787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1739005787
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3016312974
Short name T103
Test name
Test status
Simulation time 393968168979 ps
CPU time 264.69 seconds
Started Jun 22 04:42:03 PM PDT 24
Finished Jun 22 04:46:30 PM PDT 24
Peak memory 191116 kb
Host smart-33920f96-33c6-4704-8341-6811eef30fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016312974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3016312974
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1900475800
Short name T208
Test name
Test status
Simulation time 852521346676 ps
CPU time 723.01 seconds
Started Jun 22 04:42:05 PM PDT 24
Finished Jun 22 04:54:10 PM PDT 24
Peak memory 191176 kb
Host smart-447dc315-6c1a-4bf0-a7f1-af0651cf3743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900475800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1900475800
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1142041714
Short name T343
Test name
Test status
Simulation time 28701672790 ps
CPU time 71.33 seconds
Started Jun 22 04:42:08 PM PDT 24
Finished Jun 22 04:43:20 PM PDT 24
Peak memory 182880 kb
Host smart-2a287834-e516-4727-ac8d-8a4762555f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142041714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1142041714
Directory /workspace/98.rv_timer_random/latest
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