Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.51 99.36 98.73 100.00 100.00 100.00 98.98


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2446760264 Jun 23 06:15:31 PM PDT 24 Jun 23 06:15:33 PM PDT 24 28898346 ps
T507 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3533141259 Jun 23 06:15:42 PM PDT 24 Jun 23 06:15:43 PM PDT 24 17467182 ps
T508 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2289946851 Jun 23 06:15:55 PM PDT 24 Jun 23 06:15:56 PM PDT 24 133119319 ps
T509 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.150263571 Jun 23 06:15:20 PM PDT 24 Jun 23 06:15:22 PM PDT 24 1325827070 ps
T510 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2022665912 Jun 23 06:16:01 PM PDT 24 Jun 23 06:16:02 PM PDT 24 37393960 ps
T511 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3451967869 Jun 23 06:15:55 PM PDT 24 Jun 23 06:15:56 PM PDT 24 43072568 ps
T512 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1166701080 Jun 23 06:15:36 PM PDT 24 Jun 23 06:15:37 PM PDT 24 115155842 ps
T513 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2515245262 Jun 23 06:15:41 PM PDT 24 Jun 23 06:15:44 PM PDT 24 500288769 ps
T514 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1769967373 Jun 23 06:15:37 PM PDT 24 Jun 23 06:15:39 PM PDT 24 51039100 ps
T515 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2146219169 Jun 23 06:15:23 PM PDT 24 Jun 23 06:15:24 PM PDT 24 17278445 ps
T516 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4287648892 Jun 23 06:15:39 PM PDT 24 Jun 23 06:15:42 PM PDT 24 1199953583 ps
T517 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3633782027 Jun 23 06:15:47 PM PDT 24 Jun 23 06:15:48 PM PDT 24 24012024 ps
T518 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4039059431 Jun 23 06:15:49 PM PDT 24 Jun 23 06:15:51 PM PDT 24 114920405 ps
T519 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.885848038 Jun 23 06:15:41 PM PDT 24 Jun 23 06:15:43 PM PDT 24 116269482 ps
T520 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2401464370 Jun 23 06:15:55 PM PDT 24 Jun 23 06:15:56 PM PDT 24 16808445 ps
T521 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.190568408 Jun 23 06:15:51 PM PDT 24 Jun 23 06:15:52 PM PDT 24 88086195 ps
T522 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1524489905 Jun 23 06:15:38 PM PDT 24 Jun 23 06:15:39 PM PDT 24 14610876 ps
T74 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.638300892 Jun 23 06:15:24 PM PDT 24 Jun 23 06:15:26 PM PDT 24 127373454 ps
T523 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4197372273 Jun 23 06:15:56 PM PDT 24 Jun 23 06:15:57 PM PDT 24 39861158 ps
T524 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2913124301 Jun 23 06:16:02 PM PDT 24 Jun 23 06:16:03 PM PDT 24 14985106 ps
T525 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3447908061 Jun 23 06:15:52 PM PDT 24 Jun 23 06:15:55 PM PDT 24 716069770 ps
T75 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1357860137 Jun 23 06:15:32 PM PDT 24 Jun 23 06:15:33 PM PDT 24 12973322 ps
T526 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3027079408 Jun 23 06:15:47 PM PDT 24 Jun 23 06:15:48 PM PDT 24 20123268 ps
T527 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3108503413 Jun 23 06:15:49 PM PDT 24 Jun 23 06:15:50 PM PDT 24 121473449 ps
T528 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3634270337 Jun 23 06:15:50 PM PDT 24 Jun 23 06:15:51 PM PDT 24 13073083 ps
T529 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.565561606 Jun 23 06:15:39 PM PDT 24 Jun 23 06:15:40 PM PDT 24 52187370 ps
T530 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4067969039 Jun 23 06:15:50 PM PDT 24 Jun 23 06:15:51 PM PDT 24 40079747 ps
T531 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3705978152 Jun 23 06:15:44 PM PDT 24 Jun 23 06:15:45 PM PDT 24 99204852 ps
T532 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.942522313 Jun 23 06:15:40 PM PDT 24 Jun 23 06:15:41 PM PDT 24 80718409 ps
T533 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3548890615 Jun 23 06:15:39 PM PDT 24 Jun 23 06:15:41 PM PDT 24 17737588 ps
T534 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2356324992 Jun 23 06:15:38 PM PDT 24 Jun 23 06:15:40 PM PDT 24 207158827 ps
T535 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4122520525 Jun 23 06:15:54 PM PDT 24 Jun 23 06:15:55 PM PDT 24 14812143 ps
T536 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3445708306 Jun 23 06:15:23 PM PDT 24 Jun 23 06:15:25 PM PDT 24 130489062 ps
T537 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2454122204 Jun 23 06:15:51 PM PDT 24 Jun 23 06:15:53 PM PDT 24 97540219 ps
T538 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1827637433 Jun 23 06:15:55 PM PDT 24 Jun 23 06:15:56 PM PDT 24 15187041 ps
T539 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2099195013 Jun 23 06:15:39 PM PDT 24 Jun 23 06:15:41 PM PDT 24 91699280 ps
T540 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4060572106 Jun 23 06:15:42 PM PDT 24 Jun 23 06:15:43 PM PDT 24 21055179 ps
T541 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1103030990 Jun 23 06:15:36 PM PDT 24 Jun 23 06:15:37 PM PDT 24 62122240 ps
T542 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.751953045 Jun 23 06:15:41 PM PDT 24 Jun 23 06:15:43 PM PDT 24 299760163 ps
T543 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3020202405 Jun 23 06:15:27 PM PDT 24 Jun 23 06:15:28 PM PDT 24 34363597 ps
T544 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.974225359 Jun 23 06:15:35 PM PDT 24 Jun 23 06:15:37 PM PDT 24 273560397 ps
T545 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.4161663386 Jun 23 06:15:56 PM PDT 24 Jun 23 06:15:57 PM PDT 24 26987918 ps
T76 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.71943589 Jun 23 06:15:47 PM PDT 24 Jun 23 06:15:48 PM PDT 24 59345923 ps
T546 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1419185630 Jun 23 06:15:55 PM PDT 24 Jun 23 06:15:56 PM PDT 24 172119303 ps
T547 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1098174993 Jun 23 06:15:54 PM PDT 24 Jun 23 06:15:55 PM PDT 24 48178159 ps
T548 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3205599639 Jun 23 06:15:22 PM PDT 24 Jun 23 06:15:24 PM PDT 24 451767592 ps
T549 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1493118364 Jun 23 06:15:36 PM PDT 24 Jun 23 06:15:37 PM PDT 24 22091086 ps
T550 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1836637021 Jun 23 06:15:22 PM PDT 24 Jun 23 06:15:23 PM PDT 24 391461681 ps
T77 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3166705949 Jun 23 06:15:53 PM PDT 24 Jun 23 06:15:54 PM PDT 24 13960875 ps
T551 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.603613542 Jun 23 06:15:39 PM PDT 24 Jun 23 06:15:41 PM PDT 24 24114066 ps
T552 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.156771318 Jun 23 06:15:43 PM PDT 24 Jun 23 06:15:44 PM PDT 24 37451929 ps
T553 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.71436456 Jun 23 06:15:55 PM PDT 24 Jun 23 06:15:56 PM PDT 24 26037574 ps
T554 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.785249272 Jun 23 06:15:44 PM PDT 24 Jun 23 06:15:45 PM PDT 24 71206726 ps
T555 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.727832013 Jun 23 06:15:41 PM PDT 24 Jun 23 06:15:44 PM PDT 24 119632477 ps
T556 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3838248381 Jun 23 06:15:42 PM PDT 24 Jun 23 06:15:44 PM PDT 24 190206326 ps
T557 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1356722359 Jun 23 06:15:42 PM PDT 24 Jun 23 06:15:43 PM PDT 24 16111761 ps
T558 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3076370730 Jun 23 06:15:55 PM PDT 24 Jun 23 06:15:56 PM PDT 24 141272914 ps
T559 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3267997378 Jun 23 06:15:45 PM PDT 24 Jun 23 06:15:46 PM PDT 24 86477478 ps
T560 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.951256058 Jun 23 06:15:29 PM PDT 24 Jun 23 06:15:31 PM PDT 24 17128754 ps
T561 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.91501065 Jun 23 06:15:47 PM PDT 24 Jun 23 06:15:48 PM PDT 24 40791040 ps
T562 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2020065189 Jun 23 06:15:44 PM PDT 24 Jun 23 06:15:46 PM PDT 24 362657578 ps
T563 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1952455310 Jun 23 06:15:50 PM PDT 24 Jun 23 06:15:53 PM PDT 24 207109386 ps
T564 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1496209617 Jun 23 06:15:53 PM PDT 24 Jun 23 06:15:54 PM PDT 24 10735768 ps
T565 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2049719620 Jun 23 06:15:45 PM PDT 24 Jun 23 06:15:47 PM PDT 24 100362112 ps
T566 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3124639473 Jun 23 06:15:28 PM PDT 24 Jun 23 06:15:29 PM PDT 24 71188127 ps
T567 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1407373923 Jun 23 06:16:01 PM PDT 24 Jun 23 06:16:02 PM PDT 24 97972100 ps
T568 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.113801109 Jun 23 06:15:56 PM PDT 24 Jun 23 06:15:57 PM PDT 24 16218106 ps
T569 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3895263629 Jun 23 06:15:59 PM PDT 24 Jun 23 06:16:00 PM PDT 24 12808836 ps
T570 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3522584896 Jun 23 06:15:42 PM PDT 24 Jun 23 06:15:44 PM PDT 24 120679653 ps
T571 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4017207897 Jun 23 06:15:37 PM PDT 24 Jun 23 06:15:39 PM PDT 24 83946883 ps
T78 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2373254054 Jun 23 06:15:24 PM PDT 24 Jun 23 06:15:25 PM PDT 24 31118744 ps
T572 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2054235690 Jun 23 06:15:25 PM PDT 24 Jun 23 06:15:26 PM PDT 24 19254160 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3352712308 Jun 23 06:15:23 PM PDT 24 Jun 23 06:15:24 PM PDT 24 56717719 ps
T574 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.839068020 Jun 23 06:15:35 PM PDT 24 Jun 23 06:15:37 PM PDT 24 23723192 ps
T575 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1451794385 Jun 23 06:15:56 PM PDT 24 Jun 23 06:15:57 PM PDT 24 64736226 ps
T576 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3873515689 Jun 23 06:15:43 PM PDT 24 Jun 23 06:15:45 PM PDT 24 43639203 ps
T577 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1074860241 Jun 23 06:15:29 PM PDT 24 Jun 23 06:15:32 PM PDT 24 174597463 ps
T578 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4054520470 Jun 23 06:15:21 PM PDT 24 Jun 23 06:15:22 PM PDT 24 252743363 ps
T579 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3806480407 Jun 23 06:15:25 PM PDT 24 Jun 23 06:15:27 PM PDT 24 397580937 ps
T580 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2663427065 Jun 23 06:15:45 PM PDT 24 Jun 23 06:15:46 PM PDT 24 26297684 ps
T581 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3433720813 Jun 23 06:15:49 PM PDT 24 Jun 23 06:15:50 PM PDT 24 52449640 ps

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3095526495
Short name T4
Test name
Test status
Simulation time 463443561656 ps
CPU time 515.67 seconds
Started Jun 23 05:29:57 PM PDT 24
Finished Jun 23 05:38:33 PM PDT 24
Peak memory 210368 kb
Host smart-a949b21c-2b0a-40d9-80f1-21473bbf9c86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095526495 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3095526495
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1593661271
Short name T8
Test name
Test status
Simulation time 3181357201751 ps
CPU time 2038.3 seconds
Started Jun 23 05:30:12 PM PDT 24
Finished Jun 23 06:04:11 PM PDT 24
Peak memory 191088 kb
Host smart-45a84940-e4d0-4307-aaba-9439bde6c2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593661271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1593661271
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4178842822
Short name T95
Test name
Test status
Simulation time 796080301866 ps
CPU time 2250.19 seconds
Started Jun 23 05:30:07 PM PDT 24
Finished Jun 23 06:07:37 PM PDT 24
Peak memory 191176 kb
Host smart-e43f74c5-35e7-4f41-b144-0433eb643d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178842822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4178842822
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3967503543
Short name T25
Test name
Test status
Simulation time 81333092 ps
CPU time 1.09 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 195048 kb
Host smart-b06271ad-7efa-4f3e-9e46-c5b373d554d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967503543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3967503543
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.798464570
Short name T141
Test name
Test status
Simulation time 548498218450 ps
CPU time 2214.84 seconds
Started Jun 23 05:30:20 PM PDT 24
Finished Jun 23 06:07:15 PM PDT 24
Peak memory 191192 kb
Host smart-e8036016-9e06-4692-b778-80298f40b2f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798464570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
798464570
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3432443172
Short name T66
Test name
Test status
Simulation time 521224348054 ps
CPU time 1262.75 seconds
Started Jun 23 05:29:54 PM PDT 24
Finished Jun 23 05:50:58 PM PDT 24
Peak memory 191176 kb
Host smart-95355a4b-badd-430b-bc3e-5e098a27b544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432443172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3432443172
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.914696659
Short name T42
Test name
Test status
Simulation time 147345938 ps
CPU time 0.62 seconds
Started Jun 23 06:15:34 PM PDT 24
Finished Jun 23 06:15:35 PM PDT 24
Peak memory 182716 kb
Host smart-59e4ada6-3c38-45a8-96bc-49efa7024b77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914696659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.914696659
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1136499350
Short name T92
Test name
Test status
Simulation time 918775464226 ps
CPU time 2656.24 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 06:14:30 PM PDT 24
Peak memory 191188 kb
Host smart-36f3b94d-163a-4a29-a215-578c4e04ef2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136499350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1136499350
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1648508275
Short name T202
Test name
Test status
Simulation time 2594935267427 ps
CPU time 1703.97 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:58:29 PM PDT 24
Peak memory 195636 kb
Host smart-95741078-7e3f-4fde-aa8b-b9d281c46e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648508275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1648508275
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2654605607
Short name T156
Test name
Test status
Simulation time 1537042464145 ps
CPU time 1303.75 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:52:03 PM PDT 24
Peak memory 191092 kb
Host smart-3c4ae1e0-5ffb-45ab-9458-dab06271e4a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654605607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2654605607
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2654555803
Short name T226
Test name
Test status
Simulation time 2084069379957 ps
CPU time 1047.58 seconds
Started Jun 23 05:30:39 PM PDT 24
Finished Jun 23 05:48:07 PM PDT 24
Peak memory 195276 kb
Host smart-8b405627-e905-434e-a597-94074fe7de9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654555803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2654555803
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1352355266
Short name T13
Test name
Test status
Simulation time 239710855 ps
CPU time 0.88 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:30:04 PM PDT 24
Peak memory 213192 kb
Host smart-c429956f-bf5b-4231-baeb-4598518ca44d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352355266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1352355266
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1187593070
Short name T62
Test name
Test status
Simulation time 3716918414404 ps
CPU time 1661.44 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:57:48 PM PDT 24
Peak memory 191200 kb
Host smart-895a229b-af52-480e-afc4-fd550df3015f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187593070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1187593070
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3118985258
Short name T223
Test name
Test status
Simulation time 673483059539 ps
CPU time 702.66 seconds
Started Jun 23 05:29:59 PM PDT 24
Finished Jun 23 05:41:42 PM PDT 24
Peak memory 191184 kb
Host smart-c525a77f-9749-47b0-be4d-4fc393cba114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118985258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3118985258
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3484179431
Short name T181
Test name
Test status
Simulation time 1942458470986 ps
CPU time 2554.8 seconds
Started Jun 23 05:29:58 PM PDT 24
Finished Jun 23 06:12:34 PM PDT 24
Peak memory 191140 kb
Host smart-cb2f253f-0894-4c51-860f-2a28bc2ff197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484179431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3484179431
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_random.4039991985
Short name T22
Test name
Test status
Simulation time 202792786844 ps
CPU time 341.13 seconds
Started Jun 23 05:30:39 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 191196 kb
Host smart-5091c907-b41e-4c52-975d-7ad42a447a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039991985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.4039991985
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3549670665
Short name T20
Test name
Test status
Simulation time 1061350556058 ps
CPU time 517.95 seconds
Started Jun 23 05:31:33 PM PDT 24
Finished Jun 23 05:40:11 PM PDT 24
Peak memory 191192 kb
Host smart-0b969267-6afc-4ca4-b349-861083125d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549670665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3549670665
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.2159346169
Short name T113
Test name
Test status
Simulation time 1268827551993 ps
CPU time 430.94 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:37:14 PM PDT 24
Peak memory 191044 kb
Host smart-ead11194-daf1-4081-a81d-f7733fbc3df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159346169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2159346169
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.37276238
Short name T184
Test name
Test status
Simulation time 119522729798 ps
CPU time 417.96 seconds
Started Jun 23 05:30:44 PM PDT 24
Finished Jun 23 05:37:42 PM PDT 24
Peak memory 191188 kb
Host smart-d6d526a6-c194-4ea2-919e-5caecfec6c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37276238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.37276238
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.4072517425
Short name T254
Test name
Test status
Simulation time 670202442222 ps
CPU time 1673.43 seconds
Started Jun 23 05:31:53 PM PDT 24
Finished Jun 23 05:59:47 PM PDT 24
Peak memory 191184 kb
Host smart-70175151-93df-437b-8a88-691b97709065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072517425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4072517425
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.58356896
Short name T186
Test name
Test status
Simulation time 122474321109 ps
CPU time 205.97 seconds
Started Jun 23 05:32:14 PM PDT 24
Finished Jun 23 05:35:40 PM PDT 24
Peak memory 191176 kb
Host smart-653e4c14-76d7-4d22-85c2-33ecd4a6d93b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58356896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.58356896
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3247328224
Short name T262
Test name
Test status
Simulation time 260364575149 ps
CPU time 487.47 seconds
Started Jun 23 05:30:45 PM PDT 24
Finished Jun 23 05:38:53 PM PDT 24
Peak memory 191196 kb
Host smart-1d219976-bb88-4992-9b6a-4df598c4d823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247328224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3247328224
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2072981315
Short name T24
Test name
Test status
Simulation time 906677643659 ps
CPU time 876.43 seconds
Started Jun 23 05:31:16 PM PDT 24
Finished Jun 23 05:45:53 PM PDT 24
Peak memory 191184 kb
Host smart-30f6747b-2757-48f4-bd5e-de12a1dc978f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072981315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2072981315
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2866784659
Short name T167
Test name
Test status
Simulation time 528639614404 ps
CPU time 293.76 seconds
Started Jun 23 05:32:16 PM PDT 24
Finished Jun 23 05:37:10 PM PDT 24
Peak memory 193520 kb
Host smart-d6d861bd-bdb1-45c8-a33d-4ff73ce7f697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866784659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2866784659
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3000919972
Short name T60
Test name
Test status
Simulation time 515513057402 ps
CPU time 826.43 seconds
Started Jun 23 05:30:29 PM PDT 24
Finished Jun 23 05:44:16 PM PDT 24
Peak memory 191244 kb
Host smart-638eefb1-ec5b-4d49-ae43-13b62543362e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000919972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3000919972
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.3976941268
Short name T288
Test name
Test status
Simulation time 264297965652 ps
CPU time 253.57 seconds
Started Jun 23 05:30:48 PM PDT 24
Finished Jun 23 05:35:02 PM PDT 24
Peak memory 191180 kb
Host smart-518c8c0f-ff49-464b-a916-f1ae0995463a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976941268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3976941268
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.2357624672
Short name T240
Test name
Test status
Simulation time 198048003449 ps
CPU time 596.51 seconds
Started Jun 23 05:29:46 PM PDT 24
Finished Jun 23 05:39:43 PM PDT 24
Peak memory 191176 kb
Host smart-7837051f-a205-4fdd-b9ce-4183317e6cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357624672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2357624672
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1529464304
Short name T206
Test name
Test status
Simulation time 648976950974 ps
CPU time 296.68 seconds
Started Jun 23 05:31:22 PM PDT 24
Finished Jun 23 05:36:19 PM PDT 24
Peak memory 191184 kb
Host smart-8734d743-dcc4-465f-92a6-15e26dbe56bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529464304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1529464304
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1581130003
Short name T163
Test name
Test status
Simulation time 530494426968 ps
CPU time 391.98 seconds
Started Jun 23 05:31:41 PM PDT 24
Finished Jun 23 05:38:13 PM PDT 24
Peak memory 191180 kb
Host smart-b6146663-430f-47ee-8eaa-274793957b0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581130003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1581130003
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2173487476
Short name T278
Test name
Test status
Simulation time 185485724572 ps
CPU time 641.03 seconds
Started Jun 23 05:30:09 PM PDT 24
Finished Jun 23 05:40:50 PM PDT 24
Peak memory 195356 kb
Host smart-eccb1da3-e68d-4ee7-ba64-f82d2f325d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173487476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2173487476
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.2344361065
Short name T147
Test name
Test status
Simulation time 111360009810 ps
CPU time 208.92 seconds
Started Jun 23 05:31:15 PM PDT 24
Finished Jun 23 05:34:44 PM PDT 24
Peak memory 191176 kb
Host smart-df8d0729-7754-4026-a5d3-766a71bc769b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344361065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2344361065
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3243104931
Short name T166
Test name
Test status
Simulation time 466075876389 ps
CPU time 229.32 seconds
Started Jun 23 05:31:22 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 191176 kb
Host smart-98ba3b43-1882-4ffc-bfe0-44c44d34a910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243104931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3243104931
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3877178825
Short name T18
Test name
Test status
Simulation time 91042094811 ps
CPU time 138.96 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:32:24 PM PDT 24
Peak memory 183000 kb
Host smart-a7600956-6639-42ef-9438-be871c9280d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877178825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3877178825
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random.3537250808
Short name T318
Test name
Test status
Simulation time 718368920476 ps
CPU time 733.17 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:42:31 PM PDT 24
Peak memory 191180 kb
Host smart-324a53a2-09f9-434d-b910-83e24a955b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537250808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3537250808
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3607350266
Short name T266
Test name
Test status
Simulation time 195451304252 ps
CPU time 966.82 seconds
Started Jun 23 05:30:56 PM PDT 24
Finished Jun 23 05:47:03 PM PDT 24
Peak memory 191044 kb
Host smart-5a7bb4f8-e7b4-421a-9465-854059ad428c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607350266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3607350266
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2210563989
Short name T143
Test name
Test status
Simulation time 155507106925 ps
CPU time 277.78 seconds
Started Jun 23 05:30:56 PM PDT 24
Finished Jun 23 05:35:34 PM PDT 24
Peak memory 191188 kb
Host smart-ae863fc1-ea98-4294-823e-adc4449fa789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210563989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2210563989
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1275706335
Short name T161
Test name
Test status
Simulation time 642247491463 ps
CPU time 408.06 seconds
Started Jun 23 05:31:11 PM PDT 24
Finished Jun 23 05:37:59 PM PDT 24
Peak memory 191144 kb
Host smart-3bb47041-f6ab-45a3-b282-4f14be7dd886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275706335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1275706335
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3090953957
Short name T175
Test name
Test status
Simulation time 225060798099 ps
CPU time 404.3 seconds
Started Jun 23 05:29:54 PM PDT 24
Finished Jun 23 05:36:40 PM PDT 24
Peak memory 191204 kb
Host smart-134e9b6c-7fd0-4706-9590-13ef183f8d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090953957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3090953957
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_random.648119216
Short name T177
Test name
Test status
Simulation time 163811763292 ps
CPU time 641.08 seconds
Started Jun 23 05:29:57 PM PDT 24
Finished Jun 23 05:40:38 PM PDT 24
Peak memory 190468 kb
Host smart-6b2dea00-5e11-4e2a-88f8-8589fcf866fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648119216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.648119216
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3259592818
Short name T210
Test name
Test status
Simulation time 412636623068 ps
CPU time 332.47 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:35:47 PM PDT 24
Peak memory 191064 kb
Host smart-32d16e83-137c-421b-af0b-2c66b7a0b9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259592818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3259592818
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/194.rv_timer_random.2594840637
Short name T152
Test name
Test status
Simulation time 94129205647 ps
CPU time 145.85 seconds
Started Jun 23 05:32:21 PM PDT 24
Finished Jun 23 05:34:47 PM PDT 24
Peak memory 193640 kb
Host smart-96810656-bbfb-4702-9de7-2b9e66768d34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594840637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2594840637
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3078042758
Short name T190
Test name
Test status
Simulation time 124386872299 ps
CPU time 202.91 seconds
Started Jun 23 05:32:23 PM PDT 24
Finished Jun 23 05:35:46 PM PDT 24
Peak memory 191184 kb
Host smart-0aa9c1f3-aa32-40c3-bd20-69645155b8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078042758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3078042758
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3574899280
Short name T212
Test name
Test status
Simulation time 314759931356 ps
CPU time 272.71 seconds
Started Jun 23 05:31:13 PM PDT 24
Finished Jun 23 05:35:46 PM PDT 24
Peak memory 191076 kb
Host smart-3f63978b-f24e-4a59-9259-63742b102b44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574899280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3574899280
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.487682031
Short name T137
Test name
Test status
Simulation time 466792218253 ps
CPU time 262.49 seconds
Started Jun 23 05:31:16 PM PDT 24
Finished Jun 23 05:35:39 PM PDT 24
Peak memory 191172 kb
Host smart-42bbe4c6-a45f-427b-a1bd-6448cb661bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487682031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.487682031
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.4131747789
Short name T235
Test name
Test status
Simulation time 15811754971 ps
CPU time 100.56 seconds
Started Jun 23 05:31:20 PM PDT 24
Finished Jun 23 05:33:01 PM PDT 24
Peak memory 182876 kb
Host smart-6d20f6c6-911f-442e-b9ae-ab4bcb46c6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131747789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.4131747789
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2608891613
Short name T321
Test name
Test status
Simulation time 458022839962 ps
CPU time 2994.18 seconds
Started Jun 23 05:31:21 PM PDT 24
Finished Jun 23 06:21:16 PM PDT 24
Peak memory 191192 kb
Host smart-e20ccf72-324b-4447-a4f4-0b73ee952156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608891613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2608891613
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4206978045
Short name T309
Test name
Test status
Simulation time 1247387413199 ps
CPU time 646.95 seconds
Started Jun 23 05:29:55 PM PDT 24
Finished Jun 23 05:40:43 PM PDT 24
Peak memory 182904 kb
Host smart-7b5d407f-0698-4e29-b309-b4fa54055a2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206978045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.4206978045
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/187.rv_timer_random.313964256
Short name T249
Test name
Test status
Simulation time 766644288268 ps
CPU time 151.49 seconds
Started Jun 23 05:32:15 PM PDT 24
Finished Jun 23 05:34:46 PM PDT 24
Peak memory 193384 kb
Host smart-7d1a2fcf-e422-450f-ab1f-670855052a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313964256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.313964256
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.870040336
Short name T236
Test name
Test status
Simulation time 697443148447 ps
CPU time 1236.36 seconds
Started Jun 23 05:29:52 PM PDT 24
Finished Jun 23 05:50:29 PM PDT 24
Peak memory 191216 kb
Host smart-dbb99dbd-266e-43b6-96fd-f95a74f58880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870040336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.870040336
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1018589064
Short name T248
Test name
Test status
Simulation time 3525101090532 ps
CPU time 741.63 seconds
Started Jun 23 05:29:58 PM PDT 24
Finished Jun 23 05:42:20 PM PDT 24
Peak memory 191188 kb
Host smart-45eaf248-76e2-4605-8194-3a05f01780af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018589064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1018589064
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2069937542
Short name T307
Test name
Test status
Simulation time 126513692669 ps
CPU time 153.08 seconds
Started Jun 23 05:30:01 PM PDT 24
Finished Jun 23 05:32:34 PM PDT 24
Peak memory 182968 kb
Host smart-0718f4e6-fd75-4411-9d18-8feb36752b83
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069937542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2069937542
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3171046273
Short name T59
Test name
Test status
Simulation time 1155565416239 ps
CPU time 288.42 seconds
Started Jun 23 05:30:12 PM PDT 24
Finished Jun 23 05:35:02 PM PDT 24
Peak memory 191040 kb
Host smart-7d34ada0-14ef-4d64-bad9-16138e9906fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171046273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3171046273
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.151619330
Short name T349
Test name
Test status
Simulation time 117836434588 ps
CPU time 790.04 seconds
Started Jun 23 05:30:31 PM PDT 24
Finished Jun 23 05:43:41 PM PDT 24
Peak memory 208864 kb
Host smart-ea7967e6-ebab-4603-ba29-bad79becaa2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151619330 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.151619330
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4187396833
Short name T71
Test name
Test status
Simulation time 90950488 ps
CPU time 0.78 seconds
Started Jun 23 06:15:21 PM PDT 24
Finished Jun 23 06:15:23 PM PDT 24
Peak memory 191740 kb
Host smart-fbbcd99f-9f6e-4162-9a79-89b641e252ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187396833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4187396833
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1724519653
Short name T219
Test name
Test status
Simulation time 19561511835 ps
CPU time 27.22 seconds
Started Jun 23 05:30:09 PM PDT 24
Finished Jun 23 05:30:37 PM PDT 24
Peak memory 195048 kb
Host smart-d92e8f88-0e58-4242-a048-575dc1a2bdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724519653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1724519653
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/103.rv_timer_random.1574076286
Short name T331
Test name
Test status
Simulation time 150246224956 ps
CPU time 253.09 seconds
Started Jun 23 05:31:11 PM PDT 24
Finished Jun 23 05:35:25 PM PDT 24
Peak memory 182964 kb
Host smart-96addafb-7f2f-47f0-837c-a5fc9d5522b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574076286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1574076286
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.4087307628
Short name T139
Test name
Test status
Simulation time 1886402050670 ps
CPU time 1012.37 seconds
Started Jun 23 05:29:54 PM PDT 24
Finished Jun 23 05:46:47 PM PDT 24
Peak memory 182968 kb
Host smart-7b2fcd53-f0fa-41b4-9053-4a49227677eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087307628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.4087307628
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/141.rv_timer_random.911841318
Short name T164
Test name
Test status
Simulation time 463143240818 ps
CPU time 273.58 seconds
Started Jun 23 05:31:42 PM PDT 24
Finished Jun 23 05:36:16 PM PDT 24
Peak memory 191196 kb
Host smart-06ae2e8a-9865-4c73-9427-82fa52332ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911841318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.911841318
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2784130780
Short name T196
Test name
Test status
Simulation time 59145734353 ps
CPU time 104.69 seconds
Started Jun 23 05:31:44 PM PDT 24
Finished Jun 23 05:33:29 PM PDT 24
Peak memory 191184 kb
Host smart-c972d444-4567-40cb-97d0-e5064f677170
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784130780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2784130780
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.2858690229
Short name T142
Test name
Test status
Simulation time 579861092845 ps
CPU time 473.7 seconds
Started Jun 23 05:31:49 PM PDT 24
Finished Jun 23 05:39:43 PM PDT 24
Peak memory 191172 kb
Host smart-fc20ee45-2fe6-49ba-9219-df4e6a0248ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858690229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2858690229
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.661636805
Short name T221
Test name
Test status
Simulation time 510507356596 ps
CPU time 259.22 seconds
Started Jun 23 05:32:01 PM PDT 24
Finished Jun 23 05:36:21 PM PDT 24
Peak memory 194732 kb
Host smart-c9a5f8bb-f2c3-4a4d-9a10-006ad3173e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661636805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.661636805
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2865860923
Short name T314
Test name
Test status
Simulation time 29495764806 ps
CPU time 50.63 seconds
Started Jun 23 05:32:01 PM PDT 24
Finished Jun 23 05:32:52 PM PDT 24
Peak memory 191176 kb
Host smart-91b89761-0166-49a8-ab80-703eed52c28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865860923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2865860923
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3436360067
Short name T172
Test name
Test status
Simulation time 161726067733 ps
CPU time 299.44 seconds
Started Jun 23 05:32:19 PM PDT 24
Finished Jun 23 05:37:19 PM PDT 24
Peak memory 191184 kb
Host smart-467e574a-c269-4bb8-a192-a9c52a87018f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436360067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3436360067
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2061958992
Short name T6
Test name
Test status
Simulation time 1032952217676 ps
CPU time 378.56 seconds
Started Jun 23 05:30:05 PM PDT 24
Finished Jun 23 05:36:25 PM PDT 24
Peak memory 191200 kb
Host smart-ba1715c3-df26-4e7d-989c-8c93c6c2ea15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061958992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2061958992
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.883629149
Short name T154
Test name
Test status
Simulation time 177518046352 ps
CPU time 1721.1 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:58:46 PM PDT 24
Peak memory 214068 kb
Host smart-d0d2645a-cf7d-4b64-bff1-f57fd077ca62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883629149 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.883629149
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.79903643
Short name T195
Test name
Test status
Simulation time 11005787960 ps
CPU time 17.18 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:30:22 PM PDT 24
Peak memory 182976 kb
Host smart-0cc82ee5-2fe9-4c47-a65a-eb6fda53a2ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79903643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.rv_timer_cfg_update_on_fly.79903643
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random.2356559601
Short name T159
Test name
Test status
Simulation time 44140590021 ps
CPU time 66.8 seconds
Started Jun 23 05:30:07 PM PDT 24
Finished Jun 23 05:31:14 PM PDT 24
Peak memory 191188 kb
Host smart-d7e15e78-6e66-41fe-b3c9-3684b5ad7474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356559601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2356559601
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.3284727774
Short name T246
Test name
Test status
Simulation time 715214801264 ps
CPU time 2081.37 seconds
Started Jun 23 05:30:23 PM PDT 24
Finished Jun 23 06:05:05 PM PDT 24
Peak memory 194240 kb
Host smart-31a5dc2f-7964-412f-93af-48f69c5b8e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284727774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3284727774
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.2763822487
Short name T162
Test name
Test status
Simulation time 477981231118 ps
CPU time 1639.25 seconds
Started Jun 23 05:30:52 PM PDT 24
Finished Jun 23 05:58:12 PM PDT 24
Peak memory 191156 kb
Host smart-ec2dd408-0c16-4bee-ae48-ee43d5292316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763822487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2763822487
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3293902419
Short name T244
Test name
Test status
Simulation time 126960888369 ps
CPU time 500.55 seconds
Started Jun 23 05:30:59 PM PDT 24
Finished Jun 23 05:39:20 PM PDT 24
Peak memory 191196 kb
Host smart-3030d573-db31-4d5c-bfac-aeca4a101d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293902419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3293902419
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1189601010
Short name T100
Test name
Test status
Simulation time 543487181733 ps
CPU time 313.85 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:35:17 PM PDT 24
Peak memory 182980 kb
Host smart-f3526165-3dd3-4edd-9942-d6eb098d3dc9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189601010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1189601010
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/80.rv_timer_random.212704914
Short name T292
Test name
Test status
Simulation time 487162321594 ps
CPU time 2071.82 seconds
Started Jun 23 05:30:58 PM PDT 24
Finished Jun 23 06:05:30 PM PDT 24
Peak memory 191196 kb
Host smart-ebc4e085-2243-4c10-82f8-86fde8ab9ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212704914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.212704914
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1194603426
Short name T237
Test name
Test status
Simulation time 356836947715 ps
CPU time 96.83 seconds
Started Jun 23 05:31:03 PM PDT 24
Finished Jun 23 05:32:41 PM PDT 24
Peak memory 194948 kb
Host smart-359c6f8c-f1a6-4d35-8e64-11287ba2400d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194603426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1194603426
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1295450896
Short name T215
Test name
Test status
Simulation time 12126820676 ps
CPU time 42.41 seconds
Started Jun 23 05:31:08 PM PDT 24
Finished Jun 23 05:31:51 PM PDT 24
Peak memory 191188 kb
Host smart-7c432e71-f364-41c5-8f45-2189d51dcb0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295450896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1295450896
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2016107620
Short name T155
Test name
Test status
Simulation time 130323202248 ps
CPU time 230.25 seconds
Started Jun 23 05:29:55 PM PDT 24
Finished Jun 23 05:33:46 PM PDT 24
Peak memory 182984 kb
Host smart-7bb68af7-eef5-48d3-8923-ddf82e2bd2b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016107620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2016107620
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.150263571
Short name T509
Test name
Test status
Simulation time 1325827070 ps
CPU time 1.5 seconds
Started Jun 23 06:15:20 PM PDT 24
Finished Jun 23 06:15:22 PM PDT 24
Peak memory 195520 kb
Host smart-2b96794c-8338-458e-988a-5c21d7f699dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150263571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.150263571
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1697116400
Short name T37
Test name
Test status
Simulation time 72188678811 ps
CPU time 559.82 seconds
Started Jun 23 05:29:51 PM PDT 24
Finished Jun 23 05:39:11 PM PDT 24
Peak memory 208668 kb
Host smart-91ed22e1-a501-4846-9d54-71f37856f797
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697116400 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1697116400
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_random.473185879
Short name T251
Test name
Test status
Simulation time 96445889280 ps
CPU time 254.32 seconds
Started Jun 23 05:29:55 PM PDT 24
Finished Jun 23 05:34:10 PM PDT 24
Peak memory 182944 kb
Host smart-c44b0899-dd7e-43fa-a3bf-39589d77211f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473185879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.473185879
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3618700536
Short name T7
Test name
Test status
Simulation time 121480713283 ps
CPU time 104.38 seconds
Started Jun 23 05:31:15 PM PDT 24
Finished Jun 23 05:33:00 PM PDT 24
Peak memory 191104 kb
Host smart-203a53c2-ac05-4355-b097-37f8769b3fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618700536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3618700536
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1296554966
Short name T348
Test name
Test status
Simulation time 167728908813 ps
CPU time 215.05 seconds
Started Jun 23 05:31:17 PM PDT 24
Finished Jun 23 05:34:52 PM PDT 24
Peak memory 191192 kb
Host smart-3c60a3fe-fd78-4b0e-b296-1bc284ff3223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296554966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1296554966
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1976659194
Short name T200
Test name
Test status
Simulation time 5227757971822 ps
CPU time 2673.14 seconds
Started Jun 23 05:30:01 PM PDT 24
Finished Jun 23 06:14:35 PM PDT 24
Peak memory 191188 kb
Host smart-ccad0dfd-30bf-4c8f-a80a-5ebfde102a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976659194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1976659194
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/117.rv_timer_random.1008016878
Short name T158
Test name
Test status
Simulation time 93524307353 ps
CPU time 235.27 seconds
Started Jun 23 05:31:20 PM PDT 24
Finished Jun 23 05:35:16 PM PDT 24
Peak memory 191156 kb
Host smart-7c88dc47-e64c-434c-b324-f89b0e6c7191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008016878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1008016878
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3996643545
Short name T231
Test name
Test status
Simulation time 17948685135 ps
CPU time 25.73 seconds
Started Jun 23 05:31:21 PM PDT 24
Finished Jun 23 05:31:47 PM PDT 24
Peak memory 182796 kb
Host smart-86f7d4d1-b3b1-4fe5-af72-3f6fc5cddf70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996643545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3996643545
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.648074423
Short name T5
Test name
Test status
Simulation time 146134674437 ps
CPU time 492.67 seconds
Started Jun 23 05:31:22 PM PDT 24
Finished Jun 23 05:39:35 PM PDT 24
Peak memory 191196 kb
Host smart-56dda8b2-e218-4b5e-824c-dcc161e33b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648074423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.648074423
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1685393758
Short name T232
Test name
Test status
Simulation time 445110103936 ps
CPU time 541.23 seconds
Started Jun 23 05:31:28 PM PDT 24
Finished Jun 23 05:40:30 PM PDT 24
Peak memory 191188 kb
Host smart-6bfa6929-3f1d-45cd-a5c8-bbc8c781fe25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685393758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1685393758
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1765736020
Short name T245
Test name
Test status
Simulation time 604437452996 ps
CPU time 448.64 seconds
Started Jun 23 05:31:29 PM PDT 24
Finished Jun 23 05:38:58 PM PDT 24
Peak memory 191192 kb
Host smart-ace784cb-c28b-43fb-bbf3-f6f712931ea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765736020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1765736020
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1330681395
Short name T168
Test name
Test status
Simulation time 76043085657 ps
CPU time 115.5 seconds
Started Jun 23 05:31:31 PM PDT 24
Finished Jun 23 05:33:27 PM PDT 24
Peak memory 191204 kb
Host smart-4222ffba-65e9-47d9-af2b-a164bf45af54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330681395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1330681395
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2852903207
Short name T171
Test name
Test status
Simulation time 17854567352 ps
CPU time 21.68 seconds
Started Jun 23 05:31:45 PM PDT 24
Finished Jun 23 05:32:07 PM PDT 24
Peak memory 182836 kb
Host smart-861159df-235d-4e8c-ba74-18e162ecbeb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852903207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2852903207
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.4144539180
Short name T301
Test name
Test status
Simulation time 57836912341 ps
CPU time 81.16 seconds
Started Jun 23 05:31:55 PM PDT 24
Finished Jun 23 05:33:16 PM PDT 24
Peak memory 191176 kb
Host smart-11021382-7912-4bc7-8500-04d13da42b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144539180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.4144539180
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.4046381535
Short name T255
Test name
Test status
Simulation time 214214290502 ps
CPU time 117.54 seconds
Started Jun 23 05:31:56 PM PDT 24
Finished Jun 23 05:33:54 PM PDT 24
Peak memory 191184 kb
Host smart-baff8b9a-0258-408c-9913-51cbe627f8fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046381535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.4046381535
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.4271047396
Short name T140
Test name
Test status
Simulation time 80628743440 ps
CPU time 139.02 seconds
Started Jun 23 05:31:59 PM PDT 24
Finished Jun 23 05:34:18 PM PDT 24
Peak memory 191084 kb
Host smart-1631a856-c3e7-4ab5-a391-4e3a6643acb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271047396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4271047396
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.607274551
Short name T273
Test name
Test status
Simulation time 609631166691 ps
CPU time 634.46 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:40:48 PM PDT 24
Peak memory 182840 kb
Host smart-00ab259b-0773-42d0-a2eb-04a70ed605ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607274551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.607274551
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/166.rv_timer_random.2777416998
Short name T394
Test name
Test status
Simulation time 364689844222 ps
CPU time 367.7 seconds
Started Jun 23 05:31:57 PM PDT 24
Finished Jun 23 05:38:05 PM PDT 24
Peak memory 191180 kb
Host smart-c38671f7-373b-492b-9c9e-379864a195a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777416998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2777416998
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1313754720
Short name T145
Test name
Test status
Simulation time 306847935860 ps
CPU time 212.66 seconds
Started Jun 23 05:32:23 PM PDT 24
Finished Jun 23 05:35:56 PM PDT 24
Peak memory 191240 kb
Host smart-8c7d24d5-b63c-4cf8-8c30-1d8833630907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313754720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1313754720
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3887042382
Short name T342
Test name
Test status
Simulation time 51438650186 ps
CPU time 27.99 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:30:32 PM PDT 24
Peak memory 182964 kb
Host smart-67f2a19e-2024-4cae-abeb-b8eab2a567ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887042382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3887042382
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2813877727
Short name T329
Test name
Test status
Simulation time 4300418799368 ps
CPU time 1037.2 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:47:24 PM PDT 24
Peak memory 182992 kb
Host smart-60afcbc6-17f6-48ef-834b-4937d0abfe34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813877727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2813877727
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3635497774
Short name T192
Test name
Test status
Simulation time 88420019169 ps
CPU time 118.81 seconds
Started Jun 23 05:30:17 PM PDT 24
Finished Jun 23 05:32:16 PM PDT 24
Peak memory 183008 kb
Host smart-f1d9aab7-8381-4ce1-85bd-0763ef938105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635497774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3635497774
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_random.2314377994
Short name T112
Test name
Test status
Simulation time 39975490866 ps
CPU time 491.75 seconds
Started Jun 23 05:29:48 PM PDT 24
Finished Jun 23 05:38:00 PM PDT 24
Peak memory 191200 kb
Host smart-d8354a53-e6ce-445d-9779-90318dae1f39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314377994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2314377994
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2392312717
Short name T182
Test name
Test status
Simulation time 260190372617 ps
CPU time 735.67 seconds
Started Jun 23 05:31:06 PM PDT 24
Finished Jun 23 05:43:23 PM PDT 24
Peak memory 191072 kb
Host smart-42deccb0-229a-47ff-a9cd-4468009bcc69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392312717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2392312717
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.638300892
Short name T74
Test name
Test status
Simulation time 127373454 ps
CPU time 0.84 seconds
Started Jun 23 06:15:24 PM PDT 24
Finished Jun 23 06:15:26 PM PDT 24
Peak memory 182716 kb
Host smart-1da76329-8a4c-4bac-9506-5778ffa2278c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638300892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.638300892
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3205599639
Short name T548
Test name
Test status
Simulation time 451767592 ps
CPU time 1.49 seconds
Started Jun 23 06:15:22 PM PDT 24
Finished Jun 23 06:15:24 PM PDT 24
Peak memory 192080 kb
Host smart-c6d18e8d-1876-42ba-890d-21d1165508fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205599639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3205599639
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2110690311
Short name T475
Test name
Test status
Simulation time 14241049 ps
CPU time 0.57 seconds
Started Jun 23 06:15:16 PM PDT 24
Finished Jun 23 06:15:16 PM PDT 24
Peak memory 182716 kb
Host smart-53fa402c-7528-4559-ab46-902e3d140944
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110690311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2110690311
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3806480407
Short name T579
Test name
Test status
Simulation time 397580937 ps
CPU time 0.83 seconds
Started Jun 23 06:15:25 PM PDT 24
Finished Jun 23 06:15:27 PM PDT 24
Peak memory 195132 kb
Host smart-2c33f126-51e1-4d27-aedd-22f414600069
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806480407 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3806480407
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3210172411
Short name T67
Test name
Test status
Simulation time 16355428 ps
CPU time 0.55 seconds
Started Jun 23 06:15:25 PM PDT 24
Finished Jun 23 06:15:26 PM PDT 24
Peak memory 182680 kb
Host smart-11613eb3-24c7-4ed0-b066-f34ad8a71f6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210172411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3210172411
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4243610153
Short name T483
Test name
Test status
Simulation time 31105775 ps
CPU time 0.59 seconds
Started Jun 23 06:15:16 PM PDT 24
Finished Jun 23 06:15:17 PM PDT 24
Peak memory 182668 kb
Host smart-f915090b-9246-4fa0-89ff-769ef273afb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243610153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.4243610153
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2054235690
Short name T572
Test name
Test status
Simulation time 19254160 ps
CPU time 0.84 seconds
Started Jun 23 06:15:25 PM PDT 24
Finished Jun 23 06:15:26 PM PDT 24
Peak memory 191732 kb
Host smart-447103a2-328e-45d1-8fcf-2ba208b6ab33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054235690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2054235690
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1812911556
Short name T501
Test name
Test status
Simulation time 440653036 ps
CPU time 2.18 seconds
Started Jun 23 06:15:20 PM PDT 24
Finished Jun 23 06:15:22 PM PDT 24
Peak memory 197576 kb
Host smart-13a1a470-5dcd-4ba5-bb83-2681dfadd3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812911556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1812911556
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2373254054
Short name T78
Test name
Test status
Simulation time 31118744 ps
CPU time 0.73 seconds
Started Jun 23 06:15:24 PM PDT 24
Finished Jun 23 06:15:25 PM PDT 24
Peak memory 192412 kb
Host smart-a9c19658-10f8-4814-a921-0c0c6e40ecec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373254054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2373254054
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2761143456
Short name T29
Test name
Test status
Simulation time 369717663 ps
CPU time 2.69 seconds
Started Jun 23 06:15:23 PM PDT 24
Finished Jun 23 06:15:26 PM PDT 24
Peak memory 192752 kb
Host smart-cbab9bd0-0dca-406f-9161-93b682bb20e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761143456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2761143456
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4054520470
Short name T578
Test name
Test status
Simulation time 252743363 ps
CPU time 0.59 seconds
Started Jun 23 06:15:21 PM PDT 24
Finished Jun 23 06:15:22 PM PDT 24
Peak memory 191872 kb
Host smart-1adbc85a-add7-4565-bfa8-78d9a9ffc866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054520470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4054520470
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3445708306
Short name T536
Test name
Test status
Simulation time 130489062 ps
CPU time 0.87 seconds
Started Jun 23 06:15:23 PM PDT 24
Finished Jun 23 06:15:25 PM PDT 24
Peak memory 197424 kb
Host smart-8b5a041e-3d04-478f-8466-da146d8c7aab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445708306 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3445708306
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.142884380
Short name T493
Test name
Test status
Simulation time 52354396 ps
CPU time 0.61 seconds
Started Jun 23 06:15:22 PM PDT 24
Finished Jun 23 06:15:23 PM PDT 24
Peak memory 182756 kb
Host smart-5100f8fe-a334-4abf-95d9-b3b3d980b393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142884380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.142884380
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3352712308
Short name T573
Test name
Test status
Simulation time 56717719 ps
CPU time 0.58 seconds
Started Jun 23 06:15:23 PM PDT 24
Finished Jun 23 06:15:24 PM PDT 24
Peak memory 182636 kb
Host smart-c33bb4fc-a0bc-487f-b7d7-10a61c8df6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352712308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3352712308
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1481953974
Short name T459
Test name
Test status
Simulation time 132027465 ps
CPU time 1.03 seconds
Started Jun 23 06:15:24 PM PDT 24
Finished Jun 23 06:15:25 PM PDT 24
Peak memory 194944 kb
Host smart-9cea110c-6fd6-4e40-ae62-d20c6407d5bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481953974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1481953974
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3699126389
Short name T84
Test name
Test status
Simulation time 49190662 ps
CPU time 0.85 seconds
Started Jun 23 06:15:22 PM PDT 24
Finished Jun 23 06:15:23 PM PDT 24
Peak memory 193248 kb
Host smart-2c748e89-a381-402f-bdc2-69cec7b5b8b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699126389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3699126389
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.603613542
Short name T551
Test name
Test status
Simulation time 24114066 ps
CPU time 0.77 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:41 PM PDT 24
Peak memory 194828 kb
Host smart-509fb0e6-46e3-499f-8015-4ee4f03710a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603613542 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.603613542
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4166429785
Short name T496
Test name
Test status
Simulation time 15102276 ps
CPU time 0.57 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 182684 kb
Host smart-43c38738-983c-43fe-b40b-c7de74e03da4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166429785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4166429785
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2600799177
Short name T468
Test name
Test status
Simulation time 21122162 ps
CPU time 0.55 seconds
Started Jun 23 06:15:40 PM PDT 24
Finished Jun 23 06:15:42 PM PDT 24
Peak memory 182592 kb
Host smart-9fc58875-abf3-4c28-b902-9ba3246b67b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600799177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2600799177
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4060572106
Short name T540
Test name
Test status
Simulation time 21055179 ps
CPU time 0.63 seconds
Started Jun 23 06:15:42 PM PDT 24
Finished Jun 23 06:15:43 PM PDT 24
Peak memory 191628 kb
Host smart-37b617b9-1305-4fa5-b6c3-b87d6df8f9e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060572106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4060572106
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2515245262
Short name T513
Test name
Test status
Simulation time 500288769 ps
CPU time 1.68 seconds
Started Jun 23 06:15:41 PM PDT 24
Finished Jun 23 06:15:44 PM PDT 24
Peak memory 197600 kb
Host smart-28bad402-9f81-4821-9034-ba07611f6014
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515245262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2515245262
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.288318415
Short name T503
Test name
Test status
Simulation time 124284612 ps
CPU time 1.08 seconds
Started Jun 23 06:15:40 PM PDT 24
Finished Jun 23 06:15:42 PM PDT 24
Peak memory 195232 kb
Host smart-70486289-3552-432d-a227-28774233ced6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288318415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.288318415
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2278815628
Short name T478
Test name
Test status
Simulation time 110279392 ps
CPU time 1.23 seconds
Started Jun 23 06:15:42 PM PDT 24
Finished Jun 23 06:15:43 PM PDT 24
Peak memory 197568 kb
Host smart-9e841011-8246-4923-a49d-e97169212df0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278815628 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2278815628
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1524489905
Short name T522
Test name
Test status
Simulation time 14610876 ps
CPU time 0.57 seconds
Started Jun 23 06:15:38 PM PDT 24
Finished Jun 23 06:15:39 PM PDT 24
Peak memory 182728 kb
Host smart-03dc67bd-f6c6-4274-a7ea-5e418a65452d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524489905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1524489905
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3795796216
Short name T473
Test name
Test status
Simulation time 16468196 ps
CPU time 0.57 seconds
Started Jun 23 06:15:41 PM PDT 24
Finished Jun 23 06:15:42 PM PDT 24
Peak memory 182552 kb
Host smart-4864d17b-62ec-4251-93cd-373a54ee6c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795796216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3795796216
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.469288725
Short name T494
Test name
Test status
Simulation time 15624558 ps
CPU time 0.63 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 191992 kb
Host smart-cc498f13-9f58-4c8f-bb29-46a44abc6fe9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469288725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.469288725
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.727832013
Short name T555
Test name
Test status
Simulation time 119632477 ps
CPU time 2.14 seconds
Started Jun 23 06:15:41 PM PDT 24
Finished Jun 23 06:15:44 PM PDT 24
Peak memory 197596 kb
Host smart-909073dc-3a30-4c63-8ae9-5e2113957380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727832013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.727832013
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2099195013
Short name T539
Test name
Test status
Simulation time 91699280 ps
CPU time 1.31 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:41 PM PDT 24
Peak memory 195420 kb
Host smart-044c6204-cf88-4c93-8c00-935b0c759b62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099195013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2099195013
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3267997378
Short name T559
Test name
Test status
Simulation time 86477478 ps
CPU time 0.73 seconds
Started Jun 23 06:15:45 PM PDT 24
Finished Jun 23 06:15:46 PM PDT 24
Peak memory 195080 kb
Host smart-acb45e71-0291-49d2-9ebc-2915ee81d33c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267997378 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3267997378
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.656317093
Short name T41
Test name
Test status
Simulation time 15398198 ps
CPU time 0.58 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 182708 kb
Host smart-e9413d1a-1f6e-42e4-93a5-f2315e442c17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656317093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.656317093
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.885848038
Short name T519
Test name
Test status
Simulation time 116269482 ps
CPU time 0.61 seconds
Started Jun 23 06:15:41 PM PDT 24
Finished Jun 23 06:15:43 PM PDT 24
Peak memory 182584 kb
Host smart-b9b3c255-a0be-4b79-ada8-88a6db84f594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885848038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.885848038
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3548890615
Short name T533
Test name
Test status
Simulation time 17737588 ps
CPU time 0.69 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:41 PM PDT 24
Peak memory 191676 kb
Host smart-8e44eaa4-9845-4046-9894-e49f2bd5ed10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548890615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3548890615
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.726084909
Short name T43
Test name
Test status
Simulation time 317133765 ps
CPU time 1.62 seconds
Started Jun 23 06:15:41 PM PDT 24
Finished Jun 23 06:15:43 PM PDT 24
Peak memory 197560 kb
Host smart-e35b35ad-0788-4bcb-90d2-0f18c472f67b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726084909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.726084909
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2079695841
Short name T491
Test name
Test status
Simulation time 135909788 ps
CPU time 0.88 seconds
Started Jun 23 06:15:42 PM PDT 24
Finished Jun 23 06:15:44 PM PDT 24
Peak memory 196712 kb
Host smart-a73fba3e-f8cd-4921-8883-acce6db96987
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079695841 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2079695841
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.818530646
Short name T488
Test name
Test status
Simulation time 63646511 ps
CPU time 0.59 seconds
Started Jun 23 06:15:45 PM PDT 24
Finished Jun 23 06:15:46 PM PDT 24
Peak memory 182708 kb
Host smart-d36ca520-6bc1-4443-8e1a-46c866722574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818530646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.818530646
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4067969039
Short name T530
Test name
Test status
Simulation time 40079747 ps
CPU time 0.56 seconds
Started Jun 23 06:15:50 PM PDT 24
Finished Jun 23 06:15:51 PM PDT 24
Peak memory 182656 kb
Host smart-ef8ce2a4-f252-4e1d-a558-591a243775d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067969039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.4067969039
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3838248381
Short name T556
Test name
Test status
Simulation time 190206326 ps
CPU time 0.64 seconds
Started Jun 23 06:15:42 PM PDT 24
Finished Jun 23 06:15:44 PM PDT 24
Peak memory 191572 kb
Host smart-efa4bb56-9592-4750-970d-1b17b804a0c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838248381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3838248381
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1106695130
Short name T504
Test name
Test status
Simulation time 96777154 ps
CPU time 1.63 seconds
Started Jun 23 06:15:45 PM PDT 24
Finished Jun 23 06:15:47 PM PDT 24
Peak memory 197384 kb
Host smart-831dbba5-fdd0-418b-a8ae-0a0456a39683
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106695130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1106695130
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4020612003
Short name T85
Test name
Test status
Simulation time 179394257 ps
CPU time 1.38 seconds
Started Jun 23 06:15:50 PM PDT 24
Finished Jun 23 06:15:52 PM PDT 24
Peak memory 183288 kb
Host smart-eafdcf72-fd73-4060-aa55-42956f0f1dad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020612003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.4020612003
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.156771318
Short name T552
Test name
Test status
Simulation time 37451929 ps
CPU time 0.66 seconds
Started Jun 23 06:15:43 PM PDT 24
Finished Jun 23 06:15:44 PM PDT 24
Peak memory 194044 kb
Host smart-63fc4df6-0fbb-4069-8d9d-2bf09cad4825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156771318 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.156771318
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3711929120
Short name T83
Test name
Test status
Simulation time 34441372 ps
CPU time 0.55 seconds
Started Jun 23 06:15:49 PM PDT 24
Finished Jun 23 06:15:50 PM PDT 24
Peak memory 182508 kb
Host smart-919a36dc-b2e0-4b57-8f7b-8b3ad67645fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711929120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3711929120
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1356722359
Short name T557
Test name
Test status
Simulation time 16111761 ps
CPU time 0.57 seconds
Started Jun 23 06:15:42 PM PDT 24
Finished Jun 23 06:15:43 PM PDT 24
Peak memory 182532 kb
Host smart-23224ca0-9898-4f05-bff2-10c347cbd7ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356722359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1356722359
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3705978152
Short name T531
Test name
Test status
Simulation time 99204852 ps
CPU time 0.72 seconds
Started Jun 23 06:15:44 PM PDT 24
Finished Jun 23 06:15:45 PM PDT 24
Peak memory 192696 kb
Host smart-1b36d7f3-df19-4199-b802-3c96679dde9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705978152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3705978152
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3873515689
Short name T576
Test name
Test status
Simulation time 43639203 ps
CPU time 2.13 seconds
Started Jun 23 06:15:43 PM PDT 24
Finished Jun 23 06:15:45 PM PDT 24
Peak memory 197576 kb
Host smart-38c2778d-7727-49d2-852b-3becbc022f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873515689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3873515689
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2020065189
Short name T562
Test name
Test status
Simulation time 362657578 ps
CPU time 1.29 seconds
Started Jun 23 06:15:44 PM PDT 24
Finished Jun 23 06:15:46 PM PDT 24
Peak memory 195264 kb
Host smart-53efdd93-8650-4761-9be4-8dd85c358a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020065189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2020065189
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2663427065
Short name T580
Test name
Test status
Simulation time 26297684 ps
CPU time 0.78 seconds
Started Jun 23 06:15:45 PM PDT 24
Finished Jun 23 06:15:46 PM PDT 24
Peak memory 195164 kb
Host smart-467e8604-24f4-43c5-842b-f40ae2cfe391
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663427065 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2663427065
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3634270337
Short name T528
Test name
Test status
Simulation time 13073083 ps
CPU time 0.56 seconds
Started Jun 23 06:15:50 PM PDT 24
Finished Jun 23 06:15:51 PM PDT 24
Peak memory 182520 kb
Host smart-1ffb022c-d3fa-4676-9afc-c7c175150b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634270337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3634270337
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3633782027
Short name T517
Test name
Test status
Simulation time 24012024 ps
CPU time 0.58 seconds
Started Jun 23 06:15:47 PM PDT 24
Finished Jun 23 06:15:48 PM PDT 24
Peak memory 182604 kb
Host smart-3d8223a0-0322-4f82-8511-7fea579215ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633782027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3633782027
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.785249272
Short name T554
Test name
Test status
Simulation time 71206726 ps
CPU time 0.73 seconds
Started Jun 23 06:15:44 PM PDT 24
Finished Jun 23 06:15:45 PM PDT 24
Peak memory 193136 kb
Host smart-3d0523b2-4250-4625-b27c-fc18d5a64630
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785249272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.785249272
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2957303150
Short name T502
Test name
Test status
Simulation time 36994672 ps
CPU time 1.69 seconds
Started Jun 23 06:15:45 PM PDT 24
Finished Jun 23 06:15:47 PM PDT 24
Peak memory 197552 kb
Host smart-0a2467d1-c055-43e1-bfb6-4cacf735494e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957303150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2957303150
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3522584896
Short name T570
Test name
Test status
Simulation time 120679653 ps
CPU time 0.95 seconds
Started Jun 23 06:15:42 PM PDT 24
Finished Jun 23 06:15:44 PM PDT 24
Peak memory 193880 kb
Host smart-5481e60b-00d9-43c6-8a84-372c782dcac8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522584896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3522584896
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2968952119
Short name T470
Test name
Test status
Simulation time 40467034 ps
CPU time 0.75 seconds
Started Jun 23 06:15:49 PM PDT 24
Finished Jun 23 06:15:51 PM PDT 24
Peak memory 195272 kb
Host smart-c82ee009-349a-46be-bf0b-d46265f4039a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968952119 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2968952119
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3108503413
Short name T527
Test name
Test status
Simulation time 121473449 ps
CPU time 0.54 seconds
Started Jun 23 06:15:49 PM PDT 24
Finished Jun 23 06:15:50 PM PDT 24
Peak memory 182540 kb
Host smart-fdefaaf4-fbdd-4bbb-8019-f32c0b0a2a1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108503413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3108503413
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3619060209
Short name T479
Test name
Test status
Simulation time 40514549 ps
CPU time 0.58 seconds
Started Jun 23 06:15:53 PM PDT 24
Finished Jun 23 06:15:54 PM PDT 24
Peak memory 182652 kb
Host smart-b1d8965c-4e27-47d2-acd2-28cfc0df7077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619060209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3619060209
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3027079408
Short name T526
Test name
Test status
Simulation time 20123268 ps
CPU time 0.8 seconds
Started Jun 23 06:15:47 PM PDT 24
Finished Jun 23 06:15:48 PM PDT 24
Peak memory 193460 kb
Host smart-7bebc8f4-86f3-45d6-9115-cd35b4fab287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027079408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3027079408
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3171863771
Short name T461
Test name
Test status
Simulation time 337240452 ps
CPU time 2.1 seconds
Started Jun 23 06:15:49 PM PDT 24
Finished Jun 23 06:15:51 PM PDT 24
Peak memory 197720 kb
Host smart-891b9998-2915-45c8-9517-35ac37e4d4aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171863771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3171863771
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3523725736
Short name T86
Test name
Test status
Simulation time 413770042 ps
CPU time 1.39 seconds
Started Jun 23 06:15:48 PM PDT 24
Finished Jun 23 06:15:50 PM PDT 24
Peak memory 195440 kb
Host smart-4da2f622-b3af-479e-b029-0ffd91aa75d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523725736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3523725736
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.190568408
Short name T521
Test name
Test status
Simulation time 88086195 ps
CPU time 0.63 seconds
Started Jun 23 06:15:51 PM PDT 24
Finished Jun 23 06:15:52 PM PDT 24
Peak memory 193388 kb
Host smart-05a711eb-db62-4f26-a5dd-22a8210d84c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190568408 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.190568408
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.71943589
Short name T76
Test name
Test status
Simulation time 59345923 ps
CPU time 0.56 seconds
Started Jun 23 06:15:47 PM PDT 24
Finished Jun 23 06:15:48 PM PDT 24
Peak memory 182680 kb
Host smart-f4d22ad4-2f46-4c67-bb93-86ac1d441cbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71943589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.71943589
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1116350454
Short name T490
Test name
Test status
Simulation time 78125609 ps
CPU time 0.52 seconds
Started Jun 23 06:15:46 PM PDT 24
Finished Jun 23 06:15:47 PM PDT 24
Peak memory 182204 kb
Host smart-f6b868e8-098a-4bd9-b5f7-53dbf7ae007a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116350454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1116350454
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.91501065
Short name T561
Test name
Test status
Simulation time 40791040 ps
CPU time 0.61 seconds
Started Jun 23 06:15:47 PM PDT 24
Finished Jun 23 06:15:48 PM PDT 24
Peak memory 191640 kb
Host smart-1a8baba0-35d2-4b38-995d-ebf9fd03f552
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91501065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_tim
er_same_csr_outstanding.91501065
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1952455310
Short name T563
Test name
Test status
Simulation time 207109386 ps
CPU time 1.96 seconds
Started Jun 23 06:15:50 PM PDT 24
Finished Jun 23 06:15:53 PM PDT 24
Peak memory 197604 kb
Host smart-35da8b94-ef50-493f-81f1-9873fe7351bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952455310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1952455310
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2867105302
Short name T26
Test name
Test status
Simulation time 71989843 ps
CPU time 0.84 seconds
Started Jun 23 06:15:50 PM PDT 24
Finished Jun 23 06:15:52 PM PDT 24
Peak memory 193572 kb
Host smart-e79ffe9f-a2cf-4016-a576-3fdf618bb237
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867105302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2867105302
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2454122204
Short name T537
Test name
Test status
Simulation time 97540219 ps
CPU time 0.79 seconds
Started Jun 23 06:15:51 PM PDT 24
Finished Jun 23 06:15:53 PM PDT 24
Peak memory 195472 kb
Host smart-ae028534-75d0-44c5-aece-c8f7a38fb44e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454122204 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2454122204
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2294161067
Short name T28
Test name
Test status
Simulation time 12676714 ps
CPU time 0.56 seconds
Started Jun 23 06:15:48 PM PDT 24
Finished Jun 23 06:15:49 PM PDT 24
Peak memory 182432 kb
Host smart-13434326-d777-4769-a408-ee36f16f396a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294161067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2294161067
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3015933206
Short name T454
Test name
Test status
Simulation time 19635174 ps
CPU time 0.54 seconds
Started Jun 23 06:15:49 PM PDT 24
Finished Jun 23 06:15:51 PM PDT 24
Peak memory 182556 kb
Host smart-32f98883-aa12-4773-bec5-739269be3096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015933206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3015933206
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.508267593
Short name T82
Test name
Test status
Simulation time 15985410 ps
CPU time 0.72 seconds
Started Jun 23 06:15:50 PM PDT 24
Finished Jun 23 06:15:51 PM PDT 24
Peak memory 191720 kb
Host smart-8fa5f85d-55f9-49b6-8589-9514010232b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508267593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.508267593
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3447908061
Short name T525
Test name
Test status
Simulation time 716069770 ps
CPU time 2.05 seconds
Started Jun 23 06:15:52 PM PDT 24
Finished Jun 23 06:15:55 PM PDT 24
Peak memory 197612 kb
Host smart-c6906aee-4538-4cac-b80f-63a7a060a3ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447908061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3447908061
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1419185630
Short name T546
Test name
Test status
Simulation time 172119303 ps
CPU time 1.05 seconds
Started Jun 23 06:15:55 PM PDT 24
Finished Jun 23 06:15:56 PM PDT 24
Peak memory 183172 kb
Host smart-0fd5ea85-02b0-492f-93a9-c5d388612d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419185630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1419185630
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2289946851
Short name T508
Test name
Test status
Simulation time 133119319 ps
CPU time 0.83 seconds
Started Jun 23 06:15:55 PM PDT 24
Finished Jun 23 06:15:56 PM PDT 24
Peak memory 196776 kb
Host smart-4043f1c7-4e11-4260-9d3a-77fef0588783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289946851 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2289946851
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3166705949
Short name T77
Test name
Test status
Simulation time 13960875 ps
CPU time 0.59 seconds
Started Jun 23 06:15:53 PM PDT 24
Finished Jun 23 06:15:54 PM PDT 24
Peak memory 182732 kb
Host smart-59207a8e-21a8-43b5-bcc2-89269fbcafc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166705949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3166705949
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2761266159
Short name T492
Test name
Test status
Simulation time 41189696 ps
CPU time 0.54 seconds
Started Jun 23 06:15:50 PM PDT 24
Finished Jun 23 06:15:52 PM PDT 24
Peak memory 182244 kb
Host smart-4f153bf2-8dcd-45ce-91a3-2d409c42cb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761266159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2761266159
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1139531704
Short name T485
Test name
Test status
Simulation time 68295980 ps
CPU time 0.81 seconds
Started Jun 23 06:15:51 PM PDT 24
Finished Jun 23 06:15:52 PM PDT 24
Peak memory 193432 kb
Host smart-9daf5085-8fdb-4719-aa2e-ffc09a29eb42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139531704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1139531704
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1175549043
Short name T453
Test name
Test status
Simulation time 132569097 ps
CPU time 1.73 seconds
Started Jun 23 06:15:46 PM PDT 24
Finished Jun 23 06:15:49 PM PDT 24
Peak memory 197456 kb
Host smart-b7940012-8081-4ad6-8611-ab7693d960e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175549043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1175549043
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4039059431
Short name T518
Test name
Test status
Simulation time 114920405 ps
CPU time 1.28 seconds
Started Jun 23 06:15:49 PM PDT 24
Finished Jun 23 06:15:51 PM PDT 24
Peak memory 194300 kb
Host smart-5a7a0ea0-98f7-4488-9e88-c8c02ae6c2a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039059431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.4039059431
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.942522313
Short name T532
Test name
Test status
Simulation time 80718409 ps
CPU time 0.82 seconds
Started Jun 23 06:15:40 PM PDT 24
Finished Jun 23 06:15:41 PM PDT 24
Peak memory 182728 kb
Host smart-3acf168f-06ce-4f90-88df-38e9f7040909
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942522313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.942522313
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.137285866
Short name T495
Test name
Test status
Simulation time 610700730 ps
CPU time 3.61 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 191100 kb
Host smart-51fe5322-072e-4776-8488-d303c11bc887
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137285866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.137285866
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2201513604
Short name T69
Test name
Test status
Simulation time 18158819 ps
CPU time 0.6 seconds
Started Jun 23 06:15:23 PM PDT 24
Finished Jun 23 06:15:24 PM PDT 24
Peak memory 182716 kb
Host smart-178a6bbc-4640-4f0d-a9a0-5d7e76916926
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201513604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2201513604
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.177659523
Short name T460
Test name
Test status
Simulation time 29486439 ps
CPU time 0.85 seconds
Started Jun 23 06:15:29 PM PDT 24
Finished Jun 23 06:15:30 PM PDT 24
Peak memory 195264 kb
Host smart-1d376a6a-d08b-4783-a668-823cca24edd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177659523 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.177659523
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1357860137
Short name T75
Test name
Test status
Simulation time 12973322 ps
CPU time 0.58 seconds
Started Jun 23 06:15:32 PM PDT 24
Finished Jun 23 06:15:33 PM PDT 24
Peak memory 182680 kb
Host smart-6a482060-51eb-461c-b1eb-937a481750b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357860137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1357860137
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2146219169
Short name T515
Test name
Test status
Simulation time 17278445 ps
CPU time 0.57 seconds
Started Jun 23 06:15:23 PM PDT 24
Finished Jun 23 06:15:24 PM PDT 24
Peak memory 182616 kb
Host smart-b54b1c58-012f-483b-9130-2fa636e9d6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146219169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2146219169
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1500009886
Short name T73
Test name
Test status
Simulation time 90792630 ps
CPU time 0.7 seconds
Started Jun 23 06:15:31 PM PDT 24
Finished Jun 23 06:15:32 PM PDT 24
Peak memory 193096 kb
Host smart-cea7afde-78e5-4522-9a25-fcfb78fb7085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500009886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1500009886
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1350384655
Short name T464
Test name
Test status
Simulation time 38549352 ps
CPU time 1.75 seconds
Started Jun 23 06:15:24 PM PDT 24
Finished Jun 23 06:15:26 PM PDT 24
Peak memory 197608 kb
Host smart-f9155331-4849-4b3e-822a-51622e61e708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350384655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1350384655
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1836637021
Short name T550
Test name
Test status
Simulation time 391461681 ps
CPU time 0.84 seconds
Started Jun 23 06:15:22 PM PDT 24
Finished Jun 23 06:15:23 PM PDT 24
Peak memory 193880 kb
Host smart-d35f4299-e882-4a31-b701-e0850a4329ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836637021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1836637021
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3433720813
Short name T581
Test name
Test status
Simulation time 52449640 ps
CPU time 0.55 seconds
Started Jun 23 06:15:49 PM PDT 24
Finished Jun 23 06:15:50 PM PDT 24
Peak memory 182564 kb
Host smart-5ddd65a3-6f5d-4efa-8321-6aed26f69502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433720813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3433720813
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.642993773
Short name T505
Test name
Test status
Simulation time 25645106 ps
CPU time 0.54 seconds
Started Jun 23 06:15:53 PM PDT 24
Finished Jun 23 06:15:54 PM PDT 24
Peak memory 182228 kb
Host smart-31b28261-bd13-4efe-aedc-38f7126e17f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642993773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.642993773
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2401464370
Short name T520
Test name
Test status
Simulation time 16808445 ps
CPU time 0.54 seconds
Started Jun 23 06:15:55 PM PDT 24
Finished Jun 23 06:15:56 PM PDT 24
Peak memory 182584 kb
Host smart-14129df5-fc2c-4a56-895e-6aeb6a2f7d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401464370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2401464370
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1668909039
Short name T465
Test name
Test status
Simulation time 47332085 ps
CPU time 0.54 seconds
Started Jun 23 06:15:56 PM PDT 24
Finished Jun 23 06:15:57 PM PDT 24
Peak memory 182060 kb
Host smart-86a0d704-8059-4236-946e-62521c81c776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668909039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1668909039
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1827637433
Short name T538
Test name
Test status
Simulation time 15187041 ps
CPU time 0.61 seconds
Started Jun 23 06:15:55 PM PDT 24
Finished Jun 23 06:15:56 PM PDT 24
Peak memory 182544 kb
Host smart-4d6f84cd-ce2a-48dd-903c-958344dbc60a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827637433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1827637433
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3451967869
Short name T511
Test name
Test status
Simulation time 43072568 ps
CPU time 0.57 seconds
Started Jun 23 06:15:55 PM PDT 24
Finished Jun 23 06:15:56 PM PDT 24
Peak memory 182660 kb
Host smart-ebe9a2d6-2783-45d8-bbc5-e39e3609d83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451967869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3451967869
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2913124301
Short name T524
Test name
Test status
Simulation time 14985106 ps
CPU time 0.57 seconds
Started Jun 23 06:16:02 PM PDT 24
Finished Jun 23 06:16:03 PM PDT 24
Peak memory 182572 kb
Host smart-38f19a7d-face-405d-843f-ccfac7974e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913124301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2913124301
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1278214852
Short name T474
Test name
Test status
Simulation time 182945519 ps
CPU time 0.55 seconds
Started Jun 23 06:15:55 PM PDT 24
Finished Jun 23 06:15:56 PM PDT 24
Peak memory 182076 kb
Host smart-a0810563-39f6-401e-a1c7-a987984599af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278214852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1278214852
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2022665912
Short name T510
Test name
Test status
Simulation time 37393960 ps
CPU time 0.55 seconds
Started Jun 23 06:16:01 PM PDT 24
Finished Jun 23 06:16:02 PM PDT 24
Peak memory 182268 kb
Host smart-aa196524-825f-4876-8d5f-bdd9303d7179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022665912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2022665912
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1496209617
Short name T564
Test name
Test status
Simulation time 10735768 ps
CPU time 0.59 seconds
Started Jun 23 06:15:53 PM PDT 24
Finished Jun 23 06:15:54 PM PDT 24
Peak memory 182024 kb
Host smart-34f437c7-323d-470f-8018-545842dc3c61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496209617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1496209617
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.83533682
Short name T44
Test name
Test status
Simulation time 136004778 ps
CPU time 0.66 seconds
Started Jun 23 06:15:30 PM PDT 24
Finished Jun 23 06:15:31 PM PDT 24
Peak memory 191812 kb
Host smart-803752de-f367-4eef-b02b-8bd386b67371
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83533682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasi
ng.83533682
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4287648892
Short name T516
Test name
Test status
Simulation time 1199953583 ps
CPU time 2.33 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:42 PM PDT 24
Peak memory 191072 kb
Host smart-6dfcf036-577f-40cf-a598-56ddab96e900
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287648892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.4287648892
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3533141259
Short name T507
Test name
Test status
Simulation time 17467182 ps
CPU time 0.62 seconds
Started Jun 23 06:15:42 PM PDT 24
Finished Jun 23 06:15:43 PM PDT 24
Peak memory 182728 kb
Host smart-707b776a-c71a-4e07-9c57-7cb5bccf65ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533141259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3533141259
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.951256058
Short name T560
Test name
Test status
Simulation time 17128754 ps
CPU time 0.71 seconds
Started Jun 23 06:15:29 PM PDT 24
Finished Jun 23 06:15:31 PM PDT 24
Peak memory 193436 kb
Host smart-91b5d44b-6741-47c4-944c-7c5df728f3e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951256058 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.951256058
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1446539842
Short name T480
Test name
Test status
Simulation time 25583333 ps
CPU time 0.6 seconds
Started Jun 23 06:15:28 PM PDT 24
Finished Jun 23 06:15:29 PM PDT 24
Peak memory 182684 kb
Host smart-dccd0569-cc66-4f9b-bbfa-038e41ee229b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446539842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1446539842
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2271353022
Short name T458
Test name
Test status
Simulation time 17250129 ps
CPU time 0.59 seconds
Started Jun 23 06:15:30 PM PDT 24
Finished Jun 23 06:15:31 PM PDT 24
Peak memory 182692 kb
Host smart-8caa9714-fad4-4878-9483-38e30a20e8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271353022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2271353022
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3020202405
Short name T543
Test name
Test status
Simulation time 34363597 ps
CPU time 0.83 seconds
Started Jun 23 06:15:27 PM PDT 24
Finished Jun 23 06:15:28 PM PDT 24
Peak memory 193332 kb
Host smart-0f65be53-8038-4b3c-92f4-0bd6deb22573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020202405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3020202405
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3611611251
Short name T57
Test name
Test status
Simulation time 496851801 ps
CPU time 2.09 seconds
Started Jun 23 06:15:28 PM PDT 24
Finished Jun 23 06:15:30 PM PDT 24
Peak memory 197576 kb
Host smart-c159340b-c29b-450c-844f-79b20dc6b2e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611611251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3611611251
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1066230669
Short name T48
Test name
Test status
Simulation time 464646361 ps
CPU time 1.37 seconds
Started Jun 23 06:15:29 PM PDT 24
Finished Jun 23 06:15:31 PM PDT 24
Peak memory 183356 kb
Host smart-8e1fd91f-d787-4887-b3ed-bd9eb474c325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066230669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1066230669
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.71436456
Short name T553
Test name
Test status
Simulation time 26037574 ps
CPU time 0.55 seconds
Started Jun 23 06:15:55 PM PDT 24
Finished Jun 23 06:15:56 PM PDT 24
Peak memory 182500 kb
Host smart-37988324-cd48-4584-8675-1821ef031209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71436456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.71436456
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.284944670
Short name T466
Test name
Test status
Simulation time 50798148 ps
CPU time 0.56 seconds
Started Jun 23 06:15:54 PM PDT 24
Finished Jun 23 06:15:55 PM PDT 24
Peak memory 182532 kb
Host smart-465c95cd-7457-4c23-8c9a-8651de998cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284944670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.284944670
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4197372273
Short name T523
Test name
Test status
Simulation time 39861158 ps
CPU time 0.56 seconds
Started Jun 23 06:15:56 PM PDT 24
Finished Jun 23 06:15:57 PM PDT 24
Peak memory 182068 kb
Host smart-807924c3-deec-4a1e-b556-d63c14e4893a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197372273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4197372273
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1451794385
Short name T575
Test name
Test status
Simulation time 64736226 ps
CPU time 0.63 seconds
Started Jun 23 06:15:56 PM PDT 24
Finished Jun 23 06:15:57 PM PDT 24
Peak memory 182688 kb
Host smart-9ca4f64d-fc9b-4fb6-b54e-ec5d29f7f3c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451794385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1451794385
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3304354266
Short name T487
Test name
Test status
Simulation time 45725524 ps
CPU time 0.55 seconds
Started Jun 23 06:16:02 PM PDT 24
Finished Jun 23 06:16:03 PM PDT 24
Peak memory 182552 kb
Host smart-7e349231-6848-4f51-a405-635a43ee108a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304354266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3304354266
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.4161663386
Short name T545
Test name
Test status
Simulation time 26987918 ps
CPU time 0.59 seconds
Started Jun 23 06:15:56 PM PDT 24
Finished Jun 23 06:15:57 PM PDT 24
Peak memory 182068 kb
Host smart-e891145e-9544-44c2-9381-ab129027ffb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161663386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.4161663386
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1098174993
Short name T547
Test name
Test status
Simulation time 48178159 ps
CPU time 0.55 seconds
Started Jun 23 06:15:54 PM PDT 24
Finished Jun 23 06:15:55 PM PDT 24
Peak memory 182572 kb
Host smart-bec2335f-c1d7-4891-9f2a-51c741c7e98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098174993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1098174993
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3586146279
Short name T463
Test name
Test status
Simulation time 51543484 ps
CPU time 0.54 seconds
Started Jun 23 06:15:57 PM PDT 24
Finished Jun 23 06:15:58 PM PDT 24
Peak memory 182036 kb
Host smart-4f549652-0b53-4dc2-904f-95a1f30bd3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586146279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3586146279
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.113801109
Short name T568
Test name
Test status
Simulation time 16218106 ps
CPU time 0.53 seconds
Started Jun 23 06:15:56 PM PDT 24
Finished Jun 23 06:15:57 PM PDT 24
Peak memory 182232 kb
Host smart-f4de4f82-f674-4d36-91e8-4437aef58f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113801109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.113801109
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4122520525
Short name T535
Test name
Test status
Simulation time 14812143 ps
CPU time 0.55 seconds
Started Jun 23 06:15:54 PM PDT 24
Finished Jun 23 06:15:55 PM PDT 24
Peak memory 182560 kb
Host smart-bbd175e3-cef0-4c14-bc32-63ebc9e1575c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122520525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4122520525
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3501155249
Short name T47
Test name
Test status
Simulation time 116473413 ps
CPU time 0.77 seconds
Started Jun 23 06:15:33 PM PDT 24
Finished Jun 23 06:15:34 PM PDT 24
Peak memory 182716 kb
Host smart-a4a23ceb-257f-4021-9e99-755d2ef64e7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501155249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3501155249
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3718049714
Short name T484
Test name
Test status
Simulation time 1095610291 ps
CPU time 3.59 seconds
Started Jun 23 06:15:32 PM PDT 24
Finished Jun 23 06:15:36 PM PDT 24
Peak memory 191068 kb
Host smart-96a84a38-283c-4a61-b19b-be436f23e2a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718049714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3718049714
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3031407500
Short name T471
Test name
Test status
Simulation time 16126251 ps
CPU time 0.6 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 182144 kb
Host smart-cb3560d1-0e10-45e0-9edd-9ec8d5ab4161
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031407500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3031407500
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.789496825
Short name T469
Test name
Test status
Simulation time 64591709 ps
CPU time 0.91 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:41 PM PDT 24
Peak memory 197388 kb
Host smart-fb482b56-dddf-47f3-8e33-5eb5446b0c86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789496825 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.789496825
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4017207897
Short name T571
Test name
Test status
Simulation time 83946883 ps
CPU time 0.59 seconds
Started Jun 23 06:15:37 PM PDT 24
Finished Jun 23 06:15:39 PM PDT 24
Peak memory 182720 kb
Host smart-2f5bd302-167d-4a6e-96b5-d54def23b87b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017207897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.4017207897
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1769967373
Short name T514
Test name
Test status
Simulation time 51039100 ps
CPU time 0.53 seconds
Started Jun 23 06:15:37 PM PDT 24
Finished Jun 23 06:15:39 PM PDT 24
Peak memory 182588 kb
Host smart-bcbc3920-305e-44d9-b164-2f1245bf860b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769967373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1769967373
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1835559674
Short name T30
Test name
Test status
Simulation time 38301424 ps
CPU time 0.84 seconds
Started Jun 23 06:15:40 PM PDT 24
Finished Jun 23 06:15:42 PM PDT 24
Peak memory 193464 kb
Host smart-67d728cc-56b1-4ddb-b378-b5696420af8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835559674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1835559674
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1074860241
Short name T577
Test name
Test status
Simulation time 174597463 ps
CPU time 2.93 seconds
Started Jun 23 06:15:29 PM PDT 24
Finished Jun 23 06:15:32 PM PDT 24
Peak memory 197604 kb
Host smart-d14b94c4-0bea-44c8-a020-2b24f54a575d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074860241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1074860241
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3124639473
Short name T566
Test name
Test status
Simulation time 71188127 ps
CPU time 1.1 seconds
Started Jun 23 06:15:28 PM PDT 24
Finished Jun 23 06:15:29 PM PDT 24
Peak memory 195068 kb
Host smart-4f2e6ce0-45ba-4fcc-8e1d-943f26a38258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124639473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3124639473
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4244059807
Short name T477
Test name
Test status
Simulation time 13677951 ps
CPU time 0.55 seconds
Started Jun 23 06:15:57 PM PDT 24
Finished Jun 23 06:15:58 PM PDT 24
Peak memory 182060 kb
Host smart-6e6d98cb-5c28-4bc0-847d-d0c18e13f946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244059807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4244059807
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1697134863
Short name T499
Test name
Test status
Simulation time 35614247 ps
CPU time 0.55 seconds
Started Jun 23 06:15:57 PM PDT 24
Finished Jun 23 06:15:58 PM PDT 24
Peak memory 182592 kb
Host smart-af82cf2d-5f62-43e7-b73a-3182abf4bcbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697134863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1697134863
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3076370730
Short name T558
Test name
Test status
Simulation time 141272914 ps
CPU time 0.58 seconds
Started Jun 23 06:15:55 PM PDT 24
Finished Jun 23 06:15:56 PM PDT 24
Peak memory 182552 kb
Host smart-dac86a65-7fe8-4e24-b85c-575ef2548917
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076370730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3076370730
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2309711418
Short name T500
Test name
Test status
Simulation time 13740165 ps
CPU time 0.57 seconds
Started Jun 23 06:15:57 PM PDT 24
Finished Jun 23 06:15:58 PM PDT 24
Peak memory 182632 kb
Host smart-fc39df1e-990f-42e2-8a57-cfb127b085fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309711418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2309711418
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4042225966
Short name T467
Test name
Test status
Simulation time 14663168 ps
CPU time 0.56 seconds
Started Jun 23 06:15:56 PM PDT 24
Finished Jun 23 06:15:57 PM PDT 24
Peak memory 181844 kb
Host smart-520e8efc-ab0a-46f1-8f68-86d0f286bb46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042225966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4042225966
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1164053319
Short name T497
Test name
Test status
Simulation time 20048664 ps
CPU time 0.53 seconds
Started Jun 23 06:16:09 PM PDT 24
Finished Jun 23 06:16:10 PM PDT 24
Peak memory 182664 kb
Host smart-ac793729-9d54-42ce-a4c6-327565f7b06e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164053319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1164053319
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1407373923
Short name T567
Test name
Test status
Simulation time 97972100 ps
CPU time 0.58 seconds
Started Jun 23 06:16:01 PM PDT 24
Finished Jun 23 06:16:02 PM PDT 24
Peak memory 182664 kb
Host smart-88643d78-ead9-4a21-9a67-2c18b099b493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407373923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1407373923
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.825697440
Short name T456
Test name
Test status
Simulation time 15822156 ps
CPU time 0.57 seconds
Started Jun 23 06:15:58 PM PDT 24
Finished Jun 23 06:15:59 PM PDT 24
Peak memory 182572 kb
Host smart-5d40dbe1-2091-4f04-a658-cba46df316ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825697440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.825697440
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1744567079
Short name T462
Test name
Test status
Simulation time 11814782 ps
CPU time 0.56 seconds
Started Jun 23 06:15:59 PM PDT 24
Finished Jun 23 06:16:00 PM PDT 24
Peak memory 182312 kb
Host smart-5b136505-aed1-462d-bc19-f0db97b7ed99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744567079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1744567079
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3895263629
Short name T569
Test name
Test status
Simulation time 12808836 ps
CPU time 0.58 seconds
Started Jun 23 06:15:59 PM PDT 24
Finished Jun 23 06:16:00 PM PDT 24
Peak memory 182632 kb
Host smart-203a5eee-caa2-4d98-87a6-3bb38bde8f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895263629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3895263629
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.839068020
Short name T574
Test name
Test status
Simulation time 23723192 ps
CPU time 0.83 seconds
Started Jun 23 06:15:35 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 195712 kb
Host smart-f3bcec9b-3db6-4a75-b6c3-c669fe9eead8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839068020 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.839068020
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3294615286
Short name T70
Test name
Test status
Simulation time 42105883 ps
CPU time 0.57 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 182716 kb
Host smart-1e6e6ce2-298a-4a15-b78b-b5f53ed37b73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294615286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3294615286
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.565561606
Short name T529
Test name
Test status
Simulation time 52187370 ps
CPU time 0.59 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 182596 kb
Host smart-ae203a36-eb6c-40f0-a34e-013ba530b45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565561606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.565561606
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.268502867
Short name T46
Test name
Test status
Simulation time 27692695 ps
CPU time 0.71 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 191608 kb
Host smart-4338d002-a1de-4c4a-92eb-78f5a77b17bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268502867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.268502867
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2446760264
Short name T506
Test name
Test status
Simulation time 28898346 ps
CPU time 1.45 seconds
Started Jun 23 06:15:31 PM PDT 24
Finished Jun 23 06:15:33 PM PDT 24
Peak memory 197612 kb
Host smart-f8fb12ca-1e71-407a-95a1-475cd56579fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446760264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2446760264
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3179005164
Short name T27
Test name
Test status
Simulation time 250249675 ps
CPU time 1.06 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 194840 kb
Host smart-9038439a-6254-4ac7-85b5-5b9baf313c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179005164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3179005164
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2084156092
Short name T498
Test name
Test status
Simulation time 22115413 ps
CPU time 0.66 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 194288 kb
Host smart-f426c8ca-deae-4b26-a45f-cdeab52c698b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084156092 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2084156092
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4065213351
Short name T81
Test name
Test status
Simulation time 11853071 ps
CPU time 0.6 seconds
Started Jun 23 06:15:35 PM PDT 24
Finished Jun 23 06:15:36 PM PDT 24
Peak memory 182632 kb
Host smart-add12c9b-eef6-4e4d-be1d-e0573fbc3b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065213351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4065213351
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4085343763
Short name T472
Test name
Test status
Simulation time 12014175 ps
CPU time 0.55 seconds
Started Jun 23 06:15:37 PM PDT 24
Finished Jun 23 06:15:39 PM PDT 24
Peak memory 182100 kb
Host smart-bc85cda0-1d5f-47f1-9dd3-41f672e40b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085343763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4085343763
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1103030990
Short name T541
Test name
Test status
Simulation time 62122240 ps
CPU time 0.79 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 193176 kb
Host smart-6be998a9-6622-4f67-9c2c-cc8472120e5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103030990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1103030990
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3890107283
Short name T457
Test name
Test status
Simulation time 18686556 ps
CPU time 0.98 seconds
Started Jun 23 06:15:37 PM PDT 24
Finished Jun 23 06:15:38 PM PDT 24
Peak memory 195836 kb
Host smart-61599741-ab34-4ef3-9127-55974e2e2836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890107283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3890107283
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.974225359
Short name T544
Test name
Test status
Simulation time 273560397 ps
CPU time 1.35 seconds
Started Jun 23 06:15:35 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 183264 kb
Host smart-84bca7ef-5764-4361-9b8a-9a4f9888930f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974225359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.974225359
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2833275927
Short name T486
Test name
Test status
Simulation time 33505318 ps
CPU time 0.88 seconds
Started Jun 23 06:15:34 PM PDT 24
Finished Jun 23 06:15:36 PM PDT 24
Peak memory 196824 kb
Host smart-2034d793-c11a-42fc-8645-9eeb9cedfc13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833275927 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2833275927
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2826374266
Short name T79
Test name
Test status
Simulation time 25773645 ps
CPU time 0.59 seconds
Started Jun 23 06:15:38 PM PDT 24
Finished Jun 23 06:15:39 PM PDT 24
Peak memory 182716 kb
Host smart-0616eb38-57bd-472e-b82b-754f21d0984e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826374266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2826374266
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.4211573117
Short name T476
Test name
Test status
Simulation time 32039388 ps
CPU time 0.56 seconds
Started Jun 23 06:15:37 PM PDT 24
Finished Jun 23 06:15:38 PM PDT 24
Peak memory 182592 kb
Host smart-d8116bbd-6e83-426d-b7ff-1768e78f1122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211573117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.4211573117
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3625924023
Short name T72
Test name
Test status
Simulation time 15467173 ps
CPU time 0.61 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 191592 kb
Host smart-75cc9302-6ef8-42f5-8f40-8d63e2b1f7f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625924023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3625924023
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.660786225
Short name T482
Test name
Test status
Simulation time 94980804 ps
CPU time 2.47 seconds
Started Jun 23 06:15:40 PM PDT 24
Finished Jun 23 06:15:43 PM PDT 24
Peak memory 197624 kb
Host smart-3dfe0d49-6041-4315-8fbd-5c6abd9714a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660786225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.660786225
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1166701080
Short name T512
Test name
Test status
Simulation time 115155842 ps
CPU time 1.18 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 195316 kb
Host smart-6ea702ef-8ac3-4dd6-b50a-c8210a437603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166701080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1166701080
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.751953045
Short name T542
Test name
Test status
Simulation time 299760163 ps
CPU time 1.65 seconds
Started Jun 23 06:15:41 PM PDT 24
Finished Jun 23 06:15:43 PM PDT 24
Peak memory 197620 kb
Host smart-10bf39f3-d4ee-46fe-8d8d-2fc001a4b382
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751953045 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.751953045
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1493118364
Short name T549
Test name
Test status
Simulation time 22091086 ps
CPU time 0.53 seconds
Started Jun 23 06:15:36 PM PDT 24
Finished Jun 23 06:15:37 PM PDT 24
Peak memory 182072 kb
Host smart-6e5abd24-bbc5-45e3-81de-6042a590a143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493118364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1493118364
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2773638988
Short name T80
Test name
Test status
Simulation time 118884707 ps
CPU time 0.77 seconds
Started Jun 23 06:15:33 PM PDT 24
Finished Jun 23 06:15:34 PM PDT 24
Peak memory 193380 kb
Host smart-ad70724c-6ac4-453b-9851-3c4bb5792612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773638988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2773638988
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2054410276
Short name T481
Test name
Test status
Simulation time 235457128 ps
CPU time 1.51 seconds
Started Jun 23 06:15:38 PM PDT 24
Finished Jun 23 06:15:41 PM PDT 24
Peak memory 197572 kb
Host smart-b36c989d-b2e4-4649-9cf3-04a1f7c926ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054410276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2054410276
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2356324992
Short name T534
Test name
Test status
Simulation time 207158827 ps
CPU time 1.43 seconds
Started Jun 23 06:15:38 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 195008 kb
Host smart-c59f93c2-f6ef-4314-adc8-27030e677036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356324992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2356324992
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3446112361
Short name T455
Test name
Test status
Simulation time 81303457 ps
CPU time 1.08 seconds
Started Jun 23 06:15:38 PM PDT 24
Finished Jun 23 06:15:40 PM PDT 24
Peak memory 197456 kb
Host smart-5e7d197b-2abb-44d2-947e-5d61a72ed578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446112361 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3446112361
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.358569451
Short name T45
Test name
Test status
Simulation time 14596097 ps
CPU time 0.53 seconds
Started Jun 23 06:15:38 PM PDT 24
Finished Jun 23 06:15:39 PM PDT 24
Peak memory 182380 kb
Host smart-26a7f26b-6ab6-4022-914b-3327885da13c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358569451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.358569451
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2967983398
Short name T489
Test name
Test status
Simulation time 13007110 ps
CPU time 0.59 seconds
Started Jun 23 06:15:41 PM PDT 24
Finished Jun 23 06:15:42 PM PDT 24
Peak memory 182576 kb
Host smart-ca142c72-f802-4be8-8374-67c99aa03ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967983398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2967983398
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1761740554
Short name T68
Test name
Test status
Simulation time 18503772 ps
CPU time 0.78 seconds
Started Jun 23 06:15:40 PM PDT 24
Finished Jun 23 06:15:42 PM PDT 24
Peak memory 193324 kb
Host smart-758e1f35-cfc7-4fed-bc4a-e870324a84d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761740554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1761740554
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2049719620
Short name T565
Test name
Test status
Simulation time 100362112 ps
CPU time 1.86 seconds
Started Jun 23 06:15:45 PM PDT 24
Finished Jun 23 06:15:47 PM PDT 24
Peak memory 197620 kb
Host smart-f6fdea1e-304f-4c78-ab58-f5752198d48b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049719620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2049719620
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.759763616
Short name T58
Test name
Test status
Simulation time 154648367 ps
CPU time 1.19 seconds
Started Jun 23 06:15:39 PM PDT 24
Finished Jun 23 06:15:41 PM PDT 24
Peak memory 194080 kb
Host smart-a75d12ef-05c9-453b-9c88-4bee9a8e6183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759763616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.759763616
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2226326622
Short name T343
Test name
Test status
Simulation time 341742587003 ps
CPU time 278.1 seconds
Started Jun 23 05:29:51 PM PDT 24
Finished Jun 23 05:34:30 PM PDT 24
Peak memory 182976 kb
Host smart-185e78f0-7d35-4018-a141-6b76b5379911
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226326622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2226326622
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2019259438
Short name T389
Test name
Test status
Simulation time 104970411552 ps
CPU time 30.83 seconds
Started Jun 23 05:29:46 PM PDT 24
Finished Jun 23 05:30:17 PM PDT 24
Peak memory 183000 kb
Host smart-2a9ed429-b2e2-414b-9172-3d6c97653118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019259438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2019259438
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.531405945
Short name T383
Test name
Test status
Simulation time 157447693 ps
CPU time 0.77 seconds
Started Jun 23 05:29:42 PM PDT 24
Finished Jun 23 05:29:43 PM PDT 24
Peak memory 182728 kb
Host smart-b78afae1-826d-4975-b4db-c19ce72ac22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531405945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.531405945
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1316435280
Short name T63
Test name
Test status
Simulation time 96612715608 ps
CPU time 146.49 seconds
Started Jun 23 05:29:53 PM PDT 24
Finished Jun 23 05:32:19 PM PDT 24
Peak memory 191172 kb
Host smart-2bfb9127-c720-43b9-9dac-1bb2a3e52bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316435280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1316435280
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2137228143
Short name T435
Test name
Test status
Simulation time 422156545365 ps
CPU time 319.06 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:35:25 PM PDT 24
Peak memory 182996 kb
Host smart-3d4511f8-4e1c-4d23-9f06-fb408634d5f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137228143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2137228143
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1534085937
Short name T371
Test name
Test status
Simulation time 12317475464 ps
CPU time 17.27 seconds
Started Jun 23 05:29:58 PM PDT 24
Finished Jun 23 05:30:15 PM PDT 24
Peak memory 182988 kb
Host smart-0e90a9b1-6175-4675-9d4c-be05e94636de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534085937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1534085937
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.707754670
Short name T179
Test name
Test status
Simulation time 1151736047502 ps
CPU time 779.4 seconds
Started Jun 23 05:29:53 PM PDT 24
Finished Jun 23 05:42:53 PM PDT 24
Peak memory 191192 kb
Host smart-80491d20-97db-44d1-879e-d55559ad760f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707754670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.707754670
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2636339624
Short name T128
Test name
Test status
Simulation time 368288505496 ps
CPU time 566.32 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:39:31 PM PDT 24
Peak memory 191200 kb
Host smart-bfed9f2c-e268-4d5e-a20d-2c5902b22bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636339624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2636339624
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3253703264
Short name T14
Test name
Test status
Simulation time 41417880 ps
CPU time 0.76 seconds
Started Jun 23 05:29:58 PM PDT 24
Finished Jun 23 05:30:00 PM PDT 24
Peak memory 213852 kb
Host smart-7ec5c274-f3af-466e-baab-7784937eb348
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253703264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3253703264
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.4039147380
Short name T335
Test name
Test status
Simulation time 1530455644023 ps
CPU time 708.47 seconds
Started Jun 23 05:30:05 PM PDT 24
Finished Jun 23 05:41:55 PM PDT 24
Peak memory 182900 kb
Host smart-76bf169d-a631-46ed-9d86-a864e5105a57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039147380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.4039147380
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1688558120
Short name T395
Test name
Test status
Simulation time 607916642919 ps
CPU time 175.05 seconds
Started Jun 23 05:29:55 PM PDT 24
Finished Jun 23 05:32:51 PM PDT 24
Peak memory 182952 kb
Host smart-106e208f-dd47-4b8c-a2ff-0f30e81da229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688558120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1688558120
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1074178845
Short name T438
Test name
Test status
Simulation time 57663140274 ps
CPU time 20.4 seconds
Started Jun 23 05:30:00 PM PDT 24
Finished Jun 23 05:30:21 PM PDT 24
Peak memory 194640 kb
Host smart-b014f6c8-8fda-43c6-b584-b8899a58327b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074178845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1074178845
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.4113452842
Short name T106
Test name
Test status
Simulation time 674119053700 ps
CPU time 1225.62 seconds
Started Jun 23 05:31:13 PM PDT 24
Finished Jun 23 05:51:40 PM PDT 24
Peak memory 191076 kb
Host smart-6a7fb9a7-09e1-45bb-a4c7-54580a09a68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113452842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4113452842
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1772016164
Short name T96
Test name
Test status
Simulation time 285528049293 ps
CPU time 952.71 seconds
Started Jun 23 05:31:10 PM PDT 24
Finished Jun 23 05:47:04 PM PDT 24
Peak memory 191176 kb
Host smart-25d18ea0-bfe7-4993-8abe-4710df037251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772016164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1772016164
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.493143252
Short name T274
Test name
Test status
Simulation time 151041491777 ps
CPU time 67.59 seconds
Started Jun 23 05:31:17 PM PDT 24
Finished Jun 23 05:32:25 PM PDT 24
Peak memory 182968 kb
Host smart-ed284e14-0fa9-4e59-9afa-5e5a29932622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493143252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.493143252
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.651263152
Short name T94
Test name
Test status
Simulation time 476593722460 ps
CPU time 273.32 seconds
Started Jun 23 05:31:14 PM PDT 24
Finished Jun 23 05:35:47 PM PDT 24
Peak memory 191180 kb
Host smart-70b2a321-81ee-4db9-8700-15a5eca1d47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651263152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.651263152
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.475175941
Short name T40
Test name
Test status
Simulation time 152804052733 ps
CPU time 121.2 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:32:04 PM PDT 24
Peak memory 182836 kb
Host smart-84320a7a-b843-4cfb-9805-32591b79e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475175941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.475175941
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.712258869
Short name T320
Test name
Test status
Simulation time 106250680176 ps
CPU time 174.83 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:33:00 PM PDT 24
Peak memory 191184 kb
Host smart-6ac0bc6b-4a70-4482-8b3d-e4dc40981f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712258869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.712258869
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2712130489
Short name T310
Test name
Test status
Simulation time 125092719604 ps
CPU time 139.16 seconds
Started Jun 23 05:29:53 PM PDT 24
Finished Jun 23 05:32:12 PM PDT 24
Peak memory 183016 kb
Host smart-9be9d083-421a-4eed-b312-55ed8698d35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712130489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2712130489
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.2039091521
Short name T104
Test name
Test status
Simulation time 101468459315 ps
CPU time 172.67 seconds
Started Jun 23 05:31:15 PM PDT 24
Finished Jun 23 05:34:08 PM PDT 24
Peak memory 191192 kb
Host smart-70e35594-3b7c-4e3d-b682-23714cdb73f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039091521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2039091521
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2175162895
Short name T415
Test name
Test status
Simulation time 70448509616 ps
CPU time 61.82 seconds
Started Jun 23 05:31:21 PM PDT 24
Finished Jun 23 05:32:23 PM PDT 24
Peak memory 182984 kb
Host smart-92e5f8f2-19c4-414a-ba15-55ecbd2944b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175162895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2175162895
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1768644461
Short name T228
Test name
Test status
Simulation time 622499587405 ps
CPU time 219.13 seconds
Started Jun 23 05:31:21 PM PDT 24
Finished Jun 23 05:35:01 PM PDT 24
Peak memory 191168 kb
Host smart-eaa64007-4a16-420b-9eaf-d303b39272f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768644461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1768644461
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2822669626
Short name T103
Test name
Test status
Simulation time 1468676107691 ps
CPU time 451.19 seconds
Started Jun 23 05:29:56 PM PDT 24
Finished Jun 23 05:37:27 PM PDT 24
Peak memory 182976 kb
Host smart-af8a5f4e-0fc4-43f9-98f2-a7e8be9b344e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822669626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2822669626
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.999463761
Short name T434
Test name
Test status
Simulation time 147382123547 ps
CPU time 214.47 seconds
Started Jun 23 05:29:56 PM PDT 24
Finished Jun 23 05:33:31 PM PDT 24
Peak memory 182944 kb
Host smart-e780cf5c-30ee-440a-9cc4-90f0e0f371b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999463761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.999463761
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.479390477
Short name T325
Test name
Test status
Simulation time 163640316892 ps
CPU time 112.55 seconds
Started Jun 23 05:29:55 PM PDT 24
Finished Jun 23 05:31:48 PM PDT 24
Peak memory 182984 kb
Host smart-acf4df56-6fa3-469e-b15a-da6c7a93e8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479390477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.479390477
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1360438364
Short name T423
Test name
Test status
Simulation time 62031522 ps
CPU time 0.67 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:30:03 PM PDT 24
Peak memory 182788 kb
Host smart-d99dad90-9bf9-403b-b377-7b93978ee72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360438364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1360438364
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.584695133
Short name T144
Test name
Test status
Simulation time 432308228739 ps
CPU time 769.21 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:42:56 PM PDT 24
Peak memory 191188 kb
Host smart-2ba3dfdc-9ec0-47dc-b4ee-847a16bee3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584695133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
584695133
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2139672476
Short name T36
Test name
Test status
Simulation time 21278914442 ps
CPU time 230.41 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:33:57 PM PDT 24
Peak memory 205852 kb
Host smart-1cc7f018-0ea8-4cd4-9c11-57c92c8cc96b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139672476 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2139672476
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.1575240639
Short name T336
Test name
Test status
Simulation time 77260615822 ps
CPU time 34.4 seconds
Started Jun 23 05:31:21 PM PDT 24
Finished Jun 23 05:31:56 PM PDT 24
Peak memory 182992 kb
Host smart-fffdb19c-1fed-4d13-8469-8235abfe0cb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575240639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1575240639
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1113791695
Short name T198
Test name
Test status
Simulation time 88578608080 ps
CPU time 83.51 seconds
Started Jun 23 05:31:28 PM PDT 24
Finished Jun 23 05:32:52 PM PDT 24
Peak memory 191180 kb
Host smart-a79a1020-8887-42cc-bcfc-558d4b93649f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113791695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1113791695
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.396113356
Short name T127
Test name
Test status
Simulation time 50637112556 ps
CPU time 1805.63 seconds
Started Jun 23 05:31:28 PM PDT 24
Finished Jun 23 06:01:34 PM PDT 24
Peak memory 182996 kb
Host smart-cb85c276-12a3-4bbb-acf4-85733a6ab045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396113356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.396113356
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.205419446
Short name T296
Test name
Test status
Simulation time 269122875689 ps
CPU time 496.46 seconds
Started Jun 23 05:31:29 PM PDT 24
Finished Jun 23 05:39:45 PM PDT 24
Peak memory 194240 kb
Host smart-e1023566-02c0-4d16-a9bc-8dd196cfd8d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205419446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.205419446
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3577827578
Short name T39
Test name
Test status
Simulation time 80910944710 ps
CPU time 144.42 seconds
Started Jun 23 05:31:28 PM PDT 24
Finished Jun 23 05:33:53 PM PDT 24
Peak memory 191184 kb
Host smart-08f69607-7188-4209-b019-30acb83f9be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577827578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3577827578
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.728092196
Short name T442
Test name
Test status
Simulation time 210439705941 ps
CPU time 204.54 seconds
Started Jun 23 05:31:32 PM PDT 24
Finished Jun 23 05:34:57 PM PDT 24
Peak memory 191168 kb
Host smart-e64b4c8b-ff93-4f44-9c8a-eeef4651550f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728092196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.728092196
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4251468760
Short name T125
Test name
Test status
Simulation time 104671288536 ps
CPU time 164.12 seconds
Started Jun 23 05:29:54 PM PDT 24
Finished Jun 23 05:32:38 PM PDT 24
Peak memory 182980 kb
Host smart-3e5414a3-6d0b-4bcb-ace4-2dcbea7dc1bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251468760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4251468760
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1548828825
Short name T400
Test name
Test status
Simulation time 19209988576 ps
CPU time 30.58 seconds
Started Jun 23 05:30:01 PM PDT 24
Finished Jun 23 05:30:32 PM PDT 24
Peak memory 182960 kb
Host smart-04395cc3-11ea-4a42-95a5-ae45e5724fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548828825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1548828825
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.3132029885
Short name T120
Test name
Test status
Simulation time 138752562757 ps
CPU time 686.52 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:41:33 PM PDT 24
Peak memory 191180 kb
Host smart-b12df24a-7c86-447f-8bbc-ce31eeab4c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132029885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3132029885
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1278881240
Short name T54
Test name
Test status
Simulation time 96204137760 ps
CPU time 76.19 seconds
Started Jun 23 05:30:05 PM PDT 24
Finished Jun 23 05:31:22 PM PDT 24
Peak memory 194836 kb
Host smart-0c897e99-94a4-4bd7-a882-1c07350fbbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278881240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1278881240
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3767123915
Short name T272
Test name
Test status
Simulation time 39645803713 ps
CPU time 190.74 seconds
Started Jun 23 05:31:31 PM PDT 24
Finished Jun 23 05:34:42 PM PDT 24
Peak memory 191196 kb
Host smart-14561ad9-18da-488b-af30-0b16a4151b6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767123915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3767123915
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.725737563
Short name T189
Test name
Test status
Simulation time 31143035233 ps
CPU time 55.72 seconds
Started Jun 23 05:31:30 PM PDT 24
Finished Jun 23 05:32:26 PM PDT 24
Peak memory 182988 kb
Host smart-eb9c6a6a-b9fd-4db6-8a63-d11dd6d88b3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725737563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.725737563
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1650077296
Short name T115
Test name
Test status
Simulation time 707943961437 ps
CPU time 340.33 seconds
Started Jun 23 05:31:32 PM PDT 24
Finished Jun 23 05:37:13 PM PDT 24
Peak memory 191192 kb
Host smart-d3948e0b-2c81-4f49-8886-e7ad2a6b775e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650077296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1650077296
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1055841733
Short name T93
Test name
Test status
Simulation time 74410834014 ps
CPU time 734.24 seconds
Started Jun 23 05:31:32 PM PDT 24
Finished Jun 23 05:43:47 PM PDT 24
Peak memory 191092 kb
Host smart-013c6602-bbba-472f-8ec5-211b9a534aa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055841733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1055841733
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.36369420
Short name T176
Test name
Test status
Simulation time 97686088435 ps
CPU time 509.73 seconds
Started Jun 23 05:31:31 PM PDT 24
Finished Jun 23 05:40:01 PM PDT 24
Peak memory 191204 kb
Host smart-2b29761e-b215-4319-bf51-d00e01b2f5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36369420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.36369420
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1556047654
Short name T165
Test name
Test status
Simulation time 471816398621 ps
CPU time 703.11 seconds
Started Jun 23 05:31:36 PM PDT 24
Finished Jun 23 05:43:19 PM PDT 24
Peak memory 191180 kb
Host smart-7a36c430-853d-4ed9-99a8-ae3205e87cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556047654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1556047654
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2041940793
Short name T270
Test name
Test status
Simulation time 212299323614 ps
CPU time 178.32 seconds
Started Jun 23 05:31:35 PM PDT 24
Finished Jun 23 05:34:34 PM PDT 24
Peak memory 191184 kb
Host smart-1e128f3b-c136-433a-92a5-0131ba2ca9a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041940793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2041940793
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.451291222
Short name T319
Test name
Test status
Simulation time 169617216759 ps
CPU time 277.29 seconds
Started Jun 23 05:29:56 PM PDT 24
Finished Jun 23 05:34:34 PM PDT 24
Peak memory 182980 kb
Host smart-8b9e6dcd-570f-44a7-8c3d-cf59fc9f22ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451291222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.451291222
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.998665525
Short name T382
Test name
Test status
Simulation time 401587272918 ps
CPU time 141.03 seconds
Started Jun 23 05:30:05 PM PDT 24
Finished Jun 23 05:32:27 PM PDT 24
Peak memory 183000 kb
Host smart-b85895fb-946b-4721-a236-e615a8eebf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998665525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.998665525
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.4102484346
Short name T393
Test name
Test status
Simulation time 47449261918 ps
CPU time 53.95 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:30:59 PM PDT 24
Peak memory 182644 kb
Host smart-0cad2fa6-2b49-43ec-a23c-b6623ea80fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102484346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.4102484346
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.427437480
Short name T451
Test name
Test status
Simulation time 456834029518 ps
CPU time 200.3 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:33:23 PM PDT 24
Peak memory 191052 kb
Host smart-30ed91b1-1df9-4a6b-97c8-c5726211d181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427437480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.427437480
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3790853018
Short name T437
Test name
Test status
Simulation time 121106756556 ps
CPU time 64.29 seconds
Started Jun 23 05:31:42 PM PDT 24
Finished Jun 23 05:32:47 PM PDT 24
Peak memory 192212 kb
Host smart-2d623706-dbdb-4e20-8965-19de9c54c6a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790853018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3790853018
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2194348187
Short name T107
Test name
Test status
Simulation time 503340496892 ps
CPU time 378.56 seconds
Started Jun 23 05:31:40 PM PDT 24
Finished Jun 23 05:37:59 PM PDT 24
Peak memory 191184 kb
Host smart-4444c97c-909d-4497-a0a3-17e11d0642dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194348187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2194348187
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2484742574
Short name T260
Test name
Test status
Simulation time 440674615841 ps
CPU time 2012.07 seconds
Started Jun 23 05:31:41 PM PDT 24
Finished Jun 23 06:05:14 PM PDT 24
Peak memory 191180 kb
Host smart-e1c4c2d3-d449-48bb-8573-a97e094bd51f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484742574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2484742574
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.985295824
Short name T259
Test name
Test status
Simulation time 213244768794 ps
CPU time 108.12 seconds
Started Jun 23 05:31:44 PM PDT 24
Finished Jun 23 05:33:33 PM PDT 24
Peak memory 191160 kb
Host smart-68564503-ab0a-44cf-9b6a-b33c81e30b11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985295824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.985295824
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.4143798146
Short name T51
Test name
Test status
Simulation time 256075908796 ps
CPU time 109.6 seconds
Started Jun 23 05:31:45 PM PDT 24
Finished Jun 23 05:33:35 PM PDT 24
Peak memory 191168 kb
Host smart-7b66f8ab-952b-4922-b484-ff1e757a347e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143798146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.4143798146
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.4230984689
Short name T188
Test name
Test status
Simulation time 634676260859 ps
CPU time 510.38 seconds
Started Jun 23 05:31:47 PM PDT 24
Finished Jun 23 05:40:18 PM PDT 24
Peak memory 191092 kb
Host smart-9dad8259-a3d0-42c3-a503-bf090ad6d91a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230984689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4230984689
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3115822377
Short name T281
Test name
Test status
Simulation time 184277590974 ps
CPU time 301.31 seconds
Started Jun 23 05:31:50 PM PDT 24
Finished Jun 23 05:36:51 PM PDT 24
Peak memory 191192 kb
Host smart-fa568edf-7371-464a-8713-97c6474d0631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115822377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3115822377
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2537844103
Short name T2
Test name
Test status
Simulation time 50344125714 ps
CPU time 70.97 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:31:16 PM PDT 24
Peak memory 183000 kb
Host smart-1b472340-788f-41f3-9e5e-6424d24d2b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537844103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2537844103
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1094526031
Short name T433
Test name
Test status
Simulation time 57992054 ps
CPU time 0.67 seconds
Started Jun 23 05:29:54 PM PDT 24
Finished Jun 23 05:29:55 PM PDT 24
Peak memory 182764 kb
Host smart-ce845085-ae55-46b6-9e82-933a2083308e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094526031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1094526031
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3903732715
Short name T136
Test name
Test status
Simulation time 352042911372 ps
CPU time 1168.77 seconds
Started Jun 23 05:29:54 PM PDT 24
Finished Jun 23 05:49:24 PM PDT 24
Peak memory 191196 kb
Host smart-c8f32f97-2dab-45bd-b30c-a5ec99d75393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903732715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3903732715
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.2042463118
Short name T10
Test name
Test status
Simulation time 426502821965 ps
CPU time 516.63 seconds
Started Jun 23 05:31:49 PM PDT 24
Finished Jun 23 05:40:26 PM PDT 24
Peak memory 191168 kb
Host smart-a071cd0f-9efd-49b0-922e-ccdacc19e95e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042463118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2042463118
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1421220430
Short name T326
Test name
Test status
Simulation time 136975480987 ps
CPU time 65.09 seconds
Started Jun 23 05:31:50 PM PDT 24
Finished Jun 23 05:32:55 PM PDT 24
Peak memory 182880 kb
Host smart-a55f1dfc-3442-41d4-abc0-215b556f4dd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421220430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1421220430
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.4175345001
Short name T91
Test name
Test status
Simulation time 128003033139 ps
CPU time 527.27 seconds
Started Jun 23 05:31:50 PM PDT 24
Finished Jun 23 05:40:37 PM PDT 24
Peak memory 191192 kb
Host smart-39853d59-1c2d-4dce-91fa-b58a141dac7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175345001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4175345001
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1167320182
Short name T121
Test name
Test status
Simulation time 66606746567 ps
CPU time 280.54 seconds
Started Jun 23 05:31:51 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 191196 kb
Host smart-3a7cc69d-168d-432e-a1e9-552273eeee93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167320182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1167320182
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.861840939
Short name T205
Test name
Test status
Simulation time 168940475781 ps
CPU time 128.58 seconds
Started Jun 23 05:31:59 PM PDT 24
Finished Jun 23 05:34:07 PM PDT 24
Peak memory 182988 kb
Host smart-2ff77b80-e3ae-4135-9a1a-b13ba95d9595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861840939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.861840939
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.274996996
Short name T354
Test name
Test status
Simulation time 672856648986 ps
CPU time 244.36 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:34:09 PM PDT 24
Peak memory 182960 kb
Host smart-14529a48-31e7-476d-95d4-74bbb7b83098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274996996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.274996996
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.860158193
Short name T427
Test name
Test status
Simulation time 103142371 ps
CPU time 0.71 seconds
Started Jun 23 05:29:59 PM PDT 24
Finished Jun 23 05:30:00 PM PDT 24
Peak memory 182768 kb
Host smart-25597093-a8e3-4869-96ce-4abd8134c17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860158193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.860158193
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2076500868
Short name T34
Test name
Test status
Simulation time 60903977270 ps
CPU time 690.43 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:41:34 PM PDT 24
Peak memory 208540 kb
Host smart-e4f5acce-41b9-4887-ad9e-1edbee4c06e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076500868 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2076500868
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1809699705
Short name T351
Test name
Test status
Simulation time 343418431950 ps
CPU time 143.47 seconds
Started Jun 23 05:31:59 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 191084 kb
Host smart-60ad2230-3ef5-4cf1-a776-7f0faf0c7e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809699705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1809699705
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2600415299
Short name T421
Test name
Test status
Simulation time 111283900514 ps
CPU time 137.51 seconds
Started Jun 23 05:31:55 PM PDT 24
Finished Jun 23 05:34:13 PM PDT 24
Peak memory 191188 kb
Host smart-d880767f-52e6-46fb-99a4-6f12bfe2e347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600415299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2600415299
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1428963156
Short name T345
Test name
Test status
Simulation time 213951339371 ps
CPU time 103.3 seconds
Started Jun 23 05:31:54 PM PDT 24
Finished Jun 23 05:33:37 PM PDT 24
Peak memory 191192 kb
Host smart-7baf7a1f-b530-4457-a344-04fbc57983b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428963156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1428963156
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2351836700
Short name T153
Test name
Test status
Simulation time 403004849018 ps
CPU time 659.95 seconds
Started Jun 23 05:31:59 PM PDT 24
Finished Jun 23 05:42:59 PM PDT 24
Peak memory 191076 kb
Host smart-a39be24b-8b08-4e9a-8f2a-79499ffa0ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351836700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2351836700
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1604051246
Short name T403
Test name
Test status
Simulation time 145342101557 ps
CPU time 52.12 seconds
Started Jun 23 05:32:00 PM PDT 24
Finished Jun 23 05:32:52 PM PDT 24
Peak memory 182884 kb
Host smart-e0b781d6-18ba-4e3e-ac89-e05656d9bdd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604051246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1604051246
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3390890588
Short name T290
Test name
Test status
Simulation time 456874863356 ps
CPU time 694.04 seconds
Started Jun 23 05:31:58 PM PDT 24
Finished Jun 23 05:43:32 PM PDT 24
Peak memory 191044 kb
Host smart-874b8bb1-7799-4e07-99af-82ede069f9bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390890588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3390890588
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.554045650
Short name T222
Test name
Test status
Simulation time 135172403967 ps
CPU time 207.65 seconds
Started Jun 23 05:31:59 PM PDT 24
Finished Jun 23 05:35:27 PM PDT 24
Peak memory 191192 kb
Host smart-586f0556-95b5-42b4-a69f-15a12aa1d272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554045650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.554045650
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.356580946
Short name T392
Test name
Test status
Simulation time 17169459377 ps
CPU time 30.02 seconds
Started Jun 23 05:32:00 PM PDT 24
Finished Jun 23 05:32:30 PM PDT 24
Peak memory 182988 kb
Host smart-2f9d8229-543a-49eb-af31-be32441bf797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356580946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.356580946
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4024981594
Short name T267
Test name
Test status
Simulation time 109328649870 ps
CPU time 160.77 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:32:45 PM PDT 24
Peak memory 182940 kb
Host smart-5554148b-b1a0-4e5b-92aa-c7d2615b2d16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024981594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4024981594
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1421447075
Short name T56
Test name
Test status
Simulation time 632968735752 ps
CPU time 105.45 seconds
Started Jun 23 05:29:59 PM PDT 24
Finished Jun 23 05:31:45 PM PDT 24
Peak memory 183020 kb
Host smart-64c1fba8-90ab-403b-8182-aaa16e80d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421447075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1421447075
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.17790728
Short name T89
Test name
Test status
Simulation time 696715075931 ps
CPU time 1363.68 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:52:49 PM PDT 24
Peak memory 191084 kb
Host smart-2811e258-773a-4e8d-b3c7-00110ba62d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17790728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.17790728
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1111435494
Short name T53
Test name
Test status
Simulation time 67661014719 ps
CPU time 22.66 seconds
Started Jun 23 05:30:01 PM PDT 24
Finished Jun 23 05:30:24 PM PDT 24
Peak memory 183008 kb
Host smart-984a946d-9a13-4190-8774-56243e6ef432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111435494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1111435494
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2956099876
Short name T1
Test name
Test status
Simulation time 356413995823 ps
CPU time 261.33 seconds
Started Jun 23 05:29:59 PM PDT 24
Finished Jun 23 05:34:21 PM PDT 24
Peak memory 191180 kb
Host smart-4977e308-55fc-4bb5-a9ec-13375eeab073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956099876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2956099876
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2049534392
Short name T31
Test name
Test status
Simulation time 83342933950 ps
CPU time 654.67 seconds
Started Jun 23 05:30:11 PM PDT 24
Finished Jun 23 05:41:07 PM PDT 24
Peak memory 205724 kb
Host smart-4dd48f6b-8d03-4421-b233-4b73a5fb6106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049534392 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2049534392
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.1167825198
Short name T305
Test name
Test status
Simulation time 6529473414 ps
CPU time 11.16 seconds
Started Jun 23 05:32:00 PM PDT 24
Finished Jun 23 05:32:12 PM PDT 24
Peak memory 183196 kb
Host smart-9ae88f43-ee10-4d23-b88b-1f012eb1ac9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167825198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1167825198
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2647224248
Short name T339
Test name
Test status
Simulation time 872668489673 ps
CPU time 428.5 seconds
Started Jun 23 05:31:58 PM PDT 24
Finished Jun 23 05:39:07 PM PDT 24
Peak memory 191176 kb
Host smart-825d13d0-4e4f-4457-a341-4849c6083b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647224248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2647224248
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2813686301
Short name T21
Test name
Test status
Simulation time 448004536858 ps
CPU time 169.09 seconds
Started Jun 23 05:32:00 PM PDT 24
Finished Jun 23 05:34:49 PM PDT 24
Peak memory 191184 kb
Host smart-7aab262c-33a5-46d2-8922-854491ae0199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813686301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2813686301
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2367522516
Short name T218
Test name
Test status
Simulation time 368832801683 ps
CPU time 805.8 seconds
Started Jun 23 05:32:01 PM PDT 24
Finished Jun 23 05:45:27 PM PDT 24
Peak memory 191184 kb
Host smart-2d669c88-6bf6-44ec-b3e3-37e9b0eb9417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367522516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2367522516
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2415097746
Short name T183
Test name
Test status
Simulation time 165257744002 ps
CPU time 185.26 seconds
Started Jun 23 05:31:59 PM PDT 24
Finished Jun 23 05:35:04 PM PDT 24
Peak memory 191192 kb
Host smart-6aa151e1-2a05-490b-93de-631a757b70dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415097746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2415097746
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2454656664
Short name T265
Test name
Test status
Simulation time 6453869448 ps
CPU time 6.04 seconds
Started Jun 23 05:32:04 PM PDT 24
Finished Jun 23 05:32:10 PM PDT 24
Peak memory 182992 kb
Host smart-10a991e6-6f68-4040-af80-04c2ecfc5521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454656664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2454656664
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2712904396
Short name T55
Test name
Test status
Simulation time 185738905308 ps
CPU time 485.43 seconds
Started Jun 23 05:32:04 PM PDT 24
Finished Jun 23 05:40:10 PM PDT 24
Peak memory 191232 kb
Host smart-6d530d42-8379-46dc-bd39-4a61c509df8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712904396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2712904396
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2337668819
Short name T126
Test name
Test status
Simulation time 36242799232 ps
CPU time 88.06 seconds
Started Jun 23 05:32:05 PM PDT 24
Finished Jun 23 05:33:33 PM PDT 24
Peak memory 182964 kb
Host smart-800dd340-f012-4393-a3be-ced721d7a3d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337668819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2337668819
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4203355570
Short name T224
Test name
Test status
Simulation time 107198551505 ps
CPU time 165.29 seconds
Started Jun 23 05:32:06 PM PDT 24
Finished Jun 23 05:34:51 PM PDT 24
Peak memory 191068 kb
Host smart-9a18490d-5a63-439a-9e80-b6c8377751ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203355570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4203355570
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2197291728
Short name T341
Test name
Test status
Simulation time 111619582500 ps
CPU time 187 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:33:09 PM PDT 24
Peak memory 182980 kb
Host smart-42adaec3-431d-4561-a270-84f855d1d670
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197291728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2197291728
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.552002891
Short name T443
Test name
Test status
Simulation time 453121980213 ps
CPU time 160.61 seconds
Started Jun 23 05:30:20 PM PDT 24
Finished Jun 23 05:33:01 PM PDT 24
Peak memory 183000 kb
Host smart-e074f8fa-3459-49d9-a10c-a6241515779d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552002891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.552002891
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2214842599
Short name T441
Test name
Test status
Simulation time 60959152961 ps
CPU time 72.41 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:31:16 PM PDT 24
Peak memory 182980 kb
Host smart-fa6a0394-cd36-424e-8613-84a2e2f82b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214842599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2214842599
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3741405830
Short name T374
Test name
Test status
Simulation time 59860338241 ps
CPU time 76.16 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:31:21 PM PDT 24
Peak memory 182884 kb
Host smart-00b34da6-1019-4bf6-a878-b93051452061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741405830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3741405830
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.1084326854
Short name T214
Test name
Test status
Simulation time 310170893336 ps
CPU time 545.74 seconds
Started Jun 23 05:32:08 PM PDT 24
Finished Jun 23 05:41:14 PM PDT 24
Peak memory 193576 kb
Host smart-f638651b-b674-45cb-824e-9e865538e227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084326854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1084326854
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1171021194
Short name T131
Test name
Test status
Simulation time 160475912370 ps
CPU time 133.23 seconds
Started Jun 23 05:32:10 PM PDT 24
Finished Jun 23 05:34:23 PM PDT 24
Peak memory 194612 kb
Host smart-145c8457-9b53-4903-a639-2c06121b77ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171021194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1171021194
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.666569832
Short name T204
Test name
Test status
Simulation time 28063099937 ps
CPU time 43.55 seconds
Started Jun 23 05:32:10 PM PDT 24
Finished Jun 23 05:32:53 PM PDT 24
Peak memory 191172 kb
Host smart-b1039177-8d33-4d60-a0cd-d85f31533e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666569832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.666569832
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3952047364
Short name T241
Test name
Test status
Simulation time 294064470895 ps
CPU time 253.99 seconds
Started Jun 23 05:32:17 PM PDT 24
Finished Jun 23 05:36:31 PM PDT 24
Peak memory 191184 kb
Host smart-b11165fe-29f9-4520-92cb-5a7e6723a29d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952047364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3952047364
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1346945169
Short name T160
Test name
Test status
Simulation time 248294383619 ps
CPU time 179.08 seconds
Started Jun 23 05:32:15 PM PDT 24
Finished Jun 23 05:35:14 PM PDT 24
Peak memory 191144 kb
Host smart-5d579384-35d4-48ad-9827-f865fcf3a2ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346945169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1346945169
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3259049933
Short name T239
Test name
Test status
Simulation time 654486122785 ps
CPU time 1761.31 seconds
Started Jun 23 05:32:22 PM PDT 24
Finished Jun 23 06:01:44 PM PDT 24
Peak memory 191184 kb
Host smart-a79a1fde-a747-40b4-b7a6-b2be92ab4d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259049933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3259049933
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1385678539
Short name T275
Test name
Test status
Simulation time 352228542316 ps
CPU time 296.66 seconds
Started Jun 23 05:29:57 PM PDT 24
Finished Jun 23 05:34:54 PM PDT 24
Peak memory 182992 kb
Host smart-fa4f06ab-4f06-4bc2-b1d6-ebe8b578b633
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385678539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1385678539
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.331955535
Short name T388
Test name
Test status
Simulation time 55601070089 ps
CPU time 44.48 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:30:50 PM PDT 24
Peak memory 183008 kb
Host smart-0670ad14-8649-435f-8cef-31921eee000d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331955535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.331955535
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2438264821
Short name T308
Test name
Test status
Simulation time 47872261608 ps
CPU time 78.78 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:31:22 PM PDT 24
Peak memory 191196 kb
Host smart-1bfc0df6-61c4-4042-aea1-97598c606e98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438264821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2438264821
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2228996407
Short name T322
Test name
Test status
Simulation time 228630743834 ps
CPU time 333.64 seconds
Started Jun 23 05:30:12 PM PDT 24
Finished Jun 23 05:35:46 PM PDT 24
Peak memory 191200 kb
Host smart-5fa5d80e-15a3-4c18-a33a-af45f38e78c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228996407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2228996407
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1306304214
Short name T35
Test name
Test status
Simulation time 87273241209 ps
CPU time 653.39 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:40:59 PM PDT 24
Peak memory 207072 kb
Host smart-8519972e-8a89-4738-9ef7-36b4ffc97706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306304214 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1306304214
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.4113867281
Short name T350
Test name
Test status
Simulation time 703685366957 ps
CPU time 190.69 seconds
Started Jun 23 05:32:22 PM PDT 24
Finished Jun 23 05:35:33 PM PDT 24
Peak memory 191184 kb
Host smart-2f2b0d34-4880-47b6-a8c4-0a48451f079f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113867281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4113867281
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.942412831
Short name T327
Test name
Test status
Simulation time 92704435018 ps
CPU time 149.54 seconds
Started Jun 23 05:32:22 PM PDT 24
Finished Jun 23 05:34:52 PM PDT 24
Peak memory 194792 kb
Host smart-6812a62c-459b-4153-8f54-4a7d0ab9fd2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942412831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.942412831
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3601063873
Short name T234
Test name
Test status
Simulation time 172403408020 ps
CPU time 85.1 seconds
Started Jun 23 05:32:23 PM PDT 24
Finished Jun 23 05:33:48 PM PDT 24
Peak memory 191084 kb
Host smart-d1974af5-3e7d-4a6e-abd7-59c36b150336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601063873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3601063873
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1011644552
Short name T90
Test name
Test status
Simulation time 398912282609 ps
CPU time 411.94 seconds
Started Jun 23 05:32:22 PM PDT 24
Finished Jun 23 05:39:14 PM PDT 24
Peak memory 191172 kb
Host smart-7e75f0ce-1483-4cc5-bfb2-ddce1391c7ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011644552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1011644552
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2777616334
Short name T117
Test name
Test status
Simulation time 75301775316 ps
CPU time 303.03 seconds
Started Jun 23 05:32:27 PM PDT 24
Finished Jun 23 05:37:31 PM PDT 24
Peak memory 191192 kb
Host smart-a37f111e-03ea-4f8e-9a5e-95a30bc0c239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777616334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2777616334
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2139761397
Short name T352
Test name
Test status
Simulation time 61535892704 ps
CPU time 94.94 seconds
Started Jun 23 05:32:28 PM PDT 24
Finished Jun 23 05:34:04 PM PDT 24
Peak memory 194676 kb
Host smart-ca6de1fe-2d50-4fd7-a54f-a11ecd8e492d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139761397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2139761397
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.948965164
Short name T191
Test name
Test status
Simulation time 325618202271 ps
CPU time 714.02 seconds
Started Jun 23 05:32:27 PM PDT 24
Finished Jun 23 05:44:22 PM PDT 24
Peak memory 191196 kb
Host smart-7c61650a-6a26-406e-aadf-0e54e5eeead6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948965164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.948965164
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2107685076
Short name T208
Test name
Test status
Simulation time 834202428373 ps
CPU time 408.3 seconds
Started Jun 23 05:29:58 PM PDT 24
Finished Jun 23 05:36:47 PM PDT 24
Peak memory 182904 kb
Host smart-f9f708f0-64f3-4cec-b4a9-63cfa39c086e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107685076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2107685076
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.542441796
Short name T396
Test name
Test status
Simulation time 242863159165 ps
CPU time 116.22 seconds
Started Jun 23 05:29:48 PM PDT 24
Finished Jun 23 05:31:44 PM PDT 24
Peak memory 183012 kb
Host smart-96d4be5f-579f-43b4-85c1-94534df56d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542441796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.542441796
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2588299615
Short name T98
Test name
Test status
Simulation time 270769356481 ps
CPU time 171.82 seconds
Started Jun 23 05:29:51 PM PDT 24
Finished Jun 23 05:32:43 PM PDT 24
Peak memory 191196 kb
Host smart-6e5f1527-a9d1-4c45-867d-b111fc67d944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588299615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2588299615
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3974632593
Short name T16
Test name
Test status
Simulation time 327045362 ps
CPU time 1.12 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:30:06 PM PDT 24
Peak memory 215676 kb
Host smart-9ccd5702-b701-47b7-b414-34b63e8d56ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974632593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3974632593
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2175060956
Short name T32
Test name
Test status
Simulation time 90968009428 ps
CPU time 177.57 seconds
Started Jun 23 05:29:52 PM PDT 24
Finished Jun 23 05:32:50 PM PDT 24
Peak memory 205884 kb
Host smart-fe9ffc77-1a28-4d97-a914-368b5768fc1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175060956 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2175060956
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.548428586
Short name T306
Test name
Test status
Simulation time 18668185438 ps
CPU time 16.65 seconds
Started Jun 23 05:30:05 PM PDT 24
Finished Jun 23 05:30:23 PM PDT 24
Peak memory 182984 kb
Host smart-9b216bef-c99c-41e1-9bc5-1dc3292cc60c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548428586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.548428586
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2709125484
Short name T381
Test name
Test status
Simulation time 171376845086 ps
CPU time 62.41 seconds
Started Jun 23 05:30:01 PM PDT 24
Finished Jun 23 05:31:04 PM PDT 24
Peak memory 182996 kb
Host smart-60ee88c3-603f-45b5-9c96-3acd9d6de546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709125484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2709125484
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2438413659
Short name T116
Test name
Test status
Simulation time 76068052791 ps
CPU time 214.77 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:33:41 PM PDT 24
Peak memory 183008 kb
Host smart-bf3ec3f1-b469-484f-aca1-e7d17a097066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438413659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2438413659
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3302131461
Short name T3
Test name
Test status
Simulation time 82003911 ps
CPU time 0.65 seconds
Started Jun 23 05:30:01 PM PDT 24
Finished Jun 23 05:30:02 PM PDT 24
Peak memory 182648 kb
Host smart-d61809f8-9c36-4f93-a1b4-4eea3c2a1dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302131461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3302131461
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4253783508
Short name T170
Test name
Test status
Simulation time 491190826075 ps
CPU time 719.27 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:42:04 PM PDT 24
Peak memory 195856 kb
Host smart-66adb40d-4fa1-48a3-8d39-47ab41b85481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253783508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4253783508
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3957856061
Short name T425
Test name
Test status
Simulation time 462040511341 ps
CPU time 184.74 seconds
Started Jun 23 05:30:11 PM PDT 24
Finished Jun 23 05:33:17 PM PDT 24
Peak memory 182848 kb
Host smart-ba97b1d5-b333-4b27-aa06-77a93cbccb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957856061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3957856061
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1319658260
Short name T193
Test name
Test status
Simulation time 145594690620 ps
CPU time 612.08 seconds
Started Jun 23 05:29:57 PM PDT 24
Finished Jun 23 05:40:10 PM PDT 24
Peak memory 191188 kb
Host smart-91385251-8ea4-42c1-8d99-a6bc2c771bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319658260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1319658260
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4274657868
Short name T418
Test name
Test status
Simulation time 101301894175 ps
CPU time 45.14 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:30:49 PM PDT 24
Peak memory 183008 kb
Host smart-91bc63f0-64aa-43b9-a79e-e5d6e14a164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274657868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4274657868
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1138231272
Short name T135
Test name
Test status
Simulation time 153585948767 ps
CPU time 130.84 seconds
Started Jun 23 05:30:12 PM PDT 24
Finished Jun 23 05:32:23 PM PDT 24
Peak memory 182840 kb
Host smart-2d462876-b886-4fde-be09-23a34084bbab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138231272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1138231272
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3540631898
Short name T367
Test name
Test status
Simulation time 208348436999 ps
CPU time 164.84 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:32:58 PM PDT 24
Peak memory 182848 kb
Host smart-8e501b77-ca10-4bad-a4ac-74e1009bf71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540631898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3540631898
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1429873428
Short name T209
Test name
Test status
Simulation time 81967862257 ps
CPU time 115.64 seconds
Started Jun 23 05:29:59 PM PDT 24
Finished Jun 23 05:31:55 PM PDT 24
Peak memory 191156 kb
Host smart-7bdae309-dddc-4869-b065-98c0a8ee5684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429873428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1429873428
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3448056405
Short name T258
Test name
Test status
Simulation time 282543768334 ps
CPU time 134.04 seconds
Started Jun 23 05:30:01 PM PDT 24
Finished Jun 23 05:32:15 PM PDT 24
Peak memory 182984 kb
Host smart-49d8c115-013a-41c2-b004-cb8d5485f0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448056405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3448056405
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3823918654
Short name T118
Test name
Test status
Simulation time 552748773215 ps
CPU time 261.31 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:34:35 PM PDT 24
Peak memory 191040 kb
Host smart-aead840a-520d-4522-8d48-6db224c52df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823918654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3823918654
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.615658119
Short name T149
Test name
Test status
Simulation time 66731151737 ps
CPU time 110.62 seconds
Started Jun 23 05:30:12 PM PDT 24
Finished Jun 23 05:32:03 PM PDT 24
Peak memory 182836 kb
Host smart-c0df04ae-d0cc-4508-a72b-73dbbf744f72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615658119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.615658119
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2899050698
Short name T398
Test name
Test status
Simulation time 208151569355 ps
CPU time 157.41 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:32:41 PM PDT 24
Peak memory 182996 kb
Host smart-1b6b028b-859b-484b-abe9-b3a3c98d1048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899050698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2899050698
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2253089949
Short name T151
Test name
Test status
Simulation time 311908615339 ps
CPU time 606.38 seconds
Started Jun 23 05:30:07 PM PDT 24
Finished Jun 23 05:40:14 PM PDT 24
Peak memory 191188 kb
Host smart-c4896042-05ab-49d7-a720-18a0b9352f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253089949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2253089949
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2083524146
Short name T416
Test name
Test status
Simulation time 382280154496 ps
CPU time 93.15 seconds
Started Jun 23 05:30:00 PM PDT 24
Finished Jun 23 05:31:33 PM PDT 24
Peak memory 191184 kb
Host smart-a3c9cbf5-2fa1-4ebd-ba78-1686e299775d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083524146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2083524146
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3812276581
Short name T247
Test name
Test status
Simulation time 14884640784 ps
CPU time 13.32 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:30:19 PM PDT 24
Peak memory 182988 kb
Host smart-75184ee3-f61d-40ac-b902-dfd6b8e3cf44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812276581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3812276581
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4023069454
Short name T385
Test name
Test status
Simulation time 110347667339 ps
CPU time 154.34 seconds
Started Jun 23 05:30:09 PM PDT 24
Finished Jun 23 05:32:44 PM PDT 24
Peak memory 183180 kb
Host smart-7fa57603-00cd-450e-adcd-8f168f8aa9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023069454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4023069454
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1430608647
Short name T408
Test name
Test status
Simulation time 291234387153 ps
CPU time 255.22 seconds
Started Jun 23 05:30:12 PM PDT 24
Finished Jun 23 05:34:28 PM PDT 24
Peak memory 182836 kb
Host smart-86d626ea-812b-4ed0-8c7f-6f9fec962dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430608647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1430608647
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2261404299
Short name T353
Test name
Test status
Simulation time 38530872 ps
CPU time 0.53 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:30:16 PM PDT 24
Peak memory 182652 kb
Host smart-72b0988d-cc86-4824-b4fc-c1df1741d516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261404299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2261404299
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2648386568
Short name T12
Test name
Test status
Simulation time 18579293505 ps
CPU time 151.18 seconds
Started Jun 23 05:30:07 PM PDT 24
Finished Jun 23 05:32:39 PM PDT 24
Peak memory 197680 kb
Host smart-b19d78a5-d672-49c6-9946-29c07440faf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648386568 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2648386568
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.970125462
Short name T356
Test name
Test status
Simulation time 197419795903 ps
CPU time 76.37 seconds
Started Jun 23 05:30:08 PM PDT 24
Finished Jun 23 05:31:25 PM PDT 24
Peak memory 183000 kb
Host smart-34d0ab97-1cf6-4644-9158-7e45a01baa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970125462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.970125462
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3629598952
Short name T347
Test name
Test status
Simulation time 202302592986 ps
CPU time 67.4 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:31:21 PM PDT 24
Peak memory 182992 kb
Host smart-2529bca1-ef36-4086-b3b7-01304b9322ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629598952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3629598952
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3587432784
Short name T432
Test name
Test status
Simulation time 39704865811 ps
CPU time 17.13 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:30:21 PM PDT 24
Peak memory 191208 kb
Host smart-b4ab4213-7a77-47ce-8cc0-ae4bc715d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587432784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3587432784
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3604764518
Short name T238
Test name
Test status
Simulation time 241280326227 ps
CPU time 413.24 seconds
Started Jun 23 05:30:05 PM PDT 24
Finished Jun 23 05:36:59 PM PDT 24
Peak memory 191120 kb
Host smart-57bc6eb9-0bb0-48f7-8638-47d3247c8cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604764518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3604764518
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2903158370
Short name T201
Test name
Test status
Simulation time 201116980647 ps
CPU time 180.18 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:33:16 PM PDT 24
Peak memory 182984 kb
Host smart-631e3ca6-48ed-4338-a4fd-14204b142a78
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903158370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2903158370
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1133474570
Short name T370
Test name
Test status
Simulation time 301220083844 ps
CPU time 249.05 seconds
Started Jun 23 05:30:08 PM PDT 24
Finished Jun 23 05:34:18 PM PDT 24
Peak memory 183008 kb
Host smart-9329bb17-acf6-42cc-9ff8-3b7dcbef7a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133474570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1133474570
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2530905503
Short name T294
Test name
Test status
Simulation time 191119374657 ps
CPU time 513.2 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:38:40 PM PDT 24
Peak memory 191188 kb
Host smart-061b1fce-457a-4d4d-b78a-5aeab1d37f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530905503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2530905503
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2587248214
Short name T111
Test name
Test status
Simulation time 89108970123 ps
CPU time 740.39 seconds
Started Jun 23 05:30:10 PM PDT 24
Finished Jun 23 05:42:31 PM PDT 24
Peak memory 194696 kb
Host smart-2c6f99a8-512b-499e-a6c8-936b7b81787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587248214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2587248214
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3076359022
Short name T276
Test name
Test status
Simulation time 581307213068 ps
CPU time 423.38 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:37:08 PM PDT 24
Peak memory 191148 kb
Host smart-8953c4fb-7f4a-4960-8396-d6ea9a1462ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076359022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3076359022
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2881003795
Short name T449
Test name
Test status
Simulation time 857309063066 ps
CPU time 266.16 seconds
Started Jun 23 05:30:05 PM PDT 24
Finished Jun 23 05:34:33 PM PDT 24
Peak memory 183008 kb
Host smart-ccbdbdbb-596a-43d5-8c99-49b8449de787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881003795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2881003795
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1978004687
Short name T430
Test name
Test status
Simulation time 88054059909 ps
CPU time 165 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:32:52 PM PDT 24
Peak memory 190788 kb
Host smart-831fdfac-34f0-4288-b7a7-59829258c252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978004687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1978004687
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.4234884487
Short name T340
Test name
Test status
Simulation time 20183846812 ps
CPU time 14.81 seconds
Started Jun 23 05:30:09 PM PDT 24
Finished Jun 23 05:30:24 PM PDT 24
Peak memory 194452 kb
Host smart-afb46138-cd07-4b46-8150-ff1492f4591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234884487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4234884487
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2145086494
Short name T409
Test name
Test status
Simulation time 704704103257 ps
CPU time 195.38 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:33:21 PM PDT 24
Peak memory 183008 kb
Host smart-233d548a-2434-4ffd-9f4e-96ea6923dacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145086494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2145086494
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.924741693
Short name T250
Test name
Test status
Simulation time 98529440768 ps
CPU time 501.66 seconds
Started Jun 23 05:30:11 PM PDT 24
Finished Jun 23 05:38:34 PM PDT 24
Peak memory 191168 kb
Host smart-675abb8f-3e02-4dca-b2b1-a0a21ba016ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924741693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.924741693
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2507493551
Short name T264
Test name
Test status
Simulation time 57006950431 ps
CPU time 35.61 seconds
Started Jun 23 05:30:11 PM PDT 24
Finished Jun 23 05:30:47 PM PDT 24
Peak memory 191220 kb
Host smart-63f08f11-a57c-4d58-9ed4-5c651a3cadb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507493551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2507493551
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.688899037
Short name T402
Test name
Test status
Simulation time 194738245159 ps
CPU time 42.43 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:30:47 PM PDT 24
Peak memory 194864 kb
Host smart-3d58cd31-ec52-40cb-9ebf-faa05d72dfc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688899037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
688899037
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3397883023
Short name T426
Test name
Test status
Simulation time 91974238757 ps
CPU time 36.96 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:30:42 PM PDT 24
Peak memory 183008 kb
Host smart-776cfcc5-33a0-4a26-adeb-8bf54ff5e364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397883023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3397883023
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2938525835
Short name T138
Test name
Test status
Simulation time 623094770670 ps
CPU time 452.14 seconds
Started Jun 23 05:30:07 PM PDT 24
Finished Jun 23 05:37:39 PM PDT 24
Peak memory 191196 kb
Host smart-f13e5e72-28e8-46f1-a55c-69be112154ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938525835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2938525835
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1907090379
Short name T344
Test name
Test status
Simulation time 252275319903 ps
CPU time 134.68 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:32:20 PM PDT 24
Peak memory 191216 kb
Host smart-addfdbaa-4b5a-4d68-b9ad-ce33938e8d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907090379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1907090379
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.201086932
Short name T447
Test name
Test status
Simulation time 609565118799 ps
CPU time 882.16 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:44:46 PM PDT 24
Peak memory 191176 kb
Host smart-be0be867-25d3-4ead-af3c-4f3e34533154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201086932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
201086932
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2963269407
Short name T114
Test name
Test status
Simulation time 70351727105 ps
CPU time 35.2 seconds
Started Jun 23 05:29:57 PM PDT 24
Finished Jun 23 05:30:33 PM PDT 24
Peak memory 182996 kb
Host smart-96b5f0f3-b08d-488f-bcea-c03140983102
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963269407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2963269407
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3137980646
Short name T49
Test name
Test status
Simulation time 105335691294 ps
CPU time 126.95 seconds
Started Jun 23 05:29:53 PM PDT 24
Finished Jun 23 05:32:01 PM PDT 24
Peak memory 182996 kb
Host smart-29d8cc5d-0fcc-41f2-94e0-2416f1a84be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137980646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3137980646
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.262638970
Short name T134
Test name
Test status
Simulation time 185253989424 ps
CPU time 806.48 seconds
Started Jun 23 05:29:51 PM PDT 24
Finished Jun 23 05:43:18 PM PDT 24
Peak memory 191092 kb
Host smart-f432064a-cd8c-4bcf-b905-7ab05c27d460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262638970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.262638970
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3866290272
Short name T300
Test name
Test status
Simulation time 6937318840 ps
CPU time 11.03 seconds
Started Jun 23 05:30:00 PM PDT 24
Finished Jun 23 05:30:12 PM PDT 24
Peak memory 183012 kb
Host smart-369ae23f-34ab-4194-b092-658cef72a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866290272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3866290272
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.4070172152
Short name T17
Test name
Test status
Simulation time 232301411 ps
CPU time 0.76 seconds
Started Jun 23 05:29:51 PM PDT 24
Finished Jun 23 05:29:52 PM PDT 24
Peak memory 213812 kb
Host smart-c3040a17-9db7-43ff-859b-06f0a14ebd7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070172152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4070172152
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1783907107
Short name T391
Test name
Test status
Simulation time 158541600 ps
CPU time 0.75 seconds
Started Jun 23 05:29:54 PM PDT 24
Finished Jun 23 05:29:55 PM PDT 24
Peak memory 182736 kb
Host smart-81a30168-a008-4242-9d43-34f836689d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783907107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1783907107
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3997636364
Short name T132
Test name
Test status
Simulation time 35518338931 ps
CPU time 61.89 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:31:07 PM PDT 24
Peak memory 182992 kb
Host smart-3cb700e9-dcf3-4030-b370-81b7ecfff5a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997636364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3997636364
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3197778535
Short name T401
Test name
Test status
Simulation time 23763042356 ps
CPU time 36.04 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:30:51 PM PDT 24
Peak memory 182980 kb
Host smart-6d692376-c44b-4708-873f-8cbfa7d490c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197778535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3197778535
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1677345947
Short name T299
Test name
Test status
Simulation time 183095169716 ps
CPU time 76.59 seconds
Started Jun 23 05:30:05 PM PDT 24
Finished Jun 23 05:31:22 PM PDT 24
Peak memory 191076 kb
Host smart-ab40860b-32f4-4787-9f09-023fd2abc818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677345947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1677345947
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2527334037
Short name T253
Test name
Test status
Simulation time 150628407530 ps
CPU time 75.33 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:31:33 PM PDT 24
Peak memory 183000 kb
Host smart-55d2d06e-4b25-407a-a6fa-c88bc9c1e9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527334037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2527334037
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2150776737
Short name T119
Test name
Test status
Simulation time 1213492642470 ps
CPU time 475.37 seconds
Started Jun 23 05:30:14 PM PDT 24
Finished Jun 23 05:38:10 PM PDT 24
Peak memory 191084 kb
Host smart-dde1761a-328f-4b61-aa86-5a66f534263f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150776737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2150776737
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1770749664
Short name T11
Test name
Test status
Simulation time 32306721452 ps
CPU time 361.12 seconds
Started Jun 23 05:30:10 PM PDT 24
Finished Jun 23 05:36:12 PM PDT 24
Peak memory 205832 kb
Host smart-8fea42d9-9ba9-44c8-bc95-51e561ce1e94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770749664 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1770749664
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.574477852
Short name T379
Test name
Test status
Simulation time 51879229312 ps
CPU time 61.9 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:31:17 PM PDT 24
Peak memory 182980 kb
Host smart-11df30c3-6e2e-41b6-83c2-a1bb73ec2260
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574477852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.574477852
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1345340042
Short name T366
Test name
Test status
Simulation time 98756853066 ps
CPU time 69.35 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:31:25 PM PDT 24
Peak memory 183008 kb
Host smart-c4058fab-df68-4d90-9768-3ba09aae1311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345340042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1345340042
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.363075349
Short name T361
Test name
Test status
Simulation time 325243737 ps
CPU time 0.61 seconds
Started Jun 23 05:30:14 PM PDT 24
Finished Jun 23 05:30:15 PM PDT 24
Peak memory 182760 kb
Host smart-61af6e0e-4879-4ce5-aa8d-2e1828e846f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363075349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.363075349
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1983066024
Short name T346
Test name
Test status
Simulation time 230529053995 ps
CPU time 1547.37 seconds
Started Jun 23 05:30:07 PM PDT 24
Finished Jun 23 05:55:55 PM PDT 24
Peak memory 191196 kb
Host smart-5ca0c9cd-5295-421d-b5ac-378f66f5c40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983066024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1983066024
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.586646731
Short name T9
Test name
Test status
Simulation time 16358432571 ps
CPU time 7.28 seconds
Started Jun 23 05:30:14 PM PDT 24
Finished Jun 23 05:30:22 PM PDT 24
Peak memory 182992 kb
Host smart-9e09ecb3-7ad0-4727-bf09-2e631511520d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586646731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.586646731
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.40331388
Short name T428
Test name
Test status
Simulation time 171755228996 ps
CPU time 163.31 seconds
Started Jun 23 05:30:10 PM PDT 24
Finished Jun 23 05:32:54 PM PDT 24
Peak memory 182960 kb
Host smart-3475570e-d095-40da-8e4f-dcfc5a5cba0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40331388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.40331388
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1637442019
Short name T445
Test name
Test status
Simulation time 532162662790 ps
CPU time 202.16 seconds
Started Jun 23 05:30:16 PM PDT 24
Finished Jun 23 05:33:38 PM PDT 24
Peak memory 182996 kb
Host smart-4fb4881f-8fb3-46a0-a0d6-021bfcd1de7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637442019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1637442019
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.458556488
Short name T229
Test name
Test status
Simulation time 84386644515 ps
CPU time 138.03 seconds
Started Jun 23 05:30:12 PM PDT 24
Finished Jun 23 05:32:31 PM PDT 24
Peak memory 191212 kb
Host smart-2a5b4a0e-81ac-4924-bf44-d223179eeaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458556488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.458556488
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2789308644
Short name T417
Test name
Test status
Simulation time 40990820 ps
CPU time 0.56 seconds
Started Jun 23 05:30:09 PM PDT 24
Finished Jun 23 05:30:10 PM PDT 24
Peak memory 182248 kb
Host smart-80717607-35e6-4bd2-98f8-7e15111f0ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789308644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2789308644
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3929486600
Short name T225
Test name
Test status
Simulation time 263881106139 ps
CPU time 134.39 seconds
Started Jun 23 05:30:09 PM PDT 24
Finished Jun 23 05:32:24 PM PDT 24
Peak memory 182984 kb
Host smart-3b80b7a5-e87f-4a81-8661-f470ba3fcea0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929486600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3929486600
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2533651515
Short name T404
Test name
Test status
Simulation time 78589562847 ps
CPU time 115.38 seconds
Started Jun 23 05:30:11 PM PDT 24
Finished Jun 23 05:32:07 PM PDT 24
Peak memory 183008 kb
Host smart-de7b4fab-2b24-4a70-9af4-1de2aca21aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533651515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2533651515
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.840872403
Short name T180
Test name
Test status
Simulation time 512005025317 ps
CPU time 291.78 seconds
Started Jun 23 05:30:10 PM PDT 24
Finished Jun 23 05:35:02 PM PDT 24
Peak memory 193856 kb
Host smart-41d2ecd1-323a-45d2-be10-5c785add0362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840872403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.840872403
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1778061094
Short name T38
Test name
Test status
Simulation time 27970310844 ps
CPU time 26.22 seconds
Started Jun 23 05:30:10 PM PDT 24
Finished Jun 23 05:30:37 PM PDT 24
Peak memory 191216 kb
Host smart-6665c52e-7728-428d-b234-cda7d1cb4308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778061094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1778061094
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3704394683
Short name T397
Test name
Test status
Simulation time 677889632628 ps
CPU time 331.99 seconds
Started Jun 23 05:30:10 PM PDT 24
Finished Jun 23 05:35:43 PM PDT 24
Peak memory 182880 kb
Host smart-8db867a3-cf97-4348-b25b-02136737c8c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704394683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3704394683
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.692838424
Short name T411
Test name
Test status
Simulation time 57310764812 ps
CPU time 43.39 seconds
Started Jun 23 05:30:08 PM PDT 24
Finished Jun 23 05:30:52 PM PDT 24
Peak memory 183012 kb
Host smart-1c0e604a-a9c9-4954-9069-47ad8fb73885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692838424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.692838424
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.4144303509
Short name T291
Test name
Test status
Simulation time 75506109639 ps
CPU time 124.18 seconds
Started Jun 23 05:30:12 PM PDT 24
Finished Jun 23 05:32:17 PM PDT 24
Peak memory 190552 kb
Host smart-7ad4d8bd-a63e-442f-8ae5-baf89d645dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144303509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.4144303509
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3153166418
Short name T203
Test name
Test status
Simulation time 725171078921 ps
CPU time 167.42 seconds
Started Jun 23 05:30:08 PM PDT 24
Finished Jun 23 05:32:56 PM PDT 24
Peak memory 183008 kb
Host smart-7ef503bf-7ca7-4ff2-af04-741461d7c816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153166418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3153166418
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1314429481
Short name T61
Test name
Test status
Simulation time 236022739501 ps
CPU time 727.24 seconds
Started Jun 23 05:30:14 PM PDT 24
Finished Jun 23 05:42:22 PM PDT 24
Peak memory 194764 kb
Host smart-8e1da93d-4f16-4cb7-bbe7-dbaebfe62781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314429481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1314429481
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.666051742
Short name T88
Test name
Test status
Simulation time 27633693798 ps
CPU time 42.26 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:30:56 PM PDT 24
Peak memory 182976 kb
Host smart-e6850c4b-e835-43a0-8877-0d56c187ef6f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666051742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.666051742
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.4288513794
Short name T358
Test name
Test status
Simulation time 103999648236 ps
CPU time 145.8 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:32:40 PM PDT 24
Peak memory 182960 kb
Host smart-41a5deb3-3acb-410d-9cac-bab8295a6d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288513794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4288513794
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.828425720
Short name T174
Test name
Test status
Simulation time 786665447786 ps
CPU time 765.83 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:43:00 PM PDT 24
Peak memory 191168 kb
Host smart-7f5b7606-8dd2-49f9-86a1-6eb447c11ccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828425720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.828425720
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1017329694
Short name T368
Test name
Test status
Simulation time 174885667 ps
CPU time 0.51 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:30:19 PM PDT 24
Peak memory 182536 kb
Host smart-22c8a641-4b85-4b6d-8472-bd0d44d5e0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017329694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1017329694
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1861538371
Short name T363
Test name
Test status
Simulation time 240010130061 ps
CPU time 154.33 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:32:48 PM PDT 24
Peak memory 182996 kb
Host smart-79298a41-9e91-4b4b-8730-99d56e285f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861538371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1861538371
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2030841951
Short name T446
Test name
Test status
Simulation time 14857329458 ps
CPU time 21.72 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:30:37 PM PDT 24
Peak memory 182984 kb
Host smart-b9acacc1-482b-4b97-8f7d-e09306b4bd93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030841951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2030841951
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1856539858
Short name T384
Test name
Test status
Simulation time 147284117440 ps
CPU time 203.01 seconds
Started Jun 23 05:30:14 PM PDT 24
Finished Jun 23 05:33:37 PM PDT 24
Peak memory 182996 kb
Host smart-d7458d90-8bdb-4c3b-aa19-4e502a92f8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856539858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1856539858
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3252719376
Short name T431
Test name
Test status
Simulation time 304117452859 ps
CPU time 590.55 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:40:05 PM PDT 24
Peak memory 191196 kb
Host smart-996290b1-f274-4d34-aeb1-2d5d69224893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252719376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3252719376
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2641297324
Short name T387
Test name
Test status
Simulation time 10957781877 ps
CPU time 19.62 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:30:35 PM PDT 24
Peak memory 183000 kb
Host smart-907f3d93-2af3-4c4e-acc8-47df06a7ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641297324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2641297324
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3778463830
Short name T313
Test name
Test status
Simulation time 328791282503 ps
CPU time 540.62 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:39:19 PM PDT 24
Peak memory 191196 kb
Host smart-36e741de-17d4-410a-85be-6a060e12e694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778463830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3778463830
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.493587056
Short name T227
Test name
Test status
Simulation time 588983970204 ps
CPU time 563.04 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:39:37 PM PDT 24
Peak memory 182984 kb
Host smart-9d0c8ea4-5f0f-432a-ab94-d8002d8058e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493587056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.493587056
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1420568466
Short name T364
Test name
Test status
Simulation time 203629194980 ps
CPU time 252.31 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:34:31 PM PDT 24
Peak memory 183000 kb
Host smart-f162c235-1cc7-4714-94cb-271d0c38732e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420568466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1420568466
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3610203171
Short name T302
Test name
Test status
Simulation time 389563099171 ps
CPU time 183.16 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:33:17 PM PDT 24
Peak memory 191188 kb
Host smart-20673ac3-ff35-4066-9b4e-c938ae8b23a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610203171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3610203171
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1799981949
Short name T355
Test name
Test status
Simulation time 320732028 ps
CPU time 1.1 seconds
Started Jun 23 05:30:17 PM PDT 24
Finished Jun 23 05:30:19 PM PDT 24
Peak memory 192240 kb
Host smart-b32a2729-85fb-49db-a0d6-f5356456b370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799981949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1799981949
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2016576867
Short name T169
Test name
Test status
Simulation time 1683861659757 ps
CPU time 801.15 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:43:37 PM PDT 24
Peak memory 182968 kb
Host smart-77a06828-c4ca-40ef-a531-05da2d0042a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016576867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2016576867
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.4250479316
Short name T407
Test name
Test status
Simulation time 100188925075 ps
CPU time 157.05 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:32:55 PM PDT 24
Peak memory 183000 kb
Host smart-9fb6aec5-5360-4afe-a148-1379610f8f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250479316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4250479316
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1939354949
Short name T293
Test name
Test status
Simulation time 34535066656 ps
CPU time 65.6 seconds
Started Jun 23 05:30:14 PM PDT 24
Finished Jun 23 05:31:21 PM PDT 24
Peak memory 191208 kb
Host smart-02871c4f-511a-4e38-8601-4db4413e918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939354949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1939354949
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.497667178
Short name T220
Test name
Test status
Simulation time 1086893942548 ps
CPU time 790.11 seconds
Started Jun 23 05:30:14 PM PDT 24
Finished Jun 23 05:43:25 PM PDT 24
Peak memory 191204 kb
Host smart-33acc6c4-1dec-47a4-8430-1cbb794b6004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497667178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
497667178
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3585170726
Short name T33
Test name
Test status
Simulation time 188081013916 ps
CPU time 436.34 seconds
Started Jun 23 05:30:13 PM PDT 24
Finished Jun 23 05:37:30 PM PDT 24
Peak memory 205844 kb
Host smart-9dd91599-d240-4206-870a-e5ffecd49876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585170726 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3585170726
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3060617176
Short name T50
Test name
Test status
Simulation time 202847404750 ps
CPU time 214.19 seconds
Started Jun 23 05:30:16 PM PDT 24
Finished Jun 23 05:33:51 PM PDT 24
Peak memory 183036 kb
Host smart-754b6333-f2d4-4c61-aeeb-8f7a3ac6fdfc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060617176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3060617176
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1351070184
Short name T452
Test name
Test status
Simulation time 110258884610 ps
CPU time 156.02 seconds
Started Jun 23 05:30:16 PM PDT 24
Finished Jun 23 05:32:53 PM PDT 24
Peak memory 182900 kb
Host smart-4e553eb1-738e-467e-80a6-1869fb970f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351070184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1351070184
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2896794520
Short name T133
Test name
Test status
Simulation time 204135553240 ps
CPU time 1778.37 seconds
Started Jun 23 05:30:15 PM PDT 24
Finished Jun 23 05:59:54 PM PDT 24
Peak memory 191188 kb
Host smart-943ce01a-cb63-43b1-b414-ee37665dfcbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896794520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2896794520
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2159753803
Short name T450
Test name
Test status
Simulation time 348938132749 ps
CPU time 791.03 seconds
Started Jun 23 05:30:17 PM PDT 24
Finished Jun 23 05:43:29 PM PDT 24
Peak memory 194296 kb
Host smart-1a317340-0f23-4d4c-a392-83d8516b65d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159753803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2159753803
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3342189018
Short name T185
Test name
Test status
Simulation time 2588034768190 ps
CPU time 1044.29 seconds
Started Jun 23 05:30:24 PM PDT 24
Finished Jun 23 05:47:48 PM PDT 24
Peak memory 191068 kb
Host smart-53161279-9d27-4cbb-8c5e-50ff49c70951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342189018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3342189018
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1421403093
Short name T252
Test name
Test status
Simulation time 196937974745 ps
CPU time 319.69 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:35:24 PM PDT 24
Peak memory 182992 kb
Host smart-0d2b36c1-d2e7-4d2f-8998-3ec47c17e539
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421403093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1421403093
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3552716828
Short name T444
Test name
Test status
Simulation time 430638179384 ps
CPU time 175.22 seconds
Started Jun 23 05:29:51 PM PDT 24
Finished Jun 23 05:32:46 PM PDT 24
Peak memory 182920 kb
Host smart-320bcc3e-b0b1-4007-a497-c67b2095a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552716828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3552716828
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.124103666
Short name T323
Test name
Test status
Simulation time 135281192803 ps
CPU time 42.39 seconds
Started Jun 23 05:29:59 PM PDT 24
Finished Jun 23 05:30:42 PM PDT 24
Peak memory 182980 kb
Host smart-6b212869-acc6-4f7e-a61b-22372766e87b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124103666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.124103666
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.4212076388
Short name T414
Test name
Test status
Simulation time 103163860728 ps
CPU time 46.77 seconds
Started Jun 23 05:30:07 PM PDT 24
Finished Jun 23 05:30:55 PM PDT 24
Peak memory 183020 kb
Host smart-f4e613cc-f69a-406d-8c2d-915fe0428c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212076388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4212076388
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1578658251
Short name T15
Test name
Test status
Simulation time 189543357 ps
CPU time 0.96 seconds
Started Jun 23 05:29:51 PM PDT 24
Finished Jun 23 05:29:52 PM PDT 24
Peak memory 214240 kb
Host smart-36c5392c-ec33-4512-9bf7-f013a997461f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578658251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1578658251
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.53632560
Short name T377
Test name
Test status
Simulation time 66488879 ps
CPU time 0.56 seconds
Started Jun 23 05:30:01 PM PDT 24
Finished Jun 23 05:30:02 PM PDT 24
Peak memory 182732 kb
Host smart-97060290-4622-44fa-8de6-e77182f66796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53632560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.53632560
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4053156819
Short name T199
Test name
Test status
Simulation time 24017263745 ps
CPU time 37.93 seconds
Started Jun 23 05:30:19 PM PDT 24
Finished Jun 23 05:30:58 PM PDT 24
Peak memory 182988 kb
Host smart-dab07917-d8eb-4e04-a99e-a92b5689224c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053156819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4053156819
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.340460786
Short name T52
Test name
Test status
Simulation time 94752047014 ps
CPU time 36.78 seconds
Started Jun 23 05:30:19 PM PDT 24
Finished Jun 23 05:30:56 PM PDT 24
Peak memory 183008 kb
Host smart-38d17614-ae90-4019-ac0f-5ee968369f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340460786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.340460786
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3878402787
Short name T287
Test name
Test status
Simulation time 149344147970 ps
CPU time 943.72 seconds
Started Jun 23 05:30:19 PM PDT 24
Finished Jun 23 05:46:03 PM PDT 24
Peak memory 191188 kb
Host smart-a205b207-ee76-48aa-8a97-6f491f1439e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878402787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3878402787
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.803210864
Short name T448
Test name
Test status
Simulation time 123045357396 ps
CPU time 184.55 seconds
Started Jun 23 05:30:17 PM PDT 24
Finished Jun 23 05:33:22 PM PDT 24
Peak memory 182992 kb
Host smart-79436afa-a635-4c0a-9113-4d3d252ea8ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803210864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
803210864
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2108089211
Short name T419
Test name
Test status
Simulation time 3577698706 ps
CPU time 2.47 seconds
Started Jun 23 05:30:19 PM PDT 24
Finished Jun 23 05:30:22 PM PDT 24
Peak memory 182968 kb
Host smart-74644c21-6db5-47e9-927a-babb0a0b03b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108089211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2108089211
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1917261357
Short name T390
Test name
Test status
Simulation time 125473612456 ps
CPU time 192.11 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:33:31 PM PDT 24
Peak memory 182888 kb
Host smart-bc885233-342c-4bcb-aa6d-1e4f78f64252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917261357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1917261357
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2870322690
Short name T268
Test name
Test status
Simulation time 107247468927 ps
CPU time 190.54 seconds
Started Jun 23 05:30:24 PM PDT 24
Finished Jun 23 05:33:34 PM PDT 24
Peak memory 191044 kb
Host smart-9bd3a2aa-4786-4ccf-8397-8c79e5fd681c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870322690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2870322690
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3979479521
Short name T380
Test name
Test status
Simulation time 382021399 ps
CPU time 0.91 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:30:20 PM PDT 24
Peak memory 182956 kb
Host smart-067fd27c-7b5e-4730-bcbc-aa95789b74da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979479521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3979479521
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.4217281122
Short name T146
Test name
Test status
Simulation time 2523713974886 ps
CPU time 700.55 seconds
Started Jun 23 05:30:23 PM PDT 24
Finished Jun 23 05:42:04 PM PDT 24
Peak memory 182964 kb
Host smart-bb905a3b-7807-428b-8258-2d6811907aa1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217281122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.4217281122
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3013672946
Short name T359
Test name
Test status
Simulation time 13862220305 ps
CPU time 19.1 seconds
Started Jun 23 05:30:17 PM PDT 24
Finished Jun 23 05:30:36 PM PDT 24
Peak memory 182988 kb
Host smart-8561617e-2202-4f87-a18c-97d2f2a1a8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013672946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3013672946
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.4187952835
Short name T324
Test name
Test status
Simulation time 33052132397 ps
CPU time 14.33 seconds
Started Jun 23 05:30:23 PM PDT 24
Finished Jun 23 05:30:37 PM PDT 24
Peak memory 182972 kb
Host smart-ef6b3a7b-90bd-432c-90a0-8d891991d83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187952835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4187952835
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.880899081
Short name T122
Test name
Test status
Simulation time 61891406268 ps
CPU time 78.68 seconds
Started Jun 23 05:30:20 PM PDT 24
Finished Jun 23 05:31:39 PM PDT 24
Peak memory 182988 kb
Host smart-4ab5fb4c-d7fd-4865-973f-72cbae6d9428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880899081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.880899081
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1323787544
Short name T130
Test name
Test status
Simulation time 58341472007 ps
CPU time 67.69 seconds
Started Jun 23 05:30:18 PM PDT 24
Finished Jun 23 05:31:26 PM PDT 24
Peak memory 182876 kb
Host smart-dc940810-a7c1-4ea3-beb7-ca1d0115192c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323787544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1323787544
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1925165111
Short name T360
Test name
Test status
Simulation time 77846900403 ps
CPU time 60.2 seconds
Started Jun 23 05:30:24 PM PDT 24
Finished Jun 23 05:31:24 PM PDT 24
Peak memory 182844 kb
Host smart-eb7c648a-106a-418c-a658-5cd96c5b2648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925165111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1925165111
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3206670142
Short name T357
Test name
Test status
Simulation time 49771771 ps
CPU time 0.55 seconds
Started Jun 23 05:30:22 PM PDT 24
Finished Jun 23 05:30:22 PM PDT 24
Peak memory 182724 kb
Host smart-6e076063-45c3-4921-8eeb-d7c1e84d24d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206670142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3206670142
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.975553545
Short name T311
Test name
Test status
Simulation time 553779925280 ps
CPU time 95.76 seconds
Started Jun 23 05:30:22 PM PDT 24
Finished Jun 23 05:31:58 PM PDT 24
Peak memory 182984 kb
Host smart-b6d4ed57-ea35-4fb0-a01a-785677217139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975553545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
975553545
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1687643448
Short name T173
Test name
Test status
Simulation time 623873446414 ps
CPU time 585.02 seconds
Started Jun 23 05:30:23 PM PDT 24
Finished Jun 23 05:40:09 PM PDT 24
Peak memory 182972 kb
Host smart-74af2cba-21a7-4428-8666-d4af224f2453
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687643448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1687643448
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.101979906
Short name T362
Test name
Test status
Simulation time 142708408793 ps
CPU time 182.45 seconds
Started Jun 23 05:30:20 PM PDT 24
Finished Jun 23 05:33:23 PM PDT 24
Peak memory 182968 kb
Host smart-c0975bd1-4f0c-44a8-86e5-949a38052bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101979906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.101979906
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3921856398
Short name T187
Test name
Test status
Simulation time 96463155137 ps
CPU time 99 seconds
Started Jun 23 05:30:21 PM PDT 24
Finished Jun 23 05:32:01 PM PDT 24
Peak memory 191172 kb
Host smart-0a585155-44e4-476c-8601-d0cc149a4daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921856398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3921856398
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3567329041
Short name T405
Test name
Test status
Simulation time 13122677435 ps
CPU time 8.59 seconds
Started Jun 23 05:30:28 PM PDT 24
Finished Jun 23 05:30:37 PM PDT 24
Peak memory 191208 kb
Host smart-c76d8046-f469-4048-b3ab-b447759d4a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567329041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3567329041
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1052384146
Short name T271
Test name
Test status
Simulation time 1336256602835 ps
CPU time 553.66 seconds
Started Jun 23 05:30:27 PM PDT 24
Finished Jun 23 05:39:41 PM PDT 24
Peak memory 182984 kb
Host smart-6567bf8e-4a33-435a-9869-f819fe61e3d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052384146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1052384146
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3843589427
Short name T372
Test name
Test status
Simulation time 848549360545 ps
CPU time 104.39 seconds
Started Jun 23 05:30:27 PM PDT 24
Finished Jun 23 05:32:12 PM PDT 24
Peak memory 183012 kb
Host smart-38bea337-5020-4d03-973e-71352cdb8db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843589427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3843589427
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1747405872
Short name T439
Test name
Test status
Simulation time 213343275024 ps
CPU time 595.71 seconds
Started Jun 23 05:30:28 PM PDT 24
Finished Jun 23 05:40:24 PM PDT 24
Peak memory 191196 kb
Host smart-aabd0310-e828-4b4a-8279-4a0bc80e5899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747405872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1747405872
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2669874126
Short name T315
Test name
Test status
Simulation time 193465814112 ps
CPU time 69.24 seconds
Started Jun 23 05:30:29 PM PDT 24
Finished Jun 23 05:31:38 PM PDT 24
Peak memory 194496 kb
Host smart-65071528-2560-408f-92cb-c4861c717a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669874126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2669874126
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.563801291
Short name T284
Test name
Test status
Simulation time 343226594930 ps
CPU time 548.01 seconds
Started Jun 23 05:30:29 PM PDT 24
Finished Jun 23 05:39:38 PM PDT 24
Peak memory 194544 kb
Host smart-3a38bd84-921d-43df-a6d0-cdb9e0da7651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563801291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
563801291
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3499032816
Short name T338
Test name
Test status
Simulation time 15699687819 ps
CPU time 13.99 seconds
Started Jun 23 05:30:32 PM PDT 24
Finished Jun 23 05:30:47 PM PDT 24
Peak memory 182992 kb
Host smart-c3f9931c-5d0d-4b11-9044-d424e18a8f5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499032816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3499032816
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.866842618
Short name T386
Test name
Test status
Simulation time 68467690782 ps
CPU time 109.35 seconds
Started Jun 23 05:30:51 PM PDT 24
Finished Jun 23 05:32:41 PM PDT 24
Peak memory 182992 kb
Host smart-a578ce22-4440-43d2-aaa2-e45fd2518d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866842618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.866842618
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1711249417
Short name T424
Test name
Test status
Simulation time 88263262240 ps
CPU time 120.57 seconds
Started Jun 23 05:30:28 PM PDT 24
Finished Jun 23 05:32:29 PM PDT 24
Peak memory 191208 kb
Host smart-5162c75e-ab96-4b8c-9628-81785c56c785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711249417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1711249417
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2064656208
Short name T365
Test name
Test status
Simulation time 4976370986 ps
CPU time 8.1 seconds
Started Jun 23 05:30:32 PM PDT 24
Finished Jun 23 05:30:40 PM PDT 24
Peak memory 182972 kb
Host smart-03c0910d-205a-409b-b576-6c5ae689d3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064656208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2064656208
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1025638858
Short name T295
Test name
Test status
Simulation time 801481865942 ps
CPU time 1168.25 seconds
Started Jun 23 05:30:31 PM PDT 24
Finished Jun 23 05:49:59 PM PDT 24
Peak memory 191180 kb
Host smart-6218b6e1-8b52-4b9b-ba52-5715cc511168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025638858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1025638858
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1076228745
Short name T230
Test name
Test status
Simulation time 418737683750 ps
CPU time 632.69 seconds
Started Jun 23 05:30:37 PM PDT 24
Finished Jun 23 05:41:10 PM PDT 24
Peak memory 182976 kb
Host smart-40f0b80c-ad1e-4843-b9b8-a042bc7202a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076228745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1076228745
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3249415398
Short name T375
Test name
Test status
Simulation time 242571634811 ps
CPU time 100.22 seconds
Started Jun 23 05:30:32 PM PDT 24
Finished Jun 23 05:32:13 PM PDT 24
Peak memory 182976 kb
Host smart-2c2bee01-55ac-4df4-b336-24144f1eb022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249415398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3249415398
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3756394109
Short name T289
Test name
Test status
Simulation time 87636302168 ps
CPU time 321.48 seconds
Started Jun 23 05:30:33 PM PDT 24
Finished Jun 23 05:35:55 PM PDT 24
Peak memory 193360 kb
Host smart-7cb3ce25-987a-4b58-8fb6-4b3258e1f3f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756394109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3756394109
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1154915516
Short name T207
Test name
Test status
Simulation time 57103570861 ps
CPU time 306.65 seconds
Started Jun 23 05:30:40 PM PDT 24
Finished Jun 23 05:35:48 PM PDT 24
Peak memory 191208 kb
Host smart-8a937bc5-6a5d-42b3-966e-d1fa07b85f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154915516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1154915516
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1418876560
Short name T233
Test name
Test status
Simulation time 283986889838 ps
CPU time 361.99 seconds
Started Jun 23 05:30:39 PM PDT 24
Finished Jun 23 05:36:41 PM PDT 24
Peak memory 191172 kb
Host smart-78bb2fbb-9882-4ee8-961e-e0bd381b98a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418876560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1418876560
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1598463991
Short name T213
Test name
Test status
Simulation time 72698344684 ps
CPU time 117.73 seconds
Started Jun 23 05:30:37 PM PDT 24
Finished Jun 23 05:32:35 PM PDT 24
Peak memory 182984 kb
Host smart-af056862-8c70-4002-92fc-8f3130ff9a7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598463991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1598463991
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2204198579
Short name T406
Test name
Test status
Simulation time 289800129362 ps
CPU time 102.17 seconds
Started Jun 23 05:30:39 PM PDT 24
Finished Jun 23 05:32:22 PM PDT 24
Peak memory 182752 kb
Host smart-0ab8fa07-5e6f-4036-a483-dbac164d189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204198579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2204198579
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1438090104
Short name T101
Test name
Test status
Simulation time 281773245103 ps
CPU time 162.8 seconds
Started Jun 23 05:30:41 PM PDT 24
Finished Jun 23 05:33:24 PM PDT 24
Peak memory 191208 kb
Host smart-e545110e-a56e-4628-b34f-53db66d4f9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438090104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1438090104
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1461220497
Short name T277
Test name
Test status
Simulation time 1330732718892 ps
CPU time 729.39 seconds
Started Jun 23 05:30:42 PM PDT 24
Finished Jun 23 05:42:52 PM PDT 24
Peak memory 182992 kb
Host smart-303f9276-c57c-4932-8c18-2be66d687c05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461220497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1461220497
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2558272318
Short name T378
Test name
Test status
Simulation time 228022146367 ps
CPU time 94.68 seconds
Started Jun 23 05:30:41 PM PDT 24
Finished Jun 23 05:32:16 PM PDT 24
Peak memory 183000 kb
Host smart-0a57e406-b810-4ec1-bda8-c728594cc1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558272318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2558272318
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2107220218
Short name T242
Test name
Test status
Simulation time 142899820445 ps
CPU time 225.95 seconds
Started Jun 23 05:30:41 PM PDT 24
Finished Jun 23 05:34:28 PM PDT 24
Peak memory 193492 kb
Host smart-692d13bb-340d-4ea2-8320-c4fd0ae7f847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107220218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2107220218
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2570441881
Short name T413
Test name
Test status
Simulation time 8969028135 ps
CPU time 9.13 seconds
Started Jun 23 05:30:43 PM PDT 24
Finished Jun 23 05:30:52 PM PDT 24
Peak memory 183028 kb
Host smart-1e2183ab-e330-4247-9b14-2f22ba7004d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570441881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2570441881
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1311959419
Short name T369
Test name
Test status
Simulation time 60503769 ps
CPU time 0.62 seconds
Started Jun 23 05:30:45 PM PDT 24
Finished Jun 23 05:30:46 PM PDT 24
Peak memory 182740 kb
Host smart-975c4cb8-dac3-4e3f-912e-6de486975874
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311959419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1311959419
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3443018894
Short name T148
Test name
Test status
Simulation time 386480327798 ps
CPU time 668.37 seconds
Started Jun 23 05:29:53 PM PDT 24
Finished Jun 23 05:41:01 PM PDT 24
Peak memory 182996 kb
Host smart-130f78bb-49c9-4be3-aecd-b516161a2d4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443018894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3443018894
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.523480073
Short name T376
Test name
Test status
Simulation time 45518590651 ps
CPU time 67.58 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:31:10 PM PDT 24
Peak memory 182908 kb
Host smart-27731dde-b76b-4ea3-ac2a-bb32bcba3d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523480073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.523480073
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1446197583
Short name T420
Test name
Test status
Simulation time 51230787757 ps
CPU time 122.24 seconds
Started Jun 23 05:29:49 PM PDT 24
Finished Jun 23 05:31:51 PM PDT 24
Peak memory 191208 kb
Host smart-ca8aec83-352a-412a-8e5b-9a8cea192f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446197583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1446197583
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2331564823
Short name T216
Test name
Test status
Simulation time 319315410558 ps
CPU time 608.36 seconds
Started Jun 23 05:29:54 PM PDT 24
Finished Jun 23 05:40:03 PM PDT 24
Peak memory 191196 kb
Host smart-53738614-0a61-4432-bdaf-d0c3f90d118f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331564823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2331564823
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.144554062
Short name T328
Test name
Test status
Simulation time 78818285503 ps
CPU time 27.41 seconds
Started Jun 23 05:30:44 PM PDT 24
Finished Jun 23 05:31:12 PM PDT 24
Peak memory 182984 kb
Host smart-d1d8d65b-2434-4138-b77b-163c7787c643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144554062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.144554062
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3359587740
Short name T317
Test name
Test status
Simulation time 247997793231 ps
CPU time 572.78 seconds
Started Jun 23 05:30:47 PM PDT 24
Finished Jun 23 05:40:20 PM PDT 24
Peak memory 191188 kb
Host smart-354874d7-b9e5-4fc0-9ba0-89aeb54a5016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359587740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3359587740
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.906519587
Short name T243
Test name
Test status
Simulation time 191428605686 ps
CPU time 80.69 seconds
Started Jun 23 05:30:44 PM PDT 24
Finished Jun 23 05:32:05 PM PDT 24
Peak memory 182984 kb
Host smart-2956649a-5d5c-4550-9c31-20289b7f9cec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906519587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.906519587
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2156092125
Short name T263
Test name
Test status
Simulation time 374131226745 ps
CPU time 605.4 seconds
Started Jun 23 05:30:48 PM PDT 24
Finished Jun 23 05:40:54 PM PDT 24
Peak memory 191180 kb
Host smart-9d71df4a-b8f3-42a6-b76c-4769e48927b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156092125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2156092125
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1391436381
Short name T269
Test name
Test status
Simulation time 148291425243 ps
CPU time 812.1 seconds
Started Jun 23 05:30:46 PM PDT 24
Finished Jun 23 05:44:19 PM PDT 24
Peak memory 193616 kb
Host smart-1460c200-4709-4da5-bd4a-0895763f94f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391436381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1391436381
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2960462928
Short name T429
Test name
Test status
Simulation time 205098344021 ps
CPU time 78.8 seconds
Started Jun 23 05:30:46 PM PDT 24
Finished Jun 23 05:32:05 PM PDT 24
Peak memory 182996 kb
Host smart-d1da5adc-56d6-4a5c-8d69-fd9a1109c06b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960462928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2960462928
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4102917336
Short name T105
Test name
Test status
Simulation time 170285049444 ps
CPU time 659.76 seconds
Started Jun 23 05:30:47 PM PDT 24
Finished Jun 23 05:41:48 PM PDT 24
Peak memory 191100 kb
Host smart-1d27f7e3-cb7a-4d5e-8cbf-85fbbea84b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102917336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4102917336
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3504799270
Short name T279
Test name
Test status
Simulation time 9345255974 ps
CPU time 9.08 seconds
Started Jun 23 05:30:00 PM PDT 24
Finished Jun 23 05:30:09 PM PDT 24
Peak memory 182996 kb
Host smart-52b08745-15f5-4e05-b6b7-74ae49b355c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504799270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3504799270
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.774728402
Short name T436
Test name
Test status
Simulation time 53928951401 ps
CPU time 41.03 seconds
Started Jun 23 05:29:59 PM PDT 24
Finished Jun 23 05:30:40 PM PDT 24
Peak memory 183004 kb
Host smart-e8cdbc1e-d140-421a-a92d-783b79c51f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774728402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.774728402
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3240863443
Short name T194
Test name
Test status
Simulation time 122192113980 ps
CPU time 950.51 seconds
Started Jun 23 05:29:53 PM PDT 24
Finished Jun 23 05:45:44 PM PDT 24
Peak memory 191172 kb
Host smart-206f1017-1e51-41ac-afa4-cadb56d3f380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240863443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3240863443
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1882350230
Short name T256
Test name
Test status
Simulation time 15592831811 ps
CPU time 28.34 seconds
Started Jun 23 05:29:58 PM PDT 24
Finished Jun 23 05:30:27 PM PDT 24
Peak memory 183040 kb
Host smart-aceffe55-6680-4131-b20f-99816eadda9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882350230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1882350230
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1345732630
Short name T64
Test name
Test status
Simulation time 2721321476919 ps
CPU time 1402.59 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:53:29 PM PDT 24
Peak memory 190792 kb
Host smart-f9916396-decf-4770-acfa-70462b08ea05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345732630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1345732630
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2377322073
Short name T412
Test name
Test status
Simulation time 22054150771 ps
CPU time 37.04 seconds
Started Jun 23 05:30:51 PM PDT 24
Finished Jun 23 05:31:28 PM PDT 24
Peak memory 191188 kb
Host smart-23258882-1c76-4d2d-aff0-4a3e7785562d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377322073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2377322073
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1622353013
Short name T124
Test name
Test status
Simulation time 131560429166 ps
CPU time 312.89 seconds
Started Jun 23 05:30:51 PM PDT 24
Finished Jun 23 05:36:05 PM PDT 24
Peak memory 191196 kb
Host smart-3a1e1a3a-f963-443c-972e-3c42b25cdc7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622353013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1622353013
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1661017095
Short name T297
Test name
Test status
Simulation time 177676058061 ps
CPU time 118.22 seconds
Started Jun 23 05:30:51 PM PDT 24
Finished Jun 23 05:32:50 PM PDT 24
Peak memory 191196 kb
Host smart-a4ca4962-a46a-4f7b-8f1c-aea020789bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661017095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1661017095
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2340296663
Short name T304
Test name
Test status
Simulation time 78534189866 ps
CPU time 163.16 seconds
Started Jun 23 05:30:52 PM PDT 24
Finished Jun 23 05:33:35 PM PDT 24
Peak memory 191156 kb
Host smart-6f40225b-1c2e-425a-a40d-742cdefeb932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340296663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2340296663
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2593124412
Short name T197
Test name
Test status
Simulation time 187953665078 ps
CPU time 97.24 seconds
Started Jun 23 05:30:54 PM PDT 24
Finished Jun 23 05:32:31 PM PDT 24
Peak memory 191176 kb
Host smart-b35e22b4-721f-4549-ad44-ce841b381b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593124412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2593124412
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1233605832
Short name T316
Test name
Test status
Simulation time 81157669912 ps
CPU time 67.37 seconds
Started Jun 23 05:30:51 PM PDT 24
Finished Jun 23 05:31:59 PM PDT 24
Peak memory 191080 kb
Host smart-0f14efdd-fadd-42f6-a53c-70a68fa7d8c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233605832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1233605832
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.911787022
Short name T109
Test name
Test status
Simulation time 285848087841 ps
CPU time 1377.8 seconds
Started Jun 23 05:30:51 PM PDT 24
Finished Jun 23 05:53:50 PM PDT 24
Peak memory 191176 kb
Host smart-83bb5351-0c07-40b5-a46d-5c1f17d5dbba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911787022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.911787022
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1863731002
Short name T108
Test name
Test status
Simulation time 121409192607 ps
CPU time 305.83 seconds
Started Jun 23 05:30:51 PM PDT 24
Finished Jun 23 05:35:57 PM PDT 24
Peak memory 191164 kb
Host smart-87cd4803-f1d2-41da-ac62-cea69611a082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863731002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1863731002
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2746324615
Short name T87
Test name
Test status
Simulation time 379632626971 ps
CPU time 2177.12 seconds
Started Jun 23 05:30:53 PM PDT 24
Finished Jun 23 06:07:11 PM PDT 24
Peak memory 191180 kb
Host smart-be2b001c-c1c7-49bc-8c8c-1f5065216630
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746324615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2746324615
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3336332385
Short name T19
Test name
Test status
Simulation time 71561649960 ps
CPU time 78.64 seconds
Started Jun 23 05:30:51 PM PDT 24
Finished Jun 23 05:32:10 PM PDT 24
Peak memory 191172 kb
Host smart-cd54dea1-28fb-42e2-91a0-c4ac4e085d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336332385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3336332385
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.103622773
Short name T283
Test name
Test status
Simulation time 63686236180 ps
CPU time 108.08 seconds
Started Jun 23 05:29:56 PM PDT 24
Finished Jun 23 05:31:44 PM PDT 24
Peak memory 182948 kb
Host smart-eaaea29f-9f6c-42e4-918c-dbfaf4d4e395
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103622773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.103622773
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2528214723
Short name T422
Test name
Test status
Simulation time 808632031105 ps
CPU time 346.08 seconds
Started Jun 23 05:30:03 PM PDT 24
Finished Jun 23 05:35:50 PM PDT 24
Peak memory 183000 kb
Host smart-688e48a7-1ee7-4f8b-b450-39808ed41b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528214723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2528214723
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2551377304
Short name T178
Test name
Test status
Simulation time 173530167768 ps
CPU time 279.56 seconds
Started Jun 23 05:30:06 PM PDT 24
Finished Jun 23 05:34:46 PM PDT 24
Peak memory 191196 kb
Host smart-d01f4cd0-f7ec-4b0d-9f06-5a66235e81d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551377304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2551377304
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2700576746
Short name T261
Test name
Test status
Simulation time 578361325216 ps
CPU time 129.22 seconds
Started Jun 23 05:30:02 PM PDT 24
Finished Jun 23 05:32:12 PM PDT 24
Peak memory 194536 kb
Host smart-0dda998a-1a75-47c9-abfd-0f2c44800733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700576746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2700576746
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2650745025
Short name T65
Test name
Test status
Simulation time 784540262350 ps
CPU time 565.94 seconds
Started Jun 23 05:30:04 PM PDT 24
Finished Jun 23 05:39:32 PM PDT 24
Peak memory 194664 kb
Host smart-a4b084c1-6636-4436-ae62-db529432141c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650745025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2650745025
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.3903789936
Short name T97
Test name
Test status
Simulation time 276918911455 ps
CPU time 309.37 seconds
Started Jun 23 05:30:53 PM PDT 24
Finished Jun 23 05:36:03 PM PDT 24
Peak memory 191208 kb
Host smart-1cbb7481-8117-4438-9b10-361777af99bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903789936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3903789936
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2847100762
Short name T298
Test name
Test status
Simulation time 780391016322 ps
CPU time 822.91 seconds
Started Jun 23 05:30:57 PM PDT 24
Finished Jun 23 05:44:40 PM PDT 24
Peak memory 191196 kb
Host smart-6e2fbc2a-eb54-4285-9cbe-4a858656e50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847100762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2847100762
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1676652348
Short name T123
Test name
Test status
Simulation time 955115359893 ps
CPU time 1912.24 seconds
Started Jun 23 05:30:59 PM PDT 24
Finished Jun 23 06:02:52 PM PDT 24
Peak memory 191196 kb
Host smart-a137236c-8af0-48c3-8dd9-78126b06e639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676652348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1676652348
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2341604070
Short name T440
Test name
Test status
Simulation time 35477003561 ps
CPU time 56.03 seconds
Started Jun 23 05:30:57 PM PDT 24
Finished Jun 23 05:31:54 PM PDT 24
Peak memory 182972 kb
Host smart-1e23786b-fa37-4ac5-8e74-70e9499c876e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341604070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2341604070
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2308654955
Short name T334
Test name
Test status
Simulation time 132013349125 ps
CPU time 217.83 seconds
Started Jun 23 05:30:56 PM PDT 24
Finished Jun 23 05:34:34 PM PDT 24
Peak memory 191180 kb
Host smart-a18260cc-7619-4060-88c5-c60113a9801a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308654955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2308654955
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2281943756
Short name T303
Test name
Test status
Simulation time 120808997570 ps
CPU time 176.84 seconds
Started Jun 23 05:30:58 PM PDT 24
Finished Jun 23 05:33:55 PM PDT 24
Peak memory 191196 kb
Host smart-d1a3ebba-395f-477e-a6d1-c678d1da5e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281943756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2281943756
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1939671313
Short name T312
Test name
Test status
Simulation time 46361875315 ps
CPU time 28.05 seconds
Started Jun 23 05:30:58 PM PDT 24
Finished Jun 23 05:31:26 PM PDT 24
Peak memory 183008 kb
Host smart-be6a9069-cf5f-441b-bb25-f8be2fd88936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939671313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1939671313
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.1193560550
Short name T285
Test name
Test status
Simulation time 87860655325 ps
CPU time 220.75 seconds
Started Jun 23 05:29:57 PM PDT 24
Finished Jun 23 05:33:38 PM PDT 24
Peak memory 191188 kb
Host smart-ed7ccc34-2497-47cd-ba88-a098fa6a2e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193560550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1193560550
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1304071612
Short name T23
Test name
Test status
Simulation time 147828312143 ps
CPU time 162 seconds
Started Jun 23 05:29:55 PM PDT 24
Finished Jun 23 05:32:38 PM PDT 24
Peak memory 194472 kb
Host smart-1b34e4ba-39ab-452f-9c57-b22cb76273f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304071612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1304071612
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/82.rv_timer_random.813685582
Short name T211
Test name
Test status
Simulation time 51150736595 ps
CPU time 80.97 seconds
Started Jun 23 05:31:00 PM PDT 24
Finished Jun 23 05:32:21 PM PDT 24
Peak memory 191192 kb
Host smart-2889f6c2-033c-4993-ac53-ecd8e0f576c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813685582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.813685582
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.40314486
Short name T150
Test name
Test status
Simulation time 385586260264 ps
CPU time 670.06 seconds
Started Jun 23 05:30:56 PM PDT 24
Finished Jun 23 05:42:07 PM PDT 24
Peak memory 191192 kb
Host smart-ac5af635-6d2c-4b9a-a135-d86ec655389c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40314486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.40314486
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2995383886
Short name T399
Test name
Test status
Simulation time 79212333834 ps
CPU time 59.72 seconds
Started Jun 23 05:31:02 PM PDT 24
Finished Jun 23 05:32:02 PM PDT 24
Peak memory 182804 kb
Host smart-12b9db24-63bd-4d01-8c8f-65df395c7339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995383886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2995383886
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3336491030
Short name T102
Test name
Test status
Simulation time 2877850843689 ps
CPU time 683.92 seconds
Started Jun 23 05:31:01 PM PDT 24
Finished Jun 23 05:42:25 PM PDT 24
Peak memory 191036 kb
Host smart-299e5982-77ba-47d0-b549-ad0061024963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336491030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3336491030
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1442941898
Short name T217
Test name
Test status
Simulation time 542956485364 ps
CPU time 1109.58 seconds
Started Jun 23 05:31:06 PM PDT 24
Finished Jun 23 05:49:36 PM PDT 24
Peak memory 191200 kb
Host smart-4c9a6910-7291-4a51-9fea-fa707bd23a35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442941898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1442941898
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.356214662
Short name T373
Test name
Test status
Simulation time 6914732887 ps
CPU time 3.25 seconds
Started Jun 23 05:30:00 PM PDT 24
Finished Jun 23 05:30:04 PM PDT 24
Peak memory 182800 kb
Host smart-1a4d0c17-822f-4015-b3c2-1335f88159c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356214662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.356214662
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.924537912
Short name T280
Test name
Test status
Simulation time 278482289252 ps
CPU time 226.83 seconds
Started Jun 23 05:30:00 PM PDT 24
Finished Jun 23 05:33:47 PM PDT 24
Peak memory 191192 kb
Host smart-aaf76900-55fc-4924-9f86-5c0ea03a1bbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924537912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.924537912
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1496431409
Short name T286
Test name
Test status
Simulation time 34204666329 ps
CPU time 15.52 seconds
Started Jun 23 05:29:56 PM PDT 24
Finished Jun 23 05:30:12 PM PDT 24
Peak memory 191196 kb
Host smart-9d46c8ec-4545-4d59-87ac-6ff53642c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496431409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1496431409
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3422990182
Short name T282
Test name
Test status
Simulation time 132680846190 ps
CPU time 198.68 seconds
Started Jun 23 05:29:55 PM PDT 24
Finished Jun 23 05:33:14 PM PDT 24
Peak memory 182996 kb
Host smart-3d3dc5b5-6571-40e1-ae33-a0214576c191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422990182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3422990182
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.2692711954
Short name T110
Test name
Test status
Simulation time 360331405147 ps
CPU time 294.67 seconds
Started Jun 23 05:31:08 PM PDT 24
Finished Jun 23 05:36:03 PM PDT 24
Peak memory 191188 kb
Host smart-5c97dea3-d441-4f62-87e8-2027059967b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692711954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2692711954
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3261642143
Short name T99
Test name
Test status
Simulation time 412486703715 ps
CPU time 1906.09 seconds
Started Jun 23 05:31:06 PM PDT 24
Finished Jun 23 06:02:53 PM PDT 24
Peak memory 191176 kb
Host smart-bf544612-18f0-4284-95fa-f4d7345e31b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261642143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3261642143
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.711388050
Short name T333
Test name
Test status
Simulation time 356931526025 ps
CPU time 400.04 seconds
Started Jun 23 05:31:08 PM PDT 24
Finished Jun 23 05:37:49 PM PDT 24
Peak memory 193540 kb
Host smart-d45b6bd8-00c1-40b9-943f-f7f6bd1975d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711388050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.711388050
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3378405644
Short name T410
Test name
Test status
Simulation time 140531611114 ps
CPU time 50.12 seconds
Started Jun 23 05:31:06 PM PDT 24
Finished Jun 23 05:31:57 PM PDT 24
Peak memory 183044 kb
Host smart-94e2c75c-5a6b-44d8-a66e-798417fe8c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378405644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3378405644
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.673046778
Short name T129
Test name
Test status
Simulation time 75653905626 ps
CPU time 367.48 seconds
Started Jun 23 05:31:06 PM PDT 24
Finished Jun 23 05:37:14 PM PDT 24
Peak memory 182984 kb
Host smart-63e06a1c-ed2b-4178-b2df-b73252e52282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673046778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.673046778
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4186139477
Short name T330
Test name
Test status
Simulation time 566195512647 ps
CPU time 1131.76 seconds
Started Jun 23 05:31:12 PM PDT 24
Finished Jun 23 05:50:04 PM PDT 24
Peak memory 191188 kb
Host smart-4951fed5-7620-44a9-8f29-e3ac2dcba904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186139477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4186139477
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.648708314
Short name T337
Test name
Test status
Simulation time 1803071657 ps
CPU time 11.28 seconds
Started Jun 23 05:31:12 PM PDT 24
Finished Jun 23 05:31:23 PM PDT 24
Peak memory 182932 kb
Host smart-2b8fecdd-3578-4473-8e3d-9a4de60b476e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648708314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.648708314
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1560313326
Short name T332
Test name
Test status
Simulation time 137714916247 ps
CPU time 131.54 seconds
Started Jun 23 05:31:11 PM PDT 24
Finished Jun 23 05:33:24 PM PDT 24
Peak memory 191188 kb
Host smart-4047089e-a871-4122-8e60-8016402556e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560313326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1560313326
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3206128618
Short name T157
Test name
Test status
Simulation time 545123974010 ps
CPU time 332.87 seconds
Started Jun 23 05:31:11 PM PDT 24
Finished Jun 23 05:36:44 PM PDT 24
Peak memory 191196 kb
Host smart-afda61ca-7d7b-478b-806c-3a3582329b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206128618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3206128618
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2984673970
Short name T257
Test name
Test status
Simulation time 85316840660 ps
CPU time 70.36 seconds
Started Jun 23 05:31:11 PM PDT 24
Finished Jun 23 05:32:22 PM PDT 24
Peak memory 182988 kb
Host smart-7937af98-19d1-4256-97ea-4f66f873d8e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984673970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2984673970
Directory /workspace/99.rv_timer_random/latest
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