Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 579
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.146457885 Jun 24 05:39:37 PM PDT 24 Jun 24 05:39:39 PM PDT 24 18540256 ps
T507 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1679047224 Jun 24 05:39:37 PM PDT 24 Jun 24 05:39:38 PM PDT 24 53076701 ps
T508 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2563070856 Jun 24 05:39:33 PM PDT 24 Jun 24 05:39:34 PM PDT 24 57930547 ps
T509 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2562006131 Jun 24 05:39:36 PM PDT 24 Jun 24 05:39:37 PM PDT 24 14461484 ps
T510 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.91324933 Jun 24 05:39:34 PM PDT 24 Jun 24 05:39:36 PM PDT 24 35610333 ps
T511 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1174718635 Jun 24 05:39:37 PM PDT 24 Jun 24 05:39:39 PM PDT 24 183552191 ps
T512 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.376990111 Jun 24 05:39:16 PM PDT 24 Jun 24 05:39:18 PM PDT 24 115540751 ps
T513 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3334674776 Jun 24 05:39:33 PM PDT 24 Jun 24 05:39:35 PM PDT 24 45520808 ps
T514 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2444040767 Jun 24 05:39:22 PM PDT 24 Jun 24 05:39:24 PM PDT 24 32252176 ps
T515 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1633402744 Jun 24 05:39:22 PM PDT 24 Jun 24 05:39:23 PM PDT 24 42995853 ps
T516 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1818418975 Jun 24 05:39:14 PM PDT 24 Jun 24 05:39:17 PM PDT 24 56743682 ps
T517 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.539517853 Jun 24 05:39:11 PM PDT 24 Jun 24 05:39:14 PM PDT 24 72597509 ps
T518 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1963317242 Jun 24 05:39:38 PM PDT 24 Jun 24 05:39:40 PM PDT 24 34254102 ps
T519 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3176913968 Jun 24 05:39:23 PM PDT 24 Jun 24 05:39:25 PM PDT 24 17130561 ps
T520 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1331981950 Jun 24 05:39:26 PM PDT 24 Jun 24 05:39:29 PM PDT 24 20782951 ps
T521 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4129417058 Jun 24 05:39:34 PM PDT 24 Jun 24 05:39:36 PM PDT 24 216415277 ps
T522 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.736735669 Jun 24 05:39:30 PM PDT 24 Jun 24 05:39:32 PM PDT 24 53559958 ps
T523 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1287115125 Jun 24 05:39:24 PM PDT 24 Jun 24 05:39:27 PM PDT 24 74660125 ps
T524 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4073076478 Jun 24 05:39:40 PM PDT 24 Jun 24 05:39:42 PM PDT 24 42376556 ps
T525 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.811198143 Jun 24 05:39:26 PM PDT 24 Jun 24 05:39:29 PM PDT 24 71760094 ps
T526 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1309903169 Jun 24 05:39:12 PM PDT 24 Jun 24 05:39:16 PM PDT 24 300894122 ps
T527 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.443532527 Jun 24 05:39:34 PM PDT 24 Jun 24 05:39:36 PM PDT 24 35085701 ps
T83 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3819355268 Jun 24 05:39:22 PM PDT 24 Jun 24 05:39:24 PM PDT 24 17992838 ps
T84 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3460245857 Jun 24 05:39:26 PM PDT 24 Jun 24 05:39:29 PM PDT 24 251712323 ps
T528 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2776031938 Jun 24 05:39:13 PM PDT 24 Jun 24 05:39:15 PM PDT 24 58114916 ps
T529 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1809503144 Jun 24 05:39:27 PM PDT 24 Jun 24 05:39:31 PM PDT 24 23945096 ps
T530 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2244421231 Jun 24 05:39:24 PM PDT 24 Jun 24 05:39:27 PM PDT 24 109691623 ps
T531 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3511753594 Jun 24 05:39:21 PM PDT 24 Jun 24 05:39:23 PM PDT 24 206297970 ps
T532 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3420154126 Jun 24 05:39:36 PM PDT 24 Jun 24 05:39:37 PM PDT 24 17482961 ps
T86 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3291326388 Jun 24 05:39:12 PM PDT 24 Jun 24 05:39:16 PM PDT 24 121011974 ps
T533 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2377283904 Jun 24 05:39:27 PM PDT 24 Jun 24 05:39:30 PM PDT 24 29404749 ps
T85 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.29712501 Jun 24 05:39:21 PM PDT 24 Jun 24 05:39:23 PM PDT 24 30959028 ps
T534 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1469803182 Jun 24 05:39:25 PM PDT 24 Jun 24 05:39:28 PM PDT 24 31984296 ps
T535 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2171632674 Jun 24 05:39:12 PM PDT 24 Jun 24 05:39:15 PM PDT 24 56221937 ps
T536 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1668158880 Jun 24 05:39:28 PM PDT 24 Jun 24 05:39:31 PM PDT 24 24465282 ps
T537 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2196383257 Jun 24 05:39:15 PM PDT 24 Jun 24 05:39:18 PM PDT 24 13539985 ps
T538 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2178876509 Jun 24 05:39:27 PM PDT 24 Jun 24 05:39:30 PM PDT 24 28745106 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1764385756 Jun 24 05:39:38 PM PDT 24 Jun 24 05:39:40 PM PDT 24 18175546 ps
T540 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3576927218 Jun 24 05:39:35 PM PDT 24 Jun 24 05:39:37 PM PDT 24 76340919 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3318080200 Jun 24 05:39:24 PM PDT 24 Jun 24 05:39:26 PM PDT 24 14413408 ps
T542 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2666766632 Jun 24 05:39:13 PM PDT 24 Jun 24 05:39:16 PM PDT 24 91719203 ps
T543 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.944447508 Jun 24 05:39:43 PM PDT 24 Jun 24 05:39:44 PM PDT 24 17070773 ps
T544 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1816815467 Jun 24 05:39:41 PM PDT 24 Jun 24 05:39:43 PM PDT 24 24977825 ps
T545 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1677092600 Jun 24 05:39:14 PM PDT 24 Jun 24 05:39:16 PM PDT 24 39340241 ps
T546 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1170630699 Jun 24 05:39:42 PM PDT 24 Jun 24 05:39:44 PM PDT 24 89391553 ps
T547 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2632414537 Jun 24 05:39:40 PM PDT 24 Jun 24 05:39:42 PM PDT 24 26968429 ps
T548 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.650759645 Jun 24 05:39:23 PM PDT 24 Jun 24 05:39:26 PM PDT 24 36910297 ps
T549 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3724852155 Jun 24 05:39:26 PM PDT 24 Jun 24 05:39:29 PM PDT 24 126464190 ps
T550 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2887953722 Jun 24 05:39:37 PM PDT 24 Jun 24 05:39:39 PM PDT 24 16982328 ps
T87 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.360062589 Jun 24 05:39:13 PM PDT 24 Jun 24 05:39:16 PM PDT 24 111503875 ps
T551 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2469732144 Jun 24 05:39:15 PM PDT 24 Jun 24 05:39:18 PM PDT 24 93818002 ps
T552 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2168908237 Jun 24 05:39:40 PM PDT 24 Jun 24 05:39:42 PM PDT 24 17136034 ps
T553 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2554171746 Jun 24 05:39:33 PM PDT 24 Jun 24 05:39:35 PM PDT 24 18760009 ps
T554 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3925908473 Jun 24 05:39:41 PM PDT 24 Jun 24 05:39:43 PM PDT 24 51224715 ps
T555 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.690465916 Jun 24 05:39:14 PM PDT 24 Jun 24 05:39:18 PM PDT 24 64779825 ps
T556 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1382646871 Jun 24 05:39:24 PM PDT 24 Jun 24 05:39:26 PM PDT 24 21782466 ps
T557 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1236700773 Jun 24 05:39:26 PM PDT 24 Jun 24 05:39:28 PM PDT 24 23794700 ps
T558 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1359958091 Jun 24 05:39:14 PM PDT 24 Jun 24 05:39:17 PM PDT 24 50271328 ps
T559 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2199582156 Jun 24 05:39:32 PM PDT 24 Jun 24 05:39:34 PM PDT 24 31385832 ps
T560 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.716522084 Jun 24 05:39:11 PM PDT 24 Jun 24 05:39:13 PM PDT 24 40979912 ps
T561 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.135930094 Jun 24 05:39:26 PM PDT 24 Jun 24 05:39:29 PM PDT 24 48560769 ps
T562 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2915853810 Jun 24 05:39:41 PM PDT 24 Jun 24 05:39:43 PM PDT 24 96862635 ps
T563 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.710069998 Jun 24 05:39:28 PM PDT 24 Jun 24 05:39:32 PM PDT 24 38462079 ps
T564 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3156380272 Jun 24 05:39:44 PM PDT 24 Jun 24 05:39:45 PM PDT 24 62707400 ps
T565 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2026857183 Jun 24 05:39:25 PM PDT 24 Jun 24 05:39:27 PM PDT 24 32968772 ps
T566 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2943751669 Jun 24 05:39:27 PM PDT 24 Jun 24 05:39:30 PM PDT 24 56443036 ps
T567 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3941309269 Jun 24 05:39:25 PM PDT 24 Jun 24 05:39:27 PM PDT 24 236581952 ps
T568 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1918437094 Jun 24 05:39:37 PM PDT 24 Jun 24 05:39:40 PM PDT 24 620990825 ps
T569 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3413957525 Jun 24 05:39:25 PM PDT 24 Jun 24 05:39:27 PM PDT 24 22387955 ps
T570 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.727447324 Jun 24 05:39:39 PM PDT 24 Jun 24 05:39:40 PM PDT 24 29461196 ps
T571 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.434453922 Jun 24 05:39:26 PM PDT 24 Jun 24 05:39:29 PM PDT 24 95525889 ps
T572 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3887634465 Jun 24 05:39:32 PM PDT 24 Jun 24 05:39:34 PM PDT 24 34578030 ps
T573 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.76789287 Jun 24 05:39:33 PM PDT 24 Jun 24 05:39:36 PM PDT 24 64524614 ps
T574 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3712457299 Jun 24 05:39:37 PM PDT 24 Jun 24 05:39:39 PM PDT 24 46351595 ps
T575 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1332174308 Jun 24 05:39:39 PM PDT 24 Jun 24 05:39:41 PM PDT 24 17548729 ps
T576 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2081703880 Jun 24 05:39:12 PM PDT 24 Jun 24 05:39:15 PM PDT 24 14966718 ps
T577 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.280412522 Jun 24 05:39:13 PM PDT 24 Jun 24 05:39:16 PM PDT 24 17574906 ps
T578 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2608668668 Jun 24 05:39:31 PM PDT 24 Jun 24 05:39:33 PM PDT 24 28974379 ps
T579 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3496723981 Jun 24 05:39:30 PM PDT 24 Jun 24 05:39:34 PM PDT 24 180724762 ps

Test location /workspace/coverage/default/148.rv_timer_random.1095077820
Short name T7
Test name
Test status
Simulation time 88263623283 ps
CPU time 132.98 seconds
Started Jun 24 06:25:58 PM PDT 24
Finished Jun 24 06:28:11 PM PDT 24
Peak memory 191180 kb
Host smart-17ece41e-ab73-46d4-b7a6-8e4853a95ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095077820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1095077820
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.1889676334
Short name T15
Test name
Test status
Simulation time 227257192651 ps
CPU time 745.29 seconds
Started Jun 24 06:20:46 PM PDT 24
Finished Jun 24 06:33:12 PM PDT 24
Peak memory 207500 kb
Host smart-2b801ea9-6bf2-4b04-9864-e83999dbc687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889676334 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.1889676334
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.852869461
Short name T137
Test name
Test status
Simulation time 1087858247663 ps
CPU time 2320.77 seconds
Started Jun 24 06:22:22 PM PDT 24
Finished Jun 24 07:01:04 PM PDT 24
Peak memory 195472 kb
Host smart-8564e753-7026-4c70-9838-0a783dcc645a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852869461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
852869461
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3298766068
Short name T33
Test name
Test status
Simulation time 114029078 ps
CPU time 1.35 seconds
Started Jun 24 05:39:28 PM PDT 24
Finished Jun 24 05:39:32 PM PDT 24
Peak memory 195192 kb
Host smart-9b4dfe90-d142-4824-a9e4-54a4a4b2c05b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298766068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3298766068
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.151886140
Short name T140
Test name
Test status
Simulation time 547542114288 ps
CPU time 4046.66 seconds
Started Jun 24 06:22:57 PM PDT 24
Finished Jun 24 07:30:25 PM PDT 24
Peak memory 191172 kb
Host smart-1a6a96e4-c7c6-4be9-bd3d-0be27a4151d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151886140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
151886140
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2062888828
Short name T172
Test name
Test status
Simulation time 1457619696370 ps
CPU time 3280.46 seconds
Started Jun 24 06:23:51 PM PDT 24
Finished Jun 24 07:18:32 PM PDT 24
Peak memory 196088 kb
Host smart-62971c8b-2d65-4c57-a985-e578f47f0896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062888828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2062888828
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4133504816
Short name T11
Test name
Test status
Simulation time 531078440880 ps
CPU time 3994.61 seconds
Started Jun 24 06:22:06 PM PDT 24
Finished Jun 24 07:28:41 PM PDT 24
Peak memory 195596 kb
Host smart-771f527a-1923-4ca8-b51e-752a41278d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133504816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4133504816
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.553665118
Short name T111
Test name
Test status
Simulation time 572159458130 ps
CPU time 4328.72 seconds
Started Jun 24 06:20:21 PM PDT 24
Finished Jun 24 07:32:30 PM PDT 24
Peak memory 191184 kb
Host smart-91a7305b-08be-4c2f-91dc-13d6cff3fcfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553665118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.553665118
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1227905781
Short name T145
Test name
Test status
Simulation time 382424044442 ps
CPU time 558.89 seconds
Started Jun 24 06:21:11 PM PDT 24
Finished Jun 24 06:30:31 PM PDT 24
Peak memory 194940 kb
Host smart-b840c9ac-560d-4071-935e-a90048a2498d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227905781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1227905781
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3276681354
Short name T182
Test name
Test status
Simulation time 757681747507 ps
CPU time 1250.84 seconds
Started Jun 24 06:21:03 PM PDT 24
Finished Jun 24 06:41:54 PM PDT 24
Peak memory 191184 kb
Host smart-fa4ec83a-8c3f-480e-b773-1dfe10822301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276681354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3276681354
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3205339997
Short name T70
Test name
Test status
Simulation time 617777147040 ps
CPU time 1492.02 seconds
Started Jun 24 06:20:32 PM PDT 24
Finished Jun 24 06:45:25 PM PDT 24
Peak memory 195908 kb
Host smart-baba2fe7-5bd1-4a6f-9dbc-344c8b82e8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205339997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3205339997
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1274393728
Short name T19
Test name
Test status
Simulation time 33095187 ps
CPU time 0.71 seconds
Started Jun 24 06:20:24 PM PDT 24
Finished Jun 24 06:20:25 PM PDT 24
Peak memory 213204 kb
Host smart-66e3ddff-ef42-40de-908d-c6e49da6bd0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274393728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1274393728
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/187.rv_timer_random.720754664
Short name T113
Test name
Test status
Simulation time 191627349759 ps
CPU time 953.01 seconds
Started Jun 24 06:26:25 PM PDT 24
Finished Jun 24 06:42:19 PM PDT 24
Peak memory 191072 kb
Host smart-b6e0dba4-33f2-4b79-966d-3118fa6f9e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720754664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.720754664
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1651397568
Short name T75
Test name
Test status
Simulation time 1892478738733 ps
CPU time 1008.06 seconds
Started Jun 24 06:24:06 PM PDT 24
Finished Jun 24 06:40:55 PM PDT 24
Peak memory 191184 kb
Host smart-87020b6f-31f7-4bb9-a28d-f3a08476ecbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651397568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1651397568
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.915040330
Short name T151
Test name
Test status
Simulation time 6577532259396 ps
CPU time 1297.46 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:42:08 PM PDT 24
Peak memory 196508 kb
Host smart-7de2840f-c543-4b34-8bb8-481297d6f387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915040330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.915040330
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.738665808
Short name T68
Test name
Test status
Simulation time 576447644231 ps
CPU time 390.4 seconds
Started Jun 24 06:21:56 PM PDT 24
Finished Jun 24 06:28:27 PM PDT 24
Peak memory 196588 kb
Host smart-98fa62e8-3256-4034-8552-198963bd8d79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738665808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
738665808
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3896330442
Short name T228
Test name
Test status
Simulation time 1236028851878 ps
CPU time 2398.62 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 07:00:22 PM PDT 24
Peak memory 195936 kb
Host smart-7dc85607-5d5e-49e2-80c4-40d2945ac5f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896330442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3896330442
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3209960141
Short name T196
Test name
Test status
Simulation time 557445076074 ps
CPU time 1525.73 seconds
Started Jun 24 06:21:57 PM PDT 24
Finished Jun 24 06:47:24 PM PDT 24
Peak memory 191184 kb
Host smart-f542f4b5-9297-48ac-8de8-ed1a44d8ee34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209960141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3209960141
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/174.rv_timer_random.2260809705
Short name T64
Test name
Test status
Simulation time 281520772465 ps
CPU time 1663.32 seconds
Started Jun 24 06:26:26 PM PDT 24
Finished Jun 24 06:54:09 PM PDT 24
Peak memory 191172 kb
Host smart-7df671f6-2a86-4b8d-b13f-8b80e01eb303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260809705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2260809705
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.1295791481
Short name T217
Test name
Test status
Simulation time 796301480933 ps
CPU time 614.09 seconds
Started Jun 24 06:23:28 PM PDT 24
Finished Jun 24 06:33:43 PM PDT 24
Peak memory 191204 kb
Host smart-fb890abc-64b8-4c3e-9b23-09c16537a3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295791481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1295791481
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.740464469
Short name T207
Test name
Test status
Simulation time 167771108524 ps
CPU time 291.7 seconds
Started Jun 24 06:25:26 PM PDT 24
Finished Jun 24 06:30:18 PM PDT 24
Peak memory 191212 kb
Host smart-2ad51179-62af-43a9-8086-50f2daa10683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740464469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.740464469
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3252586303
Short name T170
Test name
Test status
Simulation time 764596230924 ps
CPU time 470.51 seconds
Started Jun 24 06:25:25 PM PDT 24
Finished Jun 24 06:33:16 PM PDT 24
Peak memory 193240 kb
Host smart-45cecad4-1c1c-4ecd-b421-662f1bc7e03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252586303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3252586303
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3378733957
Short name T129
Test name
Test status
Simulation time 2807829477990 ps
CPU time 1258.34 seconds
Started Jun 24 06:21:37 PM PDT 24
Finished Jun 24 06:42:37 PM PDT 24
Peak memory 191192 kb
Host smart-a847a15a-8e52-4f63-b6df-51e13e5563e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378733957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3378733957
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random.1092958742
Short name T197
Test name
Test status
Simulation time 740846219167 ps
CPU time 799.66 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:33:51 PM PDT 24
Peak memory 193232 kb
Host smart-a02f100d-ed86-4c48-83a4-14146adb74a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092958742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1092958742
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random.3336083679
Short name T167
Test name
Test status
Simulation time 130123794502 ps
CPU time 515.35 seconds
Started Jun 24 06:23:51 PM PDT 24
Finished Jun 24 06:32:27 PM PDT 24
Peak memory 191176 kb
Host smart-b34adc8c-9cfa-46c3-a7d2-5fc458acca2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336083679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3336083679
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1132786608
Short name T240
Test name
Test status
Simulation time 709854236237 ps
CPU time 516.86 seconds
Started Jun 24 06:25:09 PM PDT 24
Finished Jun 24 06:33:46 PM PDT 24
Peak memory 191164 kb
Host smart-e5c639a1-7ab6-4ac0-8439-cf71ef781c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132786608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1132786608
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2581187760
Short name T278
Test name
Test status
Simulation time 347584686571 ps
CPU time 478.44 seconds
Started Jun 24 06:26:28 PM PDT 24
Finished Jun 24 06:34:27 PM PDT 24
Peak memory 193720 kb
Host smart-471589d0-de6e-4eaf-92c3-b4fbd6249970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581187760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2581187760
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4181904931
Short name T71
Test name
Test status
Simulation time 668337788675 ps
CPU time 969.06 seconds
Started Jun 24 06:22:50 PM PDT 24
Finished Jun 24 06:38:59 PM PDT 24
Peak memory 191196 kb
Host smart-b92393c3-2f9f-4e1e-a531-bbfcc6e899f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181904931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4181904931
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1076630129
Short name T146
Test name
Test status
Simulation time 838004913353 ps
CPU time 872.52 seconds
Started Jun 24 06:24:24 PM PDT 24
Finished Jun 24 06:38:57 PM PDT 24
Peak memory 191168 kb
Host smart-118c13b1-ac1e-45c9-b112-cd4ca581112d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076630129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1076630129
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1415753004
Short name T89
Test name
Test status
Simulation time 85721725 ps
CPU time 0.74 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:17 PM PDT 24
Peak memory 191700 kb
Host smart-05454729-f58e-4edc-9060-24fd36b0d2ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415753004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1415753004
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/110.rv_timer_random.1376966760
Short name T136
Test name
Test status
Simulation time 195885666956 ps
CPU time 700.67 seconds
Started Jun 24 06:25:27 PM PDT 24
Finished Jun 24 06:37:08 PM PDT 24
Peak memory 191180 kb
Host smart-381e2cf8-dd49-4d85-95d5-ba957b10c470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376966760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1376966760
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.854028800
Short name T179
Test name
Test status
Simulation time 695714037668 ps
CPU time 947.36 seconds
Started Jun 24 06:25:27 PM PDT 24
Finished Jun 24 06:41:15 PM PDT 24
Peak memory 191180 kb
Host smart-d0ab24af-7a2c-41af-85d5-95aae78fd6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854028800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.854028800
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.13610919
Short name T441
Test name
Test status
Simulation time 194707854212 ps
CPU time 555.6 seconds
Started Jun 24 06:20:54 PM PDT 24
Finished Jun 24 06:30:10 PM PDT 24
Peak memory 191180 kb
Host smart-d4a37470-cc00-4ef7-8440-e52a6b84b4b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13610919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.13610919
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.2890576949
Short name T257
Test name
Test status
Simulation time 662546154902 ps
CPU time 309.64 seconds
Started Jun 24 06:26:36 PM PDT 24
Finished Jun 24 06:31:46 PM PDT 24
Peak memory 191176 kb
Host smart-87bd317e-7a4a-44d1-97ef-8f132c41732b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890576949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2890576949
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3478391855
Short name T317
Test name
Test status
Simulation time 139729897698 ps
CPU time 344.66 seconds
Started Jun 24 06:24:59 PM PDT 24
Finished Jun 24 06:30:44 PM PDT 24
Peak memory 191172 kb
Host smart-aae05263-928a-4ff4-b9a9-c596c3a987a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478391855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3478391855
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.4226575193
Short name T176
Test name
Test status
Simulation time 140056982997 ps
CPU time 269.34 seconds
Started Jun 24 06:25:09 PM PDT 24
Finished Jun 24 06:29:39 PM PDT 24
Peak memory 194736 kb
Host smart-e6075805-e34e-447d-b1a2-b0136a93b47c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226575193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.4226575193
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3926031788
Short name T133
Test name
Test status
Simulation time 714394087361 ps
CPU time 574.14 seconds
Started Jun 24 06:25:27 PM PDT 24
Finished Jun 24 06:35:02 PM PDT 24
Peak memory 191188 kb
Host smart-8832d920-4dbe-430f-abb4-b0e409f692e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926031788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3926031788
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2241609822
Short name T72
Test name
Test status
Simulation time 1754652357387 ps
CPU time 1152.22 seconds
Started Jun 24 06:20:56 PM PDT 24
Finished Jun 24 06:40:09 PM PDT 24
Peak memory 191188 kb
Host smart-21af6c3d-7d2e-4b41-a415-8c9c7fdaf117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241609822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2241609822
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/137.rv_timer_random.927686064
Short name T253
Test name
Test status
Simulation time 141493493272 ps
CPU time 277.41 seconds
Started Jun 24 06:25:46 PM PDT 24
Finished Jun 24 06:30:24 PM PDT 24
Peak memory 191208 kb
Host smart-6abc43fc-da97-44c7-95d4-c5a62f075e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927686064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.927686064
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.482657920
Short name T115
Test name
Test status
Simulation time 669927328269 ps
CPU time 1180.57 seconds
Started Jun 24 06:21:12 PM PDT 24
Finished Jun 24 06:40:54 PM PDT 24
Peak memory 182984 kb
Host smart-9b987b58-589e-4e26-af03-2b622a5de09e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482657920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.482657920
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/182.rv_timer_random.3048479465
Short name T248
Test name
Test status
Simulation time 711835799173 ps
CPU time 334.15 seconds
Started Jun 24 06:26:25 PM PDT 24
Finished Jun 24 06:31:59 PM PDT 24
Peak memory 191184 kb
Host smart-df86fab1-0f7e-445e-9b4c-b58437a9a362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048479465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3048479465
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.247879205
Short name T270
Test name
Test status
Simulation time 414691024589 ps
CPU time 998.92 seconds
Started Jun 24 06:23:00 PM PDT 24
Finished Jun 24 06:39:40 PM PDT 24
Peak memory 191180 kb
Host smart-92a60469-4a34-416b-84d9-154ec01cc153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247879205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.247879205
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.3628046517
Short name T216
Test name
Test status
Simulation time 158252178009 ps
CPU time 265.64 seconds
Started Jun 24 06:24:45 PM PDT 24
Finished Jun 24 06:29:11 PM PDT 24
Peak memory 182984 kb
Host smart-3e804f0e-c9f0-48a0-8647-de02feee99e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628046517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3628046517
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2005690980
Short name T213
Test name
Test status
Simulation time 656264411641 ps
CPU time 589.28 seconds
Started Jun 24 06:24:52 PM PDT 24
Finished Jun 24 06:34:42 PM PDT 24
Peak memory 191168 kb
Host smart-69c56e90-2fee-4c63-b77a-88cf4e47fafd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005690980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2005690980
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.329468818
Short name T299
Test name
Test status
Simulation time 141699514443 ps
CPU time 192.01 seconds
Started Jun 24 06:25:17 PM PDT 24
Finished Jun 24 06:28:29 PM PDT 24
Peak memory 191184 kb
Host smart-c1ed420d-cee3-4609-8ebf-0558d96a52a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329468818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.329468818
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3725707775
Short name T112
Test name
Test status
Simulation time 102946943406 ps
CPU time 1737.21 seconds
Started Jun 24 06:25:25 PM PDT 24
Finished Jun 24 06:54:23 PM PDT 24
Peak memory 194648 kb
Host smart-6f1133ff-467d-4788-9e9a-3efc25864440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725707775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3725707775
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2243327041
Short name T173
Test name
Test status
Simulation time 115957211166 ps
CPU time 366.63 seconds
Started Jun 24 06:25:42 PM PDT 24
Finished Jun 24 06:31:49 PM PDT 24
Peak memory 191176 kb
Host smart-ad098e1f-f046-4041-a3c2-25df0f1dab1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243327041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2243327041
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.1055481165
Short name T141
Test name
Test status
Simulation time 985895735256 ps
CPU time 384.51 seconds
Started Jun 24 06:21:13 PM PDT 24
Finished Jun 24 06:27:38 PM PDT 24
Peak memory 191196 kb
Host smart-3c83a44a-dc07-448b-9c2f-70ba7fb3b417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055481165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1055481165
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2336423877
Short name T161
Test name
Test status
Simulation time 326549984778 ps
CPU time 254.78 seconds
Started Jun 24 06:26:25 PM PDT 24
Finished Jun 24 06:30:40 PM PDT 24
Peak memory 191196 kb
Host smart-359402c4-b61d-4e86-89da-6a661bf87c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336423877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2336423877
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3257815226
Short name T203
Test name
Test status
Simulation time 1211391334254 ps
CPU time 533.93 seconds
Started Jun 24 06:21:22 PM PDT 24
Finished Jun 24 06:30:17 PM PDT 24
Peak memory 182980 kb
Host smart-92789313-cc2b-4281-9626-1bbad67ed045
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257815226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3257815226
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3765560010
Short name T285
Test name
Test status
Simulation time 361087850833 ps
CPU time 306.45 seconds
Started Jun 24 06:21:21 PM PDT 24
Finished Jun 24 06:26:28 PM PDT 24
Peak memory 195300 kb
Host smart-a359618c-1a2d-46f3-b5f2-d2ea1be4f81c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765560010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3765560010
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.600105956
Short name T331
Test name
Test status
Simulation time 1559464595865 ps
CPU time 802.36 seconds
Started Jun 24 06:21:38 PM PDT 24
Finished Jun 24 06:35:01 PM PDT 24
Peak memory 182972 kb
Host smart-1e1ad921-b849-4d90-9aae-4b71e0a47917
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600105956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.600105956
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1194129811
Short name T171
Test name
Test status
Simulation time 2121062403402 ps
CPU time 990.48 seconds
Started Jun 24 06:23:16 PM PDT 24
Finished Jun 24 06:39:47 PM PDT 24
Peak memory 183004 kb
Host smart-ce0bddb4-8313-498d-8588-4951adae6e73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194129811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1194129811
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1127167320
Short name T310
Test name
Test status
Simulation time 2330715163657 ps
CPU time 883.5 seconds
Started Jun 24 06:23:23 PM PDT 24
Finished Jun 24 06:38:07 PM PDT 24
Peak memory 191416 kb
Host smart-7db8f2dc-d25a-4182-b3a6-405cac9e2321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127167320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1127167320
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2884096218
Short name T81
Test name
Test status
Simulation time 36178263 ps
CPU time 0.86 seconds
Started Jun 24 05:39:16 PM PDT 24
Finished Jun 24 05:39:19 PM PDT 24
Peak memory 192564 kb
Host smart-f324e59f-b003-43a4-8b1a-0911e29205fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884096218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2884096218
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/112.rv_timer_random.1541218335
Short name T256
Test name
Test status
Simulation time 107058009874 ps
CPU time 148.19 seconds
Started Jun 24 06:25:27 PM PDT 24
Finished Jun 24 06:27:56 PM PDT 24
Peak memory 191128 kb
Host smart-168fa91c-b69c-49f9-8072-663253d90756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541218335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1541218335
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2163502661
Short name T122
Test name
Test status
Simulation time 759219833729 ps
CPU time 1368.92 seconds
Started Jun 24 06:25:52 PM PDT 24
Finished Jun 24 06:48:41 PM PDT 24
Peak memory 191176 kb
Host smart-f02b40fe-0553-4e01-bb0f-b9461e3a3bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163502661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2163502661
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.793691870
Short name T103
Test name
Test status
Simulation time 373733389571 ps
CPU time 233.77 seconds
Started Jun 24 06:26:15 PM PDT 24
Finished Jun 24 06:30:10 PM PDT 24
Peak memory 191168 kb
Host smart-ddad3bc6-7bd3-4990-9d62-2a0e4bff2edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793691870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.793691870
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2891282265
Short name T283
Test name
Test status
Simulation time 413337988712 ps
CPU time 1650.51 seconds
Started Jun 24 06:26:25 PM PDT 24
Finished Jun 24 06:53:56 PM PDT 24
Peak memory 191172 kb
Host smart-355aa4b5-dccf-4120-a792-84193b9e9c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891282265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2891282265
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4248682877
Short name T206
Test name
Test status
Simulation time 474964393216 ps
CPU time 162.05 seconds
Started Jun 24 06:21:11 PM PDT 24
Finished Jun 24 06:23:53 PM PDT 24
Peak memory 182872 kb
Host smart-f5a38cbf-cecb-4ff5-8575-c130654c6468
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248682877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.4248682877
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.2850548210
Short name T110
Test name
Test status
Simulation time 209570587785 ps
CPU time 1365.09 seconds
Started Jun 24 06:21:46 PM PDT 24
Finished Jun 24 06:44:31 PM PDT 24
Peak memory 191184 kb
Host smart-fd8f52ec-9f6d-4dd4-a48d-41c0a25275f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850548210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2850548210
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3099673616
Short name T121
Test name
Test status
Simulation time 2037325808014 ps
CPU time 1421.8 seconds
Started Jun 24 06:22:07 PM PDT 24
Finished Jun 24 06:45:49 PM PDT 24
Peak memory 191196 kb
Host smart-d1cbd344-1b2f-448b-802e-721cd977ab13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099673616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3099673616
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1213088770
Short name T177
Test name
Test status
Simulation time 362322111200 ps
CPU time 539.34 seconds
Started Jun 24 06:23:50 PM PDT 24
Finished Jun 24 06:32:49 PM PDT 24
Peak memory 193596 kb
Host smart-a530a4b0-2d35-4173-8003-f894bc49708e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213088770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1213088770
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/67.rv_timer_random.1054190209
Short name T29
Test name
Test status
Simulation time 266799497396 ps
CPU time 707.56 seconds
Started Jun 24 06:24:46 PM PDT 24
Finished Jun 24 06:36:33 PM PDT 24
Peak memory 191184 kb
Host smart-172e8306-e23b-45f5-9682-f633120dc15d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054190209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1054190209
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2522090184
Short name T198
Test name
Test status
Simulation time 610740818991 ps
CPU time 592.81 seconds
Started Jun 24 06:24:52 PM PDT 24
Finished Jun 24 06:34:46 PM PDT 24
Peak memory 194800 kb
Host smart-5a58d56c-f622-4a18-aa65-c614204b5214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522090184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2522090184
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.1649830745
Short name T204
Test name
Test status
Simulation time 117169795155 ps
CPU time 479.25 seconds
Started Jun 24 06:20:39 PM PDT 24
Finished Jun 24 06:28:39 PM PDT 24
Peak memory 193340 kb
Host smart-1acf3be7-8613-4c0f-9382-620f19dd84c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649830745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1649830745
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.488362921
Short name T56
Test name
Test status
Simulation time 532348251 ps
CPU time 1.39 seconds
Started Jun 24 05:39:23 PM PDT 24
Finished Jun 24 05:39:25 PM PDT 24
Peak memory 195436 kb
Host smart-2a3542dd-fd4a-4bd6-a475-2e2c6e1d3cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488362921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.488362921
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.191604892
Short name T59
Test name
Test status
Simulation time 92679345509 ps
CPU time 231.32 seconds
Started Jun 24 06:20:12 PM PDT 24
Finished Jun 24 06:24:05 PM PDT 24
Peak memory 191180 kb
Host smart-64b4a973-b7be-4fdf-a8cb-cb74aa95c3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191604892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.191604892
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2060452357
Short name T316
Test name
Test status
Simulation time 28285635641 ps
CPU time 43.41 seconds
Started Jun 24 06:20:24 PM PDT 24
Finished Jun 24 06:21:08 PM PDT 24
Peak memory 182980 kb
Host smart-a0f844d5-7339-4dc4-9145-ce7882d548d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060452357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2060452357
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.253753454
Short name T356
Test name
Test status
Simulation time 22490285388 ps
CPU time 15.72 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:20:39 PM PDT 24
Peak memory 194300 kb
Host smart-f894fb78-e564-4c79-a888-b7c304b9cff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253753454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.253753454
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/104.rv_timer_random.1296922103
Short name T192
Test name
Test status
Simulation time 993159707592 ps
CPU time 854.87 seconds
Started Jun 24 06:25:17 PM PDT 24
Finished Jun 24 06:39:33 PM PDT 24
Peak memory 191184 kb
Host smart-2c102ce6-7151-438e-8bf5-be719c3061ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296922103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1296922103
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.176020229
Short name T266
Test name
Test status
Simulation time 45993077384 ps
CPU time 371.38 seconds
Started Jun 24 06:25:26 PM PDT 24
Finished Jun 24 06:31:39 PM PDT 24
Peak memory 182988 kb
Host smart-af159d80-0818-4be6-a1c1-c8f7396ebbcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176020229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.176020229
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1421871656
Short name T265
Test name
Test status
Simulation time 1333730754576 ps
CPU time 274.8 seconds
Started Jun 24 06:25:27 PM PDT 24
Finished Jun 24 06:30:02 PM PDT 24
Peak memory 191200 kb
Host smart-8099e266-cd03-46ac-9970-f7aa8277c92d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421871656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1421871656
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.4242726828
Short name T260
Test name
Test status
Simulation time 150794842174 ps
CPU time 532.9 seconds
Started Jun 24 06:25:36 PM PDT 24
Finished Jun 24 06:34:29 PM PDT 24
Peak memory 191180 kb
Host smart-87fa6ee7-f04b-435b-9750-0498a3856a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242726828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.4242726828
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2607774552
Short name T168
Test name
Test status
Simulation time 569160721463 ps
CPU time 366.64 seconds
Started Jun 24 06:25:35 PM PDT 24
Finished Jun 24 06:31:42 PM PDT 24
Peak memory 191184 kb
Host smart-c3b9215a-793c-41b3-a0cd-50630bae85e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607774552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2607774552
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1198144749
Short name T242
Test name
Test status
Simulation time 16769971070 ps
CPU time 16.42 seconds
Started Jun 24 06:25:46 PM PDT 24
Finished Jun 24 06:26:03 PM PDT 24
Peak memory 191204 kb
Host smart-677b51ee-1a44-40da-9f92-9fddc9cb7db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198144749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1198144749
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1746261710
Short name T275
Test name
Test status
Simulation time 1279120580907 ps
CPU time 879.8 seconds
Started Jun 24 06:20:57 PM PDT 24
Finished Jun 24 06:35:37 PM PDT 24
Peak memory 182684 kb
Host smart-4c5603ea-0029-4dce-8427-fb4100036746
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746261710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1746261710
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random.4245865942
Short name T175
Test name
Test status
Simulation time 280238560177 ps
CPU time 163.48 seconds
Started Jun 24 06:20:59 PM PDT 24
Finished Jun 24 06:23:43 PM PDT 24
Peak memory 191188 kb
Host smart-f9a4c523-54dc-4830-80e4-8ef3edcbda07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245865942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.4245865942
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3413286939
Short name T238
Test name
Test status
Simulation time 7520371723 ps
CPU time 10.95 seconds
Started Jun 24 06:21:03 PM PDT 24
Finished Jun 24 06:21:14 PM PDT 24
Peak memory 182988 kb
Host smart-5bfe3b7e-7c8c-4a47-b41f-770e92c9f638
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413286939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3413286939
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/151.rv_timer_random.3932003063
Short name T156
Test name
Test status
Simulation time 421886995419 ps
CPU time 223.07 seconds
Started Jun 24 06:25:58 PM PDT 24
Finished Jun 24 06:29:41 PM PDT 24
Peak memory 191208 kb
Host smart-e61cea62-7fdf-4b27-8690-35d558e9a25a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932003063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3932003063
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1094342319
Short name T336
Test name
Test status
Simulation time 32772370728 ps
CPU time 545.64 seconds
Started Jun 24 06:26:07 PM PDT 24
Finished Jun 24 06:35:13 PM PDT 24
Peak memory 191204 kb
Host smart-97b89d7b-48d0-4a7e-a0f6-543b287690c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094342319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1094342319
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2757599195
Short name T226
Test name
Test status
Simulation time 60044224252 ps
CPU time 671.19 seconds
Started Jun 24 06:21:19 PM PDT 24
Finished Jun 24 06:32:31 PM PDT 24
Peak memory 206268 kb
Host smart-8150ff5c-2ce5-4d98-a529-84705578e846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757599195 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2757599195
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.1069173289
Short name T323
Test name
Test status
Simulation time 72345838264 ps
CPU time 488.98 seconds
Started Jun 24 06:26:26 PM PDT 24
Finished Jun 24 06:34:36 PM PDT 24
Peak memory 191172 kb
Host smart-cd1a697e-aa3c-4b13-8737-2ddaba622803
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069173289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1069173289
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3405045606
Short name T6
Test name
Test status
Simulation time 422060666333 ps
CPU time 137.72 seconds
Started Jun 24 06:26:42 PM PDT 24
Finished Jun 24 06:29:00 PM PDT 24
Peak memory 191072 kb
Host smart-bcc7a70e-8c21-4d30-99f8-f865ad32e783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405045606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3405045606
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.418250543
Short name T271
Test name
Test status
Simulation time 617173449913 ps
CPU time 967.9 seconds
Started Jun 24 06:21:29 PM PDT 24
Finished Jun 24 06:37:37 PM PDT 24
Peak memory 182988 kb
Host smart-ec075b38-fb32-43ae-afec-372cc785048e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418250543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.418250543
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3223695238
Short name T297
Test name
Test status
Simulation time 56986929584 ps
CPU time 41.46 seconds
Started Jun 24 06:21:29 PM PDT 24
Finished Jun 24 06:22:10 PM PDT 24
Peak memory 183004 kb
Host smart-96b75af2-babc-4aa5-9f04-084fd03dff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223695238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3223695238
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_random.801904998
Short name T290
Test name
Test status
Simulation time 153806284842 ps
CPU time 403.17 seconds
Started Jun 24 06:21:57 PM PDT 24
Finished Jun 24 06:28:41 PM PDT 24
Peak memory 191180 kb
Host smart-cb3fe566-a9ef-4465-9fa7-e7c579128cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801904998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.801904998
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3427747390
Short name T24
Test name
Test status
Simulation time 26723197027 ps
CPU time 46.1 seconds
Started Jun 24 06:22:09 PM PDT 24
Finished Jun 24 06:22:56 PM PDT 24
Peak memory 182976 kb
Host smart-1819970c-9634-43a3-b751-6b2cbbe8afc4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427747390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3427747390
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2104015230
Short name T234
Test name
Test status
Simulation time 337759708171 ps
CPU time 157.71 seconds
Started Jun 24 06:22:33 PM PDT 24
Finished Jun 24 06:25:12 PM PDT 24
Peak memory 195496 kb
Host smart-0c9f3be3-5ece-4fc6-b050-188207c2b66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104015230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2104015230
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3103583898
Short name T195
Test name
Test status
Simulation time 997304929243 ps
CPU time 2915.33 seconds
Started Jun 24 06:23:09 PM PDT 24
Finished Jun 24 07:11:45 PM PDT 24
Peak memory 195952 kb
Host smart-307ab8fd-5549-4617-a7e6-3676615169be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103583898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3103583898
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.168733071
Short name T305
Test name
Test status
Simulation time 12469941968 ps
CPU time 6.46 seconds
Started Jun 24 06:23:43 PM PDT 24
Finished Jun 24 06:23:50 PM PDT 24
Peak memory 182972 kb
Host smart-d8f46da1-4e17-4ed5-9665-af56b6ad0c98
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168733071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.168733071
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3619560026
Short name T319
Test name
Test status
Simulation time 159675531416 ps
CPU time 1456.15 seconds
Started Jun 24 06:24:06 PM PDT 24
Finished Jun 24 06:48:23 PM PDT 24
Peak memory 183056 kb
Host smart-981ce4cc-2e14-4459-9365-fab9aec5e103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619560026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3619560026
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1021540367
Short name T326
Test name
Test status
Simulation time 1846308573045 ps
CPU time 431.42 seconds
Started Jun 24 06:20:40 PM PDT 24
Finished Jun 24 06:27:53 PM PDT 24
Peak memory 182984 kb
Host smart-a49744dd-711b-490c-a495-8e66ad004823
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021540367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1021540367
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1155614801
Short name T244
Test name
Test status
Simulation time 506867119665 ps
CPU time 584.89 seconds
Started Jun 24 06:20:41 PM PDT 24
Finished Jun 24 06:30:27 PM PDT 24
Peak memory 191176 kb
Host smart-c725c246-0dbc-4b5d-a640-a54de41a772e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155614801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1155614801
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3291326388
Short name T86
Test name
Test status
Simulation time 121011974 ps
CPU time 2.32 seconds
Started Jun 24 05:39:12 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 191080 kb
Host smart-f0f37e45-b3e0-4d85-8d4d-327cbf53bec7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291326388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3291326388
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2196383257
Short name T537
Test name
Test status
Simulation time 13539985 ps
CPU time 0.56 seconds
Started Jun 24 05:39:15 PM PDT 24
Finished Jun 24 05:39:18 PM PDT 24
Peak memory 182680 kb
Host smart-81b2646c-9aef-4475-877f-f1be7e4b5fcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196383257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2196383257
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.716522084
Short name T560
Test name
Test status
Simulation time 40979912 ps
CPU time 0.8 seconds
Started Jun 24 05:39:11 PM PDT 24
Finished Jun 24 05:39:13 PM PDT 24
Peak memory 195448 kb
Host smart-b664aa2c-f198-4d32-a46a-6d9d91641d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716522084 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.716522084
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.280412522
Short name T577
Test name
Test status
Simulation time 17574906 ps
CPU time 0.62 seconds
Started Jun 24 05:39:13 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 182680 kb
Host smart-a2b4c3fa-4153-4e66-bad2-31862d2bfde6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280412522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.280412522
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2666766632
Short name T542
Test name
Test status
Simulation time 91719203 ps
CPU time 0.55 seconds
Started Jun 24 05:39:13 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 182560 kb
Host smart-c3ec8acd-6c87-44e5-ace5-4e340c8ccb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666766632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2666766632
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1577570882
Short name T80
Test name
Test status
Simulation time 32197153 ps
CPU time 0.8 seconds
Started Jun 24 05:39:15 PM PDT 24
Finished Jun 24 05:39:18 PM PDT 24
Peak memory 191852 kb
Host smart-23f3e387-36ad-4142-8b78-b43f748db1fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577570882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1577570882
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2469732144
Short name T551
Test name
Test status
Simulation time 93818002 ps
CPU time 1.39 seconds
Started Jun 24 05:39:15 PM PDT 24
Finished Jun 24 05:39:18 PM PDT 24
Peak memory 197552 kb
Host smart-79ed2817-3dc4-447d-8ac3-14073ddfc0be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469732144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2469732144
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1273025056
Short name T475
Test name
Test status
Simulation time 804040060 ps
CPU time 1.47 seconds
Started Jun 24 05:39:13 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 194992 kb
Host smart-3a8b39b3-46ac-4c8e-8358-ee809c82ef51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273025056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1273025056
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.360062589
Short name T87
Test name
Test status
Simulation time 111503875 ps
CPU time 0.73 seconds
Started Jun 24 05:39:13 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 192304 kb
Host smart-ec83e17e-135d-449f-8cbe-d2b446ea90ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360062589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.360062589
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.690465916
Short name T555
Test name
Test status
Simulation time 64779825 ps
CPU time 2.35 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:18 PM PDT 24
Peak memory 190856 kb
Host smart-e5b17e3d-7979-4941-987d-daa3677897fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690465916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.690465916
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2615726051
Short name T53
Test name
Test status
Simulation time 17235468 ps
CPU time 0.57 seconds
Started Jun 24 05:39:10 PM PDT 24
Finished Jun 24 05:39:11 PM PDT 24
Peak memory 182688 kb
Host smart-0168accf-a56e-45e0-a3ad-ae57da3a462f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615726051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2615726051
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2171632674
Short name T535
Test name
Test status
Simulation time 56221937 ps
CPU time 1.07 seconds
Started Jun 24 05:39:12 PM PDT 24
Finished Jun 24 05:39:15 PM PDT 24
Peak memory 197492 kb
Host smart-c8d2d582-5d02-49db-9536-18d5c4f9c46d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171632674 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2171632674
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1183062068
Short name T77
Test name
Test status
Simulation time 34732879 ps
CPU time 0.61 seconds
Started Jun 24 05:39:13 PM PDT 24
Finished Jun 24 05:39:15 PM PDT 24
Peak memory 182684 kb
Host smart-08b157c5-b869-4e73-a37f-e3e2abb5f3c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183062068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1183062068
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2346645026
Short name T459
Test name
Test status
Simulation time 47115805 ps
CPU time 0.56 seconds
Started Jun 24 05:39:13 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 182628 kb
Host smart-a7a30a41-4062-4fdf-99d8-a7391f1e95b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346645026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2346645026
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4208177829
Short name T95
Test name
Test status
Simulation time 56699887 ps
CPU time 0.62 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 191828 kb
Host smart-78b047ba-afe5-49c6-86cc-8d62da952344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208177829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4208177829
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.671283401
Short name T462
Test name
Test status
Simulation time 166793364 ps
CPU time 1.2 seconds
Started Jun 24 05:39:15 PM PDT 24
Finished Jun 24 05:39:18 PM PDT 24
Peak memory 195884 kb
Host smart-e88fd522-4ab1-4aa8-b760-fb8c28691655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671283401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.671283401
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2686505806
Short name T463
Test name
Test status
Simulation time 119953423 ps
CPU time 0.81 seconds
Started Jun 24 05:39:12 PM PDT 24
Finished Jun 24 05:39:14 PM PDT 24
Peak memory 183128 kb
Host smart-5a50f4ac-e2e6-4ef0-8578-52f614727302
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686505806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2686505806
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1236700773
Short name T557
Test name
Test status
Simulation time 23794700 ps
CPU time 0.69 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:28 PM PDT 24
Peak memory 194680 kb
Host smart-0d56752c-670d-42cd-9662-dfb529fe0810
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236700773 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1236700773
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4207953744
Short name T469
Test name
Test status
Simulation time 14737593 ps
CPU time 0.58 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:30 PM PDT 24
Peak memory 182904 kb
Host smart-0ba9a085-d2e3-4515-87c5-b5874718f9d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207953744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4207953744
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3318080200
Short name T541
Test name
Test status
Simulation time 14413408 ps
CPU time 0.52 seconds
Started Jun 24 05:39:24 PM PDT 24
Finished Jun 24 05:39:26 PM PDT 24
Peak memory 182052 kb
Host smart-577c5f5e-ff20-4948-bfbe-ccf6a3c6d3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318080200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3318080200
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2943751669
Short name T566
Test name
Test status
Simulation time 56443036 ps
CPU time 0.79 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:30 PM PDT 24
Peak memory 193420 kb
Host smart-45c8e1e3-05ab-4cb1-b26a-d135307542f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943751669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2943751669
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.943313881
Short name T470
Test name
Test status
Simulation time 29691815 ps
CPU time 1.27 seconds
Started Jun 24 05:39:24 PM PDT 24
Finished Jun 24 05:39:27 PM PDT 24
Peak memory 196608 kb
Host smart-e468cb33-23c0-4bc4-89f5-bbef14fbbc2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943313881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.943313881
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.650759645
Short name T548
Test name
Test status
Simulation time 36910297 ps
CPU time 1.53 seconds
Started Jun 24 05:39:23 PM PDT 24
Finished Jun 24 05:39:26 PM PDT 24
Peak memory 197576 kb
Host smart-6148d9bd-628b-4ede-9254-11cf6d82d938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650759645 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.650759645
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3295063949
Short name T58
Test name
Test status
Simulation time 42686489 ps
CPU time 0.57 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:31 PM PDT 24
Peak memory 182608 kb
Host smart-9ae8db34-2628-48be-976a-a81cb1c13e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295063949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3295063949
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4239962772
Short name T489
Test name
Test status
Simulation time 12324094 ps
CPU time 0.57 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:28 PM PDT 24
Peak memory 182468 kb
Host smart-444455e4-785c-4142-b092-ccfd0b500ee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239962772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4239962772
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.946278468
Short name T90
Test name
Test status
Simulation time 67328439 ps
CPU time 0.77 seconds
Started Jun 24 05:39:23 PM PDT 24
Finished Jun 24 05:39:25 PM PDT 24
Peak memory 191680 kb
Host smart-f1be9a1b-9c7b-48f2-888f-e59a226338f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946278468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.946278468
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1633402744
Short name T515
Test name
Test status
Simulation time 42995853 ps
CPU time 1.06 seconds
Started Jun 24 05:39:22 PM PDT 24
Finished Jun 24 05:39:23 PM PDT 24
Peak memory 196208 kb
Host smart-f133c779-a098-4174-9807-9cc89327d6c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633402744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1633402744
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.135930094
Short name T561
Test name
Test status
Simulation time 48560769 ps
CPU time 0.86 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 182944 kb
Host smart-b383c75d-751a-4da5-973d-c8419c2207a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135930094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.135930094
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.811198143
Short name T525
Test name
Test status
Simulation time 71760094 ps
CPU time 1.11 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 197592 kb
Host smart-28e5f52b-d427-4adc-8693-36b71323ea6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811198143 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.811198143
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1382646871
Short name T556
Test name
Test status
Simulation time 21782466 ps
CPU time 0.54 seconds
Started Jun 24 05:39:24 PM PDT 24
Finished Jun 24 05:39:26 PM PDT 24
Peak memory 182652 kb
Host smart-6927cd0c-4b16-45fe-adee-39aa9d59d1a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382646871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1382646871
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3941309269
Short name T567
Test name
Test status
Simulation time 236581952 ps
CPU time 0.56 seconds
Started Jun 24 05:39:25 PM PDT 24
Finished Jun 24 05:39:27 PM PDT 24
Peak memory 182564 kb
Host smart-75e3dd95-bcfe-43d7-ac67-3686088437a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941309269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3941309269
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2444040767
Short name T514
Test name
Test status
Simulation time 32252176 ps
CPU time 0.66 seconds
Started Jun 24 05:39:22 PM PDT 24
Finished Jun 24 05:39:24 PM PDT 24
Peak memory 191964 kb
Host smart-3b25dac5-d724-4ca2-9e15-f6b26eb10d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444040767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2444040767
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2540408194
Short name T466
Test name
Test status
Simulation time 35609763 ps
CPU time 1.05 seconds
Started Jun 24 05:39:28 PM PDT 24
Finished Jun 24 05:39:32 PM PDT 24
Peak memory 197360 kb
Host smart-7ca52a0f-8f24-40eb-ac46-16298214dd9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540408194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2540408194
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.710069998
Short name T563
Test name
Test status
Simulation time 38462079 ps
CPU time 0.82 seconds
Started Jun 24 05:39:28 PM PDT 24
Finished Jun 24 05:39:32 PM PDT 24
Peak memory 193452 kb
Host smart-765d70da-35c7-49d3-b596-98859a9c64a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710069998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.710069998
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1154346644
Short name T498
Test name
Test status
Simulation time 37352080 ps
CPU time 0.9 seconds
Started Jun 24 05:39:32 PM PDT 24
Finished Jun 24 05:39:34 PM PDT 24
Peak memory 197200 kb
Host smart-6a3bc58b-cc94-46c2-90b3-cadec35030d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154346644 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1154346644
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2377283904
Short name T533
Test name
Test status
Simulation time 29404749 ps
CPU time 0.57 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:30 PM PDT 24
Peak memory 182712 kb
Host smart-ee7e1e67-84c4-4c40-9c89-99541413656c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377283904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2377283904
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.736735669
Short name T522
Test name
Test status
Simulation time 53559958 ps
CPU time 0.57 seconds
Started Jun 24 05:39:30 PM PDT 24
Finished Jun 24 05:39:32 PM PDT 24
Peak memory 182528 kb
Host smart-582806e2-d806-4e53-b477-357e12dc132b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736735669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.736735669
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1679047224
Short name T507
Test name
Test status
Simulation time 53076701 ps
CPU time 0.61 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:38 PM PDT 24
Peak memory 191668 kb
Host smart-bc007d02-4146-40f2-86cf-a6f7fb9c299d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679047224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1679047224
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3785113597
Short name T495
Test name
Test status
Simulation time 69483037 ps
CPU time 1.78 seconds
Started Jun 24 05:39:25 PM PDT 24
Finished Jun 24 05:39:28 PM PDT 24
Peak memory 197568 kb
Host smart-26129f66-6ed7-4cf6-8809-c136026cb0db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785113597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3785113597
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1405549911
Short name T98
Test name
Test status
Simulation time 132442647 ps
CPU time 1.43 seconds
Started Jun 24 05:39:25 PM PDT 24
Finished Jun 24 05:39:28 PM PDT 24
Peak memory 195212 kb
Host smart-6a9dd99c-3add-42c2-be82-b7e41ce39d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405549911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1405549911
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2199582156
Short name T559
Test name
Test status
Simulation time 31385832 ps
CPU time 0.74 seconds
Started Jun 24 05:39:32 PM PDT 24
Finished Jun 24 05:39:34 PM PDT 24
Peak memory 195144 kb
Host smart-97ae198a-3d1d-4e9a-be77-640124cbe4a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199582156 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2199582156
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3887634465
Short name T572
Test name
Test status
Simulation time 34578030 ps
CPU time 0.56 seconds
Started Jun 24 05:39:32 PM PDT 24
Finished Jun 24 05:39:34 PM PDT 24
Peak memory 182664 kb
Host smart-5feaaf97-bea1-412d-84e9-5a0152fb278c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887634465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3887634465
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.727447324
Short name T570
Test name
Test status
Simulation time 29461196 ps
CPU time 0.56 seconds
Started Jun 24 05:39:39 PM PDT 24
Finished Jun 24 05:39:40 PM PDT 24
Peak memory 182544 kb
Host smart-d12aa798-3e95-4c16-b78e-12e8ca5f654b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727447324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.727447324
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2632414537
Short name T547
Test name
Test status
Simulation time 26968429 ps
CPU time 0.69 seconds
Started Jun 24 05:39:40 PM PDT 24
Finished Jun 24 05:39:42 PM PDT 24
Peak memory 192252 kb
Host smart-1a2f161e-53cf-4442-befc-b159ef9b077f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632414537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2632414537
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3248156007
Short name T450
Test name
Test status
Simulation time 352570061 ps
CPU time 3.1 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:42 PM PDT 24
Peak memory 197568 kb
Host smart-790d38a0-3d27-4aa7-b306-8e289ef92fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248156007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3248156007
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1918437094
Short name T568
Test name
Test status
Simulation time 620990825 ps
CPU time 1.22 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:40 PM PDT 24
Peak memory 183412 kb
Host smart-131b0043-b233-4b7e-a8b1-39526efb32c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918437094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1918437094
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1572607103
Short name T464
Test name
Test status
Simulation time 69130000 ps
CPU time 0.81 seconds
Started Jun 24 05:39:33 PM PDT 24
Finished Jun 24 05:39:35 PM PDT 24
Peak memory 195944 kb
Host smart-3d5cda47-050f-4f3f-92e8-e90d4058c30a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572607103 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1572607103
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3712457299
Short name T574
Test name
Test status
Simulation time 46351595 ps
CPU time 0.69 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:39 PM PDT 24
Peak memory 182624 kb
Host smart-9df8f938-ddee-4939-b567-3d920b97d7f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712457299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3712457299
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4124514896
Short name T460
Test name
Test status
Simulation time 15451628 ps
CPU time 0.55 seconds
Started Jun 24 05:39:31 PM PDT 24
Finished Jun 24 05:39:33 PM PDT 24
Peak memory 181968 kb
Host smart-7d1d6707-3e6c-4b87-9ef0-019475911647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124514896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4124514896
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.91324933
Short name T510
Test name
Test status
Simulation time 35610333 ps
CPU time 0.81 seconds
Started Jun 24 05:39:34 PM PDT 24
Finished Jun 24 05:39:36 PM PDT 24
Peak memory 191700 kb
Host smart-3ff710be-2c27-4990-b39e-2849e7328bc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91324933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_tim
er_same_csr_outstanding.91324933
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.76789287
Short name T573
Test name
Test status
Simulation time 64524614 ps
CPU time 1.31 seconds
Started Jun 24 05:39:33 PM PDT 24
Finished Jun 24 05:39:36 PM PDT 24
Peak memory 197572 kb
Host smart-dcea00d4-b584-45b3-a6c6-1cd90a198538
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76789287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.76789287
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.53691998
Short name T488
Test name
Test status
Simulation time 109839918 ps
CPU time 1.28 seconds
Started Jun 24 05:39:31 PM PDT 24
Finished Jun 24 05:39:33 PM PDT 24
Peak memory 195640 kb
Host smart-a2973ffb-67bf-4ad2-8ca3-c13f68a0cc63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53691998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_int
g_err.53691998
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2211032038
Short name T468
Test name
Test status
Simulation time 23582878 ps
CPU time 1.08 seconds
Started Jun 24 05:39:36 PM PDT 24
Finished Jun 24 05:39:38 PM PDT 24
Peak memory 197380 kb
Host smart-86b02e85-9a2c-4c73-8d1f-2f626da1de9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211032038 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2211032038
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1934826106
Short name T54
Test name
Test status
Simulation time 55400061 ps
CPU time 0.6 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:39 PM PDT 24
Peak memory 182684 kb
Host smart-f29c4202-cb2c-4121-8797-c31e8bdcc782
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934826106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1934826106
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2554171746
Short name T553
Test name
Test status
Simulation time 18760009 ps
CPU time 0.54 seconds
Started Jun 24 05:39:33 PM PDT 24
Finished Jun 24 05:39:35 PM PDT 24
Peak memory 182032 kb
Host smart-c7206fb1-3ddb-43bf-aadf-b9a8aa8c078b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554171746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2554171746
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2887953722
Short name T550
Test name
Test status
Simulation time 16982328 ps
CPU time 0.7 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:39 PM PDT 24
Peak memory 191944 kb
Host smart-8d8a99f3-bee0-4020-ba04-cfade9343c7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887953722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2887953722
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3496723981
Short name T579
Test name
Test status
Simulation time 180724762 ps
CPU time 2.98 seconds
Started Jun 24 05:39:30 PM PDT 24
Finished Jun 24 05:39:34 PM PDT 24
Peak memory 197580 kb
Host smart-c8c134a6-2df7-4225-8943-7ff36063b143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496723981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3496723981
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3576927218
Short name T540
Test name
Test status
Simulation time 76340919 ps
CPU time 0.83 seconds
Started Jun 24 05:39:35 PM PDT 24
Finished Jun 24 05:39:37 PM PDT 24
Peak memory 182996 kb
Host smart-dddcc45a-5d60-4ab9-a5c7-7baebe8afdee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576927218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3576927218
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3334674776
Short name T513
Test name
Test status
Simulation time 45520808 ps
CPU time 1.18 seconds
Started Jun 24 05:39:33 PM PDT 24
Finished Jun 24 05:39:35 PM PDT 24
Peak memory 197524 kb
Host smart-6ef2416d-433f-4299-8711-c454505b6846
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334674776 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3334674776
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.320026977
Short name T474
Test name
Test status
Simulation time 23939115 ps
CPU time 0.56 seconds
Started Jun 24 05:39:31 PM PDT 24
Finished Jun 24 05:39:33 PM PDT 24
Peak memory 182436 kb
Host smart-274db14b-eadb-4e53-8514-f23ae0b42c23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320026977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.320026977
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3420154126
Short name T532
Test name
Test status
Simulation time 17482961 ps
CPU time 0.55 seconds
Started Jun 24 05:39:36 PM PDT 24
Finished Jun 24 05:39:37 PM PDT 24
Peak memory 182476 kb
Host smart-1f14f137-06fe-46f2-86be-d43d5db33b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420154126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3420154126
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3336434193
Short name T92
Test name
Test status
Simulation time 64347289 ps
CPU time 0.61 seconds
Started Jun 24 05:39:39 PM PDT 24
Finished Jun 24 05:39:40 PM PDT 24
Peak memory 191964 kb
Host smart-de6d81c5-2bd9-4f5d-a62a-5a18943ed8b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336434193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3336434193
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2249051984
Short name T493
Test name
Test status
Simulation time 424373139 ps
CPU time 2.15 seconds
Started Jun 24 05:39:30 PM PDT 24
Finished Jun 24 05:39:34 PM PDT 24
Peak memory 197564 kb
Host smart-18c6a14a-9d2f-4f4c-862f-406b234d078f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249051984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2249051984
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2207712124
Short name T494
Test name
Test status
Simulation time 129917183 ps
CPU time 1.37 seconds
Started Jun 24 05:39:32 PM PDT 24
Finished Jun 24 05:39:35 PM PDT 24
Peak memory 194928 kb
Host smart-17020d31-8c1e-44b5-9d51-f62492bdc3db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207712124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2207712124
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2608668668
Short name T578
Test name
Test status
Simulation time 28974379 ps
CPU time 1.01 seconds
Started Jun 24 05:39:31 PM PDT 24
Finished Jun 24 05:39:33 PM PDT 24
Peak memory 197368 kb
Host smart-f075ab06-070b-46a8-822d-4bf5e8f51ecd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608668668 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2608668668
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1980329051
Short name T492
Test name
Test status
Simulation time 21542749 ps
CPU time 0.55 seconds
Started Jun 24 05:39:34 PM PDT 24
Finished Jun 24 05:39:36 PM PDT 24
Peak memory 182672 kb
Host smart-ea043128-c746-4322-984e-dfa2dd0007dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980329051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1980329051
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.869981991
Short name T487
Test name
Test status
Simulation time 32239602 ps
CPU time 0.56 seconds
Started Jun 24 05:39:30 PM PDT 24
Finished Jun 24 05:39:32 PM PDT 24
Peak memory 182236 kb
Host smart-1f8d2058-52d2-4af9-9bf2-b76809f542f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869981991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.869981991
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3442636185
Short name T91
Test name
Test status
Simulation time 62975046 ps
CPU time 0.64 seconds
Started Jun 24 05:39:36 PM PDT 24
Finished Jun 24 05:39:38 PM PDT 24
Peak memory 191876 kb
Host smart-ebd241b9-dbff-4dd5-81e6-f082632d057f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442636185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3442636185
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.45227291
Short name T67
Test name
Test status
Simulation time 122906399 ps
CPU time 2.19 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:40 PM PDT 24
Peak memory 197536 kb
Host smart-723ad670-d8a3-42cc-b87a-b7305ffb8107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45227291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.45227291
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1174718635
Short name T511
Test name
Test status
Simulation time 183552191 ps
CPU time 1.1 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:39 PM PDT 24
Peak memory 195148 kb
Host smart-bf00609e-ab15-4af8-840a-5e830bec64cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174718635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1174718635
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1963317242
Short name T518
Test name
Test status
Simulation time 34254102 ps
CPU time 0.86 seconds
Started Jun 24 05:39:38 PM PDT 24
Finished Jun 24 05:39:40 PM PDT 24
Peak memory 195156 kb
Host smart-b302383c-eb41-4cb3-80ed-c81474936285
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963317242 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1963317242
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1764385756
Short name T539
Test name
Test status
Simulation time 18175546 ps
CPU time 0.58 seconds
Started Jun 24 05:39:38 PM PDT 24
Finished Jun 24 05:39:40 PM PDT 24
Peak memory 182428 kb
Host smart-486f1204-d89b-492b-9b57-5d33e98e7f80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764385756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1764385756
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1672209913
Short name T481
Test name
Test status
Simulation time 20211796 ps
CPU time 0.58 seconds
Started Jun 24 05:39:35 PM PDT 24
Finished Jun 24 05:39:36 PM PDT 24
Peak memory 182800 kb
Host smart-5db1aef6-ea72-4725-b442-d38c72cccfd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672209913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1672209913
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2915853810
Short name T562
Test name
Test status
Simulation time 96862635 ps
CPU time 0.75 seconds
Started Jun 24 05:39:41 PM PDT 24
Finished Jun 24 05:39:43 PM PDT 24
Peak memory 191632 kb
Host smart-5f4418a3-0adc-46f4-8de5-6f3e70dc7771
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915853810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2915853810
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4129417058
Short name T521
Test name
Test status
Simulation time 216415277 ps
CPU time 1.33 seconds
Started Jun 24 05:39:34 PM PDT 24
Finished Jun 24 05:39:36 PM PDT 24
Peak memory 197540 kb
Host smart-c8dadc49-2eb5-4b03-9d31-7a0a60168efc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129417058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4129417058
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1170630699
Short name T546
Test name
Test status
Simulation time 89391553 ps
CPU time 0.82 seconds
Started Jun 24 05:39:42 PM PDT 24
Finished Jun 24 05:39:44 PM PDT 24
Peak memory 183216 kb
Host smart-53f8c143-fea9-41a7-b57c-5f41461e51d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170630699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1170630699
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2776031938
Short name T528
Test name
Test status
Simulation time 58114916 ps
CPU time 0.65 seconds
Started Jun 24 05:39:13 PM PDT 24
Finished Jun 24 05:39:15 PM PDT 24
Peak memory 191904 kb
Host smart-c4ecba7b-29c4-438e-8d59-cd3465f4faeb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776031938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2776031938
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1309903169
Short name T526
Test name
Test status
Simulation time 300894122 ps
CPU time 1.55 seconds
Started Jun 24 05:39:12 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 191068 kb
Host smart-3e6b336b-78bf-46c2-9e0e-a3e25b33a482
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309903169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1309903169
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1206016177
Short name T476
Test name
Test status
Simulation time 12827287 ps
CPU time 0.55 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:17 PM PDT 24
Peak memory 182136 kb
Host smart-bed1fc28-8529-485d-a4b8-d2e4b4622729
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206016177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1206016177
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.539517853
Short name T517
Test name
Test status
Simulation time 72597509 ps
CPU time 1.01 seconds
Started Jun 24 05:39:11 PM PDT 24
Finished Jun 24 05:39:14 PM PDT 24
Peak memory 197604 kb
Host smart-57243bb6-11dc-4412-bebd-5257502ccf8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539517853 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.539517853
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1359958091
Short name T558
Test name
Test status
Simulation time 50271328 ps
CPU time 0.57 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:17 PM PDT 24
Peak memory 182664 kb
Host smart-9e20156f-52da-448b-9aaa-18678d7f24a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359958091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1359958091
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1677092600
Short name T545
Test name
Test status
Simulation time 39340241 ps
CPU time 0.58 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:16 PM PDT 24
Peak memory 181880 kb
Host smart-4fc95638-16d6-4236-8869-d164deae3d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677092600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1677092600
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1056415361
Short name T456
Test name
Test status
Simulation time 197573466 ps
CPU time 1.32 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:17 PM PDT 24
Peak memory 196840 kb
Host smart-d883efb2-be15-454d-8807-91e195162732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056415361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1056415361
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2708527441
Short name T55
Test name
Test status
Simulation time 179041902 ps
CPU time 0.83 seconds
Started Jun 24 05:39:18 PM PDT 24
Finished Jun 24 05:39:20 PM PDT 24
Peak memory 193260 kb
Host smart-dd2a249b-bda8-4d5b-8826-233e0588cfed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708527441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2708527441
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1799160417
Short name T479
Test name
Test status
Simulation time 177101841 ps
CPU time 0.56 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:39 PM PDT 24
Peak memory 182464 kb
Host smart-dbad3a81-8d3f-4968-a5a8-c4c10cad2dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799160417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1799160417
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2256803543
Short name T472
Test name
Test status
Simulation time 51495100 ps
CPU time 0.55 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:39 PM PDT 24
Peak memory 182176 kb
Host smart-695b4214-efe5-49ac-b396-22f11a577ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256803543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2256803543
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2563070856
Short name T508
Test name
Test status
Simulation time 57930547 ps
CPU time 0.54 seconds
Started Jun 24 05:39:33 PM PDT 24
Finished Jun 24 05:39:34 PM PDT 24
Peak memory 182016 kb
Host smart-c64cf0ab-b82d-4bff-8050-fa16b1f82419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563070856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2563070856
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2321931527
Short name T480
Test name
Test status
Simulation time 36727053 ps
CPU time 0.57 seconds
Started Jun 24 05:39:36 PM PDT 24
Finished Jun 24 05:39:38 PM PDT 24
Peak memory 182624 kb
Host smart-a676b049-4565-4984-b1aa-4b1184dc7f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321931527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2321931527
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.670170752
Short name T497
Test name
Test status
Simulation time 14648991 ps
CPU time 0.57 seconds
Started Jun 24 05:39:35 PM PDT 24
Finished Jun 24 05:39:36 PM PDT 24
Peak memory 182632 kb
Host smart-0a2317a7-4a45-440a-accc-59d1982df02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670170752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.670170752
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.146457885
Short name T506
Test name
Test status
Simulation time 18540256 ps
CPU time 0.58 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:39 PM PDT 24
Peak memory 182628 kb
Host smart-8e50da1c-b2d8-4e74-8917-ef8dbefdf66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146457885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.146457885
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2291496784
Short name T454
Test name
Test status
Simulation time 33095643 ps
CPU time 0.55 seconds
Started Jun 24 05:39:31 PM PDT 24
Finished Jun 24 05:39:33 PM PDT 24
Peak memory 182520 kb
Host smart-1895e2ae-3c80-459b-974e-85571244fa01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291496784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2291496784
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3020636736
Short name T451
Test name
Test status
Simulation time 16877270 ps
CPU time 0.55 seconds
Started Jun 24 05:39:32 PM PDT 24
Finished Jun 24 05:39:34 PM PDT 24
Peak memory 182508 kb
Host smart-97b15972-27fa-46e4-95f4-d366e8a57630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020636736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3020636736
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3925908473
Short name T554
Test name
Test status
Simulation time 51224715 ps
CPU time 0.55 seconds
Started Jun 24 05:39:41 PM PDT 24
Finished Jun 24 05:39:43 PM PDT 24
Peak memory 182236 kb
Host smart-21ea1e42-567e-42e6-9ad2-741cc34d6792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925908473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3925908473
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.443532527
Short name T527
Test name
Test status
Simulation time 35085701 ps
CPU time 0.53 seconds
Started Jun 24 05:39:34 PM PDT 24
Finished Jun 24 05:39:36 PM PDT 24
Peak memory 182200 kb
Host smart-2ad974d1-2ec8-4fbc-bb60-b81bb0175d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443532527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.443532527
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3460245857
Short name T84
Test name
Test status
Simulation time 251712323 ps
CPU time 0.73 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 182692 kb
Host smart-d9e37892-6726-44f9-8234-90a4cac4df22
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460245857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3460245857
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.188698812
Short name T484
Test name
Test status
Simulation time 416625458 ps
CPU time 3.89 seconds
Started Jun 24 05:39:12 PM PDT 24
Finished Jun 24 05:39:17 PM PDT 24
Peak memory 182868 kb
Host smart-42b10f4a-16b7-467b-a4af-ca485d450d3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188698812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.188698812
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1729339825
Short name T490
Test name
Test status
Simulation time 17913765 ps
CPU time 0.6 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:17 PM PDT 24
Peak memory 182620 kb
Host smart-c27249ce-e843-4acc-b0f2-47ebfe0b0fb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729339825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1729339825
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.434453922
Short name T571
Test name
Test status
Simulation time 95525889 ps
CPU time 1 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 197388 kb
Host smart-45448766-2716-4930-bfea-a0a4693cb79d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434453922 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.434453922
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2081703880
Short name T576
Test name
Test status
Simulation time 14966718 ps
CPU time 0.6 seconds
Started Jun 24 05:39:12 PM PDT 24
Finished Jun 24 05:39:15 PM PDT 24
Peak memory 182680 kb
Host smart-c8931cf0-553b-4cc2-bc06-3efcfc7610b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081703880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2081703880
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1818418975
Short name T516
Test name
Test status
Simulation time 56743682 ps
CPU time 0.56 seconds
Started Jun 24 05:39:14 PM PDT 24
Finished Jun 24 05:39:17 PM PDT 24
Peak memory 182332 kb
Host smart-c097947c-4d9a-4781-865c-ec9c1027b35d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818418975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1818418975
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3995754162
Short name T79
Test name
Test status
Simulation time 132141212 ps
CPU time 0.74 seconds
Started Jun 24 05:39:28 PM PDT 24
Finished Jun 24 05:39:31 PM PDT 24
Peak memory 193336 kb
Host smart-da0f0d84-23fb-4594-b677-bf88e68fdfe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995754162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3995754162
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3437890498
Short name T482
Test name
Test status
Simulation time 297884945 ps
CPU time 1.8 seconds
Started Jun 24 05:39:10 PM PDT 24
Finished Jun 24 05:39:12 PM PDT 24
Peak memory 197572 kb
Host smart-78d183ce-2287-4898-a8ac-8ac36af56e35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437890498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3437890498
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.376990111
Short name T512
Test name
Test status
Simulation time 115540751 ps
CPU time 0.84 seconds
Started Jun 24 05:39:16 PM PDT 24
Finished Jun 24 05:39:18 PM PDT 24
Peak memory 193492 kb
Host smart-f105ac2b-575e-49a4-8ddd-6a6ef1ac6af3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376990111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.376990111
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2494615434
Short name T461
Test name
Test status
Simulation time 57299165 ps
CPU time 0.56 seconds
Started Jun 24 05:39:32 PM PDT 24
Finished Jun 24 05:39:33 PM PDT 24
Peak memory 182576 kb
Host smart-5c759b53-b659-4d3d-995e-98dd69bcb2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494615434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2494615434
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3673650245
Short name T503
Test name
Test status
Simulation time 14570879 ps
CPU time 0.55 seconds
Started Jun 24 05:39:32 PM PDT 24
Finished Jun 24 05:39:33 PM PDT 24
Peak memory 182488 kb
Host smart-06bcee85-28ba-43ff-95dd-2cab25f7e657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673650245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3673650245
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2562006131
Short name T509
Test name
Test status
Simulation time 14461484 ps
CPU time 0.54 seconds
Started Jun 24 05:39:36 PM PDT 24
Finished Jun 24 05:39:37 PM PDT 24
Peak memory 182052 kb
Host smart-60703964-1815-4c25-9365-d1b3512daf17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562006131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2562006131
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3351636651
Short name T477
Test name
Test status
Simulation time 18991999 ps
CPU time 0.56 seconds
Started Jun 24 05:39:37 PM PDT 24
Finished Jun 24 05:39:38 PM PDT 24
Peak memory 182584 kb
Host smart-0569a172-bebd-48b0-8687-fa9ecfd207c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351636651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3351636651
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1816815467
Short name T544
Test name
Test status
Simulation time 24977825 ps
CPU time 0.54 seconds
Started Jun 24 05:39:41 PM PDT 24
Finished Jun 24 05:39:43 PM PDT 24
Peak memory 182040 kb
Host smart-67517569-657e-4923-a0d2-06813d393d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816815467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1816815467
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3156380272
Short name T564
Test name
Test status
Simulation time 62707400 ps
CPU time 0.55 seconds
Started Jun 24 05:39:44 PM PDT 24
Finished Jun 24 05:39:45 PM PDT 24
Peak memory 182592 kb
Host smart-1d9dbac0-69fe-435d-884a-b8c09f75b90f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156380272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3156380272
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.922362445
Short name T502
Test name
Test status
Simulation time 34191612 ps
CPU time 0.53 seconds
Started Jun 24 05:39:40 PM PDT 24
Finished Jun 24 05:39:42 PM PDT 24
Peak memory 182016 kb
Host smart-d007eb06-890f-4798-afb0-09f455953d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922362445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.922362445
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1332174308
Short name T575
Test name
Test status
Simulation time 17548729 ps
CPU time 0.54 seconds
Started Jun 24 05:39:39 PM PDT 24
Finished Jun 24 05:39:41 PM PDT 24
Peak memory 182520 kb
Host smart-2d8f8b6b-814f-4176-85ab-e0c21bbe240c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332174308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1332174308
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3631724072
Short name T499
Test name
Test status
Simulation time 15388326 ps
CPU time 0.57 seconds
Started Jun 24 05:39:41 PM PDT 24
Finished Jun 24 05:39:43 PM PDT 24
Peak memory 182840 kb
Host smart-01ad3d7b-45c6-4708-9635-bfe26cd52a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631724072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3631724072
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3171608697
Short name T455
Test name
Test status
Simulation time 19652500 ps
CPU time 0.58 seconds
Started Jun 24 05:39:39 PM PDT 24
Finished Jun 24 05:39:40 PM PDT 24
Peak memory 182608 kb
Host smart-87378ea3-ba47-4b33-9ce9-6b16cb558f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171608697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3171608697
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.29712501
Short name T85
Test name
Test status
Simulation time 30959028 ps
CPU time 0.74 seconds
Started Jun 24 05:39:21 PM PDT 24
Finished Jun 24 05:39:23 PM PDT 24
Peak memory 182692 kb
Host smart-8d6c2aac-b415-4698-bf6d-7df5adc9e734
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29712501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasi
ng.29712501
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3535012818
Short name T34
Test name
Test status
Simulation time 420253793 ps
CPU time 3.9 seconds
Started Jun 24 05:39:23 PM PDT 24
Finished Jun 24 05:39:28 PM PDT 24
Peak memory 192508 kb
Host smart-a1e4c4f2-26b2-41ed-bc09-16d00209e1b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535012818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3535012818
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3819355268
Short name T83
Test name
Test status
Simulation time 17992838 ps
CPU time 0.66 seconds
Started Jun 24 05:39:22 PM PDT 24
Finished Jun 24 05:39:24 PM PDT 24
Peak memory 182676 kb
Host smart-4c8ce643-2389-47b7-bcd3-599680e99f2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819355268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3819355268
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1809503144
Short name T529
Test name
Test status
Simulation time 23945096 ps
CPU time 1.09 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:31 PM PDT 24
Peak memory 197504 kb
Host smart-ba272e9e-03f9-4396-9f1c-78483b321d65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809503144 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1809503144
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2154822104
Short name T504
Test name
Test status
Simulation time 15480532 ps
CPU time 0.6 seconds
Started Jun 24 05:39:22 PM PDT 24
Finished Jun 24 05:39:23 PM PDT 24
Peak memory 182400 kb
Host smart-db3a9d37-34a2-4499-a869-b983be928e12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154822104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2154822104
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1331981950
Short name T520
Test name
Test status
Simulation time 20782951 ps
CPU time 0.55 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 182052 kb
Host smart-b09719cd-f0f1-44af-9b9c-90f68300dfb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331981950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1331981950
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1668158880
Short name T536
Test name
Test status
Simulation time 24465282 ps
CPU time 0.72 seconds
Started Jun 24 05:39:28 PM PDT 24
Finished Jun 24 05:39:31 PM PDT 24
Peak memory 192044 kb
Host smart-b9974e13-e7ae-41e5-b36d-0f883a2c8fc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668158880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1668158880
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1987772308
Short name T483
Test name
Test status
Simulation time 268948699 ps
CPU time 2.33 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:31 PM PDT 24
Peak memory 197568 kb
Host smart-a7933f8a-57c2-441f-8314-81a8c86d85a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987772308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1987772308
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4289422964
Short name T501
Test name
Test status
Simulation time 136386734 ps
CPU time 1.43 seconds
Started Jun 24 05:39:23 PM PDT 24
Finished Jun 24 05:39:26 PM PDT 24
Peak memory 195312 kb
Host smart-548a9d16-1515-4969-8456-8c62bda0f425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289422964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4289422964
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2575794333
Short name T457
Test name
Test status
Simulation time 87998482 ps
CPU time 0.55 seconds
Started Jun 24 05:39:43 PM PDT 24
Finished Jun 24 05:39:45 PM PDT 24
Peak memory 182592 kb
Host smart-ee6a4936-03a8-4ace-930c-82788e741ada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575794333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2575794333
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2866597295
Short name T471
Test name
Test status
Simulation time 13159545 ps
CPU time 0.56 seconds
Started Jun 24 05:39:42 PM PDT 24
Finished Jun 24 05:39:44 PM PDT 24
Peak memory 182552 kb
Host smart-957f34cf-7e8c-44b3-acb0-1d29013b8944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866597295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2866597295
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.414831456
Short name T467
Test name
Test status
Simulation time 59649060 ps
CPU time 0.56 seconds
Started Jun 24 05:39:44 PM PDT 24
Finished Jun 24 05:39:45 PM PDT 24
Peak memory 182632 kb
Host smart-4fc5f0ed-4625-42eb-9bd2-9c330b1a2bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414831456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.414831456
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3185937754
Short name T452
Test name
Test status
Simulation time 46414877 ps
CPU time 0.53 seconds
Started Jun 24 05:39:42 PM PDT 24
Finished Jun 24 05:39:44 PM PDT 24
Peak memory 182048 kb
Host smart-24d813da-90f4-4545-9482-26ba1a682b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185937754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3185937754
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2080546931
Short name T500
Test name
Test status
Simulation time 42289566 ps
CPU time 0.54 seconds
Started Jun 24 05:39:43 PM PDT 24
Finished Jun 24 05:39:44 PM PDT 24
Peak memory 182060 kb
Host smart-b55599a2-d990-443f-b7bd-63ad9c7c9931
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080546931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2080546931
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.944447508
Short name T543
Test name
Test status
Simulation time 17070773 ps
CPU time 0.51 seconds
Started Jun 24 05:39:43 PM PDT 24
Finished Jun 24 05:39:44 PM PDT 24
Peak memory 182236 kb
Host smart-f365abaa-ca34-45cc-bf64-54ca276292d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944447508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.944447508
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2168908237
Short name T552
Test name
Test status
Simulation time 17136034 ps
CPU time 0.59 seconds
Started Jun 24 05:39:40 PM PDT 24
Finished Jun 24 05:39:42 PM PDT 24
Peak memory 182552 kb
Host smart-7b9d672c-6144-4192-9ba7-88da239bda7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168908237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2168908237
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.773222363
Short name T449
Test name
Test status
Simulation time 13260066 ps
CPU time 0.58 seconds
Started Jun 24 05:39:42 PM PDT 24
Finished Jun 24 05:39:44 PM PDT 24
Peak memory 182524 kb
Host smart-c3b2da56-6bd0-4c55-9015-2bae99bfd73d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773222363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.773222363
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.687612025
Short name T491
Test name
Test status
Simulation time 13370114 ps
CPU time 0.54 seconds
Started Jun 24 05:39:39 PM PDT 24
Finished Jun 24 05:39:41 PM PDT 24
Peak memory 182056 kb
Host smart-2cd7c0b8-95c7-4bcb-92e6-57b3d7005341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687612025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.687612025
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4073076478
Short name T524
Test name
Test status
Simulation time 42376556 ps
CPU time 0.54 seconds
Started Jun 24 05:39:40 PM PDT 24
Finished Jun 24 05:39:42 PM PDT 24
Peak memory 182232 kb
Host smart-a7c4e514-76d4-426b-8abe-01b3c277f162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073076478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4073076478
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.337624377
Short name T66
Test name
Test status
Simulation time 18292288 ps
CPU time 0.63 seconds
Started Jun 24 05:39:21 PM PDT 24
Finished Jun 24 05:39:23 PM PDT 24
Peak memory 193680 kb
Host smart-0744c7f9-a136-47ab-b244-4ac2e2c6070d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337624377 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.337624377
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3459680484
Short name T78
Test name
Test status
Simulation time 49067878 ps
CPU time 0.59 seconds
Started Jun 24 05:39:22 PM PDT 24
Finished Jun 24 05:39:24 PM PDT 24
Peak memory 182668 kb
Host smart-a625be64-c9bb-445d-8e25-e17164c56210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459680484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3459680484
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2203807632
Short name T453
Test name
Test status
Simulation time 16476299 ps
CPU time 0.58 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:30 PM PDT 24
Peak memory 182568 kb
Host smart-c36bbeb8-f893-4535-92f8-f6826cea6bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203807632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2203807632
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2178876509
Short name T538
Test name
Test status
Simulation time 28745106 ps
CPU time 0.73 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:30 PM PDT 24
Peak memory 193256 kb
Host smart-659d2794-5416-428d-ba99-12287e289b75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178876509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2178876509
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3957619771
Short name T473
Test name
Test status
Simulation time 61748303 ps
CPU time 0.98 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:31 PM PDT 24
Peak memory 197316 kb
Host smart-5b12ef3f-ba2a-4ab3-a043-ae345f2ab5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957619771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3957619771
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1752810313
Short name T32
Test name
Test status
Simulation time 165826438 ps
CPU time 0.86 seconds
Started Jun 24 05:39:23 PM PDT 24
Finished Jun 24 05:39:25 PM PDT 24
Peak memory 193820 kb
Host smart-7c49f470-9eee-4046-a347-8e7cca2e2e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752810313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1752810313
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3060246336
Short name T57
Test name
Test status
Simulation time 63391024 ps
CPU time 0.61 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 193416 kb
Host smart-7ecfe6c2-195b-48b7-bda2-49014bf3673f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060246336 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3060246336
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3970947628
Short name T496
Test name
Test status
Simulation time 25761748 ps
CPU time 0.63 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:30 PM PDT 24
Peak memory 182616 kb
Host smart-59f552cc-2e64-4063-aada-df2f04eee175
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970947628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3970947628
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1371787481
Short name T486
Test name
Test status
Simulation time 44661056 ps
CPU time 0.55 seconds
Started Jun 24 05:39:23 PM PDT 24
Finished Jun 24 05:39:25 PM PDT 24
Peak memory 182008 kb
Host smart-3ddb9494-65b7-4137-aa96-4ac051f09003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371787481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1371787481
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2815378107
Short name T94
Test name
Test status
Simulation time 31204254 ps
CPU time 0.73 seconds
Started Jun 24 05:39:24 PM PDT 24
Finished Jun 24 05:39:26 PM PDT 24
Peak memory 191712 kb
Host smart-6dddd9c0-1c6b-4a49-bcbb-8d716e34333b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815378107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2815378107
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.385064733
Short name T485
Test name
Test status
Simulation time 319242610 ps
CPU time 2.77 seconds
Started Jun 24 05:39:21 PM PDT 24
Finished Jun 24 05:39:25 PM PDT 24
Peak memory 197524 kb
Host smart-7340ad2b-7faa-4f1e-8ed9-7cef6ad43d63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385064733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.385064733
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1545055553
Short name T31
Test name
Test status
Simulation time 50660998 ps
CPU time 0.84 seconds
Started Jun 24 05:39:28 PM PDT 24
Finished Jun 24 05:39:31 PM PDT 24
Peak memory 192688 kb
Host smart-b53e3728-cf8a-4c0c-9b13-643ada019c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545055553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1545055553
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3724852155
Short name T549
Test name
Test status
Simulation time 126464190 ps
CPU time 0.97 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 197388 kb
Host smart-62d260cd-1266-487f-a4fe-06ec895427c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724852155 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3724852155
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3413957525
Short name T569
Test name
Test status
Simulation time 22387955 ps
CPU time 0.55 seconds
Started Jun 24 05:39:25 PM PDT 24
Finished Jun 24 05:39:27 PM PDT 24
Peak memory 182692 kb
Host smart-2e502e84-2a33-4d0b-a404-9a702f4bc885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413957525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3413957525
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.837141372
Short name T458
Test name
Test status
Simulation time 17310410 ps
CPU time 0.61 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 182620 kb
Host smart-9b7bf272-a322-48b6-b374-f463df260f64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837141372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.837141372
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1255136387
Short name T88
Test name
Test status
Simulation time 48765363 ps
CPU time 0.74 seconds
Started Jun 24 05:39:30 PM PDT 24
Finished Jun 24 05:39:32 PM PDT 24
Peak memory 192224 kb
Host smart-4d85e379-c64f-4e58-bb86-a61495133e37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255136387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1255136387
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3511753594
Short name T531
Test name
Test status
Simulation time 206297970 ps
CPU time 1.81 seconds
Started Jun 24 05:39:21 PM PDT 24
Finished Jun 24 05:39:23 PM PDT 24
Peak memory 197488 kb
Host smart-b4a31e40-2dbc-418e-8cc2-eccab6fa0ad0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511753594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3511753594
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1287115125
Short name T523
Test name
Test status
Simulation time 74660125 ps
CPU time 0.76 seconds
Started Jun 24 05:39:24 PM PDT 24
Finished Jun 24 05:39:27 PM PDT 24
Peak memory 195364 kb
Host smart-99d1638b-153d-40ff-8cf4-71e6aa547090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287115125 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1287115125
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3846841250
Short name T82
Test name
Test status
Simulation time 49479562 ps
CPU time 0.56 seconds
Started Jun 24 05:39:24 PM PDT 24
Finished Jun 24 05:39:26 PM PDT 24
Peak memory 182680 kb
Host smart-6e125073-a2a4-41c5-ab3d-3c3cfd53a426
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846841250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3846841250
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3176913968
Short name T519
Test name
Test status
Simulation time 17130561 ps
CPU time 0.51 seconds
Started Jun 24 05:39:23 PM PDT 24
Finished Jun 24 05:39:25 PM PDT 24
Peak memory 182172 kb
Host smart-b11bf90a-bea2-4307-874a-58ca354929f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176913968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3176913968
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1469803182
Short name T534
Test name
Test status
Simulation time 31984296 ps
CPU time 0.81 seconds
Started Jun 24 05:39:25 PM PDT 24
Finished Jun 24 05:39:28 PM PDT 24
Peak memory 193436 kb
Host smart-472dcda3-f5dd-41db-88d8-55340823120d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469803182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1469803182
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2244421231
Short name T530
Test name
Test status
Simulation time 109691623 ps
CPU time 1.78 seconds
Started Jun 24 05:39:24 PM PDT 24
Finished Jun 24 05:39:27 PM PDT 24
Peak memory 191188 kb
Host smart-abe78371-23b7-496a-8ae3-79fd5dba886b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244421231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2244421231
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.395145849
Short name T465
Test name
Test status
Simulation time 78285496 ps
CPU time 0.84 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:30 PM PDT 24
Peak memory 193804 kb
Host smart-3cf1e2cd-67a3-4080-b80d-8dce3426a2c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395145849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.395145849
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2026857183
Short name T565
Test name
Test status
Simulation time 32968772 ps
CPU time 0.62 seconds
Started Jun 24 05:39:25 PM PDT 24
Finished Jun 24 05:39:27 PM PDT 24
Peak memory 193224 kb
Host smart-ddf5c5bb-2c37-404d-ae9b-473cd8584d54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026857183 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2026857183
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1797498130
Short name T97
Test name
Test status
Simulation time 16437282 ps
CPU time 0.58 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:30 PM PDT 24
Peak memory 182904 kb
Host smart-82d7ca06-ffb1-4f5e-af7e-e6ab3bcfb274
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797498130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1797498130
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.875786695
Short name T478
Test name
Test status
Simulation time 13051647 ps
CPU time 0.54 seconds
Started Jun 24 05:39:22 PM PDT 24
Finished Jun 24 05:39:24 PM PDT 24
Peak memory 182244 kb
Host smart-6935d423-a344-47e7-a924-84b807a39b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875786695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.875786695
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1645216506
Short name T93
Test name
Test status
Simulation time 99870780 ps
CPU time 0.85 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 193300 kb
Host smart-d6894222-8d47-40f3-943a-69608f232729
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645216506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1645216506
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4174938848
Short name T505
Test name
Test status
Simulation time 151102415 ps
CPU time 2.57 seconds
Started Jun 24 05:39:27 PM PDT 24
Finished Jun 24 05:39:32 PM PDT 24
Peak memory 197568 kb
Host smart-e0b565bf-00c6-4173-8e0a-61fc5b7414bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174938848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4174938848
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2273982455
Short name T99
Test name
Test status
Simulation time 209583961 ps
CPU time 1.32 seconds
Started Jun 24 05:39:26 PM PDT 24
Finished Jun 24 05:39:29 PM PDT 24
Peak memory 183272 kb
Host smart-ae62e23e-5bc3-40cd-b273-825792d446ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273982455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2273982455
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2566514939
Short name T344
Test name
Test status
Simulation time 91261336571 ps
CPU time 163.39 seconds
Started Jun 24 06:20:13 PM PDT 24
Finished Jun 24 06:22:57 PM PDT 24
Peak memory 182988 kb
Host smart-7436664e-d738-4a95-bc77-06743e4afc94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566514939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2566514939
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1614469601
Short name T363
Test name
Test status
Simulation time 299721059595 ps
CPU time 96.15 seconds
Started Jun 24 06:20:15 PM PDT 24
Finished Jun 24 06:21:52 PM PDT 24
Peak memory 182992 kb
Host smart-71456e6b-8a63-4840-be26-741f2987b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614469601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1614469601
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3371294540
Short name T139
Test name
Test status
Simulation time 788290381 ps
CPU time 10.35 seconds
Started Jun 24 06:20:24 PM PDT 24
Finished Jun 24 06:20:35 PM PDT 24
Peak memory 182936 kb
Host smart-4683fa8c-c43a-42d1-b37e-77b4794e01ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371294540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3371294540
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1970955761
Short name T359
Test name
Test status
Simulation time 427855831566 ps
CPU time 151.5 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:22:54 PM PDT 24
Peak memory 183004 kb
Host smart-5062c6c3-9dcf-4273-98ed-0bc48f3d07ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970955761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1970955761
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3125461358
Short name T332
Test name
Test status
Simulation time 61618590627 ps
CPU time 134.63 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:22:37 PM PDT 24
Peak memory 194708 kb
Host smart-96a26354-1a0f-49b3-9f36-e085d05d1d4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125461358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3125461358
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3311106050
Short name T18
Test name
Test status
Simulation time 314020901 ps
CPU time 0.87 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:20:24 PM PDT 24
Peak memory 213848 kb
Host smart-f24432f3-6b5a-42bf-bd4a-d064edfd6894
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311106050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3311106050
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2119487394
Short name T138
Test name
Test status
Simulation time 416169523432 ps
CPU time 1487.26 seconds
Started Jun 24 06:20:24 PM PDT 24
Finished Jun 24 06:45:12 PM PDT 24
Peak memory 191180 kb
Host smart-72a91d74-5122-4765-9a39-0bb780d5b57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119487394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2119487394
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1427875607
Short name T396
Test name
Test status
Simulation time 235754794390 ps
CPU time 142.24 seconds
Started Jun 24 06:20:48 PM PDT 24
Finished Jun 24 06:23:10 PM PDT 24
Peak memory 182980 kb
Host smart-de9ebcc0-2f00-4c31-ba36-79693100300b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427875607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1427875607
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.916503799
Short name T389
Test name
Test status
Simulation time 47669220833 ps
CPU time 31.35 seconds
Started Jun 24 06:20:48 PM PDT 24
Finished Jun 24 06:21:20 PM PDT 24
Peak memory 182992 kb
Host smart-8b6a28f6-2592-4263-be16-1827c59e0b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916503799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.916503799
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3792567809
Short name T308
Test name
Test status
Simulation time 175793987135 ps
CPU time 176.76 seconds
Started Jun 24 06:20:50 PM PDT 24
Finished Jun 24 06:23:47 PM PDT 24
Peak memory 191188 kb
Host smart-94d73140-98a2-47aa-8dd6-2b55beb7c204
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792567809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3792567809
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1516980789
Short name T61
Test name
Test status
Simulation time 167467370 ps
CPU time 0.83 seconds
Started Jun 24 06:20:48 PM PDT 24
Finished Jun 24 06:20:49 PM PDT 24
Peak memory 182752 kb
Host smart-a7c01367-8601-4df1-be6a-b0c3c83ee7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516980789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1516980789
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1500303963
Short name T390
Test name
Test status
Simulation time 260989593163 ps
CPU time 140.98 seconds
Started Jun 24 06:20:49 PM PDT 24
Finished Jun 24 06:23:11 PM PDT 24
Peak memory 182968 kb
Host smart-55cb4700-8bcd-4ca2-b56c-bb2f4c7d6148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500303963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1500303963
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1650717653
Short name T38
Test name
Test status
Simulation time 41838632941 ps
CPU time 169.19 seconds
Started Jun 24 06:20:47 PM PDT 24
Finished Jun 24 06:23:37 PM PDT 24
Peak memory 197684 kb
Host smart-3baf2986-6feb-41ff-ae74-753296402a78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650717653 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1650717653
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1388791316
Short name T149
Test name
Test status
Simulation time 25504316569 ps
CPU time 39.74 seconds
Started Jun 24 06:25:08 PM PDT 24
Finished Jun 24 06:25:48 PM PDT 24
Peak memory 191172 kb
Host smart-ebf38058-82f8-4a70-87fc-24465b75d556
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388791316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1388791316
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1769115281
Short name T210
Test name
Test status
Simulation time 167851794986 ps
CPU time 1617.72 seconds
Started Jun 24 06:25:09 PM PDT 24
Finished Jun 24 06:52:07 PM PDT 24
Peak memory 194408 kb
Host smart-44e0e336-c537-4c01-9a82-c1be919d14af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769115281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1769115281
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1604330820
Short name T424
Test name
Test status
Simulation time 64722572107 ps
CPU time 66.5 seconds
Started Jun 24 06:25:09 PM PDT 24
Finished Jun 24 06:26:16 PM PDT 24
Peak memory 183012 kb
Host smart-59c1b01b-0ec8-4881-b86b-7adf5b060fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604330820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1604330820
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1145041252
Short name T339
Test name
Test status
Simulation time 83396216667 ps
CPU time 320.9 seconds
Started Jun 24 06:25:17 PM PDT 24
Finished Jun 24 06:30:39 PM PDT 24
Peak memory 191192 kb
Host smart-1330aaf3-171e-4a27-9e61-84a060c23ae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145041252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1145041252
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.952329456
Short name T169
Test name
Test status
Simulation time 169969896908 ps
CPU time 35.45 seconds
Started Jun 24 06:25:17 PM PDT 24
Finished Jun 24 06:25:53 PM PDT 24
Peak memory 191184 kb
Host smart-654fd2f1-6890-45fa-9777-4b2b302460a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952329456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.952329456
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.970218353
Short name T178
Test name
Test status
Simulation time 40755275127 ps
CPU time 178.81 seconds
Started Jun 24 06:25:19 PM PDT 24
Finished Jun 24 06:28:18 PM PDT 24
Peak memory 191164 kb
Host smart-5a531fa4-cff4-4a4e-a1ad-82adef696183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970218353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.970218353
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.4167511162
Short name T307
Test name
Test status
Simulation time 1050903173291 ps
CPU time 206.58 seconds
Started Jun 24 06:25:19 PM PDT 24
Finished Jun 24 06:28:47 PM PDT 24
Peak memory 191164 kb
Host smart-2afea52a-afa9-4587-80ab-8d27d4d85259
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167511162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.4167511162
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.248890523
Short name T345
Test name
Test status
Simulation time 83321504757 ps
CPU time 134.4 seconds
Started Jun 24 06:20:53 PM PDT 24
Finished Jun 24 06:23:08 PM PDT 24
Peak memory 182952 kb
Host smart-7e7e257f-762c-4048-b5d5-20cc37d282e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248890523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.248890523
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3480849957
Short name T48
Test name
Test status
Simulation time 31690578723 ps
CPU time 47.25 seconds
Started Jun 24 06:20:48 PM PDT 24
Finished Jun 24 06:21:36 PM PDT 24
Peak memory 182936 kb
Host smart-0031c2e8-59cc-41c4-a697-1e9cc273a945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480849957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3480849957
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2111332052
Short name T62
Test name
Test status
Simulation time 27756687687 ps
CPU time 42.22 seconds
Started Jun 24 06:20:48 PM PDT 24
Finished Jun 24 06:21:31 PM PDT 24
Peak memory 182980 kb
Host smart-7eb34468-02e2-408a-b0e0-db7690788640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111332052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2111332052
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.416900618
Short name T287
Test name
Test status
Simulation time 48947085713 ps
CPU time 80 seconds
Started Jun 24 06:20:49 PM PDT 24
Finished Jun 24 06:22:10 PM PDT 24
Peak memory 182992 kb
Host smart-7e5920c6-8a4f-47b0-9440-73a328a78edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416900618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.416900618
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2851284402
Short name T420
Test name
Test status
Simulation time 408165706433 ps
CPU time 51.02 seconds
Started Jun 24 06:20:51 PM PDT 24
Finished Jun 24 06:21:43 PM PDT 24
Peak memory 182952 kb
Host smart-10c82675-1995-439e-b62c-e1feb469c8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851284402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2851284402
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.711183701
Short name T267
Test name
Test status
Simulation time 10047017717 ps
CPU time 16.75 seconds
Started Jun 24 06:25:43 PM PDT 24
Finished Jun 24 06:26:01 PM PDT 24
Peak memory 182976 kb
Host smart-ee78a0cb-4b9c-441f-a118-621c845cf747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711183701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.711183701
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2298421140
Short name T330
Test name
Test status
Simulation time 62326005474 ps
CPU time 30.92 seconds
Started Jun 24 06:25:27 PM PDT 24
Finished Jun 24 06:25:58 PM PDT 24
Peak memory 182988 kb
Host smart-f11fd74b-c1a6-46ac-9d90-175af1df8007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298421140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2298421140
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.730104278
Short name T422
Test name
Test status
Simulation time 150594059372 ps
CPU time 437.25 seconds
Started Jun 24 06:25:26 PM PDT 24
Finished Jun 24 06:32:43 PM PDT 24
Peak memory 182932 kb
Host smart-fbe4348e-7e52-4855-b782-ac3706c33626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730104278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.730104278
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3285238512
Short name T342
Test name
Test status
Simulation time 630339513386 ps
CPU time 334.07 seconds
Started Jun 24 06:20:53 PM PDT 24
Finished Jun 24 06:26:28 PM PDT 24
Peak memory 182948 kb
Host smart-5edb6677-3991-47c9-b8e9-cc425cbc2471
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285238512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3285238512
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3397838273
Short name T381
Test name
Test status
Simulation time 358506792502 ps
CPU time 157.82 seconds
Started Jun 24 06:20:52 PM PDT 24
Finished Jun 24 06:23:30 PM PDT 24
Peak memory 182960 kb
Host smart-41e04c47-7749-4fa5-972b-0e94cd4ea26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397838273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3397838273
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1817055782
Short name T322
Test name
Test status
Simulation time 161453072360 ps
CPU time 69.56 seconds
Started Jun 24 06:20:48 PM PDT 24
Finished Jun 24 06:21:58 PM PDT 24
Peak memory 182988 kb
Host smart-a41c49bd-b6a3-4bf2-86e8-4ed396b57d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817055782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1817055782
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.874970589
Short name T388
Test name
Test status
Simulation time 54653426978 ps
CPU time 62.03 seconds
Started Jun 24 06:20:53 PM PDT 24
Finished Jun 24 06:21:55 PM PDT 24
Peak memory 191164 kb
Host smart-82f50be7-f3b5-497c-b505-00d63b632a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874970589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.874970589
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2634429974
Short name T132
Test name
Test status
Simulation time 964615168847 ps
CPU time 381.19 seconds
Started Jun 24 06:20:55 PM PDT 24
Finished Jun 24 06:27:17 PM PDT 24
Peak memory 182988 kb
Host smart-287b874a-44c6-4a2c-bb99-fe97da9d10be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634429974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2634429974
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.826645425
Short name T306
Test name
Test status
Simulation time 39544715240 ps
CPU time 38.93 seconds
Started Jun 24 06:25:26 PM PDT 24
Finished Jun 24 06:26:06 PM PDT 24
Peak memory 183024 kb
Host smart-839b1138-996d-48ec-94e8-11097646d2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826645425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.826645425
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1218543453
Short name T426
Test name
Test status
Simulation time 9685621780 ps
CPU time 8.87 seconds
Started Jun 24 06:25:34 PM PDT 24
Finished Jun 24 06:25:43 PM PDT 24
Peak memory 191180 kb
Host smart-f38cecdf-acd7-4ce8-8b19-22d467490f8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218543453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1218543453
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.668009150
Short name T4
Test name
Test status
Simulation time 283364759912 ps
CPU time 131.61 seconds
Started Jun 24 06:25:37 PM PDT 24
Finished Jun 24 06:27:49 PM PDT 24
Peak memory 194456 kb
Host smart-27769945-d9ed-484c-86f9-e2519bba446e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668009150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.668009150
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4074867238
Short name T2
Test name
Test status
Simulation time 461306395820 ps
CPU time 708.88 seconds
Started Jun 24 06:25:36 PM PDT 24
Finished Jun 24 06:37:25 PM PDT 24
Peak memory 191172 kb
Host smart-ccee6366-729d-4dfd-9a3c-557e245735df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074867238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4074867238
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2104509841
Short name T224
Test name
Test status
Simulation time 79200472474 ps
CPU time 128.05 seconds
Started Jun 24 06:25:35 PM PDT 24
Finished Jun 24 06:27:43 PM PDT 24
Peak memory 195076 kb
Host smart-73a0fd03-29e9-409c-85cf-4f2fa1c4daf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104509841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2104509841
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1863852999
Short name T241
Test name
Test status
Simulation time 822049641990 ps
CPU time 345.5 seconds
Started Jun 24 06:25:33 PM PDT 24
Finished Jun 24 06:31:19 PM PDT 24
Peak memory 191204 kb
Host smart-89fc726d-5505-4d54-88c2-8f0f8aa703d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863852999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1863852999
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.251775648
Short name T100
Test name
Test status
Simulation time 673509497194 ps
CPU time 625.11 seconds
Started Jun 24 06:20:54 PM PDT 24
Finished Jun 24 06:31:19 PM PDT 24
Peak memory 182972 kb
Host smart-9d039efe-c086-4c4a-8915-b33f3459e3fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251775648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.251775648
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3825736485
Short name T27
Test name
Test status
Simulation time 72131569626 ps
CPU time 95.11 seconds
Started Jun 24 06:20:57 PM PDT 24
Finished Jun 24 06:22:33 PM PDT 24
Peak memory 182976 kb
Host smart-a7b5aa19-fcbf-4fda-bd9c-e31d911903ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825736485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3825736485
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.392120615
Short name T251
Test name
Test status
Simulation time 430794995059 ps
CPU time 388.02 seconds
Started Jun 24 06:20:57 PM PDT 24
Finished Jun 24 06:27:26 PM PDT 24
Peak memory 190804 kb
Host smart-d4263606-f94f-48c4-a3b1-6fb7b396bc65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392120615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.392120615
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1460406725
Short name T284
Test name
Test status
Simulation time 50002072428 ps
CPU time 77.13 seconds
Started Jun 24 06:20:56 PM PDT 24
Finished Jun 24 06:22:14 PM PDT 24
Peak memory 195040 kb
Host smart-2dd167ba-8479-4b4d-9c93-3801cfa3dcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460406725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1460406725
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2866749466
Short name T254
Test name
Test status
Simulation time 51110049947 ps
CPU time 82.53 seconds
Started Jun 24 06:25:34 PM PDT 24
Finished Jun 24 06:26:57 PM PDT 24
Peak memory 191172 kb
Host smart-a473aef5-eda5-4632-b5f7-31cba6ae8055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866749466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2866749466
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2684025059
Short name T425
Test name
Test status
Simulation time 664964030285 ps
CPU time 343.36 seconds
Started Jun 24 06:25:35 PM PDT 24
Finished Jun 24 06:31:19 PM PDT 24
Peak memory 191176 kb
Host smart-c57dab32-04b2-4cab-81a5-7bc719e91a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684025059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2684025059
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.67337000
Short name T225
Test name
Test status
Simulation time 117100621792 ps
CPU time 410.16 seconds
Started Jun 24 06:25:46 PM PDT 24
Finished Jun 24 06:32:36 PM PDT 24
Peak memory 183004 kb
Host smart-ffa4f9a4-1928-4231-8c3f-9063a2dcc60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67337000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.67337000
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3913325998
Short name T166
Test name
Test status
Simulation time 107436834451 ps
CPU time 1776.95 seconds
Started Jun 24 06:25:41 PM PDT 24
Finished Jun 24 06:55:19 PM PDT 24
Peak memory 191180 kb
Host smart-72e1b7fa-6fd9-4072-b3fe-1f63a26c6d4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913325998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3913325998
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4145974118
Short name T433
Test name
Test status
Simulation time 134970050101 ps
CPU time 63.02 seconds
Started Jun 24 06:25:43 PM PDT 24
Finished Jun 24 06:26:47 PM PDT 24
Peak memory 191172 kb
Host smart-01984b0e-932a-405e-a4b9-f10cc88e6b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145974118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4145974118
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4144139214
Short name T60
Test name
Test status
Simulation time 141210942875 ps
CPU time 71.76 seconds
Started Jun 24 06:25:42 PM PDT 24
Finished Jun 24 06:26:54 PM PDT 24
Peak memory 182932 kb
Host smart-547a8271-f5da-4976-a4d2-cc873033f987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144139214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4144139214
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3532383286
Short name T235
Test name
Test status
Simulation time 48094318969 ps
CPU time 67.12 seconds
Started Jun 24 06:25:50 PM PDT 24
Finished Jun 24 06:26:58 PM PDT 24
Peak memory 182804 kb
Host smart-90f0af1e-52f8-41fc-bd48-bb15885f422f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532383286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3532383286
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3193215699
Short name T411
Test name
Test status
Simulation time 46321458529 ps
CPU time 73.23 seconds
Started Jun 24 06:20:55 PM PDT 24
Finished Jun 24 06:22:09 PM PDT 24
Peak memory 183000 kb
Host smart-57e7bb57-18b3-4c8c-b52b-e0b8dc6f1c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193215699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3193215699
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3337201059
Short name T22
Test name
Test status
Simulation time 309258875 ps
CPU time 0.65 seconds
Started Jun 24 06:20:57 PM PDT 24
Finished Jun 24 06:20:58 PM PDT 24
Peak memory 182740 kb
Host smart-5c5df5f1-9241-442b-8536-7ff9e208e407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337201059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3337201059
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2969600006
Short name T119
Test name
Test status
Simulation time 292025239212 ps
CPU time 323.23 seconds
Started Jun 24 06:20:59 PM PDT 24
Finished Jun 24 06:26:23 PM PDT 24
Peak memory 191168 kb
Host smart-1e437d44-92b1-4171-bde2-5b7b2bc28992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969600006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2969600006
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.1237554493
Short name T42
Test name
Test status
Simulation time 53919161420 ps
CPU time 214.38 seconds
Started Jun 24 06:20:55 PM PDT 24
Finished Jun 24 06:24:29 PM PDT 24
Peak memory 197692 kb
Host smart-3dcb411f-ec60-41b3-b8aa-89622e74c0ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237554493 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.1237554493
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3047329555
Short name T208
Test name
Test status
Simulation time 63096111921 ps
CPU time 1349.56 seconds
Started Jun 24 06:25:50 PM PDT 24
Finished Jun 24 06:48:20 PM PDT 24
Peak memory 192208 kb
Host smart-a65f5a4a-eac1-4205-8395-e42cabe76921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047329555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3047329555
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3273380415
Short name T255
Test name
Test status
Simulation time 182098354365 ps
CPU time 104.29 seconds
Started Jun 24 06:25:51 PM PDT 24
Finished Jun 24 06:27:36 PM PDT 24
Peak memory 182964 kb
Host smart-d577b8b5-5882-4ae6-8e91-52e4b6bcfb09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273380415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3273380415
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1100045049
Short name T250
Test name
Test status
Simulation time 31739039829 ps
CPU time 185.89 seconds
Started Jun 24 06:25:51 PM PDT 24
Finished Jun 24 06:28:57 PM PDT 24
Peak memory 182960 kb
Host smart-0ab8ef10-d5e4-4cb5-9abb-54f89e502362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100045049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1100045049
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2790402824
Short name T158
Test name
Test status
Simulation time 334222306712 ps
CPU time 65.62 seconds
Started Jun 24 06:26:00 PM PDT 24
Finished Jun 24 06:27:06 PM PDT 24
Peak memory 182984 kb
Host smart-ab3de497-1fd4-48ee-a472-fbb47c853ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790402824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2790402824
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2888984250
Short name T269
Test name
Test status
Simulation time 478216242082 ps
CPU time 220.75 seconds
Started Jun 24 06:25:59 PM PDT 24
Finished Jun 24 06:29:41 PM PDT 24
Peak memory 191196 kb
Host smart-f7f16b42-599c-491d-9d76-c5b7d8856d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888984250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2888984250
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3664810286
Short name T157
Test name
Test status
Simulation time 323986811280 ps
CPU time 312.39 seconds
Started Jun 24 06:26:06 PM PDT 24
Finished Jun 24 06:31:19 PM PDT 24
Peak memory 191212 kb
Host smart-ed271d3a-41cc-48c0-b520-fb660d052645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664810286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3664810286
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2763353882
Short name T263
Test name
Test status
Simulation time 1035524227126 ps
CPU time 2332.79 seconds
Started Jun 24 06:25:59 PM PDT 24
Finished Jun 24 07:04:53 PM PDT 24
Peak memory 191416 kb
Host smart-d2fd9083-6918-44ae-a65b-d9135f2838bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763353882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2763353882
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3221937245
Short name T434
Test name
Test status
Simulation time 23206768406 ps
CPU time 35.76 seconds
Started Jun 24 06:25:58 PM PDT 24
Finished Jun 24 06:26:34 PM PDT 24
Peak memory 182976 kb
Host smart-4105aea2-7756-4dce-8c9f-a40c02ca2b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221937245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3221937245
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.572377697
Short name T413
Test name
Test status
Simulation time 194752022006 ps
CPU time 151.41 seconds
Started Jun 24 06:21:02 PM PDT 24
Finished Jun 24 06:23:34 PM PDT 24
Peak memory 182988 kb
Host smart-53667b28-f07b-4087-ac97-a6d90ecbc9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572377697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.572377697
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3833033864
Short name T302
Test name
Test status
Simulation time 416286729000 ps
CPU time 162.56 seconds
Started Jun 24 06:21:03 PM PDT 24
Finished Jun 24 06:23:46 PM PDT 24
Peak memory 191208 kb
Host smart-525db2a0-b83c-48a0-9d26-9cd23c309e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833033864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3833033864
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.2753281355
Short name T106
Test name
Test status
Simulation time 350683291220 ps
CPU time 2557.26 seconds
Started Jun 24 06:26:06 PM PDT 24
Finished Jun 24 07:08:44 PM PDT 24
Peak memory 191204 kb
Host smart-e048d555-236f-48ae-bf27-e7f8683429b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753281355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2753281355
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3501830990
Short name T258
Test name
Test status
Simulation time 88276433977 ps
CPU time 70.44 seconds
Started Jun 24 06:25:59 PM PDT 24
Finished Jun 24 06:27:10 PM PDT 24
Peak memory 191188 kb
Host smart-83c84c4d-6f45-4e77-99bc-d5006f708361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501830990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3501830990
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2694953329
Short name T163
Test name
Test status
Simulation time 671665280663 ps
CPU time 1153.89 seconds
Started Jun 24 06:25:59 PM PDT 24
Finished Jun 24 06:45:14 PM PDT 24
Peak memory 191156 kb
Host smart-f3a67f8b-dd1f-4ff4-86d5-b57d8f82a98c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694953329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2694953329
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3089713431
Short name T10
Test name
Test status
Simulation time 451515429758 ps
CPU time 790.42 seconds
Started Jun 24 06:26:06 PM PDT 24
Finished Jun 24 06:39:17 PM PDT 24
Peak memory 191204 kb
Host smart-5a612f2d-9dd1-450d-9911-194ecdc6831b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089713431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3089713431
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.340085755
Short name T252
Test name
Test status
Simulation time 96138539257 ps
CPU time 426.92 seconds
Started Jun 24 06:26:09 PM PDT 24
Finished Jun 24 06:33:17 PM PDT 24
Peak memory 191124 kb
Host smart-5bd5e2f9-027e-4b29-853a-03641824caaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340085755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.340085755
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3803679813
Short name T214
Test name
Test status
Simulation time 635651178694 ps
CPU time 722.54 seconds
Started Jun 24 06:26:08 PM PDT 24
Finished Jun 24 06:38:11 PM PDT 24
Peak memory 191212 kb
Host smart-b06f9259-41f7-494c-95d3-4cc22232e195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803679813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3803679813
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.781139578
Short name T300
Test name
Test status
Simulation time 35071437031 ps
CPU time 408.57 seconds
Started Jun 24 06:26:07 PM PDT 24
Finished Jun 24 06:32:56 PM PDT 24
Peak memory 182960 kb
Host smart-6f3d2dbd-161d-444f-a4a6-a5abcc737332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781139578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.781139578
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3255472808
Short name T314
Test name
Test status
Simulation time 960114922760 ps
CPU time 298.11 seconds
Started Jun 24 06:26:08 PM PDT 24
Finished Jun 24 06:31:06 PM PDT 24
Peak memory 191416 kb
Host smart-db1c8afc-9cad-4a89-8447-f82d4fff1b6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255472808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3255472808
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3234698758
Short name T102
Test name
Test status
Simulation time 495549091729 ps
CPU time 692.69 seconds
Started Jun 24 06:26:06 PM PDT 24
Finished Jun 24 06:37:39 PM PDT 24
Peak memory 191188 kb
Host smart-018e4d2e-4eba-43de-89c5-63e1f92b3f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234698758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3234698758
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.212180796
Short name T154
Test name
Test status
Simulation time 207131043746 ps
CPU time 267.49 seconds
Started Jun 24 06:21:03 PM PDT 24
Finished Jun 24 06:25:31 PM PDT 24
Peak memory 182892 kb
Host smart-23e1cff1-37d4-498f-b9b0-8f077ee4f5a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212180796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.212180796
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2251940059
Short name T393
Test name
Test status
Simulation time 585729928136 ps
CPU time 256.42 seconds
Started Jun 24 06:21:04 PM PDT 24
Finished Jun 24 06:25:21 PM PDT 24
Peak memory 182996 kb
Host smart-c7ca114b-7f3a-4244-9866-d9a30ed5e534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251940059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2251940059
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1959087086
Short name T282
Test name
Test status
Simulation time 228016424415 ps
CPU time 292.87 seconds
Started Jun 24 06:21:05 PM PDT 24
Finished Jun 24 06:25:58 PM PDT 24
Peak memory 191184 kb
Host smart-7dad49d6-d37f-4fbf-b5b3-6e372b25673e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959087086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1959087086
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3469879576
Short name T337
Test name
Test status
Simulation time 202757453376 ps
CPU time 1478.51 seconds
Started Jun 24 06:21:04 PM PDT 24
Finished Jun 24 06:45:43 PM PDT 24
Peak memory 191184 kb
Host smart-ba540092-0502-4f18-a4fa-4f49cb26ae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469879576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3469879576
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.4192539213
Short name T69
Test name
Test status
Simulation time 1302115784481 ps
CPU time 472.38 seconds
Started Jun 24 06:21:04 PM PDT 24
Finished Jun 24 06:28:57 PM PDT 24
Peak memory 191184 kb
Host smart-542fe53a-d360-4f65-adec-baffa54d8f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192539213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.4192539213
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.3746937711
Short name T25
Test name
Test status
Simulation time 66573763378 ps
CPU time 97.45 seconds
Started Jun 24 06:26:07 PM PDT 24
Finished Jun 24 06:27:45 PM PDT 24
Peak memory 191180 kb
Host smart-e3a5242f-cdbc-4989-beca-44425e9586ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746937711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3746937711
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3288867520
Short name T404
Test name
Test status
Simulation time 334467062687 ps
CPU time 122.93 seconds
Started Jun 24 06:26:07 PM PDT 24
Finished Jun 24 06:28:11 PM PDT 24
Peak memory 182984 kb
Host smart-4b1e220c-05d1-4672-81fa-f394507a4870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288867520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3288867520
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2128511149
Short name T187
Test name
Test status
Simulation time 259477052551 ps
CPU time 228.75 seconds
Started Jun 24 06:26:08 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 191172 kb
Host smart-b5271248-1f3f-43d7-88db-3cf910f18774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128511149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2128511149
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2601970228
Short name T343
Test name
Test status
Simulation time 421838760868 ps
CPU time 135.34 seconds
Started Jun 24 06:26:17 PM PDT 24
Finished Jun 24 06:28:32 PM PDT 24
Peak memory 191180 kb
Host smart-9775ba63-bd2b-4989-9442-bc4703ee36d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601970228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2601970228
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3976765208
Short name T259
Test name
Test status
Simulation time 25239822022 ps
CPU time 42.88 seconds
Started Jun 24 06:26:17 PM PDT 24
Finished Jun 24 06:27:01 PM PDT 24
Peak memory 182988 kb
Host smart-f47ac58d-a1d7-41db-a344-ce3e34d0ad68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976765208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3976765208
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.533872297
Short name T114
Test name
Test status
Simulation time 369858706531 ps
CPU time 913.62 seconds
Started Jun 24 06:26:17 PM PDT 24
Finished Jun 24 06:41:31 PM PDT 24
Peak memory 191188 kb
Host smart-2e353f57-b9cf-4fbf-b8bb-6f3524cf7482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533872297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.533872297
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.97868870
Short name T164
Test name
Test status
Simulation time 123666093555 ps
CPU time 254.1 seconds
Started Jun 24 06:26:15 PM PDT 24
Finished Jun 24 06:30:30 PM PDT 24
Peak memory 191416 kb
Host smart-fbfcbabd-038e-42b0-ad4d-ad336e1f1906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97868870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.97868870
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4180615504
Short name T328
Test name
Test status
Simulation time 85910769925 ps
CPU time 463.44 seconds
Started Jun 24 06:26:16 PM PDT 24
Finished Jun 24 06:34:00 PM PDT 24
Peak memory 182988 kb
Host smart-456d94c0-8243-4ab3-9c49-91296580bd55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180615504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4180615504
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2428783660
Short name T375
Test name
Test status
Simulation time 63959598263 ps
CPU time 102.89 seconds
Started Jun 24 06:21:11 PM PDT 24
Finished Jun 24 06:22:54 PM PDT 24
Peak memory 182992 kb
Host smart-c92db711-9a03-4ad4-8d29-463f5d411a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428783660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2428783660
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4261197551
Short name T295
Test name
Test status
Simulation time 182934395119 ps
CPU time 476.47 seconds
Started Jun 24 06:21:11 PM PDT 24
Finished Jun 24 06:29:08 PM PDT 24
Peak memory 191212 kb
Host smart-0d31ed53-b826-4a2c-bea2-8e55cf4efbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261197551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4261197551
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4093486370
Short name T124
Test name
Test status
Simulation time 31488903987 ps
CPU time 28.25 seconds
Started Jun 24 06:26:16 PM PDT 24
Finished Jun 24 06:26:45 PM PDT 24
Peak memory 182980 kb
Host smart-28af9c94-5947-4cf6-9d97-bf2d618ba293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093486370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4093486370
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.358738352
Short name T327
Test name
Test status
Simulation time 77622205444 ps
CPU time 220.18 seconds
Started Jun 24 06:26:16 PM PDT 24
Finished Jun 24 06:29:57 PM PDT 24
Peak memory 182964 kb
Host smart-41a24c9f-66ab-4b7b-82a6-d171c1917850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358738352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.358738352
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1690768150
Short name T209
Test name
Test status
Simulation time 54211402490 ps
CPU time 277.98 seconds
Started Jun 24 06:26:28 PM PDT 24
Finished Jun 24 06:31:06 PM PDT 24
Peak memory 191180 kb
Host smart-2f3bf4cb-b0fe-433a-b12f-a90ed569f11b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690768150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1690768150
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1785607042
Short name T292
Test name
Test status
Simulation time 406459260684 ps
CPU time 203.63 seconds
Started Jun 24 06:26:26 PM PDT 24
Finished Jun 24 06:29:50 PM PDT 24
Peak memory 191180 kb
Host smart-40f1d436-30bb-4a46-80bf-9ee05f535a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785607042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1785607042
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3362373141
Short name T147
Test name
Test status
Simulation time 478842720036 ps
CPU time 255.62 seconds
Started Jun 24 06:26:26 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 191164 kb
Host smart-9fe1d440-3122-41e3-b23b-34c8ecb276a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362373141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3362373141
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3692053402
Short name T128
Test name
Test status
Simulation time 34663874857 ps
CPU time 62 seconds
Started Jun 24 06:26:28 PM PDT 24
Finished Jun 24 06:27:30 PM PDT 24
Peak memory 191180 kb
Host smart-d61ec587-9a80-4e9f-af9f-f72ec75b2041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692053402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3692053402
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2640411708
Short name T387
Test name
Test status
Simulation time 76570611494 ps
CPU time 97.94 seconds
Started Jun 24 06:21:12 PM PDT 24
Finished Jun 24 06:22:51 PM PDT 24
Peak memory 182988 kb
Host smart-0aa56bcf-6fdd-4b6a-84dd-663fbc0ccb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640411708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2640411708
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1438453852
Short name T201
Test name
Test status
Simulation time 636539765790 ps
CPU time 243.31 seconds
Started Jun 24 06:21:11 PM PDT 24
Finished Jun 24 06:25:15 PM PDT 24
Peak memory 191408 kb
Host smart-e89fd8dc-6c57-4fdd-8724-4da50e368e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438453852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1438453852
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1214499060
Short name T104
Test name
Test status
Simulation time 160417382143 ps
CPU time 103.67 seconds
Started Jun 24 06:21:22 PM PDT 24
Finished Jun 24 06:23:06 PM PDT 24
Peak memory 191164 kb
Host smart-825cbbdd-3b58-4934-881f-c611f76ee961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214499060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1214499060
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2243044170
Short name T419
Test name
Test status
Simulation time 289920273033 ps
CPU time 424.49 seconds
Started Jun 24 06:21:19 PM PDT 24
Finished Jun 24 06:28:24 PM PDT 24
Peak memory 191212 kb
Host smart-309995d1-9002-4e42-89d0-9c5c6f255b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243044170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2243044170
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.3988321519
Short name T108
Test name
Test status
Simulation time 913165797173 ps
CPU time 1290.77 seconds
Started Jun 24 06:26:26 PM PDT 24
Finished Jun 24 06:47:57 PM PDT 24
Peak memory 191172 kb
Host smart-9a4f2a8a-bc1e-4594-906c-968a76f1318d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988321519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3988321519
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2106979295
Short name T289
Test name
Test status
Simulation time 44543975980 ps
CPU time 16.83 seconds
Started Jun 24 06:26:27 PM PDT 24
Finished Jun 24 06:26:44 PM PDT 24
Peak memory 182924 kb
Host smart-a1db4357-09f6-41b1-ae4f-f7170902625c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106979295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2106979295
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2305423701
Short name T47
Test name
Test status
Simulation time 14338470789 ps
CPU time 25.46 seconds
Started Jun 24 06:26:26 PM PDT 24
Finished Jun 24 06:26:52 PM PDT 24
Peak memory 182984 kb
Host smart-ccbbaf4e-fa89-4dda-9bcf-20d6a82d736f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305423701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2305423701
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1328881470
Short name T239
Test name
Test status
Simulation time 30947405043 ps
CPU time 43.92 seconds
Started Jun 24 06:26:25 PM PDT 24
Finished Jun 24 06:27:09 PM PDT 24
Peak memory 182976 kb
Host smart-6ed11d56-2a20-4cc1-93be-49c11b00ece5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328881470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1328881470
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1484207580
Short name T96
Test name
Test status
Simulation time 198585589063 ps
CPU time 1967.86 seconds
Started Jun 24 06:26:25 PM PDT 24
Finished Jun 24 06:59:13 PM PDT 24
Peak memory 191180 kb
Host smart-8129451f-7107-428c-a8e4-0066b41190a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484207580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1484207580
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2704027695
Short name T30
Test name
Test status
Simulation time 72050215603 ps
CPU time 510.57 seconds
Started Jun 24 06:26:25 PM PDT 24
Finished Jun 24 06:34:56 PM PDT 24
Peak memory 191200 kb
Host smart-8fe26bd4-9db1-48fb-92b8-02ec273fbf90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704027695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2704027695
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1196176633
Short name T304
Test name
Test status
Simulation time 157728693199 ps
CPU time 78.98 seconds
Started Jun 24 06:26:27 PM PDT 24
Finished Jun 24 06:27:47 PM PDT 24
Peak memory 182988 kb
Host smart-b019feff-dc19-4985-b6a7-078d5fbd7e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196176633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1196176633
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3555956145
Short name T360
Test name
Test status
Simulation time 120106470000 ps
CPU time 97.79 seconds
Started Jun 24 06:21:21 PM PDT 24
Finished Jun 24 06:23:00 PM PDT 24
Peak memory 182964 kb
Host smart-eeffa1ea-637e-49e2-b6fd-ab9022a2a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555956145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3555956145
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2932569886
Short name T220
Test name
Test status
Simulation time 267972901856 ps
CPU time 144.6 seconds
Started Jun 24 06:21:20 PM PDT 24
Finished Jun 24 06:23:45 PM PDT 24
Peak memory 191164 kb
Host smart-9c5f81d7-9bb2-48b9-8f51-be2a4235cfec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932569886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2932569886
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2370330003
Short name T428
Test name
Test status
Simulation time 232466491 ps
CPU time 0.74 seconds
Started Jun 24 06:21:20 PM PDT 24
Finished Jun 24 06:21:22 PM PDT 24
Peak memory 191144 kb
Host smart-48a784a7-dd0e-4b0e-94ce-ef8010f29943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370330003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2370330003
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/191.rv_timer_random.970344832
Short name T144
Test name
Test status
Simulation time 88389877947 ps
CPU time 137.01 seconds
Started Jun 24 06:26:35 PM PDT 24
Finished Jun 24 06:28:52 PM PDT 24
Peak memory 191176 kb
Host smart-aa4b4d7d-efab-4d2b-a073-ef8e65f07122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970344832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.970344832
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2408732287
Short name T43
Test name
Test status
Simulation time 330724670197 ps
CPU time 143.88 seconds
Started Jun 24 06:26:38 PM PDT 24
Finished Jun 24 06:29:02 PM PDT 24
Peak memory 191176 kb
Host smart-b83efaf9-c2dd-4088-9e1e-f96b74e8be73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408732287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2408732287
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2307431576
Short name T320
Test name
Test status
Simulation time 599458068650 ps
CPU time 270.62 seconds
Started Jun 24 06:26:36 PM PDT 24
Finished Jun 24 06:31:07 PM PDT 24
Peak memory 191188 kb
Host smart-e3152db9-54cc-4b62-a431-ffa4271e4d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307431576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2307431576
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.338729246
Short name T409
Test name
Test status
Simulation time 119205533046 ps
CPU time 96.59 seconds
Started Jun 24 06:26:35 PM PDT 24
Finished Jun 24 06:28:12 PM PDT 24
Peak memory 191184 kb
Host smart-687e1056-50f0-41bc-902f-35bc0f3a4fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338729246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.338729246
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2093867130
Short name T162
Test name
Test status
Simulation time 73493060472 ps
CPU time 813.7 seconds
Started Jun 24 06:26:36 PM PDT 24
Finished Jun 24 06:40:10 PM PDT 24
Peak memory 193788 kb
Host smart-388edf1f-b9af-4ce9-af5b-20be91f8eafd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093867130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2093867130
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.810983009
Short name T293
Test name
Test status
Simulation time 319359448957 ps
CPU time 219.88 seconds
Started Jun 24 06:26:35 PM PDT 24
Finished Jun 24 06:30:16 PM PDT 24
Peak memory 191180 kb
Host smart-c006b1ca-d3af-410b-8ed5-462b48f7b5bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810983009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.810983009
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3111166182
Short name T348
Test name
Test status
Simulation time 188910411080 ps
CPU time 101.91 seconds
Started Jun 24 06:26:43 PM PDT 24
Finished Jun 24 06:28:25 PM PDT 24
Peak memory 191184 kb
Host smart-d415f2e2-4f3a-48a6-a0eb-9f9b393bd5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111166182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3111166182
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1054564911
Short name T125
Test name
Test status
Simulation time 25668387888 ps
CPU time 38.49 seconds
Started Jun 24 06:26:43 PM PDT 24
Finished Jun 24 06:27:22 PM PDT 24
Peak memory 182988 kb
Host smart-f45cd820-3277-40ae-8177-cabaf742ae84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054564911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1054564911
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.635536341
Short name T352
Test name
Test status
Simulation time 214208358796 ps
CPU time 368.3 seconds
Started Jun 24 06:20:27 PM PDT 24
Finished Jun 24 06:26:35 PM PDT 24
Peak memory 182980 kb
Host smart-108c1d75-656b-4531-8f27-d7c92bd02326
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635536341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.635536341
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_random.18382075
Short name T142
Test name
Test status
Simulation time 530814438420 ps
CPU time 1177.58 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:40:00 PM PDT 24
Peak memory 193816 kb
Host smart-0cf1355b-25cc-43d5-b9ed-492bc3efeae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18382075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.18382075
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.879901123
Short name T311
Test name
Test status
Simulation time 52185224372 ps
CPU time 76.33 seconds
Started Jun 24 06:20:27 PM PDT 24
Finished Jun 24 06:21:44 PM PDT 24
Peak memory 183004 kb
Host smart-cc63117a-7e17-439b-b2db-368b77f1854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879901123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.879901123
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1646308233
Short name T20
Test name
Test status
Simulation time 317123827 ps
CPU time 0.77 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:20:24 PM PDT 24
Peak memory 213752 kb
Host smart-ced26043-4137-4588-b8d0-3cedf7366cc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646308233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1646308233
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.407835525
Short name T74
Test name
Test status
Simulation time 341918015708 ps
CPU time 770.27 seconds
Started Jun 24 06:20:23 PM PDT 24
Finished Jun 24 06:33:14 PM PDT 24
Peak memory 195676 kb
Host smart-5a2e4301-5e51-4ec3-9c92-7dbc1e7913e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407835525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.407835525
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2728039553
Short name T46
Test name
Test status
Simulation time 520627055631 ps
CPU time 273.82 seconds
Started Jun 24 06:21:19 PM PDT 24
Finished Jun 24 06:25:54 PM PDT 24
Peak memory 182976 kb
Host smart-5f02ce3c-c7d0-4f70-9a10-818b28bd54a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728039553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2728039553
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1778805373
Short name T362
Test name
Test status
Simulation time 248330621201 ps
CPU time 184.71 seconds
Started Jun 24 06:21:19 PM PDT 24
Finished Jun 24 06:24:24 PM PDT 24
Peak memory 182992 kb
Host smart-edd7e0d9-7168-417d-b4c0-d7df522062c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778805373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1778805373
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.593998979
Short name T222
Test name
Test status
Simulation time 153575293915 ps
CPU time 1126.93 seconds
Started Jun 24 06:21:22 PM PDT 24
Finished Jun 24 06:40:09 PM PDT 24
Peak memory 191180 kb
Host smart-f0e370ac-f6f6-45e9-97e9-65e36f9e5958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593998979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.593998979
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1327713915
Short name T63
Test name
Test status
Simulation time 150149365161 ps
CPU time 96.52 seconds
Started Jun 24 06:21:20 PM PDT 24
Finished Jun 24 06:22:57 PM PDT 24
Peak memory 195400 kb
Host smart-e749234d-e287-449c-92e9-7e00be18c3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327713915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1327713915
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.895364513
Short name T76
Test name
Test status
Simulation time 282464336979 ps
CPU time 559.28 seconds
Started Jun 24 06:21:20 PM PDT 24
Finished Jun 24 06:30:40 PM PDT 24
Peak memory 195604 kb
Host smart-821c4307-550c-4d84-a7cf-f175f6de67ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895364513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
895364513
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.1527181439
Short name T16
Test name
Test status
Simulation time 40080699282 ps
CPU time 425.77 seconds
Started Jun 24 06:21:19 PM PDT 24
Finished Jun 24 06:28:26 PM PDT 24
Peak memory 205888 kb
Host smart-b6c6b2a4-78de-4cde-8ef7-96cec7a5072a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527181439 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.1527181439
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1408948586
Short name T372
Test name
Test status
Simulation time 18963096880 ps
CPU time 30.5 seconds
Started Jun 24 06:21:30 PM PDT 24
Finished Jun 24 06:22:01 PM PDT 24
Peak memory 182964 kb
Host smart-b5243136-ab2e-4712-92f2-63745857221e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408948586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1408948586
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1312669455
Short name T127
Test name
Test status
Simulation time 393408274910 ps
CPU time 306.89 seconds
Started Jun 24 06:21:29 PM PDT 24
Finished Jun 24 06:26:37 PM PDT 24
Peak memory 191184 kb
Host smart-f890b2b2-c28b-4436-8487-b3cac00f9a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312669455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1312669455
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2928820473
Short name T298
Test name
Test status
Simulation time 2050517123 ps
CPU time 1.97 seconds
Started Jun 24 06:21:29 PM PDT 24
Finished Jun 24 06:21:31 PM PDT 24
Peak memory 191144 kb
Host smart-81f8e627-f222-4599-91dd-51b62d4b1559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928820473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2928820473
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3422289968
Short name T382
Test name
Test status
Simulation time 118138886524 ps
CPU time 46.95 seconds
Started Jun 24 06:21:28 PM PDT 24
Finished Jun 24 06:22:16 PM PDT 24
Peak memory 182996 kb
Host smart-a4d556ac-029b-4c3a-adb5-519dd975dbec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422289968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3422289968
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1258730132
Short name T334
Test name
Test status
Simulation time 55912779593 ps
CPU time 96.3 seconds
Started Jun 24 06:21:31 PM PDT 24
Finished Jun 24 06:23:07 PM PDT 24
Peak memory 182984 kb
Host smart-e724e848-2489-4716-b8b0-b29ba2cca402
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258730132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1258730132
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3612637745
Short name T440
Test name
Test status
Simulation time 181506474344 ps
CPU time 266.77 seconds
Started Jun 24 06:21:30 PM PDT 24
Finished Jun 24 06:25:57 PM PDT 24
Peak memory 182984 kb
Host smart-a9ea15e3-7d78-41bb-ae15-885d0c0c5943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612637745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3612637745
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2152786611
Short name T181
Test name
Test status
Simulation time 355857610142 ps
CPU time 1219.32 seconds
Started Jun 24 06:21:30 PM PDT 24
Finished Jun 24 06:41:50 PM PDT 24
Peak memory 191184 kb
Host smart-cca6b30f-7e24-4c01-a3d2-77769781bf07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152786611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2152786611
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.11855190
Short name T366
Test name
Test status
Simulation time 126537534074 ps
CPU time 188.7 seconds
Started Jun 24 06:21:38 PM PDT 24
Finished Jun 24 06:24:47 PM PDT 24
Peak memory 191112 kb
Host smart-256bb410-0277-4946-a74f-d421f73b4229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11855190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.11855190
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2293387414
Short name T374
Test name
Test status
Simulation time 38621002682 ps
CPU time 53.74 seconds
Started Jun 24 06:21:37 PM PDT 24
Finished Jun 24 06:22:31 PM PDT 24
Peak memory 182992 kb
Host smart-41bdf923-a616-498d-9fb7-6b5a43f0b107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293387414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2293387414
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.262095521
Short name T9
Test name
Test status
Simulation time 30277687987 ps
CPU time 43.98 seconds
Started Jun 24 06:21:40 PM PDT 24
Finished Jun 24 06:22:25 PM PDT 24
Peak memory 192280 kb
Host smart-0efccc17-e09c-4e75-9042-eaa6dc195103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262095521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.262095521
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.989809002
Short name T406
Test name
Test status
Simulation time 622595105 ps
CPU time 0.84 seconds
Started Jun 24 06:21:39 PM PDT 24
Finished Jun 24 06:21:41 PM PDT 24
Peak memory 191500 kb
Host smart-599fb048-94b5-4386-b0f5-9cc99151c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989809002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.989809002
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.328458693
Short name T41
Test name
Test status
Simulation time 290291255561 ps
CPU time 631.25 seconds
Started Jun 24 06:21:37 PM PDT 24
Finished Jun 24 06:32:09 PM PDT 24
Peak memory 205868 kb
Host smart-06175d54-7ea6-4bb2-8993-fc019d76e5ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328458693 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.328458693
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2420520041
Short name T229
Test name
Test status
Simulation time 645194411686 ps
CPU time 569.41 seconds
Started Jun 24 06:21:46 PM PDT 24
Finished Jun 24 06:31:16 PM PDT 24
Peak memory 182972 kb
Host smart-ff03f729-0502-4f52-9b7a-e1c9e0f63cc5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420520041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2420520041
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1783414794
Short name T416
Test name
Test status
Simulation time 281189529012 ps
CPU time 39.56 seconds
Started Jun 24 06:21:47 PM PDT 24
Finished Jun 24 06:22:27 PM PDT 24
Peak memory 183216 kb
Host smart-b78f3974-fd3e-4e4b-93be-c1aaf9ad2d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783414794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1783414794
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2778360956
Short name T51
Test name
Test status
Simulation time 106941589834 ps
CPU time 389.71 seconds
Started Jun 24 06:21:47 PM PDT 24
Finished Jun 24 06:28:17 PM PDT 24
Peak memory 194856 kb
Host smart-5498c002-ed9c-4c06-b19b-a8e6f882a929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778360956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2778360956
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3667785309
Short name T377
Test name
Test status
Simulation time 372011108 ps
CPU time 0.87 seconds
Started Jun 24 06:21:46 PM PDT 24
Finished Jun 24 06:21:47 PM PDT 24
Peak memory 191184 kb
Host smart-fb908f3f-44e8-4126-9967-f5ffae1a068e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667785309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3667785309
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.249983037
Short name T152
Test name
Test status
Simulation time 727973528317 ps
CPU time 544.66 seconds
Started Jun 24 06:21:50 PM PDT 24
Finished Jun 24 06:30:55 PM PDT 24
Peak memory 191168 kb
Host smart-0cb7c177-e87c-460d-8862-a5fd514f5d7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249983037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
249983037
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2076706730
Short name T272
Test name
Test status
Simulation time 47535649340 ps
CPU time 25.08 seconds
Started Jun 24 06:21:50 PM PDT 24
Finished Jun 24 06:22:15 PM PDT 24
Peak memory 182964 kb
Host smart-011865c9-7980-4fbd-8ace-eb6ffe91f8af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076706730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2076706730
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3058632032
Short name T443
Test name
Test status
Simulation time 118126440385 ps
CPU time 133.76 seconds
Started Jun 24 06:21:50 PM PDT 24
Finished Jun 24 06:24:04 PM PDT 24
Peak memory 182984 kb
Host smart-6ef34623-fa1a-4711-8696-581c72bdcdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058632032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3058632032
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3991741543
Short name T280
Test name
Test status
Simulation time 64468457630 ps
CPU time 57.07 seconds
Started Jun 24 06:21:48 PM PDT 24
Finished Jun 24 06:22:46 PM PDT 24
Peak memory 191184 kb
Host smart-87f05062-b504-48c0-8e73-ba48af00f5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991741543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3991741543
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2567766365
Short name T435
Test name
Test status
Simulation time 190109236290 ps
CPU time 279.19 seconds
Started Jun 24 06:21:56 PM PDT 24
Finished Jun 24 06:26:35 PM PDT 24
Peak memory 182976 kb
Host smart-ee3969a9-003a-49a1-ae70-b3bcb359a06c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567766365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2567766365
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3683379858
Short name T368
Test name
Test status
Simulation time 163021130956 ps
CPU time 116.69 seconds
Started Jun 24 06:21:56 PM PDT 24
Finished Jun 24 06:23:53 PM PDT 24
Peak memory 182996 kb
Host smart-4d4ca62a-eaa7-4c9a-b245-c30b7f9671ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683379858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3683379858
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1196925669
Short name T148
Test name
Test status
Simulation time 482533229740 ps
CPU time 372.65 seconds
Started Jun 24 06:21:58 PM PDT 24
Finished Jun 24 06:28:11 PM PDT 24
Peak memory 193584 kb
Host smart-ec8b1cee-d316-47ed-8fc7-68dab69b1df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196925669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1196925669
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2877792971
Short name T155
Test name
Test status
Simulation time 262095557092 ps
CPU time 112.64 seconds
Started Jun 24 06:21:57 PM PDT 24
Finished Jun 24 06:23:50 PM PDT 24
Peak memory 182992 kb
Host smart-49e52e85-893a-4a5a-9242-60529b3187fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877792971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2877792971
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.81193792
Short name T107
Test name
Test status
Simulation time 135274582307 ps
CPU time 202.2 seconds
Started Jun 24 06:21:57 PM PDT 24
Finished Jun 24 06:25:20 PM PDT 24
Peak memory 182984 kb
Host smart-cc3ad46d-b12b-4acd-bf26-6d27b6439830
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81193792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.rv_timer_cfg_update_on_fly.81193792
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1391786104
Short name T378
Test name
Test status
Simulation time 416684819964 ps
CPU time 150.35 seconds
Started Jun 24 06:21:58 PM PDT 24
Finished Jun 24 06:24:29 PM PDT 24
Peak memory 182984 kb
Host smart-f90db363-3e72-4b09-88a9-52e67b935aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391786104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1391786104
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3940357526
Short name T321
Test name
Test status
Simulation time 162574201827 ps
CPU time 284.57 seconds
Started Jun 24 06:22:08 PM PDT 24
Finished Jun 24 06:26:53 PM PDT 24
Peak memory 182984 kb
Host smart-7dee3fb6-cdd9-4ccb-9186-1484cdadc6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940357526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3940357526
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3228538237
Short name T442
Test name
Test status
Simulation time 324582876592 ps
CPU time 112.45 seconds
Started Jun 24 06:22:13 PM PDT 24
Finished Jun 24 06:24:06 PM PDT 24
Peak memory 182936 kb
Host smart-143c0d50-75b3-439a-bbf3-7aba86ade79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228538237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3228538237
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.130512246
Short name T183
Test name
Test status
Simulation time 604995662253 ps
CPU time 275.48 seconds
Started Jun 24 06:22:07 PM PDT 24
Finished Jun 24 06:26:43 PM PDT 24
Peak memory 191196 kb
Host smart-2ff7ae87-4d4e-468e-8fe3-b037b4440b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130512246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.130512246
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1228731529
Short name T312
Test name
Test status
Simulation time 89993080645 ps
CPU time 143.94 seconds
Started Jun 24 06:22:06 PM PDT 24
Finished Jun 24 06:24:31 PM PDT 24
Peak memory 191172 kb
Host smart-2cdee125-5215-47e0-b874-034e8624f822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228731529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1228731529
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.132037410
Short name T135
Test name
Test status
Simulation time 3410837350 ps
CPU time 3.57 seconds
Started Jun 24 06:22:15 PM PDT 24
Finished Jun 24 06:22:19 PM PDT 24
Peak memory 182976 kb
Host smart-60b0a585-c267-47ae-aecb-50b92607c10d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132037410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.132037410
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1694972470
Short name T405
Test name
Test status
Simulation time 197566691151 ps
CPU time 149 seconds
Started Jun 24 06:22:15 PM PDT 24
Finished Jun 24 06:24:45 PM PDT 24
Peak memory 182992 kb
Host smart-d5b0a609-482f-44b9-aebb-3a1a20352829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694972470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1694972470
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2396151021
Short name T296
Test name
Test status
Simulation time 96241518917 ps
CPU time 160.54 seconds
Started Jun 24 06:22:16 PM PDT 24
Finished Jun 24 06:24:57 PM PDT 24
Peak memory 194564 kb
Host smart-25792947-1efd-4cd9-8dae-e5469e789e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396151021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2396151021
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2599619701
Short name T325
Test name
Test status
Simulation time 37343700501 ps
CPU time 47.37 seconds
Started Jun 24 06:22:14 PM PDT 24
Finished Jun 24 06:23:02 PM PDT 24
Peak memory 183004 kb
Host smart-b221ba77-de26-4288-a42c-0c0fdee20f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599619701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2599619701
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2834177610
Short name T45
Test name
Test status
Simulation time 54174557411 ps
CPU time 74.25 seconds
Started Jun 24 06:22:16 PM PDT 24
Finished Jun 24 06:23:30 PM PDT 24
Peak memory 182988 kb
Host smart-245c2ab4-5df4-407f-adb0-c86a8131bea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834177610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2834177610
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3166901330
Short name T309
Test name
Test status
Simulation time 741896004926 ps
CPU time 402.67 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:27:06 PM PDT 24
Peak memory 182980 kb
Host smart-37aebc51-35ba-4914-9f44-dbd0faafa6d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166901330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3166901330
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1034414822
Short name T384
Test name
Test status
Simulation time 134841251082 ps
CPU time 171.49 seconds
Started Jun 24 06:20:26 PM PDT 24
Finished Jun 24 06:23:19 PM PDT 24
Peak memory 183004 kb
Host smart-18e94ef2-48ee-400b-8c28-d788758d8341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034414822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1034414822
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2347759602
Short name T105
Test name
Test status
Simulation time 1054322474058 ps
CPU time 1388.02 seconds
Started Jun 24 06:20:26 PM PDT 24
Finished Jun 24 06:43:35 PM PDT 24
Peak memory 191192 kb
Host smart-d8552ab3-c6dd-4476-991a-c2bb2294ee22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347759602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2347759602
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.694659762
Short name T350
Test name
Test status
Simulation time 202017106684 ps
CPU time 596.45 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:30:19 PM PDT 24
Peak memory 191184 kb
Host smart-1af866f6-4800-4d4c-a4fc-5b63c8ce1137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694659762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.694659762
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.4056502115
Short name T17
Test name
Test status
Simulation time 105682032 ps
CPU time 0.95 seconds
Started Jun 24 06:20:22 PM PDT 24
Finished Jun 24 06:20:24 PM PDT 24
Peak memory 214348 kb
Host smart-dd6dd894-ce64-4718-b1fa-1cea5f3a822e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056502115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4056502115
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1298002450
Short name T354
Test name
Test status
Simulation time 867493492181 ps
CPU time 452.12 seconds
Started Jun 24 06:22:14 PM PDT 24
Finished Jun 24 06:29:47 PM PDT 24
Peak memory 182984 kb
Host smart-f4e44762-9c5e-4d88-a1a4-87fad80df00a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298002450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1298002450
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1232073297
Short name T408
Test name
Test status
Simulation time 13424541358 ps
CPU time 14.15 seconds
Started Jun 24 06:22:15 PM PDT 24
Finished Jun 24 06:22:30 PM PDT 24
Peak memory 182944 kb
Host smart-bbbe030f-9e25-4829-84ea-5b77331ff488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232073297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1232073297
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.485429725
Short name T130
Test name
Test status
Simulation time 69842122345 ps
CPU time 113.4 seconds
Started Jun 24 06:22:15 PM PDT 24
Finished Jun 24 06:24:09 PM PDT 24
Peak memory 191176 kb
Host smart-95e5be3b-5ec5-47e2-b11c-6c92168f53d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485429725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.485429725
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3573421601
Short name T373
Test name
Test status
Simulation time 229690412064 ps
CPU time 290.33 seconds
Started Jun 24 06:22:17 PM PDT 24
Finished Jun 24 06:27:08 PM PDT 24
Peak memory 182984 kb
Host smart-47c0b282-6640-4657-95b0-13d2953e6d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573421601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3573421601
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1218196184
Short name T273
Test name
Test status
Simulation time 175461164578 ps
CPU time 254.53 seconds
Started Jun 24 06:22:22 PM PDT 24
Finished Jun 24 06:26:37 PM PDT 24
Peak memory 182968 kb
Host smart-1e6a7ca2-e388-4abc-8424-e3a7b302109d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218196184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1218196184
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2446558469
Short name T415
Test name
Test status
Simulation time 137543120110 ps
CPU time 57.59 seconds
Started Jun 24 06:22:23 PM PDT 24
Finished Jun 24 06:23:21 PM PDT 24
Peak memory 182996 kb
Host smart-6f303ef4-9194-4ce2-b3d3-081b20c57ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446558469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2446558469
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3884714378
Short name T101
Test name
Test status
Simulation time 676325227784 ps
CPU time 802.51 seconds
Started Jun 24 06:22:22 PM PDT 24
Finished Jun 24 06:35:46 PM PDT 24
Peak memory 191192 kb
Host smart-71ea7c23-47fc-4b82-a8b8-bcacf7e60748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884714378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3884714378
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3911127007
Short name T44
Test name
Test status
Simulation time 17493152361 ps
CPU time 12.26 seconds
Started Jun 24 06:22:23 PM PDT 24
Finished Jun 24 06:22:36 PM PDT 24
Peak memory 183008 kb
Host smart-01470d0f-f3b6-4eae-babc-0a74542fb027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911127007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3911127007
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1300413140
Short name T73
Test name
Test status
Simulation time 207592093683 ps
CPU time 299.9 seconds
Started Jun 24 06:22:21 PM PDT 24
Finished Jun 24 06:27:22 PM PDT 24
Peak memory 191196 kb
Host smart-74efef04-af61-40e2-a3b5-f6d34e0edc57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300413140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1300413140
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.1821648933
Short name T40
Test name
Test status
Simulation time 18905480430 ps
CPU time 160.33 seconds
Started Jun 24 06:22:23 PM PDT 24
Finished Jun 24 06:25:04 PM PDT 24
Peak memory 197740 kb
Host smart-8a037bd1-801b-49be-85b7-423ec816f920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821648933 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.1821648933
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3876853032
Short name T26
Test name
Test status
Simulation time 3679383937532 ps
CPU time 1214.99 seconds
Started Jun 24 06:22:32 PM PDT 24
Finished Jun 24 06:42:47 PM PDT 24
Peak memory 182976 kb
Host smart-b9223451-2c6d-44e4-ae6d-68e001a47c96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876853032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3876853032
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.40942684
Short name T380
Test name
Test status
Simulation time 196443499908 ps
CPU time 132.52 seconds
Started Jun 24 06:22:33 PM PDT 24
Finished Jun 24 06:24:46 PM PDT 24
Peak memory 183000 kb
Host smart-868b2a57-6fe9-40c6-bbbf-b58b8db02c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40942684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.40942684
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2203961715
Short name T429
Test name
Test status
Simulation time 237213351707 ps
CPU time 103.1 seconds
Started Jun 24 06:22:33 PM PDT 24
Finished Jun 24 06:24:17 PM PDT 24
Peak memory 193436 kb
Host smart-e4af57ff-1e89-4316-b83f-bf20f980aefd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203961715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2203961715
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.126184621
Short name T417
Test name
Test status
Simulation time 74326354734 ps
CPU time 45.89 seconds
Started Jun 24 06:22:34 PM PDT 24
Finished Jun 24 06:23:20 PM PDT 24
Peak memory 182972 kb
Host smart-cfd210f0-88a2-4a5c-861c-24ddde3fc370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126184621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.126184621
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1262196794
Short name T189
Test name
Test status
Simulation time 59702325038 ps
CPU time 61.02 seconds
Started Jun 24 06:22:40 PM PDT 24
Finished Jun 24 06:23:42 PM PDT 24
Peak memory 182952 kb
Host smart-302b8bfc-ab80-4a11-871c-678b55956b48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262196794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1262196794
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3654389477
Short name T379
Test name
Test status
Simulation time 188497944452 ps
CPU time 138.93 seconds
Started Jun 24 06:22:32 PM PDT 24
Finished Jun 24 06:24:51 PM PDT 24
Peak memory 182992 kb
Host smart-7965c747-6e63-4dbc-a0f2-a9c1aa9e2353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654389477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3654389477
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.78483116
Short name T276
Test name
Test status
Simulation time 371011533422 ps
CPU time 208.41 seconds
Started Jun 24 06:22:33 PM PDT 24
Finished Jun 24 06:26:02 PM PDT 24
Peak memory 191180 kb
Host smart-5390de9f-3521-43c9-a914-5304dd452aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78483116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.78483116
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3121858439
Short name T427
Test name
Test status
Simulation time 132600957 ps
CPU time 0.81 seconds
Started Jun 24 06:22:41 PM PDT 24
Finished Jun 24 06:22:42 PM PDT 24
Peak memory 191372 kb
Host smart-dcfcaf0f-633e-4d9b-ad73-2e84e40c3d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121858439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3121858439
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2439701202
Short name T211
Test name
Test status
Simulation time 147231979033 ps
CPU time 938.53 seconds
Started Jun 24 06:22:42 PM PDT 24
Finished Jun 24 06:38:21 PM PDT 24
Peak memory 194812 kb
Host smart-8a5a0ea3-e15b-4d95-833a-be73b85cdbb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439701202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2439701202
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.3979979890
Short name T39
Test name
Test status
Simulation time 598454668794 ps
CPU time 752.77 seconds
Started Jun 24 06:22:40 PM PDT 24
Finished Jun 24 06:35:14 PM PDT 24
Peak memory 214024 kb
Host smart-2599db12-0dfd-41cf-bec1-cf04084a212d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979979890 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.3979979890
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.4187277019
Short name T165
Test name
Test status
Simulation time 91035706766 ps
CPU time 159.42 seconds
Started Jun 24 06:22:41 PM PDT 24
Finished Jun 24 06:25:21 PM PDT 24
Peak memory 182988 kb
Host smart-bc47b4a6-7658-48c1-8494-65a6e8ab223b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187277019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.4187277019
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2491716307
Short name T400
Test name
Test status
Simulation time 280042489860 ps
CPU time 81.32 seconds
Started Jun 24 06:22:39 PM PDT 24
Finished Jun 24 06:24:01 PM PDT 24
Peak memory 182956 kb
Host smart-3aa4e579-7719-4885-a2f1-4d57d39932d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491716307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2491716307
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2549072566
Short name T200
Test name
Test status
Simulation time 146313715693 ps
CPU time 1365.8 seconds
Started Jun 24 06:22:40 PM PDT 24
Finished Jun 24 06:45:27 PM PDT 24
Peak memory 182984 kb
Host smart-59f4f913-3453-40d5-83b6-83ee4aca60ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549072566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2549072566
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.142392438
Short name T407
Test name
Test status
Simulation time 37494771570 ps
CPU time 237.44 seconds
Started Jun 24 06:22:51 PM PDT 24
Finished Jun 24 06:26:49 PM PDT 24
Peak memory 191204 kb
Host smart-b79cc3b3-d43f-4f4e-982d-ba186ad98231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142392438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.142392438
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1462342194
Short name T410
Test name
Test status
Simulation time 109064734303 ps
CPU time 107.48 seconds
Started Jun 24 06:22:50 PM PDT 24
Finished Jun 24 06:24:39 PM PDT 24
Peak memory 182976 kb
Host smart-6590f12c-6728-4046-b928-c3e4e87778c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462342194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1462342194
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1327878394
Short name T414
Test name
Test status
Simulation time 72931903248 ps
CPU time 93.22 seconds
Started Jun 24 06:22:50 PM PDT 24
Finished Jun 24 06:24:24 PM PDT 24
Peak memory 183216 kb
Host smart-3e7b98e3-216b-4943-a077-27591dc2a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327878394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1327878394
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2224776149
Short name T315
Test name
Test status
Simulation time 59082637539 ps
CPU time 153.5 seconds
Started Jun 24 06:22:52 PM PDT 24
Finished Jun 24 06:25:26 PM PDT 24
Peak memory 191180 kb
Host smart-8456d500-b255-41bd-90de-59c1018ab15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224776149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2224776149
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.153329091
Short name T438
Test name
Test status
Simulation time 138822118658 ps
CPU time 99.38 seconds
Started Jun 24 06:22:52 PM PDT 24
Finished Jun 24 06:24:31 PM PDT 24
Peak memory 183000 kb
Host smart-1f291bdd-2624-41e8-b99e-f44267491045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153329091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.153329091
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2014066489
Short name T395
Test name
Test status
Simulation time 220153063083 ps
CPU time 115.6 seconds
Started Jun 24 06:22:58 PM PDT 24
Finished Jun 24 06:24:54 PM PDT 24
Peak memory 182968 kb
Host smart-38f95858-9972-448d-9a81-74a19a2dee0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014066489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2014066489
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3964400961
Short name T376
Test name
Test status
Simulation time 362883865659 ps
CPU time 185.02 seconds
Started Jun 24 06:22:57 PM PDT 24
Finished Jun 24 06:26:03 PM PDT 24
Peak memory 182996 kb
Host smart-e25dfdb6-5ef6-4c10-9da2-5c2b5f7ef1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964400961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3964400961
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2730929645
Short name T303
Test name
Test status
Simulation time 459597853757 ps
CPU time 422.97 seconds
Started Jun 24 06:22:59 PM PDT 24
Finished Jun 24 06:30:02 PM PDT 24
Peak memory 191196 kb
Host smart-28ffa7e0-32b4-4804-9c34-d4e02c15e7af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730929645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2730929645
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2593826923
Short name T385
Test name
Test status
Simulation time 19769080 ps
CPU time 0.55 seconds
Started Jun 24 06:22:57 PM PDT 24
Finished Jun 24 06:22:59 PM PDT 24
Peak memory 182748 kb
Host smart-14c6c912-5ffe-4cdb-a01a-00a5376d6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593826923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2593826923
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.824307827
Short name T212
Test name
Test status
Simulation time 488725759439 ps
CPU time 4152.07 seconds
Started Jun 24 06:22:59 PM PDT 24
Finished Jun 24 07:32:13 PM PDT 24
Peak memory 191188 kb
Host smart-9b97a860-5ee6-4c66-b79d-9b503ebb5c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824307827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
824307827
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2748980152
Short name T28
Test name
Test status
Simulation time 302325378132 ps
CPU time 265.69 seconds
Started Jun 24 06:23:09 PM PDT 24
Finished Jun 24 06:27:35 PM PDT 24
Peak memory 182976 kb
Host smart-c10d1354-164f-423a-929b-78158c54ebc3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748980152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2748980152
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1732000308
Short name T401
Test name
Test status
Simulation time 310632812988 ps
CPU time 38.08 seconds
Started Jun 24 06:23:09 PM PDT 24
Finished Jun 24 06:23:47 PM PDT 24
Peak memory 182988 kb
Host smart-6703c361-2bca-4b36-8433-858a2f8cd029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732000308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1732000308
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.251923724
Short name T365
Test name
Test status
Simulation time 99115596 ps
CPU time 1.63 seconds
Started Jun 24 06:23:07 PM PDT 24
Finished Jun 24 06:23:10 PM PDT 24
Peak memory 182888 kb
Host smart-bf6e14d2-ec7a-48f0-9b5f-ece8999aebc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251923724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.251923724
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2797861139
Short name T221
Test name
Test status
Simulation time 399974480159 ps
CPU time 625.12 seconds
Started Jun 24 06:23:08 PM PDT 24
Finished Jun 24 06:33:33 PM PDT 24
Peak memory 182980 kb
Host smart-57a80198-21c6-4357-8905-dcae6312b728
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797861139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2797861139
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.69628482
Short name T437
Test name
Test status
Simulation time 47907694546 ps
CPU time 67.65 seconds
Started Jun 24 06:23:06 PM PDT 24
Finished Jun 24 06:24:14 PM PDT 24
Peak memory 182972 kb
Host smart-b10381d8-0968-4c24-a751-dda40b9cd9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69628482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.69628482
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2511060930
Short name T261
Test name
Test status
Simulation time 437931889014 ps
CPU time 262.97 seconds
Started Jun 24 06:23:08 PM PDT 24
Finished Jun 24 06:27:32 PM PDT 24
Peak memory 191420 kb
Host smart-8c75b41e-93b0-48c1-88a1-da2ccb9cf51c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511060930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2511060930
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.495529104
Short name T333
Test name
Test status
Simulation time 67247025350 ps
CPU time 130.7 seconds
Started Jun 24 06:23:15 PM PDT 24
Finished Jun 24 06:25:27 PM PDT 24
Peak memory 183004 kb
Host smart-d9bbe983-a6e8-4c36-895c-09b6d7e832fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495529104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.495529104
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1209775228
Short name T194
Test name
Test status
Simulation time 5748206406570 ps
CPU time 3624.93 seconds
Started Jun 24 06:23:16 PM PDT 24
Finished Jun 24 07:23:42 PM PDT 24
Peak memory 191172 kb
Host smart-321b06a3-394a-4809-ae0c-4e72ac25533e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209775228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1209775228
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.2382972622
Short name T335
Test name
Test status
Simulation time 154790508745 ps
CPU time 95.05 seconds
Started Jun 24 06:23:15 PM PDT 24
Finished Jun 24 06:24:50 PM PDT 24
Peak memory 191180 kb
Host smart-f30b9fe5-5b62-4519-8c5a-7ef7c2914884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382972622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2382972622
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3996258306
Short name T439
Test name
Test status
Simulation time 377568255 ps
CPU time 0.8 seconds
Started Jun 24 06:23:17 PM PDT 24
Finished Jun 24 06:23:18 PM PDT 24
Peak memory 182748 kb
Host smart-388eb04b-cf6d-4d1d-8650-08b7899c14b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996258306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3996258306
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.282724888
Short name T340
Test name
Test status
Simulation time 501589006486 ps
CPU time 897.41 seconds
Started Jun 24 06:23:17 PM PDT 24
Finished Jun 24 06:38:15 PM PDT 24
Peak memory 191184 kb
Host smart-a9b0d103-f0ee-4708-90cf-f4d841503f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282724888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
282724888
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4116809339
Short name T402
Test name
Test status
Simulation time 202050068189 ps
CPU time 86.28 seconds
Started Jun 24 06:20:31 PM PDT 24
Finished Jun 24 06:21:58 PM PDT 24
Peak memory 182952 kb
Host smart-3a4d7f7a-a82c-47e4-a6cb-444c7a54b7ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116809339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.4116809339
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.51967088
Short name T418
Test name
Test status
Simulation time 3590697025 ps
CPU time 6.61 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:20:38 PM PDT 24
Peak memory 191184 kb
Host smart-438d4b29-be49-434f-8b22-e3d70b82a8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51967088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.51967088
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.417219984
Short name T21
Test name
Test status
Simulation time 588985189 ps
CPU time 0.92 seconds
Started Jun 24 06:20:31 PM PDT 24
Finished Jun 24 06:20:33 PM PDT 24
Peak memory 214260 kb
Host smart-f2a74dc7-0345-4678-afec-95ee8911ebaf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417219984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.417219984
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3076716555
Short name T52
Test name
Test status
Simulation time 8863768892 ps
CPU time 69.48 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:21:40 PM PDT 24
Peak memory 195112 kb
Host smart-6eda7935-b12b-4d3b-aabc-5a9431ebd6e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076716555 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3076716555
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2188530732
Short name T346
Test name
Test status
Simulation time 1113786147928 ps
CPU time 436.34 seconds
Started Jun 24 06:23:26 PM PDT 24
Finished Jun 24 06:30:43 PM PDT 24
Peak memory 182980 kb
Host smart-1969d616-1a40-4c89-acc1-325ac173af0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188530732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2188530732
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2786352609
Short name T383
Test name
Test status
Simulation time 68127194285 ps
CPU time 40.8 seconds
Started Jun 24 06:23:29 PM PDT 24
Finished Jun 24 06:24:10 PM PDT 24
Peak memory 183016 kb
Host smart-615422fe-cccd-4e8e-ac2f-2546b0c2f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786352609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2786352609
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1683070822
Short name T134
Test name
Test status
Simulation time 101346355409 ps
CPU time 187.79 seconds
Started Jun 24 06:23:28 PM PDT 24
Finished Jun 24 06:26:37 PM PDT 24
Peak memory 194616 kb
Host smart-cb9fbf2a-b05c-4fe1-8cbd-58714a5b5139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683070822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1683070822
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.837693451
Short name T445
Test name
Test status
Simulation time 165327239510 ps
CPU time 286.96 seconds
Started Jun 24 06:23:33 PM PDT 24
Finished Jun 24 06:28:20 PM PDT 24
Peak memory 182988 kb
Host smart-a36d06f1-6f6d-4f5b-b5c4-53f0d59c1b32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837693451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.837693451
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1105938195
Short name T371
Test name
Test status
Simulation time 106597980731 ps
CPU time 147.33 seconds
Started Jun 24 06:23:36 PM PDT 24
Finished Jun 24 06:26:04 PM PDT 24
Peak memory 183000 kb
Host smart-2ebfdf8f-a6e2-42bf-b37a-8ccbbfd0b7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105938195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1105938195
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3349325386
Short name T185
Test name
Test status
Simulation time 96789005346 ps
CPU time 63.96 seconds
Started Jun 24 06:23:36 PM PDT 24
Finished Jun 24 06:24:41 PM PDT 24
Peak memory 191188 kb
Host smart-b3c1730b-b14b-43ec-9e48-c3b66998cd68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349325386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3349325386
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1243274518
Short name T237
Test name
Test status
Simulation time 99999360631 ps
CPU time 50.38 seconds
Started Jun 24 06:23:34 PM PDT 24
Finished Jun 24 06:24:25 PM PDT 24
Peak memory 183000 kb
Host smart-90b2abef-21e4-4d34-8f64-87e032264258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243274518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1243274518
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3373352063
Short name T394
Test name
Test status
Simulation time 592689209570 ps
CPU time 188.6 seconds
Started Jun 24 06:23:36 PM PDT 24
Finished Jun 24 06:26:44 PM PDT 24
Peak memory 182992 kb
Host smart-6f26513a-210f-4085-9cab-af36f021587f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373352063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3373352063
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2875428491
Short name T403
Test name
Test status
Simulation time 643473697082 ps
CPU time 111.11 seconds
Started Jun 24 06:23:41 PM PDT 24
Finished Jun 24 06:25:33 PM PDT 24
Peak memory 183000 kb
Host smart-da879ebd-7d64-436c-8871-ace2658fcb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875428491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2875428491
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3948248350
Short name T5
Test name
Test status
Simulation time 364479405027 ps
CPU time 199.24 seconds
Started Jun 24 06:23:33 PM PDT 24
Finished Jun 24 06:26:52 PM PDT 24
Peak memory 191172 kb
Host smart-dda84bfb-7d69-4157-8203-b68b5dec7f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948248350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3948248350
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1235106151
Short name T431
Test name
Test status
Simulation time 19936986250 ps
CPU time 34.59 seconds
Started Jun 24 06:23:43 PM PDT 24
Finished Jun 24 06:24:18 PM PDT 24
Peak memory 194400 kb
Host smart-4e93bb21-e004-43c4-a0bd-756e9f192995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235106151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1235106151
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2668033953
Short name T215
Test name
Test status
Simulation time 120734618257 ps
CPU time 240.68 seconds
Started Jun 24 06:23:42 PM PDT 24
Finished Jun 24 06:27:43 PM PDT 24
Peak memory 191200 kb
Host smart-0a1a37f2-9399-483a-bb6c-1974c5d1690c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668033953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2668033953
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2317343944
Short name T421
Test name
Test status
Simulation time 3185758099054 ps
CPU time 719.12 seconds
Started Jun 24 06:23:43 PM PDT 24
Finished Jun 24 06:35:42 PM PDT 24
Peak memory 182980 kb
Host smart-98b57984-3723-4cb9-876a-43a3c2d8e427
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317343944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2317343944
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2784329834
Short name T432
Test name
Test status
Simulation time 310013083917 ps
CPU time 130.83 seconds
Started Jun 24 06:23:41 PM PDT 24
Finished Jun 24 06:25:52 PM PDT 24
Peak memory 182984 kb
Host smart-a7ecc8df-6d09-4ea0-bfc9-bba39e461097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784329834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2784329834
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.381818994
Short name T153
Test name
Test status
Simulation time 52585335066 ps
CPU time 94.51 seconds
Started Jun 24 06:23:41 PM PDT 24
Finished Jun 24 06:25:16 PM PDT 24
Peak memory 191216 kb
Host smart-78ff2026-bd4f-4156-9802-ffd5512e1ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381818994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.381818994
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.376040217
Short name T318
Test name
Test status
Simulation time 21643775772 ps
CPU time 25.81 seconds
Started Jun 24 06:23:43 PM PDT 24
Finished Jun 24 06:24:10 PM PDT 24
Peak memory 191168 kb
Host smart-72e0cc97-ea3c-4e0f-8166-51f781c2e549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376040217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.376040217
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1139592248
Short name T36
Test name
Test status
Simulation time 54981031510 ps
CPU time 495.71 seconds
Started Jun 24 06:23:41 PM PDT 24
Finished Jun 24 06:31:57 PM PDT 24
Peak memory 205924 kb
Host smart-bbda9d53-3a82-4e1a-b5b7-1b16119d181e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139592248 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1139592248
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1626026796
Short name T274
Test name
Test status
Simulation time 55535493699 ps
CPU time 30.6 seconds
Started Jun 24 06:23:50 PM PDT 24
Finished Jun 24 06:24:21 PM PDT 24
Peak memory 182988 kb
Host smart-5d64069f-5b9b-4f1b-8ad4-a9b1125d51b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626026796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1626026796
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1738570871
Short name T367
Test name
Test status
Simulation time 344577677489 ps
CPU time 114.16 seconds
Started Jun 24 06:23:52 PM PDT 24
Finished Jun 24 06:25:46 PM PDT 24
Peak memory 182988 kb
Host smart-78faf7fb-8e3d-498a-b664-854c1f2ff31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738570871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1738570871
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3672681851
Short name T412
Test name
Test status
Simulation time 215582045451 ps
CPU time 607.88 seconds
Started Jun 24 06:23:50 PM PDT 24
Finished Jun 24 06:33:59 PM PDT 24
Peak memory 191176 kb
Host smart-b9b63ad3-181c-46e2-a8b0-99daf301cb4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672681851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3672681851
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1894593253
Short name T391
Test name
Test status
Simulation time 17552991476 ps
CPU time 169.57 seconds
Started Jun 24 06:23:50 PM PDT 24
Finished Jun 24 06:26:40 PM PDT 24
Peak memory 182952 kb
Host smart-d9c524d2-4938-49cf-bc10-4b591454dbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894593253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1894593253
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3186120899
Short name T446
Test name
Test status
Simulation time 220734529129 ps
CPU time 604.33 seconds
Started Jun 24 06:23:49 PM PDT 24
Finished Jun 24 06:33:53 PM PDT 24
Peak memory 191188 kb
Host smart-2d0d1de4-a89c-4026-a59d-5923707b56c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186120899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3186120899
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3928341583
Short name T37
Test name
Test status
Simulation time 13383499877 ps
CPU time 111.05 seconds
Started Jun 24 06:23:50 PM PDT 24
Finished Jun 24 06:25:42 PM PDT 24
Peak memory 197680 kb
Host smart-9c22baac-4d66-47ec-8f05-8dc348b7a5b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928341583 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3928341583
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2313606557
Short name T423
Test name
Test status
Simulation time 187219413108 ps
CPU time 153.29 seconds
Started Jun 24 06:23:48 PM PDT 24
Finished Jun 24 06:26:22 PM PDT 24
Peak memory 182960 kb
Host smart-f644622b-0c76-4517-ba1c-9b069041387e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313606557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2313606557
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1275904735
Short name T398
Test name
Test status
Simulation time 460127859887 ps
CPU time 190.06 seconds
Started Jun 24 06:23:50 PM PDT 24
Finished Jun 24 06:27:01 PM PDT 24
Peak memory 182960 kb
Host smart-c3199333-fa02-4d5d-849c-decf571b98c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275904735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1275904735
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3119696872
Short name T13
Test name
Test status
Simulation time 2374711585 ps
CPU time 15.32 seconds
Started Jun 24 06:23:49 PM PDT 24
Finished Jun 24 06:24:04 PM PDT 24
Peak memory 191180 kb
Host smart-878401ac-8b2a-43c8-aa2d-4d221b45c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119696872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3119696872
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.4195330318
Short name T227
Test name
Test status
Simulation time 962759419039 ps
CPU time 442.49 seconds
Started Jun 24 06:23:58 PM PDT 24
Finished Jun 24 06:31:20 PM PDT 24
Peak memory 182940 kb
Host smart-f071f6b7-e447-413d-9bc4-8479ccc122ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195330318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.4195330318
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.974623173
Short name T397
Test name
Test status
Simulation time 120784973020 ps
CPU time 41.57 seconds
Started Jun 24 06:23:58 PM PDT 24
Finished Jun 24 06:24:40 PM PDT 24
Peak memory 183004 kb
Host smart-2c644b04-23d8-4105-a90c-1331496f18b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974623173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.974623173
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1399661338
Short name T188
Test name
Test status
Simulation time 89461882209 ps
CPU time 470.27 seconds
Started Jun 24 06:23:58 PM PDT 24
Finished Jun 24 06:31:49 PM PDT 24
Peak memory 191156 kb
Host smart-331f6c10-6434-400c-aacc-8e9e8e9e77ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399661338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1399661338
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.644048030
Short name T399
Test name
Test status
Simulation time 449088155 ps
CPU time 1.05 seconds
Started Jun 24 06:23:59 PM PDT 24
Finished Jun 24 06:24:00 PM PDT 24
Peak memory 182940 kb
Host smart-f0b75564-d1eb-462e-8de6-469e3d4229d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644048030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.644048030
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3211148834
Short name T338
Test name
Test status
Simulation time 655310986154 ps
CPU time 1082.89 seconds
Started Jun 24 06:24:06 PM PDT 24
Finished Jun 24 06:42:09 PM PDT 24
Peak memory 182972 kb
Host smart-71f43ef9-87b8-47ba-8c01-5edf985ddb0e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211148834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3211148834
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.2942289810
Short name T1
Test name
Test status
Simulation time 154396603052 ps
CPU time 88.55 seconds
Started Jun 24 06:24:05 PM PDT 24
Finished Jun 24 06:25:34 PM PDT 24
Peak memory 191180 kb
Host smart-f34939ac-caa0-46c7-8e3b-fa911ca66237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942289810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2942289810
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3318431466
Short name T358
Test name
Test status
Simulation time 27896383 ps
CPU time 0.55 seconds
Started Jun 24 06:24:07 PM PDT 24
Finished Jun 24 06:24:08 PM PDT 24
Peak memory 182748 kb
Host smart-278afe52-a4b0-4f4d-8a35-586dd6070101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318431466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3318431466
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1377484925
Short name T50
Test name
Test status
Simulation time 206319290052 ps
CPU time 350.77 seconds
Started Jun 24 06:24:17 PM PDT 24
Finished Jun 24 06:30:08 PM PDT 24
Peak memory 182988 kb
Host smart-68350e8e-e191-4a51-96dc-281685e602e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377484925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1377484925
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4219576580
Short name T364
Test name
Test status
Simulation time 140632187274 ps
CPU time 204.85 seconds
Started Jun 24 06:24:15 PM PDT 24
Finished Jun 24 06:27:40 PM PDT 24
Peak memory 182984 kb
Host smart-21a1ba2d-79f4-459f-b887-ac478829dc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219576580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4219576580
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3446751118
Short name T191
Test name
Test status
Simulation time 256497280241 ps
CPU time 897.46 seconds
Started Jun 24 06:24:06 PM PDT 24
Finished Jun 24 06:39:04 PM PDT 24
Peak memory 191180 kb
Host smart-f70475dc-f692-4329-95d3-210d2afc8947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446751118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3446751118
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1548197453
Short name T117
Test name
Test status
Simulation time 268344817897 ps
CPU time 74.7 seconds
Started Jun 24 06:24:16 PM PDT 24
Finished Jun 24 06:25:31 PM PDT 24
Peak memory 192512 kb
Host smart-355c3c3c-7ef7-4038-b389-7685b79214fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548197453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1548197453
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1043937837
Short name T444
Test name
Test status
Simulation time 65094576428 ps
CPU time 47.56 seconds
Started Jun 24 06:24:16 PM PDT 24
Finished Jun 24 06:25:04 PM PDT 24
Peak memory 182972 kb
Host smart-4cca02ab-3d84-4434-8d5a-2462559ab62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043937837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1043937837
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2669780965
Short name T202
Test name
Test status
Simulation time 901100422594 ps
CPU time 464.58 seconds
Started Jun 24 06:24:15 PM PDT 24
Finished Jun 24 06:32:00 PM PDT 24
Peak memory 182964 kb
Host smart-3a7b6d86-e18d-432e-8bcb-d4fc5278d29c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669780965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2669780965
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1422729534
Short name T370
Test name
Test status
Simulation time 415799629549 ps
CPU time 165.23 seconds
Started Jun 24 06:24:15 PM PDT 24
Finished Jun 24 06:27:01 PM PDT 24
Peak memory 183000 kb
Host smart-2e6d9639-297d-4d8a-84e5-067e401e1ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422729534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1422729534
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3034347262
Short name T223
Test name
Test status
Simulation time 155877020633 ps
CPU time 269.62 seconds
Started Jun 24 06:24:16 PM PDT 24
Finished Jun 24 06:28:46 PM PDT 24
Peak memory 191148 kb
Host smart-333730e8-eb2a-47ba-9290-d4292615e3f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034347262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3034347262
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2196036237
Short name T193
Test name
Test status
Simulation time 100867279501 ps
CPU time 105.9 seconds
Started Jun 24 06:24:16 PM PDT 24
Finished Jun 24 06:26:02 PM PDT 24
Peak memory 191204 kb
Host smart-705bd2c4-9bec-40b2-b089-39359535bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196036237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2196036237
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1541960017
Short name T174
Test name
Test status
Simulation time 1875172172338 ps
CPU time 934.95 seconds
Started Jun 24 06:20:31 PM PDT 24
Finished Jun 24 06:36:07 PM PDT 24
Peak memory 182976 kb
Host smart-18a554f8-2f69-43b2-a480-9a607bfc00bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541960017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1541960017
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3168478576
Short name T357
Test name
Test status
Simulation time 104417159355 ps
CPU time 74.76 seconds
Started Jun 24 06:20:34 PM PDT 24
Finished Jun 24 06:21:50 PM PDT 24
Peak memory 182992 kb
Host smart-2d77cab5-f02f-466a-9b17-3b52558cf54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168478576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3168478576
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.968784646
Short name T126
Test name
Test status
Simulation time 130380517148 ps
CPU time 181.61 seconds
Started Jun 24 06:20:29 PM PDT 24
Finished Jun 24 06:23:31 PM PDT 24
Peak memory 191132 kb
Host smart-b710d8ba-16d8-4d82-b6b3-58b06d998e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968784646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.968784646
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.412942195
Short name T12
Test name
Test status
Simulation time 82827013742 ps
CPU time 401.91 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:27:13 PM PDT 24
Peak memory 191216 kb
Host smart-db499458-f3e0-4760-ac39-2f4f8cc6da5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412942195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.412942195
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.477107311
Short name T180
Test name
Test status
Simulation time 95941216492 ps
CPU time 472.09 seconds
Started Jun 24 06:24:24 PM PDT 24
Finished Jun 24 06:32:16 PM PDT 24
Peak memory 191184 kb
Host smart-2112ad40-ae17-4ae7-8a90-a2a361463670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477107311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.477107311
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2121468075
Short name T324
Test name
Test status
Simulation time 82488775004 ps
CPU time 146.07 seconds
Started Jun 24 06:24:25 PM PDT 24
Finished Jun 24 06:26:51 PM PDT 24
Peak memory 191196 kb
Host smart-fb522cef-3cc7-41bb-9a31-4357a00f41f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121468075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2121468075
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2720326529
Short name T430
Test name
Test status
Simulation time 137709141256 ps
CPU time 189.71 seconds
Started Jun 24 06:24:25 PM PDT 24
Finished Jun 24 06:27:35 PM PDT 24
Peak memory 191192 kb
Host smart-6f4110ab-c1de-4b1f-aaae-09d38a672804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720326529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2720326529
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1888611104
Short name T218
Test name
Test status
Simulation time 9818474651 ps
CPU time 16.71 seconds
Started Jun 24 06:24:25 PM PDT 24
Finished Jun 24 06:24:42 PM PDT 24
Peak memory 182988 kb
Host smart-a5b75deb-7ffb-4806-b2ea-6f40c00e6eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888611104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1888611104
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.167059603
Short name T301
Test name
Test status
Simulation time 308668208367 ps
CPU time 368.44 seconds
Started Jun 24 06:24:25 PM PDT 24
Finished Jun 24 06:30:34 PM PDT 24
Peak memory 191184 kb
Host smart-e2183236-a720-4d5d-b9b1-25223a3c31da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167059603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.167059603
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.37787606
Short name T353
Test name
Test status
Simulation time 115674367940 ps
CPU time 315.61 seconds
Started Jun 24 06:24:26 PM PDT 24
Finished Jun 24 06:29:42 PM PDT 24
Peak memory 191160 kb
Host smart-4b9253a4-3304-4abc-9626-ac40d3f0f6ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37787606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.37787606
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3205759213
Short name T286
Test name
Test status
Simulation time 100785844435 ps
CPU time 201.41 seconds
Started Jun 24 06:24:26 PM PDT 24
Finished Jun 24 06:27:48 PM PDT 24
Peak memory 191176 kb
Host smart-25640dbf-2624-494d-89cb-8e0cfe36c79d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205759213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3205759213
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2866849828
Short name T291
Test name
Test status
Simulation time 100396817397 ps
CPU time 109.63 seconds
Started Jun 24 06:24:25 PM PDT 24
Finished Jun 24 06:26:15 PM PDT 24
Peak memory 191192 kb
Host smart-7e559089-cfeb-4c0f-bf88-5532ec1d819c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866849828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2866849828
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3309538950
Short name T232
Test name
Test status
Simulation time 341110631623 ps
CPU time 81.16 seconds
Started Jun 24 06:24:32 PM PDT 24
Finished Jun 24 06:25:54 PM PDT 24
Peak memory 191072 kb
Host smart-faa2c21e-d9df-49ea-beda-784dcf10bde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309538950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3309538950
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1709591060
Short name T230
Test name
Test status
Simulation time 66607381388 ps
CPU time 67.13 seconds
Started Jun 24 06:24:34 PM PDT 24
Finished Jun 24 06:25:41 PM PDT 24
Peak memory 182984 kb
Host smart-884ff093-267f-443d-a1cc-d2dc40b74cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709591060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1709591060
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3546670191
Short name T186
Test name
Test status
Simulation time 113057024567 ps
CPU time 172.74 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:23:24 PM PDT 24
Peak memory 182984 kb
Host smart-25d46c2b-f465-4ee7-b2b1-21aa4c85fef2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546670191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3546670191
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4175275970
Short name T386
Test name
Test status
Simulation time 282091470789 ps
CPU time 221.65 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:24:13 PM PDT 24
Peak memory 183000 kb
Host smart-7dbeddba-8de3-4dc0-80a2-72a2b701a0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175275970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4175275970
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1326578796
Short name T243
Test name
Test status
Simulation time 84352083783 ps
CPU time 78.79 seconds
Started Jun 24 06:20:35 PM PDT 24
Finished Jun 24 06:21:54 PM PDT 24
Peak memory 191188 kb
Host smart-7800fbf3-c1d0-4db4-8e94-9766e31db9f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326578796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1326578796
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2971219878
Short name T262
Test name
Test status
Simulation time 62234497950 ps
CPU time 96.5 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:22:08 PM PDT 24
Peak memory 182912 kb
Host smart-39ea1550-fe19-47f5-9c19-201908fb2db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971219878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2971219878
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.988075121
Short name T361
Test name
Test status
Simulation time 269626548541 ps
CPU time 174.42 seconds
Started Jun 24 06:20:33 PM PDT 24
Finished Jun 24 06:23:28 PM PDT 24
Peak memory 182992 kb
Host smart-ac0eef51-7151-4161-b82f-a5c6220edeb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988075121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.988075121
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3604747857
Short name T143
Test name
Test status
Simulation time 901561946286 ps
CPU time 438.09 seconds
Started Jun 24 06:24:32 PM PDT 24
Finished Jun 24 06:31:51 PM PDT 24
Peak memory 191188 kb
Host smart-8ea0fae0-50b5-4ffe-a83a-784a568b1182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604747857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3604747857
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.4111148417
Short name T281
Test name
Test status
Simulation time 96120882502 ps
CPU time 1286.43 seconds
Started Jun 24 06:24:34 PM PDT 24
Finished Jun 24 06:46:01 PM PDT 24
Peak memory 191188 kb
Host smart-60807963-eead-4494-bc54-8d964f4f1f50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111148417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.4111148417
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2045266146
Short name T49
Test name
Test status
Simulation time 77241190153 ps
CPU time 124.31 seconds
Started Jun 24 06:24:35 PM PDT 24
Finished Jun 24 06:26:40 PM PDT 24
Peak memory 191172 kb
Host smart-d73a262e-cfeb-404d-8fb6-b9e6b3e0dbc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045266146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2045266146
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2122082831
Short name T123
Test name
Test status
Simulation time 135877782004 ps
CPU time 72.77 seconds
Started Jun 24 06:24:34 PM PDT 24
Finished Jun 24 06:25:47 PM PDT 24
Peak memory 182964 kb
Host smart-7cefd35b-e233-4ac5-8c97-8e69a3dfc36b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122082831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2122082831
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1450126886
Short name T3
Test name
Test status
Simulation time 36422158099 ps
CPU time 62.4 seconds
Started Jun 24 06:24:42 PM PDT 24
Finished Jun 24 06:25:45 PM PDT 24
Peak memory 182972 kb
Host smart-4545ac54-8a4c-47a9-8e01-074e70fb9642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450126886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1450126886
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1953466941
Short name T219
Test name
Test status
Simulation time 90344283396 ps
CPU time 1730.29 seconds
Started Jun 24 06:24:42 PM PDT 24
Finished Jun 24 06:53:34 PM PDT 24
Peak memory 182976 kb
Host smart-7ea77242-7419-48b4-b8f9-4c4a9d3c5f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953466941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1953466941
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.698108153
Short name T347
Test name
Test status
Simulation time 20363690136 ps
CPU time 37.14 seconds
Started Jun 24 06:24:43 PM PDT 24
Finished Jun 24 06:25:21 PM PDT 24
Peak memory 182996 kb
Host smart-210671d4-6aab-4aaf-a078-fe10c97829d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698108153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.698108153
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.492562499
Short name T249
Test name
Test status
Simulation time 510555689125 ps
CPU time 1152.67 seconds
Started Jun 24 06:24:43 PM PDT 24
Finished Jun 24 06:43:56 PM PDT 24
Peak memory 191172 kb
Host smart-7423c734-6f6b-46d1-992c-d6c237af4141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492562499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.492562499
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1748952736
Short name T159
Test name
Test status
Simulation time 457072051896 ps
CPU time 335.19 seconds
Started Jun 24 06:24:41 PM PDT 24
Finished Jun 24 06:30:17 PM PDT 24
Peak memory 194732 kb
Host smart-e57aa807-ba0e-40d2-941e-e6aee5cec843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748952736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1748952736
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.4087411412
Short name T288
Test name
Test status
Simulation time 238163970818 ps
CPU time 116 seconds
Started Jun 24 06:20:39 PM PDT 24
Finished Jun 24 06:22:36 PM PDT 24
Peak memory 182980 kb
Host smart-6c8325b0-89b7-43dd-a9cb-9d52ccf34d44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087411412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.4087411412
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1641641469
Short name T436
Test name
Test status
Simulation time 286861560536 ps
CPU time 210.16 seconds
Started Jun 24 06:20:40 PM PDT 24
Finished Jun 24 06:24:11 PM PDT 24
Peak memory 182996 kb
Host smart-bf8e8971-c67d-4183-b116-45063e0a3e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641641469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1641641469
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1011296857
Short name T116
Test name
Test status
Simulation time 273027783095 ps
CPU time 303.43 seconds
Started Jun 24 06:20:30 PM PDT 24
Finished Jun 24 06:25:35 PM PDT 24
Peak memory 191168 kb
Host smart-f571a497-644f-42e9-a415-2769d97a42a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011296857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1011296857
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1613757889
Short name T294
Test name
Test status
Simulation time 2082513650 ps
CPU time 4.18 seconds
Started Jun 24 06:20:39 PM PDT 24
Finished Jun 24 06:20:44 PM PDT 24
Peak memory 182920 kb
Host smart-69a5dab1-6961-4e9e-b962-7f7c744045aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613757889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1613757889
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2136750196
Short name T329
Test name
Test status
Simulation time 1294067506715 ps
CPU time 834.05 seconds
Started Jun 24 06:20:40 PM PDT 24
Finished Jun 24 06:34:35 PM PDT 24
Peak memory 195960 kb
Host smart-22993568-f3dc-49d9-9dae-a74805452f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136750196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2136750196
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1615535687
Short name T14
Test name
Test status
Simulation time 49696242167 ps
CPU time 203.61 seconds
Started Jun 24 06:20:40 PM PDT 24
Finished Jun 24 06:24:04 PM PDT 24
Peak memory 197732 kb
Host smart-5437a0e3-acb3-44cc-8080-c5a6156c21e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615535687 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1615535687
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.3746482373
Short name T355
Test name
Test status
Simulation time 749496198920 ps
CPU time 1131.78 seconds
Started Jun 24 06:24:43 PM PDT 24
Finished Jun 24 06:43:36 PM PDT 24
Peak memory 191152 kb
Host smart-77f83253-0ece-428c-a8c2-9e025c2665bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746482373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3746482373
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3424846451
Short name T109
Test name
Test status
Simulation time 118164381114 ps
CPU time 284.13 seconds
Started Jun 24 06:24:45 PM PDT 24
Finished Jun 24 06:29:29 PM PDT 24
Peak memory 191164 kb
Host smart-6debdc67-0005-456f-a5ce-5a046fc9f27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424846451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3424846451
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3718006905
Short name T65
Test name
Test status
Simulation time 8955111347 ps
CPU time 13.98 seconds
Started Jun 24 06:24:44 PM PDT 24
Finished Jun 24 06:24:59 PM PDT 24
Peak memory 182988 kb
Host smart-43056481-a55d-4bba-a8f7-55103180612b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718006905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3718006905
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3685983081
Short name T268
Test name
Test status
Simulation time 230339398091 ps
CPU time 231.27 seconds
Started Jun 24 06:24:46 PM PDT 24
Finished Jun 24 06:28:38 PM PDT 24
Peak memory 191192 kb
Host smart-7a0c301e-22b7-4287-b6d3-1377feb5b14b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685983081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3685983081
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4099046328
Short name T349
Test name
Test status
Simulation time 158967478557 ps
CPU time 133.91 seconds
Started Jun 24 06:24:53 PM PDT 24
Finished Jun 24 06:27:08 PM PDT 24
Peak memory 194684 kb
Host smart-e51b6a4b-7d34-47a1-9c56-1a78b31eff1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099046328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4099046328
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2668075714
Short name T246
Test name
Test status
Simulation time 183047133083 ps
CPU time 32.76 seconds
Started Jun 24 06:24:53 PM PDT 24
Finished Jun 24 06:25:27 PM PDT 24
Peak memory 182976 kb
Host smart-d33e85ed-63eb-4348-8f58-407ab520f11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668075714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2668075714
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3364887767
Short name T264
Test name
Test status
Simulation time 205498847115 ps
CPU time 932.57 seconds
Started Jun 24 06:24:53 PM PDT 24
Finished Jun 24 06:40:27 PM PDT 24
Peak memory 191172 kb
Host smart-b1b66714-bbc1-4882-95f1-5c57485b32c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364887767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3364887767
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.484806920
Short name T447
Test name
Test status
Simulation time 244476011385 ps
CPU time 172.85 seconds
Started Jun 24 06:24:55 PM PDT 24
Finished Jun 24 06:27:48 PM PDT 24
Peak memory 193428 kb
Host smart-6947db38-e7c5-4030-bbdd-c77610b0eebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484806920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.484806920
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2629216863
Short name T392
Test name
Test status
Simulation time 55525006215 ps
CPU time 42.42 seconds
Started Jun 24 06:20:41 PM PDT 24
Finished Jun 24 06:21:25 PM PDT 24
Peak memory 183000 kb
Host smart-c467c6e4-1526-404c-b268-ea6c44972266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629216863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2629216863
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1853616241
Short name T279
Test name
Test status
Simulation time 873933798707 ps
CPU time 162.47 seconds
Started Jun 24 06:20:41 PM PDT 24
Finished Jun 24 06:23:24 PM PDT 24
Peak memory 191188 kb
Host smart-a7879a77-4b86-471c-8d96-9f6bf03b1522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853616241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1853616241
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.4221676126
Short name T131
Test name
Test status
Simulation time 189569949685 ps
CPU time 227.68 seconds
Started Jun 24 06:20:40 PM PDT 24
Finished Jun 24 06:24:29 PM PDT 24
Peak memory 183000 kb
Host smart-3f73c918-ada6-4be7-98e0-a4ce748bc919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221676126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.4221676126
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.4027892881
Short name T199
Test name
Test status
Simulation time 392295073422 ps
CPU time 903.84 seconds
Started Jun 24 06:20:39 PM PDT 24
Finished Jun 24 06:35:44 PM PDT 24
Peak memory 210308 kb
Host smart-5a6c4661-c9c1-40a8-9d79-190e49160ca1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027892881 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.4027892881
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.626546787
Short name T118
Test name
Test status
Simulation time 55618615007 ps
CPU time 303.77 seconds
Started Jun 24 06:24:52 PM PDT 24
Finished Jun 24 06:29:56 PM PDT 24
Peak memory 191200 kb
Host smart-e05de1be-5bed-4eab-b012-f6fb3363a64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626546787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.626546787
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.542445011
Short name T160
Test name
Test status
Simulation time 244487079483 ps
CPU time 2202.43 seconds
Started Jun 24 06:24:53 PM PDT 24
Finished Jun 24 07:01:36 PM PDT 24
Peak memory 191148 kb
Host smart-d330c93d-fec1-451c-b57d-25ec7860fe5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542445011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.542445011
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2658379641
Short name T351
Test name
Test status
Simulation time 1320694920044 ps
CPU time 285.42 seconds
Started Jun 24 06:24:52 PM PDT 24
Finished Jun 24 06:29:38 PM PDT 24
Peak memory 193488 kb
Host smart-2b7eb4f2-1301-4a4e-86d4-6c099fe89d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658379641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2658379641
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.393847889
Short name T150
Test name
Test status
Simulation time 1449532553397 ps
CPU time 461.17 seconds
Started Jun 24 06:24:53 PM PDT 24
Finished Jun 24 06:32:35 PM PDT 24
Peak memory 191180 kb
Host smart-c80bd41c-8791-4622-93c6-7384e940ff70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393847889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.393847889
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1184628439
Short name T341
Test name
Test status
Simulation time 224399478575 ps
CPU time 390.43 seconds
Started Jun 24 06:25:03 PM PDT 24
Finished Jun 24 06:31:34 PM PDT 24
Peak memory 182928 kb
Host smart-96359f1b-e9b2-4949-9ba9-612948551fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184628439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1184628439
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.519500664
Short name T231
Test name
Test status
Simulation time 184419254857 ps
CPU time 462.8 seconds
Started Jun 24 06:25:01 PM PDT 24
Finished Jun 24 06:32:45 PM PDT 24
Peak memory 191172 kb
Host smart-e3a28f23-f03b-4391-af9f-5533e63030db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519500664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.519500664
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3457690392
Short name T277
Test name
Test status
Simulation time 1837565915878 ps
CPU time 1139.53 seconds
Started Jun 24 06:25:00 PM PDT 24
Finished Jun 24 06:44:00 PM PDT 24
Peak memory 191420 kb
Host smart-5b4783d0-f302-42fc-9be6-4d859f16de6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457690392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3457690392
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4074511943
Short name T247
Test name
Test status
Simulation time 69979033617 ps
CPU time 44.26 seconds
Started Jun 24 06:25:02 PM PDT 24
Finished Jun 24 06:25:47 PM PDT 24
Peak memory 182932 kb
Host smart-c6ce0956-6383-412a-a9ad-c2502785337d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074511943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4074511943
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2062968818
Short name T313
Test name
Test status
Simulation time 177377099669 ps
CPU time 273.92 seconds
Started Jun 24 06:20:39 PM PDT 24
Finished Jun 24 06:25:13 PM PDT 24
Peak memory 182968 kb
Host smart-2173545c-1e76-4b2a-9c2e-43ecf757f310
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062968818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2062968818
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2562919563
Short name T369
Test name
Test status
Simulation time 212766229914 ps
CPU time 272.72 seconds
Started Jun 24 06:20:41 PM PDT 24
Finished Jun 24 06:25:14 PM PDT 24
Peak memory 182988 kb
Host smart-88e6a984-cf1b-4628-920d-b3ca80887199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562919563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2562919563
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2858041492
Short name T448
Test name
Test status
Simulation time 256994024 ps
CPU time 0.6 seconds
Started Jun 24 06:20:41 PM PDT 24
Finished Jun 24 06:20:42 PM PDT 24
Peak memory 182940 kb
Host smart-4920c9bc-63f9-47cc-a101-286cc0e0be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858041492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2858041492
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2922713967
Short name T35
Test name
Test status
Simulation time 277206268358 ps
CPU time 447.24 seconds
Started Jun 24 06:20:38 PM PDT 24
Finished Jun 24 06:28:06 PM PDT 24
Peak memory 195300 kb
Host smart-2df624c1-4927-4a20-8d67-aa847e2ff235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922713967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2922713967
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.3449717867
Short name T205
Test name
Test status
Simulation time 580734130452 ps
CPU time 238.69 seconds
Started Jun 24 06:25:01 PM PDT 24
Finished Jun 24 06:29:01 PM PDT 24
Peak memory 191184 kb
Host smart-9a6d0d4d-b8a9-4a49-96db-57ca175372f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449717867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3449717867
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3929796000
Short name T233
Test name
Test status
Simulation time 474977921816 ps
CPU time 1675.18 seconds
Started Jun 24 06:25:02 PM PDT 24
Finished Jun 24 06:52:58 PM PDT 24
Peak memory 194752 kb
Host smart-3bff5f6d-00d2-4b05-ad6e-376a8d20c5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929796000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3929796000
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.993553531
Short name T245
Test name
Test status
Simulation time 321276131381 ps
CPU time 144.41 seconds
Started Jun 24 06:25:01 PM PDT 24
Finished Jun 24 06:27:26 PM PDT 24
Peak memory 191180 kb
Host smart-6d4eb7bb-b17c-43fb-abf9-8c8128fee689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993553531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.993553531
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3892435863
Short name T190
Test name
Test status
Simulation time 3853791924 ps
CPU time 3.67 seconds
Started Jun 24 06:25:00 PM PDT 24
Finished Jun 24 06:25:05 PM PDT 24
Peak memory 183008 kb
Host smart-b8500612-8e90-4bd9-b3da-1c5b09a323b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892435863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3892435863
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3007227431
Short name T236
Test name
Test status
Simulation time 410103280766 ps
CPU time 209.07 seconds
Started Jun 24 06:25:10 PM PDT 24
Finished Jun 24 06:28:40 PM PDT 24
Peak memory 191416 kb
Host smart-ecbb62bf-5afa-42ca-8b18-8d626ae31e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007227431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3007227431
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3432117947
Short name T184
Test name
Test status
Simulation time 1086340457293 ps
CPU time 728.06 seconds
Started Jun 24 06:25:10 PM PDT 24
Finished Jun 24 06:37:18 PM PDT 24
Peak memory 191180 kb
Host smart-8d4ed275-bba6-4e8d-bb16-0bea292a28b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432117947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3432117947
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3468563607
Short name T120
Test name
Test status
Simulation time 93240120645 ps
CPU time 166.91 seconds
Started Jun 24 06:25:09 PM PDT 24
Finished Jun 24 06:27:56 PM PDT 24
Peak memory 191184 kb
Host smart-a42449f7-c469-402b-ab2b-f95da0928b30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468563607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3468563607
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.98242063
Short name T23
Test name
Test status
Simulation time 238161561676 ps
CPU time 166.96 seconds
Started Jun 24 06:25:10 PM PDT 24
Finished Jun 24 06:27:58 PM PDT 24
Peak memory 191180 kb
Host smart-f00b5e28-3ddd-402b-aa1e-4d7ab51c375d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98242063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.98242063
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.490823018
Short name T8
Test name
Test status
Simulation time 638300717835 ps
CPU time 395.15 seconds
Started Jun 24 06:25:09 PM PDT 24
Finished Jun 24 06:31:45 PM PDT 24
Peak memory 191180 kb
Host smart-8d4a9b69-8551-432b-81a0-c9cde72399b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490823018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.490823018
Directory /workspace/99.rv_timer_random/latest
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