Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
119085905 |
1 |
|
T1 |
8921 |
|
T2 |
138013 |
|
T3 |
28245 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
63199420 |
1 |
|
T1 |
2501 |
|
T2 |
130808 |
|
T3 |
22855 |
auto[1] |
55886485 |
1 |
|
T1 |
6420 |
|
T2 |
7205 |
|
T3 |
5390 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
119079799 |
1 |
|
T1 |
8808 |
|
T2 |
138007 |
|
T3 |
28237 |
auto[1] |
6106 |
1 |
|
T1 |
113 |
|
T2 |
6 |
|
T3 |
8 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
63196390 |
1 |
|
T1 |
2446 |
|
T2 |
130806 |
|
T3 |
22849 |
all_values[0] |
auto[0] |
auto[1] |
3030 |
1 |
|
T1 |
55 |
|
T2 |
2 |
|
T3 |
6 |
all_values[0] |
auto[1] |
auto[0] |
55883409 |
1 |
|
T1 |
6362 |
|
T2 |
7201 |
|
T3 |
5388 |
all_values[0] |
auto[1] |
auto[1] |
3076 |
1 |
|
T1 |
58 |
|
T2 |
4 |
|
T3 |
2 |