Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.53 99.36 98.73 100.00 100.00 100.00 99.09


Total test records in report: 583
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1020406334 Jun 25 05:41:52 PM PDT 24 Jun 25 05:41:54 PM PDT 24 22110187 ps
T510 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.990355089 Jun 25 05:42:09 PM PDT 24 Jun 25 05:42:12 PM PDT 24 31219334 ps
T511 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4099788098 Jun 25 05:42:07 PM PDT 24 Jun 25 05:42:11 PM PDT 24 279173078 ps
T94 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1373997153 Jun 25 05:41:57 PM PDT 24 Jun 25 05:41:59 PM PDT 24 18566255 ps
T512 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3686302146 Jun 25 05:41:59 PM PDT 24 Jun 25 05:42:04 PM PDT 24 41076389 ps
T513 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1588716515 Jun 25 05:42:09 PM PDT 24 Jun 25 05:42:13 PM PDT 24 24078399 ps
T514 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2709042065 Jun 25 05:42:08 PM PDT 24 Jun 25 05:42:10 PM PDT 24 63504461 ps
T515 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3528648212 Jun 25 05:41:49 PM PDT 24 Jun 25 05:41:53 PM PDT 24 36819554 ps
T516 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1176483401 Jun 25 05:41:55 PM PDT 24 Jun 25 05:41:58 PM PDT 24 584798859 ps
T517 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3957053098 Jun 25 05:41:50 PM PDT 24 Jun 25 05:41:54 PM PDT 24 575292268 ps
T518 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.750648232 Jun 25 05:42:07 PM PDT 24 Jun 25 05:42:10 PM PDT 24 219689174 ps
T519 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3841687204 Jun 25 05:42:02 PM PDT 24 Jun 25 05:42:06 PM PDT 24 40827864 ps
T520 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.158485060 Jun 25 05:41:49 PM PDT 24 Jun 25 05:41:55 PM PDT 24 697676051 ps
T521 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.52243955 Jun 25 05:42:05 PM PDT 24 Jun 25 05:42:09 PM PDT 24 303111288 ps
T522 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4286344741 Jun 25 05:42:10 PM PDT 24 Jun 25 05:42:13 PM PDT 24 33947258 ps
T523 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.705810100 Jun 25 05:42:11 PM PDT 24 Jun 25 05:42:14 PM PDT 24 11253507 ps
T524 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3663778729 Jun 25 05:41:59 PM PDT 24 Jun 25 05:42:02 PM PDT 24 39012369 ps
T525 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2207891766 Jun 25 05:42:10 PM PDT 24 Jun 25 05:42:14 PM PDT 24 166408043 ps
T526 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3171892200 Jun 25 05:41:51 PM PDT 24 Jun 25 05:41:54 PM PDT 24 171098722 ps
T527 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.296621611 Jun 25 05:42:06 PM PDT 24 Jun 25 05:42:09 PM PDT 24 86406103 ps
T528 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3836677357 Jun 25 05:42:05 PM PDT 24 Jun 25 05:42:08 PM PDT 24 137522824 ps
T529 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.363059154 Jun 25 05:42:07 PM PDT 24 Jun 25 05:42:09 PM PDT 24 200245360 ps
T530 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3927124513 Jun 25 05:41:50 PM PDT 24 Jun 25 05:41:53 PM PDT 24 75573275 ps
T531 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3037815129 Jun 25 05:42:00 PM PDT 24 Jun 25 05:42:03 PM PDT 24 19695468 ps
T532 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2143410834 Jun 25 05:41:57 PM PDT 24 Jun 25 05:41:58 PM PDT 24 50408239 ps
T533 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4218019985 Jun 25 05:42:09 PM PDT 24 Jun 25 05:42:11 PM PDT 24 79510502 ps
T534 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1758251280 Jun 25 05:42:01 PM PDT 24 Jun 25 05:42:04 PM PDT 24 29074440 ps
T535 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1938317948 Jun 25 05:42:15 PM PDT 24 Jun 25 05:42:16 PM PDT 24 33739373 ps
T536 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3365467665 Jun 25 05:42:11 PM PDT 24 Jun 25 05:42:14 PM PDT 24 46968910 ps
T95 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.759849444 Jun 25 05:41:55 PM PDT 24 Jun 25 05:41:57 PM PDT 24 33557670 ps
T537 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3153531460 Jun 25 05:42:03 PM PDT 24 Jun 25 05:42:06 PM PDT 24 22138210 ps
T538 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4284028401 Jun 25 05:42:08 PM PDT 24 Jun 25 05:42:11 PM PDT 24 69940645 ps
T539 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.730820530 Jun 25 05:42:00 PM PDT 24 Jun 25 05:42:03 PM PDT 24 17673316 ps
T540 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1121053762 Jun 25 05:41:57 PM PDT 24 Jun 25 05:41:59 PM PDT 24 11791031 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4266653679 Jun 25 05:42:01 PM PDT 24 Jun 25 05:42:04 PM PDT 24 27916200 ps
T542 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.32956781 Jun 25 05:41:48 PM PDT 24 Jun 25 05:41:52 PM PDT 24 21463793 ps
T543 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2866174562 Jun 25 05:42:06 PM PDT 24 Jun 25 05:42:08 PM PDT 24 33684704 ps
T544 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4267179159 Jun 25 05:41:50 PM PDT 24 Jun 25 05:41:54 PM PDT 24 14549666 ps
T545 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3449334878 Jun 25 05:41:57 PM PDT 24 Jun 25 05:41:59 PM PDT 24 183071136 ps
T546 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4245406116 Jun 25 05:42:10 PM PDT 24 Jun 25 05:42:14 PM PDT 24 34702544 ps
T96 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2919657090 Jun 25 05:41:52 PM PDT 24 Jun 25 05:41:54 PM PDT 24 59986455 ps
T547 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1338168414 Jun 25 05:42:08 PM PDT 24 Jun 25 05:42:11 PM PDT 24 44303009 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2726916401 Jun 25 05:41:53 PM PDT 24 Jun 25 05:41:55 PM PDT 24 17714731 ps
T549 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1698528665 Jun 25 05:41:58 PM PDT 24 Jun 25 05:42:01 PM PDT 24 26883643 ps
T550 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3019481092 Jun 25 05:41:59 PM PDT 24 Jun 25 05:42:02 PM PDT 24 137686061 ps
T551 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3829971268 Jun 25 05:42:01 PM PDT 24 Jun 25 05:42:05 PM PDT 24 336514707 ps
T552 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2587769904 Jun 25 05:42:04 PM PDT 24 Jun 25 05:42:08 PM PDT 24 82243298 ps
T553 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2965033556 Jun 25 05:42:00 PM PDT 24 Jun 25 05:42:04 PM PDT 24 221878009 ps
T554 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.679884684 Jun 25 05:42:10 PM PDT 24 Jun 25 05:42:13 PM PDT 24 46423213 ps
T555 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.723364661 Jun 25 05:42:05 PM PDT 24 Jun 25 05:42:08 PM PDT 24 76838885 ps
T556 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.375328664 Jun 25 05:42:09 PM PDT 24 Jun 25 05:42:12 PM PDT 24 32898394 ps
T98 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.862213416 Jun 25 05:41:55 PM PDT 24 Jun 25 05:41:57 PM PDT 24 13880630 ps
T557 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.563544305 Jun 25 05:41:58 PM PDT 24 Jun 25 05:42:00 PM PDT 24 21353393 ps
T558 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4025786481 Jun 25 05:42:04 PM PDT 24 Jun 25 05:42:08 PM PDT 24 133994216 ps
T559 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2484666109 Jun 25 05:42:07 PM PDT 24 Jun 25 05:42:10 PM PDT 24 485840056 ps
T560 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3615026781 Jun 25 05:42:05 PM PDT 24 Jun 25 05:42:09 PM PDT 24 90202300 ps
T561 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.739936134 Jun 25 05:42:05 PM PDT 24 Jun 25 05:42:08 PM PDT 24 243739460 ps
T562 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2845266454 Jun 25 05:42:09 PM PDT 24 Jun 25 05:42:11 PM PDT 24 54384904 ps
T563 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.89621807 Jun 25 05:42:04 PM PDT 24 Jun 25 05:42:07 PM PDT 24 39884399 ps
T564 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1746974530 Jun 25 05:42:08 PM PDT 24 Jun 25 05:42:10 PM PDT 24 19229495 ps
T97 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2949648042 Jun 25 05:42:05 PM PDT 24 Jun 25 05:42:08 PM PDT 24 24530762 ps
T565 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3910699632 Jun 25 05:41:56 PM PDT 24 Jun 25 05:41:58 PM PDT 24 17314497 ps
T566 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3908507490 Jun 25 05:42:00 PM PDT 24 Jun 25 05:42:04 PM PDT 24 33145497 ps
T567 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2162073211 Jun 25 05:42:01 PM PDT 24 Jun 25 05:42:04 PM PDT 24 136535408 ps
T568 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2427509562 Jun 25 05:42:10 PM PDT 24 Jun 25 05:42:13 PM PDT 24 14070613 ps
T569 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3098416855 Jun 25 05:41:54 PM PDT 24 Jun 25 05:41:57 PM PDT 24 88502706 ps
T570 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.315906325 Jun 25 05:42:07 PM PDT 24 Jun 25 05:42:10 PM PDT 24 14968336 ps
T571 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.954429770 Jun 25 05:42:09 PM PDT 24 Jun 25 05:42:12 PM PDT 24 15633599 ps
T572 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.315806298 Jun 25 05:42:11 PM PDT 24 Jun 25 05:42:14 PM PDT 24 30184679 ps
T573 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4206132710 Jun 25 05:42:08 PM PDT 24 Jun 25 05:42:11 PM PDT 24 39695454 ps
T574 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1165138461 Jun 25 05:41:58 PM PDT 24 Jun 25 05:42:01 PM PDT 24 57833044 ps
T575 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4102092042 Jun 25 05:42:09 PM PDT 24 Jun 25 05:42:12 PM PDT 24 135192162 ps
T576 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.915994784 Jun 25 05:41:56 PM PDT 24 Jun 25 05:42:00 PM PDT 24 85852845 ps
T99 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2663901990 Jun 25 05:42:03 PM PDT 24 Jun 25 05:42:06 PM PDT 24 63646542 ps
T101 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3305599095 Jun 25 05:41:58 PM PDT 24 Jun 25 05:42:01 PM PDT 24 30202739 ps
T577 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.150491748 Jun 25 05:41:51 PM PDT 24 Jun 25 05:41:54 PM PDT 24 54306541 ps
T100 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1799625374 Jun 25 05:41:55 PM PDT 24 Jun 25 05:41:59 PM PDT 24 241093679 ps
T578 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1390046015 Jun 25 05:42:00 PM PDT 24 Jun 25 05:42:03 PM PDT 24 12600908 ps
T579 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2703397336 Jun 25 05:42:01 PM PDT 24 Jun 25 05:42:05 PM PDT 24 26777475 ps
T580 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3824189152 Jun 25 05:41:56 PM PDT 24 Jun 25 05:41:58 PM PDT 24 20846574 ps
T581 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1099211369 Jun 25 05:42:02 PM PDT 24 Jun 25 05:42:07 PM PDT 24 352952121 ps
T582 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1602659867 Jun 25 05:41:57 PM PDT 24 Jun 25 05:42:00 PM PDT 24 56746012 ps
T583 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2822495916 Jun 25 05:42:13 PM PDT 24 Jun 25 05:42:15 PM PDT 24 44324550 ps

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1168940067
Short name T1
Test name
Test status
Simulation time 91838616259 ps
CPU time 960.8 seconds
Started Jun 25 05:42:40 PM PDT 24
Finished Jun 25 05:58:41 PM PDT 24
Peak memory 207952 kb
Host smart-8f3b8381-2d97-4649-aa45-235a1c46e148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168940067 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1168940067
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.3934118377
Short name T5
Test name
Test status
Simulation time 217749539244 ps
CPU time 333.4 seconds
Started Jun 25 05:43:50 PM PDT 24
Finished Jun 25 05:49:25 PM PDT 24
Peak memory 191348 kb
Host smart-4f7e328f-a637-4c64-9cd2-b48cb434d728
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934118377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3934118377
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.4024444397
Short name T11
Test name
Test status
Simulation time 3657152934284 ps
CPU time 1650.48 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 06:10:31 PM PDT 24
Peak memory 191352 kb
Host smart-ec1863aa-7958-4633-a286-75269f893c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024444397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.4024444397
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.933324808
Short name T29
Test name
Test status
Simulation time 476356460 ps
CPU time 1.15 seconds
Started Jun 25 05:41:51 PM PDT 24
Finished Jun 25 05:41:55 PM PDT 24
Peak memory 182720 kb
Host smart-105ae971-43e4-4c23-b716-ee3a1dd19e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933324808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.933324808
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.4266037388
Short name T256
Test name
Test status
Simulation time 962057305550 ps
CPU time 3372.35 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 06:39:13 PM PDT 24
Peak memory 191352 kb
Host smart-9c835d09-010e-4ccf-b428-99e1cba0c1da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266037388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.4266037388
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3773571543
Short name T62
Test name
Test status
Simulation time 763316527098 ps
CPU time 2089.65 seconds
Started Jun 25 05:42:46 PM PDT 24
Finished Jun 25 06:17:37 PM PDT 24
Peak memory 191224 kb
Host smart-adea2ede-1cf6-4195-82d8-d20bc0c1227c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773571543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3773571543
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1681236791
Short name T138
Test name
Test status
Simulation time 1281303962225 ps
CPU time 1138 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 06:01:52 PM PDT 24
Peak memory 191320 kb
Host smart-69a1d74d-e668-4a6b-8dd1-4ba4e1d85256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681236791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1681236791
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3029376946
Short name T49
Test name
Test status
Simulation time 1127219415627 ps
CPU time 1754.72 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 06:12:15 PM PDT 24
Peak memory 196092 kb
Host smart-a38f158b-3c7a-43be-8376-5c4388d46996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029376946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3029376946
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2684573069
Short name T170
Test name
Test status
Simulation time 574215677086 ps
CPU time 863.54 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 05:57:09 PM PDT 24
Peak memory 191324 kb
Host smart-ed0dd037-3381-4212-b684-f2fdc50a2829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684573069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2684573069
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.399809809
Short name T198
Test name
Test status
Simulation time 910122090046 ps
CPU time 2119.67 seconds
Started Jun 25 05:42:46 PM PDT 24
Finished Jun 25 06:18:07 PM PDT 24
Peak memory 191360 kb
Host smart-1771f6f9-569b-4712-937c-3049b0c37bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399809809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
399809809
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4032229199
Short name T88
Test name
Test status
Simulation time 31339011 ps
CPU time 0.62 seconds
Started Jun 25 05:42:03 PM PDT 24
Finished Jun 25 05:42:07 PM PDT 24
Peak memory 182268 kb
Host smart-5b02854d-2761-476f-b065-44cded0c3019
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032229199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4032229199
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/81.rv_timer_random.1845375505
Short name T147
Test name
Test status
Simulation time 151870514671 ps
CPU time 694.26 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 05:54:35 PM PDT 24
Peak memory 191320 kb
Host smart-4a3d2be8-3a7b-4080-828d-35f1d8b9a697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845375505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1845375505
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3315514246
Short name T175
Test name
Test status
Simulation time 1969337464434 ps
CPU time 1266.01 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 06:03:51 PM PDT 24
Peak memory 191340 kb
Host smart-affa8afb-e42e-486b-9f89-8fe9eaccd352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315514246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3315514246
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3384331189
Short name T18
Test name
Test status
Simulation time 44835143 ps
CPU time 0.8 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:13 PM PDT 24
Peak memory 213388 kb
Host smart-bfa1c603-dccd-4b8a-8323-706d175deaa0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384331189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3384331189
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3925677366
Short name T26
Test name
Test status
Simulation time 1187167018154 ps
CPU time 1334.27 seconds
Started Jun 25 05:42:37 PM PDT 24
Finished Jun 25 06:04:52 PM PDT 24
Peak memory 191348 kb
Host smart-93337861-b330-4dee-a7b7-899abfac7c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925677366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3925677366
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1585769303
Short name T45
Test name
Test status
Simulation time 142120713 ps
CPU time 0.83 seconds
Started Jun 25 05:42:02 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 191280 kb
Host smart-57749fb0-1314-4835-a124-7714c5cf094f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585769303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1585769303
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/176.rv_timer_random.3259262336
Short name T205
Test name
Test status
Simulation time 842130908772 ps
CPU time 1839.34 seconds
Started Jun 25 05:44:08 PM PDT 24
Finished Jun 25 06:14:48 PM PDT 24
Peak memory 191308 kb
Host smart-c25891a7-cde2-4184-9009-22b1c3943845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259262336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3259262336
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2240008815
Short name T219
Test name
Test status
Simulation time 348943861120 ps
CPU time 2715.83 seconds
Started Jun 25 05:44:13 PM PDT 24
Finished Jun 25 06:29:29 PM PDT 24
Peak memory 191340 kb
Host smart-c54ed777-8acb-43e4-be3d-dbc0647b39c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240008815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2240008815
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.458506461
Short name T260
Test name
Test status
Simulation time 1963610590768 ps
CPU time 1133.15 seconds
Started Jun 25 05:42:53 PM PDT 24
Finished Jun 25 06:01:48 PM PDT 24
Peak memory 191284 kb
Host smart-e751ee82-29a1-4a84-a072-49562903890f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458506461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
458506461
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.758712512
Short name T65
Test name
Test status
Simulation time 732635831057 ps
CPU time 1403.2 seconds
Started Jun 25 05:42:37 PM PDT 24
Finished Jun 25 06:06:01 PM PDT 24
Peak memory 191576 kb
Host smart-416f3277-3a7b-47ff-a589-e7d6918e9e40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758712512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.758712512
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1565719676
Short name T266
Test name
Test status
Simulation time 1855548510004 ps
CPU time 2234.61 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 06:19:33 PM PDT 24
Peak memory 191248 kb
Host smart-717bde35-7536-4551-af87-5e5f483c74b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565719676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1565719676
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2786022140
Short name T359
Test name
Test status
Simulation time 2279494579798 ps
CPU time 2120.4 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 06:17:55 PM PDT 24
Peak memory 191332 kb
Host smart-4edc0961-0f8a-457e-a870-84ce5a33528b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786022140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2786022140
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3670128205
Short name T66
Test name
Test status
Simulation time 767223353414 ps
CPU time 846.48 seconds
Started Jun 25 05:42:25 PM PDT 24
Finished Jun 25 05:56:33 PM PDT 24
Peak memory 191096 kb
Host smart-a6af77f9-ed77-48a0-b0dd-bbc108c8b006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670128205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3670128205
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2249437028
Short name T201
Test name
Test status
Simulation time 465976178700 ps
CPU time 494.29 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:51:17 PM PDT 24
Peak memory 191336 kb
Host smart-87ea0b44-72fb-447c-a34e-6dd351d82d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249437028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2249437028
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3778886193
Short name T135
Test name
Test status
Simulation time 138383316654 ps
CPU time 322.47 seconds
Started Jun 25 05:43:22 PM PDT 24
Finished Jun 25 05:48:45 PM PDT 24
Peak memory 191332 kb
Host smart-5da15f25-49f2-4734-b31c-780ea9df9a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778886193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3778886193
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.24045676
Short name T122
Test name
Test status
Simulation time 151871575322 ps
CPU time 730.55 seconds
Started Jun 25 05:43:31 PM PDT 24
Finished Jun 25 05:55:43 PM PDT 24
Peak memory 191356 kb
Host smart-82cdc18b-6a8d-4d0b-bef9-7239c34c0381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24045676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.24045676
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.942931189
Short name T264
Test name
Test status
Simulation time 237278186791 ps
CPU time 504.77 seconds
Started Jun 25 05:43:41 PM PDT 24
Finished Jun 25 05:52:06 PM PDT 24
Peak memory 191336 kb
Host smart-5b88debb-8d94-4f33-83cd-d3b366661174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942931189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.942931189
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.4174897171
Short name T304
Test name
Test status
Simulation time 381919273655 ps
CPU time 567.2 seconds
Started Jun 25 05:43:57 PM PDT 24
Finished Jun 25 05:53:25 PM PDT 24
Peak memory 191348 kb
Host smart-18424aba-f70d-4887-99b1-42380df3cb2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174897171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.4174897171
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2067766061
Short name T63
Test name
Test status
Simulation time 207110915567 ps
CPU time 549.61 seconds
Started Jun 25 05:42:19 PM PDT 24
Finished Jun 25 05:51:29 PM PDT 24
Peak memory 191320 kb
Host smart-a25e1ff7-005d-4384-8204-83b31a7edd9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067766061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2067766061
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2417480583
Short name T51
Test name
Test status
Simulation time 1503493084814 ps
CPU time 1519.12 seconds
Started Jun 25 05:42:24 PM PDT 24
Finished Jun 25 06:07:44 PM PDT 24
Peak memory 194196 kb
Host smart-d287aa7e-6e76-4284-9772-e7ac515ad83e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417480583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2417480583
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.4109017568
Short name T151
Test name
Test status
Simulation time 118949978813 ps
CPU time 1305.9 seconds
Started Jun 25 05:43:30 PM PDT 24
Finished Jun 25 06:05:17 PM PDT 24
Peak memory 191332 kb
Host smart-7c8e492b-f119-4d22-bcef-d91a65077797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109017568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.4109017568
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3610600811
Short name T243
Test name
Test status
Simulation time 821271290551 ps
CPU time 430.51 seconds
Started Jun 25 05:43:41 PM PDT 24
Finished Jun 25 05:50:52 PM PDT 24
Peak memory 191332 kb
Host smart-3d5c4b75-fb6f-4400-8a41-5540ec6e3024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610600811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3610600811
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.700366177
Short name T327
Test name
Test status
Simulation time 225404824909 ps
CPU time 671.45 seconds
Started Jun 25 05:44:09 PM PDT 24
Finished Jun 25 05:55:21 PM PDT 24
Peak memory 191316 kb
Host smart-c0283a72-03bb-4587-a5ef-3d72998c8c65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700366177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.700366177
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3616759707
Short name T143
Test name
Test status
Simulation time 320305019726 ps
CPU time 279.4 seconds
Started Jun 25 05:42:49 PM PDT 24
Finished Jun 25 05:47:29 PM PDT 24
Peak memory 183100 kb
Host smart-e278b07e-0d16-41e5-b59a-ebbc0d8c0258
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616759707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3616759707
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/110.rv_timer_random.1165841847
Short name T166
Test name
Test status
Simulation time 54271222652 ps
CPU time 256 seconds
Started Jun 25 05:43:33 PM PDT 24
Finished Jun 25 05:47:49 PM PDT 24
Peak memory 191456 kb
Host smart-3e45a508-d8e6-4fb4-a8f1-1dd2856a72d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165841847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1165841847
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1114185980
Short name T162
Test name
Test status
Simulation time 73878140755 ps
CPU time 323.29 seconds
Started Jun 25 05:43:30 PM PDT 24
Finished Jun 25 05:48:54 PM PDT 24
Peak memory 191344 kb
Host smart-20e913f5-a72e-452e-b91f-3e676841d3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114185980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1114185980
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2083712401
Short name T321
Test name
Test status
Simulation time 659579271547 ps
CPU time 389.09 seconds
Started Jun 25 05:43:39 PM PDT 24
Finished Jun 25 05:50:09 PM PDT 24
Peak memory 191336 kb
Host smart-04feae1a-ced6-4d3c-bf9a-767fe3bfbea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083712401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2083712401
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2431273207
Short name T248
Test name
Test status
Simulation time 498986054483 ps
CPU time 777.21 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 05:55:42 PM PDT 24
Peak memory 183124 kb
Host smart-a3d35b78-62aa-4153-a631-f90c2f299bbc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431273207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2431273207
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.746804117
Short name T220
Test name
Test status
Simulation time 120351145138 ps
CPU time 337.54 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 191360 kb
Host smart-d5ddd564-20c0-4b03-bb10-933f1fe0f28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746804117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
746804117
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/77.rv_timer_random.3890314851
Short name T312
Test name
Test status
Simulation time 156847792085 ps
CPU time 324.16 seconds
Started Jun 25 05:43:03 PM PDT 24
Finished Jun 25 05:48:30 PM PDT 24
Peak memory 194880 kb
Host smart-45317dba-9b70-4f69-a72d-b8a7581809d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890314851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3890314851
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.454597561
Short name T185
Test name
Test status
Simulation time 1320379883950 ps
CPU time 567.67 seconds
Started Jun 25 05:42:22 PM PDT 24
Finished Jun 25 05:51:50 PM PDT 24
Peak memory 183136 kb
Host smart-8d8ddd37-f5fd-4c18-8a70-134a35c7e9b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454597561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.454597561
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/128.rv_timer_random.1495884582
Short name T116
Test name
Test status
Simulation time 141536694536 ps
CPU time 212.71 seconds
Started Jun 25 05:43:40 PM PDT 24
Finished Jun 25 05:47:13 PM PDT 24
Peak memory 191324 kb
Host smart-5c3e51ae-a74b-4469-a736-29b57467be84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495884582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1495884582
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2376673334
Short name T132
Test name
Test status
Simulation time 126206347582 ps
CPU time 220.49 seconds
Started Jun 25 05:44:06 PM PDT 24
Finished Jun 25 05:47:47 PM PDT 24
Peak memory 191336 kb
Host smart-1bd653bd-46ea-475c-8472-906e34c74698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376673334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2376673334
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3728335538
Short name T60
Test name
Test status
Simulation time 1173116327717 ps
CPU time 486.21 seconds
Started Jun 25 05:42:32 PM PDT 24
Finished Jun 25 05:50:40 PM PDT 24
Peak memory 195368 kb
Host smart-7c1c07bf-2218-4c69-acea-aa12d0473223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728335538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3728335538
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/183.rv_timer_random.2596788026
Short name T271
Test name
Test status
Simulation time 126362847364 ps
CPU time 364.74 seconds
Started Jun 25 05:44:13 PM PDT 24
Finished Jun 25 05:50:18 PM PDT 24
Peak memory 193572 kb
Host smart-118bfd49-fb48-4126-ba90-9c2da4835c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596788026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2596788026
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1135825181
Short name T357
Test name
Test status
Simulation time 668001042337 ps
CPU time 683.24 seconds
Started Jun 25 05:43:02 PM PDT 24
Finished Jun 25 05:54:28 PM PDT 24
Peak memory 191280 kb
Host smart-62b5eb55-2570-4289-b146-81d6292c7013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135825181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1135825181
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.4033221303
Short name T237
Test name
Test status
Simulation time 329077170909 ps
CPU time 711.6 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:54:55 PM PDT 24
Peak memory 191348 kb
Host smart-39f2bb10-4351-4e86-9387-3bc782a67739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033221303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.4033221303
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3648860253
Short name T109
Test name
Test status
Simulation time 95798571 ps
CPU time 1.15 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:11 PM PDT 24
Peak memory 194828 kb
Host smart-d04b1ac7-f6f7-4f2f-bf64-c58cb45ff8b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648860253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3648860253
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/108.rv_timer_random.866311231
Short name T239
Test name
Test status
Simulation time 152955607751 ps
CPU time 2117.08 seconds
Started Jun 25 05:43:33 PM PDT 24
Finished Jun 25 06:18:51 PM PDT 24
Peak memory 191464 kb
Host smart-fb98c2b5-7709-4dc7-9194-5ed1f55db6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866311231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.866311231
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.4044598530
Short name T232
Test name
Test status
Simulation time 82299720723 ps
CPU time 145.97 seconds
Started Jun 25 05:43:40 PM PDT 24
Finished Jun 25 05:46:07 PM PDT 24
Peak memory 194224 kb
Host smart-86a4a6a7-8344-422f-b0f3-4db3fac6ba61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044598530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4044598530
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1749386723
Short name T213
Test name
Test status
Simulation time 52389449751 ps
CPU time 85.01 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:44:04 PM PDT 24
Peak memory 183144 kb
Host smart-676bcd33-70c1-426f-9034-5d0852d6e54e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749386723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1749386723
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/179.rv_timer_random.3464802692
Short name T242
Test name
Test status
Simulation time 3288594170379 ps
CPU time 631.85 seconds
Started Jun 25 05:44:06 PM PDT 24
Finished Jun 25 05:54:38 PM PDT 24
Peak memory 191336 kb
Host smart-65c9351e-2fb5-4bfc-ba73-9e975d6ec081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464802692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3464802692
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3502654049
Short name T282
Test name
Test status
Simulation time 605598341412 ps
CPU time 531.41 seconds
Started Jun 25 05:44:22 PM PDT 24
Finished Jun 25 05:53:14 PM PDT 24
Peak memory 191364 kb
Host smart-98a408ea-c520-4f8d-b3cb-9434a0caa011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502654049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3502654049
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1431804177
Short name T71
Test name
Test status
Simulation time 443004481488 ps
CPU time 404.42 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:49:03 PM PDT 24
Peak memory 183076 kb
Host smart-91ce5d78-0b3e-4bad-904c-7e94c2dc20c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431804177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1431804177
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_random.2560278993
Short name T186
Test name
Test status
Simulation time 579344704390 ps
CPU time 324.83 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:47:38 PM PDT 24
Peak memory 191320 kb
Host smart-67d84c39-b344-4e22-b8c4-5887d757e916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560278993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2560278993
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2489755373
Short name T136
Test name
Test status
Simulation time 83443504488 ps
CPU time 142.64 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:45:26 PM PDT 24
Peak memory 183128 kb
Host smart-bf169306-8dd5-4064-90e9-fda0d3bf8dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489755373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2489755373
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_random.2974985402
Short name T240
Test name
Test status
Simulation time 139299173751 ps
CPU time 387.96 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:48:46 PM PDT 24
Peak memory 191344 kb
Host smart-afe43a19-0015-475e-9c55-ad43285527e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974985402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2974985402
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2598491936
Short name T225
Test name
Test status
Simulation time 121247834939 ps
CPU time 227.59 seconds
Started Jun 25 05:43:00 PM PDT 24
Finished Jun 25 05:46:52 PM PDT 24
Peak memory 191336 kb
Host smart-fa30326c-3354-42c3-a791-fdb4af54f58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598491936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2598491936
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3241206977
Short name T250
Test name
Test status
Simulation time 108240377228 ps
CPU time 173.28 seconds
Started Jun 25 05:43:21 PM PDT 24
Finished Jun 25 05:46:16 PM PDT 24
Peak memory 191328 kb
Host smart-f29bdb8b-4845-42a5-a920-83bed85fb4aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241206977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3241206977
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3452245955
Short name T120
Test name
Test status
Simulation time 466541646504 ps
CPU time 218.31 seconds
Started Jun 25 05:43:32 PM PDT 24
Finished Jun 25 05:47:11 PM PDT 24
Peak memory 193856 kb
Host smart-44fdc2c7-a8fb-4dc3-a53b-3a50b6ce3db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452245955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3452245955
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.653727652
Short name T171
Test name
Test status
Simulation time 430602500110 ps
CPU time 262.86 seconds
Started Jun 25 05:43:39 PM PDT 24
Finished Jun 25 05:48:03 PM PDT 24
Peak memory 194868 kb
Host smart-8e81b4a7-b75d-42a8-909d-262082f6ea64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653727652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.653727652
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.79837942
Short name T172
Test name
Test status
Simulation time 44919795518 ps
CPU time 73.74 seconds
Started Jun 25 05:43:39 PM PDT 24
Finished Jun 25 05:44:53 PM PDT 24
Peak memory 191332 kb
Host smart-1906bf3b-17a5-4116-9f05-76943704e97a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79837942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.79837942
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4012676243
Short name T180
Test name
Test status
Simulation time 124693442990 ps
CPU time 718.24 seconds
Started Jun 25 05:43:49 PM PDT 24
Finished Jun 25 05:55:50 PM PDT 24
Peak memory 191336 kb
Host smart-020002ba-57f9-48b0-a44f-26a9eb38c594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012676243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4012676243
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3471720264
Short name T238
Test name
Test status
Simulation time 739166114355 ps
CPU time 382.39 seconds
Started Jun 25 05:43:51 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 191164 kb
Host smart-4d1eb268-d0a9-4fc1-9014-45cc3403a793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471720264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3471720264
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1931499194
Short name T154
Test name
Test status
Simulation time 1302506020772 ps
CPU time 725.09 seconds
Started Jun 25 05:43:58 PM PDT 24
Finished Jun 25 05:56:04 PM PDT 24
Peak memory 192648 kb
Host smart-12b3445f-dbcc-4f7d-82a6-6c7ac2497790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931499194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1931499194
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.879307506
Short name T279
Test name
Test status
Simulation time 27384286794 ps
CPU time 92.68 seconds
Started Jun 25 05:42:43 PM PDT 24
Finished Jun 25 05:44:16 PM PDT 24
Peak memory 191584 kb
Host smart-8143abd6-9104-42ef-b936-8e193b030bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879307506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.879307506
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4262898019
Short name T275
Test name
Test status
Simulation time 70163326096 ps
CPU time 105.23 seconds
Started Jun 25 05:44:31 PM PDT 24
Finished Jun 25 05:46:17 PM PDT 24
Peak memory 191312 kb
Host smart-4e98afeb-afed-4923-8311-abe4b2eb72bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262898019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4262898019
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2605072202
Short name T189
Test name
Test status
Simulation time 292496239034 ps
CPU time 133.51 seconds
Started Jun 25 05:44:29 PM PDT 24
Finished Jun 25 05:46:43 PM PDT 24
Peak memory 191348 kb
Host smart-321ecd3a-f708-4430-b766-8682870129d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605072202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2605072202
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.998217175
Short name T52
Test name
Test status
Simulation time 750524090532 ps
CPU time 376.85 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 05:49:02 PM PDT 24
Peak memory 183136 kb
Host smart-1b4f5213-a74d-4706-893a-e859ef062ea0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998217175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.998217175
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1620358094
Short name T229
Test name
Test status
Simulation time 1683566416248 ps
CPU time 1334.87 seconds
Started Jun 25 05:42:51 PM PDT 24
Finished Jun 25 06:05:08 PM PDT 24
Peak memory 191344 kb
Host smart-5cbcb7ba-843b-442b-9fbb-7b78c35e9b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620358094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1620358094
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random.830041378
Short name T274
Test name
Test status
Simulation time 31950087491 ps
CPU time 47.79 seconds
Started Jun 25 05:42:41 PM PDT 24
Finished Jun 25 05:43:30 PM PDT 24
Peak memory 191356 kb
Host smart-86d30a90-dc70-44c3-a460-4b06dd193ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830041378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.830041378
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.374995204
Short name T262
Test name
Test status
Simulation time 128263584616 ps
CPU time 1360.7 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 06:05:35 PM PDT 24
Peak memory 191328 kb
Host smart-30e0c903-0a51-48a6-90bb-ade561f5eaf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374995204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.374995204
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.4252910278
Short name T195
Test name
Test status
Simulation time 705001092353 ps
CPU time 576.28 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 05:52:38 PM PDT 24
Peak memory 191328 kb
Host smart-f14a570e-3ff6-42d3-9b46-9871f215b7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252910278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4252910278
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2013506063
Short name T299
Test name
Test status
Simulation time 304617316834 ps
CPU time 1092.26 seconds
Started Jun 25 05:43:12 PM PDT 24
Finished Jun 25 06:01:25 PM PDT 24
Peak memory 191332 kb
Host smart-7eebc039-e0e1-45d6-8de8-1222690b394d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013506063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2013506063
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3083672202
Short name T119
Test name
Test status
Simulation time 77217365541 ps
CPU time 125.97 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:44:16 PM PDT 24
Peak memory 191352 kb
Host smart-4f5f6308-27f2-41de-9600-8195761c4cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083672202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3083672202
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_random.3680788656
Short name T257
Test name
Test status
Simulation time 318006315883 ps
CPU time 139 seconds
Started Jun 25 05:42:25 PM PDT 24
Finished Jun 25 05:44:45 PM PDT 24
Peak memory 191328 kb
Host smart-1109832e-6dea-4ec4-944b-c17b646d365f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680788656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3680788656
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.33831399
Short name T150
Test name
Test status
Simulation time 22334347123 ps
CPU time 36.75 seconds
Started Jun 25 05:43:31 PM PDT 24
Finished Jun 25 05:44:09 PM PDT 24
Peak memory 183132 kb
Host smart-3be4dba8-3acb-49f8-b5e8-49b058e06d50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33831399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.33831399
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2944888766
Short name T329
Test name
Test status
Simulation time 134160086186 ps
CPU time 231.69 seconds
Started Jun 25 05:42:26 PM PDT 24
Finished Jun 25 05:46:18 PM PDT 24
Peak memory 183164 kb
Host smart-35b16721-0f98-4af6-b3ef-b9e7f7f5f572
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944888766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2944888766
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_random.3829431103
Short name T139
Test name
Test status
Simulation time 368684038261 ps
CPU time 203.6 seconds
Started Jun 25 05:42:25 PM PDT 24
Finished Jun 25 05:45:49 PM PDT 24
Peak memory 191352 kb
Host smart-b8999865-b5e8-4cad-bbb0-d6ffe03f3b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829431103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3829431103
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2246693359
Short name T177
Test name
Test status
Simulation time 167017898972 ps
CPU time 62.27 seconds
Started Jun 25 05:43:42 PM PDT 24
Finished Jun 25 05:44:45 PM PDT 24
Peak memory 183064 kb
Host smart-af8bb419-8ab9-4df1-970a-41dff4d7861f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246693359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2246693359
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3332171350
Short name T188
Test name
Test status
Simulation time 94478756469 ps
CPU time 262.52 seconds
Started Jun 25 05:43:41 PM PDT 24
Finished Jun 25 05:48:04 PM PDT 24
Peak memory 191340 kb
Host smart-6df20123-b13b-46ad-8522-143162ac7907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332171350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3332171350
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.632287687
Short name T210
Test name
Test status
Simulation time 224165103235 ps
CPU time 196.21 seconds
Started Jun 25 05:43:40 PM PDT 24
Finished Jun 25 05:46:58 PM PDT 24
Peak memory 194892 kb
Host smart-b43a8f21-661d-4473-b6f2-73b695be40bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632287687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.632287687
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3754632532
Short name T223
Test name
Test status
Simulation time 539856183436 ps
CPU time 619.3 seconds
Started Jun 25 05:42:27 PM PDT 24
Finished Jun 25 05:52:47 PM PDT 24
Peak memory 191332 kb
Host smart-3233fc03-ba24-4c27-a6c6-3b08375c42bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754632532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3754632532
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/149.rv_timer_random.2700239241
Short name T167
Test name
Test status
Simulation time 215434595359 ps
CPU time 113.79 seconds
Started Jun 25 05:43:51 PM PDT 24
Finished Jun 25 05:45:46 PM PDT 24
Peak memory 191336 kb
Host smart-a90c5cbc-583d-49db-8515-7589c7b7ca1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700239241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2700239241
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3905506653
Short name T174
Test name
Test status
Simulation time 241496712216 ps
CPU time 937.94 seconds
Started Jun 25 05:43:57 PM PDT 24
Finished Jun 25 05:59:36 PM PDT 24
Peak memory 191280 kb
Host smart-3d442293-8ab4-46b6-9315-1554c8fc37dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905506653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3905506653
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1444078255
Short name T123
Test name
Test status
Simulation time 166628199110 ps
CPU time 330.52 seconds
Started Jun 25 05:43:58 PM PDT 24
Finished Jun 25 05:49:30 PM PDT 24
Peak memory 191336 kb
Host smart-22ea9160-9083-4072-bdf5-c9c0751bfa11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444078255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1444078255
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1726752700
Short name T295
Test name
Test status
Simulation time 353863890581 ps
CPU time 263.06 seconds
Started Jun 25 05:44:14 PM PDT 24
Finished Jun 25 05:48:37 PM PDT 24
Peak memory 191348 kb
Host smart-5c44a6c1-ca4e-4119-a4a9-0fa1b0a713c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726752700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1726752700
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.694310562
Short name T121
Test name
Test status
Simulation time 291538757725 ps
CPU time 173.26 seconds
Started Jun 25 05:42:37 PM PDT 24
Finished Jun 25 05:45:31 PM PDT 24
Peak memory 191332 kb
Host smart-60a82eb5-e963-4de4-a1a0-1f49f4b34353
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694310562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.694310562
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.1295459457
Short name T73
Test name
Test status
Simulation time 108740195436 ps
CPU time 393.29 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 05:49:18 PM PDT 24
Peak memory 191332 kb
Host smart-2e15535f-19cc-4af4-9af9-2f173d3205ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295459457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1295459457
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.64944574
Short name T246
Test name
Test status
Simulation time 412988688135 ps
CPU time 207 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:46:24 PM PDT 24
Peak memory 183148 kb
Host smart-44236db8-25a3-4382-98f3-ec092fae8851
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64944574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.rv_timer_cfg_update_on_fly.64944574
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_random.2915606533
Short name T349
Test name
Test status
Simulation time 49870085373 ps
CPU time 80.64 seconds
Started Jun 25 05:42:53 PM PDT 24
Finished Jun 25 05:44:15 PM PDT 24
Peak memory 183144 kb
Host smart-3c2f6af1-6552-47ef-ae63-36c4db131100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915606533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2915606533
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1856790053
Short name T315
Test name
Test status
Simulation time 1077146885413 ps
CPU time 829.9 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:56:44 PM PDT 24
Peak memory 183136 kb
Host smart-164155a9-6d8b-4179-bb49-062deae99d87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856790053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1856790053
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3580933020
Short name T296
Test name
Test status
Simulation time 179022869049 ps
CPU time 302.42 seconds
Started Jun 25 05:42:43 PM PDT 24
Finished Jun 25 05:47:46 PM PDT 24
Peak memory 183128 kb
Host smart-f5310679-2fe5-4703-ba86-7fcd34b23e04
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580933020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3580933020
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1503473555
Short name T163
Test name
Test status
Simulation time 466948344785 ps
CPU time 1591.04 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 06:09:23 PM PDT 24
Peak memory 191332 kb
Host smart-841c31c0-ba1d-450c-93c8-c1be4031ac1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503473555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1503473555
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_random.1613111341
Short name T230
Test name
Test status
Simulation time 219796201826 ps
CPU time 742.22 seconds
Started Jun 25 05:42:51 PM PDT 24
Finished Jun 25 05:55:15 PM PDT 24
Peak memory 191332 kb
Host smart-363d0651-879e-46cd-bf74-1f529b93758e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613111341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1613111341
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3885300260
Short name T164
Test name
Test status
Simulation time 104537744781 ps
CPU time 280.45 seconds
Started Jun 25 05:43:14 PM PDT 24
Finished Jun 25 05:47:55 PM PDT 24
Peak memory 191348 kb
Host smart-06a6c840-93da-4814-8d78-b17c914b0bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885300260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3885300260
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.759849444
Short name T95
Test name
Test status
Simulation time 33557670 ps
CPU time 0.83 seconds
Started Jun 25 05:41:55 PM PDT 24
Finished Jun 25 05:41:57 PM PDT 24
Peak memory 192252 kb
Host smart-07beab7e-ed4b-4e00-acae-562e3d6f1fc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759849444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.759849444
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1799625374
Short name T100
Test name
Test status
Simulation time 241093679 ps
CPU time 2.79 seconds
Started Jun 25 05:41:55 PM PDT 24
Finished Jun 25 05:41:59 PM PDT 24
Peak memory 193012 kb
Host smart-aeb08251-712a-4bf5-a63e-65ac5fa53aa2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799625374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1799625374
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2638151874
Short name T467
Test name
Test status
Simulation time 16734539 ps
CPU time 0.6 seconds
Started Jun 25 05:41:49 PM PDT 24
Finished Jun 25 05:41:53 PM PDT 24
Peak memory 182272 kb
Host smart-7ae49971-9ae5-474f-b99a-5f97b82beb98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638151874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2638151874
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2765176078
Short name T498
Test name
Test status
Simulation time 164458699 ps
CPU time 0.77 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:41:51 PM PDT 24
Peak memory 194596 kb
Host smart-1259aa8c-c153-4caa-8f77-443a160b877b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765176078 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2765176078
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4267179159
Short name T544
Test name
Test status
Simulation time 14549666 ps
CPU time 0.6 seconds
Started Jun 25 05:41:50 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 182100 kb
Host smart-568bbec4-a712-4cf1-a21e-98af2a515c11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267179159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4267179159
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3528648212
Short name T515
Test name
Test status
Simulation time 36819554 ps
CPU time 0.54 seconds
Started Jun 25 05:41:49 PM PDT 24
Finished Jun 25 05:41:53 PM PDT 24
Peak memory 182228 kb
Host smart-101ebfd8-1338-4748-aac8-4db662c5f112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528648212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3528648212
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2929070854
Short name T87
Test name
Test status
Simulation time 27410387 ps
CPU time 0.74 seconds
Started Jun 25 05:41:47 PM PDT 24
Finished Jun 25 05:41:50 PM PDT 24
Peak memory 191280 kb
Host smart-ae89e238-7213-4e75-af6b-e7230b5d60eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929070854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2929070854
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1099211369
Short name T581
Test name
Test status
Simulation time 352952121 ps
CPU time 2.05 seconds
Started Jun 25 05:42:02 PM PDT 24
Finished Jun 25 05:42:07 PM PDT 24
Peak memory 197072 kb
Host smart-7d835b62-c284-4a7f-8a2f-985360a70889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099211369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1099211369
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3171892200
Short name T526
Test name
Test status
Simulation time 171098722 ps
CPU time 0.9 seconds
Started Jun 25 05:41:51 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 193548 kb
Host smart-393fee87-908d-4f9c-a6fd-eec2986308d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171892200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3171892200
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.424888264
Short name T89
Test name
Test status
Simulation time 35136819 ps
CPU time 0.79 seconds
Started Jun 25 05:42:04 PM PDT 24
Finished Jun 25 05:42:07 PM PDT 24
Peak memory 182320 kb
Host smart-e4695b38-0c91-4d2b-9027-1550e0ec37a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424888264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.424888264
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1176483401
Short name T516
Test name
Test status
Simulation time 584798859 ps
CPU time 1.64 seconds
Started Jun 25 05:41:55 PM PDT 24
Finished Jun 25 05:41:58 PM PDT 24
Peak memory 191704 kb
Host smart-244a76f7-aa33-4abb-8459-ba17748e4975
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176483401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1176483401
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3301918659
Short name T504
Test name
Test status
Simulation time 25533374 ps
CPU time 0.54 seconds
Started Jun 25 05:41:53 PM PDT 24
Finished Jun 25 05:41:55 PM PDT 24
Peak memory 181964 kb
Host smart-70af6e54-a36f-4c17-890e-ed44f503d1df
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301918659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3301918659
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.150491748
Short name T577
Test name
Test status
Simulation time 54306541 ps
CPU time 0.78 seconds
Started Jun 25 05:41:51 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 194920 kb
Host smart-a0771da3-54d4-4be2-b5f9-50e072dc711e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150491748 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.150491748
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1121053762
Short name T540
Test name
Test status
Simulation time 11791031 ps
CPU time 0.61 seconds
Started Jun 25 05:41:57 PM PDT 24
Finished Jun 25 05:41:59 PM PDT 24
Peak memory 182312 kb
Host smart-2a9feb28-a17f-47af-9ad0-b0f6740d2ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121053762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1121053762
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2752555960
Short name T484
Test name
Test status
Simulation time 18402746 ps
CPU time 0.57 seconds
Started Jun 25 05:42:03 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 181640 kb
Host smart-063ee198-b792-4b74-8397-16a7bdecd81a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752555960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2752555960
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.32956781
Short name T542
Test name
Test status
Simulation time 21463793 ps
CPU time 0.77 seconds
Started Jun 25 05:41:48 PM PDT 24
Finished Jun 25 05:41:52 PM PDT 24
Peak memory 192764 kb
Host smart-d93779c5-828b-4665-b73a-de1ec33bbd84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32956781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_time
r_same_csr_outstanding.32956781
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2965033556
Short name T553
Test name
Test status
Simulation time 221878009 ps
CPU time 1.41 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 197352 kb
Host smart-bb7a6127-34ce-46b1-8226-43e2757f8a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965033556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2965033556
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3957053098
Short name T517
Test name
Test status
Simulation time 575292268 ps
CPU time 1.35 seconds
Started Jun 25 05:41:50 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 182748 kb
Host smart-c6a60f70-a290-4c62-98a3-e33141bae57c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957053098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3957053098
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.89621807
Short name T563
Test name
Test status
Simulation time 39884399 ps
CPU time 0.65 seconds
Started Jun 25 05:42:04 PM PDT 24
Finished Jun 25 05:42:07 PM PDT 24
Peak memory 192796 kb
Host smart-c135f0df-26ec-4d9c-bd92-a007db0a46a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89621807 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.89621807
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3735078479
Short name T92
Test name
Test status
Simulation time 54450662 ps
CPU time 0.59 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:03 PM PDT 24
Peak memory 182336 kb
Host smart-fa79e3d5-3a62-4c75-8eca-238f378316d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735078479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3735078479
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.774584251
Short name T507
Test name
Test status
Simulation time 69676103 ps
CPU time 0.55 seconds
Started Jun 25 05:41:57 PM PDT 24
Finished Jun 25 05:41:59 PM PDT 24
Peak memory 182200 kb
Host smart-ecb8f1c5-74ad-4578-91dd-9b3e55b44ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774584251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.774584251
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4266653679
Short name T541
Test name
Test status
Simulation time 27916200 ps
CPU time 0.7 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 192892 kb
Host smart-b9a6873f-67c4-47b3-a380-501cdb2548e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266653679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4266653679
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3184930153
Short name T42
Test name
Test status
Simulation time 332545151 ps
CPU time 2.56 seconds
Started Jun 25 05:42:02 PM PDT 24
Finished Jun 25 05:42:07 PM PDT 24
Peak memory 197100 kb
Host smart-05b1cfe7-e15a-4387-9184-aa88250a8775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184930153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3184930153
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3836677357
Short name T528
Test name
Test status
Simulation time 137522824 ps
CPU time 0.81 seconds
Started Jun 25 05:42:05 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 195256 kb
Host smart-be68d886-e766-43d2-b41c-bb086faef363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836677357 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3836677357
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1698528665
Short name T549
Test name
Test status
Simulation time 26883643 ps
CPU time 0.59 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:01 PM PDT 24
Peak memory 182120 kb
Host smart-0d7448cd-8203-4110-8b39-bc210b3b54d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698528665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1698528665
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3785464914
Short name T463
Test name
Test status
Simulation time 16908487 ps
CPU time 0.58 seconds
Started Jun 25 05:41:59 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 182216 kb
Host smart-07862784-79b3-4327-8b5c-59e8a7d2a573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785464914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3785464914
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3019481092
Short name T550
Test name
Test status
Simulation time 137686061 ps
CPU time 0.79 seconds
Started Jun 25 05:41:59 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 191156 kb
Host smart-27d0574b-4d92-4f22-b578-3ce3138069e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019481092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3019481092
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1084580490
Short name T492
Test name
Test status
Simulation time 116974287 ps
CPU time 1.64 seconds
Started Jun 25 05:42:05 PM PDT 24
Finished Jun 25 05:42:09 PM PDT 24
Peak memory 197144 kb
Host smart-a57ed0b4-87d1-4f6d-8c01-e682cb5f0d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084580490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1084580490
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3829971268
Short name T551
Test name
Test status
Simulation time 336514707 ps
CPU time 1.36 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 182768 kb
Host smart-1d43c783-53e8-4fbc-a81d-e2bdb039f535
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829971268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3829971268
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3395625451
Short name T483
Test name
Test status
Simulation time 19327045 ps
CPU time 0.91 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 196932 kb
Host smart-5fdf90c0-ed28-4a8c-9a65-5ea7a807c11c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395625451 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3395625451
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1390046015
Short name T578
Test name
Test status
Simulation time 12600908 ps
CPU time 0.57 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:03 PM PDT 24
Peak memory 182316 kb
Host smart-984249ef-76b2-46de-8762-a59c04a9bc62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390046015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1390046015
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.730820530
Short name T539
Test name
Test status
Simulation time 17673316 ps
CPU time 0.57 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:03 PM PDT 24
Peak memory 182236 kb
Host smart-54eff883-d1c1-486f-8c0c-48d9babd756d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730820530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.730820530
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2248018450
Short name T57
Test name
Test status
Simulation time 324619771 ps
CPU time 2.91 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 197096 kb
Host smart-8cec423e-d970-4a7a-9b58-480cd664dbc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248018450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2248018450
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.481308885
Short name T107
Test name
Test status
Simulation time 74515938 ps
CPU time 1.13 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 194824 kb
Host smart-3720e2a7-4086-4507-b4dd-84881cf5c006
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481308885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.481308885
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2709042065
Short name T514
Test name
Test status
Simulation time 63504461 ps
CPU time 0.64 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 192616 kb
Host smart-0643fadb-09c4-4adb-99ed-f2760465ed06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709042065 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2709042065
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2644477558
Short name T486
Test name
Test status
Simulation time 13276647 ps
CPU time 0.61 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 182296 kb
Host smart-69886ca1-e0e7-4df0-b3b3-6b16955ea460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644477558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2644477558
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.479245646
Short name T493
Test name
Test status
Simulation time 91186718 ps
CPU time 0.57 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 182160 kb
Host smart-d9a07f55-1bf6-4319-a345-abc1b4c64ada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479245646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.479245646
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2763606975
Short name T43
Test name
Test status
Simulation time 50101999 ps
CPU time 0.64 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:01 PM PDT 24
Peak memory 190864 kb
Host smart-c85b3d45-1954-4ca9-a485-fbce6f7faa00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763606975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2763606975
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2435989520
Short name T488
Test name
Test status
Simulation time 192391487 ps
CPU time 1.21 seconds
Started Jun 25 05:41:57 PM PDT 24
Finished Jun 25 05:42:00 PM PDT 24
Peak memory 196340 kb
Host smart-ef0a8494-602d-4bb3-9517-8ad275715927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435989520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2435989520
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1464447700
Short name T497
Test name
Test status
Simulation time 153323951 ps
CPU time 0.85 seconds
Started Jun 25 05:42:02 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 193256 kb
Host smart-d60318d2-05d4-46cc-b917-4c4aae132313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464447700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1464447700
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.723364661
Short name T555
Test name
Test status
Simulation time 76838885 ps
CPU time 0.72 seconds
Started Jun 25 05:42:05 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 194412 kb
Host smart-ab695281-0e50-44fa-91b9-91bb1d3d98c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723364661 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.723364661
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1962338640
Short name T85
Test name
Test status
Simulation time 17380878 ps
CPU time 0.61 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 182276 kb
Host smart-10fe6804-2cdf-4ed1-bf66-38a9580d819b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962338640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1962338640
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2866174562
Short name T543
Test name
Test status
Simulation time 33684704 ps
CPU time 0.56 seconds
Started Jun 25 05:42:06 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 181640 kb
Host smart-3f0fac9c-612e-4fd0-a711-a97fefde14ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866174562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2866174562
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3966768134
Short name T84
Test name
Test status
Simulation time 19445872 ps
CPU time 0.89 seconds
Started Jun 25 05:42:04 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 194132 kb
Host smart-ed4751ec-87f8-43bf-bbb8-f0968f8fdc45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966768134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3966768134
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3686302146
Short name T512
Test name
Test status
Simulation time 41076389 ps
CPU time 1.98 seconds
Started Jun 25 05:41:59 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 197104 kb
Host smart-54a5e483-2120-4e4b-be8d-9bebc0e87235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686302146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3686302146
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3873515424
Short name T110
Test name
Test status
Simulation time 138126695 ps
CPU time 1.22 seconds
Started Jun 25 05:42:05 PM PDT 24
Finished Jun 25 05:42:09 PM PDT 24
Peak memory 193624 kb
Host smart-b714b69a-a07c-4da3-8395-5facc6fc011a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873515424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3873515424
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3908507490
Short name T566
Test name
Test status
Simulation time 33145497 ps
CPU time 1.36 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 197132 kb
Host smart-e8f56647-5358-40b5-97cc-afa66cbb110f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908507490 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3908507490
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2616251205
Short name T482
Test name
Test status
Simulation time 40390449 ps
CPU time 0.58 seconds
Started Jun 25 05:42:12 PM PDT 24
Finished Jun 25 05:42:15 PM PDT 24
Peak memory 182144 kb
Host smart-9251a994-c9cd-4de4-a135-7fec4ee783d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616251205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2616251205
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3841687204
Short name T519
Test name
Test status
Simulation time 40827864 ps
CPU time 0.52 seconds
Started Jun 25 05:42:02 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 182160 kb
Host smart-f8327aa5-ddd0-4688-91e0-5fba88254b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841687204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3841687204
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2492012649
Short name T33
Test name
Test status
Simulation time 21042232 ps
CPU time 0.74 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:03 PM PDT 24
Peak memory 191276 kb
Host smart-84f050d0-20d5-40d2-aa99-80c4d130d82e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492012649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2492012649
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3982455703
Short name T465
Test name
Test status
Simulation time 339325163 ps
CPU time 1.59 seconds
Started Jun 25 05:42:06 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 196068 kb
Host smart-bffe6fcf-805d-484e-bfa4-cbb4d30a4ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982455703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3982455703
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2587769904
Short name T552
Test name
Test status
Simulation time 82243298 ps
CPU time 1.14 seconds
Started Jun 25 05:42:04 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 194460 kb
Host smart-0bc6f203-d2c0-4143-b991-9075a2bca2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587769904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2587769904
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4245406116
Short name T546
Test name
Test status
Simulation time 34702544 ps
CPU time 0.69 seconds
Started Jun 25 05:42:10 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 193736 kb
Host smart-ad01409a-8799-4e09-9664-4ab09bbcb150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245406116 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.4245406116
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2678886499
Short name T91
Test name
Test status
Simulation time 13276651 ps
CPU time 0.56 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:13 PM PDT 24
Peak memory 182236 kb
Host smart-56022154-2201-453b-9dc0-d605b94d0ef3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678886499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2678886499
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2822495916
Short name T583
Test name
Test status
Simulation time 44324550 ps
CPU time 0.55 seconds
Started Jun 25 05:42:13 PM PDT 24
Finished Jun 25 05:42:15 PM PDT 24
Peak memory 181660 kb
Host smart-66c8bae0-1183-40ce-b429-95176bdd0d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822495916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2822495916
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2207891766
Short name T525
Test name
Test status
Simulation time 166408043 ps
CPU time 0.63 seconds
Started Jun 25 05:42:10 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 191544 kb
Host smart-d6fe5358-36e3-4582-8204-29e4860d42c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207891766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2207891766
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2703397336
Short name T579
Test name
Test status
Simulation time 26777475 ps
CPU time 1.37 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 197092 kb
Host smart-ef53d7ea-ea87-434c-9a07-825e6ae5272c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703397336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2703397336
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.9533816
Short name T108
Test name
Test status
Simulation time 87774463 ps
CPU time 1.14 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 194592 kb
Host smart-08a2975d-da64-43a3-9661-4bfc960573b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9533816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg
_err.9533816
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.954887393
Short name T478
Test name
Test status
Simulation time 16182588 ps
CPU time 0.79 seconds
Started Jun 25 05:42:02 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 193980 kb
Host smart-c0c71225-7f3b-4046-94d4-062adcbfe796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954887393 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.954887393
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2663901990
Short name T99
Test name
Test status
Simulation time 63646542 ps
CPU time 0.59 seconds
Started Jun 25 05:42:03 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 182312 kb
Host smart-8d8cd15c-f7ec-4bad-b218-71be98cc9f54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663901990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2663901990
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3037815129
Short name T531
Test name
Test status
Simulation time 19695468 ps
CPU time 0.59 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:03 PM PDT 24
Peak memory 182212 kb
Host smart-7d2ccc4c-3728-4529-84dd-0e80b06802fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037815129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3037815129
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3691651964
Short name T480
Test name
Test status
Simulation time 50751417 ps
CPU time 0.72 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 192616 kb
Host smart-ae0da1f4-b47b-4405-aa7d-2c4be31074dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691651964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3691651964
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4284028401
Short name T538
Test name
Test status
Simulation time 69940645 ps
CPU time 1.22 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:42:11 PM PDT 24
Peak memory 197108 kb
Host smart-4d66891e-4fd7-4bba-8af0-c5ebcffd4721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284028401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4284028401
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1864771120
Short name T31
Test name
Test status
Simulation time 172359534 ps
CPU time 1.36 seconds
Started Jun 25 05:42:03 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 194680 kb
Host smart-d04dd063-0edc-4bee-95ef-9482979894a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864771120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1864771120
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.954429770
Short name T571
Test name
Test status
Simulation time 15633599 ps
CPU time 0.64 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 193348 kb
Host smart-76374aaa-872c-4146-9b9e-8350bd20d114
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954429770 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.954429770
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2949648042
Short name T97
Test name
Test status
Simulation time 24530762 ps
CPU time 0.59 seconds
Started Jun 25 05:42:05 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 182312 kb
Host smart-2d4b8d1e-6fd5-4fd8-a7ef-b4c4a658b60c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949648042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2949648042
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3153531460
Short name T537
Test name
Test status
Simulation time 22138210 ps
CPU time 0.53 seconds
Started Jun 25 05:42:03 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 181888 kb
Host smart-f1aa2535-1dd5-4de2-8736-10b39e1431a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153531460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3153531460
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1539098219
Short name T105
Test name
Test status
Simulation time 21002110 ps
CPU time 0.71 seconds
Started Jun 25 05:42:15 PM PDT 24
Finished Jun 25 05:42:17 PM PDT 24
Peak memory 191260 kb
Host smart-6b88070b-10ba-41e8-82e7-28fafdbcb280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539098219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1539098219
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3615026781
Short name T560
Test name
Test status
Simulation time 90202300 ps
CPU time 2.2 seconds
Started Jun 25 05:42:05 PM PDT 24
Finished Jun 25 05:42:09 PM PDT 24
Peak memory 196616 kb
Host smart-4cca96c8-b0bb-46fa-80bd-4fd73f25d2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615026781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3615026781
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4102092042
Short name T575
Test name
Test status
Simulation time 135192162 ps
CPU time 0.81 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 192872 kb
Host smart-907ddb7d-85d0-4510-8f65-1e437475b0dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102092042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4102092042
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2764268136
Short name T464
Test name
Test status
Simulation time 51592821 ps
CPU time 0.9 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 195804 kb
Host smart-206c05b5-cfb0-418b-8e7c-e009b68e37f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764268136 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2764268136
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.81203797
Short name T93
Test name
Test status
Simulation time 13897210 ps
CPU time 0.59 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 182564 kb
Host smart-520b08b0-9606-4108-a24e-ad7defbbc701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81203797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.81203797
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3420167751
Short name T505
Test name
Test status
Simulation time 46464296 ps
CPU time 0.58 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 181892 kb
Host smart-c87157a7-c75f-4521-bac3-effcb9f8edd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420167751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3420167751
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4286344741
Short name T522
Test name
Test status
Simulation time 33947258 ps
CPU time 0.82 seconds
Started Jun 25 05:42:10 PM PDT 24
Finished Jun 25 05:42:13 PM PDT 24
Peak memory 191256 kb
Host smart-ac4d5bc1-6e6b-43ef-8736-85bafaa36401
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286344741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4286344741
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.923082108
Short name T462
Test name
Test status
Simulation time 89863433 ps
CPU time 1.91 seconds
Started Jun 25 05:42:14 PM PDT 24
Finished Jun 25 05:42:17 PM PDT 24
Peak memory 196972 kb
Host smart-198ded27-68e5-4c85-834c-0a7580acbefd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923082108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.923082108
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2484666109
Short name T559
Test name
Test status
Simulation time 485840056 ps
CPU time 0.84 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 193432 kb
Host smart-52ef984e-4282-4799-8fe9-73e077d6bb65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484666109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2484666109
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4016357044
Short name T86
Test name
Test status
Simulation time 111639046 ps
CPU time 0.83 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 192256 kb
Host smart-1d98da91-13a3-4d1f-98fb-fbc83d7954a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016357044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4016357044
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2989130935
Short name T502
Test name
Test status
Simulation time 147464955 ps
CPU time 1.75 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 192412 kb
Host smart-f0b8125b-8287-4615-864e-710d0b9540b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989130935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2989130935
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1423149482
Short name T46
Test name
Test status
Simulation time 45089360 ps
CPU time 0.54 seconds
Started Jun 25 05:41:50 PM PDT 24
Finished Jun 25 05:41:53 PM PDT 24
Peak memory 182312 kb
Host smart-6efcca19-e1af-4469-ada4-66f65de43911
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423149482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1423149482
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1602659867
Short name T582
Test name
Test status
Simulation time 56746012 ps
CPU time 0.87 seconds
Started Jun 25 05:41:57 PM PDT 24
Finished Jun 25 05:42:00 PM PDT 24
Peak memory 195096 kb
Host smart-e3babe71-671d-4342-b983-8c7601440a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602659867 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1602659867
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2143410834
Short name T532
Test name
Test status
Simulation time 50408239 ps
CPU time 0.63 seconds
Started Jun 25 05:41:57 PM PDT 24
Finished Jun 25 05:41:58 PM PDT 24
Peak memory 182436 kb
Host smart-3fc1e178-1a03-4763-9fe3-5e74b280ffc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143410834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2143410834
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2726916401
Short name T548
Test name
Test status
Simulation time 17714731 ps
CPU time 0.63 seconds
Started Jun 25 05:41:53 PM PDT 24
Finished Jun 25 05:41:55 PM PDT 24
Peak memory 182168 kb
Host smart-b47783e2-7887-4864-992d-a1ba16dec587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726916401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2726916401
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3098416855
Short name T569
Test name
Test status
Simulation time 88502706 ps
CPU time 0.72 seconds
Started Jun 25 05:41:54 PM PDT 24
Finished Jun 25 05:41:57 PM PDT 24
Peak memory 191776 kb
Host smart-c840fc47-337b-49e9-85ae-7cf71a7133bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098416855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3098416855
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.915994784
Short name T576
Test name
Test status
Simulation time 85852845 ps
CPU time 2.39 seconds
Started Jun 25 05:41:56 PM PDT 24
Finished Jun 25 05:42:00 PM PDT 24
Peak memory 197232 kb
Host smart-8abc4ea3-bf2a-4f33-8393-70852ac1aa57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915994784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.915994784
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1588716515
Short name T513
Test name
Test status
Simulation time 24078399 ps
CPU time 0.58 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:13 PM PDT 24
Peak memory 182192 kb
Host smart-c5ec37a1-8915-47c9-9d9e-7268e5e85594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588716515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1588716515
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2744532730
Short name T476
Test name
Test status
Simulation time 14631289 ps
CPU time 0.58 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 181880 kb
Host smart-880ffbec-af9b-4f5f-a87f-7833766f90c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744532730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2744532730
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.750648232
Short name T518
Test name
Test status
Simulation time 219689174 ps
CPU time 0.68 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 182212 kb
Host smart-9c4f4f33-5412-4af2-884e-447f2f55ed4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750648232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.750648232
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.100090272
Short name T496
Test name
Test status
Simulation time 44376513 ps
CPU time 0.53 seconds
Started Jun 25 05:42:14 PM PDT 24
Finished Jun 25 05:42:16 PM PDT 24
Peak memory 181480 kb
Host smart-52439484-cfbc-40f7-a408-5f32ceab8427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100090272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.100090272
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3909816339
Short name T471
Test name
Test status
Simulation time 13665985 ps
CPU time 0.56 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 182108 kb
Host smart-535dc9b4-d496-4ae6-84ba-dc94373ddd6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909816339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3909816339
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4218019985
Short name T533
Test name
Test status
Simulation time 79510502 ps
CPU time 0.56 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:11 PM PDT 24
Peak memory 182232 kb
Host smart-4d6f1f97-02e4-45e8-985c-b9f3f752ba70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218019985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4218019985
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.990355089
Short name T510
Test name
Test status
Simulation time 31219334 ps
CPU time 0.58 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 182232 kb
Host smart-6ae4a1c0-24fb-4232-a845-b374e9e34b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990355089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.990355089
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1514607298
Short name T495
Test name
Test status
Simulation time 36942575 ps
CPU time 0.58 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 182220 kb
Host smart-ca5d43b5-3754-4cc0-a856-38cf97a81483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514607298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1514607298
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.565334122
Short name T468
Test name
Test status
Simulation time 56893220 ps
CPU time 0.57 seconds
Started Jun 25 05:42:14 PM PDT 24
Finished Jun 25 05:42:16 PM PDT 24
Peak memory 182008 kb
Host smart-830ea44b-aa6c-419f-befc-b9813330aad8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565334122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.565334122
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3645641657
Short name T489
Test name
Test status
Simulation time 13223752 ps
CPU time 0.55 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:16 PM PDT 24
Peak memory 181816 kb
Host smart-07d0eca5-e79d-487e-ad97-34e20de724d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645641657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3645641657
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3449334878
Short name T545
Test name
Test status
Simulation time 183071136 ps
CPU time 0.85 seconds
Started Jun 25 05:41:57 PM PDT 24
Finished Jun 25 05:41:59 PM PDT 24
Peak memory 182316 kb
Host smart-c2a04a82-ebb5-4fd7-a3f7-d66405532c81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449334878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3449334878
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1995784281
Short name T481
Test name
Test status
Simulation time 131117557 ps
CPU time 1.55 seconds
Started Jun 25 05:41:56 PM PDT 24
Finished Jun 25 05:41:59 PM PDT 24
Peak memory 182464 kb
Host smart-f556a1f2-cc17-4a50-86d5-1d0a4e4eb05c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995784281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1995784281
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3910699632
Short name T565
Test name
Test status
Simulation time 17314497 ps
CPU time 0.55 seconds
Started Jun 25 05:41:56 PM PDT 24
Finished Jun 25 05:41:58 PM PDT 24
Peak memory 181960 kb
Host smart-7a3f71de-ab99-4224-b484-2e9fb63be4a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910699632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3910699632
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1114416426
Short name T44
Test name
Test status
Simulation time 43967313 ps
CPU time 0.64 seconds
Started Jun 25 05:41:59 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 193420 kb
Host smart-ac56b254-91a3-4cfb-833e-e7beaca7f361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114416426 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1114416426
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1373997153
Short name T94
Test name
Test status
Simulation time 18566255 ps
CPU time 0.57 seconds
Started Jun 25 05:41:57 PM PDT 24
Finished Jun 25 05:41:59 PM PDT 24
Peak memory 182160 kb
Host smart-9447df61-3531-41c8-a716-f74a3e8e88af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373997153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1373997153
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1020406334
Short name T509
Test name
Test status
Simulation time 22110187 ps
CPU time 0.57 seconds
Started Jun 25 05:41:52 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 182244 kb
Host smart-c3caf5f0-c7b1-41b7-a12b-f68e15c29aad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020406334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1020406334
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4093777881
Short name T103
Test name
Test status
Simulation time 71335986 ps
CPU time 0.62 seconds
Started Jun 25 05:41:53 PM PDT 24
Finished Jun 25 05:41:55 PM PDT 24
Peak memory 191000 kb
Host smart-a981b250-9ece-4089-9468-0864c07be64c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093777881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4093777881
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.52243955
Short name T521
Test name
Test status
Simulation time 303111288 ps
CPU time 2.53 seconds
Started Jun 25 05:42:05 PM PDT 24
Finished Jun 25 05:42:09 PM PDT 24
Peak memory 196944 kb
Host smart-d78a34f6-8348-4c07-9942-a6771bf9f3aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52243955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.52243955
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.335982087
Short name T30
Test name
Test status
Simulation time 51424499 ps
CPU time 0.85 seconds
Started Jun 25 05:41:55 PM PDT 24
Finished Jun 25 05:41:57 PM PDT 24
Peak memory 182588 kb
Host smart-d9dc8a08-fcb4-46c7-89e4-1ec789e80a15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335982087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.335982087
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.577263494
Short name T475
Test name
Test status
Simulation time 39518149 ps
CPU time 0.56 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 182216 kb
Host smart-85770b63-1a40-4600-a3d7-81eb3fac5dbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577263494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.577263494
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2845266454
Short name T562
Test name
Test status
Simulation time 54384904 ps
CPU time 0.59 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:11 PM PDT 24
Peak memory 182232 kb
Host smart-842ca6b8-ac58-4c52-93bb-1748b701a36c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845266454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2845266454
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.315906325
Short name T570
Test name
Test status
Simulation time 14968336 ps
CPU time 0.58 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 182236 kb
Host smart-fc31f426-70cd-4975-9bc1-fb0ff627fa21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315906325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.315906325
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3840942674
Short name T470
Test name
Test status
Simulation time 31241435 ps
CPU time 0.56 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:13 PM PDT 24
Peak memory 182192 kb
Host smart-4c767c26-f4d9-4166-a9a6-6d1ea4ec69e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840942674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3840942674
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.375328664
Short name T556
Test name
Test status
Simulation time 32898394 ps
CPU time 0.55 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 181876 kb
Host smart-492f06fa-bc2e-4fd2-9bb8-3e0c0f51b329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375328664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.375328664
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1938317948
Short name T535
Test name
Test status
Simulation time 33739373 ps
CPU time 0.53 seconds
Started Jun 25 05:42:15 PM PDT 24
Finished Jun 25 05:42:16 PM PDT 24
Peak memory 181892 kb
Host smart-5c70d14c-d971-40de-ae62-ab2211b86e18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938317948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1938317948
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3773975674
Short name T472
Test name
Test status
Simulation time 14692915 ps
CPU time 0.59 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:42:11 PM PDT 24
Peak memory 182228 kb
Host smart-4f0c55f8-458d-4e02-9a40-c06ea222917c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773975674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3773975674
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1746974530
Short name T564
Test name
Test status
Simulation time 19229495 ps
CPU time 0.58 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 182208 kb
Host smart-0dd8b086-d339-4979-9b83-bd2bb2ce3f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746974530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1746974530
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1594345789
Short name T479
Test name
Test status
Simulation time 18590787 ps
CPU time 0.6 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 182220 kb
Host smart-7893212f-07ba-471a-9c79-9c7942e30e8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594345789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1594345789
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1859531830
Short name T474
Test name
Test status
Simulation time 49646867 ps
CPU time 0.59 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 182224 kb
Host smart-a428d355-dbe8-46cf-b77f-bcfcf14509ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859531830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1859531830
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3824189152
Short name T580
Test name
Test status
Simulation time 20846574 ps
CPU time 0.65 seconds
Started Jun 25 05:41:56 PM PDT 24
Finished Jun 25 05:41:58 PM PDT 24
Peak memory 182236 kb
Host smart-2f9093f7-31b3-4b44-bab9-4435e15b40df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824189152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3824189152
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1444134968
Short name T469
Test name
Test status
Simulation time 37625378 ps
CPU time 1.47 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:42:12 PM PDT 24
Peak memory 192492 kb
Host smart-c104c76c-c125-482a-8230-4e366a72651c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444134968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1444134968
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2919657090
Short name T96
Test name
Test status
Simulation time 59986455 ps
CPU time 0.58 seconds
Started Jun 25 05:41:52 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 182320 kb
Host smart-d7a0986d-9179-4a0b-b5d3-740ee9fe7145
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919657090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2919657090
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.437030682
Short name T58
Test name
Test status
Simulation time 114543513 ps
CPU time 0.82 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:00 PM PDT 24
Peak memory 194808 kb
Host smart-0d91f180-bdf6-4df3-bacb-bb8f9ed67401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437030682 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.437030682
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.862213416
Short name T98
Test name
Test status
Simulation time 13880630 ps
CPU time 0.57 seconds
Started Jun 25 05:41:55 PM PDT 24
Finished Jun 25 05:41:57 PM PDT 24
Peak memory 182300 kb
Host smart-a14bd1a1-0c29-48c9-be65-74bafd6240de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862213416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.862213416
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.471904348
Short name T506
Test name
Test status
Simulation time 46498614 ps
CPU time 0.58 seconds
Started Jun 25 05:41:54 PM PDT 24
Finished Jun 25 05:41:56 PM PDT 24
Peak memory 182228 kb
Host smart-260e772d-cc48-447e-839c-1772fa61eef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471904348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.471904348
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3401454536
Short name T501
Test name
Test status
Simulation time 20393281 ps
CPU time 0.64 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:00 PM PDT 24
Peak memory 191540 kb
Host smart-105b249c-a397-4970-8017-8a245ee603fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401454536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3401454536
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.158485060
Short name T520
Test name
Test status
Simulation time 697676051 ps
CPU time 2.91 seconds
Started Jun 25 05:41:49 PM PDT 24
Finished Jun 25 05:41:55 PM PDT 24
Peak memory 197104 kb
Host smart-6bbec77c-a0b8-438f-94f9-06fe38e6efc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158485060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.158485060
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2557303688
Short name T508
Test name
Test status
Simulation time 164296444 ps
CPU time 1.03 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 194272 kb
Host smart-29ce0925-9b2b-4960-8ca8-486742e45dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557303688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2557303688
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3365467665
Short name T536
Test name
Test status
Simulation time 46968910 ps
CPU time 0.55 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 182244 kb
Host smart-063fa0e7-cb79-461a-95d2-f6155a2b91a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365467665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3365467665
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.679884684
Short name T554
Test name
Test status
Simulation time 46423213 ps
CPU time 0.57 seconds
Started Jun 25 05:42:10 PM PDT 24
Finished Jun 25 05:42:13 PM PDT 24
Peak memory 182160 kb
Host smart-baf53e1d-d32d-4a43-a999-fad558616d79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679884684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.679884684
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1338168414
Short name T547
Test name
Test status
Simulation time 44303009 ps
CPU time 0.57 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:42:11 PM PDT 24
Peak memory 182164 kb
Host smart-b744fa7a-b924-4a75-ae16-0c2261c5cfd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338168414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1338168414
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.315806298
Short name T572
Test name
Test status
Simulation time 30184679 ps
CPU time 0.59 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 182224 kb
Host smart-b402795c-189b-4fbf-bf30-937c2eb491dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315806298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.315806298
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.363059154
Short name T529
Test name
Test status
Simulation time 200245360 ps
CPU time 0.58 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:09 PM PDT 24
Peak memory 182236 kb
Host smart-63d4603e-b205-48a7-bbe8-bc42b18a2a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363059154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.363059154
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1224006886
Short name T460
Test name
Test status
Simulation time 13129671 ps
CPU time 0.57 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 182160 kb
Host smart-f56e1754-78f2-4725-8cb0-2737bc6d9605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224006886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1224006886
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3084675022
Short name T494
Test name
Test status
Simulation time 41455351 ps
CPU time 0.57 seconds
Started Jun 25 05:42:13 PM PDT 24
Finished Jun 25 05:42:15 PM PDT 24
Peak memory 182324 kb
Host smart-5d7737f6-49da-419b-b218-ae1ece3af308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084675022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3084675022
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.705810100
Short name T523
Test name
Test status
Simulation time 11253507 ps
CPU time 0.54 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:42:14 PM PDT 24
Peak memory 181680 kb
Host smart-3910cc52-63c4-4c4a-a983-f7cae977de8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705810100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.705810100
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2427509562
Short name T568
Test name
Test status
Simulation time 14070613 ps
CPU time 0.55 seconds
Started Jun 25 05:42:10 PM PDT 24
Finished Jun 25 05:42:13 PM PDT 24
Peak memory 181848 kb
Host smart-f56a32b0-3155-4041-a8f5-11a789b0b446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427509562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2427509562
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4206132710
Short name T573
Test name
Test status
Simulation time 39695454 ps
CPU time 0.56 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:42:11 PM PDT 24
Peak memory 182200 kb
Host smart-f3aa47ce-8250-490f-af85-f2ce690869ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206132710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4206132710
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1847989170
Short name T500
Test name
Test status
Simulation time 181868716 ps
CPU time 0.95 seconds
Started Jun 25 05:41:52 PM PDT 24
Finished Jun 25 05:41:55 PM PDT 24
Peak memory 196972 kb
Host smart-273312fa-62da-4044-9f81-6f040a6d2678
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847989170 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1847989170
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1418532044
Short name T485
Test name
Test status
Simulation time 14968020 ps
CPU time 0.57 seconds
Started Jun 25 05:41:51 PM PDT 24
Finished Jun 25 05:41:54 PM PDT 24
Peak memory 182316 kb
Host smart-403268bc-6693-4d47-bbca-76b762c85d25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418532044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1418532044
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.563544305
Short name T557
Test name
Test status
Simulation time 21353393 ps
CPU time 0.56 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:00 PM PDT 24
Peak memory 181636 kb
Host smart-b4c83a14-8535-4d86-9f11-4a58ea64002b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563544305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.563544305
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3927124513
Short name T530
Test name
Test status
Simulation time 75573275 ps
CPU time 0.69 seconds
Started Jun 25 05:41:50 PM PDT 24
Finished Jun 25 05:41:53 PM PDT 24
Peak memory 192712 kb
Host smart-81530fee-4a10-4ec9-a10d-5ed6312d78ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927124513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3927124513
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.943578480
Short name T491
Test name
Test status
Simulation time 373770768 ps
CPU time 3.21 seconds
Started Jun 25 05:41:50 PM PDT 24
Finished Jun 25 05:41:56 PM PDT 24
Peak memory 197100 kb
Host smart-dfd5f0b5-9185-42c0-bf6e-8aee7e183f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943578480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.943578480
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4070984390
Short name T111
Test name
Test status
Simulation time 116838696 ps
CPU time 1.38 seconds
Started Jun 25 05:41:52 PM PDT 24
Finished Jun 25 05:41:55 PM PDT 24
Peak memory 194812 kb
Host smart-b6f340f8-6b6f-4252-9413-ef975c73c8ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070984390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.4070984390
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2175404795
Short name T32
Test name
Test status
Simulation time 38620182 ps
CPU time 0.9 seconds
Started Jun 25 05:42:03 PM PDT 24
Finished Jun 25 05:42:07 PM PDT 24
Peak memory 196184 kb
Host smart-f20110bb-c200-456a-b1b6-3472d935dc66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175404795 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2175404795
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3305599095
Short name T101
Test name
Test status
Simulation time 30202739 ps
CPU time 0.61 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:01 PM PDT 24
Peak memory 182324 kb
Host smart-5e065c21-dcdf-4e2c-8bb2-505e6ef3bfbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305599095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3305599095
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4267144328
Short name T490
Test name
Test status
Simulation time 23877668 ps
CPU time 0.56 seconds
Started Jun 25 05:41:59 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 181680 kb
Host smart-286c865c-ba7b-4999-829a-e2ab7e400175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267144328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4267144328
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1758251280
Short name T534
Test name
Test status
Simulation time 29074440 ps
CPU time 0.73 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 191796 kb
Host smart-b193c933-49af-4861-8255-9906f0528718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758251280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1758251280
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3641877546
Short name T466
Test name
Test status
Simulation time 60217313 ps
CPU time 3 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:06 PM PDT 24
Peak memory 197140 kb
Host smart-0caa3d4e-0217-4e9f-b923-b197d2e7fd86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641877546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3641877546
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1085572172
Short name T473
Test name
Test status
Simulation time 244319901 ps
CPU time 1.1 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 194440 kb
Host smart-72bdd5f2-6ec0-448d-9044-6cfbc4a46aa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085572172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1085572172
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3053546179
Short name T461
Test name
Test status
Simulation time 147230331 ps
CPU time 0.89 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 196504 kb
Host smart-b727bfab-601c-4370-ac1e-48178b4ffcff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053546179 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3053546179
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.296621611
Short name T527
Test name
Test status
Simulation time 86406103 ps
CPU time 0.6 seconds
Started Jun 25 05:42:06 PM PDT 24
Finished Jun 25 05:42:09 PM PDT 24
Peak memory 182316 kb
Host smart-ac38c55f-887a-4c37-bf21-1e255b77cb91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296621611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.296621611
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3871970
Short name T499
Test name
Test status
Simulation time 69966373 ps
CPU time 0.6 seconds
Started Jun 25 05:42:08 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 182192 kb
Host smart-7bce410f-c925-4f53-a33a-5e4bf198d6fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3871970
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3869813031
Short name T104
Test name
Test status
Simulation time 74578714 ps
CPU time 0.75 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:10 PM PDT 24
Peak memory 192964 kb
Host smart-cbc8eed8-4a17-4364-8d51-384b974a6325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869813031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3869813031
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1165138461
Short name T574
Test name
Test status
Simulation time 57833044 ps
CPU time 1.2 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:01 PM PDT 24
Peak memory 197132 kb
Host smart-54314423-2d50-486d-8801-e432ff945cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165138461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1165138461
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1166436757
Short name T112
Test name
Test status
Simulation time 92076871 ps
CPU time 1.17 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 194768 kb
Host smart-3ab0f61a-8f9f-4c68-ad2c-e73665196838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166436757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1166436757
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2162073211
Short name T567
Test name
Test status
Simulation time 136535408 ps
CPU time 0.72 seconds
Started Jun 25 05:42:01 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 193980 kb
Host smart-dd61cd6f-2b82-4eec-8240-2e426314e9e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162073211 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2162073211
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3663778729
Short name T524
Test name
Test status
Simulation time 39012369 ps
CPU time 0.56 seconds
Started Jun 25 05:41:59 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 181388 kb
Host smart-94010d10-85da-4146-9020-63114e29dc5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663778729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3663778729
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4071605061
Short name T102
Test name
Test status
Simulation time 15719886 ps
CPU time 0.71 seconds
Started Jun 25 05:42:02 PM PDT 24
Finished Jun 25 05:42:05 PM PDT 24
Peak memory 192436 kb
Host smart-f6d97efd-2aa1-430e-8abb-324f5d7db2e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071605061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.4071605061
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2598107621
Short name T47
Test name
Test status
Simulation time 258008121 ps
CPU time 2.39 seconds
Started Jun 25 05:41:58 PM PDT 24
Finished Jun 25 05:42:03 PM PDT 24
Peak memory 197120 kb
Host smart-29a747c6-5bd3-4bb7-b6ca-3cdfd32c8c68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598107621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2598107621
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4099788098
Short name T511
Test name
Test status
Simulation time 279173078 ps
CPU time 1.19 seconds
Started Jun 25 05:42:07 PM PDT 24
Finished Jun 25 05:42:11 PM PDT 24
Peak memory 194676 kb
Host smart-7a9519fe-ab49-4e03-b8f3-9e33edaabb53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099788098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4099788098
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.739936134
Short name T561
Test name
Test status
Simulation time 243739460 ps
CPU time 0.83 seconds
Started Jun 25 05:42:05 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 196260 kb
Host smart-42361147-6a2a-4ecc-812f-f2048e8928cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739936134 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.739936134
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1697683183
Short name T477
Test name
Test status
Simulation time 39840000 ps
CPU time 0.56 seconds
Started Jun 25 05:41:59 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 181480 kb
Host smart-3250ff88-234b-4018-9c69-e1f3bdeffa22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697683183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1697683183
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2530340658
Short name T503
Test name
Test status
Simulation time 14453627 ps
CPU time 0.61 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 182252 kb
Host smart-6deee2c4-5310-47fc-a469-ad3f350929f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530340658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2530340658
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.83768547
Short name T90
Test name
Test status
Simulation time 343006110 ps
CPU time 0.82 seconds
Started Jun 25 05:41:59 PM PDT 24
Finished Jun 25 05:42:02 PM PDT 24
Peak memory 192848 kb
Host smart-706f5103-f91d-48e5-bffc-075203f73207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83768547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_time
r_same_csr_outstanding.83768547
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.502574125
Short name T487
Test name
Test status
Simulation time 128874590 ps
CPU time 1.33 seconds
Started Jun 25 05:42:00 PM PDT 24
Finished Jun 25 05:42:04 PM PDT 24
Peak memory 197108 kb
Host smart-616416c7-6e97-4a5e-b52a-f948dd8890fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502574125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.502574125
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4025786481
Short name T558
Test name
Test status
Simulation time 133994216 ps
CPU time 1.41 seconds
Started Jun 25 05:42:04 PM PDT 24
Finished Jun 25 05:42:08 PM PDT 24
Peak memory 195040 kb
Host smart-44ad8052-ce49-4fb7-b345-a8f486ff3527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025786481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4025786481
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1838150559
Short name T55
Test name
Test status
Simulation time 583453545878 ps
CPU time 889.53 seconds
Started Jun 25 05:42:12 PM PDT 24
Finished Jun 25 05:57:04 PM PDT 24
Peak memory 183144 kb
Host smart-dea70b00-e102-42c7-8d2c-b3077e26ed8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838150559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1838150559
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.481305597
Short name T429
Test name
Test status
Simulation time 168704720644 ps
CPU time 251.64 seconds
Started Jun 25 05:42:15 PM PDT 24
Finished Jun 25 05:46:27 PM PDT 24
Peak memory 183140 kb
Host smart-b70e1081-3414-4cc3-be04-d080acf1d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481305597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.481305597
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2816295047
Short name T144
Test name
Test status
Simulation time 843393661837 ps
CPU time 566.83 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:51:40 PM PDT 24
Peak memory 191320 kb
Host smart-c9953e5c-c463-4745-819c-e7401a17f41d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816295047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2816295047
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1525973127
Short name T386
Test name
Test status
Simulation time 186122184315 ps
CPU time 282.1 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:46:56 PM PDT 24
Peak memory 183140 kb
Host smart-91b1e36b-1d76-4aa1-a730-88695e3c8e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525973127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1525973127
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2009437220
Short name T129
Test name
Test status
Simulation time 730846864729 ps
CPU time 295.11 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:47:07 PM PDT 24
Peak memory 183136 kb
Host smart-a2ceab3e-4f24-4b19-bee4-40a61bc4df10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009437220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2009437220
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3091409774
Short name T374
Test name
Test status
Simulation time 124597918160 ps
CPU time 158.28 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:44:52 PM PDT 24
Peak memory 183084 kb
Host smart-a47abe93-460b-40c0-b9de-25259df09f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091409774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3091409774
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2557332908
Short name T218
Test name
Test status
Simulation time 207547452299 ps
CPU time 392.31 seconds
Started Jun 25 05:42:11 PM PDT 24
Finished Jun 25 05:48:45 PM PDT 24
Peak memory 191336 kb
Host smart-a3ec367d-2b94-41e0-9429-4e2542381348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557332908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2557332908
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2221368597
Short name T69
Test name
Test status
Simulation time 37288789848 ps
CPU time 54.19 seconds
Started Jun 25 05:42:09 PM PDT 24
Finished Jun 25 05:43:05 PM PDT 24
Peak memory 183144 kb
Host smart-fef12115-42f6-4a97-8e44-0de17932f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221368597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2221368597
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2781058153
Short name T17
Test name
Test status
Simulation time 118759121 ps
CPU time 0.84 seconds
Started Jun 25 05:42:12 PM PDT 24
Finished Jun 25 05:42:15 PM PDT 24
Peak memory 213268 kb
Host smart-8e154136-e287-4d65-bda5-f2dc824d87f6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781058153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2781058153
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2042214989
Short name T453
Test name
Test status
Simulation time 321986476333 ps
CPU time 216.92 seconds
Started Jun 25 05:42:12 PM PDT 24
Finished Jun 25 05:45:51 PM PDT 24
Peak memory 194396 kb
Host smart-1b5a6887-8c57-43f4-8677-854d0887d92f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042214989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2042214989
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2480090991
Short name T7
Test name
Test status
Simulation time 153240745707 ps
CPU time 54.97 seconds
Started Jun 25 05:42:30 PM PDT 24
Finished Jun 25 05:43:26 PM PDT 24
Peak memory 183144 kb
Host smart-bd0c1d90-acfa-4a51-a425-a3e5f034ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480090991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2480090991
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.4250103971
Short name T287
Test name
Test status
Simulation time 150594065713 ps
CPU time 84.93 seconds
Started Jun 25 05:42:35 PM PDT 24
Finished Jun 25 05:44:01 PM PDT 24
Peak memory 191352 kb
Host smart-293b798c-1913-4a2c-9bd9-0ef2c409f7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250103971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.4250103971
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.331090297
Short name T53
Test name
Test status
Simulation time 97873054898 ps
CPU time 93.42 seconds
Started Jun 25 05:42:26 PM PDT 24
Finished Jun 25 05:44:00 PM PDT 24
Peak memory 183160 kb
Host smart-2d285f94-781a-431e-abba-28a2244b2fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331090297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.331090297
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2107951356
Short name T241
Test name
Test status
Simulation time 240670459218 ps
CPU time 506.03 seconds
Started Jun 25 05:43:22 PM PDT 24
Finished Jun 25 05:51:49 PM PDT 24
Peak memory 191296 kb
Host smart-ac43bb3f-12e0-488b-a6af-a5a526e71c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107951356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2107951356
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3190029046
Short name T235
Test name
Test status
Simulation time 72216706858 ps
CPU time 301.3 seconds
Started Jun 25 05:43:24 PM PDT 24
Finished Jun 25 05:48:27 PM PDT 24
Peak memory 191344 kb
Host smart-201c2432-a320-4a8f-8e1f-e043cec0e304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190029046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3190029046
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2289759224
Short name T344
Test name
Test status
Simulation time 45194996170 ps
CPU time 66.92 seconds
Started Jun 25 05:43:22 PM PDT 24
Finished Jun 25 05:44:30 PM PDT 24
Peak memory 183144 kb
Host smart-671f401b-45ab-48c8-ae01-328679cd2612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289759224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2289759224
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1773079626
Short name T284
Test name
Test status
Simulation time 225677987808 ps
CPU time 567.51 seconds
Started Jun 25 05:43:22 PM PDT 24
Finished Jun 25 05:52:51 PM PDT 24
Peak memory 193580 kb
Host smart-da78001f-0002-4f39-9cd0-510a6f56fec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773079626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1773079626
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2570276111
Short name T313
Test name
Test status
Simulation time 48703663207 ps
CPU time 31.18 seconds
Started Jun 25 05:43:22 PM PDT 24
Finished Jun 25 05:43:54 PM PDT 24
Peak memory 183140 kb
Host smart-91358b2e-8170-40da-bb1a-c25c83a4e767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570276111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2570276111
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2715771471
Short name T326
Test name
Test status
Simulation time 368433511913 ps
CPU time 648.26 seconds
Started Jun 25 05:43:31 PM PDT 24
Finished Jun 25 05:54:20 PM PDT 24
Peak memory 191280 kb
Host smart-c5abcb05-783c-4f9c-b800-b17c194a8b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715771471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2715771471
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1310014503
Short name T316
Test name
Test status
Simulation time 94734074676 ps
CPU time 81.43 seconds
Started Jun 25 05:43:31 PM PDT 24
Finished Jun 25 05:44:54 PM PDT 24
Peak memory 183144 kb
Host smart-2af6cd74-d676-48ae-aeb7-39e8c7f89872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310014503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1310014503
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1095755758
Short name T216
Test name
Test status
Simulation time 16313779214 ps
CPU time 25.87 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:43:01 PM PDT 24
Peak memory 183132 kb
Host smart-4b39481b-b7e2-47be-a410-2575f7905975
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095755758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1095755758
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2992652474
Short name T435
Test name
Test status
Simulation time 63925942346 ps
CPU time 90.18 seconds
Started Jun 25 05:42:24 PM PDT 24
Finished Jun 25 05:43:55 PM PDT 24
Peak memory 183164 kb
Host smart-02cb8c57-327d-4d78-abc4-9e89e742889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992652474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2992652474
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1943008055
Short name T289
Test name
Test status
Simulation time 7961192045 ps
CPU time 1.85 seconds
Started Jun 25 05:42:32 PM PDT 24
Finished Jun 25 05:42:34 PM PDT 24
Peak memory 191348 kb
Host smart-acab92a6-bc74-408d-a16a-8066aaeb6b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943008055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1943008055
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.708447746
Short name T285
Test name
Test status
Simulation time 256494076484 ps
CPU time 394.58 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:49:13 PM PDT 24
Peak memory 195552 kb
Host smart-26a1e494-d187-4552-9a3c-71631fafc75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708447746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
708447746
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/112.rv_timer_random.1031745932
Short name T353
Test name
Test status
Simulation time 97939089000 ps
CPU time 109.99 seconds
Started Jun 25 05:43:31 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 191332 kb
Host smart-75b74e4a-4360-4fd8-846c-2a09c5d431d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031745932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1031745932
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1580640147
Short name T142
Test name
Test status
Simulation time 237820838745 ps
CPU time 172.19 seconds
Started Jun 25 05:43:30 PM PDT 24
Finished Jun 25 05:46:23 PM PDT 24
Peak memory 191328 kb
Host smart-00d3e740-c0ea-44c3-92ec-b9cdf0c76ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580640147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1580640147
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1606972421
Short name T159
Test name
Test status
Simulation time 227533230517 ps
CPU time 130.85 seconds
Started Jun 25 05:43:31 PM PDT 24
Finished Jun 25 05:45:42 PM PDT 24
Peak memory 183124 kb
Host smart-c45d74ec-8313-404e-afb3-f942ca18db31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606972421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1606972421
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2397424254
Short name T231
Test name
Test status
Simulation time 21075968463 ps
CPU time 169.45 seconds
Started Jun 25 05:43:31 PM PDT 24
Finished Jun 25 05:46:21 PM PDT 24
Peak memory 183148 kb
Host smart-0a58ce88-f094-468f-b860-9fa14e7374d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397424254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2397424254
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1936390511
Short name T365
Test name
Test status
Simulation time 33823751906 ps
CPU time 45.36 seconds
Started Jun 25 05:42:29 PM PDT 24
Finished Jun 25 05:43:15 PM PDT 24
Peak memory 183100 kb
Host smart-60aa0d0e-8de4-41dc-8d9c-8488b50dfaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936390511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1936390511
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.808118645
Short name T405
Test name
Test status
Simulation time 175983329 ps
CPU time 1.42 seconds
Started Jun 25 05:42:32 PM PDT 24
Finished Jun 25 05:42:34 PM PDT 24
Peak memory 183060 kb
Host smart-74455485-e966-4382-bb09-7eeca3c95761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808118645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.808118645
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.313652780
Short name T343
Test name
Test status
Simulation time 2218623001293 ps
CPU time 2055.08 seconds
Started Jun 25 05:43:40 PM PDT 24
Finished Jun 25 06:17:56 PM PDT 24
Peak memory 191344 kb
Host smart-356a7a2e-4054-4ecb-accc-5a5b9241357f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313652780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.313652780
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1510296548
Short name T291
Test name
Test status
Simulation time 163412261623 ps
CPU time 1462.24 seconds
Started Jun 25 05:43:43 PM PDT 24
Finished Jun 25 06:08:06 PM PDT 24
Peak memory 194864 kb
Host smart-99e677d9-3a78-42b6-a25c-2f01bda42d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510296548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1510296548
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3104163254
Short name T439
Test name
Test status
Simulation time 97131392275 ps
CPU time 51.97 seconds
Started Jun 25 05:43:40 PM PDT 24
Finished Jun 25 05:44:33 PM PDT 24
Peak memory 183152 kb
Host smart-42a60cb1-675e-46d4-b96a-7ba621eb75a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104163254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3104163254
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.65496197
Short name T8
Test name
Test status
Simulation time 308268835289 ps
CPU time 114.35 seconds
Started Jun 25 05:43:38 PM PDT 24
Finished Jun 25 05:45:34 PM PDT 24
Peak memory 183124 kb
Host smart-8f786975-5020-40d5-81c0-371b85df38b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65496197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.65496197
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2211047686
Short name T82
Test name
Test status
Simulation time 73766575877 ps
CPU time 118.77 seconds
Started Jun 25 05:43:39 PM PDT 24
Finished Jun 25 05:45:38 PM PDT 24
Peak memory 191324 kb
Host smart-10feb2da-adb6-41c9-9354-7f708e338f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211047686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2211047686
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2162495039
Short name T54
Test name
Test status
Simulation time 40806768542 ps
CPU time 15.63 seconds
Started Jun 25 05:43:41 PM PDT 24
Finished Jun 25 05:43:57 PM PDT 24
Peak memory 183072 kb
Host smart-2da717ae-9f3e-422f-8e7b-fb512a140b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162495039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2162495039
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4115528737
Short name T297
Test name
Test status
Simulation time 329587577767 ps
CPU time 160.99 seconds
Started Jun 25 05:43:42 PM PDT 24
Finished Jun 25 05:46:23 PM PDT 24
Peak memory 191328 kb
Host smart-640c3cf4-02e0-4693-8a03-1e4eaa0af2f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115528737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4115528737
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1386847526
Short name T288
Test name
Test status
Simulation time 409403301189 ps
CPU time 204.7 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:46:00 PM PDT 24
Peak memory 183128 kb
Host smart-31ad2778-fed7-4f5d-be72-abf1678d6228
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386847526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1386847526
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3673357380
Short name T434
Test name
Test status
Simulation time 74602075836 ps
CPU time 82.61 seconds
Started Jun 25 05:42:30 PM PDT 24
Finished Jun 25 05:43:53 PM PDT 24
Peak memory 183088 kb
Host smart-512c23c4-cbc9-43a3-af1c-57cdb02f649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673357380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3673357380
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2249393894
Short name T131
Test name
Test status
Simulation time 406520603791 ps
CPU time 1647.01 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 06:10:02 PM PDT 24
Peak memory 191280 kb
Host smart-41cb80f0-9440-4670-9596-d0086a8a0bb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249393894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2249393894
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.52923843
Short name T157
Test name
Test status
Simulation time 16493299336 ps
CPU time 35.35 seconds
Started Jun 25 05:42:25 PM PDT 24
Finished Jun 25 05:43:01 PM PDT 24
Peak memory 183148 kb
Host smart-b63459cc-abd4-471a-b6eb-15620984e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52923843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.52923843
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.958612229
Short name T426
Test name
Test status
Simulation time 18964867198 ps
CPU time 25.96 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:43:02 PM PDT 24
Peak memory 183112 kb
Host smart-0811f453-67d6-4e04-88a2-93bbddd98508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958612229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
958612229
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2305389144
Short name T75
Test name
Test status
Simulation time 254496857055 ps
CPU time 640.87 seconds
Started Jun 25 05:42:32 PM PDT 24
Finished Jun 25 05:53:14 PM PDT 24
Peak memory 208304 kb
Host smart-3c2f0726-321c-4a96-878d-f1bb0ba44b84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305389144 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2305389144
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.687946885
Short name T72
Test name
Test status
Simulation time 28985306162 ps
CPU time 46.67 seconds
Started Jun 25 05:43:42 PM PDT 24
Finished Jun 25 05:44:30 PM PDT 24
Peak memory 191356 kb
Host smart-ded6c8e9-c4d5-4362-8056-95cfd39da614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687946885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.687946885
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2569602478
Short name T276
Test name
Test status
Simulation time 34093548892 ps
CPU time 56.44 seconds
Started Jun 25 05:43:40 PM PDT 24
Finished Jun 25 05:44:37 PM PDT 24
Peak memory 183136 kb
Host smart-0ee49d47-e916-4671-9d52-68f5a60c2133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569602478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2569602478
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.509157288
Short name T168
Test name
Test status
Simulation time 590936168858 ps
CPU time 479.53 seconds
Started Jun 25 05:43:39 PM PDT 24
Finished Jun 25 05:51:39 PM PDT 24
Peak memory 191340 kb
Host smart-463a1d67-7d60-410f-aeb3-ada3fa42d00d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509157288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.509157288
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2312507492
Short name T187
Test name
Test status
Simulation time 931293435412 ps
CPU time 456.21 seconds
Started Jun 25 05:43:42 PM PDT 24
Finished Jun 25 05:51:19 PM PDT 24
Peak memory 191320 kb
Host smart-ef25aa9e-49e1-4c5b-80a6-20c94c3f3b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312507492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2312507492
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1306168390
Short name T153
Test name
Test status
Simulation time 568865407717 ps
CPU time 863.04 seconds
Started Jun 25 05:42:24 PM PDT 24
Finished Jun 25 05:56:47 PM PDT 24
Peak memory 183148 kb
Host smart-07d526cb-d36c-45b6-b185-90ae3d9315df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306168390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1306168390
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3965474589
Short name T370
Test name
Test status
Simulation time 792432166942 ps
CPU time 206.36 seconds
Started Jun 25 05:42:25 PM PDT 24
Finished Jun 25 05:45:51 PM PDT 24
Peak memory 183164 kb
Host smart-f31b67f3-4ff1-4474-9549-bde590c11746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965474589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3965474589
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3740994136
Short name T330
Test name
Test status
Simulation time 45451492706 ps
CPU time 234.41 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:46:30 PM PDT 24
Peak memory 191340 kb
Host smart-cd69277c-d12d-4920-9a60-d1aaa879e580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740994136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3740994136
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2895307367
Short name T345
Test name
Test status
Simulation time 195233507667 ps
CPU time 93.75 seconds
Started Jun 25 05:42:27 PM PDT 24
Finished Jun 25 05:44:01 PM PDT 24
Peak memory 183160 kb
Host smart-36bc90da-c3d2-457e-befe-5aab345fdd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895307367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2895307367
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/142.rv_timer_random.3752636810
Short name T197
Test name
Test status
Simulation time 31855098081 ps
CPU time 59.21 seconds
Started Jun 25 05:43:51 PM PDT 24
Finished Jun 25 05:44:51 PM PDT 24
Peak memory 191332 kb
Host smart-5a64d4cc-7b7c-4060-9066-7ba72293cfd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752636810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3752636810
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2946860082
Short name T251
Test name
Test status
Simulation time 476825985042 ps
CPU time 591.71 seconds
Started Jun 25 05:43:52 PM PDT 24
Finished Jun 25 05:53:45 PM PDT 24
Peak memory 194832 kb
Host smart-fc352974-0211-4528-88e9-697122a2edd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946860082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2946860082
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3478539117
Short name T183
Test name
Test status
Simulation time 146110216749 ps
CPU time 661.69 seconds
Started Jun 25 05:43:50 PM PDT 24
Finished Jun 25 05:54:53 PM PDT 24
Peak memory 191336 kb
Host smart-c5ff9b4f-f3b9-4fb6-80ce-0b531fc5a546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478539117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3478539117
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3599472663
Short name T117
Test name
Test status
Simulation time 47909591135 ps
CPU time 67.81 seconds
Started Jun 25 05:43:50 PM PDT 24
Finished Jun 25 05:44:59 PM PDT 24
Peak memory 183136 kb
Host smart-93201004-78cd-430a-9fb2-103f9ace9af3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599472663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3599472663
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2835990310
Short name T209
Test name
Test status
Simulation time 129902616993 ps
CPU time 424.07 seconds
Started Jun 25 05:43:51 PM PDT 24
Finished Jun 25 05:50:56 PM PDT 24
Peak memory 191332 kb
Host smart-434e188c-575d-4642-8262-d30703f56322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835990310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2835990310
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3573393720
Short name T324
Test name
Test status
Simulation time 37126212202 ps
CPU time 56.54 seconds
Started Jun 25 05:43:49 PM PDT 24
Finished Jun 25 05:44:48 PM PDT 24
Peak memory 183140 kb
Host smart-99e02f32-3031-4d84-b0e6-8ab7a14f61a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573393720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3573393720
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1399486735
Short name T27
Test name
Test status
Simulation time 251708334613 ps
CPU time 132.44 seconds
Started Jun 25 05:42:35 PM PDT 24
Finished Jun 25 05:44:49 PM PDT 24
Peak memory 183152 kb
Host smart-ff53930a-896a-4de6-bf6e-9975c51fbd9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399486735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1399486735
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1896986430
Short name T448
Test name
Test status
Simulation time 487300988893 ps
CPU time 178.58 seconds
Started Jun 25 05:42:22 PM PDT 24
Finished Jun 25 05:45:21 PM PDT 24
Peak memory 183148 kb
Host smart-d0e2c211-504c-4b73-9f1c-4bac7e5d954a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896986430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1896986430
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.350775560
Short name T292
Test name
Test status
Simulation time 351234620837 ps
CPU time 957.45 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:58:35 PM PDT 24
Peak memory 191328 kb
Host smart-86e3a853-4324-4cb5-b85a-699ede8972dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350775560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.350775560
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2137281150
Short name T12
Test name
Test status
Simulation time 52047630157 ps
CPU time 59.14 seconds
Started Jun 25 05:42:35 PM PDT 24
Finished Jun 25 05:43:35 PM PDT 24
Peak memory 191336 kb
Host smart-7859f244-a27f-4b1f-9a5b-048d917177b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137281150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2137281150
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2676841627
Short name T208
Test name
Test status
Simulation time 1495448683493 ps
CPU time 795.89 seconds
Started Jun 25 05:42:37 PM PDT 24
Finished Jun 25 05:55:54 PM PDT 24
Peak memory 195980 kb
Host smart-72348990-7af0-409a-99b1-67b20ef9d182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676841627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2676841627
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.2525405949
Short name T244
Test name
Test status
Simulation time 73526414582 ps
CPU time 129.22 seconds
Started Jun 25 05:43:50 PM PDT 24
Finished Jun 25 05:46:01 PM PDT 24
Peak memory 191252 kb
Host smart-2071d8ef-9d3c-403d-bdb3-95650c3114aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525405949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2525405949
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.4031321545
Short name T149
Test name
Test status
Simulation time 6180403202 ps
CPU time 4.89 seconds
Started Jun 25 05:43:49 PM PDT 24
Finished Jun 25 05:43:55 PM PDT 24
Peak memory 183136 kb
Host smart-38d28412-1d17-4569-a887-888bdd5af5c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031321545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4031321545
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.4077903575
Short name T447
Test name
Test status
Simulation time 265173030740 ps
CPU time 132.19 seconds
Started Jun 25 05:43:50 PM PDT 24
Finished Jun 25 05:46:04 PM PDT 24
Peak memory 191336 kb
Host smart-eba30243-c312-44bb-a796-a93890406de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077903575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4077903575
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3894474463
Short name T9
Test name
Test status
Simulation time 84454246466 ps
CPU time 133.25 seconds
Started Jun 25 05:43:52 PM PDT 24
Finished Jun 25 05:46:06 PM PDT 24
Peak memory 194912 kb
Host smart-ecac0f60-1f6e-4af6-ae4b-65d0e7f11e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894474463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3894474463
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.221102128
Short name T184
Test name
Test status
Simulation time 108854597385 ps
CPU time 626.49 seconds
Started Jun 25 05:43:49 PM PDT 24
Finished Jun 25 05:54:17 PM PDT 24
Peak memory 191276 kb
Host smart-e9c0a58b-badd-4fe0-b688-dc3c4eb0e50f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221102128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.221102128
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1290620011
Short name T404
Test name
Test status
Simulation time 101418968905 ps
CPU time 79.77 seconds
Started Jun 25 05:43:53 PM PDT 24
Finished Jun 25 05:45:13 PM PDT 24
Peak memory 183132 kb
Host smart-9d35df29-1501-4a13-a16d-a1a367270ac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290620011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1290620011
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1991448907
Short name T193
Test name
Test status
Simulation time 217041082976 ps
CPU time 487.25 seconds
Started Jun 25 05:43:52 PM PDT 24
Finished Jun 25 05:52:00 PM PDT 24
Peak memory 191332 kb
Host smart-1a106580-7b43-43ae-a3b7-10555bca295e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991448907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1991448907
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3982855148
Short name T202
Test name
Test status
Simulation time 118660764861 ps
CPU time 209.21 seconds
Started Jun 25 05:43:51 PM PDT 24
Finished Jun 25 05:47:21 PM PDT 24
Peak memory 191200 kb
Host smart-70917013-2756-4a0b-b7e7-3602c689dfd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982855148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3982855148
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1364786844
Short name T322
Test name
Test status
Simulation time 40584230266 ps
CPU time 289.7 seconds
Started Jun 25 05:43:51 PM PDT 24
Finished Jun 25 05:48:42 PM PDT 24
Peak memory 183144 kb
Host smart-bef39b96-5209-4ae4-9339-35042dea3812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364786844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1364786844
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4025568633
Short name T310
Test name
Test status
Simulation time 8334269078 ps
CPU time 15.05 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:42:50 PM PDT 24
Peak memory 183152 kb
Host smart-72e2c61d-9d1e-4a99-8440-912259a65bdf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025568633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4025568633
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2339899556
Short name T440
Test name
Test status
Simulation time 115932821337 ps
CPU time 136.45 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:44:55 PM PDT 24
Peak memory 183156 kb
Host smart-63d94ca0-d08d-40d8-b966-c5ea9f66a300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339899556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2339899556
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.367131919
Short name T200
Test name
Test status
Simulation time 674175321367 ps
CPU time 711.33 seconds
Started Jun 25 05:42:32 PM PDT 24
Finished Jun 25 05:54:24 PM PDT 24
Peak memory 191340 kb
Host smart-1dee2638-8a57-4229-9962-8f740e869f3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367131919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.367131919
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.620534720
Short name T371
Test name
Test status
Simulation time 664255682 ps
CPU time 1.69 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:42:37 PM PDT 24
Peak memory 183088 kb
Host smart-c3f1e2e2-e9c4-412b-97c7-0ce187726ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620534720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.620534720
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3298908159
Short name T401
Test name
Test status
Simulation time 744518541758 ps
CPU time 341.14 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:48:18 PM PDT 24
Peak memory 194708 kb
Host smart-f0b3d941-0eff-4841-ad62-8e7bd497308c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298908159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3298908159
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2429652191
Short name T13
Test name
Test status
Simulation time 43744787929 ps
CPU time 129.21 seconds
Started Jun 25 05:42:35 PM PDT 24
Finished Jun 25 05:44:46 PM PDT 24
Peak memory 197860 kb
Host smart-a21a9396-d375-403e-9298-e0ddfb99bb4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429652191 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2429652191
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3534444199
Short name T140
Test name
Test status
Simulation time 46549995474 ps
CPU time 652.38 seconds
Started Jun 25 05:44:00 PM PDT 24
Finished Jun 25 05:54:53 PM PDT 24
Peak memory 191332 kb
Host smart-46c413d3-415a-434c-9011-3640d4cab0c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534444199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3534444199
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1950845337
Short name T286
Test name
Test status
Simulation time 101661031615 ps
CPU time 374.39 seconds
Started Jun 25 05:44:00 PM PDT 24
Finished Jun 25 05:50:15 PM PDT 24
Peak memory 191336 kb
Host smart-72bf8896-1a8c-4ab6-bc1c-e980c6fc8780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950845337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1950845337
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.605056067
Short name T278
Test name
Test status
Simulation time 148921539332 ps
CPU time 281.66 seconds
Started Jun 25 05:43:58 PM PDT 24
Finished Jun 25 05:48:41 PM PDT 24
Peak memory 191340 kb
Host smart-3ff6db25-2072-4039-9e02-61bdfd8dbba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605056067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.605056067
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1268352665
Short name T190
Test name
Test status
Simulation time 232525682020 ps
CPU time 102.97 seconds
Started Jun 25 05:43:57 PM PDT 24
Finished Jun 25 05:45:41 PM PDT 24
Peak memory 191356 kb
Host smart-79d01733-c2bc-4299-9364-eb73063b741f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268352665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1268352665
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.688116386
Short name T265
Test name
Test status
Simulation time 816463854679 ps
CPU time 351.85 seconds
Started Jun 25 05:43:58 PM PDT 24
Finished Jun 25 05:49:51 PM PDT 24
Peak memory 191344 kb
Host smart-f57d07c7-db86-4821-87f9-bb27a845cf00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688116386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.688116386
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4272164769
Short name T23
Test name
Test status
Simulation time 201236964473 ps
CPU time 110.15 seconds
Started Jun 25 05:43:58 PM PDT 24
Finished Jun 25 05:45:49 PM PDT 24
Peak memory 183140 kb
Host smart-c619ab39-007d-47b0-b83c-e333bae2f396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272164769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4272164769
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2018098930
Short name T422
Test name
Test status
Simulation time 46402879113 ps
CPU time 66.01 seconds
Started Jun 25 05:42:35 PM PDT 24
Finished Jun 25 05:43:42 PM PDT 24
Peak memory 183172 kb
Host smart-013733f7-c4d7-44e2-b075-62be9310ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018098930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2018098930
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3333706301
Short name T156
Test name
Test status
Simulation time 11513872596 ps
CPU time 16.5 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:42:56 PM PDT 24
Peak memory 183048 kb
Host smart-78f8b850-551b-43f4-9d3f-02adecd02c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333706301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3333706301
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3966486859
Short name T270
Test name
Test status
Simulation time 270904671556 ps
CPU time 170.21 seconds
Started Jun 25 05:42:33 PM PDT 24
Finished Jun 25 05:45:24 PM PDT 24
Peak memory 191348 kb
Host smart-ef8b98a5-2a81-4963-89a7-2178fe2035e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966486859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3966486859
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.475758926
Short name T176
Test name
Test status
Simulation time 17647158302 ps
CPU time 171.63 seconds
Started Jun 25 05:43:56 PM PDT 24
Finished Jun 25 05:46:49 PM PDT 24
Peak memory 183152 kb
Host smart-569548e6-2acb-482d-90e5-37599e4b8d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475758926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.475758926
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4094824462
Short name T215
Test name
Test status
Simulation time 418310236072 ps
CPU time 616.1 seconds
Started Jun 25 05:43:57 PM PDT 24
Finished Jun 25 05:54:14 PM PDT 24
Peak memory 193368 kb
Host smart-37b17647-9587-4bf5-b710-2f0462d49b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094824462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4094824462
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.312372344
Short name T227
Test name
Test status
Simulation time 546765264349 ps
CPU time 797.61 seconds
Started Jun 25 05:44:09 PM PDT 24
Finished Jun 25 05:57:27 PM PDT 24
Peak memory 191336 kb
Host smart-11ff9370-a881-418e-884f-f437eda5f890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312372344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.312372344
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3134693546
Short name T134
Test name
Test status
Simulation time 134414655462 ps
CPU time 104.86 seconds
Started Jun 25 05:44:06 PM PDT 24
Finished Jun 25 05:45:52 PM PDT 24
Peak memory 191324 kb
Host smart-d5cc48e6-647d-4447-849c-8245472e6ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134693546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3134693546
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1522501887
Short name T311
Test name
Test status
Simulation time 243880873812 ps
CPU time 289.99 seconds
Started Jun 25 05:44:05 PM PDT 24
Finished Jun 25 05:48:56 PM PDT 24
Peak memory 191348 kb
Host smart-3a0cd39d-5d5d-401f-aa4c-0a5094cafc36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522501887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1522501887
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3213962188
Short name T306
Test name
Test status
Simulation time 125577071316 ps
CPU time 73.15 seconds
Started Jun 25 05:44:08 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 191304 kb
Host smart-cfb0df84-7471-4e1b-bd58-fc9e43ada89d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213962188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3213962188
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3760599877
Short name T445
Test name
Test status
Simulation time 1354461437979 ps
CPU time 683.19 seconds
Started Jun 25 05:42:39 PM PDT 24
Finished Jun 25 05:54:03 PM PDT 24
Peak memory 183376 kb
Host smart-8bad7f29-a02b-4429-9858-9e074eb9f817
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760599877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3760599877
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3722037547
Short name T391
Test name
Test status
Simulation time 707914402121 ps
CPU time 207.18 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:46:06 PM PDT 24
Peak memory 183100 kb
Host smart-dbb65ff1-d561-4b55-a5cf-36ee54dec5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722037547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3722037547
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1127866295
Short name T196
Test name
Test status
Simulation time 104145684472 ps
CPU time 964.95 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:58:42 PM PDT 24
Peak memory 191348 kb
Host smart-7aa072ec-c68b-4bb7-9fdc-35e873116e24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127866295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1127866295
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2329153733
Short name T437
Test name
Test status
Simulation time 33458583065 ps
CPU time 31.87 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:43:07 PM PDT 24
Peak memory 183152 kb
Host smart-728e0405-b857-4e3f-8262-fd1cf87ec4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329153733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2329153733
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.4113407393
Short name T432
Test name
Test status
Simulation time 157036707249 ps
CPU time 80.11 seconds
Started Jun 25 05:44:14 PM PDT 24
Finished Jun 25 05:45:34 PM PDT 24
Peak memory 182896 kb
Host smart-d7031b4d-5166-4db1-b20f-c330f98b2857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113407393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4113407393
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1839873960
Short name T21
Test name
Test status
Simulation time 39980014929 ps
CPU time 18.52 seconds
Started Jun 25 05:44:14 PM PDT 24
Finished Jun 25 05:44:33 PM PDT 24
Peak memory 183152 kb
Host smart-637974b7-728d-40f4-9e28-41f51bdc7d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839873960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1839873960
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.15816113
Short name T137
Test name
Test status
Simulation time 95521937117 ps
CPU time 230.25 seconds
Started Jun 25 05:44:12 PM PDT 24
Finished Jun 25 05:48:03 PM PDT 24
Peak memory 191348 kb
Host smart-b563f430-74f6-4609-9cfd-01dc4471b20e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15816113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.15816113
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.331157709
Short name T253
Test name
Test status
Simulation time 218756247883 ps
CPU time 213.95 seconds
Started Jun 25 05:44:13 PM PDT 24
Finished Jun 25 05:47:48 PM PDT 24
Peak memory 191336 kb
Host smart-c026baf6-dd48-4c1d-93cd-8ad1c2bccce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331157709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.331157709
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3921966512
Short name T450
Test name
Test status
Simulation time 224591062482 ps
CPU time 89.39 seconds
Started Jun 25 05:44:21 PM PDT 24
Finished Jun 25 05:45:51 PM PDT 24
Peak memory 193096 kb
Host smart-71349260-8391-4437-97fc-4dcbfb71795c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921966512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3921966512
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3455032436
Short name T118
Test name
Test status
Simulation time 2171402989129 ps
CPU time 657.96 seconds
Started Jun 25 05:44:21 PM PDT 24
Finished Jun 25 05:55:20 PM PDT 24
Peak memory 191332 kb
Host smart-ec3a0199-a6a2-4d8b-ad11-07c2d8258cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455032436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3455032436
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1735493493
Short name T67
Test name
Test status
Simulation time 184133490889 ps
CPU time 312.61 seconds
Started Jun 25 05:42:35 PM PDT 24
Finished Jun 25 05:47:48 PM PDT 24
Peak memory 183144 kb
Host smart-90c0198c-d2ab-4574-9ba0-53028f512a04
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735493493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1735493493
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.4272280224
Short name T398
Test name
Test status
Simulation time 146879600924 ps
CPU time 84.22 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:44:01 PM PDT 24
Peak memory 183148 kb
Host smart-9e49913e-3cc7-46f5-9fc4-a5595431d574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272280224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.4272280224
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3423104088
Short name T360
Test name
Test status
Simulation time 279595113002 ps
CPU time 481.1 seconds
Started Jun 25 05:42:45 PM PDT 24
Finished Jun 25 05:50:47 PM PDT 24
Peak memory 191360 kb
Host smart-9144f47e-f670-4acd-bd34-32fed0c813a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423104088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3423104088
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2264363933
Short name T178
Test name
Test status
Simulation time 1511074393668 ps
CPU time 709.14 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:54:29 PM PDT 24
Peak memory 191336 kb
Host smart-342c40eb-7dd9-4f08-a8f3-e06f241a6a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264363933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2264363933
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2296048746
Short name T37
Test name
Test status
Simulation time 38830597639 ps
CPU time 436.78 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 206044 kb
Host smart-a75aaadc-2e83-48b6-a711-56b3acd931fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296048746 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.2296048746
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.3872735748
Short name T300
Test name
Test status
Simulation time 81713165587 ps
CPU time 116.95 seconds
Started Jun 25 05:44:21 PM PDT 24
Finished Jun 25 05:46:18 PM PDT 24
Peak memory 191340 kb
Host smart-557b4967-71f5-40c8-aaa7-ed992f102e96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872735748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3872735748
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1218009588
Short name T361
Test name
Test status
Simulation time 138661803754 ps
CPU time 122.23 seconds
Started Jun 25 05:44:21 PM PDT 24
Finished Jun 25 05:46:24 PM PDT 24
Peak memory 193888 kb
Host smart-1f65f001-6971-40c2-b9ab-c719d9d30d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218009588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1218009588
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.641164856
Short name T126
Test name
Test status
Simulation time 75507469833 ps
CPU time 1614.41 seconds
Started Jun 25 05:44:20 PM PDT 24
Finished Jun 25 06:11:15 PM PDT 24
Peak memory 191316 kb
Host smart-a8224ec1-8bcc-471b-a2b0-27f3cf53e1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641164856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.641164856
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1101136470
Short name T22
Test name
Test status
Simulation time 113179570027 ps
CPU time 618 seconds
Started Jun 25 05:44:19 PM PDT 24
Finished Jun 25 05:54:38 PM PDT 24
Peak memory 191336 kb
Host smart-2dff2004-6989-40e9-922b-4e44c8be6c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101136470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1101136470
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2433612268
Short name T191
Test name
Test status
Simulation time 214448845026 ps
CPU time 109.99 seconds
Started Jun 25 05:44:29 PM PDT 24
Finished Jun 25 05:46:20 PM PDT 24
Peak memory 191324 kb
Host smart-ea2bea4e-90a4-48d0-a24d-fcdaf2193490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433612268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2433612268
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1268433477
Short name T273
Test name
Test status
Simulation time 334868502790 ps
CPU time 276.6 seconds
Started Jun 25 05:44:28 PM PDT 24
Finished Jun 25 05:49:05 PM PDT 24
Peak memory 191332 kb
Host smart-c3792222-2f3a-4027-a03e-7088522e621c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268433477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1268433477
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3602791138
Short name T28
Test name
Test status
Simulation time 38625060574 ps
CPU time 382.84 seconds
Started Jun 25 05:44:30 PM PDT 24
Finished Jun 25 05:50:54 PM PDT 24
Peak memory 191328 kb
Host smart-c7cc8223-4324-4b66-90f6-42bbe52da934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602791138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3602791138
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.623321941
Short name T78
Test name
Test status
Simulation time 540690593893 ps
CPU time 616.89 seconds
Started Jun 25 05:44:28 PM PDT 24
Finished Jun 25 05:54:46 PM PDT 24
Peak memory 191284 kb
Host smart-e0005b1d-f88e-4026-bed9-6e9cb14b0e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623321941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.623321941
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.142147715
Short name T382
Test name
Test status
Simulation time 23002388351 ps
CPU time 17.7 seconds
Started Jun 25 05:42:16 PM PDT 24
Finished Jun 25 05:42:35 PM PDT 24
Peak memory 183152 kb
Host smart-2aece488-eddc-426a-8276-18ecda066004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142147715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.142147715
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2971469011
Short name T417
Test name
Test status
Simulation time 456976475 ps
CPU time 1.25 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:42:19 PM PDT 24
Peak memory 182992 kb
Host smart-e6757732-c08f-43b8-b235-614f0fd77f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971469011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2971469011
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.667746876
Short name T16
Test name
Test status
Simulation time 440532980 ps
CPU time 1.08 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:42:19 PM PDT 24
Peak memory 214492 kb
Host smart-46bcda46-5908-4317-b629-bfc3032284a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667746876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.667746876
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.815386538
Short name T179
Test name
Test status
Simulation time 931972475884 ps
CPU time 1922.72 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 06:14:21 PM PDT 24
Peak memory 195688 kb
Host smart-07e9fc03-36c3-4c45-aa86-ecfc2357dcb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815386538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.815386538
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3480179562
Short name T79
Test name
Test status
Simulation time 169242282458 ps
CPU time 252.62 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:46:48 PM PDT 24
Peak memory 183128 kb
Host smart-31a3a4a7-e21a-4e52-9f70-f620d148c7e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480179562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3480179562
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4130278427
Short name T389
Test name
Test status
Simulation time 345936210073 ps
CPU time 160.01 seconds
Started Jun 25 05:42:32 PM PDT 24
Finished Jun 25 05:45:13 PM PDT 24
Peak memory 182912 kb
Host smart-b57577ff-399f-4ee4-bf89-97faa1e50696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130278427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4130278427
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.777928982
Short name T165
Test name
Test status
Simulation time 89632052588 ps
CPU time 290.94 seconds
Started Jun 25 05:42:39 PM PDT 24
Finished Jun 25 05:47:31 PM PDT 24
Peak memory 191332 kb
Host smart-854e50d3-c3e0-48cb-9b42-530282d8164d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777928982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.777928982
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2893550381
Short name T338
Test name
Test status
Simulation time 203580026790 ps
CPU time 97.68 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:44:32 PM PDT 24
Peak memory 194852 kb
Host smart-59dbdf58-583a-469c-af7a-1b195208fc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893550381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2893550381
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4223590733
Short name T293
Test name
Test status
Simulation time 228268742617 ps
CPU time 320.65 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:47:58 PM PDT 24
Peak memory 195696 kb
Host smart-a6ed7487-6531-45b1-9658-06dc060dde6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223590733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4223590733
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3177214818
Short name T254
Test name
Test status
Simulation time 2852617224559 ps
CPU time 1203.2 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 06:02:41 PM PDT 24
Peak memory 183244 kb
Host smart-c2536710-1dce-4516-907b-7fa96ae75f21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177214818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3177214818
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4253446263
Short name T416
Test name
Test status
Simulation time 9003350567 ps
CPU time 13.87 seconds
Started Jun 25 05:42:41 PM PDT 24
Finished Jun 25 05:42:56 PM PDT 24
Peak memory 183160 kb
Host smart-ebed1a02-8bca-469c-8c83-371a4ce6d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253446263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4253446263
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1214899930
Short name T124
Test name
Test status
Simulation time 59205266061 ps
CPU time 258.14 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:46:58 PM PDT 24
Peak memory 191360 kb
Host smart-10f5a20e-75d2-4386-a258-47f1ec90f0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214899930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1214899930
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.844144299
Short name T407
Test name
Test status
Simulation time 44398929 ps
CPU time 0.65 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:42:38 PM PDT 24
Peak memory 182992 kb
Host smart-a805cecd-6fab-4e91-a83e-d6a18653d590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844144299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
844144299
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1427621846
Short name T6
Test name
Test status
Simulation time 45121865918 ps
CPU time 77.78 seconds
Started Jun 25 05:42:42 PM PDT 24
Finished Jun 25 05:44:01 PM PDT 24
Peak memory 183140 kb
Host smart-72a1ab5a-ed15-43d3-8421-290252ae7da1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427621846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1427621846
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.388798051
Short name T444
Test name
Test status
Simulation time 462285738861 ps
CPU time 202.02 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:45:59 PM PDT 24
Peak memory 183252 kb
Host smart-f8fadff1-bc37-4074-a863-dd4649ba798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388798051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.388798051
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.277335428
Short name T319
Test name
Test status
Simulation time 17826731338 ps
CPU time 31.33 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:43:10 PM PDT 24
Peak memory 183076 kb
Host smart-6f5b07c4-6463-4b8f-a304-454cf657e843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277335428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.277335428
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1123753916
Short name T169
Test name
Test status
Simulation time 94646890393 ps
CPU time 46.8 seconds
Started Jun 25 05:42:39 PM PDT 24
Finished Jun 25 05:43:27 PM PDT 24
Peak memory 191356 kb
Host smart-1624cf4b-b5ff-454c-aef4-7d1adc13052a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123753916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1123753916
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.573871118
Short name T381
Test name
Test status
Simulation time 456537146046 ps
CPU time 70.54 seconds
Started Jun 25 05:42:47 PM PDT 24
Finished Jun 25 05:43:59 PM PDT 24
Peak memory 183068 kb
Host smart-602b0064-6b30-4b8e-b706-29650d4a1fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573871118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
573871118
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1794938918
Short name T182
Test name
Test status
Simulation time 148260708974 ps
CPU time 240.78 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:46:40 PM PDT 24
Peak memory 183376 kb
Host smart-708a8d0d-f166-4563-ae31-50ef62fa460b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794938918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1794938918
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1354836210
Short name T380
Test name
Test status
Simulation time 364661713098 ps
CPU time 97.2 seconds
Started Jun 25 05:42:33 PM PDT 24
Finished Jun 25 05:44:11 PM PDT 24
Peak memory 183168 kb
Host smart-e1e3cd9f-f9d1-48d5-8b1f-07db85c4f0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354836210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1354836210
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.644524251
Short name T332
Test name
Test status
Simulation time 1057398039693 ps
CPU time 596.42 seconds
Started Jun 25 05:42:39 PM PDT 24
Finished Jun 25 05:52:37 PM PDT 24
Peak memory 191348 kb
Host smart-33b92aae-6a78-4e06-a226-8e3590f688e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644524251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.644524251
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2623801603
Short name T367
Test name
Test status
Simulation time 1253013302 ps
CPU time 45.91 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:43:23 PM PDT 24
Peak memory 183100 kb
Host smart-9c0b6599-9937-44e1-a313-294b74bd23d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623801603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2623801603
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.171459079
Short name T323
Test name
Test status
Simulation time 39993631663 ps
CPU time 20.42 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:42:56 PM PDT 24
Peak memory 183140 kb
Host smart-48eb40da-fb10-45f7-81c4-bdeced895ce0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171459079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.171459079
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2876441046
Short name T411
Test name
Test status
Simulation time 139833608169 ps
CPU time 188.67 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:45:47 PM PDT 24
Peak memory 183140 kb
Host smart-1f4e3e73-32c3-44a1-9fa6-534542ea47b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876441046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2876441046
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3187297751
Short name T74
Test name
Test status
Simulation time 31468148930 ps
CPU time 20.64 seconds
Started Jun 25 05:42:33 PM PDT 24
Finished Jun 25 05:42:55 PM PDT 24
Peak memory 183140 kb
Host smart-cae04226-5b20-4cda-aac8-0766d375b117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187297751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3187297751
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2250327152
Short name T161
Test name
Test status
Simulation time 48393255537 ps
CPU time 219.12 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:46:18 PM PDT 24
Peak memory 195736 kb
Host smart-a06d1933-7ab1-4522-906f-78f09a254bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250327152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2250327152
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.490364900
Short name T64
Test name
Test status
Simulation time 51050517701 ps
CPU time 373.96 seconds
Started Jun 25 05:42:37 PM PDT 24
Finished Jun 25 05:48:52 PM PDT 24
Peak memory 194504 kb
Host smart-a0c6ec60-5f64-47e3-a336-98a9f44c8c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490364900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
490364900
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.193918271
Short name T328
Test name
Test status
Simulation time 1422522711544 ps
CPU time 405.07 seconds
Started Jun 25 05:42:46 PM PDT 24
Finished Jun 25 05:49:32 PM PDT 24
Peak memory 183152 kb
Host smart-5764b2cb-a648-490b-8465-799918195e8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193918271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.193918271
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2503623946
Short name T368
Test name
Test status
Simulation time 450025735416 ps
CPU time 194.37 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:45:51 PM PDT 24
Peak memory 183172 kb
Host smart-0e4b48af-0681-4c4a-8429-7ae3152a4994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503623946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2503623946
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2960756827
Short name T424
Test name
Test status
Simulation time 42443907764 ps
CPU time 69.93 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:43:49 PM PDT 24
Peak memory 183128 kb
Host smart-a155b320-6ceb-4c9f-a766-a0849892383d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960756827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2960756827
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.787014693
Short name T446
Test name
Test status
Simulation time 6354543492 ps
CPU time 4.91 seconds
Started Jun 25 05:42:36 PM PDT 24
Finished Jun 25 05:42:42 PM PDT 24
Peak memory 183080 kb
Host smart-997ac9e0-d995-48ef-b10d-1684273cef1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787014693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.787014693
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3935444736
Short name T34
Test name
Test status
Simulation time 103671885193 ps
CPU time 952.46 seconds
Started Jun 25 05:42:38 PM PDT 24
Finished Jun 25 05:58:32 PM PDT 24
Peak memory 206040 kb
Host smart-b6c5424c-d402-4007-b66e-01a49242cb40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935444736 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3935444736
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3145257740
Short name T378
Test name
Test status
Simulation time 203419807162 ps
CPU time 77.85 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 05:44:19 PM PDT 24
Peak memory 183148 kb
Host smart-6062249d-699b-403c-9e8e-c2f962c35a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145257740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3145257740
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.327828603
Short name T347
Test name
Test status
Simulation time 423752601927 ps
CPU time 97.4 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 05:44:29 PM PDT 24
Peak memory 191336 kb
Host smart-20395153-258c-46d4-95aa-c643a76e113a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327828603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.327828603
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.254782799
Short name T408
Test name
Test status
Simulation time 53522242 ps
CPU time 0.62 seconds
Started Jun 25 05:42:46 PM PDT 24
Finished Jun 25 05:42:48 PM PDT 24
Peak memory 182996 kb
Host smart-b5ba52eb-d0cb-43a4-9727-4f789a7a929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254782799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.254782799
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1544557668
Short name T61
Test name
Test status
Simulation time 3896150605087 ps
CPU time 451.3 seconds
Started Jun 25 05:42:47 PM PDT 24
Finished Jun 25 05:50:19 PM PDT 24
Peak memory 191340 kb
Host smart-4d838dc1-92bf-4f68-aa46-1da174d8048d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544557668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1544557668
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.412170090
Short name T354
Test name
Test status
Simulation time 10280942301 ps
CPU time 16.22 seconds
Started Jun 25 05:42:45 PM PDT 24
Finished Jun 25 05:43:02 PM PDT 24
Peak memory 183152 kb
Host smart-7107e3d2-51bf-4abc-ba63-ae827cf7c76d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412170090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.412170090
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2299726318
Short name T449
Test name
Test status
Simulation time 117557229166 ps
CPU time 90.22 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 05:44:20 PM PDT 24
Peak memory 183152 kb
Host smart-ba29302d-6718-4e36-93da-570ac5fe0195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299726318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2299726318
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1936159639
Short name T2
Test name
Test status
Simulation time 98095580854 ps
CPU time 227.16 seconds
Started Jun 25 05:42:46 PM PDT 24
Finished Jun 25 05:46:35 PM PDT 24
Peak memory 191328 kb
Host smart-5a863ad3-02c0-4631-bf06-59ded2ff5698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936159639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1936159639
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1222925394
Short name T114
Test name
Test status
Simulation time 450567234356 ps
CPU time 578.99 seconds
Started Jun 25 05:42:45 PM PDT 24
Finished Jun 25 05:52:25 PM PDT 24
Peak memory 191360 kb
Host smart-a9310956-1b75-4c3d-b9cc-07063b79a17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222925394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1222925394
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1162397124
Short name T59
Test name
Test status
Simulation time 2531412967382 ps
CPU time 989.82 seconds
Started Jun 25 05:42:53 PM PDT 24
Finished Jun 25 05:59:25 PM PDT 24
Peak memory 191356 kb
Host smart-a8c9fb7a-091a-4df8-9af6-4dd330529c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162397124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1162397124
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.69340173
Short name T212
Test name
Test status
Simulation time 341158016719 ps
CPU time 581.14 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 05:52:26 PM PDT 24
Peak memory 183128 kb
Host smart-f73dff6c-5672-44a4-ac05-4133a96d77a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69340173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.rv_timer_cfg_update_on_fly.69340173
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.987248724
Short name T394
Test name
Test status
Simulation time 366801624064 ps
CPU time 133.22 seconds
Started Jun 25 05:42:46 PM PDT 24
Finished Jun 25 05:45:01 PM PDT 24
Peak memory 183260 kb
Host smart-2ee28281-58bf-42ed-a695-084283500cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987248724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.987248724
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.953960681
Short name T396
Test name
Test status
Simulation time 221233853 ps
CPU time 0.68 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 05:42:51 PM PDT 24
Peak memory 182948 kb
Host smart-b84f734c-6af7-4c05-83ca-f5db8d276bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953960681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.953960681
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2634775872
Short name T383
Test name
Test status
Simulation time 585976902344 ps
CPU time 240.4 seconds
Started Jun 25 05:42:42 PM PDT 24
Finished Jun 25 05:46:44 PM PDT 24
Peak memory 183144 kb
Host smart-88e37bbe-0766-48dd-8962-e321f5f67233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634775872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2634775872
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.466440509
Short name T372
Test name
Test status
Simulation time 873276516 ps
CPU time 2.23 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 05:42:48 PM PDT 24
Peak memory 191280 kb
Host smart-535a5d78-7ee6-44dc-a13d-0bad04ba5918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466440509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.466440509
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2367488248
Short name T442
Test name
Test status
Simulation time 31663471306 ps
CPU time 53.89 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:43:12 PM PDT 24
Peak memory 183152 kb
Host smart-9615a4b7-82b6-44f4-a24b-1aa997926425
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367488248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2367488248
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3982097963
Short name T428
Test name
Test status
Simulation time 538859283676 ps
CPU time 215.29 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:45:54 PM PDT 24
Peak memory 183148 kb
Host smart-d594b48e-982d-40dd-9538-9db639054c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982097963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3982097963
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.863184315
Short name T397
Test name
Test status
Simulation time 172814150730 ps
CPU time 366.8 seconds
Started Jun 25 05:42:20 PM PDT 24
Finished Jun 25 05:48:28 PM PDT 24
Peak memory 183132 kb
Host smart-38108cc3-e636-42f5-abf2-6373b187e34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863184315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.863184315
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2754557588
Short name T384
Test name
Test status
Simulation time 150945580 ps
CPU time 1.6 seconds
Started Jun 25 05:42:15 PM PDT 24
Finished Jun 25 05:42:18 PM PDT 24
Peak memory 192852 kb
Host smart-fcf17d27-82b2-45ad-a019-b92802d632a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754557588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2754557588
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2865436295
Short name T19
Test name
Test status
Simulation time 82068280 ps
CPU time 0.8 seconds
Started Jun 25 05:42:15 PM PDT 24
Finished Jun 25 05:42:16 PM PDT 24
Peak memory 214080 kb
Host smart-1f8fdfb9-fc9b-4296-9247-7ccfaa5ec1a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865436295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2865436295
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.503132285
Short name T390
Test name
Test status
Simulation time 28119838944 ps
CPU time 303.16 seconds
Started Jun 25 05:42:16 PM PDT 24
Finished Jun 25 05:47:20 PM PDT 24
Peak memory 197824 kb
Host smart-c30b9b46-01bb-41c2-83e1-890430d245a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503132285 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.503132285
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1549471297
Short name T406
Test name
Test status
Simulation time 392578141304 ps
CPU time 151.01 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:45:25 PM PDT 24
Peak memory 183152 kb
Host smart-ed6d086a-3631-44bd-9f52-4085ae8502c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549471297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1549471297
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2711939253
Short name T363
Test name
Test status
Simulation time 67414326659 ps
CPU time 372.28 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 05:49:12 PM PDT 24
Peak memory 183116 kb
Host smart-8a968121-f7cb-4d14-b864-08472a263b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711939253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2711939253
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3190369799
Short name T70
Test name
Test status
Simulation time 660518039 ps
CPU time 1.42 seconds
Started Jun 25 05:42:48 PM PDT 24
Finished Jun 25 05:42:50 PM PDT 24
Peak memory 193772 kb
Host smart-ab65e9e7-90e0-4e24-a115-4e8e491e1575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190369799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3190369799
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1867512052
Short name T419
Test name
Test status
Simulation time 457124591501 ps
CPU time 361.53 seconds
Started Jun 25 05:42:42 PM PDT 24
Finished Jun 25 05:48:45 PM PDT 24
Peak memory 191332 kb
Host smart-841b280c-b5a1-4358-a4d1-3cfb86928868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867512052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1867512052
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2359079354
Short name T39
Test name
Test status
Simulation time 41051909236 ps
CPU time 331.73 seconds
Started Jun 25 05:42:42 PM PDT 24
Finished Jun 25 05:48:15 PM PDT 24
Peak memory 206844 kb
Host smart-1ad8837c-ef7c-4adc-86f8-d69f1c08f2a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359079354 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2359079354
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.728884606
Short name T415
Test name
Test status
Simulation time 377462985924 ps
CPU time 141.16 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:45:23 PM PDT 24
Peak memory 182980 kb
Host smart-a9de4141-c95b-4924-95aa-0b7d60c2926f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728884606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.728884606
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.4103403809
Short name T302
Test name
Test status
Simulation time 2370221568919 ps
CPU time 2087.69 seconds
Started Jun 25 05:42:42 PM PDT 24
Finished Jun 25 06:17:31 PM PDT 24
Peak memory 191100 kb
Host smart-e00f0d88-b777-45ca-b2ee-31d28c851320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103403809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4103403809
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2488384075
Short name T226
Test name
Test status
Simulation time 43841763852 ps
CPU time 62.85 seconds
Started Jun 25 05:43:00 PM PDT 24
Finished Jun 25 05:44:07 PM PDT 24
Peak memory 191360 kb
Host smart-baa476ad-deee-4845-8512-884e71ae7f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488384075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2488384075
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2401390409
Short name T38
Test name
Test status
Simulation time 58634131890 ps
CPU time 531.35 seconds
Started Jun 25 05:42:41 PM PDT 24
Finished Jun 25 05:51:33 PM PDT 24
Peak memory 206060 kb
Host smart-68807448-d700-4779-bd0a-a62a5d9ba3f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401390409 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2401390409
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2894948283
Short name T456
Test name
Test status
Simulation time 79165602563 ps
CPU time 121.68 seconds
Started Jun 25 05:42:43 PM PDT 24
Finished Jun 25 05:44:46 PM PDT 24
Peak memory 183132 kb
Host smart-30f1a3b6-39da-4eeb-8335-2dfd6a22918e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894948283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2894948283
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3132824446
Short name T443
Test name
Test status
Simulation time 527694709981 ps
CPU time 96.89 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 05:44:22 PM PDT 24
Peak memory 183144 kb
Host smart-2be41cbb-c03d-46a1-a3ec-d6677c19d25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132824446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3132824446
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3825383471
Short name T145
Test name
Test status
Simulation time 412849473942 ps
CPU time 289.89 seconds
Started Jun 25 05:42:41 PM PDT 24
Finished Jun 25 05:47:32 PM PDT 24
Peak memory 191356 kb
Host smart-b1f3a74c-0ccf-448b-b398-424124cc2b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825383471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3825383471
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2682684843
Short name T333
Test name
Test status
Simulation time 21190870651 ps
CPU time 34.28 seconds
Started Jun 25 05:42:44 PM PDT 24
Finished Jun 25 05:43:19 PM PDT 24
Peak memory 183148 kb
Host smart-1d91cafa-a953-4aaa-81fa-08d8015a1dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682684843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2682684843
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.346998507
Short name T48
Test name
Test status
Simulation time 201300670106 ps
CPU time 381.61 seconds
Started Jun 25 05:42:45 PM PDT 24
Finished Jun 25 05:49:08 PM PDT 24
Peak memory 191328 kb
Host smart-f3f31c0d-5c23-4150-802d-a14cbbe23c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346998507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
346998507
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2214763251
Short name T173
Test name
Test status
Simulation time 5350888670 ps
CPU time 3.86 seconds
Started Jun 25 05:42:45 PM PDT 24
Finished Jun 25 05:42:50 PM PDT 24
Peak memory 183144 kb
Host smart-0e6494cb-c1b0-4556-8c6b-36b2a9d0d906
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214763251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2214763251
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1310131198
Short name T412
Test name
Test status
Simulation time 99014440769 ps
CPU time 136.75 seconds
Started Jun 25 05:42:47 PM PDT 24
Finished Jun 25 05:45:05 PM PDT 24
Peak memory 183120 kb
Host smart-82bb9f4a-3134-4928-a367-fa1cd138d888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310131198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1310131198
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3602075613
Short name T263
Test name
Test status
Simulation time 83740048542 ps
CPU time 1139.98 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 06:01:52 PM PDT 24
Peak memory 191296 kb
Host smart-53045116-76c0-425e-b6ce-8531f52097fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602075613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3602075613
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.9884258
Short name T362
Test name
Test status
Simulation time 441466340567 ps
CPU time 337.48 seconds
Started Jun 25 05:42:43 PM PDT 24
Finished Jun 25 05:48:21 PM PDT 24
Peak memory 191332 kb
Host smart-c161d825-f6c1-4dbc-9422-74e7d4626f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9884258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.9884258
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.366382209
Short name T438
Test name
Test status
Simulation time 170469708302 ps
CPU time 113.75 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:44:51 PM PDT 24
Peak memory 183168 kb
Host smart-625a6b0f-127d-4346-96fe-708aeac9bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366382209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.366382209
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3284083530
Short name T421
Test name
Test status
Simulation time 494242311 ps
CPU time 1.82 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:43:05 PM PDT 24
Peak memory 191288 kb
Host smart-cb4afa1f-4325-441c-ab0c-fbe11ffef64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284083530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3284083530
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2938737107
Short name T399
Test name
Test status
Simulation time 564787259932 ps
CPU time 1188.05 seconds
Started Jun 25 05:42:41 PM PDT 24
Finished Jun 25 06:02:30 PM PDT 24
Peak memory 195568 kb
Host smart-6ea1661b-d43c-413a-9252-ae307545abca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938737107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2938737107
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3064098738
Short name T400
Test name
Test status
Simulation time 5803038284 ps
CPU time 5.08 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 05:42:58 PM PDT 24
Peak memory 183056 kb
Host smart-c9b1c121-d1ee-4554-8070-cf6e3d7b9274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064098738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3064098738
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.467472575
Short name T155
Test name
Test status
Simulation time 433520111521 ps
CPU time 1486.3 seconds
Started Jun 25 05:42:45 PM PDT 24
Finished Jun 25 06:07:33 PM PDT 24
Peak memory 191452 kb
Host smart-763429ae-038a-402a-9a75-7099f73d9da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467472575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.467472575
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2695156040
Short name T337
Test name
Test status
Simulation time 34596479256 ps
CPU time 18.13 seconds
Started Jun 25 05:42:43 PM PDT 24
Finished Jun 25 05:43:02 PM PDT 24
Peak memory 192080 kb
Host smart-053b89d0-ede0-4ff9-8649-aa234ccbfd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695156040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2695156040
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3321167500
Short name T25
Test name
Test status
Simulation time 9929444603 ps
CPU time 105.27 seconds
Started Jun 25 05:42:42 PM PDT 24
Finished Jun 25 05:44:28 PM PDT 24
Peak memory 197856 kb
Host smart-615f010a-b210-4211-984b-0056064da2ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321167500 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3321167500
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3034257250
Short name T76
Test name
Test status
Simulation time 11588935409 ps
CPU time 19.1 seconds
Started Jun 25 05:42:43 PM PDT 24
Finished Jun 25 05:43:03 PM PDT 24
Peak memory 183120 kb
Host smart-001ccb44-75f6-4ed0-9668-ea812ac726f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034257250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3034257250
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3840935208
Short name T452
Test name
Test status
Simulation time 126128659126 ps
CPU time 203.29 seconds
Started Jun 25 05:43:05 PM PDT 24
Finished Jun 25 05:46:30 PM PDT 24
Peak memory 183168 kb
Host smart-a16c2518-d5ed-4267-ba2d-ad314edff148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840935208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3840935208
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1163951569
Short name T56
Test name
Test status
Simulation time 338630277348 ps
CPU time 305.9 seconds
Started Jun 25 05:42:43 PM PDT 24
Finished Jun 25 05:47:49 PM PDT 24
Peak memory 183136 kb
Host smart-ce13bb09-fcc3-428e-bb74-d51e9821ba6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163951569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1163951569
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2653306825
Short name T388
Test name
Test status
Simulation time 57127783 ps
CPU time 0.9 seconds
Started Jun 25 05:42:46 PM PDT 24
Finished Jun 25 05:42:49 PM PDT 24
Peak memory 183196 kb
Host smart-f5fab773-89c1-4be4-ac71-cc18e6d09245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653306825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2653306825
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.988967475
Short name T203
Test name
Test status
Simulation time 248234513172 ps
CPU time 304.48 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:48:03 PM PDT 24
Peak memory 195768 kb
Host smart-7ed0fdb6-0fbc-4493-ae51-190b71a7ccec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988967475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
988967475
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.606188743
Short name T40
Test name
Test status
Simulation time 38641455466 ps
CPU time 231.29 seconds
Started Jun 25 05:42:43 PM PDT 24
Finished Jun 25 05:46:35 PM PDT 24
Peak memory 197836 kb
Host smart-63d45200-8a17-4ed1-af97-1a047eb0459b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606188743 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.606188743
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1796987830
Short name T336
Test name
Test status
Simulation time 91683410030 ps
CPU time 148.94 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:45:32 PM PDT 24
Peak memory 183156 kb
Host smart-437fdb10-93dc-4b67-a206-ecfdf8845894
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796987830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1796987830
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1225495465
Short name T402
Test name
Test status
Simulation time 76158041807 ps
CPU time 100.04 seconds
Started Jun 25 05:43:05 PM PDT 24
Finished Jun 25 05:44:46 PM PDT 24
Peak memory 183168 kb
Host smart-73e0b530-bdbc-4b9a-8c2b-6fb4b567c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225495465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1225495465
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.121502216
Short name T458
Test name
Test status
Simulation time 73859766379 ps
CPU time 38.4 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:43:37 PM PDT 24
Peak memory 191304 kb
Host smart-c84b132a-a3f7-4f55-8f5b-9ced5559d08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121502216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.121502216
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1005388453
Short name T454
Test name
Test status
Simulation time 96440408 ps
CPU time 0.72 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:42:58 PM PDT 24
Peak memory 183016 kb
Host smart-eae19db7-5e58-4243-93df-0f9a1553b310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005388453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1005388453
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.820141291
Short name T35
Test name
Test status
Simulation time 37781814379 ps
CPU time 194.43 seconds
Started Jun 25 05:42:53 PM PDT 24
Finished Jun 25 05:46:09 PM PDT 24
Peak memory 206040 kb
Host smart-c3d6eb5b-bb55-41ed-a817-4769073854ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820141291 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.820141291
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.162816314
Short name T301
Test name
Test status
Simulation time 328941458249 ps
CPU time 314.69 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 05:48:07 PM PDT 24
Peak memory 183152 kb
Host smart-175047b3-9691-41e7-8437-a8dd580bfc7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162816314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.162816314
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.4222036154
Short name T379
Test name
Test status
Simulation time 228979011908 ps
CPU time 96.38 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:44:30 PM PDT 24
Peak memory 183144 kb
Host smart-feefed2c-29df-4696-93c1-f6728582c628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222036154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4222036154
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1562339481
Short name T4
Test name
Test status
Simulation time 67721497852 ps
CPU time 80.83 seconds
Started Jun 25 05:42:51 PM PDT 24
Finished Jun 25 05:44:13 PM PDT 24
Peak memory 194324 kb
Host smart-344c13f7-b299-45e0-9cbe-f3717b7d1b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562339481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1562339481
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.98483177
Short name T234
Test name
Test status
Simulation time 163876505218 ps
CPU time 89.09 seconds
Started Jun 25 05:43:02 PM PDT 24
Finished Jun 25 05:44:34 PM PDT 24
Peak memory 195076 kb
Host smart-702cf18a-ca4b-469c-b736-207fd5016476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98483177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.98483177
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2286505995
Short name T125
Test name
Test status
Simulation time 3156323289794 ps
CPU time 572.94 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:52:32 PM PDT 24
Peak memory 191324 kb
Host smart-dfe855e1-26d5-440e-9d48-7329b907ec17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286505995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2286505995
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2999317402
Short name T356
Test name
Test status
Simulation time 3367592637 ps
CPU time 5.28 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:43:09 PM PDT 24
Peak memory 183108 kb
Host smart-aa08842d-0cd5-42ba-8189-48a6a3d0ce8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999317402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2999317402
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.915809175
Short name T373
Test name
Test status
Simulation time 219358489806 ps
CPU time 175.74 seconds
Started Jun 25 05:42:51 PM PDT 24
Finished Jun 25 05:45:48 PM PDT 24
Peak memory 183164 kb
Host smart-b4a4ba5d-9b26-4c39-b67c-740f5b19f629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915809175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.915809175
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.307731949
Short name T206
Test name
Test status
Simulation time 2964300777023 ps
CPU time 1012.45 seconds
Started Jun 25 05:42:48 PM PDT 24
Finished Jun 25 05:59:42 PM PDT 24
Peak memory 191316 kb
Host smart-e868b9fc-5755-4496-8753-e9c1f9c3f753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307731949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.307731949
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1976836134
Short name T457
Test name
Test status
Simulation time 240542521723 ps
CPU time 107.98 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 05:44:40 PM PDT 24
Peak memory 191344 kb
Host smart-adfc9ed2-8c58-4657-b6ce-e821d5e7de90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976836134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1976836134
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1225633791
Short name T233
Test name
Test status
Simulation time 190089333058 ps
CPU time 283.61 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:47:37 PM PDT 24
Peak memory 191336 kb
Host smart-2ae5cc9b-e208-410a-869b-4184d4b93c9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225633791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1225633791
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3583137472
Short name T350
Test name
Test status
Simulation time 534526764894 ps
CPU time 266.63 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:46:44 PM PDT 24
Peak memory 183104 kb
Host smart-a9be07d1-8315-4f8b-9e3a-7cf17a78f410
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583137472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3583137472
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1226447742
Short name T377
Test name
Test status
Simulation time 21612026220 ps
CPU time 30.77 seconds
Started Jun 25 05:42:32 PM PDT 24
Finished Jun 25 05:43:03 PM PDT 24
Peak memory 183144 kb
Host smart-3c8cc05b-48ba-43f7-a26a-709fa087f4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226447742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1226447742
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2299259915
Short name T181
Test name
Test status
Simulation time 1008717616979 ps
CPU time 982.79 seconds
Started Jun 25 05:42:18 PM PDT 24
Finished Jun 25 05:58:42 PM PDT 24
Peak memory 191336 kb
Host smart-526b15c4-73ac-4b84-9402-de6ab073a32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299259915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2299259915
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2379850101
Short name T403
Test name
Test status
Simulation time 15258982007 ps
CPU time 10.65 seconds
Started Jun 25 05:42:14 PM PDT 24
Finished Jun 25 05:42:26 PM PDT 24
Peak memory 194528 kb
Host smart-5b94b0c0-763a-4a60-a9ad-bf9e82fd2796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379850101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2379850101
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.582080384
Short name T15
Test name
Test status
Simulation time 153736063 ps
CPU time 0.94 seconds
Started Jun 25 05:42:18 PM PDT 24
Finished Jun 25 05:42:20 PM PDT 24
Peak memory 213504 kb
Host smart-ad71cd25-b5f1-464a-9af6-125477242307
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582080384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.582080384
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3111621313
Short name T224
Test name
Test status
Simulation time 4849258608 ps
CPU time 9.06 seconds
Started Jun 25 05:42:18 PM PDT 24
Finished Jun 25 05:42:28 PM PDT 24
Peak memory 183152 kb
Host smart-9a13b240-6793-4bb2-aec4-6e3a32e14340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111621313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3111621313
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2084499246
Short name T106
Test name
Test status
Simulation time 46473512262 ps
CPU time 183.4 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:45:22 PM PDT 24
Peak memory 197856 kb
Host smart-c34c0b01-53a4-46a6-9312-f4281617babf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084499246 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.2084499246
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3391269750
Short name T20
Test name
Test status
Simulation time 396404623156 ps
CPU time 405.59 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:49:49 PM PDT 24
Peak memory 183144 kb
Host smart-df48ce17-38cd-4feb-8d61-47aed43905f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391269750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3391269750
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2022083223
Short name T376
Test name
Test status
Simulation time 471914905661 ps
CPU time 152.13 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:45:30 PM PDT 24
Peak memory 183132 kb
Host smart-1ee1dd8e-6b52-4fa2-8d21-22e1e69430be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022083223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2022083223
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.595584018
Short name T249
Test name
Test status
Simulation time 168057877112 ps
CPU time 403.11 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:49:41 PM PDT 24
Peak memory 191328 kb
Host smart-43cc8eff-e88e-4ab4-9a46-94b25ae060b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595584018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.595584018
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1324791710
Short name T364
Test name
Test status
Simulation time 42371497466 ps
CPU time 9.86 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:43:07 PM PDT 24
Peak memory 183148 kb
Host smart-dc82f9b4-277f-45e7-b74b-a6f877fb519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324791710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1324791710
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3270014605
Short name T113
Test name
Test status
Simulation time 3108538912793 ps
CPU time 884.14 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:57:42 PM PDT 24
Peak memory 183140 kb
Host smart-da95c33c-79e9-4a75-832e-887355cdb505
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270014605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3270014605
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3654568402
Short name T366
Test name
Test status
Simulation time 140171523281 ps
CPU time 199.99 seconds
Started Jun 25 05:42:54 PM PDT 24
Finished Jun 25 05:46:16 PM PDT 24
Peak memory 183152 kb
Host smart-2334a8cb-7982-4f68-b470-4d216c1c65ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654568402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3654568402
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3317073241
Short name T346
Test name
Test status
Simulation time 151291381443 ps
CPU time 83.11 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:44:23 PM PDT 24
Peak memory 191256 kb
Host smart-847edbe2-37e4-4ca7-90a6-434deae3bdfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317073241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3317073241
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3342684037
Short name T130
Test name
Test status
Simulation time 129607693636 ps
CPU time 144.62 seconds
Started Jun 25 05:42:54 PM PDT 24
Finished Jun 25 05:45:20 PM PDT 24
Peak memory 191336 kb
Host smart-af13d37e-3538-43b8-8bee-78953bd6b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342684037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3342684037
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.642127675
Short name T36
Test name
Test status
Simulation time 70104764663 ps
CPU time 619.22 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 05:53:10 PM PDT 24
Peak memory 206048 kb
Host smart-4668e85a-1138-492d-8565-141e652ebdcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642127675 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.642127675
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3836433381
Short name T247
Test name
Test status
Simulation time 16989844091 ps
CPU time 24.5 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:43:19 PM PDT 24
Peak memory 183144 kb
Host smart-b3333936-8d5a-4bb7-aa45-d6fcf88097db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836433381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3836433381
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random.3624178082
Short name T259
Test name
Test status
Simulation time 304656499598 ps
CPU time 222.73 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:46:45 PM PDT 24
Peak memory 191336 kb
Host smart-b0922089-eda4-422b-aafb-18ef377b43d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624178082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3624178082
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2082387819
Short name T50
Test name
Test status
Simulation time 4279761657 ps
CPU time 7.48 seconds
Started Jun 25 05:42:53 PM PDT 24
Finished Jun 25 05:43:02 PM PDT 24
Peak memory 183140 kb
Host smart-60a5f740-990a-4aa6-914c-a22d25364e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082387819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2082387819
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3898872834
Short name T192
Test name
Test status
Simulation time 5619425993601 ps
CPU time 1429.49 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 06:06:52 PM PDT 24
Peak memory 191160 kb
Host smart-eaf69b19-eb42-4917-a609-3304173011d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898872834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3898872834
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.4268564224
Short name T342
Test name
Test status
Simulation time 50712986710 ps
CPU time 29.14 seconds
Started Jun 25 05:42:50 PM PDT 24
Finished Jun 25 05:43:20 PM PDT 24
Peak memory 183148 kb
Host smart-df8482e8-d813-4e40-9d83-f506c392555a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268564224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.4268564224
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3408067392
Short name T385
Test name
Test status
Simulation time 661425112229 ps
CPU time 272.08 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:47:35 PM PDT 24
Peak memory 183376 kb
Host smart-7d303ff7-4259-4df7-bd8d-fe4aca3ee8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408067392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3408067392
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1262963593
Short name T351
Test name
Test status
Simulation time 96431653422 ps
CPU time 262.63 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:47:16 PM PDT 24
Peak memory 191336 kb
Host smart-e047c0be-98fb-4259-864f-e8a4855f84d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262963593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1262963593
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.126445435
Short name T431
Test name
Test status
Simulation time 434721785441 ps
CPU time 636.43 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:53:35 PM PDT 24
Peak memory 191304 kb
Host smart-edc42e56-12de-4c8c-a7f2-2fed1fa57122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126445435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.126445435
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1623704516
Short name T277
Test name
Test status
Simulation time 376572489270 ps
CPU time 161.6 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:45:35 PM PDT 24
Peak memory 183124 kb
Host smart-e1aeabf1-223e-4993-8c24-c1d3ec8e895d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623704516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1623704516
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2041743663
Short name T423
Test name
Test status
Simulation time 319279828936 ps
CPU time 249.48 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:47:08 PM PDT 24
Peak memory 183160 kb
Host smart-c53111b0-21ea-4e4b-8ff7-03f05d1c06cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041743663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2041743663
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1199236184
Short name T425
Test name
Test status
Simulation time 64945217531 ps
CPU time 448.61 seconds
Started Jun 25 05:42:54 PM PDT 24
Finished Jun 25 05:50:24 PM PDT 24
Peak memory 191336 kb
Host smart-71d054c6-2db0-4a0b-a648-e0a28afe5eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199236184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1199236184
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3295222687
Short name T436
Test name
Test status
Simulation time 40928175 ps
CPU time 0.59 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 05:43:01 PM PDT 24
Peak memory 183020 kb
Host smart-53e8b45c-78d1-4831-9485-6577e0784155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295222687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3295222687
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.798915011
Short name T392
Test name
Test status
Simulation time 36726535943 ps
CPU time 301.91 seconds
Started Jun 25 05:42:51 PM PDT 24
Finished Jun 25 05:47:55 PM PDT 24
Peak memory 197864 kb
Host smart-1811e987-0200-4b03-b8e8-81304631f4f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798915011 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.798915011
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1949144218
Short name T10
Test name
Test status
Simulation time 1324214841029 ps
CPU time 442.69 seconds
Started Jun 25 05:42:53 PM PDT 24
Finished Jun 25 05:50:17 PM PDT 24
Peak memory 183108 kb
Host smart-7ce0a7f4-5c34-43d5-8ed2-272744f079fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949144218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1949144218
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2632819746
Short name T80
Test name
Test status
Simulation time 124118647224 ps
CPU time 179.78 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:45:57 PM PDT 24
Peak memory 183148 kb
Host smart-e97820b1-a778-4428-b207-6d1ca3318f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632819746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2632819746
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2704481557
Short name T236
Test name
Test status
Simulation time 112361381303 ps
CPU time 425.11 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:50:07 PM PDT 24
Peak memory 183048 kb
Host smart-86bb333d-d05f-4941-ae02-b4a35ca55650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704481557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2704481557
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2402698279
Short name T214
Test name
Test status
Simulation time 1762568850010 ps
CPU time 728.66 seconds
Started Jun 25 05:42:55 PM PDT 24
Finished Jun 25 05:55:05 PM PDT 24
Peak memory 196444 kb
Host smart-f27e8653-33b2-4b64-8ab5-096e52651a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402698279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2402698279
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1769717026
Short name T269
Test name
Test status
Simulation time 405360921850 ps
CPU time 197.38 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 05:46:18 PM PDT 24
Peak memory 183048 kb
Host smart-62e905af-0c2b-4545-ae4e-9a711b8fc45a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769717026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1769717026
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.4127834855
Short name T395
Test name
Test status
Simulation time 118857491111 ps
CPU time 189.98 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 05:46:10 PM PDT 24
Peak memory 183172 kb
Host smart-14f0f070-a26e-48e4-ab6f-ea0be4b84d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127834855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4127834855
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2202505013
Short name T433
Test name
Test status
Simulation time 1025494060 ps
CPU time 0.93 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:42:59 PM PDT 24
Peak memory 182848 kb
Host smart-25d9fc6b-be5c-4f98-a830-64a71e4d0c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202505013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2202505013
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3140439948
Short name T204
Test name
Test status
Simulation time 343337670797 ps
CPU time 591.18 seconds
Started Jun 25 05:43:05 PM PDT 24
Finished Jun 25 05:52:58 PM PDT 24
Peak memory 191360 kb
Host smart-5ecf6e37-7013-41ef-9169-afd12ad10dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140439948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3140439948
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3348948179
Short name T317
Test name
Test status
Simulation time 501690724306 ps
CPU time 444.03 seconds
Started Jun 25 05:42:54 PM PDT 24
Finished Jun 25 05:50:20 PM PDT 24
Peak memory 183124 kb
Host smart-a2dcec5a-29b3-45c5-b242-dcf180044d07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348948179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3348948179
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2222556024
Short name T375
Test name
Test status
Simulation time 113821787392 ps
CPU time 146.23 seconds
Started Jun 25 05:43:05 PM PDT 24
Finished Jun 25 05:45:32 PM PDT 24
Peak memory 183168 kb
Host smart-7c138e98-7350-424d-b15c-d326c3a749f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222556024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2222556024
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.656340518
Short name T222
Test name
Test status
Simulation time 668655458888 ps
CPU time 450.77 seconds
Started Jun 25 05:43:02 PM PDT 24
Finished Jun 25 05:50:36 PM PDT 24
Peak memory 191328 kb
Host smart-c0993908-9545-4b57-ae32-59a8f46d6c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656340518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.656340518
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3059025496
Short name T290
Test name
Test status
Simulation time 680899716028 ps
CPU time 531.69 seconds
Started Jun 25 05:42:54 PM PDT 24
Finished Jun 25 05:51:48 PM PDT 24
Peak memory 191332 kb
Host smart-b47cb90b-df34-4f93-b0a6-f7d49d2ce635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059025496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3059025496
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3998461057
Short name T320
Test name
Test status
Simulation time 1715062622004 ps
CPU time 975.09 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:59:17 PM PDT 24
Peak memory 183048 kb
Host smart-989818e4-e85d-415b-baa2-7d0aa0967729
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998461057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3998461057
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1056582280
Short name T68
Test name
Test status
Simulation time 71860544046 ps
CPU time 63.18 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:44:05 PM PDT 24
Peak memory 183068 kb
Host smart-8e75c4d9-8dde-435e-a8e1-eb18916d4f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056582280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1056582280
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2261566681
Short name T194
Test name
Test status
Simulation time 59888412905 ps
CPU time 91.48 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:44:34 PM PDT 24
Peak memory 191364 kb
Host smart-09ff3e5e-6f71-4a48-8233-7f35facabcfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261566681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2261566681
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.4188546111
Short name T83
Test name
Test status
Simulation time 58124263353 ps
CPU time 28.71 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:43:22 PM PDT 24
Peak memory 194320 kb
Host smart-3b87e651-0ab3-4a98-8c56-70b05f0e6252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188546111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4188546111
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1224199790
Short name T199
Test name
Test status
Simulation time 2002199504098 ps
CPU time 793.4 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:56:16 PM PDT 24
Peak memory 183144 kb
Host smart-33f8574c-08e9-419e-95b9-fd4791cc0a07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224199790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1224199790
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_random.1558784599
Short name T358
Test name
Test status
Simulation time 152905503614 ps
CPU time 224.42 seconds
Started Jun 25 05:42:52 PM PDT 24
Finished Jun 25 05:46:38 PM PDT 24
Peak memory 194852 kb
Host smart-920b021c-d615-406c-b4ae-857a035f8fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558784599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1558784599
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3859007917
Short name T298
Test name
Test status
Simulation time 109688282207 ps
CPU time 375.96 seconds
Started Jun 25 05:42:53 PM PDT 24
Finished Jun 25 05:49:10 PM PDT 24
Peak memory 191356 kb
Host smart-644c294d-aa2d-449c-acab-840750b84548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859007917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3859007917
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1402309014
Short name T252
Test name
Test status
Simulation time 971974844133 ps
CPU time 503.84 seconds
Started Jun 25 05:42:27 PM PDT 24
Finished Jun 25 05:50:51 PM PDT 24
Peak memory 183124 kb
Host smart-3cd8a060-2b2a-4f78-b6b2-6d14ee057e6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402309014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1402309014
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4027506703
Short name T414
Test name
Test status
Simulation time 810559350299 ps
CPU time 288.39 seconds
Started Jun 25 05:42:18 PM PDT 24
Finished Jun 25 05:47:08 PM PDT 24
Peak memory 183144 kb
Host smart-2d7fad8a-fcda-4fdc-b55c-057918b05230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027506703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4027506703
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.123756809
Short name T325
Test name
Test status
Simulation time 102773783370 ps
CPU time 60.96 seconds
Started Jun 25 05:42:18 PM PDT 24
Finished Jun 25 05:43:20 PM PDT 24
Peak memory 191376 kb
Host smart-e61d91f3-bd3b-4c9e-ad46-72b0bc591f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123756809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.123756809
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.536381759
Short name T211
Test name
Test status
Simulation time 585150130543 ps
CPU time 343.91 seconds
Started Jun 25 05:42:16 PM PDT 24
Finished Jun 25 05:48:00 PM PDT 24
Peak memory 191320 kb
Host smart-e05e5aae-5303-45d1-8cf1-2286fc098dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536381759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.536381759
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.463541309
Short name T14
Test name
Test status
Simulation time 67041113549 ps
CPU time 419.65 seconds
Started Jun 25 05:42:16 PM PDT 24
Finished Jun 25 05:49:17 PM PDT 24
Peak memory 197864 kb
Host smart-aea21341-9393-4946-afd1-b3606c19a0d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463541309 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.463541309
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3011080141
Short name T331
Test name
Test status
Simulation time 55409255974 ps
CPU time 58.85 seconds
Started Jun 25 05:42:56 PM PDT 24
Finished Jun 25 05:43:58 PM PDT 24
Peak memory 183148 kb
Host smart-d4906365-3e27-4bc3-afe2-af4ad6a550c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011080141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3011080141
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1340076623
Short name T261
Test name
Test status
Simulation time 79505048170 ps
CPU time 209.92 seconds
Started Jun 25 05:42:53 PM PDT 24
Finished Jun 25 05:46:24 PM PDT 24
Peak memory 191344 kb
Host smart-eefc9949-fbbe-49bf-86f8-55f71168b44c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340076623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1340076623
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2560258132
Short name T280
Test name
Test status
Simulation time 39189687366 ps
CPU time 454.86 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:50:38 PM PDT 24
Peak memory 183164 kb
Host smart-74dc92e1-1ec7-4661-87c3-12ab6049fb9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560258132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2560258132
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.810634874
Short name T128
Test name
Test status
Simulation time 83441013046 ps
CPU time 1792.79 seconds
Started Jun 25 05:43:04 PM PDT 24
Finished Jun 25 06:12:59 PM PDT 24
Peak memory 191272 kb
Host smart-324320a9-ed17-4044-9351-b0687ae61ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810634874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.810634874
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1968068904
Short name T207
Test name
Test status
Simulation time 195637856891 ps
CPU time 118.06 seconds
Started Jun 25 05:43:03 PM PDT 24
Finished Jun 25 05:45:03 PM PDT 24
Peak memory 191068 kb
Host smart-1ce88865-902d-4695-b624-798d5997b498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968068904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1968068904
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.997819962
Short name T309
Test name
Test status
Simulation time 86519799514 ps
CPU time 143.28 seconds
Started Jun 25 05:43:00 PM PDT 24
Finished Jun 25 05:45:27 PM PDT 24
Peak memory 191332 kb
Host smart-85182919-8158-4bfd-89fb-fc1f4fe4be42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997819962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.997819962
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.229921145
Short name T451
Test name
Test status
Simulation time 55194179803 ps
CPU time 92.6 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:44:34 PM PDT 24
Peak memory 191336 kb
Host smart-631e661e-e87a-4bc3-96df-acf8af79d25d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229921145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.229921145
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.89430946
Short name T77
Test name
Test status
Simulation time 418874382966 ps
CPU time 305.37 seconds
Started Jun 25 05:42:57 PM PDT 24
Finished Jun 25 05:48:05 PM PDT 24
Peak memory 191336 kb
Host smart-5490dc86-49a8-4115-a770-6748dce26b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89430946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.89430946
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1439017060
Short name T160
Test name
Test status
Simulation time 48273025468 ps
CPU time 412.96 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:49:55 PM PDT 24
Peak memory 183152 kb
Host smart-c9328f50-d580-4dc3-9477-f9f837b1460b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439017060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1439017060
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1152450281
Short name T348
Test name
Test status
Simulation time 638966568610 ps
CPU time 1109.36 seconds
Started Jun 25 05:42:19 PM PDT 24
Finished Jun 25 06:00:50 PM PDT 24
Peak memory 183152 kb
Host smart-1fb3a3df-0ea9-41d4-b4a9-4f2dcc61c750
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152450281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1152450281
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.120154660
Short name T393
Test name
Test status
Simulation time 468587429345 ps
CPU time 117.32 seconds
Started Jun 25 05:42:15 PM PDT 24
Finished Jun 25 05:44:13 PM PDT 24
Peak memory 183080 kb
Host smart-d642a182-5fd3-4cbf-b7ac-1154d54391fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120154660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.120154660
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2463802288
Short name T268
Test name
Test status
Simulation time 129267041247 ps
CPU time 370.42 seconds
Started Jun 25 05:42:18 PM PDT 24
Finished Jun 25 05:48:30 PM PDT 24
Peak memory 191352 kb
Host smart-ee2197b8-6386-4a1a-97b0-02683f612f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463802288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2463802288
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4123088195
Short name T340
Test name
Test status
Simulation time 50866181489 ps
CPU time 81.09 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:43:39 PM PDT 24
Peak memory 183156 kb
Host smart-f1c3f8ae-7d87-4746-ae35-bd26ab1534ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123088195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4123088195
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3148384234
Short name T409
Test name
Test status
Simulation time 101227026114 ps
CPU time 70.8 seconds
Started Jun 25 05:42:16 PM PDT 24
Finished Jun 25 05:43:28 PM PDT 24
Peak memory 183144 kb
Host smart-d037fac1-ba74-472c-abac-eddd05b8a817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148384234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3148384234
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/62.rv_timer_random.2178813469
Short name T81
Test name
Test status
Simulation time 765398886174 ps
CPU time 423.24 seconds
Started Jun 25 05:43:03 PM PDT 24
Finished Jun 25 05:50:09 PM PDT 24
Peak memory 191336 kb
Host smart-2c730313-bf8d-4cf6-bf99-7ba48f1d3507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178813469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2178813469
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.279018263
Short name T258
Test name
Test status
Simulation time 8348008376 ps
CPU time 6.8 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:43:09 PM PDT 24
Peak memory 183064 kb
Host smart-f4b7e8a6-908a-4bd2-a549-bd9a86ac2f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279018263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.279018263
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1049040070
Short name T430
Test name
Test status
Simulation time 21565714433 ps
CPU time 31.71 seconds
Started Jun 25 05:43:03 PM PDT 24
Finished Jun 25 05:43:37 PM PDT 24
Peak memory 182852 kb
Host smart-0cf83665-f52b-47d5-b000-bcb53c8810e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049040070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1049040070
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.340963655
Short name T158
Test name
Test status
Simulation time 32836938003 ps
CPU time 26.43 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:43:28 PM PDT 24
Peak memory 191352 kb
Host smart-f5fe3739-0645-4359-a212-7c1a901810b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340963655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.340963655
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.563173756
Short name T303
Test name
Test status
Simulation time 194644421058 ps
CPU time 806.55 seconds
Started Jun 25 05:43:04 PM PDT 24
Finished Jun 25 05:56:32 PM PDT 24
Peak memory 191336 kb
Host smart-43c115b6-485b-4e99-8ae6-9a586969e155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563173756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.563173756
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1739615800
Short name T459
Test name
Test status
Simulation time 119455974788 ps
CPU time 172.56 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:45:56 PM PDT 24
Peak memory 191332 kb
Host smart-2faf49bb-2353-4e0b-9b5c-e49d2a9f8c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739615800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1739615800
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2082175173
Short name T307
Test name
Test status
Simulation time 146034737565 ps
CPU time 252.61 seconds
Started Jun 25 05:43:01 PM PDT 24
Finished Jun 25 05:47:17 PM PDT 24
Peak memory 191336 kb
Host smart-97d4e493-1ab8-4e5d-b679-5f4ff83b3f27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082175173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2082175173
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1524300115
Short name T217
Test name
Test status
Simulation time 140083534379 ps
CPU time 309.87 seconds
Started Jun 25 05:43:00 PM PDT 24
Finished Jun 25 05:48:14 PM PDT 24
Peak memory 191332 kb
Host smart-8bed2097-4762-4f5a-802f-7c683fb69ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524300115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1524300115
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1493783708
Short name T413
Test name
Test status
Simulation time 524695370166 ps
CPU time 422.97 seconds
Started Jun 25 05:42:30 PM PDT 24
Finished Jun 25 05:49:33 PM PDT 24
Peak memory 183076 kb
Host smart-604fd5f0-093a-4c2a-9aec-0438f6f7646e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493783708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1493783708
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3883062058
Short name T369
Test name
Test status
Simulation time 467542324009 ps
CPU time 179.02 seconds
Started Jun 25 05:42:18 PM PDT 24
Finished Jun 25 05:45:18 PM PDT 24
Peak memory 183172 kb
Host smart-cec63ef0-532e-404b-99d2-4f534fd743c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883062058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3883062058
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3946236899
Short name T3
Test name
Test status
Simulation time 118635499143 ps
CPU time 115.54 seconds
Started Jun 25 05:42:27 PM PDT 24
Finished Jun 25 05:44:23 PM PDT 24
Peak memory 191308 kb
Host smart-1a2dd375-08bf-4d2f-b62d-42bb1972bcab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946236899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3946236899
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3741476033
Short name T335
Test name
Test status
Simulation time 35841834174 ps
CPU time 38.3 seconds
Started Jun 25 05:42:23 PM PDT 24
Finished Jun 25 05:43:02 PM PDT 24
Peak memory 183144 kb
Host smart-45a3cd54-f99a-4e60-834a-84251b958812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741476033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3741476033
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1401167726
Short name T41
Test name
Test status
Simulation time 21140529997 ps
CPU time 102.38 seconds
Started Jun 25 05:42:18 PM PDT 24
Finished Jun 25 05:44:01 PM PDT 24
Peak memory 197868 kb
Host smart-842ee3b6-f920-40c4-ae89-912edb92c282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401167726 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1401167726
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.2495449442
Short name T420
Test name
Test status
Simulation time 52461792276 ps
CPU time 46.07 seconds
Started Jun 25 05:43:08 PM PDT 24
Finished Jun 25 05:43:55 PM PDT 24
Peak memory 183100 kb
Host smart-93f20295-b631-4ce2-a902-8c5cc6900ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495449442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2495449442
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2705798033
Short name T283
Test name
Test status
Simulation time 156671089721 ps
CPU time 73.5 seconds
Started Jun 25 05:43:08 PM PDT 24
Finished Jun 25 05:44:22 PM PDT 24
Peak memory 191336 kb
Host smart-5a6de118-c947-469e-b602-a59b3cb1213f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705798033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2705798033
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1261412607
Short name T318
Test name
Test status
Simulation time 74466607122 ps
CPU time 337.06 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:48:40 PM PDT 24
Peak memory 191352 kb
Host smart-4af61885-f967-4aec-a215-168f02b6a29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261412607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1261412607
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1145406924
Short name T314
Test name
Test status
Simulation time 80931948278 ps
CPU time 79.57 seconds
Started Jun 25 05:43:04 PM PDT 24
Finished Jun 25 05:44:25 PM PDT 24
Peak memory 191284 kb
Host smart-d79983e3-1f24-43cd-8a61-a4455ca07de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145406924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1145406924
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3298057368
Short name T339
Test name
Test status
Simulation time 180946543902 ps
CPU time 125.99 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:45:09 PM PDT 24
Peak memory 191352 kb
Host smart-b6d9c02d-6055-4822-acc6-ae30bd1d0b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298057368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3298057368
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3367576911
Short name T305
Test name
Test status
Simulation time 2532828862059 ps
CPU time 755.49 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:55:38 PM PDT 24
Peak memory 191352 kb
Host smart-ca97f75f-a63c-468d-b447-09cadd586717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367576911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3367576911
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3930958241
Short name T141
Test name
Test status
Simulation time 100880080220 ps
CPU time 164.67 seconds
Started Jun 25 05:43:03 PM PDT 24
Finished Jun 25 05:45:50 PM PDT 24
Peak memory 191340 kb
Host smart-ff363886-98d6-43cd-a480-8844c7befa1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930958241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3930958241
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.4164648724
Short name T334
Test name
Test status
Simulation time 480876988919 ps
CPU time 227.63 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:46:06 PM PDT 24
Peak memory 183152 kb
Host smart-637d5dae-5a6c-4df1-b5ef-1cbdad57d99b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164648724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.4164648724
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.408233905
Short name T441
Test name
Test status
Simulation time 25489505499 ps
CPU time 35.68 seconds
Started Jun 25 05:42:17 PM PDT 24
Finished Jun 25 05:42:53 PM PDT 24
Peak memory 183168 kb
Host smart-57b0b0f8-60f0-4a92-8407-12f28650b84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408233905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.408233905
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.163079602
Short name T152
Test name
Test status
Simulation time 187347200706 ps
CPU time 465.29 seconds
Started Jun 25 05:42:27 PM PDT 24
Finished Jun 25 05:50:13 PM PDT 24
Peak memory 191320 kb
Host smart-12a58f36-2fd3-4950-b95e-0258d3aff2a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163079602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.163079602
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.4252030087
Short name T355
Test name
Test status
Simulation time 180190562644 ps
CPU time 104.86 seconds
Started Jun 25 05:42:16 PM PDT 24
Finished Jun 25 05:44:01 PM PDT 24
Peak memory 194984 kb
Host smart-d5b986ef-8940-41ea-b614-08f027a9f074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252030087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.4252030087
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.2009114705
Short name T221
Test name
Test status
Simulation time 213351250109 ps
CPU time 326.12 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:48:28 PM PDT 24
Peak memory 194660 kb
Host smart-c89f5802-4344-4b9f-9b82-02437746e54f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009114705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2009114705
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1408638070
Short name T267
Test name
Test status
Simulation time 24193901620 ps
CPU time 38.93 seconds
Started Jun 25 05:43:00 PM PDT 24
Finished Jun 25 05:43:43 PM PDT 24
Peak memory 191336 kb
Host smart-84106f75-edea-4a04-8ee8-ef5c9d272eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408638070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1408638070
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3781747073
Short name T245
Test name
Test status
Simulation time 1925386840529 ps
CPU time 1008.73 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 05:59:52 PM PDT 24
Peak memory 191464 kb
Host smart-7e850ad6-e97c-45a2-bf9c-07fe958ca3b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781747073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3781747073
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2332386015
Short name T352
Test name
Test status
Simulation time 83839815334 ps
CPU time 432.48 seconds
Started Jun 25 05:42:58 PM PDT 24
Finished Jun 25 05:50:14 PM PDT 24
Peak memory 191328 kb
Host smart-303acc08-0674-40bb-9e11-bb654ec44431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332386015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2332386015
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2630891870
Short name T115
Test name
Test status
Simulation time 32662256410 ps
CPU time 1178.02 seconds
Started Jun 25 05:42:59 PM PDT 24
Finished Jun 25 06:02:41 PM PDT 24
Peak memory 183136 kb
Host smart-9624560f-fe85-4324-b4f0-4d50014130ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630891870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2630891870
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3624418172
Short name T341
Test name
Test status
Simulation time 116220171294 ps
CPU time 170.45 seconds
Started Jun 25 05:43:10 PM PDT 24
Finished Jun 25 05:46:01 PM PDT 24
Peak memory 191336 kb
Host smart-cd650abc-ae5b-431e-9311-048ef892b3ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624418172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3624418172
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2418539412
Short name T272
Test name
Test status
Simulation time 329544359083 ps
CPU time 2160.8 seconds
Started Jun 25 05:43:12 PM PDT 24
Finished Jun 25 06:19:14 PM PDT 24
Peak memory 191340 kb
Host smart-239cf6b1-d43d-452c-99dd-73d913e9ba01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418539412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2418539412
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2371592823
Short name T418
Test name
Test status
Simulation time 184909349032 ps
CPU time 262.08 seconds
Started Jun 25 05:43:10 PM PDT 24
Finished Jun 25 05:47:33 PM PDT 24
Peak memory 191340 kb
Host smart-472df5c9-fa13-4b86-818d-c85fa7e6fc07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371592823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2371592823
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.87905877
Short name T133
Test name
Test status
Simulation time 527717378572 ps
CPU time 488.62 seconds
Started Jun 25 05:42:25 PM PDT 24
Finished Jun 25 05:50:35 PM PDT 24
Peak memory 183148 kb
Host smart-9a06a456-2620-493a-8340-29b88faa1c10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87905877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
rv_timer_cfg_update_on_fly.87905877
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1615810364
Short name T387
Test name
Test status
Simulation time 381481826285 ps
CPU time 140.5 seconds
Started Jun 25 05:42:33 PM PDT 24
Finished Jun 25 05:44:54 PM PDT 24
Peak memory 183160 kb
Host smart-9a6f1353-9d31-488b-9f51-e089cbb0cdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615810364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1615810364
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1673740184
Short name T294
Test name
Test status
Simulation time 55558942129 ps
CPU time 79.69 seconds
Started Jun 25 05:42:28 PM PDT 24
Finished Jun 25 05:43:48 PM PDT 24
Peak memory 191336 kb
Host smart-a6bc7814-8178-45b9-9f53-d424b9584b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673740184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1673740184
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.800989441
Short name T148
Test name
Test status
Simulation time 16207815915 ps
CPU time 26.62 seconds
Started Jun 25 05:42:25 PM PDT 24
Finished Jun 25 05:42:53 PM PDT 24
Peak memory 183172 kb
Host smart-4ea08e0b-4399-4a39-b500-3fb924a175bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800989441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.800989441
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.652557348
Short name T427
Test name
Test status
Simulation time 270049197750 ps
CPU time 189.32 seconds
Started Jun 25 05:42:34 PM PDT 24
Finished Jun 25 05:45:44 PM PDT 24
Peak memory 191332 kb
Host smart-4845d2a8-0e7d-4bac-aa9c-6644a2d1eb94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652557348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.652557348
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1989764821
Short name T410
Test name
Test status
Simulation time 169369839087 ps
CPU time 48 seconds
Started Jun 25 05:43:13 PM PDT 24
Finished Jun 25 05:44:02 PM PDT 24
Peak memory 183136 kb
Host smart-0b7a72f3-eea0-4703-ab6f-b7a2bae82ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989764821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1989764821
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.814287499
Short name T455
Test name
Test status
Simulation time 2060664315295 ps
CPU time 422 seconds
Started Jun 25 05:43:15 PM PDT 24
Finished Jun 25 05:50:18 PM PDT 24
Peak memory 191348 kb
Host smart-31c342e2-3ad9-4d80-b3a2-c09683c51d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814287499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.814287499
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2826778540
Short name T146
Test name
Test status
Simulation time 163185035240 ps
CPU time 127.35 seconds
Started Jun 25 05:43:15 PM PDT 24
Finished Jun 25 05:45:23 PM PDT 24
Peak memory 193264 kb
Host smart-e63c8eb8-3b75-4648-999d-327993ff7a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826778540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2826778540
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2625814028
Short name T308
Test name
Test status
Simulation time 77371558531 ps
CPU time 128.37 seconds
Started Jun 25 05:43:13 PM PDT 24
Finished Jun 25 05:45:23 PM PDT 24
Peak memory 191352 kb
Host smart-1f0f44c6-2e49-4bd1-86dd-34f5eaf80a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625814028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2625814028
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3391429582
Short name T228
Test name
Test status
Simulation time 87533403477 ps
CPU time 96.31 seconds
Started Jun 25 05:43:12 PM PDT 24
Finished Jun 25 05:44:49 PM PDT 24
Peak memory 191328 kb
Host smart-e323ceee-304d-4f67-8d1a-a84ba4942565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391429582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3391429582
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2380026306
Short name T255
Test name
Test status
Simulation time 166338742290 ps
CPU time 152.85 seconds
Started Jun 25 05:43:13 PM PDT 24
Finished Jun 25 05:45:47 PM PDT 24
Peak memory 191348 kb
Host smart-d3adf18b-3148-4bfb-9b08-865305489663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380026306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2380026306
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3331386869
Short name T127
Test name
Test status
Simulation time 1062385110689 ps
CPU time 1786.49 seconds
Started Jun 25 05:43:13 PM PDT 24
Finished Jun 25 06:13:01 PM PDT 24
Peak memory 191352 kb
Host smart-7cbdd787-122e-430d-b9d3-8b7bb5260f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331386869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3331386869
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3542686483
Short name T24
Test name
Test status
Simulation time 73415530935 ps
CPU time 71.94 seconds
Started Jun 25 05:43:20 PM PDT 24
Finished Jun 25 05:44:33 PM PDT 24
Peak memory 191332 kb
Host smart-66cb32f8-8921-4b57-9d92-05fb533a9ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542686483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3542686483
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1754818235
Short name T281
Test name
Test status
Simulation time 292320888317 ps
CPU time 1375.42 seconds
Started Jun 25 05:43:20 PM PDT 24
Finished Jun 25 06:06:17 PM PDT 24
Peak memory 191092 kb
Host smart-7db291a5-48f8-40d1-8d97-0624fe7d6a5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754818235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1754818235
Directory /workspace/99.rv_timer_random/latest
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