Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
114723980 |
1 |
|
T1 |
79142 |
|
T2 |
38033 |
|
T3 |
46576 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55466973 |
1 |
|
T1 |
13910 |
|
T2 |
38033 |
|
T3 |
6 |
auto[1] |
59257007 |
1 |
|
T1 |
65232 |
|
T3 |
46570 |
|
T4 |
5873 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
114717837 |
1 |
|
T1 |
79134 |
|
T2 |
38033 |
|
T3 |
46574 |
auto[1] |
6143 |
1 |
|
T1 |
8 |
|
T3 |
2 |
|
T5 |
2 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
55463835 |
1 |
|
T1 |
13908 |
|
T2 |
38033 |
|
T3 |
6 |
all_values[0] |
auto[0] |
auto[1] |
3138 |
1 |
|
T1 |
2 |
|
T5 |
2 |
|
T6 |
2 |
all_values[0] |
auto[1] |
auto[0] |
59254002 |
1 |
|
T1 |
65226 |
|
T3 |
46568 |
|
T4 |
5873 |
all_values[0] |
auto[1] |
auto[1] |
3005 |
1 |
|
T1 |
6 |
|
T3 |
2 |
|
T6 |
10 |